Modular multilevel cascade converter and control method therefor

Abstract

To provide a modular multilevel cascade converter in which power duty in each phase can be intentionally unbalanced without causing a flow of a reverse phase current.SOLUTION: A modular multilevel cascade converter in which one phase module is formed by connecting in series, between both ends of a cell capacitor, a plurality of bridge cells each formed by bridge connecting a plurality of semiconductor switching elements, and three phases of the module are included and are connected to a three-phase AC system, comprises a control unit that calculates a zero-phase voltage on the basis of a system-side phase voltage detection signal and output power command values of the respective phases (calculator 44), superimposes the calculated zero-phase voltage on a phase voltage detection signal (adder 58), adds a phase voltage on which the zero-phase voltage has been superimposed on a phase voltage outputted as a result of current control based on a current command value by an adder 59 to obtain output voltage command values of the respective phases, and generates a gate signal of each semiconductor switching element in each bridge cell on the basis of the output voltage command value of each phase.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a technology for intentionally creating an imbalance in the power load of each phase without flowing a reverse-phase current in a modular multilevel cascade converter (hereinafter also referred to as MMCC) of single-star bridge cells (hereinafter also referred to as SSBC) connected to a three-phase AC system, in which a separate power supply, DC / DC converter, etc. are connected to the DC side of the full-bridge cells that make up the converter. [Background technology]

[0002] A typical example of the configuration of a modular multilevel cascade converter is a solid-state transformer (hereinafter sometimes referred to as SST) as described in Patent Document 1.

[0003] Figures 1 to 3 show an SST consisting of multiple cells per phase that combines an MMCC-SSBC and a bidirectional isolated DC / DC converter. Figure 1 shows the SST main circuit configuration when two DC power systems are prepared with nine MMCC-SSBC cells, Figure 2 shows an example of an SST main circuit configuration when three DC power systems are prepared with six MMCC-SSBC cells, and Figure 3 shows another example of an SST main circuit configuration when three DC power systems are prepared with six MMCC-SSBC cells (an example with different connections from Figure 2).

[0004] In Figures 1 to 3, 10 is a three-phase AC system power supply, v U ,v V ,v W is the voltage of each phase on the grid side, i U ,i V ,i W indicates the output current of the SST flowing through the reactor of each phase.

[0005] 1, the first, second, and third bridge cells 20U1, 20U2, and 20U3 on the U-phase side are connected in series to the U-phase of the system via reactors (U-phase module). The first, second, and third bridge cells 20V1, 20V2, and 20V3 on the V-phase side are connected in series to the V-phase of the system via reactors (V-phase module). The first, second, and third bridge cells 20W1, 20W2, and 20W3 on the W-phase side are connected in series to the W-phase of the system via reactors (W-phase module).

[0006] A bidirectional insulating DC / DC converter 30... is connected to the DC side of each of the bridge cells 20U1 to 20U3, 20V1 to 20V3, and 20W1 to 20W3.

[0007] The DC output terminals of the bidirectional isolated DC / DC converters 30... connected to the first, second and third bridge cells 20U1, 20U2 and 20U3 on the U-phase side and the first and second bridge cells 20V1 and 20V2 on the V-phase side are connected in parallel to each other, and a first DC power system P1 (DC voltage is V DC / 2) is configured.

[0008] The DC output terminals of the bidirectional isolated DC / DC converters 30 connected to the V-phase side third bridge cell 20U3 and the W-phase side first, second, and third bridge cells 20W1, 20W2, and 20W3 are connected in parallel to form a second DC power system P2 (DC voltage is V DC / 2) is configured.

[0009] The bridge cells 20 (20U1 to 20U3, 20V1 to 20V3, 20W1 to 20W3) are configured by connecting semiconductor switching elements S1 to S4 in a bridge configuration across a cell capacitor C, as shown in FIG.

[0010] The common connection point of the semiconductor switching elements S1 and S2 is one connection terminal, and the common connection point of the semiconductor switching elements S3 and S4 is the other connection terminal, and the first to third bridge cells on each phase side are connected in series by these one connection terminal and the other connection terminal.

[0011] As shown in FIG. 4, the bidirectional isolated DC / DC converter 30 includes a first inverter 31 in which semiconductor switching elements S11-S14 are bridge-connected across a cell capacitor C, a first inverter 32 in which semiconductor switching elements S21-S24 are bridge-connected across a DC side capacitor 34, and a high-frequency transformer 33 connected between the AC side of the first inverter 31 and the AC side of the second inverter 32.

[0012] In the example of Fig. 4, an LLC resonant converter is used as the bidirectional isolated DC / DC converter 30. A capacitor is connected in series to the high-frequency transformer 33, and resonance occurs between the leakage inductance of the transformer and a reactor connected in series separately. The first and second inverters 31, 32 on both sides of the high-frequency transformer 33 output an AC voltage of this resonant frequency.

[0013] The duty ratio of the gate signal that drives the first inverter 31 and the second inverter 32 is fixed at 50%. After a dead time is added to this gate signal, it is supplied to the gates of the semiconductor switching elements S11, S14, S21, and S24, respectively, and after a dead time is added to a signal obtained by inverting the gate signal, it is supplied to the gates of the semiconductor switching elements S12, S13, S22, and S23, respectively.

[0014] As a result, active power according to the difference in DC voltage on both sides of the high-frequency transformer 33 is transferred through the high-frequency transformer 33. Alternatively, the series capacitor in Fig. 4 may be omitted and a dual active bridge (DAB) type DC / DC converter may be adopted, and the transferred active power may be adjusted by adjusting the phase difference in the output voltages of the inverters 31, 32 on both sides of the high-frequency transformer 33. Note that the gate signal "gate" of the bridge cell 20 connected to the three-phase AC system receives a gate signal generated by an embodiment of the present invention described later.

[0015] 2, the first and second bridge cells 20U1 and 20U2 on the U-phase side are connected in series to the U-phase of the system via a reactor (U-phase module). The first and second bridge cells 20V1 and 20V2 on the V-phase side are connected in series to the V-phase of the system via a reactor (V-phase module). The first and second bridge cells 20W1 and 20W2 on the W-phase side are connected in series to the W-phase of the system via a reactor (W-phase module).

[0016] A bidirectional isolated DC / DC converter 30 is connected to the DC side of each of the bridge cells 20U1, 20U2, 20V1, 20V2, 20W1, and 20W2.

[0017] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30 connected to the first and second bridge cells 20U1, 20U2 on the U-phase side, respectively, are connected in parallel to each other, and a first DC power system P1 (DC voltage is V DC / 3) is configured.

[0018] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30 connected to the first and second bridge cells 20V1, 20V2 on the V-phase side, respectively, are connected in parallel to each other, and a second DC power system P2 (DC voltage is V DC / 3) is configured.

[0019] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30, which are connected to the W-phase first and second bridge cells 20W1, 20W2, respectively, are connected in parallel to each other, and a third DC power system P3 (DC voltage is V DC / 3) is configured.

[0020] 3, the first and second bridge cells 20U1 and 20U2 on the U-phase side are connected in series to the U-phase of the system via a reactor (U-phase module). The first and second bridge cells 20V1 and 20V2 on the V-phase side are connected in series to the V-phase of the system via a reactor (V-phase module). The first and second bridge cells 20W1 and 20W2 on the W-phase side are connected in series to the W-phase of the system via a reactor (W-phase module).

[0021] A bidirectional isolated DC / DC converter 30 is connected to the DC side of each of the bridge cells 20U1, 20U2, 20V1, 20V2, 20W1, and 20W2.

[0022] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30, which are connected to the U-phase side first bridge cell 20U1 and the V-phase side first bridge cell 20V1, respectively, are connected in parallel to form a first DC power system P1 (DC voltage is V DC / 3) is configured.

[0023] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30, which are connected to the W-phase side first bridge cell 20W1 and the U-phase side second bridge cell 20U2, are connected in parallel to each other, and a second DC power system P2 (DC voltage is V DC / 3) is configured.

[0024] The DC output terminals of the bidirectional isolated DC / DC converters 30, 30, which are connected to the V-phase side second bridge cell 20V2 and the W-phase side second bridge cell 20W2, respectively, are connected in parallel to form a third DC power system P3 (DC voltage is V DC / 3) is configured.

[0025] As shown in Figures 1 to 3, in an SST consisting of multiple cells per set that combines an MMCC-SSBC and a bidirectional isolated DC / DC converter, high-voltage AC power is converted into DC power by cascaded cells, and the DC power is then converted into high-frequency AC power, which is then isolated and rectified by a transformer, allowing it to be converted back into DC power. Power interchange from the DC side to the AC side is also possible. Since the iron core of a transformer becomes smaller as the frequency increases, an SST, even including the converter section, can be made smaller than a conventional commercial frequency transformer.

[0026] One application requiring intentional imbalance is when multiple isolated DC power systems need to be prepared with one SST, as shown in Figures 1 to 3.

[0027] Figure 1 shows an example of obtaining a high DC voltage by creating two DC power systems P1 and P2 with a total of nine cells, three per phase, and connecting them in series. However, the cells cannot be divided equally between the two DC power systems, so the lower DC power system P2 is configured with four cells, and the upper DC power system P1 is configured with five cells. If the power consumption of the two DC power systems P1 and P2 is equal, in order to maintain equal DC voltages between the upper and lower systems, it is necessary to increase the power sharing rate of the cells connected to the lower DC power system P2. To do this, the input power of the U phase must be reduced and the input power of the W phase must be increased in the MMCC-SSBC.

[0028] Figures 2 and 3 show an example of creating three DC power systems P1, P2, and P3 using a total of six cells, two per phase. In this example, the total number of cells is divisible by the number of DC power systems, but the number of cells per phase is not. For this reason, the upper DC power system P1 is connected only to the U phase in Figure 2, and is not connected to the W phase in Figure 3. In this configuration, if the loads of the DC power systems P1, P2, and P3 differ and the DC voltage balance is lost, it is necessary to compensate for the imbalance by creating a difference in the MMCC input power of each phase.

[0029] One possible solution to this problem is to adjust the number of cells per phase in the MMCC-SSBC. In Fig. 1, adding one cell per phase would allow two cells per phase to be connected to the upper and lower DC power grids. In Figs. 2 and 3, one cell per phase can also be connected to the respective DC power grids. With this configuration, the intra-phase cell capacitor voltage balance control shown in embodiment 4 of Patent Document 1 can be applied.

[0030] However, for example, commercially available IGBTs generally have a voltage rating of 600V, 1200V, or 1700V, making fine adjustments difficult. Reducing one cell per phase may require replacing with an IGBT with a higher voltage rating, which reduces the output voltage level and requires an increase in the switching frequency, resulting in an unavoidable increase in switching loss. Conversely, adding one cell is expected to reduce the switching frequency, but it is not necessarily possible to use an IGBT with a lower voltage rating, and there is a risk that the increase in the number of cells will have negative effects such as increased costs and conduction losses. As described above, the method of adjusting the number of cells may not be able to configure the MMCC-SSBC with the optimal number of cells, which may result in reduced efficiency and increased distortion.

[0031] As another measure, it is possible to create an imbalance in the power load of each phase by passing a negative-sequence current into the AC grid. However, since the negative-sequence current has adverse effects on generators connected to the grid, such as causing abnormal vibrations, increased losses, and overheating, it is desirable to suppress the flow of the current.

[0032] In this example, the DC power systems are connected in series, but they may be treated as separate systems without being connected. Power consumption in separate systems is not necessarily equal, and it may be necessary to intentionally create a larger imbalance.

[0033] Incidentally, as conventional techniques related to the present invention, those described in Patent Documents 1 to 3, for example, have been proposed. [Prior art documents] [Patent documents]

[0034] [Patent Document 1] JP 2020-14264 A [Patent Document 2] JP 2013-5694 A [Patent Document 3] Patent Publication No. 2021-19481 Summary of the Invention [Problem to be solved by the invention]

[0035] Patent document 1 discloses a technology in which, in a configuration consisting of only an MMCC-SSBC, the deviation between the average cell capacitor voltage of all devices and the average cell capacitor voltage of each phase is input, and the cell capacitor voltage of each phase is maintained evenly through feedback control.

[0036] Patent Documents 2 and 3 disclose a method for outputting a negative-phase current without causing an imbalance in the power load of each phase in a single MMCC-SSBC configuration. In both of these documents, the superposition of a zero-phase voltage is used as the means.

[0037] The objective of Patent Document 1 is to maintain the cell capacitor voltages of each phase even. However, for example, if the cell capacitor voltage of the U phase drops and the cell capacitor voltage of the V phase rises, the cell capacitor voltages are returned to equality by generating an imbalance in the power duties. By inputting the deviation between the command value of the power duty of each phase and its actual value, rather than the deviation of the average cell capacitor voltage, as the input for feedback control, it is possible to realize the intentional generation of an imbalance, which is the objective of the present invention.

[0038] However, in Patent Document 1, feedback control is used to derive the required zero-sequence voltage. When feedback control is applied, a deviation occurs in the power duty of each phase, and the zero-sequence voltage to be superimposed is adjusted according to the deviation to reduce the deviation. This causes a problem that the response is slow and it takes a long time to input and output power according to the command value. Since the power surplus or shortage during that time is compensated for by the cell capacitor, the voltage fluctuation of the cell capacitor increases. This causes problems such as increased distortion of the MMCC-SSBC current on the AC side and increased voltage duty of the cell. As a countermeasure, there is a method of increasing the feedback gain, but this has the problem that the control becomes unstable. Voltage fluctuation can also be suppressed by increasing the capacity of the cell capacitor, but this increases the cost and size accordingly. To solve this problem, it is necessary to calculate the optimal zero-sequence voltage from the operating conditions without using feedback.

[0039] In Patent Documents 2 and 3, the necessary zero-phase voltage can be obtained by feedforward, and a calculation formula for this purpose is disclosed. However, the purpose is to equalize the power burden of each phase. A method or a calculation formula for obtaining the zero-phase voltage required to intentionally cause an imbalance is not disclosed.

[0040] The present invention is to solve the above problems, and has an object to provide a modular multilevel cascade converter that can intentionally create an imbalance in the power duties of each phase without flowing a reverse-phase current. [Means for solving the problem]

[0041] In order to solve the above problem, the modular multilevel cascade converter according to claim 1 comprises: A three-phase modular multilevel cascade converter is provided with three phases of modules each of which is connected in series to a one-phase module, the one-phase module being formed by connecting a plurality of bridge cells, each of which has a plurality of semiconductor switching elements bridge-connected across both ends of a cell capacitor, and which is connected to a three-phase AC system, The present invention is characterized in that it comprises a control unit that calculates a zero-sequence voltage based on a phase voltage detection signal from the system side and an output power command value for each phase, superimposes the calculated zero-sequence voltage on the phase voltage detection signal, performs current control based on a current command value, and adds the phase voltage on which the zero-sequence voltage is superimposed to the output phase voltage to obtain an output voltage command value for each phase, and generates a gate signal for each semiconductor switching element in each bridge cell based on the output voltage command value for each phase.

[0042] The modular multilevel cascade converter according to claim 2 comprises: The control unit is Amplitude V of the positive-phase d-axis component of the system voltage 1d and the output power command value P U * ,P V * ,P W * Based on this, calculate the zero-phase voltage V 0d , V 0q A zero-phase voltage calculation unit for calculating

[0043]

number

[0044] (V 1d is the amplitude of the positive-phase d-axis component obtained by dq-transforming the system side phase voltage with a phase ωt synchronized with the system, P U * is the output power command value of U phase, P V * is the output power command value of V phase, P W * is the output power command value for W phase) The zero-phase voltage V 0d , V 0q a zero-phase voltage superimposing unit for superimposing the Positive-phase d-axis component output current command value I 1d * and the output current command value I 1q * A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; The present invention is characterized by comprising:

[0045] The modular multilevel cascade converter according to claim 3 comprises: The control unit is Amplitude V of the positive-sequence d-axis component of the system voltage 1d , the amplitude of the negative-phase d-axis component of the system voltage V 2d , the amplitude of the negative-phase q-axis component of the system voltage V 2q , the output current command value of the reactive power component I 1q * and the output power command value P U * ,P V * ,P W * Based on this, calculate equation (11), equation (12), or equation (13) to obtain the zero-phase voltage V 0d , V 0q A zero-phase voltage calculation unit for calculating a zero-phase voltage;

[0046]

number

[0047]

number

[0048]

number

[0049] (I 1q is the amplitude of the positive-phase q-axis component of the output current (output current of the reactive power component), I 1d is the amplitude of the positive-phase d-axis component of the output current, P U is the output power of U phase, P V is the output power of phase V, P W is the output power of W phase) The zero-phase voltage V0d , V 0q a zero-phase voltage superimposing unit for superimposing the Positive-phase d-axis component output current command value I 1d * , the output current command value of the reactive power component I 1q * and the negative-phase output current command value I 2d * , I 2q * A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; The present invention is characterized by comprising:

[0050] The modular multilevel cascade converter according to claim 4 comprises: The control unit is Amplitude V of the positive-sequence d-axis component of the system voltage 1d , the output current command value of the reactive power component I 1q * , negative-phase output current command value I 2d * , I 2q * and the output power command value P U * ,P V * ,P W * Based on this, calculate equation (16), equation (17), or equation (18) to obtain the zero-phase voltage V 0d , V 0q A zero-phase voltage calculation unit for calculating a zero-phase voltage;

[0051]

number

[0052]

number

[0053]

number

[0054] (I 2q is the amplitude of the negative-phase q-axis component of the output current, I 2d is the amplitude of the negative-phase d-axis component of the output current) The zero-phase voltage V 0d , V 0q a zero-phase voltage superimposing unit for superimposing the Positive-phase d-axis component output current command value I 1d * , the output current command value of the reactive power component I 1q * and the negative-phase output current command value I 2d * , I 2q * A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; The present invention is characterized by comprising:

[0055] The modular multilevel cascade converter according to claim 5 further comprises: The system includes an odd number of bridge cells on a U-phase side connected in series to a U-phase of the system, an odd number of bridge cells on a V-phase side connected in series to a V-phase of the system, and an odd number of bridge cells on a W-phase side connected in series to a W-phase of the system, A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to one of the bridge cells obtained by dividing the odd number of bridge cells on the U-phase side and the odd number of bridge cells on the V-phase side into a set number in two in parallel; a second DC power system is configured by connecting in parallel the other divided bridge cells among the odd number of bridge cells on the V-phase side and DC output side terminals of bidirectional isolated DC / DC converters connected to the odd number of bridge cells on the W-phase side, respectively; The voltage detection value V of the first DC power systemDC1 , the voltage detection value V of the second DC power system DC2 From the voltage command value V DC * / 2 to obtain the power command P 1 * , the power command P of the first DC power system 2 * The V-phase output power command P V * is arbitrarily set, and the P 1 * From 2P V * / 3 is subtracted to obtain the U-phase output power command value P U * The above P 2 * From P V * / 3 is subtracted to obtain the output power command value P W * The output power command value calculation unit calculates the output power command value.

[0056] The modular multilevel cascade converter according to claim 6 further comprises: The system includes a plurality of bridge cells on a U-phase side connected in series to a U-phase of the system, a plurality of bridge cells on a V-phase side connected in series to a V-phase of the system, and a plurality of bridge cells on a W-phase side connected in series to a W-phase of the system, A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the plurality of bridge cells on the U-phase side in parallel with each other; a second DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters, each of which is connected to the plurality of bridge cells on the V-phase side, in parallel with each other; a third DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the W-phase side bridge cells in parallel with each other; The voltage detection value V of the first DC power system DC1, the voltage detection value V of the second DC power system DC2 , the voltage detection value V of the third DC power system DC3 From the voltage command value V DC * / 3 is subtracted from each of the first, second, and third DC power system power commands P 1 * , P 2 * , P 3 * Each of the above P 1 * , P 2 * , P 3 * The output power command value P U * , P V * , P W * The present invention is characterized by comprising an output power command value calculation unit that:

[0057] The modular multilevel cascade converter according to claim 7 further comprises: the system includes U-phase side first and second bridge cells connected in series to a U-phase of the system, V-phase side first and second bridge cells connected in series to a V-phase of the system, and W-phase side first and second bridge cells connected in series to a W-phase of the system; A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the U-phase side first bridge cell and the V-phase side first bridge cell in parallel with each other; a second DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the W-phase side first bridge cell and the U-phase side second bridge cell in parallel with each other; a third DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the V-phase side second bridge cell and the W-phase side second bridge cell in parallel with each other; The voltage detection value V of the first DC power system DC1 , the voltage detection value V of the second DC power system DC2 , the voltage detection value V of the third DC power system DC3 From the voltage command value V DC * / 3 is subtracted from each of the first, second, and third DC power system power commands P 1 * , P 2 * , P 3 * Each of the above P 1 * , P 2 * , P 3 * Using Eq. (25),

[0058]

number

[0059] The output power command value P for U phase, V phase, and W phase is calculated. U * , P V * , P W * The output power command value calculation unit calculates the output power command value.

[0060] A method for controlling a modular multilevel cascade converter according to claim 8, comprising: A control method for a three-phase modular multilevel cascade converter, which includes three phases of modules each of which is connected in series to form a one-phase module, and which is connected to a three-phase AC system, comprises the steps of: The control unit includes a step of calculating a zero-sequence voltage based on a phase voltage detection signal from the system side and an output power command value for each phase, a step of superimposing the calculated zero-sequence voltage on the phase voltage detection signal, a step of performing current control based on a current command value, a step of adding the phase voltage on which the zero-sequence voltage is superimposed to the phase voltage output by performing the current control to obtain an output voltage command value for each phase, and a step of generating a gate signal for each semiconductor switching element in each bridge cell based on the obtained output voltage command value for each phase. Effect of the Invention

[0061] (1) According to the invention as set forth in claims 1 to 8, it is possible to intentionally create an imbalance in the power load of each phase without causing a negative-phase-sequence current to flow in the MMCC-SSBC.

[0062] For example, when multiple DC power systems are created in an SST using MMCC-SSBC, even if the number of cells connected to a specific DC power system differs for each phase, it is possible to output equal power to each DC power system. This eliminates the need to redesign the number of cells in the MMCC-SSBC, and helps to avoid losses and increased costs. It can also be used when there are differences in the load of the DC power systems.

[0063] The zero-phase voltage required to generate the imbalance can be calculated by feedforward using a formula. Therefore, unlike feedback, it has the effect of shortening the response time, preventing control instability, and reducing the capacity of the cell capacitor. (2) According to the invention described in claim 2, it is possible to calculate the required zero-sequence voltage when the system voltage and the MMCC-SSBC output current are both three-phase balanced and the power factor is 1. If compensation for reactive power is not required, the zero-sequence voltage can be calculated using the simplest formula, and the calculation load can be reduced. (3) According to the invention described in claim 3, if the MMCC-SSBC output current is three-phase balanced, the required zero-sequence voltage can be obtained even if the system voltage is unbalanced. The MMCC-SSBC can output reactive power, and can have functions for reactive power compensation and system voltage amplitude adjustment. In addition, although input and output of reactive power is required, an imbalance can be generated even if the total active power of the three phases of the MMCC-SSBC is zero. (4) According to the invention described in claim 4, if the system voltage is three-phase balanced, the required zero-sequence voltage can be obtained even if the MMCC-SSBC output current is unbalanced. The MMCC-SSBC can be provided with a negative-sequence power compensation function. As with the invention described in claim 3, an imbalance can be generated when the active power is zero. (5) According to the inventions recited in claims 5 to 7, when a power command value for a DC power system is given or when feedback control is performed to keep the DC voltage constant, a power command value can be given to the MMCC-SSBC, and each of the controls recited in claims 2 to 4 can be executed.

[0064] The power duty imbalance control for each phase described above makes it possible to maintain the DC voltages above and below the MMCC-SSBC (the DC voltages of each DC power system) evenly. This makes it possible to suppress overvoltage breakdown of each cell and DC load connected to this DC voltage section. [Brief description of the drawings]

[0065] [Figure 1] FIG. 2 is a circuit diagram showing an example of an SST main circuit configuration. [Diagram 2] FIG. 4 is a circuit diagram showing another example of the SST main circuit configuration. [Diagram 3] FIG. 4 is a circuit diagram showing another example of the SST main circuit configuration. [Figure 4] This is a diagram showing the main circuit configuration of the cells that make up the SST. [Diagram 5] FIG. 2 is a configuration diagram of a control block according to the first embodiment of the present invention. [Figure 6] FIG. 11 is a configuration diagram of a control block according to a second embodiment of the present invention. [Figure 7]FIG. 11 is a configuration diagram of a control block according to a third embodiment of the present invention. [Figure 8] FIG. 11 is an output power command value calculation block diagram according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiment. The embodiment is applied to the SST shown in Figs. 1 to 3, for example. EXAMPLES

[0067] 5 shows a control block on the MMCC-SSBC side of the SST in the embodiment 1. In the embodiment 1, the following signals are input.

[0068] Grid side phase voltage detection signal v U ,v V ,v W When detecting line voltage, convert it into phase voltage by calculation before inputting it. MMCC-SSBC output current i U ,i V ,i W Output power command value P for each phase U * ,P V * ,P W * The set MMCC-SSBC reactive power component output current command value I 1q * However, in Example 1, 1q * =0.

[0069] The zero-phase voltage calculation block of the first embodiment is composed of the following: 41 is a detection signal v of the system side phase voltage U ,v V ,v W This is a low-pass filter that removes switching ripple and noise from the

[0070] 42 is v after low-pass filtering U ,v V ,v W The PLL is a phase locked loop (PLL) that inputs a phase ωt and outputs a phase ωt synchronized with the system.

[0071] 43 is v after low-pass filtering U ,v V ,v W This is a dq converter that inputs ωt, performs dq conversion, and outputs values ​​on a rotating coordinate system synchronized with the grid. The q-axis component of the dq converter output, V 1q is zero in the steady state if the PLL 42 is normal.

[0072] 44 is the d-axis component V of the dq converter output 1d (Amplitude of the positive-phase d-axis component) and P U * ,P V * ,P W * The amplitude of the zero-phase voltage V is calculated based on the equation (6) described later. 0d ,V 0q This is a calculator (zero-phase voltage calculator) that outputs the following:

[0073] 45 is V 0d and cosωt, and the oscillator that outputs a sine wave, 46, is V 0q and sinωt, the oscillator that outputs a sine wave, 47 is V 0d cosωt and V 0q This is an adder that calculates the sum with sinωt.

[0074] The current control block of the first embodiment is composed of the following: 48 is the MMCC-SSBC output current i U ,i V ,i W This is a low-pass filter that removes switching ripple and noise from the

[0075] 49 is the i after low-pass filtering U ,i V ,i WThe dq converter inputs the phase ωt, performs dq conversion, and outputs the value on the rotating coordinate system synchronized with the grid. 50 is the output power command value P U * ,P V * ,P W * 51 is an adder that adds P U * +P V * +P W * A multiplier that multiplies the gain by 2 / 3, 52 is 2(P U * +P V * +P W * ) / 3 to V 1d The positive-phase d-axis component I 1d * This is a divider that calculates:

[0076] 53 and 54 are the d-axis and q-axis components of the SST output current output from the dq converter 49 and the current command value I 1d * ,I 1q * The subtractors 53 and 54 are subtractors which obtain the deviation between the input and output, and 55 and 56 are PI amplifiers which amplify the outputs of the subtractors 53 and 54, respectively.

[0077] Reference numeral 57 denotes a dq inverse converter which receives the outputs of the PI amplifiers 55 and 56 and the phase ωt and converts values ​​on the rotating coordinate system synchronized with the system into values ​​on the fixed coordinate system.

[0078] 58 is the v after low-pass filtering U ,v V ,v W The V calculated by the adder 47 of the zero-phase voltage calculation block is 0d cosωt+V 0q This is an adder that adds sinωt.

[0079] 59 is the voltage obtained by adding the zero-phase voltage in adder 58. U ,v V ,v Wand the output of the dq inverse converter 57. The output of the adder 59 becomes the output voltage command value of the MMCC-SSBC, which is converted into a gate signal through PWM processing and input to the semiconductor switching elements (S1 to S4 in FIG. 4) of each cell 20 in FIGS. 1 to 3.

[0080] Next, the operation of the control block in FIG. 5 will be described. In the first embodiment, it is assumed that the system voltage and the MMCC-SSBC output current are three-phase balanced, and the MMCC-SSBC operates with a power factor of 1. The system voltages v U ,v V ,v W is defined as equation (1).

[0081]

number

[0082] However, V 1d is the amplitude of the positive-sequence d-axis component of the system voltage, V 0d ,V 0q are the d-axis and q-axis components of the superimposed zero-sequence voltage, respectively, and ω is the fundamental wave angular frequency of the system. The amplitude V of the positive-sequence q-axis component of the system voltage 1q If the PLL 42 is operating normally, it will be zero in the steady state. Similarly, the SST output current i U ,i V ,i W is defined as equation (2).

[0083]

number

[0084] I 1d indicates the amplitude of the positive-sequence d-axis component of the MMCC-SSBC output current. From equations (1) and (2), the output power P U ,P V ,P w can be expressed by equation (3).

[0085]

number

[0086] However, P U ,P V ,P w and I 1d The following relationships (4) and (5) hold between them.

[0087]

number

[0088]

number

[0089] The zero-phase voltage V that satisfies equation (3) 0d ,V 0q can be obtained, resulting in equation (6).

[0090]

number

[0091] In the first embodiment, the necessary zero-phase voltage is calculated based on the above, and feedforward control is performed to superimpose the voltage. The output power of each phase is the command value P U * ,P V * ,P W * The amplitude of the zero-phase voltage is calculated by equation (7) in which the power in equation (6) is replaced by the command value (calculator 44).

[0092]

number

[0093] The zero-phase voltage is determined based on the obtained amplitude and is added to all three phases of the MMCC-SSBC output voltage (adder 58), so that the output power of each phase can be made to match the command value.

[0094] To apply the first embodiment, the necessary voltage amplitude is calculated. Let the rated capacity of the SST be P, and take the case where a 10% imbalance is intentionally generated between the U and W phases as an example. U * = P / 3 × 110%, P v * =P / 3, P w * Substituting =P / 3×90% into equation (7), the amplitude of the zero-phase voltage is √(V 0d 2 +V 0q 2 )=0.1155V 1d Therefore, the voltage amplitude of each phase increases by a maximum of 11.55%. However, if a larger imbalance is intentionally created, for example, P U * =0,P v * =P w * Then the amplitude of the zero-phase voltage is V 1d The output voltage amplitude of the U phase is zero, but increases by a factor of √3 in the V and W phases.

[0095] P v * =P w * = 0, the amplitude of the zero-phase voltage is 2V 1d As a result, the U-phase output voltage amplitude increases by a factor of three. Therefore, the greater the imbalance that occurs, the greater the required number of cells and the cell capacitor voltage.

[0096] In the first embodiment, the total command value P U * +P V * +P W * When is zero, the denominator of equation (7) becomes zero and the zero-sequence voltage cannot be calculated. U * +P V * +P W * It is necessary to exclude the cases where P is close to zero from the operating conditions. U * =P v* =P w * =0 then I 1d * = 0 for any V 0d ,V 0q Therefore, equation (3) holds true. U * +P V * +P W * When approaches zero, V 0d =V 0q By setting =0, imbalance cannot occur but division by zero can be avoided.

[0097] As described above, according to the first embodiment, it is possible to obtain the zero-sequence voltage required when the system voltage and the MMCC-SSBC output current are both three-phase balanced and the power factor is 1. If compensation for reactive power is not required, the zero-sequence voltage can be obtained by the simplest formula, and the calculation load can be reduced. EXAMPLES

[0098] Fig. 6 shows a control block on the MMCC-SSBC side of the SST in the embodiment 2. In Fig. 6, the same parts as in Fig. 5 are denoted by the same reference numerals. In the embodiment 2, the following input signals are added to the embodiment 1.

[0099] ·MMCC-SSBC reactive power component output current command value I 1q * However, unlike the first embodiment, values ​​other than zero are also allowed. ·MMCC-SSBC negative-phase output current command value I 2d * ,I 2q * However, in Example 2, I 2d * =I 2q * =0.

[0100] The zero-phase voltage calculation block of the second embodiment is configured by adding the following to the first embodiment: 60, 61, and 62 are multipliers that multiply the phase ωt output from the PLL 42 by −1.

[0101] 63 is the v after low-pass filtering U ,v V ,v W and phase -ωt, performs dq transformation, and outputs a value on the rotating coordinate system synchronized with the negative phase component of the system.

[0102] Filters 64 and 65 (MAVE: for example, moving average filters) remove ripples of twice the frequency of the system caused by the positive-phase component, which are superimposed on the output of the dq converter 63 that outputs the negative-phase component.

[0103] Filters 66 and 67 (MAVE: for example, moving average filters) remove ripples of twice the frequency of the system caused by the negative phase component, which are superimposed on the output of the dq converter 43 that outputs the positive phase component.

[0104] 68 is the filtered dq converter output signal V 1d , V 2d , V 2q And, I 1q * , P U * ,P v * ,P w * The amplitude of the zero-phase voltage V is calculated based on the equations (11) and (12) described later. 0d ,V 0q It is an arithmetic unit that outputs

[0105] The calculator 68 calculates the positive-phase d-axis component I 1d * may also be input and calculation may be performed based on equation (13) described later.

[0106] The current control block of the second embodiment is configured by adding the following to the first embodiment. 69 is the i U ,iV ,i W and phase -ωt, performs dq transformation, and outputs a value on the rotating coordinate system synchronized with the negative phase component of the system.

[0107] 70 and 71 are the d-axis and q-axis components of the SST output current output from the dq converter 69 and the negative-phase current command value I 2d * ,I 2q * It is a subtractor that calculates the deviation between

[0108] Reference numerals 72 and 73 denote I amplifiers which respectively amplify the outputs of the subtractors 70 and 71. Reference numeral 74 denotes a dq inverse converter which receives the outputs of the I amplifiers 72 and 73 and a phase -ωt and converts values ​​on the rotating coordinate system synchronized with the system into values ​​on the fixed coordinate system.

[0109] 75 is the voltage obtained by adding the zero-phase voltage in adder 58. U ,v V ,v W and an adder that adds the outputs of the dq inverse converter 57 and the dq inverse converter 74. The output of the adder 75 becomes the output voltage command value of the MMCC-SSBC, and is subjected to PWM processing to output a gate signal.

[0110] Next, a description will be given of the operation of the control block in Fig. 6. In the second embodiment, it is assumed that the MMCC-SSBC output current is three-phase balanced but the system voltage is unbalanced, and the MMCC-SSBC also outputs reactive power.

[0111] U-phase, V-phase, and W-phase system voltage v U ,v V ,v W is defined as equation (8).

[0112]

number

[0113] However, V 2d is the amplitude of the negative-phase d-axis component of the system voltage, V 2qis the amplitude of the negative-phase q-axis component. The amplitude of the positive-phase q-axis component of the system voltage V 1q If the PLL 42 is operating normally, it will be zero in the steady state. Similarly, the SST output current i U ,i V ,i W is defined as in equation (9).

[0114]

number

[0115] I 1q indicates the amplitude of the positive-phase q-axis component of the MMCC-SSBC output current. From equations (8) and (9), the output power P U ,P V ,P W can be expressed by equation (10).

[0116]

number

[0117] However, P U ,P V ,P W and I 1d Similar to the first embodiment, the above formulas (4) and (5) hold between these.

[0118] The zero-phase voltage V that satisfies Eq. (10) 0d ,V 0q can be obtained, resulting in equations (11) and (12).

[0119]

number

[0120]

number

[0121] In the second embodiment, the power in the equations (11) and (12) is expressed as a command value P U* ,P V * ,P W * The required zero-sequence voltage is calculated and superimposed by replacing with . Unlike the first embodiment, the zero-sequence voltage can be calculated even when the system voltage is unbalanced and reactive power is being output, so that it can be used under a wide range of operating conditions. U * +P V * +P W * 3I 1d * V 1d / 2, the equation can be transformed to (13), and the zero-sequence voltage can be calculated using (13).

[0122]

number

[0123] In the second embodiment, when the amplitude of the MMCC-SSBC output current is zero, the zero-sequence voltage cannot be obtained. However, unlike the first embodiment, U * +P V * +P W * Even if P is zero, the zero-sequence voltage can be calculated as long as reactive power is being output. U * +P V * +P W * When approaches zero, V 0d =V 0q = 0 to stop the generation of the unbalance, but the unbalance can be continued by outputting a certain amount of reactive power. However, the larger the unbalance that is generated, the more the required reactive power or zero-sequence voltage will increase.

[0124] In the second embodiment, a set of dq converter-inverter is added to the current control block (dq converter 69, subtractors 70, 71, I amplifiers 72, 73, dq inverter 74). The reason for this is to suppress the risk of an unintended unbalanced current flowing in the MMCC-SSBC output current, which is caused by assuming that the system voltage is unbalanced. By applying an integral amplifier (I amplifiers 72, 73) on the negative-phase rotating coordinate system, the feedback gain becomes infinite in the negative phase, and the deviation can be made zero. However, if the deviation of the negative-phase current can be made sufficiently small, the additional block is not necessary, or a method of applying a resonant amplifier instead of the additional block can be considered.

[0125] As described above, according to the second embodiment, if the MMCC-SSBC output current is three-phase balanced, the required zero-sequence voltage can be obtained even if the system voltage is unbalanced. The MMCC-SSBC can output reactive power, and can have functions for reactive power compensation and system voltage amplitude adjustment. In addition, although input and output of reactive power is required, an imbalance can be generated even if the total active power in the three phases of the MMCC-SSBC is zero. EXAMPLES

[0126] Fig. 7 shows a control block on the MMCC-SSBC side of the SST in the third embodiment. In Fig. 7, the same parts as in Fig. 5 and Fig. 6 are denoted by the same reference numerals. In the third embodiment, the following input signals are added to the first embodiment.

[0127] ·MMCC-SSBC reactive power component output current command value I 1q * ·MMCC-SSBC negative-phase output current command value I 2d * ,I 2q * However, unlike the first and second embodiments, all three values ​​other than zero are permitted.

[0128] The zero-phase voltage calculation block of the third embodiment is configured by adding the following to the first embodiment. 76 is the d-axis component V of the dq converter output.1d And, P U * ,P V * ,P W * , I 1q * ,I 2d * , I 2q * The amplitude of the zero-phase voltage V is calculated based on the equations (16) and (17) described later. 0d ,V 0q It is a calculator that outputs

[0129] The calculator 76 calculates the positive-phase d-axis component I 1d * may also be input and calculation may be performed based on equation (18) described later.

[0130] The current control block of the third embodiment is the same as that of the second embodiment (FIG. 6).

[0131] Next, a description will be given of the operation of the control block in Fig. 7. In the third embodiment, it is assumed that the system voltage is balanced, but the SST output current is three-phase unbalanced.

[0132] U-phase, V-phase, and W-phase system voltage v U ,v V ,v W The definition of is the same as that of formula (1) above.

number

[0133] SST output current for each phase i U ,i V ,i W is defined as equation (14).

[0134]

number

[0135] I 2d is the amplitude of the negative-phase d-axis component of the SST output current, and I2q indicates the amplitude of the negative-phase q-axis component of the SST output current. From equations (1) and (14), the output power P U ,P V ,P W can be expressed by equation (15).

[0136]

number

[0137] However, P U ,P V ,P W and I 1d As in the first and second embodiments, the formulas (4) and (5) hold between these.

[0138] The zero-phase voltage V that satisfies Eq. (15) 0d ,V 0q can be obtained, resulting in equations (16) and (17).

[0139]

number

[0140]

number

[0141] In the third embodiment, the power in the equations (16) and (17) is expressed as the command value P U * ,P V * ,P W * The necessary zero-sequence voltage is calculated and superimposed by replacing with . Unlike the first embodiment, the zero-sequence voltage can be obtained even when reactive power or negative-sequence current is output. Equations (16) and (17) are expressed as P U * +P V * +P W * I 1d *This can be transformed into equation (18), and the zero-phase voltage may be calculated using equation (18) (calculator 76).

[0142]

number

[0143] However, when the amplitudes of the positive-sequence current and the negative-sequence current are close to each other, the denominator of equation (18) approaches zero, and the amplitude of the required zero-sequence voltage increases. When the amplitudes of the positive-sequence current and the negative-sequence current are equal, the zero-sequence voltage cannot be obtained. Therefore, the amplitude of the negative-sequence current command value must be adjusted so that there is a sufficient difference from the amplitude of the positive-sequence current command value.

[0144] Up until now, embodiment 2 has dealt with connection to an unbalanced voltage system, and embodiment 3 has dealt with the output of an unbalanced current. It is possible to deal with unbalanced conditions in both voltage and current by combining these two, defining the system voltage by equation (8) in embodiment 2, and defining the SST output current by equation (14) in embodiment 3 to obtain the power of each phase. However, in this case, the sum of the power of each phase becomes equation (19), and equations (4) and (5) no longer hold.

[0145]

number

[0146] As a result, although the zero-phase voltage can be calculated using equations (20) and (21), these equations are very complicated.

[0147]

number

[0148]

number

[0149] The zero-sequence voltage may be calculated using equations (20) and (21) and superimposed on the output voltage. Alternatively, √(V2d 2 +V 2q 2 ) is compared with a preset threshold value, and √(V 2d 2 +V 2q 2 ) is smaller than the threshold value, that is, when the system voltage can be considered to be almost balanced, the output of the negative-sequence current is permitted, the zero-sequence voltage is calculated based on Example 3, and when a large imbalance occurs in the system voltage due to a system fault, etc., √(V 2d 2 +V 2q 2 ) increases, the negative-phase current command value I 2d * ,I 2q * may be temporarily set to zero to stop the output of the negative-phase current and calculate the zero-phase voltage based on the embodiment 2. Although this requires switching between the embodiments 2 and 3, it is possible to avoid complicating the equation for deriving the zero-phase voltage.

[0150] As described above, according to the third embodiment, if the system voltage is three-phase balanced, the required zero-sequence voltage can be obtained even if the MMCC-SSBC output current is unbalanced. The MMCC-SSBC can be provided with a negative-sequence power compensation function. As in the second embodiment, an imbalance can be generated when the active power is zero. EXAMPLES

[0151] FIG. 8 shows the output power command value P U * ,P V * ,P W * The calculation block (output power command value calculation unit) of Fig. 8 (a), (b), and (c) are assumed to be applied to the configurations of Fig. 1, Fig. 2, and Fig. 3, respectively.

[0152] In the calculation block of Fig. 8, the power command P 1 * ,P 2 * ,(P3 * ,…), the voltage detection value V of each DC power system DC1 ,V DC2 ,(V DC3 ,…), the voltage command value V DC * / 2 or V DC * / 3, a subtractor that calculates the deviation between the voltage detection value and the command value, and an amplifier that amplifies the output of the subtractor are used to calculate the output power command value P U * ,P V * ,P W * is calculated as follows:

[0153] First, in FIG. 8(a) applied to the configuration of FIG. 1, the voltage detection value V DC1 , the voltage detection value V of the second DC power system P2 DC2 From the voltage command value V DC * / 2 are subtracted by subtractors 81 and 82, respectively, and the subtracted results are amplified by PI amplifiers 83 and 84 to obtain the power command P 1 * , the power command P of the first DC power system 2 * Request.

[0154] And the V-phase output power command P V * is set arbitrarily, and the P 1 * Then, multiplier 85 outputs P V * 2P multiplied by 2 / 3 V * / 3 is subtracted by subtractor 86 to obtain the U-phase output power command value P U * The above P 2 * Then, multiplier 87 outputs P V * P multiplied by 1 / 3 V * / 3 is subtracted by subtractor 88 to obtain the W-phase output power command value P W* Request.

[0155] The power relationships in Figures 1 and 8(a) are explained below. Assuming that the power per phase of the MMCC-SSBC is shared equally among all cells connected to that phase, the following relationships hold between the DC power systems P1 and P2 and the power of each phase of the MMCC-SSBC.

[0156]

number

[0157] However, since the AC side has a high degree of freedom, P U * ,P V * ,P W * In this example, the power command value P V * If you decide freely, P U * ,P W * By solving the above equation (22),

[0158]

number

[0159] In Fig. 8(a), the power command P 1 * ,P 2 * From P U * ,P W * P 1 * ,P 2 * Here, an example is shown in which feedback control is configured to keep the voltage constant. Any other power command given from the outside can be used as is, or the power consumed in the DC power system can be detected.

[0160] P can be freely decided v * An example of how to set the value is explained below. For example, v * =(P 1 * +P 3 * ) / 3 to get P v * =(P U * +P W * ) / 2 holds, the generated power unbalance is reduced, and the required amplitude of the zero-phase voltage can be reduced to a certain extent. In order to minimize the amplitude of the zero-phase voltage under the same operating conditions as in the first embodiment, the equation (23) can be substituted into the equation (7) to obtain

[0161]

number

[0162] This P v * Differentiating with

[0163]

number

[0164] Therefore, P v * =(6P 1 * +3P 2 * ) / 14.

[0165] P v * The results of calculations of how the required zero-phase voltage amplitude changes depending on the

[0166] Here, we consider the case where the power is equally shared between two DC systems. 1 * =P 2 *= P / 2. As in the first embodiment, both the system voltage and the MMCC-SSBC output current are three-phase balanced, and the MMCC-SSBC operates with a power factor of 1. v * is set to four types as shown in Table 1.

[0167] [Table 1]

[0168] From this result, P v * =(6P 1 * +3P 2 * It can be seen that the amplitude of the zero-sequence voltage to be superimposed can be minimized by setting the operating conditions as follows:

[0169] In FIG. 8(b) applied to the configuration of FIG. 2, the voltage detection value of the first DC power system P1, V DC1 , the voltage detection value V of the second DC power system P2 DC2 , the voltage detection value V of the third DC power system P3 DC3 Then, the voltage command value of each DC power system is V DC * / 3 is subtracted by subtractors 89, 90, and 91, respectively, and the subtracted outputs are amplified by PI amplifiers 92, 93, and 94 to generate power commands P 1 * ,P 2 * ,P 3 * Then, calculate P 1 * ,P 2 * ,P 3 * The output power command value P U * ,P V * ,P W * Let us assume that.

[0170] That is, in FIG. 8(b), all two cells of the DC power system P1 in FIG. 2 are connected to the U phase, so P U * =P 1 * ,P V * =P 2 * ,P W * =P 3 * It is.

[0171] In Figure 2, there is no room for freedom, so P U * ,P V * ,P W * is uniquely determined, and the relationship in equation (24) holds.

[0172]

number

[0173] In FIG. 8(c) which is applied to the configuration of FIG. 3, the voltage detection value of the first DC power system P1, V DC1 , the voltage detection value V of the second DC power system P2 DC2 , the voltage detection value V of the third DC power system P3 DC3 Then, the voltage command value of each DC power system is V DC * / 3 is subtracted by subtractors 89, 90, and 91, respectively, and the subtracted outputs are amplified by PI amplifiers 92, 93, and 94 to generate power commands P 1 * ,P 2 * ,P 3 * Each person is asked to: And P 1 * ,P 2 * ,P 3 * are added by adder 95, and P 1 * ,P2 * ,P 3 * are multiplied by two by multipliers 96, and the outputs of the three multipliers 96 are subtracted from the sum of the adder 95 by subtractors 97, 98, and 99, respectively, to obtain output power command values ​​P U * ,P V * ,P W * Request.

[0174] In Figure 3, there is no room for freedom, so P U * ,P V * ,P W * is uniquely determined, and P U * ,P V * ,P W * is being sought.

[0175]

number

[0176] In the configurations of Figs. 2 and 3, 1 * = 1 / 3 × 110%, P 2 * =1 / 3, P 3 * If we calculate the required zero-phase voltage amplitude based on equation (7) under the condition of = 1 / 3 × 90%, in the configuration of Figure 2, we get √(V 0d 2 +V 0q 2 )=0.1155V 1d , 0.2309V in Figure 3 1d It becomes.

[0177] As a result, the configuration of FIG. 2 has the advantage that it is easier to generate an imbalance and the amplitude of the required zero-phase voltage can be suppressed. On the other hand, the configuration of FIG. 2 has the problem that it is more susceptible to the effects of system accidents and the like. For example, when the U phase has a ground fault, only the DC power system P1 is affected in FIG. 2, but in FIG. 3, the effect is distributed to the DC power systems P1 and P2. This effect continues until the superposition of the zero-phase voltage according to the second embodiment is completed, that is, for the delay time of the filter MAVE (filters 64 to 67), which is a very short time compared to the conventional feedback control, but during that time, the power cannot be converted according to the command value. Therefore, in FIG. 2, it is necessary to mount a large-capacity capacitor to suppress this effect, but conversely, in FIG. 3, a reduction in the capacitor capacity can be expected.

[0178] As described above, according to the fourth embodiment, when a power command value for a DC power system is given or when feedback control is performed to keep the DC voltage constant, a power command value can be given to the MMCC-SSBC and the first to third embodiments can be applied.

[0179] The power duty imbalance control for each phase described above makes it possible to maintain the DC voltages above and below the MMCC-SSBC (the DC voltages of each DC power system) evenly. This makes it possible to suppress overvoltage breakdown of each cell and DC load connected to this DC voltage section. [Explanation of symbols]

[0180] 10…System power supply 20…Bridge cell 30...Bidirectional isolated DC / DC converter 31,32...Inverter 33...High frequency transformer 34…DC side capacitor 41,48…Low pass filter 42…PLL 43,49,63,69…dq converter 44,68,76...Arithmetic unit 45,46…Oscillator 47,50,58,59,75,95…Adder 51,60,61,62,85,87,96…Multiplier 52...Divider 53,54,70,71,81,82,86,88,89,90,91,97,98,99…Subtractor 55,56,83,84,92,93,94…PI amplifiers 57,74…dq inverter 64~67…Filter 72,73…I Amplifier

Claims

1. A three-phase modular multilevel cascade converter includes three modules each of which is connected in series to form a one-phase module, the three modules being connected to a three-phase AC system, the three-phase modular multilevel cascade converter comprising: a plurality of bridge cells each of which is connected in series to a cell capacitor and each of which has a plurality of semiconductor switching elements bridge-connected across the two ends of the cell capacitor; a control unit that calculates a zero-sequence voltage based on a phase voltage detection signal on a system side and an output power command value for each phase, superimposes the calculated zero-sequence voltage on a phase voltage detection signal, performs current control based on a current command value, and adds the phase voltage on which the zero-sequence voltage is superimposed to an output phase voltage, thereby obtaining an output voltage command value for each phase, and generates a gate signal for each semiconductor switching element in each of the bridge cells based on the output voltage command value for each phase.

2. The control unit is Amplitude V of the positive-phase d-axis component of the system voltage １ｄ and the output power command value P Ｕ ＊ , P Ｖ ＊ , P Ｗ ＊ Based on this, the zero-phase voltage V ０ｄ , V ０ｑ A zero-phase voltage calculation unit for calculating a zero-phase voltage; [0070] (V １ｄ is the amplitude of the positive-phase d-axis component obtained by dq-transforming the system side phase voltage with a phase ωt synchronized with the system, P Ｕ ＊ is the output power command value of U phase, P Ｖ ＊ is the output power command value of the V phase, P Ｗ ＊ is the output power command value for W phase) The zero-phase voltage V ０ｄ , V ０ｑ a zero-phase voltage superimposing unit for superimposing the Positive phase d-axis component output current command value I １ｄ ＊ and the output current command value I １ｑ ＊ A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; 2. The modular multilevel cascade converter according to claim 1, comprising:

3. The control unit is Amplitude V of the positive-phase d-axis component of the system voltage １ｄ , the amplitude of the negative-phase d-axis component of the system voltage V ２ｄ , the amplitude V of the negative-phase q-axis component of the system voltage ２ｑ , the output current command value I １ｑ ＊ and the output power command value P Ｕ ＊ , P Ｖ ＊ , P Ｗ ＊ Based on this, the zero-phase voltage V ０ｄ , V ０ｑ A zero-phase voltage calculation unit for calculating a zero-phase voltage; ##EQU00011## ##EQU00012## ##EQU00013## (I １ｑ is the amplitude of the positive-phase q-axis component of the output current (output current of the reactive power component), I １ｄ is the amplitude of the positive phase d-axis component of the output current, P Ｕ is the output power of U phase, P Ｖ is the output power of V phase, P Ｗ is the output power of W phase) The zero-phase voltage V ０ｄ , V ０ｑ a zero-phase voltage superimposing unit for superimposing the Positive phase d-axis component output current command value I １ｄ ＊ , the output current command value I １ｑ ＊ and the negative phase output current command value I ２ｄ ＊ , I ２q ＊ A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; 2. The modular multilevel cascade converter according to claim 1, comprising:

4. The control unit is Amplitude V of the positive-phase d-axis component of the system voltage １ｄ , the output current command value I １ｑ ＊ , negative phase output current command value I ２ｄ ＊ , I ２q ＊ and the output power command value P Ｕ ＊ , P Ｖ ＊ , P Ｗ ＊ Based on this, the zero-phase voltage V ０ｄ , V ０ｑ A zero-phase voltage calculation unit for calculating a zero-phase voltage; ##EQU00016## ##EQU00017## [0018] (I ２ｑ is the amplitude of the negative phase q-axis component of the output current, I ２ｄ is the amplitude of the negative phase d-axis component of the output current) The zero-phase voltage V ０ｄ , V ０ｑ a zero-phase voltage superimposing unit for superimposing the Positive phase d-axis component output current command value I １ｄ ＊ , the output current command value I １ｑ ＊ and the negative phase output current command value I ２ｄ ＊ , I ２q ＊ A current control unit that performs current control based on the an adder unit that calculates an output voltage command value for each phase by adding an output voltage of the zero-phase voltage superimposing unit to a phase voltage output from the current control unit; 2. The modular multilevel cascade converter according to claim 1, comprising:

5. The system includes an odd number of bridge cells on a U-phase side connected in series to a U-phase of the system, an odd number of bridge cells on a V-phase side connected in series to a V-phase of the system, and an odd number of bridge cells on a W-phase side connected in series to a W-phase of the system, A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to one of the bridge cells obtained by dividing the odd number of bridge cells on the U-phase side and the odd number of bridge cells on the V-phase side into a set number in two in parallel; a second DC power system is configured by connecting in parallel the other divided bridge cells among the odd number of bridge cells on the V-phase side and DC output side terminals of bidirectional isolated DC / DC converters connected to the odd number of bridge cells on the W-phase side, respectively; The voltage detection value V of the first DC power system ＤＣ１ , the voltage detection value V of the second DC power system ＤＣ２ From the voltage command value V ＤＣ ＊ / 2 to obtain the power command P １ ＊ , the power command P ２ ＊ The V-phase output power command P Ｖ ＊ is arbitrarily set, and the P １ ＊ From 2P Ｖ ＊ / 3 is subtracted to obtain the U-phase output power command value P Ｕ ＊ and ２ ＊ From P Ｖ ＊ / 3 is subtracted to obtain the W-phase output power command value P Ｗ ＊ 5. The modular multilevel cascade converter according to claim 2, further comprising an output power command value calculation unit for calculating an output power command value.

6. The system includes a plurality of bridge cells on a U-phase side connected in series to a U-phase of the system, a plurality of bridge cells on a V-phase side connected in series to a V-phase of the system, and a plurality of bridge cells on a W-phase side connected in series to a W-phase of the system, A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the plurality of bridge cells on the U-phase side in parallel with each other; a second DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the plurality of bridge cells on the V-phase side in parallel with each other; a third DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the W-phase side bridge cells in parallel with each other; The voltage detection value V of the first DC power system ＤＣ１ , the voltage detection value V of the second DC power system ＤＣ２ , the voltage detection value V of the third DC power system ＤＣ３ From the voltage command value V ＤＣ ＊ / 3 is subtracted from each of the first, second, and third DC power systems to obtain the power command P １ ＊ , P ２ ＊ , P ３ ＊ and １ ＊ , P ２ ＊ , P ３ ＊ The output power command value P Ｕ ＊ , P Ｖ ＊ , P Ｗ ＊ 5. The modular multilevel cascade converter according to claim 2, further comprising an output power command value calculation unit which calculates an output power command value based on the above-mentioned formula:

7. the power supply system includes first and second bridge cells on a U-phase side connected in series to a U-phase of the power supply system, first and second bridge cells on a V-phase side connected in series to a V-phase of the power supply system, and first and second bridge cells on a W-phase side connected in series to a W-phase of the power supply system; A bidirectional isolated DC / DC converter is connected to the DC side of each of the bridge cells, a first DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the U-phase side first bridge cell and the V-phase side first bridge cell in parallel with each other; a second DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the W-phase side first bridge cell and the U-phase side second bridge cell in parallel with each other; a third DC power system is configured by connecting DC output side terminals of bidirectional isolated DC / DC converters connected to the V-phase side second bridge cell and the W-phase side second bridge cell in parallel with each other; The voltage detection value V of the first DC power system ＤＣ１ , the voltage detection value V of the second DC power system ＤＣ２ , the voltage detection value V of the third DC power system ＤＣ３ From the voltage command value V ＤＣ ＊ / 3 is subtracted from each of the first, second, and third DC power systems to obtain the power command P １ ＊ , P ２ ＊ , P ３ ＊ and １ ＊ , P ２ ＊ , P ３ ＊ Using equation (25), [0025] The output power command value P Ｕ ＊ , P Ｖ ＊ , P Ｗ ＊ 5. The modular multilevel cascade converter according to claim 2, further comprising an output power command value calculation unit for calculating an output power command value.

8. A control method for a three-phase modular multilevel cascade converter, which includes three phases of modules each of which is connected in series to form a one-phase module, and which is connected to a three-phase AC system, comprises the steps of: a control unit for calculating a zero-phase-sequence voltage based on a phase voltage detection signal from a system side and an output power command value for each phase, a step of superimposing the calculated zero-phase-sequence voltage on a phase voltage detection signal, a step of performing current control based on a current command value, a step of adding the phase voltage on which the zero-phase-sequence voltage is superimposed to the phase voltage output by performing the current control to obtain an output voltage command value for each phase, and a step of generating a gate signal for each semiconductor switching element in each bridge cell based on the obtained output voltage command value for each phase.

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