Input / output signal retaining device and input / output signal retaining device system

Abstract

To provide an input / output signal retaining device which can retain a logical value of an input / output signal even when a power supply potential drops.SOLUTION: An input / output signal retaining device includes: a detection part which detects a power supply potential of a first device being a predetermined potential or lower; and a retaining part which stores an input / output signal which is output from the first device and input into a second device and retains the logical value of the input / output signal at the stored logical value based on detection of the detection part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an input / output signal holding device and an input / output signal holding device system. [Background technology]

[0002] 2. Description of the Related Art Conventionally, devices that have a function for stopping operation when an abnormality is detected are known.

[0003] In this regard, Patent Document 1 discloses a control device that, when an impact applied to the operation unit is detected, blocks an input / output signal transmitted from the operation unit to the control device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-288105 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the technique described in Patent Document 1 has a problem in that the input / output signals are blocked even when it is better to maintain the logic values ​​of the input / output signals when an abnormality such as a shock or a drop in power supply potential occurs.

[0006] The present invention has been made in consideration of these problems, and its object is to provide an input / output signal holding device and an input / output signal holding device system that can hold the logical value of an input / output signal even when the power supply potential drops. [Means for solving the problem]

[0007] In order to solve the above problem, the input / output signal holding device of the present invention comprises a detection unit that detects that the power supply potential of a first device is below a predetermined potential, and a holding unit that stores the logical value of an input / output signal output from the first device and input to a second device, and holds the logical value of the input / output signal to the stored logic based on detection by the detection unit.

[0008] Also, the second device is a robot or a tool connected to the robot, The first device is a control device for controlling the operation of the second device.

[0009] The holding unit also has a capacitive element having one end to which charge is supplied from an input / output signal line that transmits the input / output signal, and a latch circuit to which a potential of a detection signal indicating a detection result of the detection unit is supplied as a power source, and which supplies the potential of the detection signal to the input / output signal line based on the potential of the one end of the capacitive element.

[0010] Moreover, the detection unit is operated by a power source different from a power source of the first device and the second device.

[0011] The holding section is provided for each of a plurality of input / output signals.

[0012] In addition, the input / output signal holding device system of the present invention includes a robot to which a tool is connected, a control device for controlling the operation of the robot or the tool, an input / output signal holding device having a detection unit that detects whether a power supply potential of the control device is below a predetermined potential, and a holding unit that stores the logical values ​​of input / output signals output from the control device and input to the tool, and holds the logical values ​​of the input / output signals at the stored logical values ​​based on detection by the detection unit. Effect of the Invention

[0013] According to the present invention, the input / output signal holding device and the input / output signal holding device system can hold the logical value of the input / output signal even when the power supply potential drops. [Brief description of the drawings]

[0014] [Figure 1] 1 is a block diagram showing an overall configuration of an input / output signal holding device system according to a first embodiment; [Diagram 2] 2 is a diagram showing details of a circuit configuration of the input / output signal holding device system shown in FIG. 1. [Diagram 3] FIG. 11 is a block diagram showing the overall configuration of an input / output signal holding device system according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention (hereinafter, referred to as a "first embodiment" or a "second embodiment") will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components and steps in each drawing are denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0016] ---First embodiment--- First, the first embodiment will be described.

[0017] <Overall composition> 1 is a block diagram showing the overall configuration of an input / output signal holding device system 1A according to a first embodiment. As shown in FIG. 1, the main part of the input / output signal holding device system 1A includes, for example, a device 10A, a device 20A, an input / output signal holding device 30A, and an auxiliary power supply 40.

[0018] The device 10A is, for example, a control device for the device 20A. The device 10A operates with a power supply potential VDD supplied from a main power supply device (not shown) and controls the operation of the device 20A by transmitting an input / output signal IOS including a control command to the device 20A via an input / output signal line W_IOS. The device 10A also outputs the input / output signal IOS to the device 20A as well as to the input / output signal holding device 30A. A reference potential GND is supplied to the device 10A as a ground potential. The power supply potential VDD is, for example, a potential of several volts to several tens of volts, such as 24V, or a potential of approximately 100V to several hundreds of volts.

[0019] The device 20A is, for example, a tool provided in association with a robot or a driving device for the robot to which the tool is connected, and operates based on a control command included in an input / output signal IOS transmitted from the device 10A. An example of a tool provided in association with a robot is a gripper operated by air pressure.

[0020] The I / O signal holding device 30A stores the logical value of the I / O signal IOS transmitted from the device 10A to the device 20A, detects a drop in the power supply potential VDD, and holds the logical value of the I / O signal IOS at the stored logical value in response to the detection. The I / O signal holding device 30A includes, for example, a holding section 31 and a detection section 32. The I / O signal holding device 30A is supplied with a potential Vbat from an auxiliary power supply 40 as a backup when the power supply potential VDD drops. The I / O signal holding device 30A is also supplied with a reference potential GND as a ground potential. The potential Vbat is, for example, a potential of the same value as the power supply potential VDD, and is a potential of about several tens of volts such as 24V, or a potential of about 100V to several hundreds of volts.

[0021] The holding unit 31 stores the logical value of the input / output signal IOS, and, in response to detection by the detection unit 32 of a drop in the power supply potential VDD, holds the logical value of the input / output signal IOS at the stored logical value.

[0022] The detection unit 32 detects that the power supply potential VDD of the device 10A is equal to or lower than a predetermined potential. The detection unit 32 transmits a potential Vsub of a detection signal indicating the detection result to the holding unit 31. The detection unit 32 is also supplied with a reference potential Vref and a potential Vbat from the auxiliary power supply 40. The reference potential Vref is a potential used to determine a drop in the power supply potential VDD, and is a potential lower than the potential of the power supply potential VDD when the main power supply device (not shown) is operating normally. The reference potential Vref is, for example, a predetermined predetermined potential itself, or a potential determined based on the predetermined potential.

[0023] The auxiliary power supply 40 is a power supply for supplying power to the I / O signal holding device 30A when a power supply potential VDD supplied from a main power supply device (not shown) to the I / O signal holding device system 1A drops. The auxiliary power supply 40 generates a potential Vbat and a reference potential Vref, and supplies the generated potential Vbat and reference potential Vref to the detection unit 32 of the I / O signal holding device 30A.

[0024] <Circuit configuration> Next, a detailed description will be given of the circuit configuration of the I / O signal holding device 30A and the auxiliary power supply 40 of the I / O signal holding device system 1A with reference to Fig. 2. Fig. 2 is a diagram showing the detailed circuit configuration of the I / O signal holding device system 1A shown in Fig. 1.

[0025] As shown in FIG. 2, the main part of the holding unit 31 in the I / O signal holding device 30A includes, for example, a rectifying element DI, a capacitive element C, a resistive element R1, a latch circuit 311, and a switch SW.

[0026] The rectifier element DI is, for example, a diode, and is provided between the input / output signal line W_IOS and one end of the capacitance element C. The rectifier element DI rectifies the current flowing between the input / output signal line W_IOS and one end of the capacitance element C so that the current path from the input / output signal line W_IOS to one end of the capacitance element C is conductive, while the current path from the one end of the capacitance element C to the input / output signal line W_IOS is non-conductive. The capacitance element C has an anode terminal connected to the input / output signal line W_IOS, and a cathode terminal connected to one end of the capacitance element C, one end of the resistance element R1, and the input terminal of the latch circuit 311.

[0027] The capacitance element C is, for example, a capacitor. The capacitance element C stores electric charge supplied to one end from the input / output signal line W_IOS via the rectifier element DI. One end of the capacitance element C is connected to the cathode terminal of the rectifier element DI, one end of the resistor element R1, and the input terminal of the latch circuit 311, and the other end is connected to the reference line W_GND.

[0028] The resistive element R1 is, for example, a resistor. The resistive element R1 is provided between the capacitive element C and the reference line W_GND, and determines the time that the capacitive element C can continue to store a logical value. Specifically, the resistive element R1 determines the discharge speed when an electric charge is discharged from one end of the capacitive element C to the reference line W_GND via the resistive element R1 by a time constant τ determined by the capacitance value of the capacitive element C and the resistance value of the resistive element R1. One end of the resistive element R1 is connected to the cathode terminal of the rectifier element DI, one end of the capacitive element C, and the input terminal of the latch circuit 311, and the other end is connected to the reference line W_GND.

[0029] The latch circuit 311 receives the potential Vsub of the detection signal as a power supply to the power supply terminal, and supplies the potential Vsub from the output terminal to the input / output signal line W_IOS via the switch SW based on the potential of one end of the capacitance element C supplied to the input terminal. Specifically, when the potential supplied to the input terminal becomes high level, the latch circuit 311 supplies the potential Vsub supplied to the power supply terminal to the input / output signal line W_IOS from the output terminal via the switch SW. Furthermore, the latch circuit 311 outputs the potential Vsub from the output terminal until the charge stored at one end of the capacitance element C is discharged via the resistance element R1 and the potential supplied to the input terminal transitions from high level to low level, and stops the output in response to the transition of the potential supplied to the input terminal to low level. Furthermore, the latch circuit 311 is mainly configured to include, for example, transistors TR1 and TR2.

[0030] The transistor TR1 is, for example, a PNP bipolar transistor. In the transistor TR1, a current path from the emitter terminal to the collector terminal is conductive in response to a current being supplied to the base terminal. The transistor TR1 has a base terminal connected to the collector terminal of the transistor TR2, an emitter terminal connected to the output terminal of the detection unit 32, and a collector terminal connected to the input terminal of the latch circuit 311 and the base terminal of the transistor TR2.

[0031] The transistor TR2 is, for example, an NPN bipolar transistor. In the transistor TR2, a current path from the collector terminal to the emitter terminal is conductive in response to a current being supplied to the base terminal. The transistor TR2 has a base terminal connected to the input terminal of the latch circuit 311 and the collector terminal of the transistor TR1, an emitter terminal connected to one end of the switch SW, and a collector terminal connected to the base terminal of the transistor TR2.

[0032] The switch SW is a switching element such as a transistor or a photocoupler. The switch SW controls the state between both ends to either an open state or a short state based on the potential supplied to a control terminal. One end of the switch SW is connected to the output terminal of the latch circuit 311, the other end is connected to the input / output signal line W_IOS, and the control terminal is connected to the output terminal of the detection unit 32 and the power supply terminal of the latch circuit 311.

[0033] Next, a description will be given of the circuit configuration of the detection unit 32 in the I / O signal holding device 30A. The detection unit 32 mainly includes, for example, resistance elements R2 to R4, a comparison unit AMP, and a logic circuit NAND.

[0034] The resistive elements R2 and R3 are, for example, resistors. The resistive elements R2 and R3 are provided in series between the input terminal of the detection unit 32 and the reference line W_GND, thereby dividing the power supply potential VDD supplied to the input terminal at a ratio based on the resistance values ​​of the resistive elements R2 and R3, and supplying the divided potential to the inverting input terminal - of the comparison unit AMP. One end of the resistive element R2 is connected to the input terminal of the detection unit 32, and the other end is connected to one end of the resistive element R3 and the inverting input terminal - of the comparison unit AMP. One end of the resistive element R3 is connected to the other end of the resistive element R2 and the inverting input terminal - of the comparison unit AMP, and the other end is connected to the reference line W_GND.

[0035] The comparison unit AMP is, for example, an operational amplifier. The comparison unit AMP judges whether or not the potential input to the non-inverting input terminal + is greater than the potential input to the inverting input terminal -. When the judgment result is a positive judgment, the comparison unit AMP outputs a high-level potential, and when the judgment result is a negative judgment, the comparison unit AMP outputs a low-level potential. In the comparison unit AMP, a power supply potential VDD is supplied to a power supply terminal, a reference potential Vref is supplied to a non-inverting input terminal +, an inverting input terminal - is connected to the other end of the resistor element R2 and one end of the resistor element R3, and an output terminal is connected to one end of the resistor element R4 and another input terminal in the logic circuit NAND.

[0036] In this embodiment, the reference potential Vref input to the non-inverting input terminal + of the comparison unit AMP is, for example, a potential obtained when a predetermined potential is divided by a voltage divider circuit using resistor elements R2 and R3 of the detection unit 32. The reference potential Vref is supplied from a power source different from the main power supply device that supplies the power supply potential VDD. The reference potential Vref is supplied from, for example, the auxiliary power supply 40.

[0037] The resistive element R4 is, for example, a resistor. The resistive element R4 functions as a pull-down resistor for the other input terminal of the logic circuit NAND. One end of the resistive element R4 is connected to the output terminal of the comparator AMP and the other input terminal of the logic circuit NAND, and the other end is connected to the reference line W_GND.

[0038] The logic circuit NAND performs a logical NOT operation on a logical value based on the potential input to the other input terminal, and further performs a NAND operation on a logical value based on the potential input to the one input terminal and the result of the operation, and outputs the result of the NAND operation as a detection signal. The logic circuit NAND treats a high level potential as a logical value "1" and a low level potential as a logical value "0". The logic circuit NAND is supplied with a high level potential Vbat from the auxiliary power supply 40 to a power supply terminal and one input terminal, is supplied with the potential of the output terminal of the comparison unit AMP to the other input terminal, and has a ground terminal connected to the reference line W_GND. The logic circuit NAND also outputs a detection signal having a potential Vsub from an output terminal to a control terminal of the switch SW in the holding unit 31 and a power supply terminal of the latch circuit 311.

[0039] The auxiliary power supply 40 is a power supply device different from the main power supply device, and generates a potential Vbat so that the logic circuit NAND of the detection unit 32 operates even when the power supply potential VDD supplied from the main power supply device drops, and supplies the generated potential Vbat to the logic circuit NAND of the detection unit 32. The auxiliary power supply 40 also generates a reference potential Vref, and supplies the generated reference potential Vref to the non-inverting input terminal + of the comparison unit AMP. The main part of the auxiliary power supply 40 includes, for example, a voltage source VB and a boost circuit 41.

[0040] The voltage source VB is, for example, a primary battery, a secondary battery, a low-capacity power supply device, etc. The voltage source VB generates a potential of about several volts and supplies the generated potential to the input terminal IN of the boost circuit 41. The voltage source VB has a positive terminal connected to the input terminal IN of the boost circuit 41 and a negative terminal connected to the reference line W_GND and the reference terminal G on the input side of the boost circuit 41.

[0041] The boost circuit 41 generates a potential Vbat and a reference potential Vref by boosting a potential of about several volts supplied from the voltage source VB. The boost circuit 41 supplies the generated potential Vbat from an output terminal O1 to a power supply terminal and one input terminal of the logic circuit NAND of the detection unit 32, and supplies the generated Vref from an output terminal O2 to a non-inverting input terminal + of the comparison unit AMP of the detection unit 32. The input terminal IN of the boost circuit 41 is connected to the positive terminal of the voltage source VB, the reference terminals G of the input and output sides are connected to a reference line W_GND, the output terminal O1 is connected to a power supply terminal and one input terminal of the logic circuit NAND of the detection unit 32, and the output terminal O2 is connected to the non-inverting input terminal + of the comparison unit AMP of the detection unit 32.

[0042] <An example of operation when the power supply potential VDD is higher than a predetermined potential> The above describes the circuit configuration of the I / O signal holding device 30 A. Next, a description will be given of the operation of the I / O signal holding device 30 A when the power supply potential VDD supplied from the main power supply is higher than a predetermined potential and does not drop.

[0043] First, the I / O signal holding device 30A stores the logical value of the I / O signal IOS by the capacitive element C of the holding unit 31. Specifically, when the logical value of the I / O signal IOS is "1", the capacitive element C stores the logical value "1" by storing charge supplied via the rectifier element DI. When the logical value of the I / O signal IOS is "0", the capacitive element C stores the logical value "10" by discharging the charge stored via the resistive element R1.

[0044] Furthermore, the input / output signal holding device 30A divides the power supply potential VDD supplied from the main power supply device by the resistor elements R2 and R3 of the detection section 32.

[0045] Next, the I / O signal holding device 30A uses the comparator AMP to determine whether the potential divided by the resistor elements R2 and R3 is equal to or lower than the reference potential Vref. The I / O signal holding device 30A uses the comparator AMP to determine that the power supply potential VDD is higher than a predetermined potential, and transmits a low-level potential as the determination result to the logic circuit NAND.

[0046] Next, the I / O signal holding device 30A performs a logical operation on the high-level potential supplied to one input terminal and the low-level potential supplied to the other input terminal by the logic circuit NAND. The I / O signal holding device 30A supplies a detection signal having a low-level potential Vsub as the operation result to the control terminal of the switch SW in the holding unit 31 and the power supply terminal of the latch circuit 311.

[0047] Next, the I / O signal holding device 30A stops the output of the latch circuit 311 by supplying a low-level potential Vsub to the power supply terminal of the latch circuit 311 of the holding unit 31. The I / O signal holding device 30A also controls the state of the switch SW of the holding unit 31 to an open state by supplying a low-level potential Vsub to the control terminal of the switch SW. As a result, the I / O signal holding device 30A stops the output of a signal from the holding unit 31 to the I / O signal line W_IOS, thereby stopping the operation of holding the logical value of the I / O signal IOS at the stored logical value.

[0048] <An example of operation when the power supply potential VDD is equal to or lower than a predetermined potential> Next, the operation of the I / O signal holding device 30A when the power supply potential VDD supplied from the main power supply is equal to or lower than a predetermined potential and is dropping will be described. Note that the operations of the capacitive element C in the holding unit 31 and the resistive elements R2 and R3 in the detection unit 32 are the same as those when the power supply potential VDD is higher than the predetermined potential, so their explanation will be omitted.

[0049] The I / O signal holding device 30A uses the comparator AMP to determine whether the potential divided by the resistor elements R2 and R3 is equal to or lower than the reference potential Vref. The I / O signal holding device 30A uses the comparator AMP to determine that the power supply potential VDD is equal to or lower than a predetermined potential, and transmits a high-level potential as the determination result to the logic circuit NAND.

[0050] Next, the I / O signal holding device 30A performs a logical operation on the high-level potential supplied to one input terminal and the high-level potential supplied to the other input terminal by the logic circuit NAND. The I / O signal holding device 30A supplies a detection signal having a high-level potential Vsub as the operation result to the control terminal of the switch SW in the holding unit 31 and the power supply terminal of the latch circuit 311.

[0051] Next, the I / O signal holding device 30A outputs a potential from its output terminal based on the potential supplied to the input terminal of the latch circuit 311 by supplying a high-level potential Vsub to the power terminal of the latch circuit 311 of the holding section 31. Specifically, when the capacitive element C stores a logical value of "1", the input terminal of the latch circuit 311 is supplied with a high-level potential corresponding to the logical value of "1", turning the latch circuit 311 on, and the output terminal of the latch circuit 311 is supplied with the potential Vsub supplied to the power terminal of the latch circuit 311. When the capacitive element C stores a logical value of "0", the input terminal of the latch circuit 311 is supplied with a low-level potential corresponding to the logical value of "0", turning the latch circuit 311 off, and the output of the potential Vsub supplied to the power terminal of the latch circuit 311 from the output terminal of the latch circuit 311 is stopped.

[0052] Furthermore, the I / O signal holding device 30A controls the state of the switch SW to a short-circuit state by supplying a high-level potential Vsub to the control terminal of the switch SW of the holding unit 31. As a result, the I / O signal holding device 30A outputs a signal from the holding unit 31 to the I / O signal line W_IOS, thereby holding the logical value of the I / O signal IOS at the stored logical value.

[0053] <Effects> As described above, in the first embodiment, the input / output signal holding device 30A includes a detection unit 32 that detects whether the power supply potential VDD of device 10A (first device) is equal to or lower than a predetermined potential, and a holding unit 31 that stores the logical value of the input / output signal IOS output from device 10A and input to device 20A (second device) and holds the logical value of the input / output signal IOS to the stored logical value based on detection by the detection unit 32.

[0054] Therefore, the input / output signal holding device 30A can hold the state of the logic value of the input / output signal IOS even when the power supply potential VDD drops.

[0055] In the first embodiment, the device 20A is a robot or a tool connected to a robot, and the device 10A is a control device for controlling the operation of the device 20A.

[0056] As a result, the input / output signal holding device 30A can hold the logical value state of the input / output signal IOS even when the power supply potential VDD drops, thereby enabling device 10A to continue to maintain its control over the operation of device 20A in the state it was in immediately before the power supply potential VDD dropped.

[0057] In addition, in the first embodiment, the holding unit 31 has a capacitive element C to one end of which charge is supplied from an input / output signal line W_IOS that transmits an input / output signal IOS, and a latch circuit 311 to which a potential Vsub of a detection signal indicating a detection result of the detection unit 32 is supplied as a power source and which supplies the potential Vsub of the detection signal to the input / output signal line W_IOS based on the potential of one end of the capacitive element C.

[0058] Therefore, when the power supply potential VDD drops, the input / output signal holding device 30A supplies a potential Vsub from the latch circuit 311 to the input / output signal line W_IOS based on the potential at one end of the capacitive element C, thereby enabling the logical value state of the input / output signal IOS to be held with a simple configuration when the power supply potential VDD drops.

[0059] In the first embodiment, the detection unit 32 is operated by an auxiliary power supply 40 that is a power supply different from the power supplies of the devices 10A and 20A.

[0060] Therefore, the I / O signal holding device 30A reduces the effect of a drop in the power supply potential VDD on the operation of the detection unit 32, and can hold the logic state of the I / O signal IOS with high reliability when the power supply potential VDD drops.

[0061] In the first embodiment, the input / output signal holding device system 1A includes a device 20A (a robot to which a tool is connected), a device 10A (a control device) for controlling the operation of the device 20A, and an input / output signal holding device 30A. The input / output signal holding device 30A also includes a detection unit 32 that detects whether the power supply potential VDD of the device 10A is equal to or lower than a predetermined potential, and a holding unit 31 that stores the logical value of the input / output signal IOS output from the device 10A and input to the device 20A, and holds the logical value of the input / output signal IOS at the stored logical value based on the detection by the detection unit 32.

[0062] Therefore, the input / output signal holding device system 1A can hold the state of the logic value of the input / output signal IOS between the device 10A and the device 20A even if the power supply potential VDD drops.

[0063] --- Second embodiment --- Next, a second embodiment will be described.

[0064] <Overall composition> 3 is a block diagram showing the overall configuration of an I / O signal holding device system 1B according to a second embodiment. As shown in FIG. 3, the I / O signal holding device system 1B includes, for example, a plurality of devices 10A and 10B, I / O signal lines W_IOS1 to W_IOS3, devices 20A and 20B, an I / O signal holding device 30B, and an auxiliary power supply 40.

[0065] The auxiliary power supply 40 is the same as in the first embodiment, and therefore a description thereof will be omitted. In the second embodiment, the I / O signal holding device system 1B includes one device 10A, one device 10B, two devices 20A, one device 20B, and three I / O signal lines W_IOS1 to WIOS3, and the I / O signal holding device 30B has three holding units 31, but is not limited to this. The I / O signal holding device system 1B may include a plurality of I / O signal lines, and the I / O signal holding device 30B may have a plurality of holding units 31.

[0066] The device 10A is a control device for the device 20A, but unlike the first embodiment, it controls the operation of the two devices 20A. The device 10A controls the operation of one device 20A by transmitting an input / output signal IOS1 including a control command to the one device 20A via an input / output signal line W_IOS1. The device 10A also controls the operation of the other device 20A by transmitting an input / output signal IOS2 including a control command to the other device 20A via an input / output signal line W_IOS2.

[0067] The device 10B is a control device for the device 20B. The device 10B controls the operation of the device 20B by transmitting an input / output signal IOS3 including a control command to the device 20B via an input / output signal line W_IOS3.

[0068] One device 20A operates based on a control command included in an input / output signal IOS1 transmitted from device 10A. The other device 20A operates based on a control command included in an input / output signal IOS2 transmitted from device 10A. The device 20B operates based on a control command included in an input / output signal IOS3 transmitted from device 10B.

[0069] The I / O signal holding device 30A stores the logical values ​​of the I / O signals IOS1 to IOS3, detects a drop in the power supply potential VDD, and holds the logical values ​​of the I / O signals IOS1 to IOS3 at the stored logical values ​​in response to the detection. The I / O signal holding device 30A includes, for example, three holding units 31, each of which corresponds to one of the I / O signals IOS1 to IOS3, and one detection unit 32 that detects a drop in the power supply potential VDD and supplies a potential Vsub of a detection signal in response to the detection to each holding unit 31. Note that the holding unit 31 and the detection unit 32 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0070] <Effects> As described above, in the second embodiment, the holding unit 31 is provided for each of the multiple input / output signals IOS1 to IOS3.

[0071] Therefore, the I / O signal holding device 30B can hold the state of the logical values ​​of the multiple I / O signals IOS1 to IOS3 even when the power supply potential VDD drops.

[0072] <Modification>

[0073] The present invention is not limited to the above-described embodiment. In other words, the above-described embodiment may be modified by a person skilled in the art as appropriate, and the modifications may be included within the scope of the present invention as long as they include the characteristics of the present invention. In addition, the elements of the above-described embodiment and the modifications described below may be combined to the extent technically possible, and the combinations of these may be included within the scope of the present invention as long as they include the characteristics of the present invention.

[0074] For example, in the first and second embodiments, the reference potential Vref supplied to the comparison unit AMP is generated by the auxiliary power supply 40, but is not limited to this. The reference potential Vref may be supplied from a constant voltage circuit, such as a BGR (Bandgap Reference) circuit that uses the power supply potential VDD as its power source.

[0075] According to this configuration, the input / output signal holding devices 30A and 30B are supplied with the reference potential Vref by the constant voltage circuit, so that even if the power supply potential VDD drops, the effects of fluctuations due to a drop in the power supply potential VDD or other factors can be reduced while the logical value of the input / output signal IOS can be held at the stored logical value.

[0076] Furthermore, the input / output signal holding devices 30A and 30B may supply the power supply potential VDD, instead of the potential Vbat, to the power supply terminal of the comparator AMP of the detection section 32 and to the power supply terminal and one input terminal of the logic circuit NAND.

[0077] According to this configuration, the input / output signal holding devices 30A and 30B operate the detection unit 32 using the power supply potential VDD and the reference potential Vref based on the power supply potential VDD, without relying on the auxiliary power supply 40, so that the logical value of the input / output signal IOS can be held at the stored logical value at low cost and in a space-saving manner, even if the power supply potential VDD drops.

[0078] Moreover, the resistive elements R3 and R4 in the detection unit 32 may be variable resistors.

[0079] According to this configuration, the I / O signal holding devices 30A and 30B can change the voltage division ratio by the resistor elements R3 and R4, and can essentially change the predetermined potential that is the reference for determining whether the power supply potential VDD has dropped. Therefore, the I / O signal holding devices 30A and 30B can change the predetermined potential for determining whether the power supply potential VDD has dropped with a simple configuration. [Explanation of symbols]

[0080] 10A to 10B... device (first device), 20A to 20B... device (second device), 30A to 30B... input / output signal holding device, 31... holding section, 32... detection section

Claims

1. a detection unit that detects whether a power supply potential of the first device is equal to or lower than a predetermined potential; a holding unit that stores a logical value of an input / output signal output from the first device and input to the second device, and holds the logical value of the input / output signal at the stored logical value based on detection by the detection unit; 1. An input / output signal holding device comprising:

2. the second device is a robot or a tool connected to the robot; The first device is a control device for controlling the operation of the second device.

2. The input / output signal holding device according to claim 1.

3. the holding unit includes a capacitance element having one end to which charge is supplied from an input / output signal line that transmits the input / output signal, and a latch circuit to which a potential of a detection signal indicating a detection result of the detection unit is supplied as a power source, and which supplies the potential of the detection signal to the input / output signal line based on the potential of the one end of the capacitance element.

3. The input / output signal holding device according to claim 2, further comprising:

4. The detection unit is operated by a power source different from a power source of the first device and the second device.

4. The input / output signal holding device according to claim 2 or 3.

5. The holding unit is provided for each of a plurality of input / output signals.

4. The input / output signal holding device according to claim 2 or 3.

6. A robot to which the tool is connected; A control device for controlling the operation of the robot or the tool; an input / output signal holding device including a detection unit that detects whether a power supply potential of the control device is equal to or lower than a predetermined potential, and a holding unit that stores logical values ​​of input / output signals output from the control device and input to the tool, and holds the logical values ​​of the input / output signals at the stored logical values ​​based on the detection by the detection unit; An input / output signal holding device system comprising:

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