Semiconductor device

Abstract

To provide a semiconductor device in which oscillation of a transistor can be suppressed.SOLUTION: A semiconductor device includes a substrate, first to fourth conductive parts provided on the substrate, a first transistor having a drain connected to the first conductive part and a source connected to the second conductive part, and second and third transistors each having a drain connected to the second conductive part, a source connected to the third conductive part, and a gate connected to the fourth conductive part. The second conductive part includes a first part and a second part that are in contact with the second and third transistors, respectively. The third conductive part includes a third part and a fourth part that are connected to the sources of the second and third transistor, respectively, and a fifth part electrically connecting the third and fourth parts. The fourth conductive part includes a sixth part and a seventh part connected to the gates of the second and third transistors, respectively, and an eight part electrically connecting the sixth and seventh parts. The shape of the eighth part is different from the shapes of the sixth part and the seventh part.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A power module having a half-bridge configuration in which a plurality of transistors are connected in series is known as a semiconductor device, and is used in a traction inverter or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6899976 [Patent Document 2] International Publication No. 2019 / 44748 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing transistor oscillation is provided. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a substrate, a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion provided on the substrate, a first transistor having a drain electrically connected to the first conductive portion and a source electrically connected to the second conductive portion, and a second transistor and a third transistor each having a drain electrically connected to the second conductive portion, a source electrically connected to the third conductive portion, and a gate electrically connected to the fourth conductive portion, the second conductive portion including a first portion in contact with the second transistor and a second portion in contact with the third transistor and located on the opposite side to the first portion with respect to the first conductive portion, and the third conductive portion includes a first portion in contact with the second transistor and a second portion in contact with the third transistor and located on the opposite side to the first portion with respect to the first conductive portion. the fourth conductive portion includes a sixth portion to which a gate of the second transistor is connected and located on the opposite side of the first conductive portion with respect to the third portion, a seventh portion to which a gate of the third transistor is connected and located on the opposite side of the first conductive portion with respect to the fourth portion, and an eighth portion electrically connecting the sixth portion and the seventh portion, wherein the shape of the eighth portion is different from the shapes of the sixth portion and the seventh portion. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing an example of an external structure of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a perspective view showing an example of an internal structure of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a plan view showing an example of a planar layout of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the first embodiment. [Figure 6] FIG. 6 is a plan view showing an example of a planar layout of a semiconductor device according to a second modification of the first embodiment. [Figure 7] FIG. 7 is a perspective view showing an example of an internal structure of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a plan view showing an example of a planar layout of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When it is not necessary to distinguish between elements represented by reference numerals containing the same letters, these elements are referred to by reference numerals containing only letters.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element through an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] 1. First embodiment A first embodiment will be described. In the following, a power module will be described as an example of a semiconductor device according to the first embodiment. The power module is applied to, for example, a traction inverter or the like.

[0010] The configuration of the semiconductor device according to the first embodiment will be described.

[0011] First, the external structure of the semiconductor device according to the first embodiment will be described.

[0012] 1 is a perspective view showing an example of the external structure of a semiconductor device according to the first embodiment. The semiconductor device 1 includes a housing structure in which a package provided on a substrate 10 is sealed with a sealing resin 100.

[0013] The substrate 10 is, for example, a ceramic substrate. In the following description, the plane on which the substrate 10 extends is the XY plane. In the XY plane, the longer direction and the shorter direction of the substrate 10 are the X direction and the Y direction, respectively. The direction intersecting the XY plane is the Z direction or upward direction. The directions opposite to the X direction, the Y direction, and the Z direction are the -X direction, the -Y direction, and the -Z direction, respectively. The -Z direction is the downward direction.

[0014] The sealing resin 100 includes, for example, an epoxy resin. The sealing resin 100 insulates between conductors in the semiconductor device 1. The sealing resin 100 also protects the components of the semiconductor device 1 from physical disturbances.

[0015] The semiconductor device 1 further includes terminals P, N, AC, HS, HG, LS, and LG, and a heat sink 40.

[0016] The terminals P, N, AC, HS, HG, LS, and LG are ends of metal parts that electrically connect between an external device and an internal circuit configuration of the semiconductor device 1. The semiconductor device 1 includes two terminals N and one each of terminals P, AC, HG, HS, LG, and LS. These terminals are provided spaced apart from each other.

[0017] The terminal P is an input terminal. The terminal P is connected to a positive terminal (P) of an external DC power supply. The terminal P is provided so as to extend in the -Y direction from the -Y side surface of the housing structure formed by the sealing resin 100.

[0018] The two terminals N are input terminals. The two terminals N are connected to the negative terminal (N: negative terminal) of an external DC power supply. The two terminals N are electrically connected to each other. The two terminals N are arranged side by side in the X direction to sandwich the terminal P, and are provided to extend in the -Y direction from the -Y side surface portion of the housing structure formed by the sealing resin 100.

[0019] The terminal AC is an output terminal. An alternating current is output to an external device through the terminal AC. The terminal AC is provided so as to extend in the Y direction from the Y side surface of the housing structure formed by the sealing resin 100.

[0020] The terminals HG and LG are control terminals. For example, the terminals HG and LG are terminals for controlling whether or not to drive a semiconductor element included in the circuit configuration of the semiconductor device 1. The terminals HG and LG are arranged side by side with the terminal AC in the X direction, and are provided so as to extend in the Y direction from the Y side surface portion of the housing structure formed by the sealing resin 100.

[0021] The terminals HS and LS are control terminals. The terminal HS is, for example, a terminal that serves as a reference for the voltage of the terminal HG. The terminal LS is, for example, a terminal that serves as a reference for the voltage of the terminal LG. The terminals HS and LS are arranged side by side with the terminals AC, HG, and LG in the Y direction, and are provided so as to extend in the Y direction from the Y side surface portion of the housing structure formed by the sealing resin 100.

[0022] The heat sink 40 has a plate shape containing copper, for example. The heat sink 40 is in contact with the lower surface of the substrate 10. The heat sink 40 has a role of releasing heat generated inside the substrate 10 to the outside, thereby cooling the semiconductor device 1.

[0023] Next, the circuit configuration of the semiconductor device according to the first embodiment will be described.

[0024] 2 is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the first embodiment. The semiconductor device 1 further includes a high-side transistor HTr and a low-side transistor LTr as electrical elements included in the internal circuit configuration.

[0025] The high-side transistor HTr and the low-side transistor LTr are, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). As shown in FIG. 4, the high-side transistor HTr and the low-side transistor LTr are connected in series via a node N1. That is, the high-side transistor HTr and the low-side transistor LTr form a half-bridge circuit. The semiconductor device 1 is a 2-in-1 module including a half-bridge circuit in one module. In the following description, components related to the operation of the high-side transistor HTr are labeled "high side" and components related to the operation of the low-side transistor LTr are labeled "low side" to distinguish them from each other.

[0026] The drain terminal of the high-side transistor HTr is connected to the terminal P.

[0027] The source terminal of the high-side transistor HTr is connected to the drain terminal of the low-side transistor LTr via a node N1. A terminal HS is also connected to the node N1. That is, the terminal HS is a terminal connected to a high-side source terminal. A voltage applied to the source of the high-side transistor HTr and the drain of the low-side transistor LTr is monitored via the terminal HS. Furthermore, a terminal AC is connected to the node N1. For example, by controlling the driving of the high-side transistor HTr and the low-side transistor LTr, an AC signal is output from the terminal AC to the outside.

[0028] A terminal HG is connected to the gate terminal of the high-side transistor HTr. In other words, the terminal HG is a terminal connected to a high-side gate terminal. Whether or not to drive the high-side transistor HTr is controlled via the terminal HG. When the voltage applied to the terminal HG is higher than the threshold voltage of the high-side transistor HTr, the drain terminal and the source terminal of the high-side transistor HTr are electrically connected. When the voltage applied to the terminal HG is lower than the threshold voltage of the high-side transistor HTr, the drain terminal and the source terminal of the high-side transistor HTr are electrically insulated.

[0029] The source terminal of the low-side transistor LTr is connected to two terminals N via a node N2. A terminal LS is also connected to the node N2. That is, the terminal LS is a terminal connected to a low-side source terminal. The voltage applied to the source of the low-side transistor LTr is monitored via the terminal LS.

[0030] The gate terminal of the low-side transistor LTr is connected to the terminal LG. That is, the terminal LG is a terminal connected to the low-side gate terminal. Whether or not to drive the low-side transistor LTr is controlled via the terminal LG. When the voltage applied to the terminal LG is higher than the threshold voltage of the low-side transistor LTr, the drain terminal and the source terminal of the low-side transistor LTr are electrically connected. When the voltage applied to the terminal LG is lower than the threshold voltage of the low-side transistor LTr, the drain terminal and the source terminal of the low-side transistor LTr are electrically insulated.

[0031] With the above-mentioned configuration, the semiconductor element inside the semiconductor device 1 is controlled by a voltage supplied from outside the semiconductor device 1, and generates and outputs an AC signal to the outside.

[0032] Next, the internal structure of the semiconductor device according to the first embodiment will be described.

[0033] Fig. 3 is a perspective view showing an example of the internal structure of the semiconductor device according to the first embodiment. Fig. 4 is a plan view showing an example of the planar layout of the semiconductor device according to the first embodiment. The sealing resin 100 is omitted in Figs. 3 and 4. The structure of the semiconductor device 1 will be described with reference to Figs. 3 and 4.

[0034] 3 and 4, the semiconductor device 1 further includes conductive portions 21, 22, 23, 24, and 25. The semiconductor device 1 also includes a plurality of transistors 31a and 31b as transistors corresponding to the high-side transistor HTr, and a plurality of transistors 32a and 32b as transistors corresponding to the low-side transistor LTr.

[0035] In the following description, "conductor pattern" refers to flat conductors spaced apart from each other on the upper surface of the substrate 10. "Wire" refers to linear bonding wires that electrically connect conductor patterns. "Terminal member" refers to a conductive member that electrically connects between the conductor pattern and a device that exists outside the semiconductor device 1.

[0036] A "wire" has a different shape from a "conductor pattern." Therefore, the electrical properties of a "wire" and a "conductor pattern," such as inductance, are significantly different. Specifically, the inductance of a "wire" that connects two points is higher than the inductance of a "conductor pattern" that connects the same two points.

[0037] The conductive portion 21 is a group of conductors corresponding to the wiring of the high side gate. The conductive portion 21 includes conductor patterns 21a and 21b, a wire 21c, a plurality of wires 21d and 21e, and a terminal member 21f. The conductor pattern 21a is provided in the center of the substrate 10. The conductor pattern 21b extends in the X direction and is provided on the substrate 10 so as to be aligned with the conductor pattern 21a in the Y direction. The wire 21c has a first end in contact with the conductor pattern 21a and a second end in contact with the conductor pattern 21b. The wire 21c is provided so as to pass above a third portion of the conductor pattern 23a and a terminal member 23e, which will be described later. Each of the plurality of wires 21d has a first end in contact with the conductor pattern 21a and a second end in contact with a gate electrode (not shown) provided on the upper surface of a corresponding transistor among the plurality of transistors 31a. Each of the wires 21e has a first end in contact with the conductor pattern 21a and a second end in contact with a gate electrode (not shown) provided on the upper surface of a corresponding one of the transistors 31b. The terminal member 21f has a first end in contact with the conductor pattern 21b and a second end that functions as a terminal HG. The terminal member 21f passes over a third portion of the conductor pattern 24a (described later) and a conductor pattern 25c, and extends toward the outside of the semiconductor device 1.

[0038] The conductive portion 22 is a group of conductors corresponding to the high-side drain. The conductive portion 22 includes a conductor pattern 22a and a terminal member 22b. The conductor pattern 22a includes a first portion, a second portion, and a third portion. The first portion and the second portion of the conductor pattern 22a are provided to sandwich the conductor pattern 21a in the X direction. The first portion of the conductor pattern 22a contacts a drain electrode (not shown) provided on the lower surface of each of the plurality of transistors 31a. The second portion of the conductor pattern 22a contacts a drain electrode (not shown) provided on the lower surface of each of the plurality of transistors 31b. The third portion of the conductor pattern 22a is provided extending in the X direction on the opposite side of the conductor pattern 21b with respect to the conductor pattern 21a, and has a first end that contacts the first portion of the conductor pattern 21a and a second end that contacts the second portion of the conductor pattern 21a. The terminal member 22b has a first end that contacts the third portion of the conductor pattern 22a and a second end that functions as a terminal P. The terminal member 22b extends toward the outside of the semiconductor device 1.

[0039] The conductive portion 23 is a group of conductors corresponding to the high-side source and the low-side drain. The conductive portion 23 includes a conductor pattern 23a, a plurality of wires 23b and 23c, and terminal members 23d and 23e. The conductor pattern 23a includes a first portion, a second portion, and a third portion. The first portion and the second portion of the conductor pattern 23a are provided to sandwich the conductor pattern 21a and the first portion and the second portion of the conductor pattern 22a in the X direction. The first portion of the conductor pattern 23a contacts a drain electrode (not shown) provided on the lower surface of each of the plurality of transistors 32a. The second portion of the conductor pattern 23a contacts a drain electrode (not shown) provided on the lower surface of each of the plurality of transistors 32b. The third portion of the conductor pattern 23a is provided between the conductor patterns 21a and 21b and extends in the X direction, and has a first end that contacts the first portion of the conductor pattern 23a and a second end that contacts the second portion of the conductor pattern 23a. Each of the wires 23b has a first end in contact with a first portion of the conductor pattern 23a and a second end in contact with a source electrode (not shown) provided on the upper surface of a corresponding transistor among the transistors 31a. Each of the wires 23c has a first end in contact with a second portion of the conductor pattern 23a and a second end in contact with a source electrode (not shown) provided on the upper surface of a corresponding transistor among the transistors 31b. In addition, in FIG. 3 and FIG. 4, the wires 23b and 23c are provided in pairs for each source electrode of the corresponding transistor among the transistors 31a or 31b, but this is not limited thereto. The wires 23b and 23c may be provided in pairs for each source electrode of the corresponding transistor among the transistors 31a or 31b. The terminal member 23d has a first end in contact with a third portion of the conductor pattern 23a and a second end that functions as a terminal HS. The terminal member 23e has a first end in contact with the third portion of the conductor pattern 23a and a second end functioning as a terminal AC. The terminal members 23d and 23e pass over the conductor pattern 21b, a third portion of a conductor pattern 24a (described later), and a conductor pattern 25c (described later), and extend toward the outside of the semiconductor device 1.

[0040] The conductive portion 24 is a group of conductors corresponding to the low-side source. The conductive portion 24 includes a conductor pattern 24a, a plurality of wires 24b and 24c, and terminal members 24d, 24e, and 24f. The conductor pattern 24a includes a first portion, a second portion, and a third portion. The first and second portions of the conductor pattern 24a are provided to sandwich the conductor pattern 21a, the first and second portions of the conductor pattern 22a, and the first and second portions of the conductor pattern 23a in the X direction. The third portion of the conductor pattern 24a is provided extending in the X direction on the opposite side to the third portion of the conductor pattern 23a with respect to the conductor pattern 21b, and has a first end contacting the first portion of the conductor pattern 24a and a second end contacting the second portion of the conductor pattern 24a. Each of the wires 24b has a first end in contact with a first portion of the conductor pattern 24a and a second end in contact with a source electrode (not shown) provided on the upper surface of the corresponding transistor among the plurality of transistors 32a. Each of the wires 24c has a first end in contact with a second portion of the conductor pattern 24a and a second end in contact with a source electrode (not shown) provided on the upper surface of the corresponding transistor among the plurality of transistors 32b. In addition, in FIG. 3 and FIG. 4, the plurality of wires 24b and 24c are provided in pairs for each source electrode of the corresponding transistor among the plurality of transistors 32a or 32b, but this is not limited thereto. The plurality of wires 24b and 24c may be provided in pairs for each source electrode of the corresponding transistor among the plurality of transistors 32a or 32b. The terminal member 24d has a first end in contact with a first portion of the conductor pattern 24a and a second end functioning as a terminal N. The terminal member 24e has a first end in contact with a second portion of the conductor pattern 24a and a second end functioning as a terminal N. The terminal members 24d and 24e extend side by side toward the outside of the semiconductor device 1. The terminal member 24f has a first end in contact with a third portion of the conductor pattern 24a and a second end functioning as a terminal LS. The terminal member 24f passes over a conductor pattern 25c (described later) and extends toward the outside of the semiconductor device 1.

[0041] The conductive portion 25 is a group of conductors corresponding to the low-side gate. The conductive portion 25 includes conductor patterns 25a, 25b, and 25c, wires 25d and 25e, a plurality of wires 25f and 25g, and a terminal member 25h. The conductor patterns 25a and 25b are provided to sandwich the conductor pattern 21a, the first and second parts of the conductor pattern 22a, the first and second parts of the conductor pattern 23a, and the first and second parts of the conductor pattern 24a in the X direction. The conductor pattern 25c is provided to extend in the X direction on the opposite side to the conductor pattern 21b with respect to the third part of the conductor pattern 24a. The wire 25d has a first end in contact with the conductor pattern 25a and a second end in contact with the conductor pattern 25c. The wire 25e has a first end in contact with the conductor pattern 25b and a second end in contact with the conductor pattern 25c. The wires 25d and 25e are provided so as to pass only above the substrate 10, without passing over other conductors. Each of the wires 25f has a first end in contact with the conductor pattern 25a and a second end in contact with a gate electrode (not shown) provided on the upper surface of a corresponding transistor among the plurality of transistors 32a. The wires 25f are provided so as to pass over the first portion of the conductor pattern 24a. Each of the wires 25g has a first end in contact with the conductor pattern 25b and a second end in contact with a gate electrode (not shown) provided on the upper surface of a corresponding transistor among the plurality of transistors 32b. The wires 25g are provided so as to pass over the second portion of the conductor pattern 24a. The terminal member 25h has a first portion in contact with the conductor pattern 25c and a second end functioning as a terminal LG.

[0042] A plurality of transistors 31a are arranged in the Y direction on the upper surface of the first portion of the conductor pattern 22a. A plurality of transistors 31b are arranged in the Y direction on the upper surface of the second portion of the conductor pattern 22a. A plurality of transistors 32a are arranged in the Y direction on the upper surface of the first portion of the conductor pattern 23a. A plurality of transistors 32b are arranged in the Y direction on the upper surface of the second portion of the conductor pattern 23a. Note that, although three transistors 31a, 31b, 32a, and 32b are provided in each of the examples in FIG. 3 and FIG. 4, it is sufficient that there are one or more transistors 31a and 31b in total, and one or more transistors 32a and 32b each.

[0043] With the configuration according to the first embodiment, it is possible to suppress oscillation of the transistor, as will be described in detail below.

[0044] When there are two transistors that share the same potential at the connections of their drain, source, and gate terminals, the inductance seen in the circuit connecting the source terminals of each transistor is called the source inductance (Ls), and the inductance seen in the circuit connecting the gate terminals of each transistor is called the gate inductance (Lg).

[0045] When manufacturing a large-capacity semiconductor device, multiple transistors having the same function may be distributed in one package in order to increase heat dissipation efficiency. When multiple distributed transistors having the same function are mounted on the same conductor pattern, the distance between the conductor patterns becomes longer, and the inductance (e.g., source inductance) of the conductor pattern tends to increase. High source inductance can cause the transistor to oscillate during switching. Transistor oscillation is undesirable, as it can lead to transistor malfunction, increased losses, and in some cases, the destruction of the transistor.

[0046] One method to suppress transistor oscillation is to increase the ratio of gate inductance to source inductance (Lg / Ls) in the circuit connecting the terminals of each transistor. When the Lg / Ls ratio is large, transistor oscillation is suppressed.

[0047] In the configuration according to the first embodiment, multiple low-side transistors are arranged separately in one package so as to sandwich multiple high-side transistors in the X direction. Therefore, the conductor pattern 24a connecting the source terminals of the low-side transistors extends long in the X direction, resulting in a high source inductance on the low side. Therefore, it is desirable to increase the gate inductance of the low side in order to increase the Lg / Ls ratio.

[0048] In the configuration according to the first embodiment, the conductor pattern in the circuit connecting the gate terminal of the transistor 32a and the gate terminal of the transistor 32b in the low-side transistor is divided into a plurality of pieces (conductor patterns 25a, 25b, and 25c), and wires 25d and 25e having high inductance are provided as conductors connecting the conductor patterns. This configuration can increase the gate inductance in the circuit connecting the gate terminal of the transistor 32a and the gate terminal of the transistor 32b. As a result, the Lg / Ls ratio can be increased, and oscillation of the low-side transistor can be suppressed.

[0049] In addition, in the configuration according to the first embodiment, the transistors 31a, 31b, 32a, and 32b are distributed on both sides of the conductor pattern 21a, with multiple transistors on each side. With this configuration, the transistors, which are heat sources, are distributed, thereby improving the heat dissipation efficiency of the semiconductor device.

[0050] The semiconductor device 1 according to the first embodiment described above can be modified in various ways. Modifications are shown below.

[0051] Fig. 5 is a plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the first embodiment. Fig. 6 is a plan view showing an example of a planar layout of a semiconductor device according to a second modified example of the first embodiment.

[0052] As shown in FIGS. 5 and 6, the configuration for connecting the conductor patterns 25a and 25c and the configuration for connecting the conductor patterns 25b and 25c are not limited to wires.

[0053] In the first modified example shown in Fig. 5, the conductive portion 25 includes a conductor pattern 25i instead of the conductor patterns 25a, 25b, and 25c, and the wires 25d and 25e. The conductor pattern 25i includes a first portion, a second portion, a third portion, a fourth portion (25i-4), and a fifth portion (25i-5). The first portion, the second portion, the third portion, the fourth portion, and the fifth portion of the conductor pattern 25i correspond to the conductor pattern 25a, the conductor pattern 25b, the conductor pattern 25c, the wire 25d, and the wire 25e in the first embodiment, respectively. The first and second portions of the conductor pattern 25i are provided to sandwich the conductor pattern 21a, the first and second portions of the conductor pattern 22a, the first and second portions of the conductor pattern 23a, and the first and second portions of the conductor pattern 24a in the X direction. The third portion of the conductor pattern 25i is provided extending in the X-direction on the opposite side to the conductor pattern 21b with respect to the third portion of the conductor pattern 24a. The fourth and fifth portions of the conductor pattern 25i are flat conductors having a meandering shape that bends back multiple times. The fourth portion of the conductor pattern 25i has a first end that contacts the first portion of the conductor pattern 25i and a second end that contacts the third portion of the conductor pattern 25i. The fifth portion of the conductor pattern 25i has a first end that contacts the second portion of the conductor pattern 25i and a second end that contacts the third portion of the conductor pattern 25i. The fourth and fifth portions of the conductor pattern 25i having a meandering shape that bends back multiple times have a higher inductance than a conductor pattern having a straight shape.

[0054] In the configuration shown in the first modification, the gate inductance of the low side increases due to an increase in inductance caused by the shapes of the fourth and fifth portions of the conductor pattern 25i, which results in an increase in the Lg / Ls ratio and suppresses oscillation of the low side transistor.

[0055] In the second modified example shown in FIG. 6, the conductive portion 25 includes a conductor pattern 25j instead of the conductor patterns 25a, 25b, and 25c, and the wires 25d and 25e. The conductor pattern 25j includes a first portion, a second portion, a third portion, a fourth portion (25j-4), and a fifth portion (25j-5). The first portion, the second portion, the third portion, the fourth portion, and the fifth portion of the conductor pattern 25j correspond to the conductor pattern 25a, the conductor pattern 25b, the conductor pattern 25c, the wire 25d, and the wire 25e in the first embodiment, respectively. The first and second portions of the conductor pattern 25j are provided so as to sandwich the conductor pattern 21a, the first and second portions of the conductor pattern 22a, the first and second portions of the conductor pattern 23a, and the first and second portions of the conductor pattern 24a in the X direction. The third portion of the conductor pattern 25j is provided extending in the X-direction on the opposite side to the conductor pattern 21b with respect to the third portion of the conductor pattern 24a. The fourth and fifth portions of the conductor pattern 25j are flat conductors having a shorter width than the first, second, and third portions of the conductor pattern 25j. The fourth portion of the conductor pattern 25j has a first end contacting the first portion of the conductor pattern 25j and a second end contacting the third portion of the conductor pattern 25j. The fifth portion of the conductor pattern 25j has a first end contacting the second portion of the conductor pattern 25j and a second end contacting the third portion of the conductor pattern 25j. The fourth and fifth portions of the conductor pattern 25j having a shorter conductor pattern width have a higher inductance than the first, second, and third portions of the conductor pattern 25j.

[0056] In the configuration shown in the second modification, the gate inductance of the low side increases due to an increase in inductance caused by the shapes of the fourth and fifth portions of the conductor pattern 25j, which results in an increase in the Lg / Ls ratio and suppresses oscillation of the low side transistor.

[0057] In addition to the above-described first and second modified examples, various modifications are possible for the configuration corresponding to the wires 25d and 25e in the first embodiment. As long as the configuration corresponding to the wires 25d and 25e in the first embodiment increases the gate inductance on the low side, the shape of the configuration is not important.

[0058] 2. Second embodiment Next, a second embodiment will be described, with the differences from the first embodiment being mainly described below.

[0059] Fig. 7 is a perspective view showing an example of the internal structure of the semiconductor device according to the second embodiment. Fig. 8 is a plan view showing an example of the planar layout of the semiconductor device according to the second embodiment. Note that the sealing resin 100 is omitted in Figs. 7 and 8. The structure of the semiconductor device 1A will be described with reference to Figs. 7 and 8.

[0060] 7 and 8, the semiconductor device 1A includes a conductive portion 26 instead of the conductive portion 24 in the first embodiment. The configuration of the semiconductor device 1A excluding the conductive portion 26 is the same as the configuration of the semiconductor device 1A excluding the conductive portion 24 in the first embodiment.

[0061] The conductive portion 26 is a group of conductors corresponding to the low-side source. The conductive portion 26 includes conductor patterns 26a, 26b, and 26c, wires 26d and 26e, a plurality of wires 26f and 26g, and terminal members 26h, 26i, and 26j. The conductor patterns 26a and 26b correspond to the first and second portions of the conductor pattern 24a in the first embodiment. The conductor pattern 26c and the wires 26d and 26e correspond to the third portion of the conductor pattern 24a in the first embodiment. The plurality of wires 26f and 26g correspond to the plurality of wires 24b and 24c in the first embodiment. The terminal members 26h, 26i, and 26j correspond to the terminal members 24d, 24e, and 24f in the first embodiment.

[0062] The conductor patterns 26a and 26b are provided so as to sandwich the conductor pattern 21a, the first and second parts of the conductor pattern 22a, and the first and second parts of the conductor pattern 23a in the X direction. The conductor pattern 26c is provided so as to extend in the X direction on the opposite side of the conductor pattern 21b from the third part of the conductor pattern 23a. The wire 26d has a first end in contact with the conductor pattern 26a and a second end in contact with the conductor pattern 26c. The wire 26e has a first end in contact with the conductor pattern 26b and a second end in contact with the conductor pattern 26c. The wires 26d and 26e are provided so as to pass only above the substrate 10 without passing over other conductors. Each of the multiple wires 26f has a first end in contact with the conductor pattern 26a and a second end in contact with a source electrode provided on the upper surface of the corresponding transistor among the multiple transistors 32a. Each of the wires 26g has a first end in contact with the conductor pattern 26b and a second end in contact with a source electrode provided on the upper surface of a corresponding transistor among the transistors 32b. In FIG. 7 and FIG. 8, the wires 26f and 26g are provided in pairs for each source electrode of the corresponding transistor among the transistors 32a or 32b, but the number of wires 26f and 26g may be one or more for each source electrode of the corresponding transistor among the transistors 32a or 32b. The terminal member 26h has a first end in contact with the conductor pattern 26a and a second end that functions as a terminal N. The terminal member 26i has a first end in contact with the conductor pattern 26b and a second end that functions as a terminal N. The terminal member 26j has a first end in contact with the conductor pattern 26c and a second end that functions as a terminal LS. The terminal member 26j passes above the conductive pattern 25c and extends toward the outside of the semiconductor device 1.

[0063] The wires 25d and 26d have approximately the same thickness and length. The wires 25d and 26d are arranged side by side. Specifically, the distance between the wires 25d and 26d is designed to be approximately 0.1 mm, including a portion that is at most 2 mm or less. However, the wires 25d and 26d do not touch each other.

[0064] The wires 25e and 26e have approximately the same thickness and length. The wires 25e and 26e are arranged side by side. Specifically, the distance between the wires 25e and 26e is designed to be approximately 0.1 mm, including a portion that is at most 2 mm or less. However, the wires 25e and 26e do not touch each other.

[0065] Furthermore, in the semiconductor device 1A according to this embodiment, in an external configuration (not shown), the circuits connected to the two terminals N are short-circuited to each other.

[0066] The configuration according to the second embodiment can suppress delays in control signals input from the outside. Furthermore, the configuration according to the second embodiment can suppress oscillation of transistors, as in the first embodiment. This will be described in detail below.

[0067] In a circuit connecting the gate terminals of multiple low-side transistors LTr, when the gate inductance Lg increases, the resistance in the circuit also increases, and therefore the control signal sent from the terminal LG to the gate terminal of the low-side transistor LTr may be delayed. Since a semiconductor device having this configuration performs high-speed switching in which the control signal is switched multiple times in a short period of time, a delay in the control signal may lead to a malfunction of the semiconductor device, and is therefore undesirable.

[0068] In the configuration according to the second embodiment, high-inductance wires 26d and 26e are provided as conductors connecting the conductor patterns 26a and 26c, and connecting the conductor patterns 26b and 26c, respectively, in the low-side transistor, which increases the inductance of the circuit connecting the terminal LS and the source terminal of the transistor 32a and the circuit connecting the terminal LS and the source terminal of the transistor 32b.

[0069] Also, wires 25d and 26d are arranged side by side so that they are aligned. Therefore, mutual induction occurs between the inductance of wire 25d and the inductance of wire 26d. Similarly, wires 25e and 26e are arranged side by side so that they are aligned. Therefore, mutual induction occurs between the inductance of wire 25e and the inductance of wire 26e.

[0070] When a low-side gate control voltage is applied to the gate terminal of the transistor 32a, a current flows through the wire 25d from the terminal LG toward the gate terminal of the transistor 32a. On the other hand, when a low-side source control voltage is applied to the source terminal of the transistor 32a, a current flows through the wire 26d from the source terminal of the transistor 32a toward the terminal LS. Therefore, when a control voltage is applied to the transistor 32a, currents flow through the wires 25d and 26d in opposite directions. As a result, the inductances of the wires 25d and 26d cancel each other out due to the mutual induction between the wires 25d and 26d. Similarly, when a control voltage is applied to the transistor 32b, the inductances of the wires 25e and 26e cancel each other out due to the mutual induction between the wires 25e and 26e. As a result, when a control voltage is applied, the inductance of the circuit connecting the terminal LG and the gate terminal of the low-side transistor LTr and the inductance of the circuit connecting the terminal LS and the source terminal of the low-side transistor LTr both decrease, thereby suppressing the delay of the control signal caused by an increase in inductance.

[0071] Furthermore, since the circuits connected to the two terminals N are short-circuited to each other externally, the inductance between the source terminal of the transistor 32a and the source terminal of the transistor 32b connected via the wires 26d and 26e decreases. On the other hand, the inductance between the gate terminal of the transistor 32a and the gate terminal of the transistor 32b connected via the wires 25d and 25e remains high. Therefore, in the circuit connecting the terminals of the low-side transistor LTr, the Lg / Ls ratio becomes large, so that the oscillation of the low-side transistor can be suppressed. At this time, since almost no current flows through the wires 26d and 26e, the inductances do not cancel each other out due to mutual induction. Therefore, the inductance between the gate terminal of the transistor 32a and the gate terminal of the transistor 32b does not decrease.

[0072] The semiconductor device 1A according to the second embodiment described above can be modified in various ways, similar to the semiconductor device 1 according to the first embodiment.

[0073] The configuration for connecting the conductor patterns 26a and 26c, and the configuration for connecting the conductor patterns 26b and 26c are not limited to wires.

[0074] For example, the conductive part 26 may use a flat conductor having a meandering shape that bends back multiple times instead of the wires 26d and 26e to connect the conductor pattern 26a to the conductor pattern 26c, and the conductor pattern 26b to the conductor pattern 26c. In this case, the conductive part 25 uses a flat conductor having a meandering shape that bends back multiple times instead of the wires 25d and 25e to connect the conductor pattern 25a to the conductor pattern 25c, and the conductor pattern 25b to the conductor pattern 25c. A conductor having a meandering shape that bends back multiple times has a higher inductance than a conductor having a straight shape. The conductor connecting the conductor pattern 25a to the conductor pattern 25c and the conductor connecting the conductor pattern 26a to the conductor pattern 26c are arranged side by side in the Z direction, for example, and the distance between these two conductors is about 0.1 mm, and is at most 2 mm or less. The conductor connecting conductor pattern 25b and conductor pattern 25c and the conductor connecting conductor pattern 26b and conductor pattern 26c are arranged side by side, for example, in the Z direction, and the distance between these two conductors is approximately 0.1 mm and at most 2 mm or less.

[0075] Also, for example, the conductive portion 26 may use a flat conductor having a shorter width than the conductor patterns 26a, 26b, and 26c instead of the wires 26d and 26e to connect the conductor patterns 26a and 26c, and the conductor patterns 26b and 26c. In this case, the conductive portion 25 uses a flat conductor having a shorter width than the conductor patterns 25a, 25b, and 25c instead of the wires 25d and 25e to connect the conductor patterns 25a and 25c, and the conductor patterns 25b and 25c. A conductor having a shorter width has a higher inductance than a conductor having a longer width. The conductor connecting conductor pattern 25a and conductor pattern 25c and the conductor connecting conductor pattern 26a and conductor pattern 26c are arranged side by side in the Z direction, for example, with the distance between these two conductors being approximately 0.1 mm and no more than 2 mm at most. The conductor connecting conductor pattern 25b and conductor pattern 25c and the conductor connecting conductor pattern 26b and conductor pattern 26c are arranged side by side in the Z direction, for example, with the distance between these two conductors being approximately 0.1 mm and no more than 2 mm at most.

[0076] As with the second embodiment, the configuration according to the above modification can suppress delays in control signals input from the outside, and can also suppress oscillation of transistors.

[0077] In addition to the above-mentioned modified examples, various modifications are possible for the configuration corresponding to the wires 26d and 26e in the second embodiment. As long as the configuration corresponding to the wires 26d and 26e in the second embodiment and the configuration corresponding to the wires 25d and 25e in the second embodiment are arranged side by side and cancel each other's inductance, the shape is not important.

[0078] 3.Other Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0079] 1, 1A... Semiconductor device 10...Substrate 21, 22, 23, 24, 24A, 25...Conductive part 21a, 21b, 22a, 23a, 24a, 25a, 25b, 25c, 25i, 25j, 26a, 26b, 26c... Conductor patterns 21c, 21d, 21e, 23b, 23c, 24b, 24c, 25d, 25e, 25f, 25g, 26d, 26e, 26f, 26g…Wire 21f, 22b, 23d, 23e, 24d, 24e, 24f, 25h, 26h, 26i, 26j...Terminal parts HTr (31a, 31b), LTr (32a, 32b)...Transistors 40…Heat sink 100…Sealing resin P, N, AC, HS, HG, LS, LG...terminals

Claims

1. A substrate; a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion provided on the substrate; a first transistor having a drain electrically connected to the first conductive portion and a source electrically connected to the second conductive portion; a second transistor and a third transistor, each having a drain electrically connected to the second conductive portion, a source electrically connected to the third conductive portion, and a gate electrically connected to the fourth conductive portion; Equipped with the second conductive portion includes a first portion in contact with the second transistor and a second portion in contact with the third transistor and located on an opposite side of the first conductive portion to the first portion, the third conductive portion includes a third portion to which a source of the second transistor is connected and which is located on the opposite side of the first conductive portion with respect to the first portion, a fourth portion to which a source of the third transistor is connected and which is located on the opposite side of the first conductive portion with respect to the second portion, and a fifth portion electrically connecting the third portion and the fourth portion, the fourth conductive portion includes a sixth portion to which a gate of the second transistor is connected and which is located on the opposite side of the first conductive portion with respect to the third portion, a seventh portion to which a gate of the third transistor is connected and which is located on the opposite side of the first conductive portion with respect to the fourth portion, and an eighth portion electrically connecting the sixth portion and the seventh portion, The shape of the eighth portion is different from the shape of the sixth portion and the shape of the seventh portion. Semiconductor device.

2. the sixth portion and the seventh portion of the fourth conductive portion include a conductor pattern, the eighth portion of the fourth conductive portion includes a wire; The semiconductor device according to claim 1 .

3. the wire included in the eighth portion of the fourth conductive portion is provided so as not to straddle any of the conductor patterns provided on the substrate; The semiconductor device according to claim 2 .

4. the sixth portion, the seventh portion, and the eighth portion of the fourth conductive portion are continuous conductor patterns, the eighth portion of the fourth conductive portion has a meandering portion; The semiconductor device according to claim 1 .

5. the sixth portion, the seventh portion, and the eighth portion of the fourth conductive portion are continuous conductor patterns, a width of the eighth portion of the fourth conductive portion is shorter than a width of the sixth portion and a width of the seventh portion; The semiconductor device according to claim 1 .

6. The shape of the fifth portion of the third conductive portion is different from the shape of the third portion and the shape of the fourth portion. The semiconductor device according to claim 1 .

7. the third portion and the fourth portion of the third conductive portion, and the sixth portion and the seventh portion of the fourth conductive portion include conductor patterns, the fifth portion of the third conductive portion and the eighth portion of the fourth conductive portion include wires. The semiconductor device according to claim 6.

8. the wires included in the fifth portion of the third conductive portion and the eighth portion of the fourth conductive portion are provided so as not to straddle any of the conductor patterns provided on the substrate; The semiconductor device according to claim 7.

9. the third portion, the fourth portion, and the fifth portion of the third conductive portion are continuous conductor patterns, the sixth portion, the seventh portion, and the eighth portion of the fourth conductive portion are continuous conductor patterns, each of the fifth portion of the third conductive portion and the eighth portion of the fourth conductive portion has a meandering portion; The semiconductor device according to claim 6.

10. the third portion, the fourth portion, and the fifth portion of the third conductive portion are continuous conductor patterns, the sixth portion, the seventh portion, and the eighth portion of the fourth conductive portion are continuous conductor patterns, a width of the fifth portion of the third conductive portion is shorter than a width of each of the third portion and the fourth portion of the third conductive portion; a width of the eighth portion of the fourth conductive portion is shorter than a width of each of the sixth portion and the seventh portion of the fourth conductive portion; The semiconductor device according to claim 6.

11. The fifth portion of the third conductive portion and the eighth portion of the fourth conductive portion are spaced apart from each other and are arranged side by side with an interval of 2 mm or less. The semiconductor device according to claim 6 .

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