Photodetector, electronic device, and method for manufacturing photodetector

Abstract

To provide a photodetector capable of reducing the chip area.SOLUTION: A photodetector has a semiconductor layer, a wiring layer, a terminal pad, and an element. The semiconductor layer has a photoelectric conversion section, with one side being a light input surface and the other side being an element formation surface. The wiring layer is stacked on the element formation surface of the semiconductor layer. The terminal pad is at least partially located in the semiconductor layer and is connected to the metal wiring in the wiring layer. The element is placed between the terminal pad and the wiring layer.SELECTED DRAWING: Figure 7B

Description

[Technical field]

[0001] The technology according to the present disclosure (the present technology) relates to a light detection device, an electronic device including the light detection device, and a method for manufacturing the light detection device. [Background technology]

[0002] In a solid-state imaging device, a certain number of protective elements are usually arranged in correspondence with each terminal pad within a chip to protect the semiconductor element from ESD (Electrostatic Discharge), PID (Process Induced Damage), etc. Patent Document 1 discloses a structure in which the emitter region of a protective transistor is electrically connected under a terminal pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 10-335627 A Summary of the Invention [Problem to be solved by the invention]

[0004] In solid-state imaging devices, it is desirable to reduce the chip size, but since a certain number of protection elements are required within a chip, the chip area increases.

[0005] The present disclosure has been made in consideration of the above circumstances, and has an object to provide a photodetector, an electronic device, and a method for manufacturing a photodetector that are capable of reducing the chip area. [Means for solving the problem]

[0006] One aspect of the present disclosure is a photodetector comprising: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad having at least a portion located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

[0007] Another aspect of the present disclosure is a photodetector comprising: a semiconductor layer having a photoelectric conversion portion, one surface being a light incident surface and the other surface being an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein an element is positioned at a formation position of the pad opening before the pad opening is formed.

[0008] Another aspect of the present disclosure is an electronic device including a photodetector including: a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad having at least a portion located in the semiconductor layer and connected to metal wiring of the wiring layer; and an element disposed between the terminal pad and the wiring layer.

[0009] Furthermore, another aspect of the present disclosure is an electronic device comprising: a semiconductor layer having a photoelectric conversion portion, one surface being a light incident surface and the other surface being an element formation surface; a wiring layer stacked on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, the electronic device comprising a photodetector that positions an element at a formation position of the pad opening before the pad opening is formed.

[0010] Another aspect of the present disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface, and laminating a wiring layer on the element formation surface of the semiconductor layer; forming a terminal pad, the upper surface of which is exposed to the outside, within the semiconductor layer; and connecting the lower surface of the terminal pad to the metal wiring of the wiring layer by a via so that an element to be placed in the semiconductor layer is located between the lower surface of the terminal pad and the wiring layer.

[0011] Furthermore, another aspect of the present disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion unit, one surface of which is a light incident surface and the other surface of which is an element formation surface, and laminating a wiring layer on the element formation surface of a semiconductor layer; forming a terminal pad connected to metal wiring of the wiring layer on the wiring layer side of the element formation surface of the semiconductor layer; and forming a pad opening that extends from the light incident surface of the semiconductor layer to the terminal pad and exposes the terminal pad from the light incident surface, wherein an element is disposed at a formation position of the pad opening before forming the pad opening. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a planar layout diagram illustrating a schematic configuration example of a solid-state imaging device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present disclosure. [Diagram 3] 2 is an equivalent circuit diagram of a pixel unit of the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 4A] 1 is a plan view (part 1) illustrating an example of a schematic structure of a solid-state imaging device according to a comparative example of the first embodiment of the present disclosure. [Figure 4B] 1 is a second plan view illustrating an example of a schematic structure of a solid-state imaging device according to a comparative example of the first embodiment of the present disclosure. FIG. [Figure 5A] 4B is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device taken along line AA' shown in FIG. 4A. [Figure 5B] 4C is a partial cross-sectional view showing an example of a schematic structure of the solid-state imaging device taken along line AA' shown in FIG. 4B. [Figure 6A] FIG. 1 is a plan view (part 1) illustrating an example of a schematic structure of a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 6B] 2 is a plan view (part 2) illustrating an example of a schematic structure of the solid-state imaging device according to the first embodiment of the present disclosure. FIG. [Figure 7A] 6B is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device taken along line AA' shown in FIG. 6A. [Figure 7B] 6C is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device taken along line AA' shown in FIG. 6B. [Figure 8A] 1A to 1C are cross-sectional views (part 1) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 8B] 5A to 5C are cross-sectional views (part 2) illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 8C] 5A to 5C are cross-sectional views (part 3) illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 8D] 4A to 4C are cross-sectional views illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure (part 4). [Figure 8E] 5A to 5C are cross-sectional views illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure (part 5). [Figure 8F] 6 is a cross-sectional view (part 6) illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 8G] 7A to 7C are cross-sectional views illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 8H] 8 is a cross-sectional view (part 8) illustrating a process procedure of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 9A] 11 is a plan view (part 1) illustrating an example of a schematic structure of a solid-state imaging device according to a second embodiment of the present disclosure viewed from an element formation surface. FIG. [Figure 9B] 13 is a plan view (part 2) illustrating an example of a schematic structure of a solid-state imaging device according to a second embodiment of the present disclosure viewed from an element formation surface. FIG. [Figure 10A] 9B is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device taken along line BB' shown in FIG. 9A. [Figure 10B] 9C is a partial cross-sectional view showing an example of a schematic structure of the solid-state imaging device taken along line BB' shown in FIG. 9B. [Figure 11A] 6A to 6C are cross-sectional views (part 1) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 11B] 8A to 8C are cross-sectional views (part 2) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 11C] 10A to 10C are cross-sectional views (part 3) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 11D] 11A to 11C are cross-sectional views (part 4) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 11E] 13A to 13C are cross-sectional views (part 5) illustrating a process procedure of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 12] 11 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to a third embodiment of the present disclosure. FIG. [Figure 13A] 11 is a partial cross-sectional view (part 1) illustrating an example of a schematic structure of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. [Figure 13B] 13 is a partial cross-sectional view (part 2) illustrating an example of a schematic structure of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. [Figure 14A] 13 is a partial cross-sectional view (part 1) illustrating an example of a schematic structure of a solid-state imaging device according to a fifth embodiment of the present disclosure. FIG. [Figure 14B] 13 is a partial cross-sectional view (part 2) illustrating an example of a schematic structure of a solid-state imaging device according to a fifth embodiment of the present disclosure. FIG. [Figure 15] 13 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to a sixth embodiment of the present disclosure. FIG. [Figure 16] 13 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to a seventh embodiment of the present disclosure. FIG. [Figure 17] 13 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device according to an eighth embodiment of the present disclosure. FIG. [Figure 18] 1 is a block diagram showing an example configuration of an imaging system as an electronic device to which the present technology is applied. [Figure 19] 1 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile object control system to which the technology according to the present disclosure can be applied. [Figure 20] 20 is a diagram showing an example of the installation position of the imaging unit shown in FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are given the same or similar reference numerals, and duplicated descriptions are omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc. differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0014] In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type that is different from the "first conductivity type." In addition, "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without "+" or "-". However, even if the semiconductor regions have the same "n" and "n" attached, it does not mean that the impurity density of each semiconductor region is strictly the same.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical ideas of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read. The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0016] <First embodiment> In this embodiment, an example of applying the present technology to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described. The solid-state imaging device is an example of a photodetection device. The photodetection device includes not only solid-state imaging devices but also devices that only detect light, such as distance measuring devices. (Overall configuration of solid-state imaging device) First, the overall configuration of the solid-state imaging device 1A will be described. 1, a solid-state imaging device 1A according to an embodiment of the present technology is mainly configured with a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. In other words, the solid-state imaging device 1A is mounted on the semiconductor chip 2. This solid-state imaging device 1A takes in image light from a subject via an optical lens (not shown), converts the amount of incident light imaged on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted has, in a two-dimensional plane including an X direction and a Y direction which are perpendicular to each other, a rectangular pixel region 2A provided in the center, and a peripheral region 2B arranged outside the pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, an optical lens. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other on the two-dimensional plane.

[0019] 1, a plurality of terminal pads 14 are arranged in the peripheral region 2B. The plurality of terminal pads 14 are arranged, for example, along four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of terminal pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] <Logic circuit> 2, the semiconductor chip 2 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 outputs an output voltage (Vout) for each pixel 3 to the outside. The logic circuit 13 is configured with a CMOS (Complementary MOS) circuit including, as field effect transistors, for example, a p-channel conductivity type (first conductivity type) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and an n-channel conductivity type (second conductivity type) MOSFET.

[0021] The vertical drive circuit 4 is formed of, for example, a shift register. The vertical drive circuit 4 sequentially selects a desired pixel drive line 10, supplies a pulse for driving the pixel 3 to the selected pixel drive line 10, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel area 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion element of each pixel 3 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 11.

[0022] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion for removing fixed pattern noise specific to each pixel.

[0023] The horizontal drive circuit 6 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5 to select each of the column signal processing circuits 5 in turn, and causes each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to a horizontal signal line 12.

[0024] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signal. As the signal processing, for example, buffering, black level adjustment, column variation correction, various digital signal processing, etc. can be used.

[0025] The control circuit 8 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0026] <Pixels> 3 is an equivalent circuit diagram showing an example of the configuration of the pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) the signal charge photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge according to the amount of received light. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0028] A drain region of the transfer transistor TR is electrically connected to the charge storage region FD. A gate electrode of the transfer transistor TR is electrically connected to a transfer transistor driving line of the pixel driving lines 10 (see FIG. 2). The charge holding region FD temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0029] The readout circuit 15 reads out the signal charge stored in the charge holding region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are configured as field effect transistors, for example, MOSFETs with a silicon oxide (SiO2) film as a gate insulating film. These transistors may be MISFETs (Metal Insulator Semiconductor FETs) with a silicon nitride (Si3N4) film or a laminated film such as a silicon nitride film and a silicon oxide film as a gate insulating film.

[0030] The amplifier transistor AMP has a source region electrically connected to the drain region of the selection transistor SEL, and a drain region electrically connected to the power supply line Vdd1. The gate electrode of the amplification transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0031] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain region electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor driving line of the pixel driving lines 10 shown in FIG.

[0032] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplification transistor AMP, and a drain region electrically connected to the power supply line Vdd2.

[0033] When the transfer transistor TR is turned on, it transfers the signal charge generated in the photoelectric conversion element PD to the charge holding region FD. When the reset transistor RST is turned on, it resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd2. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 15.

[0034] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of the signal charge held in the charge holding region FD. The amplification transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion element PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the charge holding region FD, and outputs a pixel signal corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0035] <Specific configuration of solid-state imaging device> <Comparative Example> 4A and 4B are plan views showing an example of a schematic structure of a solid-state imaging device B1 according to a comparative example of the first embodiment of the present disclosure, and Fig. 5A and Fig. 5B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device B1 taken along line A-A' shown in Fig. 4A and Fig. 4B.

[0036] As shown in FIG. 4A, the solid-state imaging device B1 includes a semiconductor chip B2. The semiconductor chip B2 is configured with a single crystal silicon substrate of a first conductivity type, for example, p type. The semiconductor chip B2 includes a well region B21 of a second conductivity type, for example, n type, and a well region B22 of a first conductivity type, for example, p type. Protection diodes B31 to B33 are disposed in the p-type well region B22. A power supply terminal B34 for applying a power supply VDD to the protection diodes B31 to B33 is provided in the n-type well region B21. Furthermore, the semiconductor chip B2 is provided with a terminal B35 for supplying a reference potential.

[0037] 4B, a terminal pad B14 is provided in an area adjacent to the protection diodes B31 to B33 of the semiconductor chip B2. The upper surface of the terminal pad B14 is exposed through an opening B41.

[0038] As shown in FIG. 5A, the semiconductor chip B2 includes a semiconductor layer B200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer B300 superimposed on the first surface S1 of the semiconductor layer B200, and a second wiring layer B400 superimposed on a third surface S3, which is the surface of the first wiring layer B300 opposite to the surface of the semiconductor layer B200 side. Such a laminated structure can be realized, for example, by stacking the first wiring layer B300 on the first surface S1 of the semiconductor layer B200, and superimposing and bonding the second wiring layer B400 on the third surface S3 of the first wiring layer B300. In addition, the second surface S2, which is one surface of the semiconductor layer B200, is sometimes called a light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer B200, is sometimes called an element forming surface or front surface.

[0039] The semiconductor chip B2 is provided with an element isolation portion B210 on the first surface S1 side. The element isolation portion B210 is a region that isolates each element including the protection diodes B31 to B33. In the first wiring layer B300, for example, a metal layer B310 connected to the anode of the protection diode B32, a metal layer B320 connected to the cathode of the protection diode B32, a metal layer B330 connected to a power supply terminal B34, and a metal layer B340 connected to a terminal B35 are formed.

[0040] 5B, the terminal pad B14 is provided in an area adjacent to the protection diodes B31 to B33 of the semiconductor chip B2. The terminal pad B14 is exposed to the outside from the second surface S2 of the semiconductor chip B2 through an opening B41. Incidentally, in the solid-state imaging device B1 of the comparative example, an area is required in the semiconductor chip B2 for arranging a certain number of protection diodes B31 to B33, which increases the chip area.

[0041] <Means for realizing the first embodiment> 6A and 6B are plan views showing an example of a schematic structure of a solid-state imaging device 1A according to a first embodiment of the present disclosure, and Fig. 7A and 7B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device 1A taken along line A-A' shown in Fig. 6A and Fig. 6B.

[0042] As shown in FIG. 6A, the semiconductor chip 2 is composed of a single crystal silicon substrate of a first conductivity type, for example, p type. The semiconductor chip 2 has a well region 21 of a second conductivity type, for example, n type, and a well region 22 of a first conductivity type, for example, p type. Protection diodes 31 to 33 are arranged in the p type well region 22. A power supply terminal 34 is provided in the n type well region 21 for applying a power supply voltage VDD to the protection diodes 31 to 33. Furthermore, the semiconductor chip 2 is provided with a terminal 35 for supplying a reference potential. Note that, in addition to the protection diodes 31 to 33, elements such as transistors that protect the transistors in the semiconductor chip 2 from ESD and PID may be used. The semiconductor chip 2 is provided with an element isolation portion 210 on the first surface S1 side.

[0043] 6B, the terminal pad 14 is provided in an area where the protection diodes 31 to 33 of the semiconductor chip 2 are provided. The upper surface of the terminal pad 14 is exposed through an opening 41 (an example of a pad opening).

[0044] As shown in FIG. 7A, the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 superimposed on a third surface S3, which is the surface of the first wiring layer 300 opposite to the surface on the semiconductor layer 200 side. Such a laminated structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200, and superimposing and bonding the second wiring layer 400 on the third surface S3 of the first wiring layer 300. In addition, the second surface S2, which is one surface of the semiconductor layer 200, is sometimes called a light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer 200, is sometimes called an element forming surface or front surface. The solid-state imaging device 1A is a back-illuminated imaging device (an example of a photodetector) in which the first surface S1 is the front surface and the second surface S2 is the back surface.

[0045] The semiconductor chip 2 has an element isolation section 210 on the first surface S1 side. The element isolation section 210 is a region that isolates each element including the protection diodes 31 to 33. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, a metal layer 330 connected to a power supply terminal 34, and a metal layer 340 connected to a terminal 35 are formed.

[0046] (Terminal Pad) As shown in FIG. 7B, the terminal pad 14 is embedded in the semiconductor layer 200, that is, is located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and has an upper surface 14a, a lower surface 14b opposite to the upper surface 14a, and a via 14c. The upper surface 14a is an exposed surface exposed to the outside through the opening 41. The terminal pad 14 is an input / output terminal used when electrically connecting the solid-state imaging device 1A to an external device. Therefore, the terminal pad 14 is exposed to the outside. The lower surface 14b of the terminal pad 14 is connected to the via 14c. The terminal pad 14 is made of a conductive material such as aluminum.

[0047] A plurality of vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 to a metal layer 352 described later. One end of the via 14c penetrates the semiconductor layer 200 and is connected to the lower surface 14b of the terminal pad 14. The other end of the via 14c penetrates the n-type well region 21 and the p-type well region 22 constituting the protection diodes 31 to 33 and the element isolation portion 210 in the thickness direction of the semiconductor layer 200 and extends into the first wiring layer 300. Then, the via 14c is connected to a metal layer 352 in the first wiring layer 300. Here, the metal layer 352 to which the other end of the via 14c is connected is called a metal layer 352a in order to distinguish it from the other metal layers 352. For this reason, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0048] (First wiring layer) 7B, the first wiring layer 300 further includes an interlayer insulating film 351, a metal layer 352 (an example of metal wiring), a first connection pad 353, and a via 354. The metal layer 352 and the first connection pad 353 are stacked with the interlayer insulating film 351 interposed therebetween as shown in the figure. The via 354 connects the metal layers 352 to each other and connects the metal layer 352 to the first connection pad 353.

[0049] (Second wiring layer) As shown in FIG. 7B, the second wiring layer 400 includes an interlayer insulating film 411, a metal layer 412, a second connection pad 413, and a via 414. The metal layer 412 and the second connection pad 413 are laminated with the interlayer insulating film 411 interposed therebetween as shown in the figure. The via 414 connects the metal layers 412 to each other and between the metal layer 412 and the second connection pad 413. The second connection pad 413 is joined to the first connection pad 353. As a result, the terminal pad 14 is electrically connected to the metal layer 412 of the second wiring layer 400. As shown in FIG. 7B, the terminal pad 14, the first connection pad 353, and the second connection pad 413 overlap in the thickness direction of the semiconductor chip 2. The second wiring layer 400 may include a logic substrate on which the logic circuit 13 is formed. The logic substrate includes the logic circuit 13, such as the control circuit 8 that controls the operation of each pixel 3, and the like.

[0050] <Method of Manufacturing Solid-State Imaging Device> Hereinafter, a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present disclosure will be described with reference to Figs. 8A to 8H. Figs. 8A to 8H are cross-sectional views showing the steps of the method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present disclosure. The solid-state imaging device 1A is manufactured using various types of equipment, such as a film forming apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses are collectively referred to as manufacturing apparatuses.

[0051] 8A, a substrate 51 is prepared in which a semiconductor layer 200, a first wiring layer 300, and a second wiring layer 400 are laminated in that order. An n-type well region 21, a p-type well region 22, an element isolation portion 210, and the like are already formed in the semiconductor layer 200. Then, a first connection pad 353 and a second connection pad 413 are bonded to each other.

[0052] Next, as shown in Fig. 8B, the manufacturing equipment forms opening 52 by etching on second surface S2 of semiconductor layer 200. Next, as shown in Fig. 8C, the manufacturing equipment forms openings 53 and 54 by etching from opening 52 to element isolation portion 210. Then, as shown in Fig. 8D, the manufacturing equipment fills openings 52, 53, and 54 with oxide film 55.

[0053] 8E, the manufacturing equipment etches the oxide film 55 to form an opening 56 for forming the terminal pad 14 and the via 14c therefor. At this time, the opening 56 penetrates the element isolation portion 210 and reaches the metal layer 320 of the first wiring layer 300. Next, as shown in FIG. 8F, the manufacturing equipment patterns, for example, aluminum in the opening 56 to form the terminal pad 14.

[0054] Next, as shown in Fig. 8G, the manufacturing equipment fills in the portions not filled with aluminum with oxide film 57. Next, as shown in Fig. 8H, the manufacturing equipment etches oxide film 57 to form openings 41 that expose upper surfaces 14a of terminal pads 14 to the outside.

[0055] <Effects of the First Embodiment> As described above, according to the first embodiment, by arranging the protection diodes 31-33 between the lower surface 14b of the terminal pad 14 and the first wiring layer 300, it is not necessary to secure an area for a certain number of protection diodes 31-33 in addition to the terminal pad 14 in the semiconductor chip 2, and this makes it possible to reduce the chip area. Furthermore, by providing the terminal pad 14 in the semiconductor layer 200, wire bonding can be easily performed. Note that the terminal pad 14 may have a structure in which a part of it is embedded in the semiconductor layer 200 and another part of it protrudes above the semiconductor layer 200.

[0056] <Second embodiment> 9A and 9B are plan views showing an example of a schematic structure of a solid-state imaging device 1B according to a second embodiment of the present disclosure, as viewed from an element formation surface. Also, FIGS. 10A and 10B are partial cross-sectional views showing an example of a schematic structure of the solid-state imaging device 1B cut along line B-B' shown in FIGS. 9A and 9B. In FIGS. 9A and 9B, the same parts as those in FIGS. 6A and 6B are given the same reference numerals, and detailed descriptions thereof are omitted. Also, in FIGS. 10A and 10B, the same parts as those in FIGS. 7A and 7B are given the same reference numerals, and detailed descriptions thereof are omitted.

[0057] 9A, the semiconductor chip 60 of the solid-state imaging device 1B is composed of a single crystal silicon substrate of a second conductivity type, for example, n-type. The semiconductor chip 60 has a well region 61 of a first conductivity type, for example, p-type. The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply VDD to the protection diodes 31 to 33. The cathodes of the protection diodes 31 to 33 are surrounded by a plurality of vias 354 of a first wiring layer 300 described later.

[0058] 9B, a terminal pad 71 is provided in an area where the protection diodes 31 to 33 are provided on the semiconductor chip 60. An upper surface 71a of the terminal pad 71 is exposed through an opening 72 (an example of a pad opening).

[0059] As shown in FIG. 10A, the semiconductor chip 60 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 superimposed on a third surface S3, which is the surface of the first wiring layer 300 opposite to the surface on the semiconductor layer 200 side. Such a laminated structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200, and superimposing and bonding the second wiring layer 400 on the third surface S3 of the first wiring layer 300. In addition, the second surface S2, which is one surface of the semiconductor layer 200, is sometimes called a light incident surface or back surface, and the first surface S1, which is the other surface of the semiconductor layer 200, is sometimes called an element forming surface or front surface.

[0060] An element isolation portion 210 is provided on the first surface S1 side of the semiconductor chip 60. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed.

[0061] The first wiring layer 300 further includes an interlayer insulating film 351, a metal layer 352 (an example of a metal wiring), and a via 354. As shown in the figure, the metal layer 352 is stacked with the interlayer insulating film 351 interposed therebetween. The via 354 connects the metal layers 352 to each other.

[0062] The second wiring layer 400 includes a terminal pad 71, an interlayer insulating film 411, a metal layer 412, and a via 414. The terminal pad 71 and the metal layer 412 are laminated with the interlayer insulating film 411 interposed therebetween as shown in the figure. The via 414 connects the metal layers 412 to each other and between the metal layer 412 and the terminal pad 71. This electrically connects the terminal pad 71 to the metal layer 412 of the second wiring layer 400. The second wiring layer 400 may include a logic substrate on which a logic circuit is formed. The logic substrate includes, for example, a pixel control circuit that controls the operation of each pixel 3, a front-end circuit that realizes quenching and recharging of each pixel 3, and the like.

[0063] As shown in FIG. 10B, the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through an opening 72. The terminal pad 71 is an input / output terminal used when electrically connecting the solid-state imaging device 1B to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to a via 414. The via 414 electrically connects the terminal pad 71 and the metal layer 412.

[0064] 10B, the opening 72 is formed from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400. The protection diodes 31 to 33 are disposed at the positions where the openings 72 are formed. After the openings 72 are formed, the protection diodes 31 to 33 disappear.

[0065] <Method of Manufacturing Solid-State Imaging Device> Hereinafter, a method for manufacturing the solid-state imaging device 1B according to the second embodiment of the present disclosure will be described with reference to Fig. 11A to Fig. 11E. Fig. 11A to Fig. 11E are cross-sectional views showing the steps of the method for manufacturing the solid-state imaging device 1B according to the second embodiment of the present disclosure. The solid-state imaging device 1B is manufactured using various types of equipment, such as a film forming apparatus (including a CVD (Chemical Vapor Deposition) apparatus and a sputtering apparatus), an ion implantation apparatus, a heat treatment apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, and a bonding apparatus. Hereinafter, these apparatuses are collectively referred to as manufacturing apparatuses.

[0066] First, as shown in Fig. 11A, a semiconductor chip 60 including only a semiconductor layer 200 is prepared. Next, as shown in Fig. 11B, a manufacturing device forms a p-type well region 61 and an element isolation portion 210 in the semiconductor layer 200 of the semiconductor chip 60.

[0067] Next, as shown in FIG. 11C, the manufacturing equipment stacks the first wiring layer 300 on the surface of the semiconductor layer 200 where the element isolation portion 210 is formed. At this time, an interlayer insulating film 351, a metal layer 352, and a via 354 are formed in the first wiring layer 300. In the process of forming the metal layer 352 and the via 354, a plasma charge generated may cause PID (Process Induced Damage) that causes a gate failure of a transistor. In order to protect the solid-state imaging device 1B from this PID, for example, a protection diode 32 is arranged in the arrangement region of the terminal pad 71, and, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed in the first wiring layer 300.

[0068] Next, as shown in FIG. 11D, the manufacturing equipment stacks a second wiring layer 400 on the upper surface of the support substrate 73, inverts the semiconductor chip 60 from the state shown in FIG. 11C, and bonds the first connection pad 353 of the first wiring layer 300 and the second connection pad 413 of the second wiring layer 400 together.

[0069] 11E, the manufacturing equipment forms an opening 72 from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400, and exposes the upper surface 71a of the terminal pad 71 to the outside. With the formation of this opening 72, the protection diodes 31 to 33 arranged in the semiconductor layer 200 disappear.

[0070] <Effects of the second embodiment> As described above, according to the second embodiment, when the terminal pad 71 is located on the second wiring layer 400, until the opening 72 is formed to expose the terminal pad 71 from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, the protection diodes 31-33 are arranged at the formation position of the opening 72. This makes it possible to protect other elements in the semiconductor layer 200 from ESD, PID, etc. until the opening 72 is formed. In addition, there is no need to secure an area for a certain number of protection diodes 31-33 in the semiconductor layer 200 separate from the terminal pad 71, thereby enabling a reduction in the chip area.

[0071] <Third embodiment> Fig. 12 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1C according to a third embodiment of the present disclosure, in which the same parts as those in Fig. 7B and Fig. 10A are denoted by the same reference numerals and detailed description thereof will be omitted.

[0072] The semiconductor chip 60 of the solid-state imaging device 1C is made of a single crystal silicon substrate of a second conductivity type, for example, n-type. The semiconductor chip 60 has a well region 61 of a first conductivity type, for example, p-type. The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply VDD to the protection diodes 31 to 33.

[0073] The terminal pad 14 is embedded in the semiconductor layer 200, that is, located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and has an upper surface 14a, a lower surface 14b opposite to the upper surface 14a, and a via 14c. The upper surface 14a is an exposed surface exposed to the outside through the opening 41. The terminal pad 14 is an input / output terminal used when electrically connecting the solid-state imaging device 1A to an external device. Therefore, the terminal pad 14 is exposed to the outside. The lower surface 14b of the terminal pad 14 is connected to the via 14c.

[0074] A plurality of vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 and the metal layer 352. One end of the via 14c penetrates the semiconductor layer 200 and is connected to the lower surface 14b of the terminal pad 14. The other end of the via 14c penetrates the n-type well region 21 and the p-type well region 22 constituting the protection diodes 31 to 33 and the element isolation portion 210 in the thickness direction of the semiconductor layer 200 and extends into the first wiring layer 300. Then, the via 14c is connected to a metal layer 352 in the first wiring layer 300. Here, the metal layer 352 to which the other end of the via 14c is connected is called a metal layer 352a in order to distinguish it from the other metal layers 352. For this reason, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0075] <Effects of the Third Embodiment> As described above, the third embodiment also provides the same effects as the first embodiment.

[0076] <Fourth embodiment> 13A and 13B are partial cross-sectional views showing an example of a schematic structure of a solid-state imaging device 1D according to a fourth embodiment of the present disclosure. In Fig. 13A and Fig. 13B, the same parts as those in Fig. 10A and Fig. 10B are denoted by the same reference numerals and detailed description thereof will be omitted.

[0077] 13A, the semiconductor chip 2 of the solid-state imaging device 1D is composed of a single crystal silicon substrate of a first conductivity type, for example, p type. The semiconductor chip 2 has a well region 21 of a second conductivity type, for example, n type, and a well region 22 of the first conductivity type, for example, p type. Protection diodes 31 to 33 are arranged in the p-type well region 22. A power supply terminal 34 is provided in the n-type well region 21 for applying a power supply VDD to the protection diodes 31 to 33. Furthermore, the semiconductor chip 2 is provided with a terminal 35 for supplying a reference potential.

[0078] In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, a metal layer 330 connected to the power supply terminal 34, and a metal layer 340 connected to the terminal 35 are formed.

[0079] As shown in FIG. 13B, the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through an opening 72. The terminal pad 71 is an input / output terminal used when electrically connecting the solid-state imaging device 1B to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to a via 414. The via 414 electrically connects the terminal pad 71 and the metal layer 412.

[0080] 13B, the opening 72 is formed from the second surface S2 of the semiconductor layer 200, i.e., the light incident surface, to the terminal pad 71 of the second wiring layer 400. The protection diodes 31 to 33 are disposed at the positions where the openings 72 are formed. After the openings 72 are formed, the protection diodes 31 to 33 disappear.

[0081] <Effects of the Fourth Embodiment> As described above, the fourth embodiment also provides the same effects as the second embodiment.

[0082] <Fifth embodiment> 14A and 14B are partial cross-sectional views showing an example of a schematic structure of a solid-state imaging device 1E according to a fifth embodiment of the present disclosure. In Fig. 14A and Fig. 14B, the same parts as those in Fig. 7A and Fig. 7B are denoted by the same reference numerals and detailed description thereof will be omitted.

[0083] As shown in FIG. 14A, the semiconductor chip 2 of the solid-state imaging device 1E includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, and a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200.

[0084] As shown in FIG. 14B, the terminal pad 14 is embedded in the semiconductor layer 200, i.e., is located closer to the first surface S1 than the second surface S2 of the semiconductor layer 200, and has an upper surface 14a, a lower surface 14b which is the surface opposite to the upper surface 14a, and a via 14c.

[0085] <Effects of the Fifth Embodiment> As described above, the fifth embodiment also provides the same advantageous effects as the first embodiment.

[0086] Sixth embodiment Fig. 15 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1F according to a sixth embodiment of the present disclosure. In Fig. 15, the same parts as those in Fig. 7B above are denoted by the same reference numerals and detailed description thereof will be omitted.

[0087] 15, the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located opposite to each other, a first wiring layer 300 superimposed on the first surface S1 of the semiconductor layer 200, a second wiring layer 400 superimposed on a third surface S3, which is the surface opposite to the surface of the first wiring layer 300 facing the semiconductor layer 200, and a third wiring layer 500 superimposed on a fourth surface S4, which is the surface opposite to the third surface S3 of the second wiring layer 400. Such a laminated structure can be realized, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200, superimposing and bonding the second wiring layer 400 to the third surface S3 of the first wiring layer 300, and superimposing and bonding the third wiring layer 500 to the fourth surface S4 of the second wiring layer 400.

[0088] (Third wiring layer) As shown in FIG. 15, the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, and a via 513. The metal layer 512 is laminated with the interlayer insulating film 511 interposed therebetween. The via 513 connects the metal layers 512 to each other. The metal layer 512 is joined to the metal layer 412 of the second wiring layer 400 by a through via 81 made of a conductive material. This electrically connects the terminal pad 14 to the metal layer 512 of the third wiring layer 500. The terminal pad 14, the first connection pad 353, and the second connection pad 413 overlap in the thickness direction of the semiconductor chip 2, but the terminal pad 14 and the through via 81 do not overlap in the thickness direction of the semiconductor chip 2.

[0089] (First substrate) As shown in FIG. 15, the second wiring layer 400 has a first substrate 415. The first substrate 415 is, for example, a second-stage pixel substrate or a logic substrate on which a logic circuit such as the control circuit 8 is formed. The first substrate 415 is located on the fourth surface S4 side and is made of a semiconductor substrate of a first conductivity type, for example, a p-type. The first substrate 415 is provided with an element isolation section 416 that isolates a plurality of transistors and the like from other elements. Furthermore, the first substrate 415 is electrically connected to the metal layer 412 by a via 414.

[0090] (Second substrate) 15, the third wiring layer 500 has a second substrate 514 on which a logic circuit such as the column signal processing circuit 5 is formed. The second substrate 514 is located on the surface side opposite to the fourth surface, and is made of a semiconductor substrate of a first conductivity type, for example, a p-type. The second substrate 514 is provided with an element isolation section 515 that isolates a plurality of transistors from other elements. Furthermore, the second substrate 514 is electrically connected to the metal layer 512 by a via 513.

[0091] <Effects of the sixth embodiment> As described above, the sixth embodiment can provide the same effects as the first embodiment. Furthermore, according to the sixth embodiment, various circuits such as the column signal processing circuit 5 and the control circuit 8 constituting the logic circuit 13 can be arranged in the thickness direction of the semiconductor chip 2, so that the area of ​​the entire solid-state imaging device 1F can be reduced.

[0092] Seventh embodiment Fig. 16 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1G according to a seventh embodiment of the present disclosure. In Fig. 16, the same parts as those in Fig. 15 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0093] 16, the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, a via 513, and a third connection pad 516. The metal layer 512 and the third connection pad 516 are laminated with the interlayer insulating film 511 interposed therebetween as shown in the figure. The via 513 connects the metal layers 512 to each other and between the metal layer 512 and the third connection pad 516. The third connection pad 516 is joined to the second connection pad 413. As a result, the terminal pad 14 is electrically connected to the metal layer 512 of the third wiring layer 500.

[0094] The first substrate 415 is located on the third surface S3 side. The through via 81 joins the metal layer 352 of the first wiring layer 300 and the metal layer 412 of the second wiring layer 400. At this time, the through via 81 penetrates the first substrate 415.

[0095] <Effects of the Seventh Embodiment> As described above, the seventh embodiment also provides the same advantageous effects as the sixth embodiment.

[0096] <Eighth embodiment> Fig. 17 is a partial cross-sectional view showing an example of a schematic structure of a solid-state imaging device 1H according to an eighth embodiment of the present disclosure. In Fig. 17, the same parts as those in Figs. 13B and 15 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0097] 17, the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through an opening 72. The metal layer 512 of the third wiring layer 500 is joined to the metal layer 412 of the second wiring layer 400 by a through via 81 made of a conductive material. This electrically connects the terminal pad 71 to the metal layer 512 of the third wiring layer 500.

[0098] <Effects of the eighth embodiment> As described above, the eighth embodiment can provide the same effects as those of the second embodiment. Furthermore, according to the eighth embodiment, various circuits such as the column signal processing circuit 5 and the control circuit 8 constituting the logic circuit 13 can be arranged in the thickness direction of the semiconductor chip 2, so that the area of ​​the entire solid-state imaging device 1H can be reduced.

[0099] <Other embodiments> As described above, the present technology has been described by the first to eighth embodiments, but the descriptions and drawings forming part of this disclosure should not be understood as limiting the present technology. If the gist of the technical contents disclosed in the first to eighth embodiments is understood, it will be clear to those skilled in the art that various alternative embodiments, examples, and operation techniques can be included in the present technology. In addition, the configurations disclosed in the first to eighth embodiments can be appropriately combined within a range that does not cause contradictions. For example, the configurations disclosed in multiple different embodiments may be combined, and the configurations disclosed in multiple different modified examples of the same embodiment may be combined.

[0100] <Applications to electronic devices> The above-described solid-state imaging device can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions. FIG. 18 is a block diagram showing an example configuration of an imaging system as an electronic device to which the present technology is applied.

[0101] The imaging system 2201 shown in FIG. 18 is configured with an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as a solid-state imaging device, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and is capable of capturing still images and moving images.

[0102] The optical system 2202 is configured to have one or more lenses, and guides light from a subject (incident light) to the solid-state image sensor 2204 , forming an image on the light receiving surface of the solid-state image sensor 2204 . The shutter device 2203 is disposed between the optical system 2202 and the solid-state imaging element 2204 , and controls the light irradiation period and light blocking period for the solid-state imaging element 2204 under the control of a control circuit 2205 .

[0103] The solid-state imaging element 2204 is configured by a package including the above-mentioned solid-state imaging element. The solid-state imaging element 2204 accumulates signal charges for a certain period of time in response to light imaged on the light receiving surface via the optical system 2202 and the shutter device 2203. The signal charges accumulated in the solid-state imaging element 2204 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 2205.

[0104] The control circuit 2205 outputs drive signals that control the transfer operation of the solid-state imaging element 2204 and the shutter operation of the shutter device 2203 , thereby driving the solid-state imaging element 2204 and the shutter device 2203 .

[0105] The signal processing circuit 2206 performs various signal processing on the signal charges output from the solid-state imaging element 2204. An image (image data) obtained by performing the signal processing by the signal processing circuit 2206 is supplied to a monitor 2207 and displayed, or supplied to a memory 2208 and stored (recorded). In the imaging system 2201 configured in this manner, the solid-state imaging devices 1A to 1H can also be applied in place of the solid-state imaging element 2204 described above.

[0106] <Applications to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0107] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied. The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0108] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0109] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0110] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle, and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0111] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0112] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0113] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0114] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0115] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0116] The audio / image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 19, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0117] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031. In FIG. 20, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0118] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0119] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0120] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0121] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0122] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0123] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0124] The present disclosure can also be configured as follows. (1) a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad at least a part of which is located in the semiconductor layer and connected to a metal wiring of the wiring layer; An element disposed between the terminal pad and the wiring layer; A light detection device comprising: (2) The photodetector according to claim 1, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer. (3) The photodetector according to (1) above, wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is a front surface and the light incidence surface is a back surface. (4) The photodetector according to (1) above, wherein the terminal pad is located on the element formation surface side of the light incident surface of the semiconductor layer. (5) The light detection device according to (1) above, wherein the wiring layer is formed by stacking a plurality of layers. (6) The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; The photodetector according to (5) above, wherein the second wiring layer has a substrate on which a logic circuit is formed. (7) The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; a third wiring layer laminated on a surface of the second wiring layer opposite to a surface of the second wiring layer on the first wiring layer side; The photodetector device described in (5) above, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed. (8) a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to a metal wiring of the wiring layer; a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; A photodetection device, comprising: a first pad opening formed on the first substrate; a second pad opening formed on the first substrate; (9) The photodetector according to claim 8, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer. (10) The photodetector according to (8) above, wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface is a front surface and the light incidence surface is a back surface. (11) The light detection device according to (8) above, wherein the wiring layer is formed by stacking a plurality of layers. (12) The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; The photodetector according to (11) above, wherein the second wiring layer has a substrate on which a logic circuit is formed. (13) The photodetector according to (12) above, wherein the terminal pad is located on the second wiring layer. (14) The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; a third wiring layer laminated on a surface of the second wiring layer opposite to a surface of the second wiring layer on the first wiring layer side; The photodetector device described in (11) above, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed. (15) The photodetector according to claim 14, wherein the terminal pad is located on the second wiring layer. (16) a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad at least a part of which is located in the semiconductor layer and which is connected to a metal wiring of the wiring layer; an element disposed between the terminal pad and the wiring layer; (17) a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incidence surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to a metal wiring of the wiring layer; a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; An electronic device comprising a photodetector, the photodetector locating an element at a position where the pad opening is to be formed before the pad opening is formed. (18) A method for manufacturing a photodetector, comprising: preparing a semiconductor chip having a photoelectric conversion portion, one surface of a semiconductor layer being a light incident surface and the other surface being an element formation surface, and stacking a wiring layer on the element formation surface of the semiconductor layer; forming a terminal pad in the semiconductor layer that is connected to metal wiring of the wiring layer; and arranging an element between the terminal pad and the wiring layer. (19) A semiconductor chip is prepared by laminating a wiring layer on an element formation surface of a semiconductor layer having a photoelectric conversion unit, one surface of the semiconductor layer being a light incidence surface and the other surface being an element formation surface; forming a terminal pad connected to a metal wiring of the wiring layer on the wiring layer side of the element formation surface of the semiconductor layer; forming a pad opening extending from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; A method for manufacturing a photodetector, comprising the steps of: arranging an element at a position where the pad opening is to be formed before the pad opening is formed. [Explanation of symbols]

[0125] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, B1 Solid-state imaging device 2,60 Semiconductor chips 2A Pixel area 2B Peripheral Areas 3 pixels 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control Circuit 10 Pixel drive lines 11 Vertical signal line 12 Horizontal signal line 13 Logic Circuits 14,71 Terminal Pad 15 Readout circuit 14a,71a Top surface 14b,71b Bottom surface 14c Via 21, 22, 61 Well area 31, 32, 33 Protection diodes 34 Power terminal 35 Terminals 41, 52, 53, 54, 56, 72 Opening 51 Substrate 55,57 Oxide film 73 Support Substrate 81 Through Via 200 Semiconductor layer 210,416,515 Element isolation section 300 First wiring layer 310, 320, 330, 340, 352, 352a, 412, 512 Metal layer 351,411,511 Interlayer insulating film 353 First Connection Pad 354,414,513 via 400 Second wiring layer 413 Second Connection Pad 415 First Substrate 500 3rd wiring layer 514 Second Board 516 3rd Connection Pad 2201 Imaging System 2202 Optical system 2203 Shutter device 2204 Solid-state image sensor 2205 Control circuit 2206 Signal Processing Circuit 2207 Monitor 2208 Memory 12000 Vehicle Control System 12001 Communication Networks 12010 Drive system control unit 12020 Body control unit 12030 External information detection unit 12031 Imaging unit 12040 In-vehicle information detection unit 12041 Driver status detection unit 12050 Integrated Control Unit 12051 Microcomputer 12052 Audio / Video Output Unit 12061 Audio Speaker 12062 Display section 12063 Instrument Panel 12100 Vehicles 12101~12105 Imaging section 12111~12114 Imaging range

Claims

1. a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad at least a part of which is located in the semiconductor layer and which is connected to a metal wiring of the wiring layer; An element disposed between the terminal pad and the wiring layer; A light detection device comprising:

2. 2. The photodetector device according to claim 1, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer.

3. 2 . The photodetector according to claim 1 , wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface serves as a front surface and the light incidence surface serves as a back surface.

4. The photodetector according to claim 1 , wherein the terminal pad is located closer to an element formation surface than the light incident surface of the semiconductor layer.

5. The photodetector according to claim 1 , wherein the wiring layer is a multi-layered structure.

6. The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; The photodetector according to claim 5 , wherein the second wiring layer has a substrate on which a logic circuit is formed.

7. The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; a third wiring layer laminated on a surface of the second wiring layer opposite to a surface of the second wiring layer on the first wiring layer side; 6. The photodetector according to claim 5, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed.

8. a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on the wiring layer side of the element formation surface of the semiconductor layer and connected to a metal wiring of the wiring layer; a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; A photodetection device, comprising: a first pad opening formed on the first substrate; a second pad opening formed on the first substrate;

9. 9. The photodetector device according to claim 8, wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer.

10. 9. The photodetector according to claim 8, wherein the semiconductor layer is used in a back-illuminated photodetector in which the element formation surface serves as a front surface and the light incidence surface serves as a back surface.

11. The photodetector according to claim 8 , wherein the wiring layer is a multi-layered structure.

12. The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; The photodetector according to claim 11 , wherein the second wiring layer has a substrate on which a logic circuit is formed.

13. The photodetector device of claim 12 , wherein the terminal pad is located in the second wiring layer.

14. The wiring layers include a first wiring layer laminated on an element forming surface of the semiconductor layer; a second wiring layer laminated on a surface of the first wiring layer opposite to a surface of the first wiring layer on the semiconductor layer side; a third wiring layer laminated on a surface of the second wiring layer opposite to a surface of the second wiring layer on the first wiring layer side; 12. The photodetector device according to claim 11, wherein the second wiring layer has a first substrate on which a first logic circuit is formed, and the third wiring layer has a second substrate on which a second logic circuit is formed.

15. The photodetector device of claim 14 , wherein the terminal pad is located in the second wiring layer.

16. a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad at least a part of which is located in the semiconductor layer and which is connected to a metal wiring of the wiring layer; an element disposed between the terminal pad and the wiring layer;

17. a semiconductor layer having a photoelectric conversion portion, one surface of which is a light incident surface and the other surface of which is an element formation surface; a wiring layer laminated on the element formation surface of the semiconductor layer; a terminal pad located on a wiring layer side of the element formation surface of the semiconductor layer and connected to a metal wiring of the wiring layer; a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; An electronic device comprising a photodetector, the photodetector locating an element at a position where the pad opening is to be formed before the pad opening is formed.

18. A semiconductor chip is prepared by laminating a wiring layer on an element formation surface of a semiconductor layer having a photoelectric conversion unit, one surface of the semiconductor layer being a light incidence surface and the other surface being an element formation surface; forming a terminal pad in the semiconductor layer, the upper surface of which is exposed to the outside; connecting a lower surface of the terminal pad to a metal wiring of the wiring layer by a via so that an element disposed in the semiconductor layer is located between the lower surface of the terminal pad and the wiring layer; A method for manufacturing a light detection device comprising the steps of:

19. A semiconductor chip is prepared by laminating a wiring layer on an element formation surface of a semiconductor layer having a photoelectric conversion unit, one surface of the semiconductor layer being a light incidence surface and the other surface being an element formation surface; forming a terminal pad connected to a metal wiring of the wiring layer on a wiring layer side of the element formation surface of the semiconductor layer; forming a pad opening extending from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface; A method for manufacturing a photodetector, comprising the steps of: arranging an element at a position where the pad opening is to be formed before the pad opening is formed.

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