Transmission circuit, electronic control unit, and vehicle

Abstract

To improve an EMI characteristic of a differential transmission circuit in a transmission circuit, an electronic control unit, and a vehicle.SOLUTION: A transmission circuit (4) comprises: a first terminal (CANH); a second terminal (CANL); first current sources (Q1_1 to Q1_n) having a construction that an injection current is injected; second current sources (Q4_1 to Q4_n) having a construction that a sucking current is sucked; a first diode (D1) having a construction of preventing the current from flowing toward each first current source from the first terminal; a second diode (D2) having a construction of preventing the current from flowing toward the second terminal from each second current source; at least one of a first correction circuit (41) having a construction that a first correction current is injected to an anode of the first diode and a second correction circuit (42) having a construction that a second correction current is sucked from a cathode of the second diode; and adjustment circuits (R4, R5, ZD1, COMP1, COMP2, 43, and 44) that are constructed so that a value of correction current is adjusted on the basis of a common mode component.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The invention disclosed herein relates to a transmission circuit, an electronic control unit, and a vehicle. [Background technology]

[0002] Vehicles such as automobiles are equipped with many electronic control units (ECUs). For communication between the many ECUs, for example, LIN (Local Interconnect Network) communication, CAN (Controller Area Network) communication, CXPI (Clock Extension Peripheral Interface) communication, etc. are used (for example, see Patent Document 1).

[0003] CAN (Controller Area Network) communication is a differential signaling method with high noise resistance. A differential signal consisting of a first signal and a second signal can be decomposed into a common mode component and a differential mode component. The common mode component is the average of the first signal and the second signal, and the differential mode component is the difference between the first signal and the second signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 185782

[0005] [overview] When the symmetry between the first and second signals constituting the differential signal is lost, the common mode component fluctuates, and the fluctuation of the common mode component deteriorates the EMI (Electromagnetic Interference) characteristics.

[0006] The transmission circuit disclosed in the present specification comprises a first terminal, a second terminal, a first current source configured to source a source current, a second current source configured to sink a sink current, a first diode configured to prevent a current from flowing from the first terminal toward the first current source, a second diode configured to prevent a current from flowing from the second current source toward the second terminal, at least one of a first correction circuit configured to source a first correction current to an anode of the first diode and a second correction circuit configured to sink a second correction current from a cathode of the second diode, and an adjustment circuit configured to adjust a value of the correction current based on an average of a first voltage generated at the first terminal and a second voltage generated at the second terminal, wherein the transmission circuit comprises at least the first correction circuit and the correction current includes at least the first correction current, or comprises at least the second correction circuit and the correction current includes at least the second correction current.

[0007] The electronic control unit disclosed in this specification comprises a transmitting circuit having the above-described configuration, and a computer configured to send the transmission data to the transmitting circuit.

[0008] The vehicle disclosed in this specification includes a communication bus and a plurality of electronic control units of the above configuration connected to the communication bus. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an external view of a vehicle according to an embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a CAN communication system. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the ECU. [Figure 4] FIG. 4 is a diagram showing a transceiver circuit according to a reference example. [Diagram 5] FIG. 5 is a timing chart showing an ideal differential signal. [Figure 6]FIG. 6 is a timing chart showing an actual differential signal. [Figure 7] FIG. 7 is a diagram illustrating a transceiver circuit according to the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of the first correction circuit according to the first embodiment. [Figure 9] FIG. 9 is a timing chart showing an example of the first correction current. [Figure 10] FIG. 10 is a timing chart showing another example of the first correction current. [Figure 11] FIG. 11 is a diagram showing a transceiver circuit according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing a transceiver circuit according to the third embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of the first correction circuit according to the third embodiment. [Figure 14] FIG. 14 is a diagram showing a modification of the transceiver circuit according to the third embodiment.

[0010] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, a P-channel type MOSFET will be referred to as a PMOS transistor, and an N-channel type MOSFET will be referred to as an NMOS transistor.

[0011] In this specification, a constant voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0012] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0013] <Vehicle and CAN communication system> 1 is an external view of a vehicle X according to an embodiment. The vehicle X includes a plurality of ECUs 1 (not shown in FIG. 1). The vehicle X also includes a battery (not shown).

[0014] Fig. 2 is a schematic diagram of a CAN communication system provided in a vehicle X. The CAN communication system shown in Fig. 2 includes a plurality of ECUs 1, a first bus line BL1, a second bus line BL2, and resistors R101 and R102.

[0015] One end of a resistor R101 is connected to one end of a first bus line BL1, and one end of a resistor R102 is connected to the other end of the first bus line BL1. The other end of the resistor R101 is connected to one end of a second bus line BL2, and the other end of the resistor R102 is connected to the other end of the second bus line BL2. Each of the multiple ECUs 1 is connected to the first bus line BL1 and the second bus line BL2. A voltage VBAT output from a battery is supplied to each of the multiple ECUs 1. Each of the multiple ECUs 1 is connected to a ground potential. The multiple ECUs 1 use the voltage VBAT as a power supply voltage.

[0016] <ecu> 3 is a diagram showing an example of the configuration of the ECU 1. The ECU 1 of the example configuration shown in FIG.

[0017] A voltage VBAT is supplied to the terminal T1 from outside the ECU 1. The anode of the diode 5 is connected to the terminal T1. The cathode of the diode 5 is connected to the input terminal of the power supply circuit 2 and a first end of the capacitor 6.

[0018] The output terminal of the power supply circuit 2 is connected to the power supply voltage input terminal of the microcomputer 3, the terminal VCC of the transceiver circuit 4, and a first end of the capacitor 7. The output terminal of the power supply circuit 2 outputs a constant voltage.

[0019] The microcomputer 3 sends transmission data to a terminal TXD of the transceiver circuit 4, and receives reception data from a terminal RXD of the transceiver circuit 4. The transmission data and reception data are each a single signal.

[0020] The terminal CANH of the transceiver circuit 4 is connected to the terminal T2, and the terminal CANL of the transceiver circuit 4 is connected to the terminal T3. The terminal T2 is connected to the first bus line BL1 shown in FIG. 2, and the terminal T3 is connected to the second bus line BL2 shown in FIG.

[0021] The transceiver circuit 4 converts the transmission data into a differential signal (CAN signal) composed of a first signal SCANH (see FIG. 5 etc. described later) and a second signal SCANL (see FIG. 5 etc. described later) and outputs the data. The transceiver circuit 4 also converts the differential signal (CAN signal) composed of the first signal and the second signal into reception data and outputs the data. That is, the transceiver circuit 4 includes a transmission circuit that transmits the differential signal and a reception circuit that receives the differential signal. The first signal is transmitted by the first bus line BL1, and the second signal is transmitted by the second bus line BL2.

[0022] The ground terminal of the power supply circuit 2 is connected to the second end of the capacitor 6, the terminal T4, the terminal GND of the transceiver circuit 4, the ground terminal of the microcomputer 3, and the second end of the capacitor 7. The terminal T4 is connected to a ground potential outside the ECU 1.

[0023] <Transceiver circuit reference example> First, before describing an embodiment of the transceiver circuit, a reference example will be described to help understand the characteristics of the transceiver circuit according to the embodiment. Fig. 4 is a diagram showing a configuration of a transceiver circuit 4 according to the reference example. The transceiver circuit 4 according to the reference example shown in Fig. 4 includes a terminal VCC, a terminal GND, a terminal TXD, a terminal RXD, a terminal CANH, and a terminal CANL.

[0024] 4 further includes a first current source configured to output a source current and a second current source configured to sink a sink current. The first current source is configured with n (n is a natural number of 2 or more) PMOS transistors Q1_1 to Q1_n. The second current source is configured with n (n is a natural number of 2 or more) NMOS transistors Q4_1 to Q4_n.

[0025] 4 further includes diodes D1 and D2. The diode D1 is configured to prevent a current from flowing from the terminal CANH to the PMOS transistors Q1_1 to Q1_n. The diode D2 is configured to prevent a current from flowing from the NMOS transistors Q4_1 to Q4_n to the terminal CANL.

[0026] The transceiver circuit 4 according to the reference example shown in FIG. 4 further includes a PMOS transistor Q2, an inverter INV1, and an NMOS transistor Q3. The enable signal EN is inverted by the inverter INV1 and then supplied to the gate of the PMOS transistor Q2. The enable signal EN is also supplied to the gate of the NMOS transistor Q3. The PMOS transistor Q2 and the NMOS transistor Q3 each function as a switch that is turned on when the enable signal EN is at a high level and turned off when the enable signal EN is at a low level. When the enable signal EN is at a high level, the transceiver circuit 4 is in an enabled state. On the other hand, when the enable signal EN is at a low level, the transceiver circuit 4 is in a disabled state. The withstand voltage of the PMOS transistor Q2 is higher than that of the PMOS transistors Q1_1 to Q1_n. By providing the PMOS transistor Q2, which has a higher withstand voltage than the PMOS transistors Q1_1 to Q1_n, the PMOS transistors Q1_1 to Q1_n are protected from a high voltage input. The withstand voltage of the NMOS transistor Q3 is higher than that of the NMOS transistors Q4_1 to Q4_n. By providing the NMOS transistor Q3, which has a higher withstand voltage than the NMOS transistors Q4_1 to Q4_n, the NMOS transistors Q4_1 to Q4_n are protected from high-voltage input.

[0027] 4 further includes a control circuit CNT1 and a receiver circuit RCV1. The control circuit CNT1 receives transmission data supplied to a terminal TXD, generates bias voltages Vbp_1 to Vbp_n and Vbn_1 to Vbn_n based on the transmission data, and outputs the bias voltages to the gates of the PMOS transistors Q1_1 to Q1_n and the NMOS transistors Q4_1 to Q4_n.

[0028] The sources of the PMOS transistors Q1_1 to Q1_n are connected to the terminal VCC. The drains of the PMOS transistors Q1_1 to Q1_n are connected to the anode of the diode D1. The cathode of the diode D1 is connected to the source of the PMOS transistor Q2. The drain of the PMOS transistor Q2 is connected to the terminal CANH and the first input terminal of the receiver circuit RCV1.

[0029] The anode of the diode D2 is connected to the terminal CANL and the second input terminal of the receiver circuit RCV1. The cathode of the diode D2 is connected to the drain of the NMOS transistor Q3. The source of the NMOS transistor Q3 is connected to each drain of the NMOS transistors Q4_1 to Q4_n. Each source of the NMOS transistors Q4_1 to Q4_n is connected to the terminal GND.

[0030] An input terminal of the control circuit CNT1 is connected to the terminal TXD, and an output terminal of the receiver circuit RCV1 is connected to the terminal RXD.

[0031] The above-mentioned first signal SCANH is a binary signal of V1 and (V1+V2) as shown in Fig. 5, and the above-mentioned second signal SCANL is a binary signal of V1 and (V1-V2) as shown in Fig. 5. The first signal SCANH and the second signal SCANL are signals corresponding to the input data DATA1 input to the terminal TXD. The differential signal (CAN signal) constituted by the first signal SCANH and the second signal SCANL can be decomposed into a common mode component COM which is the average of the first signal SCANH and the second signal SCANL, and a differential mode component DIFF which is the difference between the first signal SCANH and the second signal SCANL.

[0032] The first transition period P1 is a period during which the voltage value of the first signal SCANH transitions from V1 to (V1+V2) and the voltage value of the second signal SCANL transitions from V1 to (V1-V2). In the first transition period P1, the control circuit CNT1 gradually increases the number of the bias voltages Vbp_1 to Vbp_n that are set to constant voltages greater than zero from a state in which all the bias voltages Vbp_1 to Vbp_n are zero, until all the bias voltages Vbp_1 to Vbp_n are constant voltages greater than zero. Also, in the first transition period P1, the control circuit CNT1 gradually increases the number of the bias voltages Vbn_1 to Vbn_n that are set to constant voltages greater than zero from a state in which all the bias voltages Vbn_1 to Vbn_n are zero, until all the bias voltages Vbn_1 to Vbn_n are constant voltages greater than zero.

[0033] The second transition period P2 is a period during which the voltage value of the first signal SCANH transitions from (V1+V2) to V1, and the voltage value of the second signal SCANL transitions from (V1-V2) to V1. During the second transition period P2, the control circuit CNT1 gradually reduces the number of the bias voltages Vbp_1-Vbp_n that are set to constant voltages greater than zero from a state in which all the bias voltages Vbp_1-Vbp_n are constant voltages greater than zero, until all the bias voltages Vbp_1-Vbp_n are zero. Also, during the second transition period P2, the control circuit CNT1 gradually reduces the number of the bias voltages Vbn_1-Vbn_n that are set to constant voltages greater than zero from a state in which all the bias voltages Vbn_1-Vbn_n are constant voltages greater than zero, until all the bias voltages Vbn_1-Vbn_n are zero.

[0034] FIG. 5 shows an ideal differential signal (CAN signal), and an actual differential signal (CAN signal) is as shown in FIG. 6. In the actual differential signal (CAN signal), in the second transition period P2, a leakage current ILEAKH from the diode D1 reduces the current ICANH' flowing out from the cathode of the diode D1 relative to the current ICANH flowing into the anode of the diode D1. In the actual differential signal (CAN signal), in the second transition period P2, a leakage current ILEAKL from the diode D2 increases the current ICANL' flowing out from the cathode of the diode D2 relative to the current ICANL flowing into the anode of the diode D2. As a result, in the actual differential signal (CAN signal), when the input data DATA1 switches from a low level to a high level, the common mode component COM fluctuates, and the EMI characteristics deteriorate.

[0035] The present inventors have investigated the cause of the fluctuation in the common mode component COM when the input data DATA1 switches from low level to high level by utilizing actual measurements and simulations of the voltages and currents of each part of the transceiver circuit 4 according to the reference example shown in Fig. 4. As a result, the present inventors have found that the cause is a transient increase in current leaking from diodes D1 and D2 to the substrate on which the diodes D1 and D2 are formed when the input data DATA1 switches from low level to high level. The transceiver circuit according to the embodiment described below was developed by the present inventors based on this knowledge.

[0036] <Transceiver circuit according to the first embodiment> Fig. 7 is a diagram showing a configuration of a transceiver circuit 4 according to the first embodiment. The transceiver circuit 4 according to the first embodiment shown in Fig. 7 has a configuration in which a first correction circuit 41 and a second correction circuit 42 are added to the transceiver circuit 4 according to the reference example shown in Fig. 4.

[0037] The first correction circuit 41 is configured to output a first correction current ICORRH to the anode of the diode D1. More specifically, the first correction circuit 41 is configured to output the first correction current ICORRH to the anode of the diode D1 in the second transition period P2. In the second transition period P2, the first correction current ICORRH corrects a decrease in the current ICANH' flowing from the cathode of the diode D1 relative to the current ICANH flowing into the anode of the diode D1.

[0038] The second correction circuit 42 is configured to sink the second correction current ICORRL from the cathode of the diode D2. More specifically, the second correction circuit 42 is configured to sink the second correction current ICORRL from the cathode of the diode D2 in the second transition period P2. In the second transition period P2, the second correction current ICORRL corrects an increase in the current ICANL' flowing out of the cathode of the diode D2 relative to the current ICANL flowing into the anode of the diode D2.

[0039] 7 includes the first correction circuit 41 and the second correction circuit 42, it is possible to suppress the fluctuation of the common mode component COM in the second transition period P2 and improve the EMI characteristics. Note that even if the transceiver circuit 4 includes only one of the first correction circuit 41 and the second correction circuit 42, it is possible to suppress the fluctuation of the common mode component COM in the second transition period P2 and improve the EMI characteristics.

[0040] 8 is a diagram showing an example of the configuration of the first correction circuit 41. Note that the second correction circuit 42 can be designed based on the same concept as the first correction circuit 41, so a configuration example of the second correction circuit 42 will be omitted.

[0041] The first correction circuit 41 shown in FIG. 8 includes NMOS transistors Q10 to Q13, PMOS transistors Q14 to Q18, and resistors R1 to R3.

[0042] When the NMOS transistor Q10 is turned on by the gate pre-discharge control signal GPDC1, a gate pre-discharge current IGPDC flows, and pre-discharges the gate of the PMOS transistor Q18, which is the output transistor of the first correction circuit 41. This pre-discharge can increase the response speed of the first correction circuit 41.

[0043] When the NMOS transistor Q11 is turned on by the gate discharge control signal GDC1, a gate discharge current IGDC flows and the gate of the PMOS transistor Q18 is discharged. This discharging increases the first correction current ICORRH. When the PMOS transistor Q14 is turned on by the gate charge control signal GC1, a gate charge current IGC flows and the gate of the PMOS transistor Q18 is charged. This charging decreases the first correction current ICORRH.

[0044] The control circuit CNT1 generates a gate pre-discharge control signal GPDC1, a gate discharge control signal GDC1, and a gate charge control signal GC1 shown in Fig. 9 based on the input data DATA1, and outputs them to the first correction circuit 41. In the timing chart of Fig. 9, the first correction circuit 41 starts operating at the timing when the first current source and the second current source switch from on to off. More specifically, in the timing chart of Fig. 9, the first correction circuit 41 starts operating to increase the first correction current ICORRH from a minute current (a current that can be approximated to zero) at the timing when the first current source and the second current source start to decrease their output currents.

[0045] The leakage current ILEAKH from the diode D1 becomes larger than zero before the first current source and the second current source start to decrease their output currents. Therefore, as in the timing chart of Fig. 10, the first correction circuit 41 may start operating before the first current source and the second current source switch from on to off. More specifically, in the timing chart of Fig. 10, the first correction circuit 41 starts an operation of increasing the first correction current ICORRH from zero before the first current source and the second current source start to decrease their output currents.

[0046] <Transceiver circuit according to the second embodiment> Fig. 11 is a diagram showing a configuration of a transceiver circuit 4 according to the second embodiment. The transceiver circuit 4 according to the second embodiment shown in Fig. 11 has a configuration in which a first replica circuit, a second replica circuit, a resistor RL', a first detection circuit, and a second detection circuit are added to the transceiver circuit 4 according to the first embodiment shown in Fig. 7.

[0047] The first replica circuit includes PMOS transistors Q1'_1 to Q1'_n, a diode D1', a PMOS transistor Q2', and an inverter INV1'. The first replica circuit has a circuit configuration that replicates a circuit configured with the PMOS transistors Q1_1 to Q1_n, the diode D1, the PMOS transistor Q2, and the inverter INV1. The drain of the PMOS transistor Q2' is connected to a first end of the resistor RL'. The first detection circuit is configured to detect a difference between a current flowing into the diode D1' and a current flowing out of the diode D1'. The first detection circuit includes shunt resistors SR1 and SR2, current sense amplifiers A1 and A2, and an error amplifier A3 that outputs an error output ERR1 according to a difference between an output of the current sense amplifier A1 and an output of the current sense amplifier A2. In this embodiment, the first correction circuit 41 is configured to adjust the value of the first correction current ICORRH according to a detection result of the first detection circuit.

[0048] The second replica circuit includes a diode D2', an NMOS transistor Q3', and NMOS transistors Q4'_1 to Q4'_n. The second replica circuit has a circuit configuration that replicates a circuit configured by the diode D2, the NMOS transistor Q3, and the NMOS transistors Q4_1 to Q4_n. The anode of the diode D2' is connected to the second end of the resistor RL' via a shunt resistor SR3, which will be described later. The second detection circuit is configured to detect a difference between a current flowing into the diode D2' and a current flowing out of the diode D2'. The second detection circuit includes shunt resistors SR3 and SR4, current sense amplifiers A4 and A5, and an error amplifier A6 that outputs an error output ERR2 according to a difference between the output of the current sense amplifier A4 and the output of the current sense amplifier A5. In this embodiment, the second correction circuit 42 is configured to adjust the value of the second correction current ICORRL according to the detection result of the second detection circuit.

[0049] The transceiver circuit 4 according to the second embodiment shown in FIG. 11 can adjust the value of the first correction current ICORRH based on the difference between the current flowing into the diode D1' and the current flowing out of the diode D1', i.e., based on the leakage current ILEAKH from the diode D1'. Similarly, the transceiver circuit 4 according to the second embodiment shown in FIG. 11 can adjust the value of the second correction current ICORRL based on the difference between the current flowing into the diode D2' and the current flowing out of the diode D2', i.e., based on the leakage current ILEAKL from the diode D2'. This makes it possible to precisely suppress the fluctuation of the common mode component COM. Therefore, the transceiver circuit 4 according to the second embodiment shown in FIG. 11 can further improve the EMI characteristics compared to the transceiver circuit 4 according to the first embodiment shown in FIG. 7.

[0050] <Transceiver circuit according to the third embodiment> Fig. 12 is a diagram showing a configuration of a transceiver circuit 4 according to a third embodiment. The transceiver circuit 4 according to the third embodiment shown in Fig. 12 has a configuration in which resistors R4 and R5, a Zener diode ZD1, hysteresis comparators COMP1 and COMP2, an up-down counter 43, and a decoder 44 are added to the transceiver circuit 4 according to the first embodiment shown in Fig. 7.

[0051] A common mode component COM is generated by resistors R4 and R5 and a Zener diode ZD1. A hysteresis comparator COMP1 outputs a comparison result DN between the common mode component COM and a first reference voltage VREF1. A hysteresis comparator COMP2 outputs a comparison result UP between the common mode component COM and a second reference voltage VREF2 that is smaller than the first reference voltage VREF1. An up-down counter 43 decreases a count value by one if the output DN of the hysteresis comparator COMP1 is at a high level at the rising edge timing of the timing signal DATA1', and increases a count value by one if the output UP of the hysteresis comparator COMP2 is at a high level at the rising edge timing of the input data DATA1. The timing signal DATA1' is a signal based on the input data DATA1. The rising edge timing of the timing signal DATA1' appears with a certain time delay from the rising edge timing of the input data DATA1.

[0052] The decoder 44 decodes the count value of the up-down counter 43. The output of the decoder 44 is supplied to the first correction circuit 41 and the second correction circuit 42. The first correction circuit 41 may have a configuration shown in FIG. 13, which is a modified version of the configuration shown in FIG. 8. The first correction circuit 41 shown in FIG. 13 can change the peak value of the first correction current ICORRH according to the output of the decoder 44. That is, the adjustment circuit formed by the resistors R4 and R5, the Zener diode ZD1, the hysteresis comparators COMP1 and COMP2, the up-down counter 43, and the decoder 44 can adjust the value of the first correction current ICORRH based on the common mode component COM. This makes it possible to precisely suppress the fluctuation of the common mode component COM. Therefore, the transceiver circuit 4 according to the third embodiment shown in FIG. 12 can have better EMI characteristics than the transceiver circuit 4 according to the first embodiment shown in FIG. 7.

[0053] The first correction circuit 41 shown in FIG. 13 includes a plurality of PMOS transistors Q16 and a plurality of switches SW1. Each of the plurality of switches SW1 is, for example, a PMOS transistor. The plurality of switches SW1 are controlled by the output of a decoder 44. By changing the number of switches SW1 in the on state, it is possible to change the mirror ratio of the current mirror circuit configured by the PMOS transistors Q15 and Q16. The first correction circuit 41 shown in FIG. 13 includes a plurality of NMOS transistors Q13 and a plurality of switches SW2. Each of the plurality of switches SW2 is, for example, an NMOS transistor. The plurality of switches SW2 are controlled by the output of a decoder 44. By changing the number of switches SW2 in the on state, it is possible to change the mirror ratio of the current mirror circuit configured by the NMOS transistors Q12 and Q13.

[0054] FIG. 14 is a diagram showing a modification of the transceiver circuit 4 according to the third embodiment. In the transceiver circuit 4 according to the modification of the third embodiment shown in FIG. 14, the hysteresis comparators COMP1 and COMP2 in FIG. 12 are replaced with an error amplifier A7, and the up-down counter 43 and the decoder 44 in FIG. 12 are replaced with a current adjustment circuit 45 which is an analog circuit. The adjustment circuit including the resistors R4 and R5, the Zener diode ZD1, the hysteresis comparators COMP1 and COMP2, the up-down counter 43, and the decoder 44 can adjust the value of the first correction current ICORRH in a non-gradational manner based on the common mode component COM. The first correction circuit 41 provided in the transceiver circuit 4 according to the modification of the third embodiment shown in FIG. 14 can be configured to include, for example, a variable resistor whose resistance value is variable in a non-gradational manner, and the resistance value of the variable resistor can be changed according to the output of the current adjustment circuit 45.

[0055] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0056] For example, in the above-described embodiment, a transceiver circuit that performs CAN communication has been described, but the transceiver circuit may be configured to perform communication using a differential signaling method other than CAN communication.

[0057] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0058] A transmission circuit (4) of the present disclosure includes a first terminal (CANH), a second terminal (CANL), a first current source (Q1_1 to Q1_n) configured to output a source current, a second current source (Q4_1 to Q4_n) configured to sink a sink current, a first diode (D1) configured to prevent a current from flowing from the first terminal toward the first current source, a second diode (D2) configured to prevent a current from flowing from the second current source toward the second terminal, and a first correction circuit (4) configured to output a first correction current to an anode of the first diode. 1) and a second correction circuit (42) configured to sink a second correction current from the cathode of the second diode, and an adjustment circuit (R4, R5, ZD1, COMP1, COMP2, 43, 44, A7, 45) configured to adjust the value of the correction current based on the average of a first voltage generated at the first terminal and a second voltage generated at the second terminal, wherein the configuration (first configuration) includes at least the first correction circuit and the correction current includes at least the first correction current, or includes at least the second correction circuit and the correction current includes at least the second correction current.

[0059] According to the transmission circuit of the first configuration, the fluctuation of the common mode component can be suppressed, and therefore the EMI characteristics can be improved. Also, according to the transmission circuit of the first configuration, the value of the correction current is adjusted, and therefore the fluctuation of the common mode component can be suppressed with high accuracy, and the EMI characteristics can be further improved compared to the case where the value of the correction current is not adjusted.

[0060] In the transmission circuit of the first configuration, the adjustment circuit may be configured (second configuration) to include a counter (43) configured to vary a count value based on the average.

[0061] In the transmission circuit of the second configuration, the adjustment circuit may be configured to include a decoder (44) configured to decode the count value (third configuration).

[0062] In the transmission circuit of the third configuration, the transmission circuit may be configured to include at least the first correction circuit and a current mirror circuit in the first correction circuit configured to vary a mirror ratio according to the output of the decoder, or may be configured to include at least the second correction circuit and a current mirror circuit in the second correction circuit configured to vary a mirror ratio according to the output of the decoder (fourth configuration).

[0063] In the transmission circuit of the first configuration, the adjustment circuit may be configured to generate an analog voltage based on the average (fifth configuration).

[0064] The electronic control unit (1) of the present disclosure has a configuration (sixth configuration) including a transmission circuit of any one of the first to fifth configurations described above, and a computer (3) configured to send the transmission data to the transmission circuit.

[0065] The vehicle (X) of the present disclosure has a configuration (seventh configuration) including communication buses (BL1, BL2) and a plurality of electronic control units of the sixth configuration connected to the communication buses. [Explanation of symbols]

[0066] 1 ECU 2 Power circuit 3. Microcomputer 4 Transceiver Circuit 5, D1, D2, D1', D2' Diodes 6, 7 Capacitor 41 1st correction circuit 42 Second correction circuit 43 Up / Down Counter 44 Decoder 45 Current adjustment circuit A1, A2, A4, A5 Current Sense Amplifiers A3, A6, A7 Error amplifiers BL1 1st Bus Line BL2 2nd Bus Line CNT1 Control circuit COMP1, COMP2 Hysteresis comparators INV1, INV1' inverter Q1_1~Q1_n, Q2, Q10~Q13 PMOS transistors Q1'_1~Q1'_n, Q2' PMOS transistors Q3, Q4_1 to Q4_n, Q14 to Q18 NMOS transistors Q3', Q4'_1 to Q4'_n NMOS transistors R1~R3, R101, R102, RL' resistance RCV1 Receiver circuit SR1~SR4 Shunt resistors SW1, SW2 switches T1~T4, VCC, GND, TXD, RXD, CANH, CANL terminal X Vehicle ZD1 Zener diode< / ecu>

Claims

1. A first terminal; A second terminal; a first current source configured to source a sourcing current; a second current source configured to sink a current; a first diode configured to prevent current flow from the first terminal toward the first current source; a second diode configured to prevent current from flowing from the second current source toward the second terminal; At least one of a first correction circuit configured to source a first correction current to the anode of the first diode and a second correction circuit configured to sink a second correction current from the cathode of the second diode; an adjustment circuit configured to adjust a value of a correction current based on an average of a first voltage generated at the first terminal and a second voltage generated at the second terminal; Equipped with A transmission circuit comprising at least the first correction circuit and wherein the correction current includes at least the first correction current, or comprising at least the second correction circuit and wherein the correction current includes at least the second correction current.

2. The transmission circuit of claim 1 , wherein the adjustment circuit includes a counter configured to vary a count value based on the average.

3. The transmitter circuit of claim 2 , wherein the conditioning circuit comprises a decoder configured to decode the count value.

4. 4. The transmission circuit according to claim 3, further comprising at least the first correction circuit, and a current mirror circuit in the first correction circuit configured to vary a mirror ratio in response to an output of the decoder, or further comprising at least the second correction circuit, and a current mirror circuit in the second correction circuit configured to vary a mirror ratio in response to an output of the decoder.

5. The transmitter circuit of claim 1 , wherein the conditioning circuit is configured to generate an analog voltage based on the average.

6. A transmission circuit according to any one of claims 1 to 5; and a computer configured to send the transmission data to the transmission circuit.

7. A communication bus; A plurality of electronic control units according to claim 6 connected to the communication bus; A vehicle equipped with:

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