Phased-array antenna

Abstract

To provide a phased-array antenna with excellent reliability.SOLUTION: A phased-array antenna includes: a pring wiring board 10 having a plurality of first terminals; a plurality of second terminals; a TFT substrate 50 that is arranged oppositely to the pring wiring board 10; and a plurality of conductors 30 that connects a first terminal and a second terminal. The pring wiring board comprises: a plurality of transmission and reception electrodes 12; and a plurality of beam forming IC20 that receives a control signal from the TFT substrate via the first terminal, and controls a phase of a signal that is transmitted and received by a transmission and reception electrode on the basis of the control signal. The TFT substrate contains: a plurality of control circuits 90 that contains the TFT, and generates a control signal for controlling each beam forming IC; and a flat lamination 70 that covers the plurality of control circuits. The flat lamination 70 comprises a plurality of concave parts 80 having an open on an upper surface, respectively.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present disclosure relates to phased array antennas. [Background technology]

[0002] In wireless communication such as wireless LAN, mobile phone communication network, and satellite communication, microwaves in the range of about 1 GHz to about 30 GHz are used because they can transmit a large amount of information. Since such high-frequency radio waves propagate with high directivity, they may be transmitted and received using beamforming technology. For example, Patent Document 1 discloses a phased array antenna that uses a liquid crystal layer for phase control. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-25914 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a highly reliable phased array antenna. [Means for solving the problem]

[0005] A phased array antenna according to an embodiment of the present disclosure includes a printed wiring board having a plurality of first terminals, and a TFT substrate having a plurality of second terminals and a plurality of third terminals, the TFT substrate being disposed on the printed wiring board such that the plurality of first terminals and the plurality of second terminals face each other and are electrically connected to each other. The printed wiring board includes a first substrate, a plurality of transmitting / receiving electrodes arranged one-dimensionally or two-dimensionally on the first substrate, and a plurality of beam forming ICs disposed on the first substrate and connected to the plurality of first terminals and the plurality of transmitting / receiving electrodes. The TFT substrate includes a second substrate, a plurality of control circuits formed on the second substrate and connected to the plurality of second terminals and the plurality of third terminals, each control circuit including at least one TFT, the control circuits generating a control signal for controlling one of the plurality of beam forming ICs, a planarization stack disposed on the second substrate to cover the plurality of control circuits and expose the plurality of third terminals, and a plurality of recesses provided in the planarization stack, each of which has an opening on an upper surface of the planarization stack. Effect of the Invention

[0006] According to one embodiment of the present disclosure, a highly reliable phased array antenna is provided. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing an example of a phased array antenna according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view illustrating an example of the phased array antenna of the first embodiment. [Diagram 3] FIG. 3 is a block diagram showing a schematic configuration of the beamforming IC. [Figure 4A] FIG. 4A is a cross-sectional view showing an example of a TFT substrate of a phased array antenna. [Figure 4B] FIG. 4B is a plan view showing the positional relationship between the recessed portion of the TFT substrate, the transmitting electrode, and the beam forming IC. [Figure 4C] FIG. 4C is a plan view of a recessed portion of the TFT substrate. [Diagram 5] FIG. 5 is a circuit diagram showing an example of the configuration of the control circuit. [Figure 6] FIG. 6 shows an example of a layout of the control circuit shown in FIG. [Figure 7] 7A to 7C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 8] 8A to 8D are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 9] 9A to 9C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 10] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 11] 11A to 11C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 12] 12A to 12C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 13] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 14] 14A to 14C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 15] 15A to 15C are cross-sectional views illustrating steps in a method for manufacturing a TFT substrate. [Figure 16] 16A to 16C are cross-sectional views showing the steps of a method for manufacturing a TFT substrate. [Figure 17] 17A to 17C are cross-sectional views illustrating steps in a manufacturing method for a phased array antenna. [Figure 18] 18A to 18C are process cross-sectional views for explaining the reason why defective patterning of the resist and metal film occurs when a planarization laminate having no terrace is used. [Figure 19] 19A to 19C are process cross-sectional views for explaining the reason why defective patterning of the resist and metal film occurs when a planarization laminate having no terrace is used. [Figure 20]20A to 20C are process cross-sectional views for explaining the reason why defective patterning of the resist and metal film occurs when a planarization laminate having no terrace is used. [Figure 21] 21A to 21C are process cross-sectional views for explaining the reason why defective patterning of the resist and metal film occurs when a planarization laminate having no terrace is used. [Figure 22] FIG. 22 is a cross-sectional view showing an example of a TFT substrate of the phased array antenna according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. The present disclosure is not limited to the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the following description, the same parts or parts having similar functions are commonly designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or modified within the scope of the gist of the present disclosure. In order to make the description easier to understand, in the drawings referred to below, the configuration may be shown in a simplified or schematic manner, or some of the components may be omitted. In addition, the dimensional ratio between the components shown in each drawing does not necessarily indicate the actual dimensional ratio.

[0009] Fig. 1 is a schematic plan view of a phased array antenna 101 of this embodiment, and Fig. 2 is a schematic cross-sectional view of the phased array antenna 101 taken along line AA in Fig. 1. The phased array antenna 101 includes a printed wiring board 10, a TFT substrate 50, and a plurality of conductors 30.

[0010] The printed wiring board 10 and the TFT substrate 50 are disposed to face each other. Specifically, a plurality of first terminals 13 and a plurality of second terminals 73 are provided on the opposing surfaces of the printed wiring board 10 and the TFT substrate 50, respectively. The plurality of first terminals 13 and the plurality of second terminals 73 face each other and are electrically connected to each other by a plurality of conductors 30.

[0011] The printed wiring board 10 includes a plurality of transmitting and receiving electrodes 12 for transmitting and receiving electromagnetic waves, and performs beamforming by adjusting the phase of the electromagnetic waves transmitted and received by each transmitting and receiving electrode 12, as described below. The TFT substrate 50 includes a plurality of control circuits, and transmits various control signals for performing beamforming to the printed wiring board 10 via the conductors 30. The TFT substrate 50 also transmits a transmission wave to the printed wiring board 10 via the conductors 30, and receives a reception wave received by the printed wiring board 10 from the printed wiring board 10 via the conductors 30.

[0012] The TFT substrate 50 further includes a plurality of third terminals 67B, and transmits and receives signals to and from an external circuit by connecting the flexible substrate 40 to the third terminals 67B via conductors 75. An IC such as a control IC 41 may be mounted on the flexible substrate 40.

[0013] The TFT substrate 50 includes a planarizing laminate 70 on a surface facing the printed wiring board 10. In order to form a wiring layer 64 that connects the multiple control circuits formed on the TFT substrate 50 to the multiple second terminals 73 in a layer different from the multiple second terminals 73, the planarizing laminate 70 preferably includes at least two planarizing layers.

[0014] As described later, the planarization laminate 70 is thick and located on one side of the TFT substrate 50, which may cause a large stress on the TFT substrate 50. If a large stress is generated by the planarization laminate 70, the TFT substrate 50 may be warped, making it impossible to properly bond the TFT substrate 50 to the printed wiring substrate 10, or a large stress may be applied to any of the bonding portions of the first terminal 13, the conductor 30, and the second terminal 73 located between the TFT substrate 50 and the printed wiring substrate 10, which may cause problems such as cracks and breakage. In addition, the stress of the TFT substrate 50 may be transmitted to the printed wiring substrate 10, which may cause a decrease in reliability of the phased array antenna 101. Furthermore, the planarization laminate 70 may be thick, which may make it difficult to properly form the second terminal 73 and the wiring layer 64, which may cause a decrease in yield.

[0015] In order to solve such problems, the phased array antenna 101 of the present disclosure has a plurality of recesses 80 in the planarized stack 70. The sides of the recesses have a structure that can suppress such a decrease in reliability and a decrease in yield. Such a structure of the planarized stack 70 will be described in detail below.

[0016] The printed wiring board 10 includes a first substrate 11, a plurality of transmitting and receiving electrodes 12, and a plurality of beam forming ICs 20. The first substrate 11 has a first main surface 11a and a second main surface 11b located on the opposite side to the first main surface 11a. The first main surface 11a faces the TFT substrate 50. The printed wiring board 10 is, for example, a multilayer substrate in which a plurality of wiring layers and a base material layer are laminated. The base material layer is, for example, made of resin alone or glass fiber impregnated with resin, and the wiring layer is made by patterning a metal layer such as copper foil. The printed wiring board 10 may be a flexible substrate having flexibility.

[0017] The multiple transmitting and receiving electrodes 12 are arranged one-dimensionally or two-dimensionally on the first main surface 11a. In this embodiment, the multiple transmitting and receiving electrodes 12 are arranged at the vertices of an equilateral triangle with pitch a as one side along the x-axis direction. In other words, the multiple transmitting and receiving electrodes 12 are arranged at pitch a in the x-axis direction and in a direction forming an angle of 60° with respect to the x-axis direction.

[0018] 1, in this embodiment, each transmitting and receiving electrode 12 is a circular radiation conductor. However, the transmitting and receiving electrodes 12 may have other shapes, such as a rectangular shape other than a circle. Furthermore, the multiple transmitting and receiving electrodes 12 may be arranged in a lattice pattern in the x-axis and y-axis directions, instead of at the vertices of an equilateral triangle. When the phased array antenna 101 is used for communication in a band range from about 1 GHz to about 30 GHz, the size of the transmitting and receiving electrode 12 is, for example, from sub-millimeter to several millimeters in diameter or the length of one side of a rectangle.

[0019] The printed wiring board 10 further includes a plurality of feeding elements electrically connected to a beamforming IC 20 described later and feeding transmission and reception signals between the respective transmitting and receiving electrodes 12. Each feeding element may be, for example, a via conductor or a wiring pattern, and may be directly connected to the transmitting and receiving electrodes 12, or may be a strip conductor arranged at a position where it can be electromagnetically coupled to the transmitting and receiving electrodes 12. The feeding elements are formed inside the first substrate 11 or on the first main surface 11a. Each transmitting and receiving electrode 12 and the corresponding feeding element constitute one planar antenna. A plurality of planar antennas are arranged one-dimensionally or two-dimensionally to constitute an array antenna.

[0020] The beamforming ICs 20 are disposed on the second main surface 11b and mounted on the first substrate 11. In the example shown in FIG. 1 and FIG. 2, the beamforming ICs 20 are disposed so that the transmitting and receiving electrodes 12 and the beamforming ICs 20 do not overlap in a plan view. However, the beamforming ICs 20 may be disposed so as to overlap with the transmitting and receiving electrodes 12 in a plan view. Since the beamforming ICs 20 and the transmitting and receiving electrodes 12 are disposed on different main surfaces of the first substrate 11, the transmitting and receiving electrodes 12 can be disposed on the first main surface 11a without being restricted by the arrangement of the beamforming ICs 20. This makes it possible to increase the area of ​​the transmitting and receiving electrodes 12 disposed on the first main surface 11a or to increase the number of the transmitting and receiving electrodes 12.

[0021] In this embodiment, one beamforming IC 20 controls the phase of one transmitting / receiving electrode 12. However, one beamforming IC 20 may control the phases of two or more transmitting / receiving electrodes 12.

[0022] 3 is a block diagram showing a schematic configuration of the beamforming IC 20. The beamforming IC 20 includes, for example, an antenna switch 21, a phase shifter 22, a variable gain amplifier 23, a power amplifier 24, an antenna switch 21, a phase shifter 22, a variable gain amplifier 23, a power amplifier 24, an antenna switch 25, a low noise amplifier 26, a variable gain amplifier 27, a phase shifter 28, and a controller 29. The beamforming IC 20 also includes a transmission / reception terminal TRX, an RF signal terminal RFC, and a control terminal CTL.

[0023] The beamforming IC 20 receives a transmission signal from the TFT substrate 50 via the conductor 30, the first terminal 13, and the RF signal terminal RFC. When the antenna switches 21 and 25 select the transmission circuit 20TX, the phase of the transmission signal input from the RF signal terminal RFC is adjusted by the phase shifter 22, and the gain is adjusted by the variable gain amplifier 23. The transmission signal whose phase and gain have been adjusted is amplified by the power amplifier 24, and is radiated to the outside from the transmitting and receiving electrode 12.

[0024] A reception signal generated by radio waves received by the transmitting / receiving electrode 12 is output to the TFT substrate 50 by the antenna switches 21 and 25 selecting the receiving circuit 20RX. Specifically, the reception signal is amplified by the low-noise amplifier 26, the gain is adjusted by the variable gain amplifier 27, and the phase is adjusted by the phase shifter 28. The reception signal whose phase and gain have been adjusted is output to the TFT substrate 50 via the RF signal terminal RFC, the first terminal 13, and the conductor 30.

[0025] To perform the above-mentioned operations, the beamforming IC 20 receives control signals via the conductor 30, the first terminal 13, and the control terminal CTL. The control signals include a clock signal, a bias voltage signal, an address signal, and a signal including phase information. Although FIG. 3 shows one control terminal CTL, the control terminal CTL is composed of multiple terminals in order to receive different types of signals. The controller 29 includes, for example, a memory, a temperature sensor, an interface, a processor, and the like, and controls other block circuits of the beamforming IC 20, such as the antenna switch 21 and the phase shifter 22, based on the control signals.

[0026] FIG. 4A is a schematic cross-sectional view showing a part of a configuration example of the TFT substrate 50. The TFT substrate 50 includes a control circuit that generates at least one of the control signals for controlling the above-mentioned beam forming IC 20. This control circuit includes a TFT. In this embodiment, the TFT substrate 50 includes, for example, a plurality of control circuits 90 for generating bias voltage signals for each beam forming IC 20. FIG. 5 is a circuit diagram showing a configuration example of the control circuit 90. Also, FIG. 6 shows an example of the layout of the circuit shown in FIG. 5.

[0027] The control circuit 90 includes a bias voltage generating circuit, which includes transistors T1 to T4. As will be described in more detail below, the transistors T1 to T4 are TFTs, preferably with a double gate structure for improved reliability.

[0028] When a voltage is applied to Vg and the transistors T1 and T3 are on, a bias voltage signal with a magnitude according to Vin is output from Vout. When Vg is zero volts and the transistors T1 and T3 are off, a constant voltage determined by the capacitance stored in C1 is output from Vout.

[0029] 4A shows the structure of the TFT substrate 50 in a cross section including the transistor T1 of the control circuit 90. The TFT substrate 50 includes a second substrate 51. The second substrate 51 is preferably made of an insulating material that is not substantially deformed by heat to which the TFT substrate 50 is exposed during manufacture. The second substrate 51 is, for example, a glass substrate. The second substrate 51 may be made of a material having a thermal expansion coefficient similar to that of the first substrate 11. For example, the second substrate 51 may be made of the same material as the base layer of the first substrate 11.

[0030] In the manufacturing process of the phased array antenna 101, when the printed wiring board 10 and the TFT substrate 50 are heated and bonded, if there is a large difference in the thermal expansion coefficient between the first substrate 11 of the printed wiring board 10 and the second substrate 51 of the TFT substrate 50, the phased array antenna 101 returns to room temperature after bonding, causing a difference in the amount of contraction between the first substrate 11 and the second substrate 51. This may cause a large stress near the first terminal 13 of the first substrate 11 and the second terminal 73 of the second substrate 51, or cause warping in one of the printed wiring board 10 and the TFT substrate 50, which may cause the phased array antenna 101 to be unable to fully exhibit the desired performance due to the stress or warping, or may cause reliability to decrease. The occurrence of such problems may be suppressed by selecting materials for the first substrate 11 and the second substrate 51 so that the difference in the thermal expansion coefficient between the first substrate 11 and the second substrate 51 is small.

[0031] Alternatively, the second substrate 51 may be made of a flexible substrate made of polyimide resin or the like. The second substrate 51 may be made of glass, and the first substrate 11 may be made of a flexible substrate. If either the first substrate 11 or the second substrate 51 is made of a flexible substrate, even if a difference occurs in the amount of expansion or contraction due to a difference in the thermal expansion coefficient, the flexible substrate bends, thereby suppressing the stress applied to the joint portion and the substrate. In this case, from the viewpoint of ensuring the rigidity of the entire phased array antenna 101, it is preferable that the other of the first substrate 11 and the second substrate 51 is made of a substrate having rigidity, not a flexible substrate.

[0032] The TFT substrate 50 includes a base coat layer 52, a resistive layer 53, an interlayer insulating layer 54, a first gate electrode 55A, wiring layers 55B, 55C, 55D, a bottom gate insulating layer 56, a semiconductor layer 57, a top gate insulating layer 58, a second gate electrode 59A, wiring layers 59B, 59C, an interlayer insulating layer 60, wiring layers 61A, 61B, 61C, 61D, a planarizing stack 70, a wiring layer 64, a protective layer 66, an electrode layer 67A, a third terminal 67B, and a pad 68.

[0033] The base coat layer 52 is disposed on the main surface of the second substrate 51. The base coat layer 52 adjusts the stress difference between the second substrate 51 and the laminated structure above the base coat layer 52. The base coat layer 52 is made of, for example, silicon oxide and has a thickness of 100 nm. The base coat layer 52 may be made of silicon nitride.

[0034] The resistive layer 53 is located on the base coat layer 52. The resistive layer 53 is a part of a voltage dividing circuit formed on the TFT substrate 50, and the voltage dividing circuit is included in the control circuit 90. The resistive layer 53 has a resistivity higher than that of good conductors such as copper and aluminum. For example, the resistive layer 53 is made of a transparent electrode material such as indium tin oxide, indium zinc oxide, or tin oxide, which has a resistivity of about several hundred μΩ·cm to several mΩ·cm.

[0035] The interlayer insulating layer 54 is located on the base coat layer 52, covering the resistive layer 53. The interlayer insulating layer 54 is made of, for example, silicon oxide, and has a thickness of 300 nm.

[0036] The first gate electrode 55A and the wiring layers 55B, 55C, and 55D are disposed on the interlayer insulating layer 54. Among them, the wiring layers 55C and 55D are connected to the resistance layer 53 through contact holes provided in the interlayer insulating layer 54. The first gate electrode 55A and the wiring layers 55B, 55C, and 55D are made of, for example, molybdenum and have a thickness of 260 nm. The first gate electrode 55A and the wiring layers 55B, 55C, and 55D are indicated by M1 in FIG. 6.

[0037] The bottom gate insulating layer 56 covers the first gate electrode 55A and the wiring layers 55B, 55C, and 55D and is located on the interlayer insulating layer 54. The bottom gate insulating layer 56 has a laminated structure including, for example, a silicon oxide layer having a thickness of 50 nm and a silicon nitride layer having a thickness of 325 nm.

[0038] The semiconductor layer 57 is positioned so as to overlap the first gate electrode 55A in a plan view. The semiconductor layer 57 is preferably made of amorphous silicon, low-temperature polycrystalline silicon (LTPS), or an oxide semiconductor. As the oxide semiconductor, copper oxide, silver oxide, zinc oxide, gallium oxide, tin oxide, indium oxide, indium gallium zinc oxide, indium tin oxide, indium zinc oxide, titanium oxide, indium titanium oxide, indium titanium zinc oxide, or the like can be used. For example, the semiconductor layer 57 is made of indium gallium zinc oxide and has a thickness of 30 nm.

[0039] Low-temperature polycrystalline silicon and oxide semiconductors are characterized by high electron mobility and high driving capability, and have excellent response at high frequencies. In addition, a transistor including an oxide semiconductor is characterized by low leakage current when turned off.

[0040] The top gate insulating layer 58 covers at least the upper part of the first gate electrode 55A and is located on the semiconductor layer 57. The top gate insulating layer 58 is made of, for example, silicon oxide, and has a thickness of 150 nm.

[0041] The second gate electrode 59A and the wiring layers 59B and 59C are located on the top gate insulating layer 58. Of these, the second gate electrode 59A is located so as to overlap the first gate electrode 55A with the semiconductor layer 57 interposed therebetween. The second gate electrode 59A and the wiring layers 59B and 59C are configured, for example, with a three-layer structure of titanium / aluminum / titanium, with the titanium having a thickness of 30 nm and the aluminum having a thickness of 300 nm. The second gate electrode 59A and the wiring layers 59B and 59C are indicated by M2 in FIG. 6.

[0042] The interlayer insulating layer 60 covers the second gate electrode 59A and the wiring layers 59B and 59C and is located on the top gate insulating layer 58. The interlayer insulating layer 60 has a laminated structure including, for example, a silicon nitride layer having a thickness of 200 nm and a silicon oxide layer having a thickness of 380 nm.

[0043] The wiring layers 61A, 61B, 61C, and 61D are located on the interlayer insulating layer 60. The wiring layers 61A, 61B, 61C, and 61D have a laminated structure including, for example, a copper layer having a thickness of 630 nm and a titanium layer having a thickness of 30 nm. The wiring layers 61A and 61B are each connected to the semiconductor layer 57 through a contact hole provided in the interlayer insulating layer 60. The wiring layer 61C is connected to the wiring layer 59B through a contact hole provided in the interlayer insulating layer 60, and is connected to the wiring layer 55B and the wiring layer 55C through contact holes provided in the interlayer insulating layer 60, the top gate insulating layer 58, and the bottom gate insulating layer 56. The wiring layer 61D is connected to the wiring layer 55D through contact holes provided in the interlayer insulating layer 60, the top gate insulating layer 58, and the bottom gate insulating layer 56, and is connected to the wiring layer 59C through a contact hole provided in the interlayer insulating layer 60. The wiring layers 61A, 61B, 61C, and 61D are indicated by M3 in Fig. 6. A control circuit 90 is formed by these wiring layers and the TFTs.

[0044] The planarizing laminate 70 supports the printed wiring board 10 and planarizes the surface of the second substrate 51 on which the multiple control circuits 90 are formed. Specifically, the planarizing laminate 70 is disposed on the second substrate 51, covering the multiple control circuits 90 and exposing the third terminal 67B. More specifically, the planarizing laminate 70 is disposed on the interlayer insulating layer 60, covering the wiring layers 61A, 61B, 61C, and 61D.

[0045] The phased array antenna 101 has openings 80 a in the top portion 70 a of the planarized stack 70 , and a number of recesses 80 formed in the planarized stack 70 .

[0046] As shown in FIG. 2, for example, the recesses 80 are arranged at positions overlapping the transmitting / receiving electrodes 12 arranged on the printed wiring board 10 in a planar view, that is, in the z-axis direction. FIG. 4B is a plan view showing the positional relationship between the recesses 80 provided in the planarized laminated layer 70 of the TFT substrate 50, the transmitting / receiving electrodes 12, and the beam forming IC 20. A driving unit U including a control circuit 90 for driving the transmitting / receiving electrodes 12 and the beam forming IC 20 constituting one antenna element is arranged, for example, in an area overlapping the transmitting / receiving electrodes 12 and the beam forming IC 20 on the TFT substrate 50. As described above, in this embodiment, the transmitting / receiving electrodes 12 are arranged at the apexes of a plurality of equilateral triangles arranged in a grid, so that the driving unit U of the corresponding antenna element also has a regular hexagonal shape in a planar view. The wiring layers 61A, 61B, 61C, and 61D of the control circuit 90 are arranged in the wiring area UL around the recesses 80 of the driving unit U.

[0047] 4B, the wiring region UL can be secured adjacent to six sides of a regular hexagon that is the outer edge of the recess 80, but the TFTs and wiring layers 61A, 61B, 61C, and 61D of the control circuit 90 may be disposed adjacent to all six sides or may be disposed only adjacent to some of the sides, such as one side or three sides, depending on the circuit scale and circuit pattern. The number and positions of the second terminals 73 can also be set arbitrarily as long as they are within the wiring region UL.

[0048] The recess 80 has a side 80c and a terrace 80t provided on the side 80c. The recess 80 further has the above-mentioned opening 80a and a bottom 80b.

[0049] The terrace 80t is located between the opening 80a and the bottom 80b of the recess 80 in the height direction, and divides the side 80c into two surfaces, a lower portion 80c1 and an upper portion 80c2. The recess 80 may be expressed as having a staircase on the side 80c. In this case, the terrace 80t is the tread of the staircase.

[0050] The terrace 80t is, for example, a plane that forms an angle of, for example, ±30° or less with respect to the surface of the second substrate 51. The distance between the position at the depth of the terrace 80t, which is the position where the terrace 80t contacts the lower portion 80c1, and the position where the terrace 80t contacts the upper portion 80c2, is, for example, not less than 1.0 μm and not more than 4.0 μm.

[0051] 4C is a plan view of the recess 80. The opening 80a and the bottom 80b of the recess 80 each have a regular hexagonal shape. The terrace 80t has a regular hexagonal outer shape and a link shape with a regular hexagonal hole.

[0052] In this embodiment, a terrace 70t is also provided on the side portion 70c of the outer edge of the planarization stack 70. The terrace 70t is located between the upper portion 70a and the lower portion 70b of the planarization stack 70 in the height direction, and has the same characteristics as the terrace 80t, except for its shape.

[0053] By providing the plurality of recesses 80 in the planarized laminate 70, it is possible to reduce the volume of the planarized laminate 70 corresponding to the space of the recesses 80, thereby reducing the stress of the planarized laminate 70. Furthermore, by overlapping the recesses 80 located in the planarized laminate 70 of the TFT substrate 50 and the transmitting / receiving electrodes 12 arranged on the printed wiring board 10 in a planar view, it is possible to suppress attenuation of radio waves in the thick planarized laminate 70 when the phased array antenna 101 transmits and receives radio waves from the TFT substrate 50 side.

[0054] Furthermore, as described in detail below, by having the terrace 80t on the side portion 80c of the planarization stack 70, it is possible to reduce the maximum thickness of the photoresist in the height direction when the side portion 80c is covered with photoresist in the manufacturing process of the TFT substrate 50. This makes it possible to suppress resist residue due to exposure and development.

[0055] In order to form the wiring layer 64 that connects the multiple control circuits 90 formed on the TFT substrate 50 to the multiple second terminals 73 in a layer different from the multiple second terminals 73, the planarizing stack 70 preferably includes two or more planarizing layers.

[0056] The first planarization layer 62 has an upper portion 62a, a lower portion 70b, and a side portion 62c, and the second planarization layer 63 has an upper portion 63a, a lower portion 63b, and a side portion 63c. The first planarization layer 62 is located on the second substrate 51, covering the multiple control circuits 90, and the second planarization layer 63 covers the upper portion 62a and the side portion 62c of the first planarization layer 62.

[0057] The first planarization layer 62 has a first terrace 62t on a side portion 62c, and the second planarization layer 63 has a second terrace 63t on a side portion 63c. In a plan view, the second terrace 63t overlaps with a portion of the first terrace 62t, and a portion of the second terrace 63t is located above the first terrace 62t.

[0058] In this embodiment, the planarization stack 70 further includes a third planarization layer 65. The third planarization layer 65 has an upper portion 70a, a lower portion 65b, a side portion 80c, and a terrace 80t, and covers the upper portion 63a and the side portion 63c of the second planarization layer 63. The upper portion 70a, the side portion 80c, and the terrace 80t are also the upper portion 70a, the side portion 80c, and the terrace 80t of the planarization stack 70. In a plan view, the terrace 70t overlaps with a part of the second terrace 63t and a part of the first terrace 62t, and a part of the terrace 70t is located above the second terrace 63t.

[0059] Focusing on the recess 80, the first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 have a first through hole 62h, a second through hole 63h, and a third through hole 65h, respectively, at the position of the recess 80. As described above, the side portion 62c is located within the first through hole 62h, and the side portion 62c is covered by the side portion 63c. Furthermore, the side portion 65c covers the side portion 63c.

[0060] The side 80c and bottom 80b of the recess 80 are covered with the protective layer 66. The inside of the recess 80 is preferably hollow. In other words, the inside of the recess 80 is preferably filled with the external environment such as air, and is preferably not filled with an insulator such as a resin or an inorganic material, or a conductor such as a metal. This allows the formation of the recess 80 to fully exert the effect of relaxing the stress of the planarized stack 70. In addition, since the recess 80 is not filled with another insulator, the dielectric constant of the recess 80 can be reduced.

[0061] The first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 each have a thickness of, for example, about 1 μm or more and 4 μm or less. More preferably, the maximum thickness of at least one of the first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 is 2 μm or more. By having a maximum thickness of 2 μm or more, the upper surface of the second substrate 51 can be planarized even if large irregularities are generated by forming a plurality of control circuits 90.

[0062] The first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 are preferably made of an organic material, that is, a synthetic resin. Since an organic material has a smaller relative dielectric constant than an inorganic material, the capacitance between the wiring layers is smaller, and the parasitic capacitance can be suppressed. Specifically, the first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 preferably contain an acrylic resin or a polyimide resin as a main component, and are more preferably made of a polyimide resin. The polyimide resin has a smaller dielectric tangent than other resins such as an acrylic resin. Therefore, by making the first planarization layer 62, the second planarization layer 63, and the third planarization layer 65 out of a polyimide resin, the dielectric loss can be reduced when the wiring layer transmits a transmission signal or a reception signal.

[0063] 4A, the wiring layer 64 is located on the second planarization layer 63. The wiring layer 64 has a laminated structure including, for example, a 630 nm copper layer and a 30 nm titanium layer. The wiring layer 64 is connected to the wiring layer 61C via contact holes provided in the first planarization layer 62 and the second planarization layer 63. The wiring layer 64 is located in the wiring region UL around the recess 80.

[0064] The protective layer 66 is positioned so as to cover the entire structure of the main surface of the second substrate 51, including the third planarization layer 65. The protective layer 66 is made of, for example, silicon nitride, and has a thickness of 200 nm.

[0065] The electrode layer 67A and the third terminal 67B are made of, for example, indium zinc oxide and have a thickness of 125 nm. The electrode layer 67A is connected to the wiring layer 64 through contact holes provided in the protective layer 66 and the third planarization layer 65, and the third terminal 67B is connected to 59C through a contact hole provided in the protective layer 66.

[0066] The pad 68 is located on the third terminal 67B. The pad 68 has a laminated structure including, for example, a copper layer having a thickness of 300 nm and a titanium layer having a thickness of 30 nm. The pad 68 and the electrode layer 67A constitute a second terminal 73. The printed wiring board 10 and the TFT substrate 50 are electrically connected to each other by connecting the conductor 30 to the second terminal 73, and a transmission signal and a reception signal are transmitted between the printed wiring board 10 and the TFT substrate 50. In addition, a control signal for controlling the beam forming IC 20 is transmitted from the TFT substrate 50 to the printed wiring board 10.

[0067] The third terminal 67B is connected to the flexible substrate 40 via a conductor 75, and transmits transmission signals, reception signals, and control signals to and from a communication unit external to the phased array antenna 101.

[0068] In this embodiment, the TFT substrate 50 includes the first planarization layer 62 and the second planarization layer 63, but these may be formed integrally. In addition, each of the wiring layers, the first gate electrode, the second gate electrode, and the electrode layer may be made of one or more layers of molybdenum, aluminum, titanium, and copper, or may be made of an alloy layer of these materials.

[0069] As described with reference to FIG. 4A, the transistor T1 has a double gate structure having a first gate electrode 55A and a second gate electrode 59A. As shown in FIG. 6, the transistors T2, T3, and T4 preferably have a double gate structure as well. The transistors T2, T3, and T4 can be formed by wiring layers indicated by M1 and M2, which are formed simultaneously with the first gate electrode 55A and the second gate electrode 59A, as in the case of the transistor T1. The capacitance C1 can be formed by, for example, a wiring layer indicated by M2, which is formed simultaneously with the second gate electrode 59A and the wiring layers 59B and 59C, a wiring layer indicated by M3, which is formed simultaneously with the wiring layers 61A, 61B, 61C, and 61D, and an interlayer insulating layer 60 located between them.

[0070] Next, a method for manufacturing the TFT substrate 50 will be described. The TFT substrate 50 can be manufactured using general semiconductor device manufacturing techniques. An example of a method for manufacturing the TFT substrate 50 will be described with reference to FIGS.

[0071] First, as shown in Fig. 7, a CVD apparatus is used to form a base coat layer 52 made of silicon oxide having a thickness of 100 nm on a second substrate 51 made of glass. Then, a sputtering apparatus is used to form an indium zinc oxide film having a thickness of 80 nm. The indium zinc oxide film is patterned to obtain a resistance layer 53.

[0072] As shown in FIG. 8, an interlayer insulating layer 54 made of silicon oxide and having a thickness of 300 nm is formed on the resistance layer 53 and the base coat layer 52 using a CVD apparatus.

[0073] After forming a contact hole in interlayer insulating layer 54 to expose a part of resistive layer 53, a sputtering device is used to form a molybdenum film having a thickness of 260 nm in the contact hole and on interlayer insulating layer 54. By patterning the molybdenum film, first gate electrode 55A and wiring layers 55B, 55C, and 55D are formed.

[0074] Next, using a CVD apparatus, a bottom gate insulating layer 56 including a 50 nm thick silicon oxide film and a 325 nm thick silicon nitride film is formed on the interlayer insulating layer 54, the first gate electrode 55A, and the wiring layers 55B, 55C, and 55D. Thereafter, using a sputtering apparatus, a 30 nm thick indium gallium zinc oxide film is formed on the bottom gate insulating layer 56, and after annealing, a semiconductor layer 57 is formed by patterning.

[0075] A CVD apparatus is used to form a silicon oxide film having a thickness of 150 nm on the semiconductor layer 57 and the bottom gate insulating layer 56, and an annealing process is performed to form a top gate insulating layer 58. A sputtering apparatus is used to form a titanium film having a thickness of 30 nm, an aluminum film having a thickness of 300 nm, and a titanium film having a thickness of 30 nm in that order on the top gate insulating layer 58, and patterning is performed to form a second gate electrode 59A and wiring layers 59B and 59C.

[0076] As shown in FIG. 9, an interlayer insulating layer 60 including a silicon nitride film having a thickness of 200 nm and a silicon oxide film having a thickness of 380 nm is formed on the second gate electrode 59A, the wiring layers 59B and 59C and the top gate insulating layer 58 using a CVD apparatus.

[0077] Contact holes exposing parts of wiring layers 59B, 55B, 55C, 55D, and 59C are formed in interlayer insulating layer 60, top gate insulating layer 58, and bottom gate insulating layer 56, and then a copper film having a thickness of 630 nm and a titanium film having a thickness of 30 nm are formed in the contact holes and on interlayer insulating layer 69, and patterned to form wiring layers 61A, 61B, 61C, and 61D. In this way, a plurality of control circuits 90 are formed on second substrate 51.

[0078] Next, a planarization laminate 70 is formed having a wiring layer 64 and a recess 80. The planarization laminate 70 includes a first planarization layer 62, a second planarization layer 63, and a third planarization layer 65, each of which is made of an acrylic or polyimide resin, for example, with a thickness of 1 μm to 4 μm.

[0079] First, as shown in FIG. 10, an uncured first planarization layer 62' is applied onto the second substrate 51, covering the control circuit 90, and the uncured first planarization layer 62' is exposed using a multi-tone mask 201. The multi-tone mask 201 is also called a gray-tone mask or a half-tone mask, and has a light-shielding portion 211 that blocks the exposure light, a semi-transmitting portion 212 that blocks a part of the exposure light, and a transmitting portion 213 that does not block the exposure light. In this embodiment, the light transmittance in the semi-transmitting portion 212 is approximately uniform over the entire area of ​​the semi-transmitting portion 212. However, the transmittance of the semi-transmitting portion 212 may have a non-uniform distribution.

[0080] By performing exposure using the multi-tone mask 201, light is substantially blocked in region R1, a sufficient amount of light is irradiated in region R3 to remove the uncured first planarization layer 62', and a sufficient amount of light is irradiated in region R2 to remove a portion of the uncured first planarization layer 62'.

[0081] Thereafter, the uncured first planarization layer 62' is developed and heat-treated to obtain the first planarization layer 62, as shown in FIG. 11. The first planarization layer 62 has a maximum thickness of t1 in the region R1, and a maximum thickness of t2 smaller than t1 in the region R2. In the region R3, the first planarization layer 62 is not formed, and the interlayer insulating layer 60 is exposed. With such a thickness distribution, the first planarization layer 62 has an upper portion 62a, a lower portion 70b, a side portion 62c, and a first terrace 62t located on the side portion 62c. In the region where the interlayer insulating layer 60 is exposed, the portion surrounded by the side portion 62c becomes a first through hole 62h.

[0082] 12, a second planarization layer 63 having an upper portion 63a, a lower portion 63b, a side portion 63c, and a second terrace 63t located on the side portion 63c is formed on the first planarization layer 62 using a similar photolithography technique. A second through hole 63h is formed in the second planarization layer 63 so as to overlap the first through hole 62h.

[0083] 13, contact holes exposing parts of the wiring layer 61C are formed in the first planarization layer 62 and the second planarization layer 63, a metal film 64' is formed on the second planarization layer 63, in the contact holes, and on parts of the interlayer insulating layer 60, and an uncured resist film 71' is further formed. The metal film 64' includes, for example, a copper film having a thickness of 630 nm and a titanium film having a thickness of 30 nm.

[0084] At this time, since a second terrace 63t is formed on the side 63c of the second planarization layer 63, the uncured resist film 71' formed on the side 63c of the second planarization layer 63 is divided into two parts, an inclined portion 71'a and an inclined portion 71'c, by a horizontal portion 71'b formed on the second terrace 63t.

[0085] The uncured resist film 71' is exposed and developed using an exposure mask 202 having a pattern 202p corresponding to the wiring layer 64. The uncured resist film 71' on the side portion 63c of the second planarization layer 63 is divided into two portions, an inclined portion 71'a and an inclined portion 71'c, by the horizontal portion 71'b. Therefore, the maximum thickness of the uncured resist film 71' on the side portion 63c in the vertical direction (y-axis direction) is smaller than when the horizontal portion 71'b is not formed, that is, when the second terrace 63t is not formed. As a result, the amount of light is insufficient during exposure, and the resist film is prevented from remaining. This allows the resist pattern 71 to be formed without the resist remaining on the side portion 63c, as shown in FIG. 14.

[0086] Subsequently, the metal film 64' is etched by dry etching or the like using the resist pattern 71 as a mask, thereby forming the wiring layer 64 as shown in FIG.

[0087] As shown in Fig. 16, a third planarization layer 65 is formed by applying an acrylic or polyimide resin having a thickness of 1 µm to 4 µm on the wiring layer 64 and the second planarization layer 63 and patterning the resin. The third planarization layer 65 can be formed using the same photolithography technique as that for the first planarization layer 62 and the second planarization layer 63. A terrace 80t is formed on a side portion 80c of the third planarization layer 65. A third through hole 65h is formed in the third planarization layer 65 so as to overlap with the second through hole 63h.

[0088] A CVD apparatus is used to form a silicon nitride film having a thickness of 200 nm on the third planarization layer 65, and contact holes exposing parts of the wiring layer 64 are formed in the silicon nitride film, the third planarization layer 65, and the second planarization layer 63 to form a protective layer 66. In addition, a contact hole exposing parts of the wiring layer 59C is formed in the interlayer insulating layer 60 exposed from the planarization stack 70.

[0089] A sputtering device is used to form an indium zinc oxide film having a thickness of 125 nm in the contact holes and on the interlayer insulating layer 60 and protective layer 66, and then patterned to form electrode layer 67A and third terminal 67B. Furthermore, a sputtering device is used to form a copper film having a thickness of 300 nm and a titanium film having a thickness of 30 nm on electrode layer 67A and protective layer 66, and then patterned to form pad 68. This completes the TFT substrate 50 provided with second terminal 73.

[0090] Also, when forming the electrode layer 67A and pad 68 constituting the second terminal 73, the maximum thickness in the vertical direction (y-axis direction) of the resist film located on the side portion 80c is reduced due to the formation of the terrace 80t. Therefore, the electrode layer 67A and pad 68 having the correct pattern can be formed without any resist remaining on the side portion 80c.

[0091] As shown in FIG. 17, the phased array antenna 101 is completed by joining the second terminals 73 of the TFT substrate 50 and the first terminals 13 of the printed wiring board 10 via conductors 30 such as solder bumps.

[0092] Thus, according to the present embodiment, even if the thickness of the planarizing laminate 70 is large, the formation of the recess 80 can reduce the area of ​​the planarizing laminate 70 where the thickness is large, thereby reducing the stress generated in the planarizing laminate 70 and suppressing the occurrence of various problems caused by the stress. Specifically, even if the planarizing laminate 70 is provided only on one side of the TFT substrate 50, the stress caused by the planarizing laminate 70 can be reduced, thereby suppressing problems such as the TFT substrate 50 warping and being unable to properly bond the TFT substrate 50 to the printed wiring substrate 10, the application of large stress to any of the bonding portions of the first terminal 13, the conductor 30, and the second terminal 73 located between the TFT substrate 50 and the printed wiring substrate 10, which makes it easy for cracks or breaks to occur, and the stress of the printed wiring substrate being transmitted, which reduces the reliability of the phased array antenna.

[0093] Furthermore, by providing the terrace 80t on the side 80c of the planarizing stack 70, the thickness in the vertical direction of the resist film for patterning the wiring layer 64 located in the planarizing stack 70 and the second terminal 73 formed on the planarizing stack 70 is prevented from becoming too large on the side. This makes it possible to reliably pattern the wiring layer and the terminals, thereby improving the manufacturing yield.

[0094] In contrast, if the first planarization layer 62 and the second planarization layer 63 do not have terraces on the sides, the resist pattern 71 may not be formed correctly, and therefore a wiring layer with a correct pattern may not be formed. The reason for this will be described with reference to Figs. 18 to 21.

[0095] Consider a case where the first planarization layer 162 does not have a terrace on the side portion 162c, and the second planarization layer 163 does not have a terrace on the side portion 163c, as shown in Fig. 18. When a metal film 164' is formed on the second planarization layer 163, and an uncured resist film 171' is further formed, as shown in Fig. 19, a sloped portion 171'c of the uncured resist film 171' is continuously formed on the side portion 163c. Therefore, as shown in Fig. 19, the vertical thickness of the sloped portion 171'c is at most tmax.

[0096] When the uncured resist film 171' is exposed using an exposure mask 202 having a pattern 202p corresponding to the wiring layer 64, the exposure amount is insufficient at the portion where the vertical thickness of the inclined portion 171'c is tmax. Therefore, as shown in FIG. 20, after development, a resist residue 171R is generated so as to cover a part of the side portion 163c of the second planarization layer 163. Therefore, when the metal film 164' is etched by dry etching using the resist pattern 171 as a mask, the metal film 164' remains in the portion of the residue 171R, and as shown in FIG. 21, a metal pattern 64R is formed. Such a TFT substrate is determined to be defective, which causes a decrease in the manufacturing yield of the TFT substrate 50. Since many steps in the manufacturing process of the TFT substrate 50 have been completed before the wiring layer 64 is formed, the occurrence of defects at this point also leads to an increase in manufacturing costs and takt time. According to the phased array antenna 101 of this embodiment, it is possible to solve such manufacturing problems.

[0097] Furthermore, according to the phased array antenna 101 of this embodiment, the phase of the transmission and reception signals is controlled by the beam forming IC 20, and therefore the temperature stability is superior to the case of using phase control by a dielectric. Furthermore, by forming at least a part of the circuit for controlling the beam forming IC 20 on the TFT substrate 50 separate from the printed wiring board 10, it is possible to reduce the scale of the circuit arranged on the printed wiring board 10, increase the area of ​​the transmission and reception electrodes 12, and / or increase the number of transmission and reception electrodes. This makes it possible to improve the transmission and reception sensitivity and the beam control.

[0098] Moreover, in the printed wiring board 10, the transmitting and receiving electrodes 12 and the beam forming IC 20 are mounted on different main surfaces. This increases the degree of freedom in arranging the transmitting and receiving electrodes 12, and ensures a sufficient area for arranging the transmitting and receiving electrodes 12. Furthermore, by mounting the transmitting and receiving electrodes on the first main surface 11a facing the TFT substrate 50, the transmitting and receiving electrodes 12 are prevented from being exposed to the outside, and the radiation conductor of the transmitting and receiving electrodes 12 can be protected. Since the beam forming IC 20 is mounted on the second main surface 11b, interference of the beam forming IC 20 is prevented when the printed wiring board 10 and the TFT substrate 50 are joined together.

[0099] In addition, when the control circuit formed on the TFT substrate 50 includes a TFT having an oxide semiconductor layer, the leakage current when the TFT is off can be reduced. The channel of the TFT has high electron mobility, so that the response at high frequencies is excellent. Furthermore, the TFT has a double gate structure, so that the leakage current can be reduced and the reliability can be improved.

[0100] In addition, when copper is used for the wiring layer of the TFT substrate 50, the loss during high frequency control can be reduced. By making the planarization layer from an organic material, the relative dielectric constant can be reduced, and the loss between the wiring layers can be reduced. Furthermore, when the organic material is polyimide, the dielectric loss tangent is small, so that the dielectric loss during the transmission of high frequency signals can be reduced.

[0101] In addition, the TFT substrate 50 may include, for example, a voltage divider circuit for supplying a bias voltage to the beam forming IC 20. This reduces the number of circuits to be formed on the printed wiring board, and increases the area of ​​the antenna. Such a voltage divider circuit may be formed of an oxide conductor.

[0102] Second embodiment 22 is a schematic cross-sectional view showing a part of a configuration example of a TFT substrate 250 of the phased array antenna of this embodiment. The TFT substrate 250 includes a planarization laminate 270 having a different form from that of the first embodiment.

[0103] As shown in FIG. 22, the planarization stack 270 includes a first planarization layer 262, a second planarization layer 263, and a third planarization layer 265. The planarization stack 270 includes a recess 280 having an opening 280a in an upper portion 270a. As in the first embodiment, the recess 280 is disposed at a position overlapping the transmitting / receiving electrode 12 in a planar view. The first planarization layer 262 does not have a terrace on a side portion 262c. Moreover, the first planarization layer 262 does not have a first through hole. On the other hand, the second planarization layer 263 covers the upper portion 262a of the first planarization layer 262, and has a second terrace 263t on the side portion 263c. Moreover, the second planarization layer 263 has a second through hole 263h that exposes a part of the upper portion 262a of the first planarization layer 262.

[0104] The third planarization layer 265 covers the top 263a and the side portion 263c of the second planarization layer 263, and has a terrace 280t on the side portion 280c. Furthermore, the third planarization layer 265 has a third through hole 265h overlapping the second through hole 263h.

[0105] By providing the recess 280 in the planarized laminate 270, similarly to the first embodiment, it is possible to reduce the stress generated in the planarized laminate and prevent various problems caused by the stress, thereby realizing a highly reliable phased array antenna.

[0106] Furthermore, since the second terrace 263t is provided on the side portion 263c of the second planarization layer 263, as described in the first embodiment, no unnecessary resist residue is generated when the wiring layer 64 is formed. Furthermore, since the planarization stack 270 also has the terrace 270t on the side portion 270c, no unnecessary resist residue is generated when the second terminal 73 is formed. Therefore, it is possible to manufacture the phased array antenna of this embodiment while suppressing a decrease in manufacturing yield, an increase in manufacturing cost, and an increase in takt time.

[0107] (Other forms) Various modifications are possible for the phased array antenna of the present disclosure. First, the planar shape of the recess provided in the planar laminate, i.e., the shape of the opening, is not limited to a regular hexagon, and may be other shapes such as a circle, an ellipse, an oval, a triangle, a rectangle, etc. In the first and second embodiments, the opening, the terrace, and the bottom of the recess are all the same regular hexagon, but at least one of them may be different.

[0108] The arrangement of the recesses in the planarized laminate is not limited to that in the first and second embodiments, and may be other arrangements. The transmitting and receiving electrodes 12 and the beam forming ICs 20 in the printed wiring board 10 may also be arranged in other arrangements. The radiating conductor of the transmitting and receiving electrodes 12 may have a shape other than a circle. The TFT substrate 50 may include a control circuit other than the circuit shown in FIG. 5.

[0109] Furthermore, the number of planarization layers included in the planarization stack may be 2 or may be 4 or more. The position of the wiring layer that is disposed in the planarization stack and electrically connects the wiring layer 61C and the second terminal 73 is not limited to between the second planarization layer 63 and the third planarization layer 65, and may be located between other planarization layers or between multiple planarization layers.

[0110] In the first and second embodiments, a terrace is provided on the side of the recess provided in the TFT substrate. However, when the thickness of the planarizing laminate is small enough to suppress the generation of unnecessary resist residues during the formation of the wiring layer located in the planarizing laminate and the second terminal located on the planarizing laminate, for example, the terrace does not need to be provided on the side.

[0111] The phased array antenna of the present disclosure can also be described as follows.

[0112] The phased array antenna according to the first configuration includes: a printed wiring board having a plurality of first terminals; a TFT substrate having a plurality of second terminals and a plurality of third terminals, the TFT substrate being disposed on the printed wiring board such that the plurality of first terminals and the plurality of second terminals face each other and are electrically connected to each other; A phased array antenna comprising: The printed wiring board is A first substrate; A plurality of transmitting and receiving electrodes arranged one-dimensionally or two-dimensionally on a first substrate; A plurality of beamforming ICs are disposed on a first substrate and connected to the plurality of first terminals and the plurality of transmitting / receiving electrodes; Equipped with The TFT substrate is A second substrate; A plurality of control circuits formed on the second substrate and connected to the plurality of second terminals and the plurality of third terminals, each control circuit including at least one TFT, and generating a control signal to control one of the plurality of beam forming ICs; a planarization stack disposed on the second substrate to cover the plurality of control circuits and to expose the plurality of third terminals; a plurality of recesses in the planarization stack, each recess having an opening in an upper surface of the planarization stack; According to the first configuration, the recess is provided in the planarizing stack, thereby reducing stress in the planarizing stack.

[0113] In the phased array antenna according to the second configuration, in the first configuration, each of the plurality of recesses may overlap one of the plurality of transmitting / receiving electrodes of the printed wiring board in a plan view. Since the thickness of the planarized laminate is reduced in the recesses, the influence on radio waves transmitted and received by the antenna is suppressed.

[0114] In a phased array antenna according to a third configuration, in the first configuration, each of the plurality of recesses may have a side portion and a terrace provided on the side portion. By providing the terrace on the side portion, resist residue can be suppressed.

[0115] A phased array antenna of a fourth configuration may be such that in the first configuration, the planarization stack includes a first planarization layer covering the multiple control circuits and positioned on the second substrate, and a second planarization layer positioned on the first planarization layer and having multiple second through holes, and each recess may be located in one of the multiple second through holes.

[0116] A phased array antenna according to a fifth configuration may be such that, in the fourth configuration, the first planarization layer has a plurality of first through holes, and the recesses are located in the plurality of first through holes.

[0117] In the phased array antenna according to the sixth configuration, in the fourth configuration, each recess may be located on the first planarization layer.

[0118] In the phased array antenna of the seventh configuration, in the seventh configuration, the planarization stack further includes a third planarization layer located on the second planarization layer covering the second side and having a third side, the first planarization layer having a first side facing the first through hole and a first terrace located on the first side, the second planarization layer having a second side facing the second through hole and a second terrace located on the second side, the second side of the second planarization layer covering the first side of the first planarization layer, and the side of the recess covering the second side.

[0119] The phased array antenna of the eighth configuration is the sixth configuration, wherein the planarization stack further includes a third planarization layer located on the second planarization layer, the second planarization layer having a second side facing the second through hole and a second terrace located on the second side, and the side of the recess may cover the second side.

[0120] A ninth configuration of the phased array antenna is the seventh configuration, wherein the planarization stack further includes a wiring layer located between the second planarization layer and the third planarization layer or between the first planarization layer and the second planarization layer, and the wiring layer may be connected to the plurality of control circuits and the second terminal.

[0121] A phased array antenna according to a tenth configuration is the eighth configuration, wherein the planarization stack further includes a wiring layer located between the second planarization layer and the third planarization layer or between the first planarization layer and the second planarization layer, and the wiring layer may be connected to the plurality of control circuits and the second terminal.

[0122] A phased array antenna according to an eleventh configuration is the phased array antenna of the ninth or tenth configuration, wherein the wiring layer is located around the recess.

[0123] A phased array antenna according to a twelfth configuration may be the ninth or tenth configuration, wherein at least one of the first planarization layer, the second planarization layer, and the third planarization layer has a maximum thickness of 2 μm or more.

[0124] A phased array antenna according to a thirteenth configuration is the ninth or tenth configuration, wherein the first planarization layer, the second planarization layer, and the third planarization layer are made of an organic material.

[0125] A phased array antenna according to a fourteenth configuration is the ninth or tenth configuration, wherein at least one of the first planarization layer, the second planarization layer and the third planarization layer may be made of polyimide resin.

[0126] The phased array antenna according to the fifteenth configuration is any one of the first to tenth configurations, wherein the conductor does not need to be located within the recess. [Explanation of symbols]

[0127] 10...printed wiring board, 11...first substrate, 12...transmitting / receiving electrode, 13...first terminal, 20...beamforming IC, 20RX...receiving circuit, 20TX...transmitting circuit, 21...antenna switch, 22...phase shifter, 23...variable gain amplifier, 24...power amplifier, 25...antenna switch, 26...low noise amplifier, 27...variable gain amplifier, 28...phase shifter, 29...controller, 30...conductor, 40...flexible substrate, 50...TFT substrate, 51...second substrate, 52...base coat layer, 53...resistance layer, 54...interlayer insulating layer, 55A...first gate electrode, 55B to 55D, 59B, 59C, 61A to 61D...wiring layer, 56...bottom gate insulating layer, 57...semiconductor layer, 58...top gate insulating layer, 59A...second gate electrode, 60...interlayer insulating layer, 62,162,262...first planarization layer, 62a,63a,70a...upper portion, 62c,63c,65c,70c,0c...side portion, 62h...first through hole, 62t...first terrace, 63,163,263...second planarization layer, 63b,70b...lower portion, 63h...second through hole, 63t...second terrace, 64R...metal pattern, 65...third planarization layer, 65b...lower portion , 65h...third through hole, 66...protective layer, 67A...electrode layer, 67B...third terminal, 68...pad, 69...interlayer insulating layer, 70...planarization stack, 70t...terrace, 71...resist pattern, 73...second terminal, 75...conductor, 80...recess, 80a...opening, 80b...bottom, 80t...terrace, 101...phased array antenna, 201...multi-tone mask, 202...exposure mask

Claims

1. a printed wiring board having a plurality of first terminals; a TFT substrate having a plurality of second terminals and a plurality of third terminals, the TFT substrate being disposed on the printed wiring substrate such that the plurality of first terminals and the plurality of second terminals face each other and are electrically connected to each other; A phased array antenna comprising: The printed wiring board is A first substrate; a plurality of transmitting and receiving electrodes arranged one-dimensionally or two-dimensionally on the first substrate; a plurality of beamforming ICs disposed on the first substrate and connected to the plurality of first terminals and the plurality of transmitting / receiving electrodes; Equipped with The TFT substrate is A second substrate; A plurality of control circuits formed on the second substrate and connected to a plurality of second terminals and the plurality of third terminals, each control circuit including at least one TFT, and generating a control signal to control one of the beam forming ICs; a planarization stack disposed on the second substrate to cover the control circuits and expose the third terminals; a plurality of recesses in the planarization stack, each recess having an opening in an upper surface of the planarization stack; A phased array antenna comprising:

2. The phased array antenna according to claim 1 , wherein each of the recesses overlaps one of the transmitting and receiving electrodes of the printed wiring board in a plan view.

3. The phased array antenna according to claim 1 , wherein each of the plurality of recesses has a side portion and a terrace provided on the side portion.

4. The planarization stack comprises: a first planarization layer positioned on a second substrate overlying the plurality of control circuits; a second planarization layer located on the first planarization layer and having a plurality of second through holes; Including, The phased array antenna according to claim 1 , wherein each recess is located in one of the plurality of second through holes.

5. the first planarization layer has a plurality of first through holes; The phased array antenna according to claim 4 , wherein each of the recesses is located in one of the first plurality of through holes.

6. The phased array antenna of claim 4 , wherein each of the recesses is located on the first planarizing layer.

7. the planarization stack further includes a third planarization layer positioned on the second planarization layer over the second side and having a third side; the first planarization layer has a first side facing the first through hole and a first terrace located on the first side, the second planarization layer has a second side facing the second through hole and a second terrace located on the second side, the second side of the second planarization layer overlies the first side of the first planarization layer; The phased array antenna of claim 5 , wherein a side of the recess covers the second side.

8. the planarization stack further includes a third planarization layer located on the second planarization layer; the second planarization layer has a second side facing the second through hole and a second terrace located on the second side, The phased array antenna of claim 6 , wherein a side of the recess covers the second side.

9. the planarization stack further includes a wiring layer located between the second planarization layer and the third planarization layer or between the first planarization layer and the second planarization layer; The phased array antenna according to claim 7 , wherein the wiring layer is connected to the plurality of control circuits and the second terminal.

10. the planarization stack further includes a wiring layer located between the second planarization layer and the third planarization layer or between the first planarization layer and the second planarization layer; The phased array antenna according to claim 8 , wherein the wiring layer is connected to the plurality of control circuits and the second terminal.

11. The phased array antenna according to claim 9 , wherein the wiring layer is located around the recess.

12. 11. The phased array antenna according to claim 9 or 10, wherein a maximum thickness of at least one of the first planarization layer, the second planarization layer and the third planarization layer is 2 μm or more.

13. The phased array antenna according to claim 9 or 10, wherein the first planarization layer, the second planarization layer, and the third planarization layer are made of an organic material.

14. 11. The phased array antenna according to claim 9, wherein at least one of the first planarization layer, the second planarization layer, and the third planarization layer is made of a polyimide resin.

15. 11. The phased array antenna of claim 1, wherein no conductors are located within the recess.

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