Driver, electro-optical device and electronic apparatus

Abstract

To provide a driver, etc., capable of making data voltage ranges in a drive period and a precharge period of a pixel close during capacitor drive.SOLUTION: A driver 100 includes a capacitor circuit 10, a capacitor drive circuit 20, a variable capacitance circuit 30 and a control circuit 40. The capacitor circuit 10 includes first to n-th capacitors CA1 to CAn provided between first to n-th nodes NDR1 to NDRn for capacitor drive and an output terminal TQj. The variable capacitance circuit 30 is connected to the output terminal TQj. The control circuit 40 sets the variable capacitance circuit 30 to a first capacitance value CA(7) during a drive period of a pixel 1 of an electro-optical panel 200 and sets the variable capacitance circuit 30 to a second capacitance value CA(0), which is smaller than the first capacitance value CA(7), during a precharge period of the electro-optical panel 200.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a driver that capacitively drives an electro-optical panel. The driver in Patent Document 1 includes a capacitor circuit connected to a data voltage output terminal, a capacitor drive circuit that drives the capacitor circuit, and a variable capacitance circuit connected to the data voltage output terminal. The capacitance of the variable capacitance circuit is set so that the capacitance obtained by adding the capacitance of the variable capacitance circuit and the capacitance of the electro-optical panel side and the capacitance of the capacitor circuit have a given capacitance ratio relationship. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-80805 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to improve display quality, the driver applies a precharge voltage to the data lines before writing data voltages to the pixels. Also, demultiplex driving or phase expansion driving is known as a method in which one output of the driver drives multiple data lines in a time-division manner. In such a driving method, one output of the driver is connected to multiple data lines during precharge and to one data line during pixel writing.

[0005] In capacitive driving as in Patent Document 1, data voltages are supplied to pixels by charge redistribution, but the data voltage is determined by the capacitance ratio between the capacitance on the driving side and the capacitance on the panel side. Therefore, in precharge and pixel writing, if the number of data lines connected to the driver output differs, the capacitance ratio in charge redistribution changes, and the range of data voltages that can be output differs. Similar problems arise not only in precharge and pixel writing, but also in any operating state in which the capacitance ratio changes. Thus, in capacitive driving, there is a problem that the range of data voltages differs for each operating state. [Means for solving the problem]

[0006] One aspect of the present disclosure relates to a driver including a capacitor driving circuit that outputs first to nth capacitor driving voltages (n is a natural number equal to or greater than 2) corresponding to gray scale data to first to nth capacitor driving nodes, a capacitor circuit having first to nth capacitors provided between the first to nth capacitor driving nodes and an output terminal, a variable capacitance circuit connected to the output terminal, and a control circuit that sets the variable capacitance circuit to a first capacitance value during a driving period of a pixel of an electro-optical panel, and sets the variable capacitance circuit to a second capacitance value smaller than the first capacitance value during a pre-charge period of the electro-optical panel.

[0007] Another aspect of the present disclosure relates to an electro-optical device including the driver described above and the electro-optical panel, the electro-optical panel including a signal supply line, first to p-th switches (p is an integer greater than or equal to 2) having one ends connected to the signal supply line, and first to p-th data lines connected to the other ends of the first to p-th switches.

[0008] Yet another aspect of the present disclosure relates to an electronic device including the driver described above. [Brief description of the drawings]

[0009] [Figure 1] 1 shows an example of the configuration of an electro-optical device. [Diagram 2] An example of pixel configuration. [Diagram 3] Detailed driver configuration example. [Figure 4] 3 shows an example of detailed configurations of a capacitor circuit, a capacitor driving circuit, and a variable capacitance circuit. [Diagram 5] FIG. 4 is a diagram for explaining capacitances involved in capacitive driving. [Figure 6] 1A and 1B are diagrams showing a configuration example of a driver circuit and a connection relationship between the driver circuit and a capacitor. [Figure 7] 5A and 5B are diagrams for explaining control of a variable capacitance circuit in each operation state. [Figure 8] 13 is a specific example of a capacitance driving amplitude when the capacitance value of a variable capacitance circuit does not change regardless of the operating state. [Figure 9] 13 is a specific example of a capacitance driving amplitude when the capacitance value of a variable capacitance circuit does not change regardless of the operating state. [Figure 10] 13 is a specific example of the capacitance drive amplitude when the capacitance value of a variable capacitance circuit is changed according to the operating state. [Figure 11] 13 is a specific example of the capacitance drive amplitude when the capacitance value of a variable capacitance circuit is changed according to the operating state. [Figure 12] 5A and 5B are diagrams for explaining control of a variable capacitance circuit in each operation state when a divided precharge is performed. [Figure 13] Example of electronic device configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0011] 1. Electro-optical device 1 shows an example of the configuration of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. In the following, an electro-optical device 400 using a demultiplex drive method will be described as an example, but the present invention is not limited to this, and for example, the electro-optical device 400 may use a phase expansion drive method. In addition, in the following, an example in which the demultiplex number is 8 will be described, but the demultiplex number may be p, where p is an integer of 2 or more.

[0012] The driver 100 includes a control circuit 40, output circuits DD1 to DDk, output terminals TQ1 to TQk, and control signal output terminals SQ1 to SQ8, where k is an integer equal to or greater than 2. The driver 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0013] The electro-optical panel 200 includes input terminals TI1 to TIk, signal supply lines SL1 to SLk, demultiplexers DM1 to DMk, data lines DL11 to DL18, DL21 to DL28, ..., DLk1 to DLk8, and control signal input terminals SI1 to SI8. The electro-optical panel 200 is an active matrix type liquid crystal display panel, an EL display panel using self-luminous elements, or the like. EL is an abbreviation for Electro-Luminescence.

[0014] The control circuit 40 outputs corresponding grayscale data to the output circuit DD1. The output circuit DD1 converts the grayscale data into a data voltage and outputs the data voltage to the output terminal TQ1. The output terminal TQ1 is connected to the input terminal TI1, and the input terminal TI1 is connected to a signal supply line SL1. The same is true for the output circuits DD2 to DDk, the output terminals TQ2 to TQk, the input terminals TI2 to TIk, and the signal supply lines SL2 to SLk.

[0015] The demultiplexer DM1 includes switches SW11 to SW18. Each switch is, for example, a TFT. TFT is an abbreviation for Thin Film Transistor. One end of the switch SW11 is connected to a signal supply line SL1, and the other end is connected to a data line DL11. The switch SW11 is controlled to be turned on or off by a control signal S1. Similarly, one end of the switches SW12 to SW18 is connected to a signal supply line SL1, and the other end is connected to data lines DL12 to DL18. The switches SW12 to SW18 are controlled to be turned on or off by control signals S2 to S8. The same is true for the demultiplexers DM2 to DMk, the switches SW21 to SW28, . . . , SWk1 to SWk8, and the data lines DL21 to DL28, . . . , DLk1 to DLk8. The number of switches and the number of data lines in each demultiplexer may be p, which is the same as the number of demultiplexes.

[0016] Although not shown in FIG. 1, a plurality of pixels are arranged in a matrix in the electro-optical panel 200. FIG. 2 shows an example of the configuration of a pixel. The pixel 1 includes a pixel transistor 2, a pixel electrode 3, and a storage capacitor 4. The pixel transistor 2 is, for example, a TFT. The source of the pixel transistor 2 is connected to a data line DLx, and the gate is connected to a scanning line GLy. DLx is one of the data lines shown in FIG. 1. GLy is one of the plurality of scanning lines provided in the electro-optical panel 200. The pixel electrode 3 has two electrodes facing each other. In a liquid crystal display panel, the two electrodes face each other with liquid crystal sandwiched therebetween. One electrode of the pixel electrode 3 and the storage capacitor 4 is connected to the drain of the pixel transistor 2, and the other is connected to a node of a common voltage VCOM. The scanning line is selected by a scanning line driving circuit (not shown). The scanning line driving circuit may be included in the driver 100, or may be provided outside the driver 100.

[0017] The demultiplex drive will be described by taking the output circuit DD1 as an example. In one horizontal scanning period, the switches SW11, SW12, ..., SW18 are sequentially turned on. When the switch SW11 is on, the output circuit DD1 writes a data voltage to the pixel connected to the data line DL11. Similarly, when the switches SW12, ..., SW18 are on, the output circuit DD1 writes a data voltage to the pixel connected to the data lines DL12, ..., DL1k. Note that rotation or the like may be performed in the demultiplex drive, and the order in which the switches SW11, SW12, ..., SW18 are turned on may be arbitrary. The data voltage is a voltage written to one pixel at a time. Eight pixels are driven in a time series by the demultiplex drive, and the data voltage for each pixel is output to a signal supply line as a time series signal. This signal is called a data signal. In addition to driving the pixels, precharging and the like are performed during the horizontal scanning period, which will be described later.

[0018] 2. Detailed driver configuration example Fig. 3 shows a detailed configuration example of a driver. Fig. 3 shows an output circuit DDj, which is any one of the output circuits DD1 to DDk, and a control circuit 40. j is an integer between 1 and k. The output circuit DDj includes a capacitor circuit 10, a capacitor driving circuit 20, and a variable capacitance circuit 30. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0019] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS type, the parallel RGB type, or the display port type. LVDS is an abbreviation of Low Voltage Differential Signaling.

[0020] The processing circuit 42 outputs the grayscale data DTH[10:0] to the capacitor driving circuit 20 based on the grayscale data GD[9:0]. The capacitor driving circuit 20 drives the capacitor circuit 10 based on the grayscale data DTH[10:0]. The capacitor circuit 10 and the variable capacitance circuit 30 are connected to an output node NVQ that is connected to the output terminal TQj. When the capacitor circuit 10 is driven, charge is injected from the capacitor circuit 10 to the output node NVQ, or charge is discharged from the output node NVQ to the capacitor circuit 10. This charge transfer is redistributed to the variable capacitance circuit 30 and the internal capacitance of the electro-optical panel 200, and the output voltage VQ of the output node NVQ becomes a data voltage corresponding to the grayscale data DTH[10:0].

[0021] As an example, the common voltage is 7.5 V, the voltage range for positive drive is 7.5 V to 12.5 V, and the voltage range for negative drive is 7.5 V to 2.5 V. In this case, DTH[10:0]=000h corresponds to 2.5 V, DTH[10:0]=400h corresponds to 7.5 V, and DTH[10:0]=4FFh corresponds to 12.5 V. When the polarity is not inverted, the grayscale data GD[9:0] may be output to the capacitor drive circuit 20 as is.

[0022] The register circuit 48 stores setting data CSW[4:0] that sets the capacitance value of the variable capacitance circuit 30. For example, the display controller 300 writes the setting data CSW[4:0] to the register circuit 48 via the interface circuit 44. Alternatively, the driver 100 may include a non-volatile memory (not shown) that stores the setting data CSW[4:0] in advance, and the setting data CSW[4:0] may be loaded from the non-volatile memory to the register circuit 48.

[0023] The processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 by outputting the setting data CSW[4:0] read from the register circuit 48 to the variable capacitance circuit 30. The value of the setting data CSW[4:0] is set for each operation state of the driver 100. In each operation state, the processing circuit 42 outputs the setting data CSW[4:0] corresponding to that operation state to the variable capacitance circuit 30, and changes the capacitance value of the variable capacitance circuit 30 in each operation state. The operation states include pre-charge and pixel drive. In addition, the operation states may further include post-charge.

[0024] FIG. 4 shows an example of detailed configurations of the capacitor circuit, the capacitor driving circuit, and the variable capacitance circuit.

[0025] The capacitor circuit 10 includes capacitors CD1 to CD11. The capacitor driving circuit 20 includes driving circuits DR1 to DR11. However, the number of capacitors and driving circuits may be n, where n is an integer equal to or greater than 2. Similarly, the number of bits of the grayscale data DTH[10:0] may be n.

[0026] One end of the capacitor CDi is connected to the output node NVQ, and the other end is connected to the capacitor drive node NDRi. i is an integer between 1 and 11. The capacitors CD1 to CD11 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor CDi is 2 (i-1) ×CD1.

[0027] The processing circuit 42 outputs the i-th bit DTH[i-1] of the grayscale data DTH[10:0] to the input node of the driving circuit DRi. The driving circuit DRi outputs a capacitor driving voltage according to the logic level of the i-th bit DTH[i-1] to the capacitor driving node NDRi. That is, the driving circuit DRi outputs a first voltage level to the capacitor driving node NDRi when the bit DTH[i-1] is at a first logic level, and outputs a second voltage level to the capacitor driving node NDRi when the bit DTH[i-1] is at a second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is a low potential side power supply voltage, and the second voltage level is a high potential side power supply voltage. The driving circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the driving circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0028] When the drive circuits DR1 to DR11 drive the capacitors CD1 to CD11, charge redistribution occurs between the capacitors CD1 to CD11, the variable capacitance circuit 30, and the electro-optical panel-side capacitance, and as a result, a data voltage is written to the pixel.

[0029] The variable capacitance circuit 30 includes adjustment switches SWA1 to SWA5 and adjustment capacitors CA1 to CA5. However, the number of the switches and adjustment capacitors may be m, where m is an integer of 2 or more.

[0030] One end of the adjustment switches SWAs is connected to the output node NVQ, and the other end is connected to one end of the adjustment capacitor CAs. The other end of the adjustment capacitor CAs is connected to the low-potential power supply. s is an integer between 1 and 5. The adjustment switches SWA1 to SWA6 are, for example, P-type MOS transistors, N-type MOS transistors, or transfer gates. The adjustment capacitors CA1 to CA5 have binary-weighted capacitance values. Specifically, the capacitance value of the adjustment capacitor CAs is 2 (s-1) ×CA1.

[0031] The adjustment switches SWAs are controlled to be on or off by the s-th bit CSW[s-1] of CSW[4:0]. When the adjustment switches SWAs are on, the adjustment capacitor CAs is connected to the output node NVQ, and the capacitance value of the adjustment capacitor CAs is added to the capacitance value of the variable capacitance circuit 30. That is, the capacitance value of the variable capacitance circuit 30 is set according to the on / off state of the adjustment switches SWA1 to SWA5.

[0032] The output circuit DDj may further include a grayscale voltage generating circuit and an amplifier circuit. The grayscale voltage generating circuit performs D / A conversion on the grayscale data DTH[10:0] and outputs a grayscale voltage corresponding to the grayscale data DTH[10:0]. The grayscale voltage generating circuit includes, for example, a ladder resistor that generates a voltage corresponding to each grayscale value, and a selection circuit that selects a voltage corresponding to the grayscale data DTH[10:0] from the voltages. The amplifier circuit amplifies or buffers the grayscale voltage output by the grayscale voltage generating circuit and outputs it to the output node NVQ. The amplifier circuit is, for example, a voltage follower circuit. The voltage output by the amplifier circuit and the voltage output by the capacitive drive are basically the same.

[0033] 3. Capacitive drive circuit control 5 is a diagram for explaining capacitances involved in capacitive driving, in which the capacitor driving circuit 20 is illustrated in a simplified manner.

[0034] If the total capacitance of the capacitors CD1 to CD11 in the capacitor circuit 10 is CD, the capacitance of the capacitor CDi is CD / 2 (12-i) If the total capacitance of the adjustment capacitors CA1 to CA5 in the variable capacitance circuit 30 is CAall, the capacitance of the adjustment capacitor CAs is CAall / 2 (6-s) The capacitance value CA of the variable capacitance circuit 30 is obtained by adding up the capacitance values ​​of the adjustment capacitors connected to the output node NVQ by the adjustment switches SWA1 to SWA5.

[0035] The capacitance when the electro-optical panel 200 is viewed from the output terminal TQj is referred to as the electro-optical panel side capacitance CLCD. The capacitance value of the signal supply line SLj is CP, and the capacitance value of each of the data lines DLj1 to DLj8 is CL. These are parasitic capacitances between the wiring and the substrate, etc. The number of switches that are on among the switches SWj1 to SWj8 of the demultiplexer is α. In this case, the electro-optical panel side capacitance is CLCD = CP + α × CL.

[0036] FIG. 6 shows an example of the configuration of the driver circuit and the connection relationship between the driver circuit and the capacitance. Here, the voltage of the low-potential power supply is the ground voltage, and the voltage of the high-potential power supply is VDH. The driver circuit DRi may further include a level shifter, etc., but only the final-stage buffer portion is shown here.

[0037] The drive circuit DRi includes a P-type MOS transistor TPD and an N-type MOS transistor TND connected in an inverter configuration. The bit DTH[i-1] is input to the gates of these transistors. A capacitor CDi and a capacitance CLDC+CA are connected in series between the output of the drive circuit DRi and the ground voltage node. The capacitance CLDC+CA is a capacitance obtained by connecting the electro-optical panel side capacitance CLCD and the variable capacitance circuit 30 in parallel.

[0038] 7 is a diagram for explaining the control of the variable capacitance circuit in each operation state. During a horizontal scanning period, the operation states are precharge, pixel drive, and postcharge in that order.

[0039] When the operating state is precharge, the control circuit 40 outputs control signals S1 to S8 indicating ON. As a result, all of the switches SWj1 to SWj8 of the demultiplexer DMj are turned ON, and the precharge voltage is applied to all eight data lines. Since all eight data lines are connected to the signal supply line SLj, the electro-optical panel side capacitance is CLCD=CP+8CL. The period during which precharge is performed during the horizontal scanning period is called the precharge period.

[0040] When the operation state is pixel drive, the following control is performed. The control circuit 40 outputs a control signal S1 indicating ON, and outputs control signals S2 to S7 indicating OFF. As a result, the switch SWj1 of the demultiplexer DMj turns ON, and the switches SWj2 to SWj8 turn OFF. Similarly, the control circuit 40 sequentially outputs control signals S2, ..., S8 indicating ON. A data voltage is applied to each one of the data lines, and the data voltage is written to the pixel connected to that data line. Since one data line is connected to the signal supply line SLj, the electro-optical panel side capacitance is CLCD = CP + CL. The period during which pixel drive is performed during the horizontal scanning period is called the pixel drive period.

[0041] When the operating state is post-charge, the control circuit 40 outputs control signals S1 to S8 indicating off. As a result, all of the switches SWj1 to SWj8 of the demultiplexer DMj are turned off. Since all of the eight data lines are not connected to the signal supply line SLj, the capacitance of the electro-optical panel becomes CLCD=CP. The period during which post-charge is performed during the horizontal scanning period is called the post-charge period.

[0042] The variable capacitance circuit 30 and the electro-optical panel side capacitance CLCD are referred to as capacitances other than the capacitor circuit 10. The capacitance value of the variable capacitance circuit 30 is adjusted so that at least an appropriate data voltage is written to the pixel during pixel drive. If the capacitance value of the variable capacitance circuit 30 is constant regardless of the operating state, the electro-optical panel side capacitance CLCD changes depending on the operating state, and therefore the capacitances other than the capacitor circuit 10 also change. This causes a distribution ratio between the capacitor circuit 10 and the capacitances other than the capacitor circuit 10 to vary, making it impossible to generate appropriate voltages during pre-charge and post-charge.

[0043] In this embodiment, the control circuit 40 controls the capacitance value of the variable capacitance circuit 30 so that the capacitances of the circuits other than the capacitor circuit 10 are constant during pre-charge, pixel drive, and post-charge.

[0044] In precharging, the control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 1. Connection state 1 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(0). The number in parentheses of CA(0) indicates how many data lines the capacitance value corresponds to. CA(0) is a capacitance value corresponding to 0 data lines, for example, 0 pF. However, an offset of CA(0) > 0 pF may also be used. The capacitance other than that of the capacitor circuit 10 is CP + 8CL + CA(0).

[0045] The control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 2 during pixel driving. Connection state 2 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(7). CA(7) is a capacitance value corresponding to seven data lines, and is CA(0)+7CL. However, CA(7) does not need to be strictly the same as CA(0)+7CL, and only needs to be approximately the same. The capacitance other than that of the capacitor circuit 10 is CP+CL+CA(7)≈CP+8CL+CA(0).

[0046] The control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 3 during post-charge. Connection state 3 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(8). CA(8) is a capacitance value corresponding to eight data lines, and is CA(0)+8CL. However, CA(8) does not need to be strictly the same as CA(0)+8CL, and only needs to be approximately the same. The capacitance of the capacitor circuit 10 other than that of the capacitor circuit 10 is CP+CA(8)≈CP+8CL+CA(0).

[0047] As described above, the capacitances of the components other than the capacitor circuit 10 are constant, CP+8CL+CA(0), regardless of the operating state.

[0048] 8 and 9 are specific examples of the capacitive driving amplitude when the capacitance value of the variable capacitance circuit does not change regardless of the operating state. Here, the capacitive driving amplitude in pixel driving is set to 10 V, and the capacitance value of the variable capacitance circuit 30 is set to 0 pF.

[0049] Suppose that the capacitance value CP of the signal supply line is 10 pF and the capacitance CL of each data line is 5 pF, then the capacitance CLCD on the electro-optic panel side is CP+8CL=50 pF during precharge, CP+CL=15 pF during pixel drive, and CP=10 pF during postcharge.

[0050] If the voltage VDH of the high potential power supply is 15 V, the capacitive drive amplitude is CD / (CD+CA+CLCD)×15 V. If the capacitive drive amplitude in pixel drive is 10 V, then CD / (CD+15 pF)×15 V=10 V, so CD=30 pF. That is, the total capacitance CD of the capacitor circuit 10 to achieve a capacitive drive amplitude of 10 V is 30 pF.

[0051] When the capacitance value CA of the variable capacitance circuit 30 is not changed from 0 pF, the capacitance CA+CLCD other than that of the capacitor circuit 10 is 50 pF in pre-charge, 15 pF in pixel drive, and 10 pF in post-charge. Therefore, the capacitance drive amplitude is 5.63 V in pre-charge, 10 V in pixel drive, and 11.25 V in post-charge.

[0052] In pre-charging to reduce pixel leakage, for example, the lowest voltage of the voltage range, 2.5V, is used. However, since the capacitive driving amplitude is only 5.63V, even if 2.5V is output by capacitive driving, it only drops to 4.69V. This reduces the effect of pre-charging, and there is a risk of image quality deteriorating. Similarly, in post-charging, there is a risk of not being able to output the target voltage.

[0053] If the above-mentioned amplifier circuit is added, the error in the precharge voltage can be eliminated by the amplifier circuit, and a precharge voltage of 2.5 V can be output. However, to do this, the amplifier circuit needs to charge a capacitance of 50 pF + 30 pF, which requires a large current supply capability and increases the power consumption of the amplifier circuit.

[0054] 10 and 11 are specific examples of the capacitance driving amplitude when the capacitance value of the variable capacitance circuit is changed according to the operating state. The capacitance of the signal supply line CP=10 pF, the capacitance of the data line CL=5 pF, the voltage of the high potential side power supply VDH=15 V, and the capacitance driving amplitude in pixel driving of 10 V are the same as in FIG. 8.

[0055] The capacitance value of the variable capacitance circuit 30 in pre-charge is CA(0)=0pF. At this time, the capacitance CA+CLCD other than the capacitor circuit 10 is 50pF. The capacitance value CA of the variable capacitance circuit 30 is controlled so that the capacitance CA+CLCD is constant, so that it is 50pF-15pF=35pF in pixel drive and 50pF-40pF=10pF in post-charge.

[0056] As described above, the capacitive driving amplitude is CD / (CD+CA+CLCD)×15 V. The total capacitance of the capacitor circuit 10 to achieve a capacitive driving amplitude of 10 V is CD / (CD+50 pF)×15 V=10 V, so CD=100 pF. Since CA+CLCD is constant regardless of the operating state, the capacitive driving amplitude is constant at 10 V in pre-charge, pixel drive, and post-charge.

[0057] When the above-mentioned amplifier circuit is added, the error in the precharge voltage is either zero or very small. The amplifier circuit needs to charge a capacitance of 50pF + 100pF, but since the voltage error in driving the capacitance is small, only a small current supply capacity is required, and the power consumption of the amplifier circuit can be reduced.

[0058] Although an example in which all data lines are precharged in each horizontal scanning period has been described above, precharge may be performed divided into multiple horizontal scanning periods. Such precharge is called split precharge. FIG. 12 is a diagram for explaining the control of the variable capacitance circuit in each operation state when split precharge is performed. Below, an example in which split precharge is performed in two horizontal scanning periods is described, but split precharge may be performed in three or more horizontal scanning periods.

[0059] The following controls are performed in the first horizontal scanning period. In pre-charge, the control circuit 40 outputs control signals S1 to S4 indicating ON, and outputs control signals S5 to S8 indicating OFF. As a result, the electro-optical panel side capacitance CLCD=CP+4CL. The control circuit 40 sets the variable capacitance circuit 30 to a capacitance value CA(0). In pixel drive, the control circuit 40 sequentially outputs control signals S1, S2, . . . , S8 indicating ON. As a result, the electro-optical panel side capacitance CLCD=CP+CL. The control circuit 40 sets the variable capacitance circuit 30 to a capacitance value CA(3). CA(3)≈CA(0)+3CL. In post-charge, the control circuit 40 outputs control signals S1 to S8 indicating OFF. As a result, the electro-optical device 400 becomes CLCD=CP. The control circuit 40 sets the variable capacitance circuit 30 to a capacitance value CA(4). CA(4)≈CA(0)+4CL.

[0060] The following control is performed in the second horizontal scanning period. In pre-charge, the control circuit 40 outputs control signals S1 to S4 indicating OFF, and outputs control signals S5 to S8 indicating ON. The electro-optical panel side capacitance CLCD and the capacitance value of the variable capacitance circuit 30 are the same as in the first horizontal scanning period. The control in pixel driving and post-charge is also the same as in the first horizontal scanning period. Thereafter, a horizontal scanning period similar to the first horizontal scanning period and a horizontal scanning period similar to the second horizontal scanning period are alternately repeated.

[0061] As a result of the above, the electro-optical panel capacitance CLCD is constant at CP+4CL+CA(0) regardless of the operating state.

[0062] In this embodiment, the driver 100 includes a capacitor driving circuit 20, a variable capacitance circuit 30, and a control circuit 40. The capacitor driving circuit 20 outputs first to n-th capacitor driving voltages corresponding to the grayscale data DTH[n-1:0] to the first to n-th capacitor driving nodes NDR1 to NDRn. The capacitor circuit 10 has first to n-th capacitors CA1 to CAn provided between the first to n-th capacitor driving nodes NDR1 to NDRn and the output terminal TQj. The variable capacitance circuit 30 is connected to the output terminal TQj. The control circuit 40 sets the variable capacitance circuit 30 to a first capacitance value CA(7) during a driving period of the pixel 1 of the electro-optical panel 200, and sets the variable capacitance circuit 30 to a second capacitance value CA(0) smaller than the first capacitance value CA(7) during a pre-charge period of the electro-optical panel 200.

[0063] As described with reference to FIG. 7 and the like, the electro-optical panel capacitance CLCD during the precharge period is larger than the electro-optical panel capacitance CLCD during the drive period of the pixel 1. According to this embodiment, the control circuit 40 sets the variable capacitance circuit 30 to a first capacitance value CA(7) during the drive period of the pixel 1, and sets the variable capacitance circuit 30 to a second capacitance value CA(0) smaller than the first capacitance value CA(7) during the precharge period. This makes it possible to bring the capacitance CA+CLCD other than the capacitor circuit 10 during the drive period of the pixel 1 closer to the capacitance CA+CLCD other than the capacitor circuit 10 during the precharge period than when the capacitance value of the variable capacitance circuit 30 is fixed. This makes it possible to obtain an appropriate capacitance drive amplitude even during the precharge, and to apply a highly accurate precharge voltage to the data line.

[0064] In this embodiment, the capacitance value of the variable capacitance circuit 30 is CA, and the capacitance value of the electro-optical panel side capacitance is CLCD. At this time, the control circuit 40 sets the first capacitance value CA(7) and the second capacitance value CA(0) so that CA+CLCD in the precharge period approaches CA+CLCD in the drive period of the pixel 1.

[0065] By setting the capacitance value of the variable capacitance circuit 30 in this manner, the capacitance CA+CLCD other than the capacitor circuit 10 during the precharge period can be made to approach the capacitance CA+CLCD other than the capacitor circuit 10 during the drive period of the pixel 1.

[0066] Furthermore, in this embodiment, the control circuit 40 sets the first capacitance value CA(7) and the second capacitance value CA(0) so that CA+CLCD in the drive period of the pixel 1 and CA+CLCD in the precharge period are constant.

[0067] By setting the capacitance value of the variable capacitance circuit 30 in this manner, the capacitance CA+CLCD other than that of the capacitor circuit 10 during the precharge period can be made the same as the capacitance CA+CLCD other than that of the capacitor circuit 10 during the drive period of the pixel 1. This makes it possible to make the capacitive driving amplitude during the precharge period the same as the capacitive driving amplitude during the drive period of the pixel 1.

[0068] Moreover, in this embodiment, the variable capacitance circuit 30 includes first to m-th adjustment capacitors CA1 to CAm, and first to m-th adjustment switches SWA1 to SWAm provided between the first to m-th adjustment capacitors CA1 to CAm and the output terminal TQj.

[0069] According to this embodiment, the control circuit 40 changes the on / off states of the first to m-th adjustment switches SWA1 to SWAm depending on the operation state, thereby making it possible to change the capacitance value of the variable capacitance circuit 30 depending on the operation state.

[0070] Furthermore, in this embodiment, the control circuit 40 sets the variable capacitance circuit 30 to a third capacitance value CA(8) that is greater than the first capacitance value CA(7) during the post-charge period.

[0071] As described with reference to FIG. 7 and the like, the electro-optical panel capacitance CLCD during the post-charge period is smaller than the electro-optical panel capacitance CLCD during the drive period of the pixel 1. According to this embodiment, the control circuit 40 sets the variable capacitance circuit 30 to a first capacitance value CA(7) during the drive period of the pixel 1, and sets the variable capacitance circuit 30 to a third capacitance value CA(8) larger than the first capacitance value CA(7) during the post-charge period. This makes it possible to bring the capacitance CA+CLCD other than the capacitor circuit 10 during the drive period of the pixel 1 closer to the capacitance CA+CLCD other than the capacitor circuit 10 during the post-charge period than when the capacitance value of the variable capacitance circuit 30 is fixed. This makes it possible to obtain an appropriate capacitance drive amplitude even in the post-charge, and to apply a highly accurate post-charge voltage to the data line.

[0072] Moreover, in this embodiment, the electro-optical device 400 includes a driver 100 and an electro-optical panel 200. The electro-optical panel 200 includes a signal supply line SLj, first to p-th switches SWj1 to SWjp having one ends connected to the signal supply line SLj, and first to p-th data lines DLj1 to DLjp connected to the other ends of the first to p-th switches SWj1 to SWjp.

[0073] 12, in the precharge period of the first horizontal scanning period, the 1st to p / 2th switches of the 1st to pth switches SWj1 to SWjp may be turned on. In the precharge period of the second horizontal scanning period, the p / 2+1 to pth switches of the 1st to pth switches SWj1 to SWjp may be turned on.

[0074] According to this embodiment, the capacitance value of the variable capacitance circuit 30 is set so that the capacitance CA+CLCD other than the capacitor circuit 10 during the pixel drive period and the capacitance CA+CLCD other than the capacitor circuit 10 during the precharge period are constant. In this way, even when split precharge is performed, an appropriate capacitive drive amplitude can be obtained in precharge, and a precise precharge voltage can be applied to the data line.

[0075] 4.Electronic equipment 13 shows an example of the configuration of an electronic device including the driver of this embodiment. As the electronic device of this embodiment, various electronic devices equipped with a display device can be assumed. For example, the electronic device is a projector, a television device, an information processing device, a portable information terminal, a car navigation system, a portable game terminal, etc.

[0076] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0077] The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it is composed of a button, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. For example, it is a wired communication interface such as a USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 performs control processing of each part of the electronic device and various data processing. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the driver 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the storage unit 320 into a format that the driver 100 can accept, and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on image data transferred from the display controller 300 .

[0078] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the control circuit, output circuit, driver, electro-optical panel, electro-optical device, and electronic device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0079] 1...pixel, 2...pixel transistor, 3...pixel electrode, 4...holding capacitor, 10...capacitor circuit, 20...capacitor driving circuit, 30...variable capacitance circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 100...driver, 200...electro-optical panel, 300...display controller, 310...processing device, 320...storage unit, 330...user interface unit, 340...data interface unit, 400...electro-optical device, 500...electronic device, CA1 to CA5...adjustment capacitors, CD1 to CD11...capacitors, CLCD...electro-optical panel side capacitance, DD1 to DDk...output circuit, DR1 to DR11...driving circuit, NDR1 to NDR11...capacitor driving node, SW10 to SWk8...switches, SWA1 to SWA5...adjustment switches, TQ1 to TQk...output terminals

Claims

1. a capacitor driving circuit that outputs first to n-th capacitor driving voltages (n is a natural number of 2 or more) corresponding to the grayscale data to first to n-th capacitor driving nodes; a capacitor circuit having first to n-th capacitors provided between the first to n-th capacitor driving nodes and an output terminal; a variable capacitance circuit connected to the output terminal; a control circuit that sets the variable capacitance circuit to a first capacitance value during a driving period of a pixel of an electro-optical panel, and sets the variable capacitance circuit to a second capacitance value smaller than the first capacitance value during a pre-charge period of the electro-optical panel; A driver comprising:

2. 2. The driver according to claim 1, When the capacitance value of the variable capacitance circuit is CA and the capacitance value of the electro-optical panel side capacitance is CLCD, The driver, wherein the control circuit sets the first capacitance value and the second capacitance value so that CA+CLCD in the precharge period approaches CA+CLCD in a drive period of the pixel.

3. 2. The driver according to claim 1, When the capacitance value of the variable capacitance circuit is CA and the capacitance value of the electro-optical panel side capacitance is CLCD, The driver, wherein the control circuit sets the first capacitance value and the second capacitance value so that CA+CLCD during a drive period of the pixel and CA+CLCD during the precharge period are constant.

4. 2. The driver according to claim 1, The variable capacitance circuit includes: first to mth adjustment capacitors (m is a natural number of 2 or more); first to mth adjustment switches provided between the first to mth adjustment capacitors and the output terminal; A driver comprising:

5. 2. The driver according to claim 1, The control circuit includes: A driver comprising: a variable capacitance circuit configured to set a third capacitance value greater than the first capacitance value during a postcharge period.

6. A driver according to any one of claims 1 to 5; The electro-optical panel; Including, The electro-optical panel includes: A signal supply line; first to p-th switches (p is an integer of 2 or more) each having one end connected to the signal supply line; first to p-th data lines connected to the other ends of the first to p-th switches; 1. An electro-optical device comprising:

7. 7. The electro-optical device according to claim 6, During the precharge period, the first to p-th switches are turned on, The electro-optical device, wherein any one of the first to p-th switches is turned on during a driving period of the pixel.

8. 7. The electro-optical device according to claim 6, During the precharge period of the first horizontal scanning period, the first to p / 2-th switches among the first to p-th switches are turned on (p is an even number equal to or greater than 2), The electro-optical device, wherein the p / 2+1 to p-th switches among the first to p-th switches are turned on during the precharge period of the second horizontal scanning period.

9. 6. An electronic device comprising a driver according to any one of claims 1 to 5.

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