Power supply start-up monitoring circuit

Abstract

To provide a power supply start-up monitoring circuit that can monitor the start-up of an additional power supply circuit when an external power supply is started up.SOLUTION: A power supply start-up monitoring circuit 11 comprises: a first power supply circuit 13 including a first bias circuit 21 and a first source follower circuit 23, wherein the first bias circuit 21 includes a first current source 25 and a first load circuit 27 connected in series in a first direction from a first power supply line 19b to a second power supply line 19c, and a first monitor output 21c; a second power supply circuit 15 including a second bias circuit 31 and a second source follower circuit 33, wherein the second bias circuit 31 includes a second current source 35b and a level shift device 35c connected in series in the first direction, a second load circuit, a level shift circuit, and a second monitor output 31c; and a detection circuit 17 for detecting the start-up of a power supply voltage based on a difference between a voltage change of the first monitor output 21c at the start-up of the power supply voltage and a voltage change of the second monitor output 31c.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power supply startup monitoring circuit. [Background technology]

[0002] Patent Document 1 discloses a series regulator. The series regulator includes a source follower. The source follower includes a differential amplifier, a level shifter including a level shift transistor having a gate and a drain connected to each other, and an output transistor. The differential amplifier includes an amplifier stage having a non-inverting input terminal receiving a reference voltage, an inverting input terminal receiving a feedback voltage, and an amplifier output terminal. The inverting input terminal is connected to the follower output terminal of the source follower. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-215906 A Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device starts up in response to application of a power supply from an external source. The semiconductor device has a built-in regulator circuit that steps down the voltage of the external power supply, and the regulator circuit supplies power to an internal circuit integrated together with the regulator circuit. The semiconductor device includes transistors with a high-voltage structure that can withstand the voltage of the external power supply, and transistors with a low-voltage structure that can withstand the output voltage from the regulator circuit. The transistors with a high-voltage structure require a large area in terms of element size and distance between elements. The number of transistors with a high-voltage structure in a semiconductor device is related to the size of the semiconductor device.

[0005] The semiconductor device may use an additional power supply circuit for supplying a low voltage to another circuit in the regulator circuit. The regulator circuit operates in response to the start-up of an external power supply, while the additional power supply circuit also operates in response to the start-up of the external power supply. The start-up of the additional power supply circuit depends on the speed of rise of the power supply at the start-up of the external power supply, while the start-up speed of the additional power supply circuit is independent of the start-up speed of the regulator circuit.

[0006] An object of the present invention is to provide a power supply startup monitoring circuit that can monitor the startup of an additional power supply circuit when an external power supply is started. [Means for solving the problem]

[0007] A power supply startup monitoring circuit according to a first aspect of the present invention is a first power supply circuit including a first bias circuit connected between a first power supply line and a second power supply line different from the first power supply line, and a first source follower circuit having a first power supply output, wherein the first bias circuit includes a first portion and a second portion connected in series in a direction from one of the first power supply line and the second power supply line to the other, and a first monitor output, wherein the first portion includes a first current source, the second portion includes a first load circuit, the first monitor output is connected to a first shared node of the first portion and the second portion, and the first monitor output is connected to an input of the first source follower circuit, a second power supply circuit, wherein a first portion includes a second current source and at least one first level shift device connected in series, the second portion includes a second load circuit and at least one second level shift device connected in series, the second monitor output being connected to a second shared node of the first portion and the second portion, the second monitor output being connected to an input of the second source follower circuit; and a detection circuit connected to the second power supply line, the first monitor output, and the second monitor output, the detection circuit being configured to operate at a voltage that does not exceed a larger potential difference of a potential difference between the second power supply line and the first monitor output and a potential difference between the second power supply line and the second monitor output, the detection circuit having a detection output that detects a start-up of a power supply voltage associated with the first power supply line and the second power supply line based on a difference between a voltage change of the first monitor output and a voltage change of the second monitor output to provide a detection result, the difference occurring upon start-up of the power supply voltage. Effect of the Invention

[0008] According to the above aspect, it is possible to provide a power supply startup monitoring circuit that can monitor the startup of an additional power supply circuit when an external power supply is started up. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating a power supply startup monitoring circuit according to the present embodiment. [Diagram 2] FIG. 2 is a diagram showing how the voltages of the first monitor output of an exemplary first bias circuit and the second monitor output of an exemplary second bias circuit change with increasing power supply voltage. [Diagram 3] FIG. 3 is a diagram illustrating the output characteristics of an exemplary sensing circuit. [Figure 4] FIG. 4 is a diagram showing terminal names of field effect transistors used in the transistors shown in the drawings and description of this embodiment and circuit symbols of the field effect transistors. [Diagram 5] FIG. 5 is a circuit diagram illustrating an exemplary power supply startup monitoring circuit. [Figure 6] FIG. 6 is a circuit diagram showing a circuit that does not include the power supply monitoring circuit of FIG. [Figure 7] FIG. 7 is a diagram showing the operation of the reset circuit in the circuit shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a circuit including a power supply monitoring circuit, a simple power supply circuit, and a regulator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals and duplicated description will be omitted.

[0011] FIG. 1 is a diagram illustrating a power supply startup monitoring circuit according to the present embodiment.

[0012] The power supply startup monitoring circuit 11 includes a first power supply circuit 13, a second power supply circuit 15, and a detection circuit 17. The first power supply circuit 13 and the second power supply circuit 15 are provided as additional power supply circuits, and are connected to a first power supply line 19b (e.g., VDD) and a second power supply line 19c (e.g., GND).

[0013] In the following description, the exemplary first power supply line 19b may be a high potential power supply line referred to as VDD, and the exemplary second power supply line 19c may be a low potential power supply line referred to as GND.

[0014] The first power supply circuit 13 includes a first bias circuit 21 and a first source follower circuit 23. The first bias circuit 21 is connected between the first power supply line 19b and the second power supply line 19c. The first bias circuit 21 has a first monitor output 21c.

[0015] The first bias circuit 21 includes a first portion and a second portion, which are connected in series from one of the first power supply line 19b to the other of the second power supply line 19c. A first shared node 21d of the first portion and the second portion is connected to a first monitor output 21c. The exemplary first portion includes a first current source 25, and the exemplary second portion includes a first load circuit 27.

[0016] In the exemplary first bias circuit 21, the first current source 25 and the first load circuit 27 are connected in series in a first direction from the first power supply line 19b to the second power supply line 19c. In this first bias circuit 21, the first current source 25 and the first load circuit 27 are directly connected in this order in the first direction, as shown in Fig. 1. The first current source 25 and the first load circuit 27 are connected to each other at a first shared node 21d.

[0017] The first source follower circuit 23 is connected to the first power supply line 19b and is fed with power from the first power supply line 19b. The first source follower circuit 23 has a first control input 23c and a first power supply output 23d (first power supply output 13d). The first control input 23c is connected to the first shared node 21d (and the first monitor output 21c), and the first source follower circuit 23 operates in response to a signal from the first monitor output 21c of the first bias circuit 21. The voltage of the first monitor output 21c limits the range of the voltage of the first power supply output 23d.

[0018] The second power supply circuit 15 includes a second bias circuit 31 and a second source follower circuit 33. The second bias circuit 31 is connected between the first power supply line 19b and the second power supply line 19c. The second bias circuit 31 has a second monitor output 31c.

[0019] The second bias circuit 31 has a first portion 35 and a second portion 37, and the first portion 35 and the second portion 37 can be connected in series in this order in a first direction. The first portion 35 and the second portion 37 are connected to each other at a second shared node 31d, and the second shared node 31d is connected to the second monitor output 31c.

[0020] The first section 35 includes a second current source 35b and at least one level shift device 35c, and the second current source 35b and the level shift device 35c can be connected in series as shown in Fig. 1. In the exemplary first section 35, the second current source 35b and the level shift device 35c can be directly connected in this order in a first direction, or directly connected in the reverse order. Alternatively, the second current source 35b and the multiple level shift devices 35c can be connected in any order.

[0021] The second section 37 includes a second load circuit 37b and an additional load circuit, which may include at least one second level shift device 37c. The second load circuit 37b and the level shift device 37c may be connected in series as shown in FIG. 1. In the exemplary second section 37, the second load circuit 37b and the level shift device 37c may be connected in a first direction directly in this order, or may be connected in a reverse order directly. The combination of the second load circuit 37b and the additional load circuit facilitates making the voltage of the first monitor output 21c from the first load circuit 27 different from the voltage from the second monitor output 31c.

[0022] The second source follower circuit 33 is connected to the first power supply line 19b and is supplied with power from the first power supply line 19b. The second source follower circuit 33 has a second control input 33c and a second power supply output 33d. The second control input 33c is connected to the second shared node 31d (and the second monitor output 31c), and the second source follower circuit 33 operates in response to a signal from the second monitor output 31c of the second bias circuit 31. The voltage of the second monitor output 31c limits the range of the voltage of the second power supply output 33d.

[0023] The detection circuit 17 is connected to the second power supply line 19c, the first monitor output 21c, and the second monitor output 31c. The detection circuit 17 is configured to be operable at a power supply voltage smaller than the potential difference between the first power supply line 19b and the second power supply line 19c. The exemplary detection circuit 17 is configured to operate at a voltage that does not exceed the larger of the potential difference between the second power supply line 19c and the first monitor output 21c and the potential difference between the second power supply line 19c and the second monitor output 31c.

[0024] When the power supply voltage for the first power supply line 19b and the second power supply line 19c starts, the detection circuit 17 detects the start of the power supply voltage based on the difference between the voltage change of the first monitor output 21c in response to the change in the power supply voltage and the voltage change of the second monitor output 31c in response to the change in the power supply voltage. The detection circuit 17 has a detection output 17d that provides the detection result.

[0025] The first power supply circuit 13 and the second power supply circuit 15 will now be described.

[0026] In the first power supply circuit 13, the first source follower circuit 23 can include at least one field effect transistor connected to the first power supply line 19b, the first control input 23c, and the first power supply output 23d to configure a source follower circuit. The voltage of the first power supply output 23d of the first source follower circuit 23 is lower than the voltage of the first control input 23c (the first shared node 21d, the first monitor output 21c) by the threshold voltage of the field effect transistor FETN1. The exemplary field effect transistor has an n-type.

[0027] In the second power supply circuit 15, the second source follower circuit 23 can include at least one field effect transistor connected to the first power supply line 19b, the second control input 33c, and the second power supply output 33d to configure a source follower circuit. The voltage of the second power supply output 33d of the second source follower circuit 23 is lower than the voltage of the second control input 33c (the second shared node 31d, the second monitor output 31c) by the threshold voltage of the field effect transistor FETN2. The exemplary field effect transistor has an n-type.

[0028] The difference between the first bias circuit 21 and the second bias circuit 31 is that, roughly speaking, at least one level shift device 35c and at least one level shift device 37c are provided in the second bias circuit 31. These level shift devices 35c and 37c can be provided in the first bias circuit 21, not in the second bias circuit 31. The level shift device 35c is connected between the first power supply line 19b (VDD) and the second shared node 31d, while the level shift device 37c is connected between the second shared node 31d and the second power supply line 19c (GND). Therefore, the level shift device 35c and the level shift device 37c are different from each other in terms of their effects on the voltage level of the second shared node 31d.

[0029] The first bias circuit 21 is not provided with a level shift device 37c, whereas the second bias circuit 31 is provided with a level shift device 37c. This level shift device 37c generates a voltage difference between the first monitor output 21c of the first bias circuit 21 and the second monitor output 31c of the second bias circuit 31. This potential difference generates a voltage difference between the attained voltages of the first power supply output 23d of the first source follower circuit 23 and the second power supply output 33d of the second source follower circuit 23 after the power supply is started up.

[0030] The level shifting device 37c may include at least one of the following exemplary elements: p-type and n-type depletion transistors (eg, gate and source connected together). p-type and n-type enhancement transistors (eg, gate and drain connected together). Bipolar transistors (e.g., collector and base connected together). diode.

[0031] Additionally, the at least one level shifting device 35c operates as follows.

[0032] The first bias circuit 21 is not provided with a level shift device, whereas the second bias circuit 31 is provided with a level shift device 35c. When the level shift device 35c is provided in the second bias circuit 31, a difference occurs between the minimum voltages at which the first bias circuit 21 and the second bias circuit 31 can operate. Specifically, during and after the start-up of the power supplies related to the first power supply line 19b (VDD) and the second power supply line 19c (GND), the level shift device 35c generates a potential difference between both ends thereof to allow a current to flow from the current source 35b. The level shift device 37c also functions in the same manner as the level shift device 35c.

[0033] The level shifting device 35c may include at least one of the following exemplary elements: p-type and n-type depletion transistors (eg, gate and source connected together). p-type and n-type enhancement transistors (eg, gate and drain connected together). Bipolar transistors (e.g., collector and base connected together). diode.

[0034] The level shift device 37c can have a current-voltage characteristic that causes a current to flow suddenly when a voltage difference occurs between the terminals of the level shift device 37c. Therefore, the current (almost constant current) from the current source 35b in the second bias circuit 31 causes the level shift device 37c to generate a terminal-to-terminal voltage difference (almost constant potential difference) after power supply startup. Also, the current (almost constant current) from the current source 35b causes the level shift device 37c to generate a terminal-to-terminal voltage difference (almost constant potential difference) after power supply startup. Therefore, the second bias circuit 31 requires an extra voltage than the operation start voltage of the first bias circuit 21 in order for the level shift device 35c and the level shift device 37c to flow a current from the current source 35b in the second bias circuit 31 at the time of power supply startup, and this extra voltage is applied between the terminals of each of the level shift device 35c and the level shift device 37c. The level shift device 37c acts, for example, like a current source (e.g., a non-linear current source that is a function of the voltage across its terminals), and the level shift device 35c acts, for example, like a current source (e.g., a non-linear current source that is a function of the voltage across its terminals).

[0035] FIG. 2 shows the change in the voltage of the first monitor output of an exemplary first bias circuit and the second monitor output of an exemplary second bias circuit with respect to an increase in the power supply voltage. In FIG. 2, the vertical axis shows the voltage of the first monitor output 21c and the voltage of the second monitor output 31c, and the horizontal axis shows the voltage (power supply voltage) between the first power supply line 19b (VDD) and the second power supply line 19c (GND). At the beginning of the power supply startup, the voltage of the first monitor output 21c is higher than the voltage of the second monitor output 31c, and at the later stage of startup and after startup, the voltage of the first monitor output 21c is lower than the voltage of the second monitor output 31c. The two voltage characteristic lines intersect at the voltage VCRS on the horizontal axis. The potential difference V1 shows the voltage reached by the node Va in FIG. 1, and the potential difference V2 shows the voltage reached by the node Vb in FIG. 1.

[0036] FIG. 3 shows the output characteristic of an exemplary detection circuit. In FIG. 3, the vertical axis shows the voltage of the detection output 17d of the detection circuit 17, and the horizontal axis shows the power supply voltage between the first power supply line 19b (VDD) and the second power supply line 19c (GND). The detection circuit 17 transitions at the voltage VCRS shown in FIG. 2. The output characteristic of the exemplary detection circuit 17 shows that the detection circuit 17 compares the voltage of the first monitor output 21c with the voltage of the second monitor output 31c at power up.

[0037] The detection circuit 17 has a first input 17b and a second input 17c for receiving the voltage signal of the first monitor output 21c and the voltage of the second monitor output 31c, which are different from each other when the power supply voltage is turned on. Apart from receiving the voltage signal, the detection circuit 17 can be powered from at least one of the first bias circuit and the second bias circuit, and in FIG. 1, the detection circuit 17 can be powered from both the first bias circuit and the second bias circuit.

[0038] As can be understood from the above description, the detection circuit 17 can be configured to detect the start-up of the power supply voltage based on the difference between the voltages at the first monitor output 21c and the second monitor output 31c upon start-up of the power supply voltage. The exemplary detection circuit 17 detects that the voltage at the first monitor output 21c and the voltage at the second monitor output 31c become equal to each other upon start-up of the power supply.

[0039] FIG. 4 is a drawing showing the terminal names of the field effect transistors used in the transistors of the drawings and description of this embodiment and the circuit symbols of the field effect transistors. Specifically, part (a) of FIG. 4 shows the circuit symbol of a p-type transistor. Part (b) of FIG. 4 shows the circuit symbol of an n-type transistor. In parts (a) and (b) of FIG. 4, the source, drain, gate and backgate of the field effect transistor are referred to as "S", "D", "G" and "B", respectively. To avoid complication, the reference characters "S", "D", "G" and "B" of the source, drain, gate and backgate of the field effect transistor are omitted in the drawings and the following description. The backgate of the field effect transistor is connected to a node closer to the source than the drain.

[0040] Referring again to FIG. 1, the exemplary sensing circuit 17 may include a first circuit 41, a second circuit 43, and a third circuit 45.

[0041] The first circuit 41 is connected between one of the first monitor output 21c and the second monitor output 31c, for example, the first monitor output 21c and the second power line 19c, and is powered from the first monitor output 21c. The first circuit 41 has a first output 41b. The second circuit 43 is connected between the other of the first monitor output 21c and the second monitor output 31c, for example, the second monitor output 31c and the second power line 19c, and is powered from the second monitor output 31c. The second circuit 43 has a second output 43b.

[0042] The third circuit 45 is connected between either the first monitor output 21c or the second monitor output 31c, for example, between the first monitor output 21c and the second power supply line 19c, and is powered from the first monitor output 21c. The third circuit 45 has a third output 45b.

[0043] The exemplary first circuit 41 may include a first input transistor 41c and a load circuit 41d connected in series in a direction from the first monitor output 21c to the second power supply line 19c. A shared node 41f of the first input transistor 41c and the load circuit 41d is connected to the first output 41b. The first input transistor 41c may be connected between the first monitor output 21c and the shared node 41f, and the load circuit 41d may be connected between the shared node 41f and the second power supply line 19c. The exemplary first input transistor 41c has a p-type. The exemplary load circuit 41d includes a current source.

[0044] The exemplary second circuit 43 may include a second input transistor 43c and a load circuit 43d connected in series in a direction from the second monitor output 31c to the second power supply line 19c. A shared node 43f of the second input transistor 43c and the load circuit 43d is connected to the second output 43b. The second input transistor 43c is connected between the shared node 43f and the second monitor output 31c. The load circuit 43d (third input transistor) is connected between the shared node 43f and the second power supply line 19c. The exemplary second input transistor 43c has a p-type. The exemplary load circuit 43d includes an n-type transistor (hereinafter referred to as a third input transistor 43g).

[0045] The exemplary third circuit 45 may include a fourth input transistor 45c and a fifth input transistor 45f connected in series in a direction from the first monitor output 21c to the second power supply line 19c. A shared node 45d of the fourth input transistor 45c and the fifth input transistor 45f is connected to the third output 45b. The fourth input transistor 45c is connected between the shared node 45d and the first monitor output 21c.

[0046] The fourth input transistor 45c of the exemplary third circuit 45 is powered from the same first monitor output 21c as the first input transistor 41c of the first circuit 41. Hence, the fourth input transistor 45c of the third circuit 45 and the first input transistor 41c of the first circuit 41 can be connected to form a current mirror circuit.

[0047] Also, the fifth input transistor 45f of the exemplary third circuit 45 is connected to the same second power supply line 19c as the third input transistor 43g of the load circuit 43d of the second circuit 43. Thus, the fifth input transistor 45f of the third circuit 45 and the third input transistor 43g of the second circuit 43 can be connected to configure a current mirror circuit.

[0048] The first circuit 41, which is powered from the first monitor output 21c, and the second circuit 43, which is powered from the second monitor output 31c, are combined with the third circuit 45. With this combination, the power supply startup monitoring circuit 11 can transmit the voltage change of the first monitor output 21c and the voltage change of the second monitor output 31c to the third circuit 45 via the two current mirror circuits. The third circuit 45 can be configured to compare two current values ​​from the two current mirror circuits. The third circuit 45 can generate a comparison result at the third output 45b. The comparison of the two current values ​​is not limited to such a combination of the first circuit 41 to the third circuit 45.

[0049] Also, the gate and drain of the first input transistor 41c of the first circuit 41 can be configured to be connected to each other at a shared node 41f. In addition, the shared node 41f of the first circuit 41 can be connected to the gate of the second input transistor 43c of the second circuit 43. The gate of the first input transistor 41c and the gate of the second input transistor 43c are connected to each other. However, the source of the first input transistor 41c is connected to the first monitor output 21c and the source of the second input transistor 43c is connected to the second monitor output 31c. Therefore, the first input transistor 41c and the second input transistor 43c do not form a current mirror circuit. At the intersection VCRS (see FIG. 2) of the two voltage characteristic lines in FIG. 2, the source of the first input transistor 41c has the same potential as the source of the second input transistor 43c. When the power supply voltage further increases beyond the intersection, the potential difference between the gate and source of the second input transistor 43c becomes larger than the potential difference between the gate and source of the first input transistor 41c.

[0050] The exemplary detection circuit 17 may include a fourth circuit 47 in addition to the first circuit 41, the second circuit 43, and the third circuit 45. In the exemplary detection circuit 17, a fourth circuit 47 is connected between either the first monitor output 21c or the second monitor output 31c, for example, the second monitor output 31c, and the second power supply line 19c.

[0051] The fourth circuit 47 can be powered from the second monitor output 31c, but may also be powered from the first monitor output 21c. The fourth circuit 47 can generate a detection signal with an amplitude substantially equal to the potential difference between the voltage level of the first monitor output 21c or the second monitor output 31c and the voltage level of the second power supply line. The output 47b of the fourth circuit 47 can be connected to the detection output 17d of the detection circuit 17.

[0052] The exemplary fourth circuit 47 may include a sixth transistor 47c and a load circuit 47d connected in series in a direction from the second monitor output 31c to the second power supply line 19c. A shared node 47f of the sixth transistor 47c and the load circuit 47d is connected to the fourth output 47b. The sixth transistor 47c is connected between the shared node 47f and the second monitor output 31c. The load circuit 47d is connected between the shared node 47f and the second power supply line 19c. The exemplary sixth transistor 47c has a p-type. The exemplary load circuit 47d includes a current source.

[0053] In the detection circuit 17, the third circuit 45 and the fourth circuit 47 can configure a determination circuit 51. The determination circuit 51 has a first input 51b and a second input 51c. The first input 51b and the second input 51c are connected to the first output 41b of the first circuit 41 and the second output 43b of the second circuit 43, respectively.

[0054] The exemplary determination circuit 51 may include a comparison circuit 53 and an output circuit 55. The comparison circuit 53 may be connected to the first output 41b of the first circuit 41 and the second output 43b of the second circuit 43 to compare the voltage level difference between the first monitor output 21c and the second monitor output 31c. The exemplary comparison circuit 53 may include a third circuit 45. The comparison circuit 53 operates in response to the signals from the first output 41b of the first circuit 41 and the second output 43b of the second circuit 43, respectively. The output circuit 55 may be connected to the output 53b of the comparison circuit 53 and operates in response to the signal from the output of the comparison circuit 53. The signal from the output of the comparison circuit 53 may be changed to a signal at the voltage level of the first monitor output 21c and the second monitor output 31c. The exemplary output circuit 55 may include a fourth circuit 47 and is configured to amplify the comparison signal from the comparison circuit 53 using a sixth transistor 47c and a load circuit 47d.

[0055] The power supply startup monitoring circuit 11 further comprises a regulator 61 which provides a regulated voltage at an output 61b. The regulator 61 has an output 61b, a first input 61c and a second input 61d.

[0056] The regulator 61 can include a first signal generating circuit 63, a second signal generating circuit 65, and a power supply circuit 67. The first signal generating circuit 63 is powered by the first power supply circuit 13, and the second signal generating circuit 65 is powered by the second power supply circuit 15. The power supply circuit 67 is connected between the first power supply line 19b and the second power supply line 19c.

[0057] The power supply startup monitoring circuit 11 may include a first switch 67b, a second switch 67c, and a level shifter 69. One of the first switch 67b and the second switch 67c, for example the first switch 67b, is connected between the first power supply output 23d of the first source follower circuit 23 and the first input 61c of the regulator 61. The other of the first switch 67b and the second switch 67c, for example the second switch 67c, is connected between the second power supply output 33d of the second source follower circuit 33 and the second input 61d of the regulator 61. The level shifter 69 is connected between the first power supply line 19b and the second power supply line 19c, and has a control input 69b that receives a signal from the detection output 17d and a control output 69c that provides a signal having a voltage level between the first power supply line 19b and the second power supply line 19c. The level shifter 69 is configured to control the conduction / non-conduction of the first switch 67b and the second switch 67c.

[0058] The detection circuit 17 detects that the first power supply circuit 13 and the second power supply circuit 15 are sufficiently activated upon activation of the power supply voltages related to the first power supply line 19b and the second power supply line 19c, based on the voltages of the first monitor output 21c and the second monitor output 31c. In response to an activation detection signal from the detection output 17d of the detection circuit 17, the level shifter 69 renders the first switch 67b and the second switch 67c conductive. In response to this conduction, the regulator 61 becomes operable.

[0059] The first signal generating circuit 63 is connected between the second power supply line 19c and the first input 61c, and is supplied with power from the first power supply circuit 13. The voltage Vana supplied from the first power supply circuit 13 to the first signal generating circuit 63 is smaller than the power supply voltages related to the first power supply line 19b and the second power supply line 19c. For this reason, the transistors constituting the first signal generating circuit 63 can be constructed with a low-voltage withstand structure, rather than a high-voltage withstand structure.

[0060] The second signal generating circuit 65 is connected between the second power supply line 19c and the second input 61d, and is powered by the second power supply circuit 15. The voltage Vdig supplied from the second power supply circuit 15 to the second signal generating circuit 65 is smaller than the power supply voltages related to the first power supply line 19b and the second power supply line 19c. Therefore, the transistors constituting the second signal generating circuit 65 can be configured with a low-voltage withstand structure, rather than a high-voltage withstand structure.

[0061] In contrast to the transistors of the first signal generating circuit 63 and the second signal generating circuit 65, the transistors of the first source follower circuit 23 and the second source follower circuit 33 can be provided with a high voltage resistant structure.

[0062] A transistor with a high breakdown voltage structure has a larger area in terms of the size of each element and the spacing between elements than a transistor with a low breakdown voltage structure. The use of a transistor with a low breakdown voltage structure contributes to reducing the size of a semiconductor device.

[0063] The exemplary first signal generating circuit 63 may include a reference voltage circuit 71. The exemplary first signal generating circuit 63 may further include an error amplifier circuit 73 connected between the second power supply line 19c and the first input 61c. The exemplary second signal generating circuit may further include a reset circuit 75 connected between the second input 61d and the second power supply line 19c. The reset circuit 75 may have an output 75b, a second feedback input 75c, and a reference input 75d.

[0064] The reference voltage circuit 71 is connected between the second power supply line 19c and the first input 61c, and may include a first output 71b and a second output 71c. The reference voltage circuit 71 generates a reference voltage at the first output 71b and the second output 71c, which is provided to the error amplifier circuit 73 and the reset circuit 75.

[0065] When configured in the form of a semiconductor device, the power supply start-up monitoring circuit 11 may include one or more electrodes, such as pad electrodes, that enable electrical connection between the outside of the semiconductor device and the power supply start-up monitoring circuit 11. An exemplary semiconductor device includes the power supply start-up monitoring circuit 11 and includes electrodes (10b, 10c, 10d, 10f, 10g). Specifically, the electrode (10b) is connected to the output 61b of the regulator 61. The electrode (10c) is connected to the first power supply line 19b. The electrode (10d) is connected to the second power supply line 19c. The electrode (10f) is connected to the first feedback input 73c of the error amplifier circuit 73. The electrode (10g) is connected to the second feedback input 75c of the reset circuit 75. The reset circuit 75 has a reference input 75d that is connected to the second output 71c of the reference voltage circuit 71 and an output 75b that provides a reset signal.

[0066] The output 61b of the regulator 61 is connected to the voltage divider circuit 20 at the electrode (10b). The voltage divider circuit 20 includes two resistors (20b, 20c), and a shared node 20d of the resistors (20b, 20c) is connected to the electrode (10f). The intermediate node of the resistor (20c) of the voltage divider circuit 20 is connected to the electrode (10g). The output 61b of the regulator 61 is connected to the capacitor 30 at the electrode (10b).

[0067] The regulator 61 may include a first level shift circuit 77 and a regulator output circuit 79. The first level shift circuit 77 has a feedback input 77b and a level shift output 77c. A control input 79c of the regulator output circuit 79 is connected to the level shift output 77c of the first level shift circuit 77.

[0068] The error amplifier circuit 73 of the second signal generating circuit 65 may have an output 73b, a first feedback input 73c, and a reference input 73d. The error amplifier circuit 73 receives a feedback voltage from the voltage divider circuit 20 via the electrode (10f) at the first feedback input 73c. ​​The error amplifier circuit 73 also receives a reference voltage from the output 71b of the reference voltage circuit 71 at the reference input 73d. The error amplifier circuit 73 generates a control signal at the output 73b based on the difference between the feedback voltage at the first feedback input 73c and the reference voltage at the reference input 73d. This control signal is provided to the feedback input 77b.

[0069] The reset circuit 75 of the second signal generating circuit 65 includes a comparator 76 which receives the second feedback voltage from the electrode (10g) at its negative input (second feedback input 75c) and receives the reference voltage from the reference voltage circuit 71 at its positive input (reference input 75d) and compares the second feedback voltage with the reference voltage. When the comparison result indicates that the regulator 61 is sufficiently activated, the reset circuit 75 generates a reset signal at its output 75b.

[0070] The level shift circuit 77 of the regulator 61 may include a seventh transistor 81 and a load circuit 83 connected in series in a direction from the second power supply line 19c to the first power supply line 19b. The seventh transistor 81 operates in response to a signal from the output 73b of the error amplifier circuit 73. One end of the load circuit 83 is connected to the first power supply line 19b, and the other end of the load circuit 83 is connected to the level shift output 77c. The exemplary load circuit 83 may include an eighth transistor 85. The eighth transistor 85 has a gate and a drain connected to each other.

[0071] The level shift circuit 77 may include a ninth transistor 87 connected between the seventh transistor 81 and the load circuit 83. The ninth transistor 87 has a gate connected to a bias input 77d and passes a current through the seventh transistor 81 and the eighth transistor 85. The gate of the ninth transistor 87 receives a voltage approximately halfway between the voltage of the first power supply line 19b and the voltage of the second power supply line 19c from the bias input 77d. The voltage of the gate of the ninth transistor 87 limits the range of the voltage of the source of the ninth transistor 87. The back gate and the source of the ninth transistor 87 may be well-isolated and connected to each other.

[0072] In the exemplary level shift circuit 77, the seventh transistor 81 can have a low-voltage structure of the first conductivity type (n-type), while the eighth transistor 85 can have a high-voltage structure of the second conductivity type (p-type), and the ninth transistor 87 can have a high-voltage structure of the first conductivity type (n-type).

[0073] The regulator output circuit 79 may include an output transistor 89 connected to the level shift output 77c of the first level shift circuit 77. In the exemplary regulator output circuit 79, the input 79b of the regulator output circuit 79 is connected to the gate and drain of the eighth transistor 85. The gate of the output transistor 89 is connected to the gate of the eighth transistor 83, so that the eighth transistor 83 and the output transistor 89 may form a current mirror circuit.

[0074] The output transistor 89 has a high voltage resistance structure of the second conductivity type (p-type).

[0075] The power supply startup monitoring circuit 11 may include a voltage source 59 connected between the first power supply line 19b and the second power supply line 19c. The voltage source 59 generates a voltage that is provided to the current sources for the load circuit 41d and the load circuit 47d, the first current source 25, and the second current source 35b.

[0076] 5 is a circuit diagram showing an example of a power supply startup monitoring circuit according to the present embodiment. The example power supply startup monitoring circuit 100b includes a simplified power supply circuit 91, a power supply monitoring circuit 93, a level shifter 95, a switch circuit 97, and a regulator 99.

[0077] As already explained, the simplified power supply circuit 91 has the first monitor output 21c, the second monitor output 21c, the first power supply output 23d, and the second power supply output 33d.

[0078] 5, the simplified power supply circuit 91 includes a current source CS1 and a Zener diode DLZ1 connected in series in a direction from a high voltage power supply (HV_VDD) to a low voltage power supply (GND). One end of the current source CS1 is connected to the high voltage power supply (HV_VDD), and the other end of the current source CS1 is connected to the cathode of the Zener diode DLZ1. The anode of the Zener diode DLZ1 is connected to the low voltage power supply (GND). The other end of the current source CS1 and the cathode of the Zener diode DLZ1 are connected to the first monitor output 21c and the gate of an n-type source follower transistor (VH_MN0) having a high voltage resistance structure. The drain of the source follower transistor (VH_MN0) is connected to the high voltage power supply (HV_VDD), and the source of the source follower transistor (VH_MN0) is connected to the first power supply output 23d. The back gate of the source follower transistor (VH_MN0) is well-isolated and connected to the first power supply output 23d.

[0079] The simplified power supply circuit 91 also includes a current source CS2, a p-type depletion transistor (PM0) with a low-voltage structure, a Zener diode DLZ2, and a pn diode (pdg) connected in series from the high-voltage power supply (HV_VDD) to the low-voltage power supply (GND). The pn diode (pdg) operates as a level shift circuit. One end of the current source CS2 is connected to the high-voltage power supply (HV_VDD), and the other end of the current source CS2 is connected to the source and gate of the p-type depletion transistor (MP0). The drain of the p-type depletion transistor (MP0) is connected to the cathode of the Zener diode DLZ1. The anode of the Zener diode DLZ1 is connected to the anode of the pn diode (pdg), and the cathode of the pn diode (pdg) is connected to the low-voltage power supply (GND). The back gate of the p-type depletion transistor (MP0) is well-isolated and connected to the source.

[0080] The drain of the p-type depletion transistor (MP0) and the cathode of the Zener diode DLZ1 are connected to the second monitor output 31c and the gate of an n-type source follower transistor (VH_MN1) with a high voltage resistance structure. The drain of the source follower transistor (VH_MN1) is connected to the high voltage power supply (HV_VDD), and the source of the source follower transistor (VH_MN1) is connected to the second power supply output 33d. The back gate of the source follower transistor (VH_MN1) is well-isolated and connected to the second power supply output 33d.

[0081] In the simple power supply circuit 91, the reverse characteristics of the Zener diode DLZ1 and the Zener diode DLZ2 are utilized, and the forward characteristics of a pn diode are utilized.

[0082] A pn diode can be replaced by a diode-connected (gate and drain connected) p-type field effect transistor, a diode-connected n-type field effect transistor, or a single pn diode can be replaced by multiple pn diodes connected in series.

[0083] Each of the Zener diode DLZ1 and the Zener diode DLZ2 can be replaced with a diode-connected p-type and / or n-type field effect transistor connected in series.

[0084] The power supply monitoring circuit 93 is configured to detect a change in the voltage from the first monitor output 21c and the second monitor output 31c.

[0085] The first monitor output 21c is connected to the source and back gate of a p-type first transistor (LV_MP1, well-isolated) with a low-voltage structure. The drain and gate of the first transistor (LV_MP1) are connected to one end of a current source CS3, and the other end of the current source CS3 is connected to a low-voltage power supply (GND).

[0086] The second monitor output 31c is connected to the source and back gate of a p-type second transistor (LV_MP2, well-isolated) with a low-voltage structure. The gate of the second transistor (LV_MP2) is connected to the gate of the first transistor (LV_MP1). The drain of the second transistor (LV_MP2) is connected to the drain and gate of an n-type third transistor (LV_MN3) with a low-voltage structure. The source and back gate of the third transistor (LV_MN3) are connected to the low-voltage power supply (GND).

[0087] The first monitor output 21c is connected to the source and back gate of a p-type fourth transistor (LV_MP4) with a low-voltage structure. The gate of the fourth transistor (LV_MP4) is connected to the gate of the second transistor (LV_MP2) and the gate and drain of the first transistor (LV_MP1). The drain of the fourth transistor (LV_MP4) is connected to the drain of an n-type fifth transistor (LV_MN5) with a low-voltage structure, and the gate of the fifth transistor (LV_MN5) is connected to the drain and gate of the third transistor (LV_MN3). The source and back gate of the fifth transistor (LV_MN5) are connected to the low-voltage power supply (GND).

[0088] The second monitor output 31c is connected to the source and back gate of a sixth p-type transistor (LV_MP6) with a low-voltage structure. The gate of the sixth transistor (LV_MP6) is connected to the drain of the fourth transistor (LV_MP4) and the drain of the fifth transistor (LV_MN5). The drain of the sixth transistor (LV_MP6) is connected to one end of a current source CS4. The other end of the current source CS4 is connected to a low-voltage power supply (GND).

[0089] A signal from the power supply monitoring circuit 93 controls the conduction / non-conduction of two switches (SW1, SW2) of the switch circuit 97 via a level shifter 95. The power supply monitoring circuit 93 monitors the voltages of the first monitor output 21c and the second monitor output 31c of the simple power supply circuit 91. The voltages of the second monitor output 21c and the second monitor output 31c of the simple power supply circuit 91 are provided to the respective gates of the source follower transistors (HV_MN0, HV_MN1) of the simple power supply circuit 91. The voltages of the second monitor output 21c and the second monitor output 31c are related to the source voltages of the source follower transistors (HV_MN0, HV_MN1).

[0090] After detecting that the simple power supply circuit 91 has been sufficiently started up, the power supply monitoring circuit 93 turns on the two switches (SW1, SW2) of the switch circuit 97, and the voltage of the simple power supply circuit 91 is applied to the circuit within the regulator 99.

[0091] The reverse characteristics of the Zener diode DLZ1 and the Zener diode DLZ2 are related to the conduction threshold of the switch circuit 97.

[0092] The first power supply output 23d can provide a voltage greater than the output voltage of the regulator 99, or can provide a voltage smaller than the output voltage of the regulator 99. Also, the second power supply output 33d can provide a voltage greater than the output voltage of the regulator 99, or can provide a voltage smaller than the output voltage of the regulator 99. Exemplary voltages of the first power supply output 23d and the second power supply output 33d can be approximately half the potential difference between the high voltage power supply (HV_VDD) and the low voltage power supply (GND).

[0093] Fig. 6 is a circuit diagram showing a circuit that does not include the power supply monitoring circuit of Fig. 5. For circuit elements in Fig. 6, the reference numerals used in Fig. 1 and Fig. 5 are used where possible to omit redundant description. Circuit 100c includes a simplified power supply circuit 91 and a regulator 99. Circuit 100c does not include a power supply monitoring circuit 93.

[0094] FIG. 7 is a diagram showing the operation of the reset circuit in the circuit of FIG.

[0095] When the power supply voltage for the first power supply line 19b and the second power supply line 19c is started, the simplified power supply circuit 91 operates to generate a voltage (v4v_ana) at the first power supply output 23d and a voltage (v4v_dig) at the second power supply output 23d.

[0096] The reference voltage circuit 71 and the error amplifier circuit 73 are powered by the voltage (v4v_ana). The comparator (COMP1) of the reset circuit 75 is powered by the voltage (v4v_dig). The reference voltage (VR1P0) of the reference voltage circuit 71 and the second feedback voltage (Vtree) from the voltage divider circuit 20 are applied to the respective inputs of the comparator (COMP1). The second feedback voltage (Vtree) can be constituted, for example, by a variable resistor, which makes it possible to adjust the period voltage of the second feedback voltage (Vtree).

[0097] When the power supply voltage for the first power supply line 19b and the second power supply line 19c is started, the regulator 99 operates and the simplified power supply circuit 91 operates independently of the regulator 99. When the power supply voltage is started, as shown in FIG. 7, if the second feedback voltage (Vtree) from the regulator 99 intersects with the reference voltage (VR1P0) of the reference voltage circuit 71, the reset circuit 75 generates a reset signal RESET.

[0098] As can be seen from Fig. 3 (and Fig. 1), in the power supply activation monitoring circuit 100b (and 11), after the power supply monitoring circuit 93 detects the activation of the simple power supply circuit 91, the simple power supply circuit 91 is connected to the regulator 99. After this connection, the regulator 99 starts operating.

[0099] Fig. 8 is a circuit diagram showing a circuit including a power supply monitoring circuit, a simple power supply circuit, a switch circuit, and a regulator. Referring to Fig. 8, a circuit 100c is shown. This circuit 100c includes a simple power supply circuit 91, a level shifter 95, a switch circuit 97, and a regulator 99, and further includes a power supply monitoring circuit 94 instead of the power supply monitoring circuit 93 of Fig. 5.

[0100] The power supply monitoring circuit 94 is connected to a high power supply line (HV_VDD) and a low power supply line (GND). The power supply monitoring circuit 94 includes a current mirror circuit MR0 connected to a power supply line, for example, the high power supply line (HV_VDD). The current mirror circuit MR0 has a first end connected to a current source CS5 to pass the current of the current source CS5, and a second end to pass the mirror current flowing through the first end. When a Zener diode DLZ3 is connected between the first end of the current mirror circuit MR0 and the current source CS5, a low-voltage structure can be provided for the field effect transistors (MP2, MP3) connected to the first end of the current mirror circuit MR0. A second end of the current mirror circuit MR0 is connected to a current source CS6. The current source CS6 provides a constant current Ibias. A high-voltage structure is provided for the field effect transistor (HV_MP1) directly connected to the second end of the current mirror circuit MR0. A shared node between the second end of the current mirror circuit MR0 and the current source CS6 is connected to the output of the power supply monitoring circuit 94. The output of the power supply monitoring circuit 94 is connected to a level shifter 95 .

[0101] The power supply monitoring circuit 94 includes a shunt circuit 92 connected to its output, and an exemplary shunt circuit 92 may include a series connection of multiple diode-connected field effect transistors (M0, M1, M2). The shunt circuit 92 is connected in parallel to a current source CS6.

[0102] The exemplary current mirror circuit MR0 may include a cascode current mirror circuit. The transistors (MP1, MP2, MP3) of the cascode current mirror circuit can be provided with a low voltage resistance structure, and the transistor (HV_MP1) of the cascode current mirror circuit can be provided with a high voltage resistance structure.

[0103] In the power supply monitoring circuit 93 of FIG. 3, a low-voltage structure can be provided for all the field-effect transistors.

[0104] The operation of the power supply monitoring circuit 94 will be described with reference to FIG. 8. When the power supply voltage exceeds the voltage at which the current mirror circuit MR0 can operate during start-up of the power supply voltage, the current mirror circuit MR0 operates to generate a current I1 (I1>Ibias) at the second terminal as a mirror current. While the current mirror circuit MR0 operates to cause the second terminal of the current mirror circuit MR0 to flow the current I1, when the voltage at the second terminal exceeds the conducting voltage of the shunt circuit 92, the current flowing at the second terminal of the current mirror circuit MR0 flows to both the shunt circuit 92 and the current source CS6. The voltage at the second terminal of the current mirror circuit MR0 can be an intermediate voltage between the voltage of the high voltage line and the conducting voltage of the shunt circuit 92. The shunt circuit 92 limits the voltage applied to the current source CS6.

[0105] The output of the power supply monitor circuit 94 is connected to a level shifter 95, which converts the intermediate voltage to a full swing voltage signal (OUT).

[0106] According to the above embodiment, it is possible to provide the power supply startup monitoring circuit 11 that can monitor the startup of the additional power supply circuit when the external power supply is started up.

[0107] As described above, the present embodiment has various aspects as follows.

[0108] A power supply startup monitoring circuit according to a first aspect of the present embodiment is a first power supply circuit including a first bias circuit connected between a first power supply line and a second power supply line different from the first power supply line, and a first source follower circuit having a first power supply output, wherein the first bias circuit includes a first portion and a second portion connected in series in a direction from one of the first power supply line and the second power supply line to the other, and a first monitor output, the first portion includes a first current source, the second portion includes a first load circuit, the first monitor output is connected to a first shared node of the first portion and the second portion, and the first monitor output is connected to an input of the first source follower circuit, a second bias circuit connected between the first power supply line and the second power supply line, and a second source follower circuit having a second power supply output, wherein the second bias circuit includes a first portion and a second portion connected in series in a direction from one of the first power supply line and the second power supply line to the other, and a second monitor output, a second power supply circuit, the first portion including a second current source and at least one first level shift device connected in series, the second portion including a second load circuit and at least one second level shift device connected in series, the second monitor output connected to a second shared node of the first portion and the second portion, the second monitor output connected to an input of the second source follower circuit; and a detection circuit connected to the second power supply line, the first monitor output, and the second monitor output, the detection circuit configured to operate at a voltage that does not exceed a larger potential difference of a potential difference between the second power supply line and the first monitor output and a potential difference between the second power supply line and the second monitor output, the detection circuit having a detection output that detects a start-up of a power supply voltage associated with the first power supply line and the second power supply line based on a difference between a voltage change of the first monitor output and a voltage change of the second monitor output, and provides a detection result, the difference occurring upon the start-up of the power supply voltage.

[0109] In a power supply startup monitoring circuit of a second aspect according to the first aspect of this embodiment, the detection circuit includes a first circuit connected between the first monitor output and the second power supply line and having a first output, and a second circuit connected between the second monitor output and the second power supply line and having a second output, the first circuit includes a second current source and a first transistor of a first conductivity type connected in series in a direction from the second power supply line to the first monitor output, the first output is connected to a shared node of the second current source and the first transistor, the second circuit includes a load circuit and a second transistor of the first conductivity type connected in series in a direction from the second power supply line to the second monitor output, the second output is connected to a shared node of the load circuit and the second transistor, and gates of the first transistor and the second transistor can be connected to each other.

[0110] In a power supply startup monitoring circuit of a third aspect according to the second aspect of this embodiment, the first source follower circuit includes a source follower transistor of a second conductivity type different from the first conductivity type, and the source follower transistor of the first source follower circuit has a gate connected to the first monitor output and a drain connected to the first power supply line, and the second source follower circuit includes a source follower transistor of the second conductivity type, and the source follower transistor of the second source follower circuit can have a gate connected to the second monitor output and a drain connected to the first power supply line.

[0111] In a power supply startup monitoring circuit according to the second aspect or the fourth aspect according to the third aspect of this embodiment, the detection circuit includes a determination circuit having a first input and a second input respectively connected to the first output of the first circuit and the second output of the second circuit, and the determination circuit may include a comparison circuit connected to the first input and the second input.

[0112] In a power supply startup monitoring circuit of a fifth aspect according to the fourth aspect of this embodiment, the load circuit of the second circuit includes a third transistor having a gate and a drain connected to the second output of the second circuit, the comparison circuit includes a fourth transistor of the first conductivity type and a fifth transistor of a second conductivity type different from the first conductivity type, the fourth transistor and the fifth transistor are connected in series in a direction from the second power supply line to the first monitor output, and the fourth transistor operates in response to a signal from the first output of the first circuit, and the fifth transistor operates in response to a signal from the second output of the second circuit.

[0113] In the power supply activation monitoring circuit according to the fourth or fifth aspect of the present embodiment, the comparison circuit can be connected between the first monitor output and the second power supply line.

[0114] In a power supply startup monitoring circuit of a seventh aspect according to the fifth aspect or the sixth aspect of this embodiment, the detection circuit includes an output circuit, and the output circuit includes a sixth transistor and a load circuit connected in series between the second monitor output and the second power supply line, and the output circuit can be configured to amplify a comparison signal from the comparison circuit.

[0115] In a power supply startup monitoring circuit according to an eighth aspect of any one of the first to seventh aspects of this embodiment, the first load circuit includes a first Zener diode, the second load circuit includes a second Zener diode, and at least one of the second level shift devices includes a diode.

[0116] In a power supply startup monitoring circuit according to a ninth aspect in accordance with any one of the first to eighth aspects of the present embodiment, the at least one level shift device may include at least one depletion transistor.

[0117] The power supply startup monitoring circuit of a tenth aspect according to any one of the first to ninth aspects of this embodiment further includes a regulator having a first input and a second input, and the regulator may include a first signal generating circuit powered by the first power supply circuit, a second signal generating circuit powered by the second power supply circuit, and a power supply circuit connected between the first power supply line and the second power supply line.

[0118] The power supply startup monitoring circuit of an eleventh aspect according to the tenth aspect of this embodiment further includes a first switch connected between the first power supply output of the first source follower circuit and the first input of the regulator, a second switch connected between the second power supply output of the second source follower circuit and the second input of the regulator, and a level shifter connected between the first power supply line and the second power supply line and receiving a signal from the detection output, and the level shifter may have a control output configured to control the conduction / non-conduction of the first switch and the second switch.

[0119] In the power supply startup monitoring circuit of a twelfth aspect according to the tenth or eleventh aspect of this embodiment, the first signal generating circuit can include a reference voltage circuit connected between the second power supply line and the first input.

[0120] In the power supply startup monitoring circuit of a thirteenth aspect according to the twelfth aspect of this embodiment, the first signal generating circuit further includes an error amplifier circuit connected between the second power supply line and the second input, and the error amplifier circuit can have a reference input that receives a reference voltage from the reference voltage circuit, and a feedback input configured to receive a first feedback voltage from a voltage divider circuit that is connected to the output of the regulator.

[0121] The power supply startup monitoring circuit of a fourteenth aspect according to the thirteenth aspect of this embodiment further includes a level shift circuit, the level shift circuit including a seventh transistor of a second conductivity type and an eighth transistor of a first conductivity type different from the second conductivity type, which are connected in series in a direction from the second power supply line to the first power supply line, the seventh transistor operates in response to a signal from an output of the error amplifier circuit, the eighth transistor causes a current to flow through the seventh transistor, the eighth transistor has a gate and a drain connected to each other, and the gate and the drain of the eighth transistor can be connected to an output of the level shift circuit.

[0122] In the power supply startup monitoring circuit of the 15th aspect according to the 14th aspect of this embodiment, the level shift circuit may further include a 9th transistor of the second conductivity type connected between the 7th transistor and the 8th transistor, and the 9th transistor may have a gate connected to the first input or the second input.

[0123] In the power supply startup monitoring circuit according to the fourteenth or fifteenth aspect of this embodiment, the regulator may include an output transistor connected to the output of the level shift circuit.

[0124] In a power supply startup monitoring circuit of a 17th aspect according to any one of the 12th to 16th aspects of this embodiment, the second signal generating circuit includes a reset circuit, and the reset circuit can generate a reset signal in response to the output of the regulator being started.

[0125] In the power supply startup monitoring circuit of the 18th aspect according to the 17th aspect of this embodiment, the reset circuit includes a comparator connected between the second power supply line and the second input, and the comparator can receive a second feedback voltage from a voltage divider circuit connected to the output of the regulator and a reference voltage from the reference voltage circuit.

[0126] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0127] 11...Power supply start-up monitoring circuit, 13...1st power supply circuit, 15...Second power supply circuit, 17 Detection circuit, 17b First input, 17c...Second input, 17d Detection output, 19b...1st power line, 19c...Second power line, 21 - First bias circuit, 21c 1st monitor output, 23 - First source follower circuit, 23c Control input, 23d Power output, 25...first current source, 27...first load circuit, 31... second bias circuit; 31c Second monitor output, 33 - second source follower circuit; 33c Control input, 33d Power output, 35...first part, 35b...Second current source, 35c···First level shift device, 37...second part, 37b...Second load circuit, 37c...Second level shift device, 41...1st circuit, 41b First output, 41d... Load circuit, 43...2nd circuit, 43b...Second output, 43d... Load circuit, 45...Third circuit, 45b Third output, 47...4th circuit, 47b 4th output, 47d Load circuit, 51...judgment circuit, 53...comparison circuit, 53b... Output, 55 Output circuit, 59... Voltage source, 61 Regulator, 61b... Output, 61c... First input, 61d...Second input, 63...first signal generation circuit, 65...Second signal generation circuit, 67... Power supply circuit, 67b First switch, 67c...Second switch, 69...Level shifter, 71... Reference voltage circuit, 73 Error amplifier circuit, 73c···First feedback input, 73d Reference input, 75 Reset circuit, 75b Reset output, 75c···Second feedback input, 75d Reference input, 76 Comparator, 77 Level shift circuit, 77b Feedback input, 77c Level shift output, 77d Bias input, 79 Regulator output circuit, 83...Load circuit, 89 Output transistor, 91...Simple power supply circuit, 92...Shunt circuit, 93, 94...power supply monitoring circuit, 95 Level shifter, 97 Switch circuit, 99 Regulator, 100b Power supply startup monitoring circuit, 100c...circuit, CS1, CS2, CS3, CS4, CS5, CS6...Current source, DLZ1, DLZ2, DLZ3...Zener diodes, FETN1, FETN2: Field effect transistors, I1...current, Ibias...constant current, MR0: Current mirror circuit, RESET: Reset signal.

Claims

1. a first power supply circuit including a first bias circuit connected between a first power supply line and a second power supply line different from the first power supply line, and a first source follower circuit having a first power supply output, the first bias circuit including a first portion and a second portion connected in series in a direction from one of the first power supply line and the second power supply line to the other, and a first monitor output, the first portion including a first current source, the second portion including a first load circuit, the first monitor output being connected to a first shared node of the first portion and the second portion, and the first monitor output being connected to an input of the first source follower circuit; a second power supply circuit including a second bias circuit connected between the first power supply line and the second power supply line, and a second source follower circuit having a second power supply output, the second bias circuit including a first portion and a second portion connected in series in a direction from one of the first power supply line and the second power supply line to the other, and a second monitor output, the first portion including a second current source and at least one first level shift device connected in series, the second portion including a second load circuit and at least one second level shift device connected in series, the second monitor output being connected to a second shared node of the first portion and the second portion, and the second monitor output being connected to an input of the second source follower circuit; a detection circuit connected to the second power supply line, the first monitor output, and the second monitor output, the detection circuit configured to operate at a voltage not exceeding a larger potential difference of a potential difference between the second power supply line and the first monitor output and a potential difference between the second power supply line and the second monitor output, the detection circuit having a detection output for detecting start-up of a power supply voltage related to the first power supply line and the second power supply line based on a difference between a voltage change of the first monitor output and a voltage change of the second monitor output, the difference occurring upon start-up of the power supply voltage; Equipped with Power supply start-up monitoring circuit.

2. the detection circuit includes a first circuit connected between the first monitor output and the second power supply line and having a first output, and a second circuit connected between the second monitor output and the second power supply line and having a second output; the first circuit includes a second current source and a first transistor of a first conductivity type connected in series in a direction from the second power supply line to the first monitor output; the first output is connected to a shared node of the second current source and the first transistor; the second circuit includes a load circuit and a second transistor of the first conductivity type connected in series in a direction from the second power supply line to the second monitor output, the second output is connected to a shared node of the load circuit and the second transistor; the gates of the first transistor and the second transistor are connected to each other; 2. A power supply startup monitoring circuit as claimed in claim 1.

3. the first source follower circuit includes a source follower transistor of a second conductivity type different from the first conductivity type, the source follower transistor of the first source follower circuit having a gate connected to the first monitor output and a drain connected to the first power supply line; the second source follower circuit includes a source follower transistor of the second conductivity type, the source follower transistor of the second source follower circuit having a gate connected to the second monitor output and a drain connected to the first power supply line; 3. A power supply startup monitoring circuit as claimed in claim 2.

4. the detection circuit includes a determination circuit having a first input and a second input connected to the first output of the first circuit and the second output of the second circuit, respectively; the determination circuit includes a comparison circuit connected to the first input and the second input; 3. A power supply startup monitoring circuit as claimed in claim 2.

5. the load circuit of the second circuit includes a third transistor having a gate and a drain connected to the second output of the second circuit; the comparison circuit includes a fourth transistor of the first conductivity type and a fifth transistor of a second conductivity type different from the first conductivity type; the fourth transistor and the fifth transistor are connected in series in a direction from the second power supply line to the first monitor output, the fourth transistor operates in response to a signal from the first output of the first circuit; the fifth transistor operates in response to a signal from the second output of the second circuit; 5. A power supply startup monitoring circuit as claimed in claim 4.

6. the comparison circuit is connected between the first monitor output and the second power supply line; 5. A power supply startup monitoring circuit as claimed in claim 4.

7. the detection circuit includes an output circuit; the output circuit includes a sixth transistor and a load circuit connected in series between the second monitor output and the second power supply line, the output circuit is configured to amplify the comparison signal from the comparison circuit; 5. A power supply startup monitoring circuit as claimed in claim 4.

8. the first load circuit includes a first Zener diode; the second load circuit includes a second Zener diode; At least one of the second level shifting devices includes a diode.

2. A power supply startup monitoring circuit as claimed in claim 1.

9. At least one of the first level shifting devices includes at least one depletion transistor.

2. A power supply startup monitoring circuit as claimed in claim 1.

10. a regulator having a first input and a second input; The regulator comprises: a first signal generating circuit powered by the first power supply circuit; a second signal generating circuit powered by the second power supply circuit; and a power supply circuit connected between the first power supply line and the second power supply line; Including, 2. A power supply startup monitoring circuit as claimed in claim 1.

11. a first switch connected between the first power supply output of the first source follower circuit and the first input of the regulator; a second switch connected between the second power supply output of the second source follower circuit and the second input of the regulator; a level shifter connected between the first power supply line and the second power supply line and receiving a signal from the detection output; Further comprising: The level shifter has a control output configured to control the conduction / non-conduction of the first switch and the second switch.

11. A power supply startup monitoring circuit as claimed in claim 10.

12. the first signal generating circuit includes a reference voltage circuit connected between the second power supply line and the first input; 11. A power supply startup monitoring circuit as claimed in claim 10.

13. the first signal generating circuit further includes an error amplifier circuit connected between the second power supply line and the second input; the error amplifier circuit has a reference input for receiving a reference voltage from the reference voltage circuit, and a feedback input configured to receive a first feedback voltage from a voltage divider circuit connected to an output of the regulator; 13. A power supply start-up monitoring circuit as claimed in claim 12.

14. Further comprising a level shift circuit, the level shift circuit includes a seventh transistor of a second conductivity type and an eighth transistor of a first conductivity type different from the second conductivity type, the seventh transistor and the eighth transistor being connected in series in a direction from the second power supply line to the first power supply line, the seventh transistor operates in response to a signal from an output of the error amplifier circuit; The eighth transistor causes a current to flow through the seventh transistor, the eighth transistor has a gate and a drain connected to each other; the gate and the drain of the eighth transistor are connected to the output of the level shift circuit; 14. A power supply start-up monitoring circuit as claimed in claim 13.

15. the level shift circuit further includes a ninth transistor of the second conductivity type connected between the seventh transistor and the eighth transistor, the ninth transistor has a gate connected to the first input or the second input; 15. A power supply start-up monitoring circuit as claimed in claim 14.

16. the regulator includes an output transistor connected to the output of the level shift circuit; 15. A power supply start-up monitoring circuit as claimed in claim 14.

17. the second signal generating circuit includes a reset circuit; The reset circuit generates a reset signal in response to the output of the regulator being activated.

13. A power supply start-up monitoring circuit as claimed in claim 12.

18. the reset circuit includes a comparator connected between the second power supply line and the second input; the comparator receives a second feedback voltage from a voltage divider circuit connected to an output of the regulator and a reference voltage from the reference voltage circuit; 20. A power supply start-up monitoring circuit as claimed in claim 17.

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