System and method for executing variational quantum eigensolver algorithm with quantum computer

Abstract

To provide systems and methods for executing variational quantum eigensolver algorithms with a quantum computer.SOLUTION: A method includes steps 502-508 for generating, by a classical computing device, a quantum circuit. The quantum circuit includes: a subset of qubits including at least three of the qubits arranged to execute a linear string of gates; a first layer having a vertically centered arrangement of at least three Ry gates on each of the linear strings of gates for each of the subset of qubits; a second layer having a sequence of entangling gate followed by a single qubit gate on each linear string of gates where each entangling gate entangles the linear string of gates of the subsequent qubit; and a third layer having the step shape of the second layer. The method also includes a step 510 of receiving parameters associated with a physical environment.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to executing quantum algorithms with quantum computing devices that utilize quantum circuits. [Background technology]

[0002] Classical computers can be utilized to generate quantum circuits to execute quantum algorithms on quantum computers such as noisy intermediate-scale quantum (NISQ) devices. The variational quantum eigensolver (VQE) algorithm may be one of the most promising algorithms for implementation on NISQ devices. However, the VQE algorithm suffers from a number of problems, such as the Baren Plateau, and thus algorithm development has proven challenging. Summary of the Invention [Means for solving the problem]

[0003] One or more computer systems can be configured to perform particular operations or actions by installing on the system software, firmware, hardware, or a combination thereof that causes the system to perform actions during operation. One or more computer programs can be configured to perform particular operations or actions by including instructions that, when executed by a data processing device, cause the device to perform the actions.

[0004] In one general aspect, the method may include generating, by a classical computer, a quantum circuit having a subset of qubits including at least three qubits from a plurality of qubits arranged to perform a linear gate series, the subset of qubits being arranged vertically and performing the linear gate series horizontally. The method may further include a first layer having a vertically centered arrangement of at least three Ry gates on each of the linear gate series for each of the subset of qubits. The method may also include a second layer having a step shape of Cz entanglement gates followed by an Ry gate on each linear gate series, the entanglement gates entangle the linear gate series of the subsequent qubit. The method may further include a third layer having the step shape of the second layer, the third layer not vertically overlapping the second layer. The method may include receiving parameters related to the physical environment. The method may also include performing, by the quantum computer, a VQE based on the parameters of the quantum circuit and the physical environment. The method may further include outputting, via the quantum computer, an approximation of the base state of the physical environment.

[0005] Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs stored on one or more computer storage devices, each configured to perform the actions of the method.

[0006] Implementations may include one or more of the following features. The method may further include initializing at least three Ry gates of the first layer based on random values ​​and initializing at least three Ry gates of the second layer with a value of 0. The method may further include initializing at least three Ry gates of the third layer based on negative values ​​of the Ry gates of the first layer on the respective gate columns. The method may further include an additional layer that may be included between the second layer and the third layer, where one or more Ry gates of the additional layer are initialized with a value of 0. The method may further include configuring a subset of the qubits into an entangled initial state before applying the parameterization circuit of FIG. 7 or FIG. 8. The entangled initial state may be a mean field state. The method may also include a case where the entangled initial state is not a product state. The method may further include a case where the rightmost Ry gate of the linear gate series associated with the third qubit of the subset of qubits is vertically centered with the rightmost Ry gate of the second qubit of the subset of qubits. The method may also include a case where the total number of layers is odd. The method may further include a case where the quantum computer is a noisy medium-scale quantum computer. Implementations of the described techniques may include hardware, methods or processes, or computer tangible media. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 illustrates operations acting on an exemplary qubit. [Diagram 2] FIG. 1 illustrates a schematic example of a quantum computer. [Diagram 3] FIG. 1 illustrates a schematic exemplary method for generating control signals for performing operations on a quantum computing device and processing measurement signals from the quantum computing device. [Figure 4]FIG. 1 illustrates a schematic example of a hybrid system including classical and quantum computing devices. [Diagram 5] 1 is a flowchart of an exemplary process for performing VQE based on executing a quantum circuit on a quantum computing device. [Figure 6] 1 is a flowchart of an exemplary process for initializing a quantum circuit. [Figure 7] FIG. 1 illustrates an exemplary arrangement of a quantum circuit. [Figure 8] FIG. 1 illustrates an exemplary initialization of a layer of a quantum circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The embodiments of the present disclosure are described herein. However, it should be understood that the disclosed embodiments are merely examples, and that other embodiments can take various and alternative forms. The drawings are not necessarily to scale, and some features may be exaggerated or minimized to show the details of certain components. Therefore, specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to use the embodiments in various ways. As those skilled in the art will appreciate, various features illustrated and described with reference to any one of the drawings can be combined with features illustrated in one or more other drawings to produce embodiments not explicitly illustrated or described. The combinations of the illustrated features provide representative embodiments for typical applications. However, various combinations and modifications of features consistent with the teachings of the present disclosure may be desirable for specific applications or implementations.

[0009] As used herein, "a," "an," and "the" refer to both singular and plural referents unless the context clearly dictates otherwise. By way of example, "a processor" programmed to perform various functions may refer to one processor programmed to perform each and every function, or to two or more processors collectively programmed to perform various functions.

[0010] The VQE algorithm may be one of the most promising algorithms for implementation on current NISQ devices. However, the VQE algorithm suffers from a number of problems, such as the Baren plateau, and therefore algorithm development has proven difficult. The systems and methods described herein may be configured to provide a good ground state approximation with a shallow circuit depth suitable for implementation on current NISQ devices.

[0011] The systems and methods described herein can be configured to utilize a VQE optimization strategy that can avoid the Baren Plateau problem and has a very shallow circuit depth. The systems and methods described herein can utilize configurations to generate good ground state approximations on current NISQ devices without applying any error mitigation techniques. The systems and methods described herein can demonstrate the potential for VQE algorithms to leverage the capabilities of NISQ devices, highlighting the importance that algorithm development plays in demonstrating the full potential of quantum hardware.

[0012] VQE algorithms can suffer from certain problems. Furthermore, VQE algorithms can leverage the capabilities of both classical and quantum computers, and traditional VQE implementations on current quantum devices have underperformed. Despite some advances, traditional implementations have not developed VQE algorithms that can leverage the capabilities of current NISQ devices.

[0013] The systems and methods described herein propose a VQE optimization strategy that produces good ground-state approximations with low circuit depth and low gate count, making the strategy advantageous for implementation in current NISQ devices.

[0014] Three main elements of the systems and methods described herein may include a mean-field starting state, a shallow circuit structure, and identity block initialization on a parameterized set of gates.

[0015] The systems and methods described herein may take advantage of mean-field starting states by initializing the circuit to classically inspired states that are not product states. In some embodiments, the choice of starting states may affect the trainability of shallow-depth hardware-efficient type ansatz. For example, little prior knowledge of the input states may help avoid the effects of the Baren plateau in VQE optimization. Additionally, the systems and methods described herein may be configured to take advantage of entanglement of parameterized gates.

[0016] The systems and methods described herein may be configured to utilize shallow circuit structures. The systems and methods described herein may be configured to utilize a particular circuit architecture that is hardware friendly due to its shallow circuit depth and linear entanglement map.

[0017] The systems and methods described herein may identify block initialization on a set of parameterized gates. In some embodiments, identity block initialization may select parameterized gates such that the overall partial operation of the parameterized portion of the circuit remains close to the identity, which may aid in optimizing VQE. In some embodiments, the parameterized gates may be arranged in layers, and the starting values ​​of the first layer may be randomly selected, the starting values ​​of the last layer may be set to a negative value from the starting values ​​of the first layer, and the starting values ​​of the intermediate layers may be set to zero values.

[0018] The systems and methods described herein may combine all three of the above elements, resulting in a VQE algorithm with shallow circuit depth and a high number of gate entanglements, which may avoid post-selection effects on parameterized gate starting values ​​and the associated Baren's Plateau problem.

[0019] Although the systems and methods described herein may be configured to utilize only a three-qubit circuit with two iterations, the systems and methods described herein may be generalized to larger circuit sizes. In some embodiments, the systems and methods described herein may set the last layer of the Ry gate, i.e., θ6, θ7, and θ8, to −θ1, −θ2, and −θ3, respectively, as shown in FIG. 8. The systems and methods described herein may be configured to utilize an even number of iterations, and the parameterized gates between the first and last application of the Ry gate may be set to all 0, and thus the Cz entanglement gates may be cancelled out. As a result, the sub-operations of the parameterized portion of the circuit may be initialized to be identity operators.

[0020] Operations acting on qubit states can be single-qubit or multi-qubit operations, generally represented as gates on a quantum circuit. A single-qubit operation may change the state of a single qubit to a particular superposition corresponding to a rotation of the vector |X>, as shown in FIG. 1. For example, in a superconducting quantum computer, this may be accomplished by a microwave pulse, or in a trapped-ion quantum computer, by illuminating the ion with a laser beam. A multi-qubit operation may create an entangled state between two or more qubits. For example, in a superconducting quantum computer, this may be accomplished by connecting the qubits by an intermediate electrical coupling circuit, or in a trapped-ion quantum computer, by controlling the collective vibration of the trapped ions.

[0021] In general, to prepare operations to solve a given problem, each quantum mechanical representation of the problem can be transformed into a quantum circuit, and the quantum circuit can be utilized to prepare a solution to the given problem. After the preparation of a given solution, i.e., after the application of the operations to the quantum circuit, a projective measurement of all individual qubits is performed, returning either 0 or 1 for each qubit. In a NISQ device, this measurement is achieved by applying a hardware-specific readout protocol of a sequence of readout operations including control pulses and monitoring the response to the control pulses. For example, a superconducting qubit may be coupled to a hardware resonator. The measured shift in the resonator frequency allows the state of the qubit to be identified, since this shift depends on the state of the coupled qubit. In the case of trapped ions, for example, an optical readout may be used, e.g., the state of the qubit is 1 if the ion emits light and 0 if the ion does not emit light, or vice versa. In this way, qubits may be used to implement logic circuits or gates, such as classical computing devices.

[0022] A schematic example of a quantum computer is shown in FIG. 2. The quantum computing device 100 shown in FIG. 2 includes a quantum register 104 configured to perform a quantum computation, an operation unit 106 configured to operate the quantum register, in particular the quantum elements forming the qubits, and a readout unit 108 configured to collect measurement signals from the quantum register 104 to read out the qubits after a quantum mechanical computation. The operation unit 106 provides, in particular, an operation signal for operating the quantum register, which is generated based on a received control signal determined based on the respective operation to be performed on the qubits. In some embodiments, a feedback loop can be provided between the operation unit 106 and the measurement unit 108. In contrast to classical computing, where one measurement cycle provides the state of a transistor, quantum computing involves performing multiple measurement cycles to provide a probability density or probability of a qubit state.

[0023] The quantum register 104 can be based on different quantum elements representing quantum bits. In some embodiments, the quantum bits may be implemented by photons as quantum elements. Such an optical quantum computing device may include a laser that generates photons that are provided to a waveguide. A beam splitter may be provided to manipulate the photon state based on a manipulation signal, such as a mechanical rotation applied to a mirror. In such an embodiment, the measurement unit 108 may be a photon detector and the measurement signal may be a photon.

[0024] In other embodiments, the qubits can be implemented by electronic states of ions trapped in a magnetic field. In such a case, the manipulation unit 106 can utilize a laser and the manipulation signal can provide a control laser pulse. Furthermore, in this case, the readout unit 108 can be a photon detector combined with a readout laser pulse and the measurement signal 102 can be a photon. Other qubit implementations can be based on superconductors as quantum elements, semiconductor materials with anyons as quantum elements, etc.

[0025] 3 shows a schematic exemplary method for generating control signals for performing operations on a quantum computing device and for processing measurement signals from the quantum computing device. In most embodiments of quantum computing devices known to date, the control signals for the quantum computing device are prepared on a classical computing device, and the measurement signals provided by the quantum computing device are further processed on the classical computing device. However, as quantum computing devices mature, other embodiments are possible.

[0026] In order to generate control signals for performing operations on the quantum computing device, a problem to be solved with the aid of the quantum computing device is provided in step S10, specifically as a quantum circuit. Such a problem may, for example, determine the base state of a particular chemical formula. Other problems may include applying a VQE algorithm to a physical environment. Based on the problem to be solved, a behavioral description of the problem or sub-problem may be generated in step S12 (such as a quantum circuit), the behavioral description including operations to be applied to the qubits (such as gates) of the quantum computer to solve the problem in the quantum mechanical calculation. Furthermore, the behavioral description may include a reference state that allows generating a representation of an initial qubit state on the quantum computer, where further operations are applied by manipulating the qubit states on the quantum computer. Based on the behavioral description, a control signal may be generated in step S14, for example, to control the quantum computer by providing a control signal to an operation unit, which may then operate the qubit states based on the control signal. Then, in step S16, the operation unit applies an operation operation to an individual qubit or multiple qubits of the quantum computer, and based on the operation operation the qubits perform the quantum mechanical calculation. After the manipulation, a measurement signal can be generated to determine the result of the quantum mechanical calculation in step S18. This step can include reading out, e.g., measuring, the qubit state after applying the manipulation operation to the initial qubit state. Then, in step S20, the measurement signal can be converted to a measured quantity on a classical computer and, in the case of a sub-problem, fed back to the problem to be solved. Finally, in step S22, the result of the problem calculation, including the quantum mechanical calculation, can be provided to a classical computing device.

[0027] FIG. 4 shows a schematic example of a hybrid system including a classical computing device and a quantum computing device. As described with respect to the method shown in FIG. 3, a quantum computing device is often used in conjunction with a classical computing device. As shown in FIG. 4, the problem preparation system can be realized as a classical computing device 110 that performs steps S10, S12, S20, S22 of the method shown in FIG. 3, for example. A control unit can then be provided as an interface between the classical computing device 110 and the quantum computing device 100, and the control unit can also be a classical computing device that performs step S14, for example. The control unit can then be communicatively coupled to an operation unit 106 that can control a manipulator of the quantum computing device. The operation unit 106 can also be realized as classical control hardware for controlling certain hardware components of a classical computing device, for example a quantum computer that performs operations on quantum bits. However, the operation unit 106 is generally considered to be part of the quantum computer since it directly affects the quantum register. The quantum computing device 100 is configured to perform a quantum operation S16, in particular by the operation of the quantum bits of the quantum register. The measurement unit 108, which is also generally considered to be part of a quantum computing device, can then perform step S18 by utilizing classical hardware. The measurement unit 108 can then be communicatively coupled to a preparation system for further processing of the measurement signal.

[0028] In some embodiments, classical computing device 110 may utilize one or more processors to execute computer program instructions stored in a non-transitory computer-readable medium communicatively coupled to the processor of classical computing device 110 or to the operating portion 106 of quantum computing device 100.

[0029] 5 is a flow chart of an example process 500 for performing a VQE algorithm based on executing a quantum circuit on quantum computing device 100. In some embodiments, one or more process blocks of FIG. 5 may be performed by a processor of classical computing device 110 or an operating unit 106 of quantum computing device 100.

[0030] 5, process 500 may include generating, by a classical computer, a quantum circuit having a subset of qubits including at least three qubits from a plurality of qubits arranged to perform a linear array of gates, the subset of qubits arranged vertically and performing the linear array of gates horizontally (block 502). In some embodiments, a processor of classical computing device 110 may be configured to generate a shallow state circuit having a shallow circuit depth and a number of gates.

[0031] 5, process 500 may further include generating a first tier for the quantum circuit having a vertically centered arrangement of at least three single qubit gates (e.g., Ry gates, Rz gates, and Rx gates) on each of the linear gate columns for each of the subset of qubits (block 504). In some embodiments, the processor of classical computing device 110 may arrange the qubits of the subset of qubits along a grid, with each qubit assigned a number of gates that transform the state of the qubit as it moves from an initial setting position at the left start position to a measurement position at the right. In some embodiments, the state of each qubit is measured by measurement unit 108 after the qubits perform their assigned operations through their respective gate columns.

[0032] As shown in FIG. 5, process 500 may also include generating a second layer for the quantum circuit having a sequence of entanglement gates (e.g., Cz gates, Cx gates, and Cy gates) followed by a single qubit gate on each linear gate row, where the entanglement gate entangles the linear gate row of the subsequent qubit (block 506). In some embodiments, the processor of classical computing device 110 may arrange the gates in layers on the linear gate row, stacking the layers from a left-hand starting position to a right-hand measurement position. In some embodiments, the controlled Cz gate applies a controlled Z gate to the target qubit based on the state of the control qubit. For example, when the control qubit is in a 0 state, the gate performs no action, but when the control qubit is in a 1 state, the gate applies a Pauli Z gate to the target qubit.

[0033] 5, process 500 may further include generating a third layer for the quantum circuit having the step shape of the second layer, where the third layer does not vertically overlap the second layer (block 508). In some embodiments, the processor of classical computing device 110 may include the third layer on a linear array of gates such that the rightmost gate of the second layer completes an operation on its respective qubit before the first gate of the third layer begins an operation on its respective qubit, as shown in FIG.

[0034] 5, process 500 may further include receiving a parameter associated with a physical environment (block 510). In some embodiments, the processor of classical computing device 110 may receive a parameter associated with one or more atoms in the physical environment. In some embodiments, the parameter may be associated with one or more atoms in the physical environment in which a chemical reaction may occur or is occurring.

[0035] 5, process 500 may further include running, by the quantum computer, a VQE algorithm based on parameters of the quantum circuit and the physical environment (block 512). In some embodiments, a subset of the qubits of quantum computing device 100 may be assigned to a linear array of gates of the quantum circuit. In some embodiments, the qubits may be initialized to a starting state, such as a mean-field starting state (i.e., a classically inspired state that is not a product state), that may generate some entanglement between two or more qubits.

[0036] 5, process 500 may further include outputting, via the quantum computer, an approximation of the base state of the physical environment (block 514). In some embodiments, the processor of classical computing device 110 may receive measurements from each of the qubits of the subset of qubits after all operations of the linear gate array read by measurement unit 108 have been performed.

[0037] Although Figure 5 illustrates example blocks of process 500, in some embodiments, process 500 may include more, fewer, different, or differently arranged blocks than those illustrated in Figure 5. Additionally or alternatively, two or more of the blocks of process 500 may be performed in parallel.

[0038] 6 is a flow chart of an example process 600 for initializing a quantum circuit. In some embodiments, one or more of the process blocks in FIG. 6 may be performed by a processor of classical computing device 110 or an operating unit 106 of quantum computing device 100.

[0039] 6, process 600 may include initializing at least three single qubit gates (e.g., an Ry gate, an Rz gate, and an Rx gate) of a first layer based on random values ​​(block 602). In some embodiments, the single qubit gate may be an Ry gate, and initializing the Ry gate associates a value with the Ry gate for the Ry gate's rotation operation. In some embodiments, the initialization value of the Ry gate may indicate a qubit rotation value that performs an operation about the y-axis of the respective qubit.

[0040] 6, process 600 may further include initializing at least three single qubit gates of the second layer with a value of 0 (block 604). In some embodiments, a value of the processor of classical computing device 110 may initialize the single qubit gates of the second layer with a value of 0. In some embodiments, the single qubit gates may be Ry gates, where an Ry gate initialized with a value of 0 indicates an operation of rotating the respective qubit about the y-axis by 0 radians.

[0041] 6, the process 600 may also include initializing at least three Ry gates in the last layer based on the negative values ​​of the first layer single qubit gates on the respective gate columns (block 606). In some embodiments, the value of the processor of the classical computing device 110 may initialize the single qubit gates in the last layer with the negative values ​​of the first layer. For example, the single qubit gates may be Ry gates, and when the Ry gates of the first Ry gates are initialized to 3.37 radians, the Ry gates of the last layer on the same linear path are initialized to -3.37 radians.

[0042] 6, process 600 may further include adding a layer to the quantum circuit between the second layer and the third layer (block 608). In some embodiments, the processor of the classical computing device 110 may further configure the quantum circuit to include an additional layer where the total number of layers is an odd number. In some embodiments, the additional layer mirrors the configuration and initialization of the second layer and is inserted in a position between the first layer and the last layer.

[0043] 6, the process 600 may include initializing one or more Ry gates of the additional layer with a value of 0 (block 610). In some embodiments, the processor of the classical computing device 110 may initialize the Ry gates of the additional layer to 0, where the Ry gates initialized with a value of 0 indicate an operation of rotating the respective quantum bit 0 radians around the y-axis.

[0044] Although Figure 6 illustrates example blocks of process 600, in some embodiments, process 600 may include more, fewer, different, or differently arranged blocks than those illustrated in Figure 6. Additionally or alternatively, two or more of the blocks of process 600 may be performed in parallel.

[0045] 7 illustrates an example arrangement 700 of a quantum circuit having two layers. The quantum circuit may be configured by a processor of a classical computing device 110.

[0046] 7, the constellation 700 may include a starting position 702 for each of a subset of qubits. In some embodiments, the qubits at the 702 positions are initialized to a starting state prior to execution of the VGE algorithm by the operator 106 of the quantum computing device 100.

[0047] 7, the arrangement 700 may also include a first layer 704 of gates comprised of Ry gates forming a straight line in the vertical direction. In some embodiments, this layer shape is not repeated and is only used for the first layer of the arrangement 700.

[0048] 7, the layout 700 may include a Cz gate 706 and an Ry gate 708. In some embodiments, the Cz gate 706 may be the first logic gate in a second layer of the layout 700, followed by an Ry gate 708. In some embodiments, the Cz and Ry gates are added to each of the linear gate columns and spaced apart to form a staircase structure.

[0049] 7, the arrangement 700 may include an Ry gate 710 in the rightmost position of the last linear gate column. In some embodiments, the Ry gate 710 is the only Ry gate in the second layer that is vertically symmetric with another Ry gate in the second layer.

[0050] 8 illustrates an example of initializing an uninitialized quantum circuit 800 to generate an initialized quantum circuit 850. The quantum circuit 800 may be initialized by a processor of the classical computing device 110.

[0051] As shown in FIG. 8, the uninitialized quantum circuit 800 consists of three layers: a first uninitialized layer 802, a second uninitialized layer 804, and a third uninitialized layer 806.

[0052] As further shown in FIG. 8, the initialized circuit 850 comprises three layers: a first initialized layer 852, a second initialized layer 854, and a last initialized layer 856. In some embodiments, the first initialized layer 852 may be initialized with random values. For example, Ry gate 0, Ry gate 1, and Ry gate 2 are initialized with 3.37, 2.29, and 5.41, respectively. In some embodiments, the second initialized layer 854 may be initialized with a value of 0. In some embodiments, the last initialized layer 856 may be initialized with the negative of the corresponding Ry gate of the first initialized layer 852. For example, Ry gate 6 is initialized with −3.37, Ry gate 7 is initialized with −2.29, and Ry gate 8 is initialized with −5.41.

[0053] Although exemplary embodiments have been described above, these embodiments are not intended to describe all possible forms encompassed by the claims. The words used herein are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the present disclosure. As previously mentioned, features of various embodiments may be combined to form further embodiments of the present invention that may not be expressly described or illustrated. Although various embodiments may be described as offering advantages or being preferred over other embodiments or prior art implementations with respect to one or more desired characteristics, those skilled in the art will recognize that one or more features or characteristics may be compromised to achieve desired overall system attributes that depend on the particular application and implementation. These attributes may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, maintainability, weight, manufacturability, ease of assembly, and the like. Thus, to the extent that any embodiment is described as less desirable than other embodiments or prior art implementations with respect to one or more characteristics, these embodiments are not outside the scope of the present disclosure and may be desirable for the particular application.

Claims

1. 1. A method for performing a variational quantum eigensolver (VQE) algorithm using a quantum circuit running on a quantum computer, comprising: The method comprises: generating the quantum circuit by a classical computer, the quantum circuit comprising: a subset of qubits including at least three of the qubits from a plurality of qubits arranged to perform a linear array of gates, the subset of qubits being arranged vertically and performing the linear array of gates horizontally; a first layer including a vertically centered arrangement of at least three single qubit gates on each of the linear gate arrays for each of the subsets of qubits; a second layer including a sequence of entanglement gates followed by a single qubit gate on each linear gate array, each entanglement gate entangling the linear gate array of the subsequent qubit; a third layer comprising said sequence of said second layer, said third layer not vertically overlapping said second layer; and receiving parameters related to a physical environment; executing, by the quantum computer, the VQE algorithm based on the parameters of the quantum circuit and the physical environment; outputting, via the quantum computer, an approximation of a base state of the physical environment; A method comprising:

2. The method comprises: initializing the at least three single qubit gates of the first layer based on a random value; initializing the at least three single qubit gates of the second layer with a value of 0; initializing the at least three single qubit gates in the third layer based on a negative value of the single qubit gates in the first layer on each of the linear gate arrays; The method of claim 1 further comprising:

3. 3. The method of claim 2 , further comprising: an additional layer between the second layer and the third layer, wherein one or more single qubit gates of the additional layer are initialized with the value 0.

4. The method comprises: configuring a subset of the qubits into an entangled initial state. The method of claim 1 further comprising:

5. The method of claim 4 , wherein the entangled initial state is not a product state.

6. 2. The method of claim 1 , wherein a right-most single-qubit gate in the linear array of gates associated with a third qubit of the subset of qubits is vertically centered with a right-most single-qubit gate of a second qubit of the subset of qubits.

7. The method of claim 1 , wherein the total number of layers is an odd number.

8. The method of claim 1 , wherein the quantum computer is a noisy intermediate-scale quantum computer.

9. 1. A system for executing a variational quantum eigensolver (VQE) algorithm on a quantum circuit, the system comprising: a quantum computer including a plurality of qubits; a classical computer comprising at least one processor and at least one non-transitory computer readable medium, the at least one non-transitory computer readable medium having computer program instructions configured to control the quantum computer; Equipped with The instructions include: a subset of qubits including at least three of the qubits from the plurality of qubits arranged to perform a linear array of gates, the subset of qubits being arranged vertically and performing the linear array of gates horizontally; a first layer including a vertically centered arrangement of at least three single qubit gates on each of the linear gate arrays for each of the subsets of qubits; a second layer including a sequence of entanglement gates followed by a single qubit gate on each linear gate array, each entanglement gate entangling the linear gate array of the subsequent qubit; a third layer comprising said sequence of said second layer, said third layer not vertically overlapping said second layer; generating, by the classical computer, the quantum circuit comprising: receiving parameters relating to a physical environment; executing, by the quantum computer, the VQE algorithm based on the parameters of the quantum circuit and the physical environment; outputting, via the quantum computer, an approximation of a base state of the physical environment; system.

10. The instructions further include for the system to: initializing the at least three single qubit gates of the first layer based on a random value; initializing the at least three single qubit gates of the second layer with a value of zero; initializing the at least three single qubit gates of the third layer based on a negative value of the single qubit gate of the first layer on each of the linear gate arrays. The system of claim 9.

11. 11. The system of claim 10, further comprising an additional layer between the second layer and the third layer, wherein one or more single qubit gates of the additional layer are initialized with the value 0.

12. The instructions further include for the system to: configuring a subset of the qubits into an entangled initial state; The system of claim 9.

13. The system of claim 12 , wherein the entangled initial state is not a product state.

14. 10. The system of claim 9, wherein a right-most single-qubit gate in the linear array of gates associated with a third qubit of the subset of qubits is vertically centered with a right-most single-qubit gate of a second qubit of the subset of qubits.

15. The system of claim 9 , wherein the total number of layers is an odd number.

16. The system of claim 9 , wherein the quantum computer is a noisy intermediate-scale quantum computer.

17. 1. A system for executing a variational quantum eigensolver (VQE) algorithm on a quantum circuit, the system comprising: a quantum computer including a plurality of qubits; a classical computer comprising at least one processor and at least one non-transitory computer readable medium, the at least one non-transitory computer readable medium having computer program instructions configured to control the quantum computer; Equipped with The instructions include: a subset of qubits including at least three of the qubits from the plurality of qubits arranged to perform a linear array of gates, the subset of qubits being arranged vertically and performing the linear array of gates horizontally; a first layer including a vertically centered arrangement of at least three single qubit gates on each of the linear gate arrays for each of the subsets of qubits; a second layer including a sequence of entanglement gates followed by a single qubit gate on each linear gate array, each entanglement gate entangling the linear gate array of the subsequent qubit; a third layer comprising said sequence of said second layer, said third layer not vertically overlapping said second layer; generating, by the classical computer, the quantum circuit comprising: receiving parameters relating to a physical environment; executing, by the quantum computer, the VQE algorithm based on the parameters of the quantum circuit and the physical environment; outputting, via the quantum computer, an approximation of a base state of the physical environment; system.

18. The instructions further include for the system to: initializing the at least three single qubit gates of the first layer based on a random value; initializing the at least three single qubit gates of the second layer with a value of zero; initializing the at least three single qubit gates of the third layer based on a negative value of the single qubit gate of the first layer on each of the linear gate arrays.

20. The system of claim 17.

19. The instructions further include for the system to: configuring a subset of the qubits into an entangled initial state; 20. The system of claim 17.

20. 20. The system of claim 17, wherein a right-most single-qubit gate in the linear array of gates associated with a third qubit of the subset of qubits is vertically centered with a right-most single-qubit gate of a second qubit of the subset of qubits.

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