Quantum computer, method and related device for solving combinatorial optimization problem

Abstract

The embodiment of the invention discloses a quantum computer, a method and a related device for solving a combinatorial optimization problem, and the quantum computer comprises a measurement and control all-in-one machine which is configured to generate a control signal based on a constraint condition, the constraint condition is used for representing the constraint when a plurality of elements are combined; the quantum chip comprises at least one group of quantum bits, and the number of the quantum bits is the same as that of the elements; and the interface is connected with the measurement and control all-in-one machine and the quantum chip and is configured to control the quantum chip based on the control signal so as to generate an optimal combination of elements represented by the ground state of the group of quantum bits. By adopting the embodiment of the invention, the requirement of quantum bits can be effectively reduced, the method is suitable for a real quantum computer, and a practical and feasible quantum circuit can be operated to solve a combinatorial optimization problem.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum computer, method, and related apparatus for solving combinatorial optimization problems. Background Technology

[0002] Combinatorial optimization problems (COPs) are a class of optimization problems that aim to find the optimal solution from a finite set of feasible solutions. Typical examples include the Traveling Salesman Problem (TSP), the Knapsack Problem, and the Graph Coloring Problem. COPs have important applications in information technology, economics and management, industrial engineering, transportation computing, and communication networks.

[0003] Combinatorial optimization problems have always been a challenging class of problems in computer science. The development of quantum computers has made it possible to solve combinatorial optimization problems quickly. However, current quantum computers are still in the mid-scale quantum computing era, with a limited number of qubits, which are extremely scarce computing resources, and the fidelity of quantum logic gates still needs improvement. Existing methods that construct quantum circuits using the Hamiltonian corresponding to the combinatorial optimization problem do not consider the limitations of qubits and the feasibility of executing quantum logic gates, thus presenting difficulties in practical applications. How to combine a real quantum computer with a practically feasible quantum circuit to solve combinatorial optimization problems is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a quantum computer, method, and related apparatus for solving combinatorial optimization problems. It can effectively reduce the demand for qubits, is applicable to real quantum computers, and facilitates the use of practically feasible quantum circuits to solve combinatorial optimization problems.

[0005] The first aspect of this application provides a quantum computer for solving combinatorial optimization problems, including:

[0006] The integrated measurement and control unit is configured to generate control signals based on constraints, which are used to characterize the constraints imposed when multiple elements are combined.

[0007] A quantum chip comprising at least one set of qubits, wherein the number of qubits is the same as the number of elements;

[0008] The interface connecting the measurement and control unit and the quantum chip is configured to control the quantum chip based on the control signal to generate an optimal combination of elements represented by the ground state of the set of qubits.

[0009] Optionally, the control signal includes a first control signal corresponding to the variable quantum circuit, wherein the quantum rotation gate included in the variable quantum circuit is used for both data encoding and variational processing.

[0010] Optionally, when the constraint is a global constraint and the number of elements is equal to 2, the control signal includes only the first control signal; when the constraint is a global constraint and the number of elements is greater than 2, the control signal also includes the second control signal corresponding to the beam splitting line; the beam splitting line maintains the ground state summation unchanged for the two input quantum states.

[0011] Optionally, the beam splitting circuit includes an H gate acting on two qubits, a CZ gate acting on two qubits, a rotation logic gate acting on two qubits, a CZ gate acting on two qubits, and an H gate acting on two qubits.

[0012] Optionally, when the global constraint is a global equality constraint, the variable quantum circuit includes a rotating logic gate acting on one of the qubits, a controlled NOT gate acting on two qubits, and a NOT gate acting on the other qubit, wherein the control bit of the controlled NOT gate is one of the qubits and the controlled bit is the other qubit.

[0013] Optionally, when the global constraint is a global inequality constraint, the variable quantum circuit includes the rotation logic gate acting sequentially on one of the qubits and the virtual control rotation logic gate acting on two qubits, wherein the control bit of the virtual control rotation logic gate is one of the qubits and the controlled bit is the other qubit.

[0014] A second aspect of this application provides a method for solving combinatorial optimization problems, applied to a quantum computer, the method comprising:

[0015] Control signals are generated based on constraints, which are used to characterize the constraints imposed when multiple elements are combined.

[0016] The quantum chip is controlled based on the control signal to generate an optimal combination of elements represented by the ground state of the set of qubits, the quantum chip including the at least one set of qubits, the number of qubits being the same as the number of elements.

[0017] A third aspect of this application provides an apparatus for solving combinatorial optimization problems, comprising:

[0018] A signal generation unit is used to generate control signals based on constraints, wherein the constraints are used to characterize the constraints imposed when multiple elements are combined.

[0019] A quantum state control unit is used to control the quantum chip based on the control signal to generate an optimal combination of elements represented by the set of qubits, the quantum chip including the at least one set of qubits, the number of qubits being the same as the number of elements.

[0020] A fourth aspect of this application provides an electronic device, including: a processor and a memory;

[0021] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the second aspect of the embodiments of this application.

[0022] The fifth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the second aspect of this application.

[0023] This application provides a quantum computer for solving combinatorial optimization problems, comprising a measurement and control unit configured to generate control signals based on constraints, the constraints being used to characterize the constraints on combinations of multiple elements; a quantum chip including at least one set of qubits, the number of qubits being the same as the number of elements; and an interface connecting the measurement and control unit and the quantum chip, configured to control the quantum chip based on the control signals to generate the optimal combination of elements represented by the ground state of the set of qubits. It can be seen that in this embodiment, the number of qubits is the same as the number of elements. Compared to constructing quantum circuits based on Hamiltonians, which requires a larger number of qubits due to the complexity of the constraints, this application can reduce the required number of qubits, which is advantageous for current quantum computers when the number of qubits is limited. Furthermore, by manipulating the qubits using control signals generated based on constraints to generate the optimal combination of elements represented by the ground state of the set of qubits, it is possible to solve combinatorial optimization problems on a real quantum computer. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 An example system block diagram for solving combinatorial optimization problems according to an embodiment of this application is shown;

[0026] Figure 2 This paper shows a schematic diagram of the structure of a two-bit beam splitter circuit according to an embodiment of this application;

[0027] Figure 3 This paper shows a schematic diagram of the structure of a two-bit variable fractional circuit provided in one embodiment of this application;

[0028] Figure 4 A schematic diagram of the structure of a two-bit variable component quantum circuit provided in another embodiment of this application is shown;

[0029] Figure 5 This paper shows a schematic diagram of the structure of a two-bit variable component quantum circuit provided in another embodiment of this application;

[0030] Figure 6 This paper shows a schematic diagram of the structure of a two-bit variable component quantum circuit provided in another embodiment of this application;

[0031] Figure 7 A flowchart illustrating a method for solving combinatorial optimization problems according to an embodiment of this application is shown.

[0032] Figure 8 This invention provides a schematic diagram of the structure of an apparatus for solving combinatorial optimization problems according to an embodiment of the present application.

[0033] Figure 9 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0035] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0036] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data.n A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0037] Please refer to Figure 1 This illustrates an example system block diagram for solving combinatorial optimization problems according to an embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0038] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0039] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0040] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0041] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0042] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0043] In this embodiment of the application, the quantum system 110 may be, for example, a quantum computer for solving combinatorial optimization problems, which includes:

[0044] The integrated measurement and control unit 111 is configured to generate control signals based on constraints, which are used to characterize the constraints imposed when multiple elements are combined.

[0045] Quantum chip 113 includes at least one set of qubits, the number of which is the same as the number of elements;

[0046] The interface 112 connecting the integrated measurement and control unit 111 and the quantum chip 113 is configured to control the quantum chip based on the control signal to generate an optimal combination of elements represented by the ground state of the set of qubits.

[0047] In mathematical programming, constraints, which impose limitations on decision-making schemes, often appear in the form of inequalities or equations. In economic problems, the objective function often needs to be maximized (or minimized) under certain constraints. These constraints include variables representing the decision-making schemes, thereby imposing limitations on their range. In this application, the aforementioned variables refer to elements.

[0048] Specifically, for example, in route planning, the above variables can be paths, and the values ​​of the variables represent whether to select a certain path, thereby determining the shortest path and achieving the fastest arrival time; for example, in network communication, the variables can be network communication nodes, and the values ​​of the variables represent whether to select that network node, thereby building the smallest network topology and achieving the lowest communication cost; for example, in financial investment, the variables can represent funds or stocks, and the values ​​of the variables represent whether to select a certain fund or stock, thereby constructing an optimal investment portfolio and maximizing returns, and so on.

[0049] If a two-level qubit is used, the ground state of the qubit can be a 0 state or a 1 state. In this case, a 0 state can be used to represent no selection and a 1 state can be used to represent selection; conversely, a 1 state can be used to represent no selection and a 0 state can be used to represent selection.

[0050] This application provides a quantum computer for solving combinatorial optimization problems, comprising a measurement and control unit configured to generate control signals based on constraints, the constraints being used to characterize the constraints on combinations of multiple elements; a quantum chip including at least one set of qubits, the number of qubits being the same as the number of elements; and an interface connecting the measurement and control unit and the quantum chip, configured to control the quantum chip based on the control signals to generate the optimal combination of elements represented by the ground state of the set of qubits. It can be seen that in this embodiment, the number of qubits is the same as the number of elements. Compared to constructing quantum circuits based on Hamiltonians, which requires a larger number of qubits due to the complexity of the constraints, this application can reduce the required number of qubits, which is advantageous for current quantum computers when the number of qubits is limited. Furthermore, by manipulating the qubits using control signals generated based on constraints to generate the optimal combination of elements represented by the ground state of the set of qubits, it is possible to solve combinatorial optimization problems on a real quantum computer.

[0051] In one embodiment of this application, the constraint condition is one of the following: a global equality constraint condition, a global inequality constraint condition, a local equality constraint condition, and a local inequality constraint condition. A global constraint condition means that the constraint condition is composed of all elements, and a local constraint condition means that the constraint condition is composed of multiple sub-constraint conditions. Each sub-constraint condition is composed of partial elements, and at least one of the partial elements constituting each sub-constraint condition overlaps with another partial element constituting the sub-constraint condition.

[0052] From the perspective of restricting the degrees of freedom of design variables, constraints can be divided into equality constraints and inequality constraints. Equality constraints are more stringent on design variables than inequality constraints, thus reducing the design degrees of freedom. Based on the completeness of the variables in the constraints, they can also be divided into global constraints and local constraints. Global constraints include all variables in their equality or inequality expressions; local constraints include only some variables in their equality or inequality expressions.

[0053] For example, variable x i (i = 1, 2, 3, 4) can only take the values ​​0 or 1, global equality constraint:

[0054] x1 + x2 + x3 + x4 = 3

[0055] This means that three of the four variables above have a value of 1, and one has a value of 0;

[0056] Global inequality constraints:

[0057] x1+x2+x3+x4≤3

[0058] This means that at most three of the above four variables have a value of 1, and one has a value of 0.

[0059] Local equality constraints:

[0060]

[0061] The first sub-constraint indicates that one of the first three variables has a value of 1, and the other two variables have a value of 0; the second sub-constraint indicates that one of the last three variables has a value of 1, and the other two variables have a value of 0.

[0062] Local inequality constraints:

[0063]

[0064] The first sub-constraint indicates that at most one of the first three variables has a value of 1, and the other two variables have a value of 0; the second sub-constraint indicates that at most one of the last three variables has a value of 1, and the other two variables have a value of 0.

[0065] As can be seen, the embodiments of this application cover all constraints, including equality constraints, inequality constraints, global constraints, and local constraints. Furthermore, by combining real quantum computers to solve combinatorial optimization problems, the application scope is expanded.

[0066] In one embodiment of this application, the control signal includes a first control signal corresponding to a variable quantum circuit, wherein the quantum rotation gate included in the variable quantum circuit is used for both data encoding and variational processing.

[0067] The variational quantum algorithm (VQA) uses a classical optimizer to train a parametric quantum circuit, somewhat like a natural analogy between machine learning and quantum computing. Our goal is to find a model that fits the data, i.e., to determine an optimal set of parameters. The method for determining the parameters is to make the model as close as possible to the given data (but not overfitting), with the degree of closeness defined by a loss function. By using optimizers to find the extreme points of the loss function, the goal can be achieved.

[0068] For classical machine learning algorithms, the model is typically a neural network running on a classical computer; for variable quantum algorithms, the model is a variable quantum circuit running on a quantum computer. A variable quantum circuit generally consists of three layers: an encoding layer, a variable layer, and a measurement layer. The encoding layer encodes classical data onto qubits; the variable layer evolves the quantum state of the qubits according to optimal parameters to obtain the optimal result; and the measurement layer measures the qubits and represents and stores the measurement results using classical bits.

[0069] The rotating logic gates can be, for example, RX(θ), RY(θ), RZ(θ), or logic gates that rotate along any axis. These rotating logic gates are basic logic gates and can generally be directly implemented in real quantum computers. Furthermore, unlike the variable quantum circuits in existing technologies, the use of rotating logic gates combines the preparation of the initial state and the evolution of the quantum state, reducing the number of logic gates and the overall depth of the quantum circuit. This is extremely beneficial for quantum computers in the NISQ era. An increase in the number of quantum logic gates leads to an increase in the depth of the quantum circuit, resulting in the accumulation of errors and affecting the accuracy of the measurement results. Currently, real quantum computers can only use a few hundred qubits, unlike classical computers which have billions of classical qubits with redundant qubits for error correction. Therefore, the embodiments in this application can save hardware resources such as qubits, reduce the depth of the quantum circuit, and improve the accuracy of the results.

[0070] In one embodiment of this application, when the constraint is a global constraint and the number of elements is equal to 2, the control signal includes only the first control signal; when the constraint is a global constraint and the number of elements is greater than 2, the control signal also includes a second control signal corresponding to the beam splitting line; the beam splitting line maintains the ground state summation unchanged for the two input quantum states.

[0071] Among them, the constraint is a global constraint with the number of elements equal to 2, which only requires two qubits to construct the constraint. Therefore, there is no need for a beam splitting line to make more than two qubits entangled. For the constraint is a global constraint with the number of elements greater than 2, the superposition state of two pairs of qubits can be constructed first through the variable quantum line corresponding to the first control signal, and then the superposition state of two pairs of qubits can be entangled through the beam splitting line corresponding to the second control signal to achieve the global equality constraint.

[0072] For example, when the number of elements is greater than 2, there are three cases for the global equality constraint: x1+x2=0, x1+x2=1, and x1+x2=2. For x1+x2=0, both variables must be 0 to satisfy the constraint; for x1+x2=2, both variables must be 1 to satisfy the constraint. Therefore, there is no combinatorial optimization problem for these two cases, and they generally do not need to be considered. So, we only need to consider the case of x1+x2=1. If x1+x2=1, then x1=1, x2=0, or x1=0, x2=1. We need to construct a superposition state of |01> and |10>. Therefore, variable quantum circuits are used to generate the superposition state α|01>+β|10> represented by two qubits. There are several ways to construct this superposition state. For example, we can first generate a single-qubit superposition state through a rotating logic gate or an H-gate, and then entangle the first qubit with the second qubit through a dual quantum logic gate to obtain the superposition state α|01>+β|10>.

[0073] When the number of elements is greater than 2, we can first exclude the cases where all elements are 0 or all elements are 1, which do not require combination optimization. Then, we construct a superposition state α|01>+β|10> of pairs of qubits through variable quantum circuits. Finally, we use beam splitting circuits to entangle the superposition states α|01>+β|10> of pairs of qubits, thus achieving global equality constraints. For example, the global equality constraints are:

[0074] x1+x2+x3+x4=2

[0075] Then, we can first use variable quantum circuits to generate the superposition state α1|01>+β1|10> of the first and second qubits, and the superposition state α2|01>+β2|10> of the third and fourth qubits, respectively. Then, we can use beam splitting circuits to act on the second and third qubits, so that the two superposition states become entangled, thereby achieving the global equality constraint x1+x2+x3+x4=2.

[0076] In one embodiment of this application, the beam splitting circuit includes an H gate acting on two qubits, a CZ gate acting on two qubits, a rotation logic gate acting on two qubits, a CZ gate acting on two qubits, and an H gate acting on two qubits.

[0077] The beam splitter circuit maintains the ground state summation invariance for the input quantum state. The matrix form of the two-qubit beam splitter circuit is as follows:

[0078]

[0079] Please refer to Figure 2 This diagram illustrates the structure of a two-qubit beam splitter circuit according to an embodiment of this application. In chronological order, two H gates operate on two qubits each, a CZ gate operates on two qubits each, two RY gates operate on two qubits each, and the rotation angles of the two RY gates are opposites of each other. The rotation angles of the RY gates in the beam splitter circuit are the same as the rotation angles of the rotating logic gates in the variable quantum circuit, both obtained through training, for example, using gradient descent.

[0080] In one embodiment of this application, when the global constraint is a global equality constraint, the variable quantum circuit includes a rotating logic gate acting on one of the qubits, a controlled NOT gate acting on two qubits, and a NOT gate acting on the other qubit. The control bit of the controlled NOT gate is one of the qubits, and the controlled bit is the other qubit.

[0081] It should be noted that the specific quantum logic gates constituting the variable quantum circuit need to be set according to the basic logic gates supporting the operation of real quantum computing. The above embodiment is only an example provided in this application, and other embodiments can be obtained by transforming the above quantum logic gates. Please refer to... Figure 3This document illustrates a schematic diagram of a two-qubit variable quantum circuit provided in one embodiment of this application. In this example, for instance, if a real quantum computer supports a CZ gate, the controlled NOT gate described above is replaced by an H gate acting on another qubit, a CZ gate acting on two qubits, and then another H gate acting on another qubit, thereby achieving a superposition state cosθ|01>+sinθ|10>, where the rotating quantum logic gate is RY(2θ).

[0082] In one embodiment of this application, when the global constraint is a global inequality constraint, the variable quantum circuit includes a rotating logic gate acting sequentially on one of the qubits and a virtual-controlled rotating logic gate acting on two qubits. The control bit of the virtual-controlled rotating logic gate is one of the qubits, and the controlled bit is the other qubit.

[0083] For global inequality constraints, the construction method is the same as for global equality constraints, except that the initial superposition state is different. The superposition state constructed for global inequality constraints is a|01>+b|10>+c|00>. Please refer to [reference needed]. Figure 4 This illustration shows a schematic diagram of a two-qubit variable quantum circuit according to another embodiment of this application. It includes an RY(θ1) gate acting on one of the qubits and a virtual-controlled RY(θ2) gate acting on the other qubit. Here, virtual control means that the RY(θ2) gate only acts on the other qubit when the quantum state of the control qubit is 0. Similar to the previous embodiment, the above-mentioned rotating logic gates can also be combined with different real quantum computers, transforming them into corresponding basic quantum logic gates supported by the actual machine.

[0084] It should be noted that this application can also use rotating logic gates to construct variable quantum circuits corresponding to local constraints. For example, for local equality constraints:

[0085]

[0086] The ground state can only be |101> and |010>, and can be adopted as follows: Figure 3 The variable quantum circuit shown first constructs a superposition state α|01>+β|10>, then introduces the quantum state of the third qubit through a CNOT gate, thus realizing a superposition state of |101> and |010>. Similarly, the CNOT gate can be replaced by an H gate, a CZ gate, and an H gate acting in sequence. Please refer to [reference needed]. Figure 5 This shows a schematic diagram of the structure of a two-bit variable quantum circuit provided in another embodiment of this application.

[0087] For example, consider local inequality constraints:

[0088]

[0089] The ground state can only satisfy |0000>, |0001>, |0010>, |0100>, |1000>, |1010>, |0101>. For amplitude preparation of the above ground states, please refer to [reference needed]. Figure 6 This illustration shows a schematic diagram of a two-bit variable quantum circuit provided in another embodiment of this application. A superposition state cosθ|1010>+sinθ|0101> can be obtained by sequentially applying an RY(2θ) gate to the first qubit, virtual NOT gates to the first and second qubits, virtual NOT gates to the second and third qubits, and virtual NOT gates to the third and fourth qubits. The control bit in the virtual NOT gate has a lower index than the controlled bit. Then, the first qubit controls the virtual RY gate of the second qubit, the third qubit controls the virtual RY gate of the fourth qubit, the second qubit controls the virtual RY gate of the first qubit, and the fourth qubit controls the virtual RY gate of the third qubit, thus realizing the preparation of the above-mentioned ground state superposition state.

[0090] Please refer to Figure 7 This document illustrates a flowchart of a method for solving combinatorial optimization problems according to an embodiment of this application. This method can be applied to computer devices, which refer to electronic devices capable of data computation and processing. For example, the executing entity for each step may be... Figure 1 The quantum computer shown. This method may include the following steps:

[0091] Step 701: Generate control signals based on constraints, wherein the constraints are used to characterize the constraints imposed when multiple elements are combined;

[0092] Step 702: Control the quantum chip based on the control signal to generate an optimal combination of elements represented by the ground state of a set of qubits, the quantum chip including at least the set of qubits, the number of qubits being the same as the number of elements.

[0093] It should be noted that the specific implementation of this method embodiment can be found in the above device embodiment, and will not be repeated here.

[0094] Figure 8 A schematic diagram of an apparatus for solving combinatorial optimization problems according to an embodiment of this application is shown. The apparatus includes:

[0095] The signal generation unit 801 is used to generate control signals based on constraints, which are used to characterize the constraints imposed when multiple elements are combined.

[0096] A quantum state control unit 802 is used to control the quantum chip based on the control signal to generate an optimal combination of elements represented by a set of qubits, the quantum chip including at least the set of qubits, the number of qubits being the same as the number of elements.

[0097] Figure 9 The diagram illustrates the structure of a computer device according to an embodiment of this application, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system for solving combinatorial optimization problems in any of the above embodiments.

[0098] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system for solving combinatorial optimization problems in any of the above embodiments.

[0099] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system for solving combinatorial optimization problems in any of the above embodiments.

[0100] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0101] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0102] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0103] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0104] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0105] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0106] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0108] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0109] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0110] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0111] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum computer for solving combinatorial optimization problems, characterized in that, include: The integrated measurement and control unit is configured to generate control signals based on constraints, which are used to characterize the constraints imposed when multiple elements are combined. A quantum chip comprising at least one set of qubits, wherein the number of qubits is the same as the number of elements; The interface connecting the measurement and control unit and the quantum chip is configured to control the quantum chip based on the control signal to generate an optimal combination of elements represented by the ground state of the set of qubits.

2. The quantum computer according to claim 1, characterized in that, The control signal includes a first control signal corresponding to the variable quantum circuit, wherein the quantum rotation gate included in the variable quantum circuit is used for both data encoding and variational processing.

3. The quantum computer according to claim 2, characterized in that, When the constraint is a global constraint and the number of elements is equal to 2, the control signal includes only the first control signal; when the constraint is a global constraint and the number of elements is greater than 2, the control signal also includes the second control signal corresponding to the beam splitting line; the beam splitting line maintains the ground state summation unchanged for the two input quantum states.

4. The quantum computer according to claim 3, characterized in that, The beam splitting circuit includes an H gate acting on two qubits, a CZ gate acting on two qubits, a rotation logic gate acting on two qubits, a CZ gate acting on two qubits, and an H gate acting on two qubits.

5. The quantum computer according to claim 3, characterized in that, When the global constraint is a global equality constraint, the variable quantum circuit includes a rotating logic gate acting on one of the qubits, a controlled NOT gate acting on two qubits, and a NOT gate acting on the other qubit. The control bit of the controlled NOT gate is one of the qubits, and the controlled bit is the other qubit.

6. The quantum computer according to claim 3, characterized in that, When the global constraint is a global inequality constraint, the variable quantum circuit includes a rotating logic gate acting sequentially on one of the qubits and a virtual-controlled rotating logic gate acting on two qubits. The control bit of the virtual-controlled rotating logic gate is one of the qubits, and the controlled bit is the other qubit.

7. A method for solving combinatorial optimization problems, characterized in that, Applied to quantum computers, the method includes: Control signals are generated based on constraints, which are used to characterize the constraints imposed when multiple elements are combined. The quantum chip is controlled based on the control signal to generate an optimal combination of elements represented by the ground state of a set of qubits, the quantum chip comprising at least the set of qubits, the number of qubits being the same as the number of elements.

8. An apparatus for solving combinatorial optimization problems, characterized in that, include: A signal generation unit is used to generate control signals based on constraints, wherein the constraints are used to characterize the constraints imposed when multiple elements are combined. A quantum state control unit is used to control the quantum chip based on the control signal to generate an optimal combination of elements represented by a set of qubits, the quantum chip including at least the set of qubits, the number of qubits being the same as the number of elements.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claim 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claim 7.

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