Electric power converting device

Abstract

To provide an electric power converting device that achieves both low inductance and improved reliability of solder bonding parts and TIM.SOLUTION: The electric power converting device includes: a semiconductor package having a sealing body 31 and a terminal 32a protruding from the sealing body 31; and a wiring substrate 20 to which the terminal 32a is electrically connected. The terminal 32a has: a bending part C1 that bends in a plate thickness direction of the terminal 32a; a first region C2 provided on the sealing body 31 side relative to the bending part C1 and connected to one end of the bending part C1; a second region C3 connected to the other end of the bending part C1 and facing the first region C2; and a bonding region 324 provided at the terminal tip and bonded to the wiring substrate 20. A cross-sectional area of the bending part C1 perpendicular to a terminal extension direction is smaller than a cross-sectional area of the first region C2 and the second region C3 perpendicular to the terminal extension direction.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] Card-type inverters that integrate the main circuit wiring on a printed circuit board can be mass-produced by eliminating joints through integration and utilizing small semiconductor packages (hereinafter referred to as small PKGs). However, unlike conventional printed circuit board mounting, it is necessary to mount a small PKG containing a built-in power semiconductor on the main circuit printed circuit board and install this in a water channel to cool the small PKG. In this case, the reliability of the solder joints of the small PKG and the reliability of the TIM (Thermal Interface Material) become issues.

[0003] For example, Patent Document 1 discloses a technology for reducing stress concentration at wiring terminals. The deformation of the case caused by the expansion and contraction of the sealing material filled inside the semiconductor device repeatedly applies stress to the soldered portion of the wiring terminal. The stress generated in the soldered portion of the wiring terminal differs depending on the amount of deformation and the arrangement position of the sealing material in each part of the semiconductor device. Therefore, the technology described in Patent Document 1 uses wiring terminals with different deformation adaptability amounts, and arranges wiring terminals with large deformation adaptability amounts in parts that receive large deformation amounts, thereby equalizing the stress generated in the soldered portion. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 7-221263 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when temperature cycles and power cycles occur in a configuration in which a small PKG is mounted on a circuit board, warping occurs in the circuit board due to the difference in linear expansion coefficient between the circuit board and the small PKG. Generally, a heat dissipation surface is formed on the front and back sides of a small PKG, and a heat dissipation member such as a cooler is provided on the heat dissipation surface. An insulating member is provided between the heat dissipation member and the heat dissipation surface, and the insulating member is adhered to the heat dissipation member and the heat dissipation surface by using a TIM. Therefore, when warping occurs in the circuit board due to temperature cycles and power cycles, it leads to a decrease in the reliability of the solder joints of the terminals and a decrease in the reliability of the TIM. [Means for solving the problem]

[0006] A power conversion device according to an embodiment of the present invention comprises a semiconductor package having a sealing body in which a semiconductor element is sealed with a sealing member and a plate-shaped terminal protruding from the sealing body, and a wiring board to which the terminal is electrically connected, wherein the terminal has a bent portion bent in the plate thickness direction of the terminal, a first region provided on the sealing body side of the bent portion and connected to one end of the bent portion, a second region connected to the other end of the bent portion and facing the first region, and a bonding region provided at a tip of the terminal and bonded to the wiring board, and a cross-sectional area of ​​a cross section perpendicular to the terminal extension direction of the bent portion is smaller than the cross-sectional areas of the first region and the second region perpendicular to the terminal extension direction. Effect of the Invention

[0007] According to the present invention, it is possible to achieve both low inductance and improved reliability of the solder joints and the TIM. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a power conversion device. [Diagram 2] FIG. 2 is a diagram showing a configuration of an inverter circuit. [Diagram 3] FIG. 2 is a diagram showing an example of a component arrangement on a wiring board. [Figure 4] FIG. 4 is a cross-sectional view of the section AA in FIG. [Diagram 5]FIG. 2 is an external perspective view of a semiconductor package. [Figure 6] 1A is a front view of the high-voltage side terminal for the main circuit, and FIG. [Figure 7] FIG. 13 is a diagram showing a first modified example. [Figure 8] FIG. 11 is a diagram showing a second modified example. [Figure 9] 13 is a diagram showing a wiring board on which a semiconductor package is mounted in Modification 2. FIG. [Figure 10] FIG. 13 is a perspective view of a semiconductor package according to Modification 3. [Figure 11] FIG. 13 is a diagram showing a wiring board on which a semiconductor package is mounted in Modification 3. [Figure 12] 11A to 11C are diagrams showing other shapes of the semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and are omitted and simplified as appropriate for clarity of explanation. In addition, in the following description, the same or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the contents described below are merely examples of the embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0010] FIG. 1 is a diagram showing a schematic configuration of a power conversion device 1. The power conversion device 1 converts DC power supplied from a DC voltage source 2 such as a battery into AC power to drive a motor 3. During braking of the motor 3, the power conversion device 1 is controlled to regenerate and convert the AC power into DC power. The power conversion device 1 includes an inverter circuit 10, a gate drive circuit 11, and a control circuit 12. The inverter circuit 10 includes a plurality of semiconductor elements that perform switching operations as described below. The inverter circuit 10 is connected to the DC voltage source 2 by a positive electrode wiring 103p and a negative electrode wiring 103n. The control circuit 12 includes a microcomputer, a CPU, or the like.

[0011] Fig. 2 is a diagram showing the configuration of the inverter circuit 10 shown in Fig. 1. The inverter circuit 10 is composed of a U-phase inverter circuit 10U, a V-phase inverter circuit 10V, and a W-phase inverter circuit 10W. The U-phase inverter circuit 10U, the V-phase inverter circuit 10V, and the W-phase inverter circuit 10W are connected in parallel between a positive wiring 103p and a negative wiring 103n connected to a DC voltage source 2.

[0012] Each of the U-phase inverter circuit 10U, the V-phase inverter circuit 10V, and the W-phase inverter circuit 10W includes upper and lower arm semiconductor elements and a capacitor 101. The upper arm semiconductor element includes four semiconductor elements 100a connected in parallel, and the lower arm semiconductor element includes four semiconductor elements 100b connected in parallel. This increases the output current of the power conversion device 1. Note that the number of parallel connections is not limited to four.

[0013] The semiconductor elements 100a and 100b are made of an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc. The semiconductor elements 100a and 100b are provided with three terminals: a high-voltage side terminal for the main circuit (a collector terminal for an IGBT, or a drain terminal for a MOSFET), a low-voltage side terminal for the main circuit (an emitter terminal for an IGBT, or a source terminal for a MOSFET), and a signal terminal (such as a gate terminal).

[0014] The main circuit low-voltage side terminal of the upper arm semiconductor element 100a of the U-phase inverter circuit 10U is connected to the main circuit high-voltage side terminal of the lower arm semiconductor element 100b by a U-phase output wiring 104U. The main circuit low-voltage side terminal of the upper arm semiconductor element 100a of the V-phase inverter circuit 10V is connected to the main circuit high-voltage side terminal of the lower arm semiconductor element 100b by a V-phase output wiring 104V. The main circuit low-voltage side terminal of the upper arm semiconductor element 100a of the W-phase inverter circuit 10W is connected to the main circuit high-voltage side terminal of the lower arm semiconductor element 100b by a W-phase output wiring 104W. The phase output wirings 104U, 104V, 104W are connected to the motor 3 (see FIG. 1).

[0015] The U-phase, V-phase, and W-phase inverter circuits 10U, 10V, and 10W are connected in parallel to a capacitor 102. A small ceramic capacitor is used for the capacitor 101, and a film capacitor with a large capacitance is used for the capacitor 102. By arranging the capacitors 101 and 102 in the vicinity of the semiconductor elements 100a and 100b, the wiring inductance of the positive wiring 103p and the negative wiring 103n can be reduced.

[0016] The output wirings 104U, 104V, 104W of each phase are connected to the motor 3. The signal terminals of the semiconductor elements 100a, 100b are connected to the gate drive circuit 11 of FIG.

[0017] Fig. 3 is a diagram showing a part of the inverter circuit 10, and is a diagram showing an example of the arrangement of components of the U-phase inverter circuit 10U on the wiring board 20. Fig. 4 is a diagram showing a cross section taken along line AA in Fig. 3. Note that Fig. 3 shows only the area in which the components related to the U-phase are arranged, and the area in which the V-phase components and the W-phase components are arranged is omitted. The V-phase components and the W-phase components are arranged in an area on the right side (not shown) of the wiring board 20 in Fig. 3.

[0018] In FIG. 3, the four semiconductor packages 30a are small PKGs incorporating the semiconductor elements 100a of the upper arm in the U-phase inverter circuit 10U. On the other hand, the four semiconductor packages 30b are small PKGs incorporating the semiconductor elements 100b of the lower arm in the U-phase inverter circuit 10U. A multilayer substrate is used for the wiring substrate 20. A positive electrode wiring 200, a negative electrode wiring 201, an output wiring 202U, and signal wiring 203a, 203b are formed on the first conductor layer on the substrate surface side on which the semiconductor packages 30a, 30b are mounted. The positive electrode wiring 200, the negative electrode wiring 201, and the output wiring 202U correspond to the positive electrode wiring 103p, the negative electrode wiring 103n, and the U-phase output wiring 104U shown in FIG. 2, respectively.

[0019] The semiconductor package 30a of the upper arm is disposed in a through hole 204a formed in the wiring board 20. A main circuit high voltage side terminal 32a of the semiconductor package 30a is connected to the positive wiring 200. A main circuit low voltage side terminal 32b of the semiconductor package 30a is connected to the output wiring 202U. A signal terminal 32c of the semiconductor package 30a is connected to the signal wiring 203a.

[0020] On the other hand, the semiconductor package 30b of the lower arm is disposed in a through hole 204b formed in the wiring board 20. The high voltage side terminal 32a for the main circuit of the semiconductor package 30b is connected to the output wiring 202U. The low voltage side terminal 32b for the main circuit of the semiconductor package 30b is connected to the negative wiring 201. The signal terminal 32c of the semiconductor package 30b is connected to the signal wiring 203b.

[0021] 4, the positive wiring 200, the negative wiring 201, the output wiring 202U, and the signal wiring 203a formed in the first conductor layer 21 of the wiring board 20 are electrically connected to the positive wiring 200, the negative wiring 201, the output wiring 202U, and the signal wiring 203a in other layers by interlayer connectors 25 formed by through-hole vias or the like. Four conductor layers 21 to 24 are formed in the wiring board 20.

[0022] By providing a large number of interlayer connections 25, it is possible to increase the cross-sectional area of ​​the current flowing in the thickness direction of the wiring board 20. This reduces the electrical resistance and reduces heat generation in the wiring. Furthermore, the interlayer connections 25 improve the thermal conductivity of the wiring board 20 in the thickness direction, making it possible to suppress an increase in the wiring temperature.

[0023] A collector electrode and a gate electrode are formed on the chip upper surface of the semiconductor element 100a shown in Fig. 4, and an emitter electrode is formed on the chip lower surface. A conductive member 300a provided with a main circuit high voltage side terminal 32a (not shown) is joined to the collector electrode by a bonding material 51. A conductive member 300b provided with a main circuit low voltage side terminal 32b is joined to the emitter electrode by a bonding material 51. The gate electrode is connected to a signal terminal 32c by a bonding wire 301.

[0024] The semiconductor element 100a, the conductive members 300a and 300b, the bonding wire 301, and the base regions of the terminals 32a to 32c are sealed with a sealing member 302. The main circuit high-voltage side terminal 32a (not shown), the main circuit low-voltage side terminal 32b, and the signal terminal 32c protrude from the sealing member 302 to the side of the sealing body 31 except for their base regions.

[0025] In the semiconductor package 30a, the sealing body 31 sealed with the sealing member 302 is disposed in a through hole 204a provided in the wiring board 20. Then, each of the bonding regions 324 of the main circuit high voltage side terminal 32a (not shown), the main circuit low voltage side terminal 32b, and the signal terminal 32c is bonded to the corresponding wiring of the positive electrode wiring 200, the output wiring 202U, and the signal wiring 203a formed on the conductor layer 21 by a bonding material 50 such as solder.

[0026] The upper surface of conductive member 300a and the lower surface of conductive member 300b function as heat dissipation surfaces, and these surfaces are exposed from sealing member 302. Coolers 60a and 60b, which are heat dissipation members, are provided on these heat dissipation surfaces via insulating member 303. Although not shown in the figure, a TIM (Thermal Interface Material) is provided on the surface of insulating member 303 to bond coolers 60a and 60b and the heat dissipation surface to the insulating member.

[0027] As described above, the semiconductor package 30a is mounted so as to be inserted into the through hole 204a provided in the wiring board 20. The terminals 32a to 32c on which the bent portion C1 is formed protrude from the semiconductor package 30a in a plane horizontal to the board surface of the wiring board 20. With this configuration, the coolers 60a and 60b can be disposed on the heat dissipation surfaces 310 provided on both the upper and lower surfaces of the semiconductor package 30a, as shown in FIG. 4. By cooling both sides of the semiconductor package 30a in this manner, the cooling performance is improved, and the power conversion device 1 can have a high output density.

[0028] 3, capacitor 102, which is a film capacitor, is connected to positive wiring 200 and negative wiring 201 provided on wiring board 20. By disposing capacitor 102, which is large and has a large capacitance, such as a film capacitor, on the side of wiring board 20, it becomes easier to fix it to a case that houses wiring board 20, and vibration resistance can be improved.

[0029] In addition, by extending the semiconductor packages 30a and 30b from the capacitor 102 toward the terminal side of the output wiring 202U, it is possible to shorten the positive wiring 200, the negative wiring 201, and the output wiring 202U. As a result, the power conversion device can be made smaller. Furthermore, by arranging the semiconductor packages 30a and 30b in a row, it is possible to reduce the size of the coolers arranged on both the front and back sides of the semiconductor packages 30a and 30b and improve the ease of installation.

[0030] 5 is an external perspective view of the semiconductor package 30a. The semiconductor package 30a includes a sealing body 31 sealed with a sealing member 302, and a main circuit high-voltage side terminal 32a, a main circuit low-voltage side terminal 32b, and a signal terminal 32c that protrude laterally from the sealing body 31. Heat dissipation surfaces 310 of conductive members 300a, 300b (see FIG. 4) are exposed on the front and back surfaces of the sealing body 31. The semiconductor package 30b has the same structure as the semiconductor package 30a. Below, the characteristics of the terminals of the semiconductor package 30a will be described using the main circuit high-voltage side terminal 32a as a representative.

[0031] 6(a) and (b) are diagrams illustrating the shape of the main circuit high voltage terminal 32a. Fig. 6(a) is a front view of the main circuit high voltage terminal 32a, and Fig. 6(b) is a view seen from the arrow B. The main circuit high voltage terminal 32a is formed of a plate-shaped conductive member (lead frame) with a plate thickness of t. The main circuit high voltage terminal 32a includes a bent portion C1, a first region C2, a second region C3, a connecting region C4, and a joining region 324.

[0032] The bent portion C1 is a terminal region in the range of the arrow with the symbol C1, and is a region bent in the terminal plate thickness direction. The first region C2 is provided on the sealing body 31 side from the bent portion C1 and is connected to one end (the end on the left side in the figure) of the bent portion C1. The second region C3 is connected to the other end (the end on the right side in the figure) of the bent portion C1 and is arranged to face the first region C2. The connecting region C4 is a region that connects the bent portion C1 to the first region C2 and the second region C3. The connecting region C4 has a width dimension that increases from the bent portion C1 side to the first region C2 and the second region C3 side. The bonding region 324 provided at the tip of the terminal is bonded to the wiring of the wiring board 20 by the bonding material 50, similar to the bonding region 324 of the main circuit low-voltage side terminal 32b shown in FIG. 4.

[0033] The width of the first region C2 and the second region C3 is set to W3. On the other hand, the bent portion C1 is set to a width W1 smaller than the width W3. That is, the cross-sectional area of ​​the bent portion C1 (= plate thickness t × width W1) is set smaller than the cross-sectional area of ​​the first region C2 and the second region C3 (= plate thickness t × width W3). The width of the connecting region C4 is W3 at the connection position with the first region C2 and the second region C3, and becomes smaller as it approaches the bent portion C1, and is W1 at the connection position with the bent portion C1.

[0034] Of course, the connecting region C4 may be omitted, and the first region C2 and the second region C3 with the width dimension W3 may be connected in a stepped manner to the bent portion C1 with the width dimension W1. However, when forming the bent portion C1 in the terminals 32a to 32c, the bent portion C1 is formed by punching a linear plate-shaped conductive member with a press before forming the bent portion. In this case, by setting the width dimension of the connecting region C4 to be gradually smaller toward the bent portion C1 as shown in FIG. 6(b), the manufacturability of the press punching is improved compared to the case where the width dimension changes in a stepped manner.

[0035] When a current flows from the positive wiring 200 of the wiring board 20 to the semiconductor element 100a via the main circuit high voltage terminal 32a, the current flows through the main circuit high voltage terminal 32a as indicated by the dashed arrow D. In the main circuit high voltage terminal 32a, the bent portion C1 is bent in the plate thickness direction, and the first region C2 and the second region C3 connected to both ends of the bent portion C1 are arranged to face each other. Therefore, the direction of the current flowing through the first region C2 and the direction of the current flowing through the second region C3 are opposite to each other, thereby achieving low inductance.

[0036] As described above, the difference in linear expansion coefficient between the wiring board 20 and the semiconductor package 30a causes warping of the wiring board 20, which leads to solder fracture and TIM deterioration. In this embodiment, the provision of the bent portion C1 makes the main circuit high voltage side terminal 32a more likely to deform. Furthermore, by increasing the length L (see FIG. 6) of the bent portion C1, the terminal rigidity can be further reduced, and the reliability of the solder and the TMI can be improved.

[0037] However, increasing the length L of the bent portion C1 has the disadvantage of increasing the inductance. Therefore, in this embodiment, the cross-sectional area of ​​the bent portion C1 is made smaller than that of the other terminal regions (the first region C2 and the second terminal region), thereby decreasing the terminal rigidity without increasing the length L of the bent portion C1. In other words, it is possible to achieve both low inductance and improved reliability of the solder joint and TIM during temperature cycles and power cycles.

[0038] As a method for reducing the cross-sectional area of ​​the bent portion C1, instead of reducing the width dimension W1 in the direction perpendicular to the thickness direction of the bent portion C1 (i.e., the width direction) as shown in Fig. 6, the dimension t in the thickness direction may be reduced. However, a structure in which the width dimension W1 is reduced has the advantage that the bent portion C1 with a smaller cross-sectional area can be easily formed simply by bending a lead frame member with a constant thickness.

[0039] 4 and 6, the second region C3 extends upward in the figure so as to rise from the joining region 324 in the plate thickness direction relative to the joining region 324 that is solder-joined to the wiring board 20. One end of the bent portion C1 is connected to the upper end of the first region C2 that faces the second region C3, and the other end of the bent portion C1 is connected to the upper end of the second region C3. Therefore, when the joining region 324 is solder-joined to the wiring board 20, it is possible to prevent the solder from wetting up, thereby improving the reliability of the solder joint.

[0040] (Variation 1) FIG. 7 is a diagram showing a first modified example of the embodiment described above. In the embodiment described above, the cross-sectional area of ​​the bent portion C1 is set smaller than the cross-sectional areas of the first and second regions C2, C3 in all of the terminals 32a to 32c. On the other hand, in the first modified example, the cross-sectional areas of the bent portion C1 and the first and second regions C2, C3 are set equal for the main circuit high-voltage side terminal 32a and the main circuit low-voltage side terminal 32b, which are main terminals, and the cross-sectional area of ​​the bent portion C1 is set smaller only for the signal terminal 32c. When the semiconductor element 100a built in the semiconductor package 30a is energized, a large current flows through the main circuit high-voltage side terminal 32a and the main circuit low-voltage side terminal 32b, which are main terminals. In the first modified example, the cross-sectional area of ​​the bent portion C1 of the terminals 32a and 32b is set equal to the cross-sectional area of ​​the first and second regions C2, C3, thereby preventing the terminals 32a and 32b from heating up when a large current is applied.

[0041] (Variation 2) Fig. 8 is a diagram showing an example of Modification 2. In the example shown in Figs. 4 and 6 described above, the terminals 32a to 32c protrude laterally from the sealing body 31, and the first and second regions C2, C3 are formed so as to rise upward with respect to the protruding direction. Therefore, the bent portion C1 is provided so as to protrude upward from the terminals 32a to 32c. On the other hand, in Modification 2 shown in Fig. 8, the terminal regions protruding laterally from the sealing body 31 constitute the first region C1, and the second region C3 is disposed so as to face the lower side of the first region C2 in the plate thickness direction (the direction of the arrow R in Fig. 8). Therefore, the bent portion C1 is formed so as to be bent in the thickness direction of the sealing body 31.

[0042] In the configuration of the second modification, the second region C3 extends to the tips of the terminals 32a to 32c, and the bonding region 324 (see FIG. 6) is included in the second region C3. FIG. 9 is a diagram showing the wiring board 20 on which the semiconductor package 30a of FIG. 8 is mounted. The terminals 32b and 32c protrude to the sides of the sealing body 31. The second region C3 facing the lower side of the first region C2 in the figure is solder-bonded to the wiring board 20.

[0043] In the terminal configuration shown in Fig. 8, the opposing regions of the terminals 32a to 32c can be set to a wider range than in the terminal configuration shown in Fig. 6. As a result, the inductance can be further reduced by the magnetic flux cancellation effect of the opposing currents. In this case, it is preferable to make the length of the first region C2 and the length of the second region C3 the same, which maximizes the inductance reduction effect.

[0044] (Variation 3) 10 and 11 show Modification 3. FIG. 10 is a perspective view of semiconductor package 30a, and FIG. 11 is a view showing wiring board 20 on which semiconductor package 30a is mounted. Modification 3 is a modification of the configuration shown in FIG. 8. In Modification 3, second regions C3 of each of terminals 32a to 32c are extended to sealing body 31. Then, in tip region E (see FIG. 11) of second region C3, a surface facing first region C1 (upper surface in FIG. 11) is made to face sealing body 31.

[0045] 11, a step surface 312 is formed in the sealing body 31. In the terminals 32a-32c bent into a U-shape by forming the bent portion C1, the tip region E of the second region C3 extends to a region facing the step surface 312. In the example shown in FIG. 11, the tip region E is disposed close to the step surface 312, but the tip region E may also abut against the step surface 312.

[0046] 10 and 11, when forming the terminals 32a to 32c having the bent portion C1, the flat lead frame which is the terminals 32a to 32c before bending is sealed with the sealing member 302. The lead frame is then bent to form the bent portion C1. At that time, by pressing the tip region E of the second region C3 against the step surface 312 to perform the bending process, the workability of the bending process can be improved and the processing accuracy of the bent portion C1 can be improved.

[0047] In the above-described embodiment and modified examples, for example, as shown in FIG. 4 and the like, the sealing body 31 of the semiconductor package 30a is arranged in the through hole 204a formed in the wiring board 20. However, the present invention can also be applied to a semiconductor package 30c having a configuration in which the sealing body 31 is arranged on the front side of the wiring board 20, as shown in FIGS. 12(a) and (b).

[0048] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0049] (1) As shown in Figures 4 to 6, etc., a semiconductor package 30a includes a sealing body 31 in which a semiconductor element 100a is sealed with a sealing member 302, and plate-shaped terminals 32a to 32c protruding from the sealing body 31, and a wiring board 20 to which the terminals 32a to 32c are electrically connected, and the terminals 32a to 32c have a bent portion C1 bent in the plate thickness direction of the terminals 32a to 32c, a first region C2 provided on the sealing body 31 side of the bent portion C1 and connected to one end of the bent portion C1, a second region C3 connected to the other end of the bent portion C1 and facing the first region C2, and a bonding region 324 provided at the tip of the terminal and bonded to the wiring board 20, and the cross-sectional area of ​​the bent portion C1 in a cross section perpendicular to the terminal extension direction is smaller than the cross-sectional areas of the first region C2 and the second region C3 in a cross section perpendicular to the terminal extension direction.

[0050] By providing the first region C2 and the second region C3 facing each other via the bent portion C1, the direction of the current flowing through the first region C2 is opposite to the direction of the current flowing through the first region C2, thereby enabling low inductance. Also, by making the cross-sectional area of ​​the bent portion C1 smaller than the other terminal regions (the first region C2 and the second region C3), it is possible to reduce the terminal rigidity without increasing the length of the bent portion C1. In other words, it is possible to achieve both low inductance and improved reliability of the solder joint and the TIM during temperature and power cycles.

[0051] (2) In the above (1), as shown in Fig. 6 etc., the dimension W1 of the bent portion C1 in the width direction perpendicular to the plate thickness direction is smaller than the dimension W3 of the first region C2 and the second region C3 in the width direction. Therefore, the bent portion C1 with a smaller cross-sectional area can be easily formed by simply bending a lead frame member with a constant plate thickness.

[0052] (3) In the above (2), as shown in Fig. 6 etc., a connecting region C4 is further provided that connects the bent portion C1 with the first region C2 and the second region C3 and has a cross-sectional area that changes along the terminal extension direction, and the width dimension of the connecting region C4 is set to become smaller from the first region C2 and the second region C3 toward the bent portion C1. By setting the width dimension of the connecting region C4 to become smaller from the first region C2 and the second region C3 toward the bent portion C1, manufacturability of press punching is improved.

[0053] (4) In the above (1), as shown in Figures 4, 6, etc., the second region C3 extends from the bonding region 324 so as to rise in its plate thickness direction (the vertical direction in Figure 6(a)) and is connected to the other end of the bent portion C1. Since the second region C3 extends so as to rise from the bonding region 324, when the bonding region 324 is soldered to the wiring board 20, it is possible to prevent the solder from wetting out, thereby improving the reliability of the solder joint.

[0054] (5) In the above (1), as shown in FIG. 7, the terminals include a high-voltage side terminal 32a for the main circuit and a low-voltage side terminal 32b for the main circuit (main terminals) for large current, and a signal terminal 32c for a drive signal. The signal terminal 32c has a bent portion C1 (first bent portion) having a small cross-sectional area, the first region C2, the second region C3, and a joint region 324. The terminals 32a, 32b have a bent portion C1 (second bent portion) bent in the thickness direction and having a cross-sectional area perpendicular to the terminal extension direction equal to the first region C2 and the second region C3, the first region C2, the second region C3, and the joint region 324.

[0055] For the high-voltage side terminal 32a for the main circuit and the low-voltage side terminal 32b for the main circuit, through which a large current flows, by making the cross-sectional area of ​​the bent portion C1 the same as the cross-sectional area of ​​the first and second regions C2, C3, heat generation in the terminals 32a, 32b when a large current flows can be reduced.

[0056] (6) In the above (1), as shown in Fig. 8 and other figures, the first region C2 is formed so as to protrude from the sealing body 31 to the side of the semiconductor package 30a, the second region C3 extends to the tip of the terminal, and the bonding region 324 is included in the second region C3. With this configuration, it is possible to set the opposing region of the first and second regions C2 and C3 opposing each other to a larger area. As a result, it is possible to further improve the low inductance due to the magnetic flux cancellation effect caused by the opposing currents.

[0057] (7) In the above (6), as shown in Figures 10 and 11, a part of the surface of the second region C3 facing the first region C2 faces the plug 31. Therefore, in the bending operation for forming the bent portion C1, the surface of the second region C3 facing the first region C2 is pressed against the plug 31 to perform the bending operation, which improves the workability of the bending operation and improves the processing accuracy of the bent portion C1.

[0058] (8) In the above (1), as shown in Fig. 4 etc., the wiring board 20 has a through hole 204a, and the semiconductor package 30a is arranged so that the sealing body 31 is inserted into the through hole 204a. With such a configuration, the coolers 60a, 60b can be arranged on both the top and bottom surfaces of the semiconductor package 30a, and the cooling performance is improved by cooling both sides of the semiconductor package 30a, and the power density of the power conversion device can be increased.

[0059] The above-described embodiment and various modified examples are merely examples, and the present invention is not limited to these contents as long as the characteristics of the invention are not impaired. Other aspects that are conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. [Explanation of symbols]

[0060] 1...power conversion device, 2...DC voltage source, 3...motor, 10...inverter circuit, 11...gate drive circuit, 12...control circuit, 20...wiring board, 25...interlayer connection portion, 30a, 30b...semiconductor package, 31...sealing body, 32a...high voltage side terminal for main circuit, 32b...low voltage side terminal for main circuit, 32c...signal terminal, 100a, 100b...semiconductor element, 101, 102...capacitor, 103p, 200...positive wiring, 103n, 201...negative wiring, 203a, 203b...signal wiring, 204a, 204b...through hole, 302...sealing member, 310...heat dissipation surface, 312...step surface, 324...joint region, C1...bent portion, C2...first region, C3...second region, C4...connection region

Claims

1. a semiconductor package having a sealing body in which a semiconductor element is sealed with a sealing member and a plate-shaped terminal protruding from the sealing body; a wiring board to which the terminal is electrically connected, the terminal has a bent portion bent in a plate thickness direction of the terminal, a first region provided on the sealing body side of the bent portion and connected to one end of the bent portion, a second region connected to the other end of the bent portion and facing the first region, and a bonding region provided at a tip of the terminal and bonded to the wiring board; A power conversion device, wherein a cross-sectional area of ​​the bent portion perpendicular to a terminal extension direction is smaller than cross-sectional areas of the first region and the second region perpendicular to the terminal extension direction.

2. 2. The power conversion device according to claim 1, A power conversion device, wherein a dimension of the bent portion in a width direction perpendicular to the plate thickness direction is smaller than dimensions of the first region and the second region in the width direction.

3. 3. The power conversion device according to claim 2, a connecting region that connects the bent portion to the first region and the second region and has a cross-sectional area that changes along the terminal extending direction, A power conversion device, wherein the widthwise dimension of the connecting region is set to decrease from the first region and the second region toward the bent portion.

4. 2. The power conversion device according to claim 1, The second region extends upward from the joint region in the plate thickness direction of the joint region and is connected to the other end of the bent portion.

5. 2. The power conversion device according to claim 1, The terminals include a main terminal for large current and a signal terminal for a drive signal, the signal terminal has a first bent portion formed by the bent portion, the first region, the second region, and the joining region; The main terminal has a second bent portion that is bent in a plate thickness direction of the main terminal and has a cross-sectional area perpendicular to the terminal extension direction equal to the first region and the second region, the first region, the second region, and the joining region.

6. 2. The power conversion device according to claim 1, the first region is formed to protrude from the sealing body to a side of the semiconductor package, A power conversion device, wherein the second region extends to the tip of the terminal, and the joining region is included in the second region.

7. 7. The power conversion device according to claim 6, A power conversion device, wherein a portion of a surface of the second region that faces the first region faces the sealing body.

8. 2. The power conversion device according to claim 1, The wiring board has a through hole, The semiconductor package is arranged such that the sealing body is inserted into the through hole.

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