Equipment control device

Abstract

To appropriately reflect the recovery of a measurement signal from an abnormal state to a normal state in an equipment control device which generates a control signal by subjecting the measurement signal to arithmetic processing.SOLUTION: An equipment control device which controls equipment by subjecting a measurement signal to arithmetic processing includes first arithmetic cells (C, E) to which a signal is input from an upstream cell and a second arithmetic cell (D) to which a signal from the upstream cell and a signal from a downstream cell are input. An arithmetic unit (81) of the first and second arithmetic cells output the arithmetic processing results of the input signals. A status signal unit (82) of the first arithmetic cell directly outputs the received status signal as is. When the status signal input from an upstream arithmetic cell changes from a signal representing an abnormal state to a signal representing a normal state, the status signal unit (82) of the second arithmetic cell outputs a predetermined time and the status signal representing normality to a downstream arithmetic cell. In other cases, the status signal unit outputs the input status signal to the downstream arithmetic cell as is.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an equipment control device used in plants such as factories and power plants to control equipment based on signals output from measuring instruments. [Background technology]

[0002] In plants such as factories and power plants, equipment control devices are used that monitor signals output from various measuring instruments and control the operation of the equipment based on the signals. Such equipment control devices are equipped with an arithmetic processing unit that generates signals for controlling the equipment based on signals output from the measuring instruments. The arithmetic processing unit has an input cell, multiple arithmetic cells, and an output cell. The input cell outputs a signal (measurement signal) input from the measuring instrument to a specific arithmetic cell. Each of the multiple arithmetic cells executes a specific arithmetic process on the input cell or a signal output from a previous arithmetic cell, and outputs the arithmetic result to a subsequent arithmetic cell or an output cell. The output cell generates a control signal based on a signal from a specific arithmetic cell, and outputs the control signal to the equipment. The input cell, arithmetic cell, and output cell are all arithmetic units configured with a program that executes a specific arithmetic process. In addition, in the arithmetic processing unit, each arithmetic cell executes arithmetic process on a signal input from a previous input cell or arithmetic cell for each timing signal generated at a specific time interval, and outputs a signal that is the arithmetic result to a subsequent arithmetic cell or an output cell.

[0003] In the device control device described in Patent Document 1, the calculation processing unit has a function of judging whether a measurement signal is normal / abnormal in an input cell, generating a status signal indicating normal / abnormal according to the judgment result, and outputting the status signal together with the measurement signal to a downstream calculation cell. Also, each calculation cell may have a function of sending the status signal sent from the preceding input cell or calculation cell, i.e., the status signal indicating normal / abnormal, to the downstream calculation cell as is (i.e., inheriting the status signal to the downstream calculation cell). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2023-104503 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a calculation processing unit, for example, when PID (Proportional-Integral-Differential) control is included, a signal resulting from calculation processing performed in a certain calculation cell may be returned to one or more preceding calculation cells, that is, the signal may be looped to perform calculation processing. In a calculation processing unit having such a looped signal path, if a status signal indicating whether an input signal is normal or abnormal is inherited by a subsequent calculation cell as in Patent Document 1, the following problem occurs.

[0006] When an abnormal measurement signal is input, the input cell generates a status signal (abnormal status signal) indicating that the measurement signal is abnormal, and outputs the status signal together with the measurement signal to the downstream calculation cell. In the calculation processing unit, each time a timing signal is generated, the abnormal status signal is passed on to the downstream calculation cell in sequence along with the calculation result in each calculation cell. If the measurement signal returns to normal after a while, the input cell generates a status signal (normal status signal) indicating that the measurement signal is normal, and outputs the status signal to the downstream calculation cell. When the input status signal changes from abnormal to normal, a calculation cell that is not included in the above loop signal path outputs a normal status signal to the downstream calculation cell along with the calculation result.

[0007] On the other hand, in a calculation cell included in the above-mentioned looped signal path, even if a status signal that has changed from an abnormal state to a normal state as described above is input from a preceding input cell or calculation cell, an abnormal status signal may be returned and input together with the result of calculation processing in one or more subsequent calculation cells. Therefore, even if the measurement signal has returned to normal, a status signal indicating an abnormality may be output from the calculation cell included in the looped signal path to the subsequent calculation cell, resulting in a problem in that the status signal indicating an abnormality may continue to be inherited in the calculation cell included in the looped signal path.

[0008] The problem that the present invention aims to solve is to appropriately reflect the return of a measurement signal from an abnormality to normal in an equipment control device that performs specified arithmetic processing on a signal input from a measuring instrument and generates a signal for controlling the equipment. [Means for solving the problem]

[0009] The present invention, which has been made to solve the above problems, is an equipment control device which performs arithmetic processing by a plurality of mutually connected arithmetic cells based on a measurement signal input from a measuring instrument, and controls an equipment based on the results of the arithmetic processing, the plurality of arithmetic cells include a first arithmetic cell to which the measurement signal or a signal from a preceding arithmetic cell and a signal from one or more subsequent second arithmetic cells are input, the first calculation cell includes a calculation unit and a status signal unit; the calculation unit of the first calculation cell performs a predetermined calculation process based on the measurement signal or a signal from a preceding calculation cell and a signal from the second calculation cell, and outputs the result as an output signal to the calculation unit of a succeeding calculation cell or the device; When the status signal input from the preceding calculation cell changes from a signal indicating an abnormality to a signal indicating normality, the status signal section of the first calculation cell outputs a status signal indicating normality to the succeeding calculation cell for a predetermined time from the time when the status signal changes, regardless of the status signal input from the second calculation cell, and in all other cases outputs the input status signal as is to the status signal section of the succeeding calculation cell. Effect of the Invention

[0010] In the device control device according to the present invention, in a first arithmetic cell to which a measurement signal or a signal from a preceding arithmetic cell is input, as well as a signal from a second arithmetic cell located at one or more subsequent stages, when a status signal input from the preceding arithmetic cell changes from a signal indicating an abnormality to a signal indicating a normal state, the first arithmetic cell outputs a status signal indicating a normal state to the subsequent arithmetic cell regardless of the status signal input from the second arithmetic cell for a predetermined time from the time point when the status signal changes, and outputs the input status signal as it is to the status signal section of the subsequent arithmetic cell in other cases. Therefore, even if an abnormality status signal is input from the second arithmetic cell to the first arithmetic cell at the predetermined time, the abnormality status signal is not inherited by the subsequent arithmetic cell. After the predetermined time has elapsed, the first arithmetic cell outputs the input status signal as it is to the subsequent arithmetic cell. Therefore, even if a status signal indicating an abnormality is input from one or more subsequent arithmetic cells after the measurement signal has returned to normal, the first arithmetic cell is not affected and can appropriately reflect that the measurement signal has returned from an abnormality to normal. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing the configuration of a main part of a monitoring and control system which is an embodiment of a device control device according to the present invention; [Diagram 2] 3A and 3B are diagrams for explaining a calculation cell according to the embodiment; [Diagram 3] 3A and 3B are diagrams for explaining the connection state of a plurality of cells constituting a control program in the present embodiment and the operation of each cell. [Figure 4] FIG. 1 is a diagram for explaining the connection state of a plurality of cells constituting a conventional control program and the operation of each cell. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A monitoring and control system, which is an embodiment of an equipment control device according to the present invention, will be described below with reference to the drawings.

[0013] Fig. 1 is a configuration diagram of the main parts of a monitoring and control system (hereinafter, simply referred to as "system") according to this embodiment. This system monitors and controls plant equipment in order to operate the plant equipment. As shown in Fig. 1, this system includes a control device 1 connected to a field device 5 including measuring instruments (various sensors, switches, etc.) for collecting data included in the plant equipment and devices to be controlled, an operator terminal 2 connected to the control device 1 via a control network 4, and an engineering terminal 3. In addition, a PLC (Programmable Logic Controller) 7 is connected to the control device 1 via a local network 6.

[0014] The control device 1 includes an I / O unit 12 that exchanges data (including both analog and digital signals) with the field device 5, a communication unit 10 that transmits and receives data to and from the operator terminal 2, the engineering terminal 3, and another control device 1 via the control network 4, and a control unit 11 that performs arithmetic processing of input and output data. Although not shown, the control unit 11 has an arithmetic unit such as a computer and / or a digital signal processor for performing arithmetic processing, and a memory in which a control program for operating the arithmetic unit is stored. The memory has an area in which a basic program for operating the arithmetic unit is stored, and an area in which cells that hold information on operations and the like executed by the basic program are stored. Such cells include input cells, arithmetic cells, and output cells.

[0015] The actual entities of the operator terminal 2 and the engineering terminal 3 are both general personal computers (PCs). The operator terminal 2 is usually operated by an operator who operates the plant equipment. Although only one operator terminal 2 is illustrated in Fig. 1, there may be multiple operator terminals 2.

[0016] The engineering terminal 3 is a terminal operated by a person with specific authority, such as an engineer of the instrumentation manufacturer that provides this system or a system administrator. On the engineering terminal 3, an engineer or the like uses pre-installed dedicated software to create an instrumentation drawing that combines input cells, operation cells, and output cells, and then compiles the instrumentation drawing to create a control program.

[0017] An input cell is a cell to which data signals output from various measuring instruments are input. The input cell determines whether the data signal output from the measuring instruments is normal / abnormal, and outputs the input data signal together with a status signal indicating whether the data signal is normal / abnormal to the downstream calculation cell. The calculation cell executes a specific calculation process on the data signal input from the input cell or calculation cell, and outputs the calculation result to the downstream calculation cell or output cell. The output cell generates a signal for device control based on the data signal input from the upstream calculation cell, and outputs it to the device. The input cell, calculation cell, and output cell are all calculation units composed of a program that executes a specific calculation process.

[0018] 2, each arithmetic cell 8 includes an arithmetic unit 81, a status signal unit 82, and a status fixed signal unit 83. In the arithmetic unit 81, arithmetic type information 811 indicating the type of arithmetic operation executed by the arithmetic cell and one or more pieces of parameter information (arithmetic parameters) 812 used for the arithmetic operation are registered. In addition, each arithmetic cell 8 has connection relationship information 84 indicating the connection relationship between the cell and other cells and the order of signal processing by each cell. Of these, the arithmetic type information 811 is fixed information for each arithmetic cell (i.e., it is unchanging), but the rest are information that is determined when a control program is created in the engineering terminal 3. The types of arithmetic operations may include simple arithmetic operations of addition, subtraction, multiplication, and division, various functions, first-order lag, PID (Proportional-Integral-Differential) control, and the like. In this embodiment, the calculation unit 81 performs a predetermined calculation process using calculation type information 811 and calculation parameters 812 on a data signal input with a predetermined number of bits from the calculation unit 81 of the preceding input cell or calculation cell 8, and outputs the calculation result with a predetermined number of bits to the calculation unit 81 of the following calculation cell or the output cell.

[0019] A "status signal" is a signal that indicates the state of a data signal exchanged between various cells including input cells, output cells, and arithmetic cells, more specifically, an abnormality caused by hardware, an abnormality caused by software, an abnormality caused by human factors such as some operation by an operator or signal simulation (different from a normal state), etc. Therefore, a status signal attached to data input from a certain cell to another certain cell indicates the reliability or soundness of the data. However, an abnormality here does not necessarily mean a malfunction such as a breakdown. In this embodiment, the status signal unit 82 inputs and outputs a status signal generated as an inheritance bit between the status signal unit 82 of the preceding and succeeding cells.

[0020] The status signal information in the arithmetic cell includes information for determining whether or not a status signal indicating an abnormality is output from a certain arithmetic cell when the status signal indicating an abnormality is input to the certain arithmetic cell (whether or not to inherit the input status signal). The status signal indicating an abnormality may be passed only between two cells and not inherited by subsequent cells, or may be inherited by a cell that receives data directly or indirectly from the certain cell. This is because, for example, even if a status signal indicating an abnormality is input to a certain arithmetic cell together with a data signal, if the value of the data signal output from the arithmetic cell can be fixed to a specific value to execute subsequent arithmetic operations without problems, there is no need to inherit the status signal indicating an abnormality.

[0021] A "status fixed signal" is a signal that indicates a state in which the status signal output from a certain calculation cell is fixed to a status signal indicating normality (inheritance bit: OFF), regardless of whether the status signal input to the calculation cell from a calculation cell located later than the calculation cell indicates normality (inheritance bit: OFF) or an abnormality (inheritance bit: ON). The status fixed signal unit 83 inputs and outputs the status signal generated as an indefinite bit between the status fixed signal unit 83 of the preceding and succeeding cells. The bit indicating the data signal, the inheritance bit indicating the status signal, and the indefinite bit indicating the status fixed signal are input and output simultaneously between each cell as a single bit string.

[0022] The control program used in the monitoring and control system of this embodiment performs a predetermined calculation process in each of multiple calculation processes on the data signal input from the measuring instrument to the input cell, and outputs a control signal based on the calculation result to the equipment to be controlled.

[0023] The multiple calculation cells that constitute the control program used in this embodiment include a calculation cell (third calculation cell) to which a measurement signal or a signal is input only from a preceding calculation cell, and a calculation cell (first calculation cell) to which a measurement signal or a signal from a preceding calculation cell and a signal from one or more subsequent calculation cells (second calculation cells) are input.

[0024] The third calculation cell is set to output the status signal and the fixed status signal input from the preceding input cell or calculation cell to the succeeding calculation cell or output cell as is (i.e., to inherit the status signal and the fixed status signal). Note that if two or more status signals are input and the status signals are different, the status signal that is ON is given priority and inherited.

[0025] The first arithmetic cell is set so that when the status signal input together with the status fixed signal (undefined bit: OFF) indicating that the status signal is not fixed switches from a status signal indicating an abnormality to a status signal indicating normality for a predetermined time from that point on, the first arithmetic cell outputs a status signal indicating normality (inherited bit: OFF) from the first arithmetic cell, regardless of whether the status signal input from the second arithmetic cell indicates normality (inherited bit: OFF) or abnormality (inherited bit: ON). Whether the input to the first arithmetic cell is from a preceding arithmetic cell or a succeeding arithmetic cell (second arithmetic cell) is identified based on the connection relationship information 84 held by the first arithmetic cell. This predetermined time is set in advance to a time longer than the time (loop time) required for the data signal output from the first arithmetic cell to return to the first arithmetic cell via the second arithmetic cell.

[0026] During this predetermined time, the first arithmetic cell generates a status fixed signal (indefinite bit: ON) that indicates a state fixed to a status signal (inherit bit: OFF) that indicates normality, and outputs it to the subsequent arithmetic cell. Otherwise, that is, when a status signal that indicates normality is continuously input, or when a status signal that indicates an abnormality is continuously input, the status signal and status fixed signal input from the previous input cell or arithmetic cell are set to be output as is to the subsequent arithmetic cell or output cell (i.e., the status signal and status fixed signal are inherited). Note that when two or more different status signals or status fixed signals are input, the status signal or status fixed signal that is ON is inherited.

[0027] 3 shows an example of a control program in the monitoring and control system of this embodiment. This control program performs predetermined arithmetic processing in each of three arithmetic cells (arithmetic cells C, D, and E) on data signals input from two measuring instruments to input cells A and B individually, and outputs a control signal based on the result of the arithmetic processing from output cell F to the equipment to be controlled. Of the three arithmetic cells, arithmetic cells C and E, which receive signals only from the preceding input cell or arithmetic cell, correspond to the third arithmetic cell. Arithmetic cell E also corresponds to the second arithmetic cell. Arithmetic cell D, which receives signals from the preceding input cell B and the following arithmetic cell E, corresponds to the first arithmetic cell.

[0028] In this embodiment, the order in which each cell constituting the control program performs arithmetic processing, etc. is determined in advance at the time of creating the instrumentation drawing. The control unit 11 is provided with a timing signal generating section (e.g., a clock signal generating section) that generates a timing signal (e.g., a clock signal) at a predetermined time interval, and each time this timing signal is generated, each cell performs arithmetic processing, etc. in a predetermined order.

[0029] Before describing the specific operation of the control program of the monitoring and control system of this embodiment, problems that arise in conventional control programs will be described.

[0030] Fig. 4 is an example of a conventional control program. The connection state of the cells constituting the control program in Fig. 4 (connection state of the input cell, the arithmetic cell, and the output cell) is the same as that of the control program of this embodiment. However, in the conventional control program, each arithmetic cell simply outputs the status signal input from the preceding input cell or arithmetic cell to the succeeding arithmetic cell or output cell, and does not have a configuration equivalent to the status fixed signal unit 83 in this embodiment.

[0031] In the control program shown in Fig. 4, when a data signal is input from a measuring instrument to input cell A, input cell A generates a status signal indicating whether the data signal is normal or abnormal, and outputs the status signal to the downstream processing cell C together with the data signal. Similarly, input cell B outputs a status signal indicating whether the data signal is normal or abnormal to the downstream processing cell D together with the data signal input from the measuring instrument. Processing cells C to E each perform a predetermined processing operation on the input data signal and output it to the downstream processing cell or output cell. Also, processing cells C to E each output the input status signal as it is to the downstream processing cell or output cell (i.e., they inherit the input status signal). This is the normal operation of the control program shown in Fig. 4.

[0032] In the monitoring and control system shown in Figure 4, let us assume that an abnormality occurs in the data signal input from the measuring instrument to input cell B. When an abnormality occurs in the data signal from the measuring instrument, input cell B generates a status signal (inheritance bit: ON) indicating the abnormality. After that, the status signal (inheritance bit: ON) generated by input cell B indicating the abnormality is inherited in order to operation cell D and operation cell E ((1) When an abnormality occurs). Note that in Figure 4, the hatched cells indicate the cells that output the status signal indicating the abnormality.

[0033] Thereafter, when the data signal input from the measuring instrument to input cell B returns to normal, input cell B generates a status signal (inheritance bit: OFF) indicating normality and inputs it to operation cell D.

[0034] However, when a loop-shaped signal path is included as in Figure 4, not only is a status signal indicating normality (inheritance bit: OFF) input to input cell B, but a status signal indicating an abnormality (inheritance bit: ON) that was generated in input cell B at the time when the data signal from the measuring instrument was abnormal and inherited by operation cells D and E is also input to operation cell D. As a result, operation cell D inherits the status signal indicating an abnormality that was input from operation cell E. As a result, as shown in (2) after recovery to normal, there is a problem in that the status signals indicating an abnormality continue to be inherited in operation cells D and E, which are included in the loop-shaped signal path.

[0035] A normal operation of the control program of this embodiment shown in Fig. 3 will be described. In the control program of this embodiment as well, when a data signal is input from a measuring instrument to input cell A, input cell A generates a status signal indicating whether the data signal is normal or abnormal, and outputs the status signal together with the data signal to downstream processing cell C. Input cell B similarly outputs a status signal indicating whether the data signal is normal or abnormal, together with the data signal input from the measuring instrument, to downstream processing cell D. Input cell A and input cell B also generate a status fixed signal (indefinite bit: OFF) indicating that the status signal is not fixed, and output the status signal to the downstream processing cell.

[0036] In the monitoring and control system of this embodiment, it is assumed that an abnormality occurs in the data signal input from the measuring instrument to the input cell B. When an abnormality occurs in the data signal from the measuring instrument, the input cell B generates a status signal (inheritance bit: ON) indicating the abnormality. Furthermore, even if an abnormality occurs in the data signal input from the measuring instrument, the input cell B generates a status fixed signal (indefinite bit: OFF) indicating that the status signal is not fixed, regardless of the abnormality. After that, the status signal (inheritance bit: ON) indicating the abnormality and the status fixed signal (indefinite bit: OFF) indicating that the status signal is not fixed, which are generated in the input cell B, are successively inherited by the operation cell D and the operation cell E in this order ((1) When an abnormality occurs). In FIG. 3 as well, the hatched cells indicate the cells that output the status signal indicating the abnormality.

[0037] After that, when the data signal input from the measuring instrument to input cell B returns to normal, input cell B generates a status signal (inherited bit: OFF) indicating normality. Input cell B also generates a status fixed signal (indefinite bit: OFF) indicating that the status signal is not fixed, and outputs it to calculation cell D. In calculation cell D, in response to the status fixed signal (indefinite bit: OFF) indicating that the status signal input from the previous input cell B has switched from one indicating an abnormality (inherited bit: ON) to one indicating normality (inherited bit: OFF), calculation cell D generates a status fixed signal (indefinite bit: ON) indicating that the status signal is fixed, and outputs it to the subsequent calculation cell E.

[0038] In this embodiment, a loop-shaped signal path is also formed that returns the data signal, status signal, and fixed status signal of the calculation result in the subsequent calculation cell E to the calculation cell D, so that the status signal (inheritance bit: ON) indicating the abnormality of the data signal, which is generated in the input cell B when the data signal of the measuring instrument is abnormal and inherited by the calculation cell D and the calculation cell E, is input again to the calculation cell D. In the example of FIG. 3, the status signal (inheritance bit: ON) indicating the abnormality is input from the calculation cell E to the calculation cell D together with the data signal of the calculation process. However, even if the status signal input from the subsequent calculation cell E indicates an abnormality (inheritance bit: ON), the calculation cell D does not inherit it and outputs a status signal (inheritance bit: OFF) indicating normality to the subsequent calculation cell E ((2) after returning to normal). Note that the cell indicated by the dashed line in FIG. 3 is a calculation cell that outputs a fixed status signal indicating a fixed state of the status signal.

[0039] In operation cell D, from the point in time when the status signal input from input cell B switches from one indicating an abnormality (inheritance bit: ON) to one indicating normality (inheritance bit: OFF), the operation cell D continues to generate a status fixed signal (indefinite bit: ON) indicating that the status signal is fixed for a predetermined time.

[0040] When the status signal input from input cell B located in the preceding stage changes to one indicating an abnormality (inheritance bit: ON), the input status signal is output as is to the subsequent calculation cell E. Specifically, when an abnormality occurs again in the data signal from the measuring instrument and a status signal indicating an abnormality in the data signal is generated again in input cell B, a status signal indicating the abnormality (inheritance bit: ON) and a status fixed signal indicating that the status signal is not fixed (indefinite bit: OFF) are input from input cell B to calculation cell D. In this case, calculation cell D outputs the input status signal (inheritance bit: ON) as is to the subsequent calculation cell E. In this case, the above-mentioned predetermined time can be reset and the status fixed signal changed to OFF.

[0041] In the processing cell D, when a predetermined time has elapsed since the time when the status signal input from the input cell B has switched from one indicating an abnormality (inheritance bit: ON) to one indicating normality (inheritance bit: OFF), the processing cell D stops generating a status fixed signal indicating that the status signal is fixed (generates a status fixed signal (indefinite bit: OFF) indicating that the status fixed signal is not fixed), and outputs the input status signal as is to the subsequent processing cell E, returning to normal operation ((3) after the predetermined time has elapsed). As described above, this predetermined time is set to a time longer than the time (loop time) required for the data signal output from the processing cell D, which is the second processing cell, to return to the processing cell D via one or more subsequent processing cells E. Therefore, after this predetermined time has elapsed, the status signal indicating an abnormality output from the processing cell D when the abnormality occurred ((1) is not inherited by the processing cell D.

[0042] Thus, the control program of this embodiment is characterized in that in a first processing cell that receives, in addition to a signal from an input cell or processing cell located in a preceding stage, a signal from one or more second processing cells located in a succeeding stage, a fixed status signal (indefinite bit: ON) is generated indicating that the status signal is fixed for a predetermined time from the point in time when the status signal input from the input cell or processing cell in the preceding stage changes from abnormal to normal, and during that time, even if the status signal input from the second processing cell indicates an abnormality (inheritance bit: ON), a status signal indicating normality (inheritance bit: OFF) is output to the succeeding processing cell without inheriting that status signal. And by having this feature, it is possible to correctly reflect in each cell in the control program that the data signal input to the input cell has returned from abnormal to normal.

[0043] In this embodiment, it is preferable to adopt a configuration in which each cell constituting the control program is displayed on the screen of the display unit of the operator terminal 2 while the control program is running. At this time, the operator terminal 2 displays each cell in a manner that is identifiable according to the state of the status signal and the status fixed signal. For example, input cells and operation cells that have output a status signal indicating normality are displayed in blue, and input cells and operation cells that have output a status signal indicating abnormality are displayed in red (i.e., cells are displayed in different colors according to the status signal). In addition, operation cells that have output a status fixed signal are displayed in a blinking manner, so as to be distinguishable from the other operation cells. This makes it possible to visually confirm the contents of the status signal and the status fixed signal output by each cell.

[0044] The above embodiment is merely an example and can be modified as appropriate in accordance with the spirit of the present invention.

[0045] In the control program shown in FIG. 3, a small number of arithmetic cells are connected and the arithmetic program includes only one loop-shaped signal path for ease of explanation, but the above-mentioned configuration can be adopted for an arithmetic program including multiple loop-shaped signal paths. When multiple loop-shaped signal paths are formed for one first arithmetic cell and signals are input from multiple second arithmetic cells, the time required for a signal to return from the second arithmetic cells to the first arithmetic cell is set to a time longer than the longest time (longest loop time) among the multiple loop-shaped signal paths. Note that when multiple loop-shaped signal paths are provided in series, the configuration may be such that a status fixed signal (indefinite bit: ON) output from the loop-shaped signal path on the front stage, which indicates that the status signal is fixed, is not input to the first arithmetic cell included in the loop-shaped signal path on the rear stage. Specifically, a arithmetic cell may be sandwiched between the loop-shaped signal path on the front stage and the loop-shaped signal path on the rear stage, and the arithmetic cell may be set not to inherit the status fixed signal.

[0046] In the above embodiment, a status fixed signal indicating a fixed state of the status signal is used, but it may be configured without using a status fixed signal. In that case, when the status signal input from the preceding processing cell changes from a signal indicating an abnormality to a signal indicating a normal state, the first processing cell outputs a status signal indicating a normal state to the succeeding processing cell regardless of the status signal input from the second processing cell while the timing signal is generated a predetermined number of times from the time point when the status signal changes, or while the processing in the first processing cell is performed a predetermined number of times, and outputs the input status signal as it is to the status signal section of the succeeding processing cell in other cases.

[0047] [Aspects] It will be apparent to those skilled in the art that the above-described exemplary embodiments are illustrative of the following aspects.

[0048] (Section 1) One aspect of the present invention is an equipment control device that performs arithmetic processing using a plurality of mutually connected arithmetic cells based on a measurement signal input from a measuring instrument, and controls an equipment based on the results of the processing, the plurality of arithmetic cells include a first arithmetic cell to which the measurement signal or a signal from a preceding arithmetic cell and a signal from one or more subsequent arithmetic cells are input, the first calculation cell includes a calculation unit and a status signal unit; the calculation unit of the first calculation cell performs a predetermined calculation process based on the measurement signal or a signal from a preceding calculation cell and a signal from the second calculation cell, and outputs the result as an output signal to the calculation unit of a succeeding calculation cell or the device; When the status signal input from the preceding calculation cell changes from a signal indicating an abnormality to a signal indicating normality, the status signal section of the first calculation cell outputs a status signal indicating normality to the succeeding calculation cell for a predetermined time from the time when the status signal changes, regardless of the status signal input from the second calculation cell, and in all other cases outputs the input status signal as is to the status signal section of the succeeding calculation cell.

[0049] The device control device according to paragraph 1 is used to perform arithmetic processing by a plurality of interconnected arithmetic cells based on a measurement signal input from a measuring instrument, and to control the device based on the results. The plurality of arithmetic cells includes a first arithmetic cell to which, in addition to the measurement signal or a signal from a preceding arithmetic cell, a signal from one or more subsequent second arithmetic cells is input.

[0050] The first arithmetic cell includes a calculation unit and a status signal unit. The calculation unit of the first arithmetic cell performs a predetermined calculation process on the input signal and outputs the calculation result to the calculation unit of the subsequent cell or the device.

[0051] When the status signal input from the preceding calculation cell changes from a signal indicating an abnormality to a signal indicating normality, the status signal section of the first calculation cell outputs a status signal indicating normality to the status signal section of the succeeding calculation cell for a predetermined time from the time when the status signal changed, regardless of the status signal input from the second calculation cell, and in all other cases outputs the input status signal as is to the status signal section of the succeeding calculation cell.

[0052] In the device control device according to paragraph 1, even if an abnormality status signal is input to the first arithmetic cell from a second arithmetic cell located one or more stages downstream during the specified time, the abnormality status signal is not inherited by the subsequent arithmetic cell. After the specified time has elapsed, the first arithmetic cell outputs the input status signal as is to the subsequent arithmetic cell. Therefore, even if a status signal indicating an abnormality is input from a arithmetic cell located one or more stages downstream after the measurement signal has returned to normal, the device is not affected and can appropriately reflect that the measurement signal has returned from an abnormal state to normal.

[0053] (Section 2) The device control device according to paragraph 2 is a device control device according to paragraph 1, The first processing cell further includes a status fixing signal unit, The status fixed signal section of the first processing cell generates a status fixed signal indicating that the status signal has been fixed for the specified period of time from the time the status signal changed when the status signal input from the preceding processing cell changes from a signal indicating an abnormality to a signal indicating normality.

[0054] In the device control device according to paragraph 2, it is possible to confirm that the status signal is in a fixed state based on the signal generated by the status fixing signal section.

[0055] (Section 3) The equipment control device according to paragraph 3 is an equipment control device according to paragraph 1 or 2, The predetermined time is set to be longer than the time required for the signal output from the first processing cell to be input to the first processing cell via the second processing cell.

[0056] In the device control device according to paragraph 3, it is possible to reliably prevent an abnormal status signal input from one or more downstream processing cells from being inherited after the measurement signal has returned to normal.

[0057] (Section 4) The equipment control device according to paragraph 4 is an equipment control device according to any one of paragraphs 1 to 3, An input signal is received from a plurality of the one or a plurality of downstream processing cells for one of the first processing cells; The predetermined time is set to be longer than the longest time required for a signal output from the first processing cell to be input to the first processing cell via each of the second processing cells.

[0058] In the device control device according to paragraph 4, even if multiple loop-shaped signal paths are included, it is possible to appropriately reflect the return of a measurement signal from an abnormality to a normal state.

[0059] (Section 5) The equipment control device according to paragraph 5 is an equipment control device according to any one of paragraphs 1 to 3, further comprising: a terminal device for displaying, on the display unit, the plurality of mutually connected processing cells in a distinguishable manner in accordance with a status signal and a status fixed signal outputted from each processing cell; Equipped with.

[0060] In the device control device according to paragraph 5, the state of each cell can be easily visually confirmed based on the display state of the cell on the screen of the terminal device. [Explanation of symbols]

[0061] 1...Control device 10...Communication unit 11…Control unit 12...I / O unit 2. Operator terminal 3…Engineering terminal 4. Control network 5. Field equipment 6. Local network 8...Calculation cell 80...Operation type information 81...Arithmetic section 811...Operation type information 812...Parameter information 82...Status signal section 83…Status fixed signal section 84…Connection information

Claims

1. An equipment control device that performs arithmetic processing by a plurality of mutually connected arithmetic cells based on a measurement signal input from a measuring instrument, and controls equipment based on the results of the arithmetic processing, the plurality of arithmetic cells include a first arithmetic cell to which the measurement signal or a signal from a preceding arithmetic cell and a signal from one or more subsequent second arithmetic cells are input, the first calculation cell includes a calculation unit and a status signal unit; the calculation unit of the first calculation cell performs a predetermined calculation process based on the measurement signal or a signal from a preceding calculation cell and a signal from the second calculation cell, and outputs the result as an output signal to the calculation unit of a succeeding calculation cell or the device; An equipment control device, wherein the status signal section of the first arithmetic cell outputs a status signal indicating normality to the status signal section of the subsequent arithmetic cell for a predetermined period of time from the time the status signal input from the previous arithmetic cell changes from a signal indicating abnormality to a signal indicating normality regardless of the status signal input from the second arithmetic cell, and in other cases outputs the input status signal as is to the status signal section of the subsequent arithmetic cell.

2. The first processing cell further includes a status fixing signal unit, 2. The equipment control device according to claim 1, wherein the status fixed signal section of the first calculation cell generates a status fixed signal indicating that the status signal has been fixed for the predetermined period of time from the time the status signal input from the calculation cell in the preceding stage changes from a signal indicating an abnormality to a signal indicating normality.

3. The device control device according to claim 1 , wherein the predetermined time is set to be longer than a time required for a signal output from the first processing cell to be input to the first processing cell via the second processing cell.

4. An input signal is received from a plurality of the one or a plurality of downstream processing cells for one of the first processing cells; The equipment control device according to claim 1 , wherein the specified time is set longer than the longest time required for a signal output from the first processing cell to be input to the first processing cell through each of the second processing cells.

5. moreover, a terminal device for displaying, on the display unit, the plurality of mutually connected processing cells in a distinguishable manner in accordance with a status signal and a status fixed signal outputted from each processing cell; The equipment control device according to claim 1 .

Images