Semiconductor device

Abstract

To provide a method for manufacturing a display device including a highly reliable thin film transistor with controlled threshold.SOLUTION: A gate insulating film is formed on a gate electrode. A microcrystalline semiconductor film is formed on the gate insulating film. To the microcrystalline semiconductor film, an impurity element for controlling threshold is added by an ion implantation method. After that, the microcrystalline semiconductor film is irradiated with a laser beam in order to improve the crystallinity. Then, a buffer layer is formed on the microcrystalline semiconductor film and thus, a channel-etched thin film transistor is formed. In addition, a display device including the thin film transistor is manufactured.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a circuit configured with thin film transistors (hereinafter referred to as TFTs). The present invention relates to a device and a method for manufacturing the same, for example, an electro-optical device such as a liquid crystal display panel, The present invention relates to an electronic device that incorporates a light-emitting display device having a light-emitting element as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) has been attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Development of this technology as a photonics element is being rushed.

[0004] Thin film transistors using amorphous semiconductor films as switching elements for image display devices Alternatively, a thin film transistor using a polycrystalline semiconductor film or the like is used.

[0005] Thin film transistors using amorphous semiconductor films are made of amorphous silicon films such as hydrogenated amorphous silicon films. Because a high-temperature semiconductor film is used, the process temperature is limited to 400℃, at which hydrogen is released from the film. The above heating and laser light irradiation with an intensity that would cause surface roughness due to hydrogen in the film are not performed.

[0006] In addition, the method for forming the polycrystalline semiconductor film is to preliminarily form an amorphous After dehydrogenation to reduce the hydrogen concentration in the silicon film, a pulsed excimer laser was The laser beam is processed into a linear shape by an optical system, and the dehydrogenated amorphous silicon film is On the other hand, a technique is known in which crystallization is carried out by irradiating a linear beam while scanning it.

[0007] A thin film transistor using a polycrystalline semiconductor film is a thin film transistor using an amorphous semiconductor film. Its mobility is more than two orders of magnitude higher than that of conventional devices, and it is possible to mount the pixel section of a display device and its surrounding driving circuitry on the same substrate. However, when an amorphous semiconductor film is used, In comparison, the process is complicated due to the crystallization of the semiconductor film, which reduces the yield and There is a problem of increased strikes.

[0008] In addition, the channel formation region is a semiconductor that consists of a mixture of crystalline and amorphous structures. A field effect transistor (FET) is disclosed in Patent Document 1.

[0009] In addition, a thin-film transistor using a microcrystalline semiconductor film is used as a switching element of an image display device. In this regard, a magnetron is used (Patent Documents 2 and 3).

[0010] The conventional method for manufacturing thin-film transistors involves depositing an amorphous silicon film on a gate insulating film. After the deposition, a metal film is formed on the top surface of the film, and the metal film is irradiated with a diode laser to form an a Technology to modify amorphous silicon film into microcrystalline silicon film (Non-Patent Document 1) According to this method, the metal film formed on the amorphous silicon film is It is used to convert the light energy of a diode laser into thermal energy. The metal film was then removed to complete the transistor. The amorphous silicon film is heated only by induction heating, and the microcrystalline silicon film This is a method for forming a [Prior art documents] [Patent documents]

[0011] [Patent Document 1] US Patent No. 5,591,987 [Patent Document 2] Japanese Patent Application Publication No. 4-242724 [Patent Document 3] JP 2005-49832 A [Non-patent literature]

[0012] [Non-Patent Document 1] Toshiaki Arai et al., SID 07 DIGEST, 2007, p.1370-1373 Summary of the Invention [Problem to be solved by the invention]

[0013] In thin-film transistors, a certain voltage value (called the threshold voltage (Vth)) is turned on at the gate. A switch that is turned on when a voltage is applied to the electrode and turned off when the voltage is less than that value. This threshold voltage (Vth) is the current-voltage characteristic graph of the thin film transistor. The threshold voltage (Vt h) The closer to 0V, the better. A transistor can be said to be an ideal switching element.

[0014] Due to unspecified factors in the manufacturing process of thin-film transistors, the threshold voltage may shift to the negative side. If the shift from 0V is large, the drive This leads to an increase in dynamic voltage, resulting in an increase in power consumption of the semiconductor device.

[0015] Even in a thin film transistor using a microcrystalline semiconductor film, the threshold voltage The voltage may shift to the negative or positive side.

[0016] In view of the above-mentioned problems, a thin film using a microcrystalline semiconductor film in which a threshold voltage is controlled to a desired value is provided. An object of the present invention is to propose a method for manufacturing a display device including a transistor. [Means for solving the problem]

[0017] After forming the gate electrode, a gate insulating film is formed, and a 10 nm thick film is formed on the gate insulating film. A microcrystalline semiconductor film having a thickness of about 50 nm is formed. In order to control the conductivity, impurity elements (p-type impurity elements or n-type impurity elements) are used to give a certain conductivity. A small amount of boron is intentionally added to the microcrystalline semiconductor film by ion implantation or the like. After the addition, a laser treatment is performed to activate the added boron and to form a gate insulating film and a microcrystalline semiconductor. The crystallinity of the microcrystalline semiconductor film at the interface with the semiconductor film is improved in the same process. Laser Process (hereinafter referred to as "LP") is a process that produces microcrystals by radiant heating. This is a solid-phase crystal growth method that does not melt the semiconductor film. This method utilizes the critical region where the film does not become liquid, and in that sense it is also called "critical growth." It can be said.

[0018] In this manner, a microcrystalline semiconductor film that functions as a channel formation region is formed on the gate insulating film. The microcrystalline semiconductor film obtained by performing LP processing on the formed microcrystalline semiconductor film is called LPSAS ( Laser Process Semi Amorphous Semiconductor After the laser irradiation, a film made of an amorphous semiconductor is formed on the microcrystalline semiconductor film. A buffer layer is then laminated on the buffer layer. A pair of source and drain regions is then formed on the buffer layer. and exposing a portion of the source region and the drain region. A pair of source and drain electrodes are formed in contact with the region.

[0019] In the thin film transistor having the above structure, a channel formation region is formed using a microcrystalline semiconductor film. Therefore, the field effect mobility is higher than that of a thin film transistor using a conventional amorphous semiconductor film.

[0020] A small amount of boron is added to the microcrystalline semiconductor film that functions as a channel formation region. In addition, the threshold voltage of the thin film transistor is controlled, and the oxidation of the microcrystalline semiconductor film is prevented. The buffer layer functions as a high-resistance region, reducing leakage current of thin-film transistors. It has low and high pressure resistance.

[0021] In addition, a thin film transistor (TFT) is manufactured using a microcrystalline semiconductor film. A display device is manufactured by using the microcrystalline semiconductor film in the pixel portion and further in the driver circuit. The thin film transistor used in the hole formation region has a mobility of 1 to 20 cm 2 / V sec and It has a mobility 2 to 20 times higher than that of thin-film transistors that use an amorphous semiconductor film in the channel formation region. Therefore, a part or the whole of the driver circuit is formed on the same substrate as the pixel section, and the system A moon panel can be formed.

[0022] The present invention relates to a method for manufacturing a semiconductor device, and the method comprises forming a gate electrode on a substrate. forming a second insulating film on the gate electrode; forming a second insulating film on the gate electrode; A first semiconductor film is formed, and a p-type impurity element or an n-type impurity element is added to the first semiconductor film. A second semiconductor film is formed by irradiating the second semiconductor film with laser light, and a third semiconductor film is formed by irradiating the second semiconductor film with laser light. a buffer layer is formed on the third semiconductor film, and an n-type impurity source is formed on the buffer layer; A fourth semiconductor film containing a semiconductor element is formed, and a source electrode or a drain electrode is formed on the fourth semiconductor film. This is a method for manufacturing a display device that forms a pole.

[0023] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the third semiconductor film is a The semiconductor film having a higher crystallinity than the semiconductor film of the first embodiment is a microcrystalline semiconductor film having a higher crystallinity than the semiconductor film of the first embodiment. This indicates that the crystalline / amorphous peak intensity ratio (hereinafter referred to as Ic / Ia) is high.

[0024] The present invention solves at least one of the above problems.

[0025] Microcrystalline semiconductor films are formed using high-frequency plasma CVD equipment with frequencies ranging from several tens to several hundreds of MHz. The film can be formed by a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, it can be formed by diluting silicon hydrides such as SiH4 and Si2H6 with hydrogen. In addition to silicon hydride and hydrogen, helium, argon, krypton, and neon can also be used. A microcrystalline semiconductor film can be formed by diluting with one or more selected rare gas elements. In these cases, the flow rate ratio of hydrogen to silicon hydride is preferably 12 to 1000 times. Preferably, the ratio is 50 to 200 times, more preferably 100 times. Instead, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. .

[0026] In addition, the amount of hydrogen in the microcrystalline semiconductor film obtained by the above-mentioned film formation method immediately after the film formation is usually Since the amount of hydrogenated amorphous silicon is smaller than that of hydrogenated amorphous silicon, no heat treatment for dehydrogenation is required. Both can be processed by LP.

[0027] When a microcrystalline semiconductor film having a thickness of 10 nm to 50 nm is formed on a gate insulating film, the thickness is thin. Therefore, it is difficult to obtain a highly crystalline film immediately after deposition. Therefore, even if half of the film is amorphous, at least the film after deposition contains fine crystals that can be the nuclei of growth. Therefore, it is possible to increase the margin of the film formation conditions of the microcrystalline semiconductor film. This can be done.

[0028] In addition, mass separation is performed on the microcrystalline semiconductor film that is to be the channel formation region of the thin film transistor. The threshold voltage is intentionally increased by adding impurity elements that give a single conductivity using an ion implantation method. The impurity elements that give the material a single conductivity are phosphorus, arsenic, and boron. The dopant gas used in the mass-separated ion implantation method is phosphatase. Examples include fin and diborane. Impurity elements that give one conductivity by ion implantation By adding, even if the crystallinity decreases compared to immediately after film formation, the LP treatment is performed. Ultimately, the crystallinity can be improved.

[0029] In addition, the present invention is not limited to an ion implantation device, and may be applied to a microcrystalline semiconductor film having a thickness of 10 nm to 50 nm. If it is possible to control the threshold value by adding impurity elements that give electrical conductivity, it would be possible to An on-doping device or the like may also be used.

[0030] Impurities that impart one conductivity to a microcrystalline semiconductor film of 10 nm to 50 nm by ion implantation. In order to add a desired amount of an element, for example, a silicon nitride film having a desired thickness is formed, and then ion implantation is performed. Alternatively, the LP process may be performed after removing the silicon nitride film. The thickness of the silicon nitride film used for adjustment is determined based on the concentration profile of the dopant ion-implanted into the sample. The dopant gas used in the mass-separated ion implantation method can be calculated from the B 10 H 14 , B 18 H 22 If ion implantation is performed using The amount of boron added can be reduced, and a desired amount of boron can be added to a microcrystalline semiconductor film of 10 nm to 50 nm. It can be done.

[0031] Doping is performed to control the threshold value using an ion implantation device or ion doping device. However, by performing LP treatment after doping, the damage is reduced. Depending on the LP processing conditions, the image can be recovered, and the microcrystalline semiconductor film can be made to have a larger size than before doping. It is also possible to improve the crystallinity.

[0032] The microcrystalline semiconductor film may be heated while being irradiated with a laser beam. Typically, the substrate is heated to 300°C to 400°C and irradiated with a laser beam. By irradiating the light, the crystallinity of the microcrystalline semiconductor film can be improved. The temperature of the microcrystalline semiconductor film is instantaneously increased by irradiating the film with a laser beam and strong light. A typical example of strong light is infrared light, especially light with a peak at 1 μm to 2 μm. For this purpose, infrared light (preferably halogen light (1.3 μm)) can be used.

[0033] In addition, if a thin oxide film is formed during LP processing, it can be removed by wet etching. It is preferable that the oxide film is removed to form a layer at the interface between the LPSAS film and the buffer layer. It is possible to reduce the inhibition of carrier movement caused by the oxide film. The thickness of the LPSAS film may be reduced by etching. By setting the upper limit at 50 nm or less, a fully depleted type thin film transistor can be fabricated.

[0034] In addition, it is preferable to clean the surface of the microcrystalline semiconductor film before the LP treatment. By cleaning, impurities attached to the surface of the microcrystalline semiconductor film are removed by laser beam irradiation. It is possible to prevent the crystalline semiconductor film from being contaminated.

[0035] In addition, after LP processing, ion implantation is performed, and then a second LP processing or heat treatment is performed. Another aspect of the present invention is to form a gate electrode on a substrate, and an insulating film on the gate electrode. a first semiconductor film is formed on the insulating film so as to overlap the gate electrode; A second semiconductor film is formed by irradiating a first laser beam onto the semiconductor film, and the second semiconductor film is p a third semiconductor film is formed by doping a n-type impurity element or an n-type impurity element; A fourth semiconductor film is formed by irradiating the semiconductor film with a second laser beam, and a backing is formed on the fourth semiconductor film. a fifth semiconductor film containing an n-type impurity element is formed on the buffer layer; The fifth aspect of the present invention is a method for manufacturing a display device, comprising forming a source electrode or a drain electrode on the semiconductor film. do.

[0036] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the fourth semiconductor film is a The semiconductor film in FIG. 1 is a microcrystalline semiconductor film having higher crystallinity than the semiconductor film in FIG.

[0037] The present invention solves at least one of the above problems.

[0038] If the crystallinity of the microcrystalline semiconductor film is improved by performing LP processing in advance, the crystallinity of the microcrystalline semiconductor film can be improved by ion implantation. It is possible to prevent the semiconductor film from becoming completely amorphous. The second LP treatment does not have to be performed under the same conditions. The oxide film formed during the second LP treatment is It is preferable to remove the SiO 2 layer before forming the SiO 2 layer. However, an oxide film is formed on the surface even in the case of the above-mentioned method, so it is preferable to remove it before forming the buffer layer. I wish.

[0039] In addition, the present invention is not limited to ion implantation after film formation, but may be used to control the threshold voltage of thin film transistors. A microcrystalline semiconductor film is formed by adding a small amount of boron or phosphorus element during film formation, and after film formation, The LP process may be performed. Another aspect of the present invention is to form a gate electrode on a substrate, An insulating film is formed on the electrode, and a first insulating film containing a p-type impurity element or an n-type impurity element is formed on the insulating film. forming a first semiconductor film, and irradiating the first semiconductor film with laser light to form a second semiconductor film; a buffer layer is formed on the second semiconductor film, and an n-type impurity element is doped on the buffer layer; A third semiconductor film containing a source electrode or a drain electrode is formed on the third semiconductor film. The present invention relates to a method for manufacturing a display device.

[0040] In the above manufacturing method, the first semiconductor film is a microcrystalline semiconductor film, and the second semiconductor film is a The semiconductor film in FIG. 1 is a microcrystalline semiconductor film having higher crystallinity than the semiconductor film in FIG.

[0041] The present invention solves at least one of the above problems.

[0042] When a microcrystalline semiconductor film is formed by adding a small amount of boron during film formation, and LP processing is performed after film formation. Unlike ion implantation after film formation, there is no need to add a separate process to activate boron. The LP process improves the crystallinity of the film because it contains a small amount of boron during film formation. When the LP process is performed after the film formation, the ion implantation process and the ion This process is suitable for mass production because it eliminates the need for processes such as the cleaning process before implantation. A method for incorporating a small amount of boron is, for example, to use diborane gas as one of the deposition gases during deposition. This can be done by introducing a small amount of phosphorus into the film chamber. The method of forming a microcrystalline semiconductor film by mixing a small amount of fluorine with a gas during film formation is, for example, This can be achieved by introducing phosphine gas into the film formation chamber.

[0043] A display device obtained by using the above-mentioned manufacturing method is also one aspect of the present invention. A gate electrode is disposed on the substrate, an insulating film is disposed on the gate electrode, and a p-type A first semiconductor film containing an impurity element or an n-type impurity element, and a buffer layer on the first semiconductor film. a buffer layer, a second semiconductor film containing an n-type impurity element on the buffer layer, and a second semiconductor film on the second semiconductor film. and a source electrode or a drain electrode.

[0044] The display device includes a light-emitting device and a liquid crystal display device. The liquid crystal display device includes a liquid crystal element. The light-emitting element has a luminance controlled by a current or a voltage. This category includes elements that emit light, specifically inorganic EL (Electro Luminescence) cence), organic electroluminescence, etc.

[0045] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device according to the present invention further includes a module in which an IC including a laser and the like is mounted. In the process of manufacturing the display device, the element substrate corresponds to a form before the display device is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and This is a state after forming a conductive film having the above structure and before etching to form a pixel electrode. is fine, and all forms apply.

[0046] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted. Effect of the Invention

[0047] A microcrystalline semiconductor film containing a p-type impurity element or an n-type impurity element is used as a channel formation region. In addition, the p-type impurity element or the n-type impurity element intentionally included in the microcrystalline semiconductor film It is possible to realize a thin film transistor whose threshold voltage is controlled to a desired value. [Brief description of the drawings]

[0048] [Figure 1] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Diagram 2] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Diagram 3] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 4] 1A to 1C are top views showing a manufacturing process of the present invention. [Diagram 5] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 6] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 8] 1A and 1B are diagrams illustrating a multi-tone mask applicable to the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a manufacturing process of the present invention. [Figure 12] 1A to 1C are top views showing a manufacturing process of the present invention. [Figure 13] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 14] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 15] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 16] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 17] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 18] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 19] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 20] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 21] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 22] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Diagram 23] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 24] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Diagram 25] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 26] FIG. 1 is a diagram illustrating a liquid crystal display device of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a light-emitting device of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a pixel applicable to a light-emitting device of the present invention. [Figure 29] FIG. 1 is a perspective view illustrating a display panel of the present invention. [Diagram 30] FIG. 1 is a perspective view illustrating an electronic device using a light emitting device of the present invention. [Diagram 31] 1A to 1C are diagrams illustrating electronic devices using a light-emitting device of the present invention. [Diagram 32] FIG. 1 is a block diagram illustrating a configuration of a light emitting device according to the present invention. [Diagram 33] FIG. 2 is an equivalent circuit diagram illustrating a configuration of a drive circuit for the light emitting device of the present invention. [Diagram 34] FIG. 2 is an equivalent circuit diagram illustrating a configuration of a drive circuit for the light emitting device of the present invention. [Diagram 35] FIG. 2 is a top view illustrating the layout of a drive circuit of a light emitting device according to the present invention. [Diagram 36] 1A and 1B are a top view and a cross-sectional view illustrating a display panel of the present invention. [Figure 37] 1A and 1B are a top view and a cross-sectional view illustrating a display panel of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention may be embodied in many different ways. It is possible to modify the form and details without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the details of the present embodiment may be modified in various ways. It should not be construed as being limited to the contents described.

[0050] (Embodiment 1) In this embodiment mode, a manufacturing process of a thin film transistor used in a liquid crystal display device will be described with reference to FIG. 1 to 3 are cross-sectional views showing a manufacturing process of a thin film transistor. FIG. 4 is a top view of a connection region of a thin film transistor and a pixel electrode in one pixel. be.

[0051] Thin film transistors with microcrystalline semiconductor films have higher mobility in n-type transistors than in p-type transistors. It is more suitable for use in driving circuits. It is desirable to have the same polarity for the n-channel transistors in order to reduce the number of processes. A description will be given using a thin film transistor of this type.

[0052] As shown in FIG. 1A, a gate electrode 51 is formed on a substrate 50. The substrate 50 is a ballast. Borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass Non-alkali glass substrates and ceramic substrates manufactured by the fusion method or float method. In addition, a plastic substrate or the like that has heat resistance that can withstand the processing temperature of this manufacturing process should be used. Also, a substrate having an insulating film formed on the surface of a metal substrate such as a stainless steel alloy can be used. If the substrate 50 is a mother glass, the size of the substrate is 1st generation (320 mm x 40 0mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm) , 4th generation (680mm x 880mm, or 730mm x 920mm), 5th generation (1 000mm x 1200mm or 1100mm x 1250mm), 6th generation (1500m m x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160m m×2460mm), 9th generation (2400mm×2800mm, 2450mm×3050 mm), 10th generation (2950mm x 3400mm), etc. can be used.

[0053] The gate electrode 51 is made of titanium, molybdenum, chromium, tantalum, tungsten, aluminum, or the like. The gate electrode 51 is formed by sputtering. A conductive film is formed on the substrate 50 by a coating method or a vacuum deposition method, and then a photolithography is performed on the conductive film. A mask is formed by a technique or an inkjet method, and the conductive film is etched using the mask. It can be formed by applying conductive nano-paste such as silver, gold, or copper. The gate electrode 51 can be formed by discharging the material by an ink-jet method and baking it. The above-mentioned gold is used as a barrier metal for improving the adhesion of the gate electrode 51 and preventing diffusion to the substrate. A nitride film of a metal material may be provided between the substrate 50 and the gate electrode 51. A conductive film formed on the substrate 50 using a resist mask formed using the photomask The gate electrode is formed by etching.

[0054] As a specific example of the gate electrode structure, a molybdenum film is laminated on an aluminum film. It is also possible to use a structure that prevents hillocks and electromigration that are unique to aluminum. Alternatively, a three-layer structure may be used in which an aluminum film is sandwiched between molybdenum films. Examples of structures include a molybdenum film laminated on a copper film, a titanium nitride film laminated on a copper film, and a Examples of the tantalum nitride film include a laminate of the tantalum nitride film.

[0055] Since a semiconductor film and wiring are formed on the gate electrode 51, the end portion is made to be flat to prevent disconnection. It is desirable to process it so that it has a tapered shape. Also, although not shown, the gate is removed in this process. Wiring connected to the electrodes can also be formed at the same time.

[0056] Next, on the gate electrode 51, gate insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film 2 The cross-sectional view after completing the steps up to this point corresponds to FIG. 1(A). The gate insulating films 52a, 52b, and 52c and the microcrystalline semiconductor film 23a are not exposed to the air. It is preferable to form the film continuously. By forming the film continuously, the air components and the airborne particles can be prevented from being dispersed. Since each layer interface can be formed without being contaminated by contaminating impurity elements, thin film transistors This makes it possible to reduce the variation in transistor characteristics.

[0057] The gate insulating films 52a, 52b, and 52c are formed by using a CVD method, a sputtering method, or the like. The insulating film may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In order to prevent interlayer shorts caused by pinholes or the like formed in the gate insulating film 52, It is preferable to form a multi-layer structure using the insulating layers 52a and 52b. 52c, a silicon nitride film, a silicon oxynitride film, and a silicon nitride film are laminated in this order. Shows.

[0058] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. Rutherford Backscattering (RBS) Scattering Spectrometry (HSS) and Hydrogen Forward Scattering Spectroscopy (HFS) n Forward Scattering) is used for the measurement. Oxygen is 50-70 atomic %, nitrogen is 0.5-15 atomic %, Si is 25-35 atomic %, and hydrogen is The range of 0.1 to 10 atomic percent of silicon oxide is used. The nitrogen content is higher than the oxygen content as measured by RBS and HFS. In this case, the concentration range is 5 to 30 atomic % for oxygen, 20 to 55 atomic % for nitrogen, and 25 % to 35 atomic %, and hydrogen in the range of 10 to 30 atomic %.

[0059] The thickness of the first and second layers of the gate insulating film 52 is set to be greater than 50 nm. The first layer of the insulating film is made of nitrogen to prevent the diffusion of impurities (such as alkali metals) from the substrate. The first layer of the gate insulating film 52 is preferably a silicon oxide film or a silicon oxynitride film. In addition to preventing the oxidation of the electrode, it is possible to prevent hillocks when aluminum is used for the gate electrode. The third layer of the gate insulating film 52 in contact with the microcrystalline semiconductor film is thicker than 0 nm and less than 10 nm. The third layer of the gate insulating film 52 is made of a metal in order to improve adhesion with the microcrystalline semiconductor film. In addition, the third layer of the gate insulating film 52 is made of a silicon nitride film, so that the subsequent It is possible to prevent the microcrystalline semiconductor film from being oxidized by heat treatment or laser irradiation. For example, When heat treatment is performed in a state where an insulating film with a high oxygen content is in contact with a microcrystalline semiconductor film, There is a risk of the conductive film being oxidized.

[0060] Furthermore, the gate insulating film 52 is formed using a microwave plasma CVD apparatus with a frequency of 1 GHz. It is preferable to form a silicon oxynitride film using a microwave plasma CVD apparatus. The silicon oxide film has a high withstand voltage and can improve the reliability of the thin film transistor.

[0061] The microcrystalline semiconductor film 23a has an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal). This semiconductor has a third state that is stable in terms of free energy. A semiconductor having a short-range order and lattice distortion, and a grain size of 0. Columnar or needle-like crystals of 0.5 to 20 nm are growing in the normal direction to the substrate surface. A typical example of a microcrystalline semiconductor is a mixture of a microcrystalline semiconductor and a non-single-crystal semiconductor. Silicon has a Raman spectrum of 520.5 cm, which is indicative of single crystal silicon. -1 Lower than The wave number shifts to the 520.5 cm -1 and Amorph 480cm showing the assilicon -1 The Raman spectrum of microcrystalline silicon has a peak between In addition, hydrogen or halogen is used to terminate dangling bonds. In addition, helium, argon, krypton, etc. The inclusion of rare gas elements such as neon further increases the lattice distortion, making the material more stable. A good microcrystalline semiconductor film can be obtained. For example, the description of such a microcrystalline semiconductor film is Disclosed in U.S. Patent No. 4,409,134.

[0062] This microcrystalline semiconductor film 23a is subjected to high-frequency plasma CV having a frequency of several tens to several hundreds of MHz. It is formed by using a microwave plasma CVD device with a frequency of 1 GHz or more. Typically, silicon hydrides such as SiH4 and Si2H6 are diluted with hydrogen to form In addition to silicon hydride and hydrogen, helium, argon, krypton, etc. and diluting the gas with one or more rare gas elements selected from the group consisting of fluorine, fluorine, and neon to form a microcrystalline semiconductor film. In these cases, the flow rate ratio of hydrogen to silicon hydride is set to 12 times or more, i.e., 1000 times or more. 100 times or less, preferably 50 times to 200 times, and more preferably 100 times. Instead of silicon hydride, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. are used. It is possible.

[0063] The oxygen concentration of the microcrystalline semiconductor film 23a is set to 5×10 19 atoms / cm 3 Below is good Preferably 1×10 19 atoms / cm 3 In the following, the concentrations of nitrogen and carbon are 3×10 18 atoms / cm 3 It is preferable that oxygen, nitrogen, and carbon are not included in the microcrystalline semiconductor. By reducing the concentration of the impurities in the semiconductor film, it is possible to prevent the microcrystalline semiconductor film from becoming n-type. This can be done.

[0064] The thickness of the microcrystalline semiconductor film 23a is 1 nm or more and 20 nm or less, preferably 2 nm or more and 10 nm or less. In the LP process to be performed later, the thickness of the microcrystalline semiconductor film 23a is set to be 4 nm to 8 nm. m, the absorption rate of the laser beam can be increased. By setting the thickness of the microcrystalline semiconductor film 23a within the above range, The thin film transistor is a fully depleted type. Since the deposition speed is 1 / 10 to 1 / 100 of that of amorphous semiconductor films, the deposition speed can be reduced by making the film thinner. This can improve the investment.

[0065] In addition, before the microcrystalline semiconductor film 23a is formed, the surface of the gate insulating film 52c is irradiated with hydrogen plasma. By the hydrogen plasma treatment, the gate insulating film and the microcrystalline semiconductor film It is possible to reduce the lattice distortion at the interface, and the interface between the gate insulating film and the microcrystalline semiconductor film This improves the surface characteristics, and therefore the electrical characteristics of the thin film transistors to be formed later. It is possible to improve the performance.

[0066] Next, in order to control the threshold voltage, an impurity element that imparts one conductivity is intentionally implanted by ion implantation. The microcrystalline semiconductor film 23a just after deposition exhibits weak n-type electrical conductivity. Here, a small amount of boron is added to perform channel doping for controlling the threshold voltage. In this manner, as shown in FIG. 1B, a microcrystalline semiconductor film 23b containing boron is obtained. By the ion implantation, the microcrystalline semiconductor film 23a containing boron is formed as compared with the microcrystalline semiconductor film 23a immediately after the film formation. The crystallinity of the amorphous semiconductor film 23b decreases.

[0067] Next, in order to improve the crystallinity of the microcrystalline semiconductor film 23a immediately after the deposition, the microcrystalline semiconductor film The laser beam is irradiated from the surface side of the microcrystalline semiconductor film. The gate electrode 51 is located below, so it is not irradiated with the laser beam. The energy range should be determined taking into consideration the diffusion of heat generated by the laser beam. Depending on the energy of the laser, the microcrystalline semiconductor film in the region not overlapping with the gate electrode 51 may melt. On the other hand, the area overlapping the gate electrode 51 may not melt. Since the film quality is different between the region and the region not overlapping with the gate electrode, in this embodiment, In the semiconductor layer used as a thin film transistor, preferably, only the region overlapping with the gate electrode is The area overlapping the gate electrode is used except for the tapered portion of the gate electrode. By using a semiconductor film as the channel formation region, the characteristic variation between multiple thin film transistors can be reduced. can be reduced.

[0068] The laser beam can reach the interface between the microcrystalline semiconductor film and the gate insulating film 52c. As a result, the crystals on the surface side of the microcrystalline semiconductor film are used as seeds, and the gate insulating film is formed from the surface. A microcrystalline semiconductor film with improved crystallinity due to solid phase crystal growth at the interface of the insulating film, known as LPSA. The S film 53 can be formed (see FIG. 1(C)). The solid phase crystal growth by the LP process is It does not increase the grain size, but rather improves the crystallinity in the film thickness direction. That is, the LP treatment improves the crystallinity of the microcrystalline semiconductor film near the gate insulating film. This has the effect of improving the electrical characteristics of a thin film transistor having a bottom gate structure.

[0069] Furthermore, the LP treatment here also activates the boron added to the microcrystalline semiconductor film. The threshold voltage can be controlled to a desired value by the boron contained in the microcrystalline semiconductor film. For example, a thin film transistor can be obtained by using boron contained in a microcrystalline semiconductor film. If the threshold voltage can be controlled to 0V or to the negative side, a thin-film transistor can be When the gate voltage applied to the gate of the thin film transistor is set to 0V, the thin film transistor is in the off state. It is possible to use a normally-off switching element.

[0070] When using an excimer laser as the laser beam, the pulse oscillation frequency must be 1Hz or more and 10M or less. Hz, preferably 100 Hz to 10 kHz, and the laser energy is 0.2 to 0.3 5J / cm 2 (Typically 0.2-0.3J / cm 2 In addition, a YAG laser is used. If the third harmonic is used, the pulse oscillation frequency shall be 1 Hz or more and less than 10 MHz. Laser energy is 0.2 to 0.35 J / cm 2 (Typically 0.2-0.3J / cm 2 ) It would be better to say:

[0071] The laser oscillator that emits the laser beam can be either pulsed or continuous. In addition, the laser wavelength can be set to a value that efficiently transmits the laser light to the semiconductor film. The visible to ultraviolet region (800 nm or less) is preferably in the ultraviolet region ( The wavelength of the ultraviolet laser beam is 300 to 400 nm. The light is efficiently absorbed by the microcrystalline semiconductor film. Excimer laser oscillators such as ArF, XeCl, XeF, N2, He, He-Cd, Ar, Gas laser oscillators such as He-Ne, HF, CO2, YAG, GdVO4, YVO4, YL F, YAlO3, ScO3, Lu2O3, Y2O3 crystals with Cr, Nd, Er, Ho Solid-state laser oscillator using a crystal doped with Ce, Co, Ti, Yb, or Tm, KG Solid-state lasers such as W lasers, KYW lasers, Alexandrite lasers, and Ti:sapphire lasers For example, a metal vapor laser oscillator such as a helium cadmium laser can be used. In the solid-state laser oscillator, it is preferable to use the second to fifth harmonics of the fundamental wave. It is.

[0072] Typically, the laser beam has a wavelength of 400 nm or less, typically 308 nm. A laser beam or the third harmonic (355 nm) of a YAG laser is used.

[0073] LP processing is performed by concentrating light into a long rectangular shape and forming a linear laser beam, for example, 730 mm x 9 The microcrystalline semiconductor film 23b on the 20 mm glass substrate is processed by one laser beam scan. In this case, the overlap rate of the linear laser beams is The treatment is carried out at a rate of 0 to 95% (preferably 0 to 67%). This reduces the time required and improves productivity. The shape of the laser beam is not limited to a linear shape. The LP treatment can be applied to the glass as well as to the surface. The present invention is not limited to a particular size of the substrate, and can be applied to a variety of substrates.

[0074] In addition, when a continuous wave laser beam is used as the laser beam, a polygon mirror or a gas A laser mirror is placed between the oscillator and the substrate, and the laser beam is scanned at high speed to obtain the LP. It is possible to improve the throughput of processing, for example, a 730mm x 920mm gauge The microcrystalline semiconductor film formed on the glass substrate or the larger glass substrate is subjected to LP processing. It is possible.

[0075] In addition, the laser beam can be emitted in an argon atmosphere, a hydrogen atmosphere, an argon and hydrogen atmosphere, a nitrogen atmosphere, etc. In this manner, the microcrystalline semiconductor film 23b may be irradiated with a laser beam in an inert atmosphere. By irradiating the microcrystalline semiconductor film with light, an oxide film is formed on the surface of the LPSAS film 53. Pile.

[0076] In addition, before the microcrystalline semiconductor film 23b is irradiated with a laser beam, the surface of the microcrystalline semiconductor film 23b is By cleaning the surface, the surface of the microcrystalline semiconductor film 23b is free from the adhesion of the metal particles to the surface of the microcrystalline semiconductor film 23b during channel doping or the like. It is possible to prevent impurities from being mixed into the microcrystalline semiconductor film by laser beam irradiation. do.

[0077] The microcrystalline semiconductor film may be heated while being irradiated with a laser beam. Typically, the substrate 50 is heated to 300° C. to 400° C. while being irradiated with a laser beam. By this, the crystallinity of the microcrystalline semiconductor film 23b can be improved. The conductor film 23b is irradiated with a laser beam and strong light, and the microcrystalline semiconductor The temperature of the film 23b may be increased. A typical example of strong light is infrared light, particularly light of 1 μm to 2 μm. Infrared light having a peak at 1.3 μm (preferably halogen light (1.3 μm)) can be used. do.

[0078] Next, as shown in FIG. 1(D), a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 to which the impurity to be added is formed. If an oxide film is formed on the surface of the AS film 53, it is removed before forming the buffer layer 54. It is preferred.

[0079] The buffer layer 54 is formed using an amorphous semiconductor film containing hydrogen, nitrogen, or halogen. The flow rate of the silicon hydride is preferably 1 to 10 times, more preferably 1 to 5 times. By using hydrogen, an amorphous semiconductor film containing hydrogen can be formed. A nitrogen-containing amorphous semiconductor film is formed by using hydrogen and nitrogen or ammonia. In addition, the above silicon hydride and a gas containing fluorine, chlorine, bromine, or iodine (F 2, Cl2, Br2, I2, HF, HCl, HBr, HI, etc.) to obtain fluorine, An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed. Instead of silicon, use SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be done.

[0080] The buffer layer 54 is formed by sparging with hydrogen or a rare gas using an amorphous semiconductor as a target. In this case, ammonia, nitrogen, Alternatively, by including N2O in the atmosphere, an amorphous semiconductor film containing nitrogen can be formed. In addition, gases containing fluorine, chlorine, bromine, or iodine (F2, C I2, Br2, I2, HF, HCl, HBr, HI, etc.) An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed.

[0081] In addition, a buffer layer 54 is formed on the surface of the LPSAS film 53 by plasma CVD or sputtering. After forming an amorphous semiconductor film by a deposition method, the surface of the amorphous semiconductor film is irradiated with hydrogen plasma, The surface of the amorphous semiconductor film is hydrogenated and nitrogenated by treating it with nitrogen plasma or halogen plasma. Alternatively, the surface of the amorphous semiconductor film may be irradiated with helium plasma. Alternatively, the treatment may be performed with argon plasma, krypton plasma, or the like.

[0082] The buffer layer 54 is preferably formed of an amorphous semiconductor film that does not contain crystal grains. Therefore, high-frequency plasma CVD with frequencies of several tens to several hundreds of MHz or microwave plasma CVD is used. When forming the film using the Zuma CVD method, the film formation conditions are adjusted so that the film becomes an amorphous semiconductor film that does not contain crystal grains. It is preferable to control the condition.

[0083] The buffer layer 54 is partially etched in the subsequent process of forming the source and drain regions. At this time, a part of the buffer layer 54 is formed so that the LPSAS film 53 is not exposed. It is preferable to form the remaining thickness. Typically, the thickness is 100 nm or more and 400 nm or less. It is preferable to form the thin film transistor with a thickness of 200 nm or more and 300 nm or less. In display devices where a high voltage is applied to the transistor (for example, about 15 V), typically liquid crystal display devices If the thickness of the buffer layer 54 is made thicker as shown in the above range, the breakdown voltage becomes higher. To prevent the thin film transistor from deteriorating even when a high voltage is applied to the thin film transistor It is possible.

[0084] The buffer layer 54 is doped with impurities such as phosphorus or boron that impart one conductivity type. The LPSAS film 53 contains a small amount of boron to control the threshold voltage. Impurities are diffused from the semiconductor film 55, which is doped with impurities that impart one conductivity type, into the LPSAS film. The buffer layer 54 functions as a barrier layer to prevent the formation of the oxidized layer. In this case, the LPSAS film and the semiconductor film 55 doped with an impurity that imparts one conductivity type come into contact with each other. If the threshold voltage is increased, the impurities will move during the subsequent etching process or heat treatment, making it difficult to control the threshold voltage. There is a risk.

[0085] Furthermore, a buffer layer 54 is formed on the surface of the LPSAS film 53, thereby In particular, it is possible to prevent natural oxidation of the surfaces of the crystal grains contained in the amorphous semiconductor. In the area where the fine crystal grains contact, cracks are likely to occur due to local stress. When these cracks come into contact with oxygen, The grains are then oxidized to form silicon oxide.

[0086] The energy gap of the buffer layer 54, which is an amorphous semiconductor film, is smaller than that of the LPSAS film 53. The energy gap of the amorphous semiconductor film is 1.6 to 1.8 eV, and that of the LPSAS film is 53 The energy gap of LPS is 1.1-1.5 eV, and the resistance is high, the mobility is low, and the LPS This is 1 / 5 to 1 / 10 of the AS film 53. In this case, a buffer layer is formed between the source region and the drain region and the LPSAS film 53. The LPSAS film 53 functions as a channel forming region. Therefore, the off-current of the thin film transistor can be reduced. When used as a switching element of a display device, the contrast of the display device can be improved. can be done.

[0087] A buffer layer 54 is formed on the LPSAS film 53 by plasma CVD at 300° C. to 40° C. It is preferable to form the film at a temperature of 0° C. This film forming process causes hydrogen to enter the LPSAS film 53. The same effect as hydrogenating the LPSAS film 53 can be obtained. A buffer layer 54 is deposited on the LPSAS film 53 to diffuse hydrogen into the LPSAS film 53. In this way, dangling bonds can be terminated.

[0088] The semiconductor film 55 to which an impurity that imparts one conductivity type is added is an n-channel thin film transistor. When forming a transistor, phosphorus is added as a typical impurity element, and hydrogenation All you have to do is add an impurity gas such as PH3 to silicon. Also, p-channel thin film transistors In the case of forming a silicon hydride, boron may be added as a typical impurity element. The impurity gas, such as B2H6, can be added. The semiconductor film 55 can be formed of a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 to which the impurity is added is formed to a thickness of 2 nm to 50 nm. By thinning the thickness of the semiconductor film to which impurities that give the conductivity type are added, throughput can be improved. It can be improved.

[0089] Next, as shown in FIG. 2A, a semiconductor film 55 to which an impurity that imparts one conductivity type is added is formed. A resist mask 56 is formed on the insulating film 52 by photolithography or the like. In this embodiment, the first conductive film is formed by a second photomask. A resist applied onto the semiconductor film 55 to which an impurity for providing a pattern is added is exposed and developed. A resist mask 56 is formed.

[0090] Next, the LPSAS film 53, the buffer layer 54, and the conductive type are formed using a resist mask 56. The semiconductor film 55 to which the impurity is added is etched and separated, as shown in FIG. As shown in FIG. 1, the LPSAS film 61, the buffer layer 62, and the semiconductor substrate 61 are doped with an impurity that provides one conductivity type. A semiconductor film 63 is formed. After that, the resist mask 56 is removed.

[0091] The end side surfaces of the LPSAS film 61 and the buffer layer 62 are inclined, so that the buffer layer 6 A leakage current occurs between the source and drain regions formed on the LPSAS film 61 and the LPSAS film 62. In addition, the source electrode and the drain electrode and the LPS It is possible to prevent the occurrence of leakage current between the LPSAS film 61 and the LPSAS film 6 The inclination angle of the end side surface of the buffer layer 62 is 90° to 30°, preferably 80° to 40°. By setting the angle at this angle, the source or drain electrode This can prevent the poles from breaking off.

[0092] Next, as shown in FIG. 2C, a semiconductor film 63 and a The conductive films 65a to 65c are formed so as to cover the gate insulating film 52c. 5c is aluminum, copper, silicon, titanium, neodymium, scandium, molybdenum A single layer of aluminum alloy containing heat resistance improving elements such as carbides or hillock prevention elements. It is also preferable to form the semiconductor device by lamination. The film in contact with the conductive film is made of titanium, tantalum, molybdenum, tungsten, or any of these. A laminate formed of a nitride of the above element and aluminum or aluminum alloy formed on it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be made of a tin. Laminated layers sandwiched between tantalum, molybdenum, tungsten, or nitrides of these elements Here, the conductive film may have a structure in which three conductive films 65a to 65c are laminated. The conductive film 65a and 65c are made of molybdenum, and the conductive film 65b is made of aluminum. A laminated conductive film using a titanium film, a titanium film for the conductive film 65a and 65c, and an aluminum film for the conductive film 65b. The conductive films 65a to 65c are formed by sputtering or vacuum deposition. Formed by the method.

[0093] Next, as shown in FIG. 2(D), a third photomask is used to apply a mask to the conductive films 65a to 65c. A resist mask 66 is formed, and a part of the conductive films 65a to 65c is etched to form a pair of saw blades. The source electrodes and drain electrodes 71a to 71c are formed by wet etching the conductive films 65a to 65c. When etching is performed, the conductive films 65a to 65c are selectively etched. In order to etch the resist mask 66 isotropically, the source electrode and the drain electrode, which are smaller in area than the resist mask 66, are The rain electrodes 71a to 71c can be formed.

[0094] Next, as shown in FIG. 3A, a resist mask 66 is used to perform a process of forming an impurity layer that imparts one conductivity type. The semiconductor film 63 doped with Zn is etched to form a pair of source and drain regions 72. Furthermore, in this etching step, a part of the buffer layer 62 is also etched. The buffer layer in which a part is etched and a recess (groove) is formed is shown as buffer layer 73. The source and drain regions are formed in the same process as the recesses (grooves) in the buffer layer. The depth of the recess (groove) in the buffer layer can be determined by the thickness of the thickest part of the buffer layer. By making the distance between the source and drain regions 1 / 2 to 1 / 3 of the original value, the distance between the source and drain regions can be increased. Therefore, the leakage current between the source region and the drain region can be reduced. Thereafter, the resist mask 66 is removed.

[0095] In particular, when exposed to plasma used in dry etching, the resist mask changes in quality and becomes The buffer layer is then removed by 50 nm to prevent residues from being left behind during the stripping process. The resist mask 66 is removed by etching a portion of the conductive films 65a to 65c. and an etching process for forming the source and drain regions 72. In either case, dry etching is likely to leave residues, so it is necessary to completely remove the residues. It is effective to form a thick buffer layer that can be etched when the buffer layer is removed. In addition, the buffer layer 73 is formed so that plasma damage to the LPSAS film during dry etching is prevented. It is also possible to prevent the same from being given to 61.

[0096] Next, as shown in FIG. 3B, the source and drain electrodes 71a to 71c, the source region The source and drain regions 72, the buffer layer 73, the LPSAS film 61, and the gate insulating film 52c The insulating film 76 is formed to cover the gate insulating films 52a, 52b, and 52c. The insulating film 76 can be formed by the same film formation method. The purpose of this is to prevent the intrusion of contaminating impurities such as metal objects and water vapor, and a dense membrane is preferable. In addition, by using a silicon nitride film for the insulating film 76, the oxygen concentration in the buffer layer 73 can be reduced by 5× 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 The following It is possible.

[0097] As shown in FIG. 3B, the ends of the source and drain electrodes 71a to 71c and the source The ends of the source electrode and the drain electrode 72 are not aligned but are offset. Since the ends of the drain electrodes 71a to 71c are spaced apart, It is possible to prevent leakage current and short circuits. The ends of the regions a to 71c are not aligned with the ends of the source and drain regions 72 but are shifted from each other. In order to achieve this, the source and drain electrodes 71a to 71c and the source and drain regions 7 The electric field is not concentrated at the ends of the gate electrode 51 and the source and drain electrodes 71a to 72. This prevents leakage current between the transistor 1c and the transistor 1b. This makes the transistor highly reliable and has a high withstand voltage. In addition, channel doping is performed, and It is possible to fabricate a thin film transistor with a controlled threshold value.

[0098] Through the above steps, a channel-etch type thin film transistor 74 can be formed. .

[0099] The thin film transistor shown in this embodiment has a gate insulating film, an LPSAS film, A buffer layer, a source region, a drain region, a source electrode, and a drain electrode are laminated. The surface of the LPSAS film, which functions as a channel formation region, is covered with a buffer layer. A recess (trench) is formed in a part of the layer, and the area other than the recess is a source region and a drain region. That is, the source and drain regions are covered by the recesses formed in the buffer layer. The distance between the regions reduces leakage current between the source and drain regions. In addition, a recess can be formed by etching a part of the buffer layer. In order to remove the etching residues generated in the process of forming the source and drain regions, Therefore, leakage current (parasitic channel) can flow through the residue to the source and drain regions. This can prevent the occurrence of the problem of

[0100] In addition, the LPSAS film, which functions as the channel forming region, and the source and drain regions are A buffer layer is formed between the LPSAS film and the substrate. The surface of the LPSAS film is covered with a buffer layer. A high resistance buffer layer is disposed between the LPSAS film and the source and drain regions. Since the insulating layer 14 extends in the direction perpendicular to the substrate 1, it is possible to reduce the occurrence of leakage current in the thin film transistor. In addition, the deterioration caused by the application of a high voltage can be reduced. The LPSAS film, source region, and drain region are all formed on the area overlapping the gate electrode. Therefore, it can be said that the structure is not affected by the edge shape of the gate electrode. In this structure, if aluminum is used as the lower layer, aluminum is attached to the side of the gate electrode. The source and drain regions are exposed and may form hillocks, but the gate By configuring it so that it does not overlap with the electrode edge, a short circuit does not occur in the area where it overlaps with the side of the gate electrode. In addition, the surface of the LPSAS film is terminated with hydrogen, which prevents the formation of non-surface-contacting electrodes. Since the amorphous semiconductor film is formed as a buffer layer, oxidation of the LPSAS film can be prevented. In addition, the etching residue generated in the process of forming the source and drain regions can be eliminated. This prevents the infiltration of residues into the LPSAS membrane. This results in excellent electrical properties and durability. It is possible to form a thin film transistor having excellent voltage characteristics.

[0101] In addition, the channel length of the thin film transistor can be shortened, and the area of ​​the thin film transistor can be reduced. can be reduced.

[0102] Next, a resist mask is formed on the insulating film 76 using a fourth photomask. A contact hole is formed by etching a part of 76, and A pixel electrode 77 is formed in contact with the source electrode or drain electrode 71c. ) corresponds to a cross-sectional view taken along the dashed line AB in FIG.

[0103] As shown in FIG. 4, the ends of the source and drain regions 72 are connected to the source and drain electrodes. It can be seen that the end of the buffer layer 73 is located outside the end of the electrode 71c. The source and drain electrodes 71c and the source and drain regions 72 are located outside the ends of the source and drain regions 72. In addition, one of the source electrode and the drain electrode surrounds the other of the source electrode and the drain electrode. The shape of the area where the carriers move is called the "U-shape" or "C-shape". It is possible to increase the product, which allows for a larger current flow, and thin-film transistors The area of ​​the gate electrode can be reduced. Since the source electrode and drain electrode are overlapped, the effect of unevenness of the gate electrode is small, and the coating The rate of leakage current can be reduced and the occurrence of leakage current can be suppressed. One of the n electrodes also functions as a source wiring or a drain wiring.

[0104] The pixel electrode 77 is made of indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, indium oxide with silicon oxide added A light-transmitting conductive material such as indium tin oxide can be used.

[0105] The pixel electrode 77 is made of a conductive composition containing a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by using a sheet resistor. It is preferable that the resistance is 10,000Ω / □ or less and the light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that

[0106] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0107] Here, the pixel electrode 77 is formed by forming an indium tin oxide film by a sputtering method. After that, a resist is applied onto the indium tin oxide film. Next, a fifth photomask is used. The resist is exposed and developed using the resist mask to form a resist mask. The indium tin oxide film is then etched to form the pixel electrode 77.

[0108] In this manner, an element substrate that can be used in a display device can be formed.

[0109] (Embodiment 2) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used for the same parts in FIG. 5 as in FIG. 1, and the same steps are Detailed explanation will be omitted.

[0110] First, the state shown in FIG. 5(A) is obtained in the same manner as in the first embodiment. FIG. 5(A) is the same as FIG. 1(A). After forming a gate electrode 51 on a substrate 50, a gate The insulating films 52a, 52b, and 52c and the microcrystalline semiconductor film 23a are formed in this order.

[0111] As shown in FIG. 5B, the microcrystalline semiconductor film is subjected to a first LP treatment, and then the LPSA The S film 33a is formed. The LP process is performed in advance to improve the crystallinity of the microcrystalline semiconductor film. If so, it is possible to prevent the semiconductor film from becoming completely amorphous by ion implantation.

[0112] Next, as shown in FIG. 5(C), boron is implanted into the LPSAS film 33a by ion implantation. By ion implantation, the amount of boron is increased compared to the LPSAS film 33a. The crystallinity of the microcrystalline semiconductor film 33b containing the ions is reduced. If an oxide film is formed on the surface of the LPSAS film 33a due to irradiation with ions, the oxide film is not implanted. It is preferable to perform a thermal ion implantation treatment and remove the oxide film after the ion implantation. This oxide film functions as a surface protection film. It is possible.

[0113] Next, the second LP process is performed as shown in FIG. The crystallinity is improved and the boron in the film is activated. The second LP treatment does not have to be performed under the same conditions. 3b It is preferable to clean the surface.

[0114] Alternatively, a heat treatment may be carried out instead of the second LP treatment. If the temperature is lower than the temperature that melts the conductive film and higher than the temperature that activates the boron in the film, Good.

[0115] Next, as shown in FIG. 5(E), a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 is formed by adding an impurity to the semiconductor film 55. FIG. 5(E) is the same as FIG. 1(D). In addition, the oxide film formed during the second LP process is removed before forming the buffer layer 54. It is preferable to remove

[0116] Although the number of steps is increased compared to the first embodiment, the crystallinity is improved more than that of the first embodiment. Thus, a LPSAS membrane can be obtained.

[0117] The subsequent steps are the same as those in the first embodiment, and therefore will not be repeated here.

[0118] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0119] (Embodiment 3) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used for the same parts in FIG. 6 as in FIG. 1, and the same steps are Detailed explanation will be omitted.

[0120] In this embodiment, an impurity element for imparting p-type is added at the same time as the film is formed. A process of performing LP treatment after forming a microcrystalline semiconductor film containing a trace amount of a pure element will be described.

[0121] First, a gate electrode 51 is formed on a substrate 50 in the same manner as in the first embodiment. Gate insulating films 52a, 52b, and 52c are formed on the electrode 51. Then, as shown in FIG. As shown in the figure, the microcrystalline semiconductor film 4 is intentionally doped with an impurity element for the purpose of controlling the threshold voltage. 3 is deposited.

[0122] The typical impurity element that gives the p-type conductivity is boron, and impurities such as B2H6 and BF3 are also used. The pure gas is added with silicon hydride at a ratio of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. The boron concentration in the microcrystalline semiconductor film 43 (measured by SIMS) is preferably mixed in the Concentration), for example, 1 × 10 14 ~6×10 16 atoms / cm 3 It would be better to say:

[0123] Next, in order to improve the crystallinity of the microcrystalline semiconductor film 43 immediately after deposition, The laser beam is irradiated from the front side. The energy of the laser beam melts the microcrystalline semiconductor film. The laser beam is irradiated with energy that does not cause the material to become irradiated. It is possible to form an LPSAS film 53 with improved crystallinity.

[0124] When a microcrystalline semiconductor film is formed by adding a small amount of boron during film formation, and LP processing is performed after film formation. In the case of LP treatment, since it is not necessary to activate boron, the crystallinity is not improved. The laser beam irradiation conditions may be set to be such that the laser beam can be irradiated at a desired temperature.

[0125] In this experiment, a small amount of boron is added during film formation to form a microcrystalline semiconductor film, and LP processing is performed after film formation. According to this embodiment, the number of steps is reduced, so that this process is suitable for mass production.

[0126] In addition, when using an ion implantation device or ion doping device, depending on the doping conditions, However, the addition of ions can damage the microcrystalline semiconductor film and can even damage the gate insulating film. A small amount of boron is added during film formation to form a microcrystalline semiconductor film. If the device is fabricated using a GaN-based GaN- ... can.

[0127] Next, as shown in FIG. 6C, a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 is formed by adding the impurity. FIG. 6(C) is the same as FIG. 1(D). In addition, the oxide film formed during the LP process is removed before forming the buffer layer 54. It is preferred.

[0128] The subsequent steps are the same as those in the first embodiment, and therefore will not be repeated here.

[0129] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0130] (Embodiment 4) In this embodiment, the steps that are partially different from those in the first embodiment will be described below. Since only the parts are different, the same reference numerals are used for the same parts in FIG. 7 as in FIG. 1, and the same steps are Detailed explanation will be omitted.

[0131] First, the state shown in FIG. 7(A) is obtained in the same manner as in the first embodiment. FIG. 7(A) is the same as FIG. 1(C). After forming a gate electrode 51 on a substrate 50, a gate Insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film are formed in this order. In order to achieve this, an impurity element that imparts one conductivity to a microcrystalline semiconductor film is intentionally implanted into the film by ion implantation. Next, in order to improve the crystallinity of the microcrystalline semiconductor film as soon as it is formed, The surface of the conductive film is irradiated with a laser beam. Form.

[0132] Next, as shown in FIG. 7(B), the surface of the LPSAS film 53 is irradiated with hydrogen plasma and nitrogen plasma. or halogen plasma. The LPSAS film 53 surface is irradiated with a laser beam. If an oxide film is formed on the substrate, it must be removed before forming the buffer layer. In this embodiment, the oxide film on the surface of the LPSAS film 53 is removed, and then the LPSAS film 5 3. Hydrogen plasma treatment is performed on the surface. The interface with the buffer layer to be formed later is clean. To achieve this, the surface is treated with hydrogen plasma, nitrogen plasma, or halogen plasma. LP can be improved by treating it with hydrogen plasma, nitrogen plasma, or halogen plasma. The surface of the SAS film 53 can be made to be one on which an oxide film is less likely to form.

[0133] By preventing the formation of an oxide film on the surface of the LPSAS film 53, the threshold voltage is increased. can be suppressed.

[0134] Next, as shown in FIG. 7C, a buffer layer 54 and a one-conductivity type are formed on the LPSAS film 53. A semiconductor film 55 containing the impurity to be added is formed. FIG. 7(C) is the same as FIG. 1(D). be.

[0135] The subsequent steps are the same as those in the first embodiment, and therefore will not be repeated here.

[0136] This embodiment mode can be freely combined with any one of the first to third embodiments. Cut.

[0137] (Embodiment 5) A manufacturing method of a thin film transistor different from that in Embodiment 1 will be described with reference to FIGS. Here, a process that can reduce the number of photomasks compared to the first embodiment will be described. The process for manufacturing a thin film transistor using this process will be described.

[0138] As in FIG. 1A shown in the first embodiment, a conductive film is formed on a substrate 50, and a laser is applied to the conductive film. A resist was applied to the substrate, and a resist was formed by a photolithography process using a first photomask. A part of the conductive film is etched using a resist mask to form a gate electrode 51. On the gate electrode 51, gate insulating films 52a, 52b, and 52c and a microcrystalline semiconductor film 23a are formed. Form in order.

[0139] Next, as in FIG. 1B shown in the first embodiment, a small amount of boron is added for the purpose of threshold control. A microcrystalline semiconductor film 23b is formed by ion implantation.

[0140] Next, in the same manner as in FIG. 1C shown in the first embodiment, a laser beam is irradiated to form an LPSAS Next, in the same manner as in FIG. 1(D) shown in the first embodiment, the LPSAS film 53 is formed. A buffer layer 54 and a semiconductor film 55 doped with an impurity that imparts one conductivity type are formed in this order on the substrate. do.

[0141] Next, conductive films 65a to 65c are formed on the semiconductor film 55 to which an impurity imparting one conductivity type is added. 9(A), a resist 80 is applied onto the conductive film 65a.

[0142] The resist 80 may be a positive resist or a negative resist. , shown using a positive resist.

[0143] Next, the resist 80 is irradiated with light using the multi-tone mask 59 as a second photomask. Then, the resist 80 is exposed.

[0144] Here, the exposure using the multi-tone mask 59 will be described with reference to FIG.

[0145] A multi-tone mask is a mask that performs three exposure levels for the exposed, intermediate, and unexposed areas. It is a mask that can be used for multiple (typically two types) It is possible to form a resist mask having a region with a thickness of 100 nm. By using a mask, it is possible to reduce the number of photomasks.

[0146] Representative examples of multi-tone masks include a gray-tone mask 59a as shown in FIG. 8(C) is a half-tone mask 59b.

[0147] As shown in FIG. 8A, the gray-tone mask 59a includes a light-transmitting substrate 163 and The light shielding portion 164 and the diffraction grating 165 are formed thereon. On the other hand, the diffraction grating 165 has slits, dots, meshes, etc. By making the intervals between the light transmitting portions equal to or less than the resolution limit of the light used for exposure, The transmittance can be controlled. The diffraction grating 165 is a multi-layered structure that includes periodic slits, dots, Either meshes or non-periodic slits, dots, or meshes can be used.

[0148] The light-transmitting substrate 163 may be a light-transmitting substrate such as quartz. The portion 164 and the diffraction grating 165 are made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed.

[0149] When the gray-tone mask 59a is irradiated with exposure light, the light-shielding portion 1 In the case of 64, the light transmittance 166 is 0%, and the light shielding portion 164 and the diffraction grating 165 are provided. In the unmodified area, the light transmittance 166 is 100%. The light transmittance of the diffraction grating 165 can be adjusted in the range of 10 to 70%. This is possible by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. do.

[0150] As shown in FIG. 8C, the half-tone mask 59b includes a light-transmitting substrate 163 and The semi-transmitting portion 167 and the light-shielding portion 168 are formed thereon. , MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light shielding portion 168 is formed using a light shielding material that absorbs light, such as chromium or chromium oxide. This can be done.

[0151] When the halftone mask 59b is irradiated with exposure light, the light-shielding portion 1 In the case of 68, the light transmittance 169 is 0%, and the light shielding portion 168 and the semi-transmitting portion 167 are provided. In the non-transparent region, the light transmittance 169 is 100%. The light transmittance of the semi-transmissive portion 167 can be adjusted in the range of 10 to 70%. This can be adjusted by adjusting the material of the semi-transmissive portion 167.

[0152] By exposing the film using a multi-tone mask and then developing it, the film thickness can be varied as shown in FIG. 9(B). A resist mask 81 having a region can be formed.

[0153] Next, the LPSAS film 53, the buffer layer 54, and the one-conductivity type are formed by using a resist mask 81. The semiconductor film 55 to which the impurity is added and the conductive films 65a to 65c are etched and separated. As a result, a LPSAS film 61, a buffer layer 62, and a single conductive layer are formed as shown in FIG. By forming the semiconductor film 63 to which an impurity for imparting a type is added and the conductive films 85a to 85c, FIG. 10(A) corresponds to a cross-sectional view taken along line AB in FIG. 12(A) (however, (excluding resist mask 86).

[0154] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness At this time, the resist in the thin region (which overlaps a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. 10(A). It is possible.

[0155] Next, the conductive films 85a to 85c are etched and separated using the resist mask 86. As a result, a pair of source and drain electrodes 92a to 92c are formed as shown in FIG. 10(B). The conductive films 85a to 85c are formed by wet etching using the resist mask 86. When etching is performed, the conductive films 85a to 85c are selectively etched. In order to etch the film isotropically, the source electrode and Drain electrodes 92a to 92c can be formed.

[0156] Next, a semiconductor film doped with an impurity that imparts one conductivity type is formed using a resist mask 86. 63 is etched to form a pair of source and drain regions 88. In the etching process, a part of the buffer layer 62 is also etched. The buffer layer thus formed is referred to as a buffer layer 87. A recess is formed in the buffer layer 87. The source and drain regions are formed in the same process as the recess (groove) of the buffer layer. In this case, a portion of the buffer layer 87 is smaller than the resist mask 81. The source and drain regions are partially etched away by the resist mask 86, which has a reduced area. The buffer layer 87 is formed to protrude outside the region 88. After that, the resist mask 86 is removed. In addition, the ends of the source and drain electrodes 92a to 92c and the source region and The ends of the drain region 88 are not aligned but are offset, and the source and drain electrodes 92a to 9 Outside the ends of 2c, the ends of source and drain regions 88 are formed.

[0157] FIG. 10C corresponds to a cross-sectional view taken along the line AB in FIG. 12B. Thus, the ends of the source and drain regions 88 are connected to the source and drain electrodes 92c. It can be seen that the end of the buffer layer 87 is located outside the end of the source electrode and the drain electrode. The drain electrode 92c is located outside the ends of the source and drain regions 88. One of the source electrode and the drain electrode is shaped to surround the other of the source region and the drain region. Specifically, it is U-shaped or C-shaped. This increases the area of ​​the region through which carriers move. This allows the amount of current to be increased, and the area of ​​the thin film transistor In addition, the microcrystalline semiconductor film, the source electrode, and the Since the gate electrode and drain electrode are overlapped, the effect of the unevenness of the gate electrode is small, and the coverage rate is reduced. The occurrence of leakage current can be suppressed. One of them also functions as a source wiring or a drain wiring.

[0158] As shown in FIG. 10C, the ends of the source and drain electrodes 92a to 92c and the The ends of the source region and the drain region 88 are not aligned but are offset from each other, so that the source electrode and Since the ends of the drain electrodes 92a to 92c are spaced apart, In addition, the source electrode and the drain electrode 9 can be prevented from leaking current or shorting. The ends of the electrodes 2a to 92c and the ends of the source and drain regions 88 are not aligned but are shifted. Therefore, the source and drain electrodes 92a to 92c and the source and drain regions The electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 92a to This prevents leakage current between the MOSFET 92c and the MOSFET 92c. It is possible to fabricate high-voltage thin film transistors.

[0159] Through the above steps, a channel-etch type thin film transistor 83 can be formed. Moreover, a thin film transistor can be formed using two photomasks.

[0160] Next, as shown in FIG. 11(A), the source and drain electrodes 92a to 92c, region and drain region 88, buffer layer 87, LPSAS film 90, and gate insulating film 52 An insulating film 76 is formed on the gate insulating films 52a, 52b, and 52c. The same manufacturing method can be used to form the insulating film.

[0161] Next, a part of the insulating film 76 is removed using a resist mask formed using a third photomask. Then, a contact hole is formed by etching. A pixel electrode 77 is formed in contact with the source electrode or drain electrode 92c. As for 77, an indium tin oxide film is formed by sputtering, and then indium A resist is applied onto the tin oxide film. Next, the resist is exposed using a fourth photomask. Then, the resist mask is used to form an indium tin oxide film. The oxide film is etched to form pixel electrodes 77. Note that FIG. 11(B) is similar to FIG. 12(C). This corresponds to the cross-sectional view taken along line AB in FIG.

[0162] As a result, the number of masks can be reduced by using a multi-tone mask, and a device that can be used in a display device can be obtained. A daughter board can be formed.

[0163] This embodiment mode can be freely combined with any one of the first to fourth embodiment modes. Cut.

[0164] (Embodiment 6) In this embodiment mode, the thin film transistor described in Embodiment 1 is used as one mode of a display device. A liquid crystal display device having the above structure will be described below.

[0165] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. A VA type LCD is a type of display that controls the alignment of liquid crystal molecules in the LCD panel. In VA type LCD devices, the liquid crystal molecules are aligned relative to the panel surface when no voltage is applied. In this embodiment, the pixels are divided into several regions. (sub-pixels), and each sub-pixel is designed to tilt the molecules in a different direction. In the following explanation, we will refer to multi-domain design. A liquid crystal display device that takes this into consideration will be described.

[0166] 14 and 15 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate on which the element electrodes are formed, showing a cross-sectional structure corresponding to the cutting line AB shown in the figure. FIG. 13 shows this. FIG. 15 shows a plan view of the substrate on which the counter electrode is formed. The following description will make reference to these figures.

[0167] FIG. 13 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode 640 and the like are formed is overlapped with the counter substrate 601. 4, showing the state after liquid crystal is injected.

[0168] In the position where the spacer 642 is to be formed on the opposing substrate 601, a light-shielding film 632 and a first adhesive A color film 634, a second color film 636, a third color film 638, and a counter electrode 640 are formed. This structure allows the heights of the protrusions 644 and spacers 642 for controlling the alignment of the liquid crystal to be different. An alignment film 648 is formed on the pixel electrode 624, and an alignment film 648 is formed on the counter electrode 640. An alignment film 646 is also formed on the first and second electrodes 642 and 644. A liquid crystal layer 650 is formed between these electrodes 642 and 644.

[0169] Although the spacers 642 are shown as columnar spacers here, bead spacers may be dispersed. Furthermore, a spacer 642 is formed on the pixel electrode 624 formed on the substrate 600. Good too.

[0170] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. 0 is formed. The pixel electrode 624 covers the TFT 628, the wiring, and the storage capacitor 630. A contact hole 62 penetrates an insulating film 620 and a third insulating film 622 that covers the insulating film. The TFT 628 is connected to the wiring 618 by a line 3. The storage capacitor 630 is connected to the gate wiring 602 of the TFT 628. Similarly, a first capacitance wiring 604, a gate insulating film 606, and wirings 616 and 618 are formed. It is composed of a second capacitance wiring 617 formed in a similar manner.

[0171] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0172] FIG. 14 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the first embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by controlling the alignment of the liquid crystal. This is to control the

[0173] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. A pixel is composed of a pixel electrode 624 and a pixel electrode 626. 624 and the pixel electrode 626 are a sub-pixel.

[0174] 15 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. A protrusion 644 for controlling the alignment of the liquid crystal is formed on the counter electrode 640. A spacer 642 is formed in accordance with the position of 32.

[0175] The equivalent circuit of this pixel structure is shown in Figure 16. TFT628 and TFT629 are both gate The wiring 602 and the wiring 616 are connected. In this case, the capacitance wiring 604 and the capacitance wiring 605 By making the potentials different, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 can be individually controlled. The viewing angle is expanded by precisely controlling the crystal orientation.

[0176] When a voltage is applied to the pixel electrode 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by making it multi-domain.

[0177] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 17 to 20. do.

[0178] 17 and 18 show the pixel structure of a VA type liquid crystal panel. FIG. 17 is a plan view showing a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The explanation will be given with reference to these two figures.

[0179] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode has a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel having a multi-domain design, the signal applied to each pixel electrode is independently The system has a configuration in which the control is performed independently.

[0180] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode 626 is connected to the wiring 619 through the contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are connected to each other. The line 603 is separated so that a different gate signal can be applied. The wiring 616 functioning as a data line is used in common by the TFT 628 and the TFT 629. The thin film transistors shown in the embodiment mode 1 are appropriately used for the TFT 628 and the TFT 629. This can be done.

[0181] The pixel electrodes 624 and 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outer side of the pixel electrode 624 that spreads in a V shape. The timing of applying voltages to the pixel electrodes 624 and 626 is controlled by the TFT 62. The alignment of the liquid crystal is controlled by changing the polarity of the TFT 629 and the pixel structure. The equivalent circuit is shown in FIG. 20. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is The gate wiring 602 and the gate wiring 603 are connected to different gates. By applying a signal, the operation timing of TFT628 and TFT629 can be made different. can.

[0182] On the opposing substrate 601, a light-shielding film 632, a second colored film 636, and an opposing electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. FIG. 19 shows the structure of the opposing substrate side. The opposing electrode 640 is This electrode is shared between the pixels, and has a slit 641 formed therein. The slits 641 and the slits 625 on the pixel electrode 624 and pixel electrode 626 sides are alternately interlocked. By arranging the electrodes in a way that matches the orientation of the liquid crystal, a diagonal electric field can be effectively generated and the orientation of the liquid crystal can be controlled. This allows the liquid crystal to be oriented in different directions depending on the location, resulting in a wider viewing angle. is spreading.

[0183] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure in which a child is provided.

[0184] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0185] FIG. 21 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. Since it is on the plate 600 side, it is not provided on the opposing substrate 601 side. A liquid crystal layer 650 is formed between the electrodes 601 .

[0186] On the substrate 600, a first pixel electrode 607 and a capacitance wiring connected to the first pixel electrode 607 are provided. 604, and the TFT 628 shown in the first embodiment are formed. The pixel electrode 7 can be made of the same material as that of the pixel electrode 77 shown in the first embodiment. The pixel electrode 607 is formed in a shape partitioned into a shape roughly corresponding to a pixel. A gate insulating film 606 is formed on the gate insulating film 607 and the capacitance wiring 604 .

[0187] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. Reference numeral 8 denotes the other electrode of the source and drain, which is a wiring connected to the second pixel electrode 624. do.

[0188] A second insulating film 620 is formed on the wiring 616 and the wiring 618. In the contact hole formed in the insulating film 620, a second The pixel electrode 624 is the same as the pixel electrode 77 shown in the first embodiment. It is formed using the same material.

[0189] In this manner, a TFT 628 and a first pixel electrode 624 connected thereto are formed on the substrate 600. A storage capacitor is formed between the first pixel electrode 607 and the second pixel electrode 624. It has been completed.

[0190] 22 is a plan view showing the configuration of a pixel electrode. The pixel electrode 624 has a slit 625. The slits 625 are for controlling the alignment of the liquid crystal. In this case, the electric field occurs between the first pixel electrode 607 and the second pixel electrode 624. A gate insulating film 606 is formed between the first pixel electrode 624 and the second pixel electrode 624. The thickness of 606 is 50 to 200 nm, which is sufficiently large compared with the thickness of the liquid crystal layer, which is 2 to 10 μm. Since the liquid crystal layer 600 is thin, an electric field is generated in a direction parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled by using an electric field parallel to the substrate to rotate the liquid crystal molecules horizontally. In this case, the liquid crystal molecules are horizontal in all states, so the contrast changes depending on the viewing angle. The influence of the first pixel electrode 607 and the second pixel electrode 608 is small, and the viewing angle is widened. Since both of the pixel electrodes 624 are light-transmitting electrodes, the aperture ratio can be improved.

[0191] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0192] 23 and 24 show the pixel structure of an IPS type liquid crystal display device. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0193] FIG. 23 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A light-emitting film 632, a second coloring film 636, a flattening film 637, etc. are formed. Since it is on the plate 600 side, it is not provided on the opposing substrate 601 side. A liquid crystal layer 650 is formed between the electrodes 601 .

[0194] On the substrate 600, a common potential line 609 and the TFT 628 shown in the first embodiment are formed. The common potential line 609 is formed at the same time as the gate wiring 602 of the thin film transistor 628. Moreover, the pixel electrode 624 is formed in a shape that is partitioned into approximately the shape of a pixel.

[0195] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is the data line that carries the video signal in the LCD panel and is a wiring that extends in one direction. At the same time, it is connected to the source region 610 and serves as one of the source and drain electrodes. Reference numeral 8 denotes a wiring which becomes the other of the source and drain electrodes and is connected to the pixel electrode 624 .

[0196] A second insulating film 620 is formed on the wiring 616 and the wiring 618. In the contact hole 623 formed in the insulating film 620, The pixel electrode 624 is the same as the pixel electrode 77 shown in the first embodiment. As shown in FIG. 24, the pixel electrode 624 is connected to a common potential The wire 609 is formed so that a lateral electric field is generated together with the comb-shaped electrode formed at the same time. The comb-tooth portion of the electrode 624 is alternately interdigitated with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed as follows.

[0197] When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0198] In this manner, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitance electrode 615 and the pixel electrode 624 are formed through a contact hole 633. are connected via

[0199] Next, a configuration of a TN type liquid crystal display device will be described.

[0200] Figures 25 and 26 show the pixel structure of a TN type liquid crystal display device. Figure 26 is a plan view. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0201] The pixel electrode 624 is connected to the TFT 628 through a contact hole 623 and a wiring 618. The wiring 616 functioning as a data line is connected to the TFT 628. Any of the TFTs shown in the first embodiment can be applied to 28 .

[0202] The pixel electrode 624 is formed using the pixel electrode 77 shown in the first embodiment.

[0203] On the opposing substrate 601, a light-shielding film 632, a second colored film 636, and an opposing electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. The liquid crystal layer 650 is disposed between the pixel electrode 624 and the counter electrode 640. has been formed.

[0204] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0205] In addition, the substrate 600 or the opposing substrate 601 may have a color filter or a disclination. A shielding film (black matrix) for preventing the above may be formed on the substrate 60. A polarizing plate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed, and a counter substrate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed. A polarizing plate is attached to the surface of the plate 601 opposite to the surface on which the counter electrode 640 is formed. .

[0206] The counter electrode 640 may be made of the same material as the pixel electrode 77. 24, liquid crystal 650, and counter electrode 640 are overlapped to form a liquid crystal element.

[0207] Through the above steps, a liquid crystal display device can be manufactured. The off-state current is small, and the thin film transistor with excellent electrical characteristics and high reliability is used. Therefore, the liquid crystal display device has high contrast and high visibility. The thin film transistor has a threshold voltage controlled by using a microcrystalline semiconductor film containing a small amount of silicon. Therefore, a liquid crystal display device with high visibility can be manufactured with good productivity.

[0208] (Embodiment 7) In this embodiment mode, a light-emitting device, which is one mode of a display device, will be described with reference to FIGS. 28. The light emitting device is an electroluminescent The light-emitting element that uses electroluminescence is shown below. Optical materials are classified according to whether they are organic or inorganic compounds. Generally, the former are The former are called organic EL elements, the latter inorganic EL elements.

[0209] In an organic EL element, electrons and positive electrodes are released from a pair of electrodes by applying a voltage to the light-emitting element. The holes are then injected into a layer containing a light-emitting organic compound, and a current is passed through them. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0210] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. In addition, a channel-etched thin film transistor is used as a thin film transistor for controlling the driving of the light-emitting element. Illustrated using transistors.

[0211] Through the steps shown in FIGS. 9 to 11, a thin film transistor is formed on a substrate 50 as shown in FIG. 85 and 86 are formed, and an insulating film 87 which functions as a protective film is formed on the thin film transistors 85 and 86. Next, a planarizing film 111 is formed on the insulating film 87, and a thin film transistor is formed on the planarizing film 111. A pixel electrode 112 is formed to connect to the source electrode or the drain electrode of the transistor 86 .

[0212] The planarization film 111 is made of an organic resin such as acrylic, polyimide, or polyamide, or a silicone resin. It is preferable to form the film using a son.

[0213] In FIG. 27A, the thin film transistor of the pixel is an n-type, so the pixel electrode 112 is It is preferable to use a cathode, but in the case of a p-type, it is preferable to use an anode. The cathode is made of a known material having a small work function, such as calcium, aluminum, or fluorine. Calcium fluoride, magnesium silver alloy, lithium aluminum alloy, etc. can be used. do.

[0214] Next, as shown in FIG. 27(B), a partition wall is formed on the end portion of the flattening film 111 and the pixel electrode 112. The partition wall 113 has an opening, and the pixel electrode 112 is formed in the opening. The partition wall 113 is made of an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the pixel electrode, and the side of the opening is It is preferable that the wall is formed to have an inclined surface having a continuous curvature.

[0215] Next, the light-emitting layer 114 is formed so as to contact the pixel electrode 112 in the opening of the partition wall 113. The light-emitting layer 114 may be composed of a single layer or may be composed of a plurality of layers stacked together. It doesn't matter whether it is done or not.

[0216] Then, a common electrode 115 using an anode is formed so as to cover the light-emitting layer 114. The pixel electrode 115 is made of the conductive material having light transmission properties as listed in the first embodiment. The common electrode 115 can be formed of a transparent conductive film. Alternatively, a titanium nitride film or a titanium film may be used. Indium tin oxide is used for the partition wall 113. The light emitting layer 114 and the common electrode 115 are overlapped to form a light emitting element 117. After that, in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 117, It is preferable to form a protective film 116 on the barrier 115 and the partition wall 113. It is possible to form a silicon nitride film, a silicon oxynitride film, a DLC film, or the like.

[0217] Furthermore, in practice, once the construction is completed up to Fig. 27(B), it is necessary to make it airtight to prevent it from being exposed to the outside air. Highly durable and low outgassing protective film (laminate film, UV curable resin film) It is preferable to package (enclose) the product in a container or cover material.

[0218] Next, the configuration of the light-emitting element will be described with reference to FIG. 28. Here, the driving TFT is The cross-sectional structure of a pixel will be described below taking the n-type as an example.

[0219] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top surface emission takes the light out from the surface on the substrate side, the bottom surface emission takes the light out from the surface on the substrate side, There are light emitting devices with a dual-side emission structure in which light is emitted from the opposite surface. The present invention can also be applied to a light emitting device having a light emitting structure.

[0220] A light emitting element having a top emission structure will be described with reference to FIG.

[0221] In FIG. 28A, a driving TFT 7001 is an n-type TFT, and light emitted from a light emitting element 7002 is FIG. 28(A) shows a cross-sectional view of a pixel in which the light-emitting element 7 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. A light-emitting layer 7004 and an anode 7005 are laminated on top of each other in this order. Any known material can be used as long as it is a conductive film that is thin and reflects light. For example, Calcium, aluminum, calcium fluoride, magnesium silver alloy, lithium aluminum The light-emitting layer 7004 may be made of a single layer or a plurality of layers. It may be configured so that the layers are laminated. When it is configured with multiple layers, On the cathode 7003, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. It is not necessary to provide all of these layers. The anode 7005 is a light-transmitting The insulating layer is formed of a conductive material having a high insulating property, for example, indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, acid A light-transmitting conductive film such as indium tin oxide to which silicon dioxide is added may be used. stomach.

[0222] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 28(A), the light emitted from the light emitting element 7002 corresponds to The light is emitted toward the anode 7005 as indicated by the white arrow.

[0223] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 7011 is an n-type, and light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side FIG. 28B shows a cross-sectional view of the pixel. A cathode 7013 of a light-emitting element 7012 is formed on the light-transmitting conductive material 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 7015 is transparent, a light reflecting or blocking layer is provided to cover the anode. The cathode 7013 may be formed in the same manner as in FIG. In addition, any known material can be used as long as it is a conductive film with a small work function. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, A cathode 7013 can be made of Al having a thickness of 100 nm. As in FIG. 28(A), even if it is composed of a single layer, it is composed of multiple layers stacked. The anode 7015 does not need to transmit light, but as shown in FIG. The shielding film 7 can be formed of a conductive material having light-transmitting properties, similarly to the shielding film 7. For example, a light-reflecting metal or the like can be used for 016, but the material is not limited to a metal film. For example, a resin to which a black pigment has been added may be used.

[0224] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 701. In the case of the pixel shown in FIG. 28B, the light emitted from the light-emitting element 7012 is , and is emitted toward the cathode 7013 as indicated by the white arrow.

[0225] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In the example shown in FIG. 1, a conductive material 7027 having a light-transmitting property is electrically connected to a driving TFT 7021. A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 24 and an anode 7025 are laminated in this order. The cathode 7023 is the same as in FIG. In addition, any known material can be used as long as it is a conductive film with a small work function. For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 7 may be formed of a single layer or a plurality of layers may be laminated. 025 is formed using a conductive material having light transmitting properties, similar to FIG. It is possible.

[0226] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 7 In the case of the pixel shown in FIG. 28C, the light emitted from the light-emitting element 7022 Light is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the white arrows.

[0227] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0228] In this embodiment, a thin film transistor (driving TFT) for controlling the driving of a light-emitting element is In the above example, the driving TFT and the light-emitting element are electrically connected. A current-controlling TFT may be connected.

[0229] Note that the light-emitting device shown in this embodiment is not limited to the structure shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0230] Through the above steps, a light emitting device can be manufactured. The use of thin-film transistors, which have low current, excellent electrical properties, and high reliability, This is a light-emitting device with high reliability and high visibility. Since a thin film transistor with a threshold voltage controlled by using a microcrystalline semiconductor film is used, Thus, a highly efficient light-emitting device can be manufactured with high productivity.

[0231] (Embodiment 8) A structure of a display panel, which is one mode of a display device of the present invention, will be described below.

[0232] In FIG. 29A, only a signal line driver circuit 6013 is formed separately and is formed on a substrate 6011. The pixel portion 6012 and the scan line 6013 are connected to the display panel. The driver circuit 6014 is formed using a thin film transistor using a microcrystalline semiconductor film. A transistor that has a higher mobility than a thin-film transistor that uses a crystalline semiconductor film. By forming a driving circuit, it is possible to realize a signal line driving circuit, which requires a higher driving frequency than the scanning line driving circuit. The signal line driver circuit 6013 is made of a single crystal semiconductor. A transistor using a conductor, a thin-film transistor using a polycrystalline semiconductor, or a SOI The pixel portion 6012, the signal line driver circuit 6013, and the driving circuit 6014 may be a transistor using the same. The power supply potential and various signals are respectively supplied to the scanning line driving circuit 6014 via the FPC 6015. are supplied.

[0233] In addition, both the signal line driver circuit and the scanning line driver circuit may be formed on the same substrate as the pixel portion. stomach.

[0234] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the substrate on which the pixel portion is formed. It is not necessary to attach it to a substrate on which a film is formed. For example, it can be attached to an FPC. In FIG. 29B, only a signal line driver circuit 6023 is formed separately, and A liquid crystal display panel connected to the formed pixel portion 6022 and the scanning line driver circuit 6024 The pixel portion 6022 and the scanning line driver circuit 6024 are formed using a microcrystalline semiconductor film. The signal line driver circuit 6023 is formed using a thin film transistor. The pixel portion 6022 is connected to a signal line driver circuit 6023. The scanning line driver circuit 6024 is connected to the power supply potential and various signals via the FPC 6025. and supplied.

[0235] In addition, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed using a microcrystalline semiconductor film. The thin film transistors that were used in the previous step were formed on the same substrate as the pixel section, and the remaining part was formed separately to form the pixel section. In FIG. 29C, an analog signal line driver circuit may be electrically connected to the The switch 6033a is disposed on the same substrate 6031 as the pixel portion 6032 and the scanning line driver circuit 6034. A shift register 6033b of the signal line driver circuit is formed on a different substrate. The pixel portion 6032 and the scanning line driver circuit are shown in FIG. The signal line driver circuit 6034 is formed using a thin film transistor using a microcrystalline semiconductor film. The shift register 6033b of the circuit is connected to the pixel section 6032 via the FPC 6035. A pixel portion 6032, a signal line driver circuit, and a scanning line driver circuit 6034 are provided. The power supply potential, various signals, etc. are supplied via FPC6035.

[0236] As shown in FIG. 29, the liquid crystal display device of the present invention has a driver circuit partially or entirely disposed in a pixel region. A thin film transistor using an LPSAS film can be formed on the same substrate as the .

[0237] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. The method for connecting may be a soldering method, a wire bonding method, or a TAB method. The position of the wiring is not limited to the position shown in FIG. 29, so long as electrical connection is possible. Alternatively, a controller, a CPU, a memory, etc. may be formed separately and connected.

[0238] The signal line driver circuit used in the present invention has only a shift register and an analog switch. In addition to shift registers and analog switches, buffers, level shifters, It may have other circuits such as a shift register and an analog It is not necessary to provide a shift switch. For example, a decoder circuit may be provided instead of a shift register. Alternatively, a separate circuit that can select a signal line such as A latch or the like may also be used.

[0239] FIG. 32 shows a block diagram of a liquid crystal display device according to the present invention. A pixel section 701 having a plurality of pixels each having a scanning line driver circuit 702 for selecting each pixel. and a signal line driver circuit 703 for controlling input of a video signal to a selected pixel.

[0240] In FIG. 32, a signal line driver circuit 703 includes a shift register 704 and an analog switch 705. The shift register 704 includes a clock signal (CLK), a start pulse The clock signal (CLK) and the start pulse signal (SP) are input. ) is input, a timing signal is generated in the shift register 704, and an analog This is input to switch 705 .

[0241] A video signal is also applied to the analog switch 705. The analog switch 705 outputs the video signal according to the input timing signal. The signal is then sampled and supplied to the signal line of the subsequent stage.

[0242] Next, the configuration of the scanning line driver circuit 702 will be described. A level shifter may be included in some cases. In the scanning line driver circuit 702, a clock signal is input to the shift register 706. The selection signal is generated by inputting the clock (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer 707 and applied to the corresponding scan line. The gates of the transistors of the pixels for one line are connected to the scan line. And because the transistors in the pixels of one line must all be turned on at once, The Fa 707 is capable of passing a large current.

[0243] A full-color LCD display device receives video signals corresponding to R (red), G (green), and B (blue). In the case where the signals are sampled in sequence and supplied to the corresponding signal lines, the shift register 704 and the The number of terminals for connecting the analog switch 705 to the pixel section 7 This is about 1 / 3 of the number of terminals required to connect the signal lines of 00. By forming the analog switch 705 on the same substrate as the pixel section 701, Compared with the case where the portion 701 is formed on a substrate different from the substrate, the terminals used for connecting the substrate formed separately are This reduces the number of connections, reduces the probability of connection failure, and increases the yield.

[0244] The scanning line driving circuit 702 in FIG. However, the scanning line driver circuit 702 may be configured with a shift register 706 .

[0245] Note that the configuration shown in FIG. 32 is merely one mode of the display device of the present invention, and is not limited to the signal line drive. The configuration of the circuit and the scanning line driver circuit is not limited to this.

[0246] Next, a shift register containing thin-film transistors using LPSAS films with the same polarity was An embodiment of the shift register of this embodiment will be described with reference to Figs. 33 and 34. The configuration of the register is shown in FIG. 33. The shift register shown in FIG. 33 is made up of multiple flip-flops 701. _i (any one of the flip-flops 701_1 to 701_n). , a first clock signal, a second clock signal, a start pulse signal, and a reset signal are input. It works as it is.

[0247] The connection relationship of the shift register in Fig. 33 will be described. The shift register in Fig. 33 has i-stage The first flip-flop 701_i (one of the flip-flops 701_1 to 701_n) In either one of them, the first wiring 501 shown in FIG. 34 is connected to the seventh wiring 717_i-1, The second wiring 502 shown in FIG. 34 is connected to the seventh wiring 717_i+1, The third wiring 503 is connected to the seventh wiring 717_i, and the sixth wiring 50 shown in FIG. 6 is connected to the fifth wiring 715.

[0248] In addition, the fourth wiring 504 shown in FIG. 34 is connected to the second wiring 7 in the odd-numbered flip-flops. 12, and in the even-numbered flip-flops, it is connected to the third wiring 713. The fifth wiring 505 shown in FIG.

[0249] However, the first wiring 501 shown in FIG. 34 of the first-stage flip-flop 701_1 is the first The second wiring 711 is connected to the n-th flip-flop 701_n shown in FIG. 502 is connected to the sixth wiring 716 .

[0250] The first wiring 711, the second wiring 712, the third wiring 713, and the sixth wiring 716 are They may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 714 and the fifth wiring 715 are respectively connected to the first power supply line and the second power supply line. You may call.

[0251] Next, the details of the flip-flop shown in FIG. 33 are shown in FIG. The flip-flop includes a first thin film transistor 171, a second thin film transistor 172, a third thin film transistor 173, and a The first thin film transistor 173, the fourth thin film transistor 174, and the fifth thin film transistor 1 75, a sixth thin film transistor 176, a seventh thin film transistor 177 and an eighth thin film transistor In this embodiment, the first thin film transistor 171 and the second thin film transistor 178 are The second thin film transistor 172, the third thin film transistor 173, and the fourth thin film transistor 174, the fifth thin film transistor 175, the sixth thin film transistor 176, the seventh thin film transistor The eighth thin film transistor 177 and the eighth thin film transistor 178 are n-channel transistors. When the gate-source voltage (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive. It shall become.

[0252] Next, the connection configuration of the flip-flop shown in FIG. 33 will be described below.

[0253] The first electrode (either the source electrode or the drain electrode) of the first thin film transistor 171 is A second electrode (source electrode) of the first thin film transistor 171 is connected to the fifth wiring 504. or the other of the drain electrodes) is connected to a third wiring 503.

[0254] A first electrode of the second thin film transistor 172 is connected to the sixth wiring 506, and A second electrode of the transistor 172 is connected to a third wiring 503 .

[0255] A first electrode of the third thin film transistor 173 is connected to a fifth wiring 505. A second electrode of the transistor 173 is connected to a gate electrode of the second thin film transistor 172. The gate electrode of the third thin film transistor 173 is connected to a fifth wiring 505 .

[0256] A first electrode of the fourth thin film transistor 174 is connected to the sixth wiring 506, and A second electrode of the transistor 174 is connected to the gate electrode of the second thin film transistor 172. The gate electrode of the fourth thin film transistor 174 is connected to the gate electrode of the first thin film transistor 171. The terminal is connected to the ground electrode.

[0257] A first electrode of the fifth thin film transistor 175 is connected to a fifth wiring 505. A second electrode of the transistor 175 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the fifth thin film transistor 175 is connected to the first wiring 501 .

[0258] A first electrode of the sixth thin film transistor 176 is connected to the sixth wiring 506, and A second electrode of the transistor 176 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the sixth thin film transistor 176 is connected to the gate electrode of the second thin film transistor 172. The terminal is connected to the ground electrode.

[0259] A first electrode of the seventh thin film transistor 177 is connected to the sixth wiring 506, and A second electrode of the transistor 177 is connected to the gate electrode of the first thin film transistor 171. The gate electrode of the seventh thin film transistor 177 is connected to the second wiring 502. The first electrode of the thin film transistor 178 is connected to the sixth wiring 506, and the eighth thin film transistor a second electrode of the second thin film transistor 178 connected to the gate electrode of the second thin film transistor 172; The gate electrode of the eighth thin film transistor 178 is connected to the first wiring 501 .

[0260] The gate electrode of the first thin film transistor 171 and the gate electrode of the fourth thin film transistor 174 are a first electrode of the fifth thin film transistor 175; a second electrode of the sixth thin film transistor 176 The connection point of the second electrode of the seventh thin film transistor 177 and the second electrode of the seventh thin film transistor 178 is a node 143. Furthermore, the gate electrode of the second thin film transistor 172, the gate electrode of the third thin film transistor A second electrode of the fourth thin film transistor 174 and a second electrode of the sixth thin film transistor The connection point of the gate electrode of the eighth thin film transistor 176 and the second electrode of the eighth thin film transistor 178 is The code shall be 144.

[0261] The first wiring 501, the second wiring 502, the third wiring 503 and the fourth wiring 504 are , may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 505 may be called a first power supply line, and the sixth wiring 506 may be called a second power supply line. stomach.

[0262] FIG. 35 shows an example of a top view of the flip-flop shown in FIG.

[0263] The conductive film 901 includes a portion that functions as a first electrode of the first thin film transistor 171. , and is connected to the fourth wiring 504 via a wiring 951 formed at the same time as the pixel electrode.

[0264] The conductive film 902 includes a portion that functions as a second electrode of the first thin film transistor 171. It is connected to the third wiring 503 via a wiring 952 that is formed at the same time as the pixel electrode.

[0265] The conductive film 903 is a gate electrode of the first transistor and a gate electrode of the fourth thin film transistor 174. The gate electrode includes a portion that functions as the gate electrode.

[0266] The conductive film 904 is a first electrode of the second thin film transistor 172, A first electrode of the fourth thin film transistor 174 and a first electrode of the eighth thin film transistor The sixth wiring 506 includes a portion that functions as the first electrode of the transistor 178. .

[0267] The conductive film 905 includes a portion that functions as a second electrode of the second thin film transistor 172. , and is connected to the third wiring 503 via a wiring 954 formed at the same time as the pixel electrode.

[0268] The conductive film 906 is a gate electrode of the second thin film transistor 172 and a gate electrode of the sixth transistor It includes a portion that functions as a gate electrode.

[0269] The conductive film 907 includes a portion that functions as a first electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0270] The conductive film 908 is a second electrode of the third thin film transistor 173 and a second electrode of the fourth thin film transistor 174. The wiring 9 is formed at the same time as the pixel electrode, and includes a portion that functions as the second electrode of the pixel electrode 174. It is connected to the conductive film 906 via 56 .

[0271] The conductive film 909 includes a portion that functions as a gate electrode of the third thin film transistor 173. , and is connected to the fifth wiring 505 via wiring 955.

[0272] The conductive film 910 includes a portion that functions as a first electrode of the fifth thin film transistor 175. , and is connected to the fifth wiring 505 via a wiring 959 formed at the same time as the pixel electrode.

[0273] The conductive film 911 is a second electrode of the fifth thin film transistor 175 and a second electrode of the seventh thin film transistor The wiring 9 is formed at the same time as the pixel electrode, and includes a portion that functions as the second electrode of the pixel electrode 177. It is connected to the conductive film 903 via 58.

[0274] The conductive film 912 includes a portion that functions as a gate electrode of the fifth thin film transistor 175. , and is connected to the first wiring 501 via a wiring 960 that is formed at the same time as the pixel electrode.

[0275] The conductive film 913 includes a portion that functions as a second electrode of the sixth thin film transistor 176. The pixel electrodes are connected to the conductive film 903 via wirings 957 formed at the same time as the pixel electrodes.

[0276] The conductive film 914 includes a portion that functions as a gate electrode of the seventh thin film transistor 177. , and is connected to the second wiring 502 via a wiring 962 formed at the same time as the pixel electrode.

[0277] The conductive film 915 includes a portion that functions as a gate electrode of the eighth thin film transistor 178. The pixel electrodes are connected to the conductive film 912 via wirings 961 formed at the same time as the pixel electrodes.

[0278] The conductive film 916 includes a portion that functions as a second electrode of the eighth thin film transistor 178. The pixel electrodes are connected to the conductive film 906 via wirings 953 formed at the same time as the pixel electrodes.

[0279] The circuits shown in FIGS. 32 to 34 are configured using transistors using microcrystalline semiconductors. A liquid crystal display device can operate circuits at high speed. For example, When comparing the case where the LPSAS membrane was used with the case where the LPSAS membrane was used, Since the mobility of the transistor is large, the shift register of the driver circuit (for example, the scanning line driver circuit 702) It is possible to increase the driving frequency of the scanning line driving circuit 702. Since it can be operated at a high frame rate, it is possible to increase the frame frequency or insert a black screen. It is also possible to make things come true.

[0280] When increasing the frame frequency, the screen data is generated according to the direction of the image movement. In other words, it is desirable to perform motion compensation and interpolate the data. In addition, the frame frequency is increased and image data is interpolated, improving the display characteristics of moving images. For example, the frequency can be doubled (for example, 120 Hz, 100 Hz). Hz) or more, and more preferably four times that frequency (for example, 480 Hz, 400 Hz) or more. This can reduce blurring and afterimages in moving images. The circuit 702 can also be operated at a higher drive frequency to increase the frame frequency. It is possible to do this.

[0281] When inserting a black screen, image data or data for black display is supplied to the pixel unit 701. As a result, it becomes similar to impulse driving, and afterimages can be reduced. In this case, the scanning line driving circuit 702 is also operated at a high driving frequency. This allows for black screen insertion.

[0282] Furthermore, the channel width of the transistor of the scanning line driver circuit 702 is increased, and By arranging a scanning line driving circuit, etc., a higher frame frequency can be achieved. For example, the frame frequency can be increased by 8 times (e.g., 960 Hz, 800 Hz) or more. When multiple scanning line driving circuits are arranged, the number of scanning line driving circuits is set to 100. The scanning line driving circuit for driving the odd-numbered scanning lines is disposed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is disposed on the other side. By placing it on the opposite side of the For example, the channel width of the second thin film transistor 172 is 300 μm or more. It is desirable that the thickness is 1000 μm or more.

[0283] Note that the circuits shown in FIGS. 32 to 34 may be constructed using transistors using a microcrystalline semiconductor. By forming the display device in this way, the layout area can be reduced. For example, the frame of a liquid crystal display device can be made smaller. When comparing the case where the LPSAS membrane was used with the case where the LPSAS membrane was used, Because the mobility of the transistor is high, the channel width of the transistor can be made small. As a result, it is possible to narrow the frame of the liquid crystal display device. The channel width of the thin film transistor 172 is preferably 3000 μm or less, more preferably 2000 μm or less. It is desirable that the thickness is less than 1 μm.

[0284] In addition, the second thin film transistor 172 in FIG. During this period, the second thin film transistor 172 is always in the on state. Therefore, a strong stress is applied to the second thin film transistor 172. This makes the transistor characteristics more susceptible to degradation. The low voltage gradually increases. As a result, the current value decreases. In order to ensure that sufficient current can be supplied even if the transistor deteriorates, a second thin-film transistor is used. It is desirable for the channel width of the transistor 172 to be large. It is desirable to compensate for this so that the circuit operation is not affected. A transistor is arranged in parallel with the second thin film transistor 172 and is crossed with the second thin film transistor 172. It is desirable to make the transistors less susceptible to degradation by turning them on alternately. stomach.

[0285] However, when comparing the case where an amorphous semiconductor film is used with the case where an LPSAS film is used, However, the LPSAS membrane is less prone to deterioration. In this case, the channel width of the transistor can be reduced. This allows the device to operate normally without the need for a compensation circuit. This allows the planar area of ​​each transistor to be reduced.

[0286] (Embodiment 9) FIG. 36 shows the appearance and cross section of a liquid crystal display panel corresponding to one embodiment of the display device of the present invention. FIG. 36(A) shows a semiconductor device having an LPSAS film formed on a first substrate 4001. A thin film transistor 4010 and a liquid crystal element 4013 are sandwiched between a second substrate 4006. FIG. 36(B) is a top view of the panel sealed with sealing material 4005, and FIG. 36(A) is a top view of the panel sealed with sealing material 4005. ) is a cross-sectional view taken along line A-A'.

[0287] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealant 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealant 4005, and a second substrate 400. The liquid crystal 4008 is sealed by the sealant 6 on the first substrate 4001. In a region different from the region surrounded by the material 4005, a polycrystalline silicon layer is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film is mounted. A signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is formed on the first substrate 40. We will explain an example of bonding to 01. A transistor using a single crystal semiconductor is used for the signal line. A driver circuit may be formed and then bonded. In FIG. 36, a signal line driver circuit 400 4 illustrates a thin film transistor 4009 formed of a polycrystalline semiconductor film, which is included in the third embodiment.

[0288] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 36B, the thin film transistor included in the pixel portion 4002 is The thin film transistor 4010 is an LPSAS film. This corresponds to the thin film transistor used.

[0289] The pixel electrode 4030 of the liquid crystal element 4013 is a thin The counter electrode of the liquid crystal element 4013 is electrically connected to the film transistor 4010. 4031 is formed on the second substrate 4006. The pixel electrode 4030 and the counter electrode 403 The portion where the liquid crystal 4008 overlaps with the liquid crystal element 4008 corresponds to the liquid crystal element 4013 .

[0290] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically Stainless steel, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (polyvinyl fluoride) film, polyester film, or acrylic resin You can also use aluminum foil with a PVF film or polyester film. It is also possible to use a sheet having a structure in which the sheet is sandwiched between two thermoplastic films.

[0291] Also, 4035 is a spherical spacer, which is disposed between the pixel electrode 4030 and the counter electrode 4031. The insulating film is selectively etched to control the distance (cell gap). Alternatively, a spacer obtained by gating may be used.

[0292] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section Various signals and potentials are applied to 4002 via wiring 4014 and 4015. Powered by FPC4018.

[0293] In this embodiment, the connection terminal 4016 is connected to the pixel electrode 4030 of the liquid crystal element 4013. The wiring 4014 and 4015 are formed from the same conductive film as the thin film transistor. The source electrode or drain electrode of the transistor 4010 is formed of the same conductive film.

[0294] The connection terminal 4016 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0295] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. It may further comprise a color filter and a shielding film.

[0296] In FIG. 36, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0297] This embodiment can be implemented in combination with the configurations described in other embodiment modes. be.

[0298] (Embodiment 10) Next, the appearance and cross section of a light-emitting display panel corresponding to one embodiment of the display device of the present invention will be described. The following will be explained with reference to FIG. 37(A). FIG. 37 shows a structure in which an LPSAS film formed on a first substrate is used. The thin film transistor and the light emitting element are sealed between the second substrate and the thin film transistor and the light emitting element by a sealant. 37(B) is a top view of the panel, and corresponds to a cross-sectional view taken along line A-A' in FIG. 37(A). do.

[0299] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealant 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealant 4005, and a second substrate 400. 6, together with the filler 4007. The multi-layered structure is formed on a separately prepared substrate in an area different from the area surrounded by the insulating material 4005. A signal line driver circuit 4003 formed of a crystalline semiconductor film is mounted on the substrate. A signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is mounted on a first substrate 4. We will explain an example of bonding to 001. Alternatively, a signal line driving circuit may be formed and then bonded to the substrate. In FIG. 4 shows an example of a thin film transistor 4009 formed of a polycrystalline semiconductor film, which is included in 03.

[0300] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 37B, the thin film transistor included in the pixel portion 4002 is In this embodiment, the thin film transistor 4010 is illustrated. It is assumed that TFT 010 is a driving TFT, while thin film transistor 4010 is a current control TFT. The thin film transistor 4010 may be an LPS TFT or an erasing TFT. This corresponds to a thin-film transistor using an AS film.

[0301] The pixel electrode of the light emitting element 4011 is a thin film transistor. The source electrode or drain electrode of the transistor 4010 is electrically connected to the wiring 4017. In this embodiment, the light-transmitting conductive material 4 of the light-emitting element 4011 is Note that the structure of the light-emitting element 4011 is the same as that shown in this embodiment. The direction of the light emitted from the light emitting element 4011 and the thin film transistor 4014 may be varied. The configuration of the light emitting element 4011 can be changed as appropriate in accordance with the polarity of the 010.

[0302] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel driver circuit 4006 are separately formed. Various signals and potentials are applied to the unit 4002 via wiring 4014 and 4015. and is supplied by FPC4018.

[0303] In this embodiment mode, the connection terminal 4016 is made of the same conductive film as the pixel electrode of the wiring 4017. The lead wirings 4014 and 4015 are formed of the thin film transistor 40 It is formed from the same conductive film as the source electrode or drain electrode 10 .

[0304] The connection terminal 4016 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0305] The substrate located in the direction in which light is extracted from the light emitting element 4011 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as film is used.

[0306] In addition, filler 4007 can be used with inert gases such as nitrogen and argon, as well as ultraviolet-curing gases. Resin or thermosetting resin can be used, PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used as the filler in this embodiment. Nitrogen was used.

[0307] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0308] In FIG. 37, the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. may be formed separately and mounted.

[0309] This embodiment can be implemented in combination with the configurations described in other embodiment modes. be.

[0310] (Embodiment 11) The display device obtained by the present invention can be used to manufacture an active matrix display module. In other words, the present invention can be applied to all electronic devices that incorporate these in their display units. This can be done.

[0311] Such electronic devices include video cameras, digital cameras, and head-mounted displays. Ray (goggle-type display), car navigation, projector, car stereo, Personal computers, personal digital assistants (mobile computers, mobile phones or electronic books) An example of this is shown in Figure 30.

[0312] FIG. 30(A) is a television device. The display module is as shown in FIG. Then, the TV set can be completed by installing the FPC in the housing. The display panel mounted on the display unit is also called a display module. 03 is formed, and other auxiliary equipment such as a speaker unit 2009 and an operation switch are provided. In this manner, the television device is completed.

[0313] As shown in FIG. 30A, a display panel 2002 using a display element is mounted on a housing 2001. The receiver 2005 can receive general television broadcasts, and the modem 2004 can receive the By connecting to a wired or wireless communication network via It is also possible to communicate information one-to-one (between a sender and a receiver, or between receivers) or two-way (between a sender and a receiver, or between receivers themselves). The television set can be operated by a switch built into the housing or by a separate remote control. This can be done by the remote control device 2006, which also displays the information to be output. A display unit 2007 may also be provided.

[0314] In addition to the main screen 2003, the television device also has a sub-screen 2008 for second display. The display may be formed of a panel and may be provided with a configuration for displaying channels, volume, etc. The main screen 2003 is formed of a liquid crystal display panel with a good viewing angle, and the sub screen is formed of a low-power It may be formed of a light-emitting display panel that can display with electricity. In order to achieve this, the main screen 2003 is formed of a light-emitting display panel, and the sub-screen is formed of a light-emitting display panel. The sub screen may be configured to be able to blink.

[0315] FIG. 31 is a block diagram showing the main components of a television device. A pixel portion 921 is formed on the display panel 921. A signal line driver circuit 922 and a scanning line driver circuit 923 are provided on the display panel 921. The display panel 900 may be mounted using the COG method.

[0316] As for the configuration of other external circuits, on the video signal input side, a signal received by a tuner 924 A video signal amplifier circuit 925 amplifies the video signal, and the signal output from the video signal amplifier circuit 925 is converted into red. a video signal processing circuit 926 which converts the video signals into color signals corresponding to the colors red, green, and blue; It has a control circuit 927 for converting the input specifications of the driver IC. The control circuit 927 outputs signals to the scanning line side and the signal line side. In this case, a signal division circuit 928 is provided on the signal line side to divide the input digital signal into m parts. The power supply may be configured to be supplied via the power supply.

[0317] Of the signals received by the tuner 924, the audio signal is sent to an audio signal amplifier circuit 929. The output of the control circuit 93 is supplied to a speaker 933 via an audio signal processing circuit 930. 1 receives control information for a receiving station (receiving frequency) and volume from an input unit 932, and A signal is sent to the audio signal processing circuit 930.

[0318] Of course, the present invention is not limited to television devices, and may be used with monitors of personal computers. In addition, it is also used in large-area displays such as information display boards at train stations and airports, and advertising display boards on the street. It can also be used for various purposes as a display medium.

[0319] FIG. 30B shows an example of a mobile phone 2301. This mobile phone 2301 has a display The display unit 2302 includes an operation unit 2303. By applying the display device described in the above embodiment, mass productivity can be improved.

[0320] The portable computer shown in FIG. 30C includes a main body 2401, a display unit 2402, etc. By applying the display device described in the above embodiment to the display portion 2402, , mass productivity can be improved.

[0321] FIG. 30(D) shows a table lamp, which includes a lighting unit 2501, a shade 2502, and an adjustable arm 2503. 2501, a support 2504, a base 2505, and a power source 2506. The lighting fixtures are either ceiling-mounted or wall-mounted. By applying the display device shown in the above embodiment, This improves productivity and provides an inexpensive desk lighting fixture. [Explanation of symbols]

[0322] 23a: Microcrystalline semiconductor film 23b: Microcrystalline semiconductor film containing boron 33a:LPSAS membrane 33b: Microcrystalline semiconductor film containing boron 43: Microcrystalline semiconductor film 50: Circuit board 51: Gate electrode 52a, 52b, 52c: gate insulating film 53:LPSAS membrane 54: Buffer layer 55: Semiconductor film doped with impurities that give one conductivity type 56: Resist mask 59: Multi-tone mask 61:LPSAS membrane 62: Buffer layer 63: Semiconductor film doped with impurities that give one conductivity type 65a, 65b, 65c: Conductive film 66: Resist mask 71a, 71b, 71c: source electrode and drain electrode 72: Source and drain regions 73: Buffer layer 74: Thin-film transistor 76: Insulating film 77: Pixel electrode 80: Resist 81: Resist mask 83: Thin film transistor 85a~85c: Conductive film 87: Buffer layer 86: Resist mask 88: Source and drain regions 90:LPSAS membrane 92a, 92b, 92c: source and drain electrodes 111: Flattening film

Claims

1. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; Semiconductor device.

2. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; a fourth conductive film having a function as a gate of the fifth transistor and a fifth conductive film having a function as a gate of the eighth transistor are always electrically connected to each other through a sixth conductive film; Semiconductor device.

3. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; a fourth conductive film having a function as a gate of the fifth transistor and a fifth conductive film having a function as a gate of the eighth transistor are always electrically connected to each other through a sixth conductive film; a seventh conductive film having a function as the third wiring has a function as one of a source or a drain of the second transistor, a function as one of a source or a drain of the fourth transistor, a function as one of a source or a drain of the sixth transistor, a function as one of a source or a drain of the seventh transistor, and a function as one of a source or a drain of the eighth transistor; Semiconductor device.

4. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the fourth wiring; the gate of the third transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; Semiconductor device.

5. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the fourth wiring; the gate of the third transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; a fourth conductive film having a function as a gate of the fifth transistor and a fifth conductive film having a function as a gate of the eighth transistor are always electrically connected to each other through a sixth conductive film; Semiconductor device.

6. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring, the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the third transistor is always electrically connected to the fourth wiring; the gate of the third transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; a gate of the fourth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the fourth wiring; a gate of the fifth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the third wiring, the other of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the gate of the seventh transistor is always electrically connected to the sixth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring, the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to the fifth wiring; a first conductive film having a function as one of the source or drain of the third transistor and the other of the source or drain of the fourth transistor is always electrically connected to a third conductive film having a function as the other of the source or drain of the eighth transistor through a second conductive film having a function as a gate of the second transistor and a function as a gate of the sixth transistor; a fourth conductive film having a function as a gate of the fifth transistor and a fifth conductive film having a function as a gate of the eighth transistor are always electrically connected to each other through a sixth conductive film; a seventh conductive film having a function as the third wiring has a function as one of a source or a drain of the second transistor, a function as one of a source or a drain of the fourth transistor, a function as one of a source or a drain of the sixth transistor, a function as one of a source or a drain of the seventh transistor, and a function as one of a source or a drain of the eighth transistor; Semiconductor device.

7. In any one of claims 1 to 6, The first transistor to the eighth transistor have the same polarity. Semiconductor device.

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