Adaptive zero voltage switching for near field communication

Abstract

To provide systems and methods for operating a wireless power transfer device.SOLUTION: A circuit can generate a first signal that indicates a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter falling below ground. The circuit can delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. The circuit can merge the first signal and the second signal to generate a third signal. A controller can use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at specific time. The first LS transistor being turned on at the specific time can reduce a diode conduction time of a body diode of the first LS transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD The present disclosure relates generally to an apparatus and method for wireless power transmission devices, and more particularly, to improving the operating efficiency of wireless power receivers by reducing the conduction time of diodes. [Background technology]

[0002] Wireless power transfer using a Near Field Communication (NFC) protocol (e.g., an NFC wireless power system) can occur between two devices that include a Near Field Communication (NFC) interface. Such an NFC wireless power system can include a polar having a transmit coil and a listener having a receive coil. In certain embodiments, the polar may be connected to a structure that includes a wireless charging area. In response to a device that includes a listener being placed in proximity to a device that includes a polar, the transmit coil and the receive coil can inductively couple to each other to establish an NFC communication link between the polar and the listener. This established NFC communication link can be used to generate an inductive transfer of alternating current (AC) power. The transfer of AC power from the polar to the listener can facilitate charging of a battery of a device that includes the listener. Summary of the Invention

[0003] In one embodiment, generally, a semiconductor device in a wireless power transmission device is provided. The semiconductor device may include a controller, a switching converter, and a circuit. The switching converter may include a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor, and a second LS transistor. The circuit may be configured to generate a first signal indicating that a voltage at a node between the first HS transistor and the first LS transistor goes below ground. Furthermore, the circuit may be configured to delay a gate-source voltage of the second LS transistor to generate a second signal. Furthermore, the circuit may be configured to combine the first signal and the second signal to generate a third signal. The controller may be configured to use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time. The first LS transistor being turned on at a specific time may reduce a diode conduction time of a body diode of the first LS transistor.

[0004] In one embodiment, generally, a semiconductor device for a semiconductor device in a wireless power transmission device is provided. The semiconductor device may include a comparator configured to generate a first signal indicative of a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in the switching converter going below ground. Additionally, the semiconductor device may include a delay circuit configured to delay a gate-source voltage of a second LS transistor in the switching converter to generate a second signal. Additionally, the semiconductor device may include an OR gate configured to combine the first signal and the second signal to generate a third signal. Additionally, the OR gate may be configured to send the third signal to a controller to trigger a rising edge of a command signal to turn on the first LS transistor at a particular time. The first LS transistor being turned on at a particular time may reduce a diode conduction time of a body diode of the first LS transistor.

[0005] In one embodiment, generally, a method for operating a wireless power transfer device is provided. The method may include generating a first signal indicative of a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor in a switching converter going below ground. Additionally, the method may include delaying a gate-to-source voltage of a second LS transistor in the switching converter to generate a second signal. Additionally, the method may include combining the first signal and the second signal to generate a third signal. Additionally, the method may include using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a particular time. The first LS transistor being turned on at a particular time may reduce a diode conduction time of a body diode of the first LS transistor. [Brief description of the drawings]

[0006] Further features, structure, and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings, where like reference numbers indicate identical or functionally similar elements. [Figure 1] FIG. 1 illustrates an example system capable of implementing adaptive zero voltage switching for near field wireless communication in one embodiment. [Diagram 2] FIG. 1 illustrates an example circuit capable of implementing adaptive zero voltage switching for near field communication in one embodiment. [Diagram 3] FIG. 1 is a diagram illustrating signal waveforms in an implementation example of adaptive zero voltage switching for short-range wireless communication in one embodiment. [Figure 4] FIG. 1 is a flow diagram illustrating a process for implementing adaptive zero voltage switching for near field wireless communication in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In the following description, numerous specific details are set forth, including specific structures, components, materials, dimensions, processing steps, and techniques, to facilitate an understanding of various embodiments of the present application. However, those skilled in the art will appreciate that various embodiments of the present application may be realized without these specific details. In some cases, details of known structures or processing steps are omitted in order not to obscure the present application.

[0008] The NFC wireless power system can provide charging under static or negotiation modes. The static mode uses a standard radio frequency (RF) field strength and provides a consistent power level. The negotiation mode can use a relatively high RF field corresponding to different power transfer classes, such as 250, 500, 750, 1000 milliwatts (mW). In the NFC wireless power system, the poller and the listener can communicate with each other using an NFC communication protocol. In one aspect, the NFC wireless power system can use a specific base frequency (e.g., 13.56 megahertz (MHz)) and leverage the NFC communication link between the two devices to control the power transfer. To perform NFC communication, one device can apply or transfer a modulated signal, such as an amplitude shift keying (ASK) signal, to the other device, and the other device can demodulate the modulated signal.

[0009] FIG. 1 illustrates an exemplary system capable of implementing adaptive zero voltage switching for near field wireless communication in one embodiment. System 100 can include power devices, such as transmitter 110 and receiver 120, configured to wirelessly transfer power and data therebetween via inductive coupling. Although described herein as transmitter 110 and receiver 120, each of transmitter 110 and receiver 120 may be configured to transmit and receive power or data to one another via inductive coupling. Transmitter 110 is also referred to as a wireless power transmitter and receiver 120 is also referred to as a wireless power receiver. In an embodiment in which system 100 is configured as an NFC wireless power system, transmitter 110 may be configured as a poller and receiver 120 may be configured as a listener. Transmitter 110 and receiver 120 can include various types of circuit components, such as integrated circuits (ICs), which may be semiconductor devices constructed of semiconductor materials.

[0010] The transmitter 110 may be configured to receive power from one or more power sources and wirelessly transmit the AC power to the receiver 120. For example, the transmitter 110 may be configured to connect to a power source 116, such as an adapter or a DC power source. The transmitter 110 may be a semiconductor device including a controller 112, a resonant circuit 113, and a switching converter 114. The switching converter 114 may be an integrated circuit (IC) that is part of a power driver configured to convert a particular type of current to another type of current. For example, the switching converter 114 may be configured as an inverter that converts a DC signal to an AC signal.

[0011] The controller 112 may be configured to control and operate the switching converter 114 and other components of the transmitter 110. The controller 112 may include, for example, a processor, a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), or any other circuitry configured to control and operate the switching converter 114. Although described as a CPU in the exemplary embodiments, the controller 112 is not limited to a CPU in these embodiments and may include any other circuitry configured to control and operate the switching converter 114. In the exemplary embodiments, the controller 112 may be configured to control the switching converter 114 and drive the resonant circuit 113 to generate a magnetic field. The switching converter 114 may drive the coil TX at a range of frequencies and configurations defined by a wireless power standard, such as, for example, the NFC Forum's Wireless Charging (WLC) specification. The resonant circuit 113 may include the coil TX and one or more capacitors, inductors, and resistors that may form a circuit to output various signals to transfer AC power 130 to the receiver 120. The antenna interface circuit 102 may be connected to the transmitter 110 and may include one or more capacitors, inductors, and resistors that form a filter, matching network, or other circuit to interface the transmitter 110 with an antenna 124.

[0012] The receiver 120 may be configured to receive the AC power 130 transmitted from the transmitter 110 and provide power to one or more loads 126 of the destination device or other components including the receiver 120. The loads 126 may include, for example, a battery charger configured to charge a battery of the destination device 140, a DC-DC converter configured to provide DC power 132 to a processor, display, or other electronic components of the destination device 140, or any other load of the destination device 140. The destination device may include the receiver 120 and may be, for example, a computing device, a smart device, a wearable device, or any other electronic device configured to receive power wirelessly. In other embodiments, the receiver 120 may be separate from the destination device and connected to the destination device via a wire or other component configured to provide power to the destination device 140.

[0013] The receiver 120 may be a semiconductor device including a controller 122, a resonant circuit 123, a switching converter 124, and a circuit 150. In one embodiment, the circuit 150 may be an IC, such as a semiconductor device constructed of semiconductor materials. The controller 122 may be an integrated circuit including, for example, a digital controller, such as a microcontroller, a processor, a CPU, an FPGA, or any other circuit that may be configured to control and operate the switching converter 124. The resonant circuit 123 may include a coil RX and one or more capacitors, inductors, or resistors that may form a circuit for receiving the AC power 130 and outputting the communication packet 136. The switching converter 124 may be an IC configured to convert a particular type of current to another type of current. For example, the switching converter 124 may be configured as a power rectifier that converts an AC signal to a DC signal. When configured as a power rectifier, the power switching converter 124 may include a rectifier circuit such as a half-bridge rectifier, a full-bridge rectifier, or other type of rectifier circuit that may be configured to rectify the power received via the resonant coil RX of the resonant circuit 123 into the power type required by the load 126.

[0014] For example, when receiver 120 is placed in proximity to transmitter 110, the magnetic field generated by coil TX of resonant circuit 113 and switching converter 114 induces a current in coil RX of resonant circuit 123. The induced current causes AC power 130 to be inductively transmitted through resonant circuit 123 to switching converter 124. Switching converter 124 can receive AC power 130 and convert it to DC power 132 for load 126.

[0015] The transmitter 110 and the receiver 120 are also configured to exchange data, such as information or messages, via the inductive coupling of the power driver 106 and the resonant circuits 113, 123. For example, a power contract may be agreed upon and created between the receiver 120 and the transmitter 110 before the transmitter 110 initiates power transfer to the receiver 120. For example, the receiver 120 may transmit a communication packet 136 to the transmitter 110 using an ASK signal indicating power transfer information, such as an amount of power to be transferred to the receiver 120, a command to increase, decrease, or maintain the power level of the AC power 130, a command to stop the power transfer, or other power transfer information. In another embodiment, in response to the receiver 120 being placed in close proximity to the transmitter 110, for example, in close enough proximity such that a transformer may be formed by coil TX and coil RX to enable power transfer, the receiver 120 may be configured to initiate communication by transmitting a signal to the transmitter 110 requesting power transfer. In such a case, the transmitter 110 may respond to a request by the receiver 120 by establishing a power contract or, for example, if a power contract is already in place, may initiate a power transfer to the receiver 120. The transmitter 110 and the receiver 120 may transmit and receive ASK signals, data, or other information via inductive coupling of coils TX and RX.

[0016] As shown in FIG. 1, the switching converter 124 may be formed by two half-bridge circuits including two high-side metal-oxide-semiconductor field-effect transistors (MOSFETs) HS1, HS2 and two low-side MOSFETs LS1, LS2. The MOSFETs HS1 and LS2 may be turned on and off simultaneously, and the MOSFETs HS2 and LS1 may be turned on and off simultaneously. The pair of HS1, LS2 and the pair of HS2, LS1 may be alternately switched to rectify the AC power 130 into DC power 132. The alternate switching may allow current to flow alternately from node AC1 to AC2 and vice versa. When HS2 and LS1 are turned on, current may flow from AC1 to AC2. During this time, the voltage of AC1 is low and the voltage of AC2 is high. When HS1 and LS2 are turned on, current may flow from AC2 to AC1. During this time, the voltage of AC2 is low and the voltage of AC1 is high.

[0017] Maximizing operational efficiency is a key aspect of wireless charging. Operational efficiency impacts the power density and charging time of portable devices as well as environmental impact. In one aspect, some receivers can utilize Schottky diodes to rectify the received AC power, but Schottky diodes have a large forward voltage drop that can limit the receiver efficiency to less than 80%. Some receivers can implement active rectifiers using low RDS(on) transistors, but active rectifiers may require precise control of MOSFETs while accommodating high frequencies of AC signals (e.g., in the 13.56 MHz range).

[0018] In one aspect, when the switching converter 124 senses a current flowing through one diagonal (e.g., either LS1-HS2 or LS2-HS1), the corresponding MOSFET is turned on to provide a low-loss current path. However, there is a delay in turning on the corresponding MOSFET in the diagonal. During this delay, the current path may be through the body diode of the MOSFET. This causes a forward voltage drop of the diode. The forward voltage drop of the diode may cause increased losses, increase heat, and reduce operating efficiency. In one aspect, a delay that causes the diode conduction time to exceed 3 nanoseconds (ns) reduces the efficiency of the receiver by more than 0.7%.

[0019] To improve the efficiency of the receiver 120, the receiver 120 can include at least one circuit 150 that can be configured to perform zero voltage switching (ZVS) control. ZVS control can include monitoring instances where the voltage at nodes AC1 and / or AC2 crosses zero voltage (e.g., goes below zero or below ground) and performing one or more tasks to control other aspects of the receiver 120 in response to the voltage crossing zero voltage. In one embodiment, the circuit 150 can monitor low-side MOSFETs LS1, LS2 and reduce diode conduction time when the MOSFETs LS1, LS2 are turned on. A copy of the circuit 150 can be connected across LS1 and another copy of the circuit 150 can be connected across LS2. In one embodiment, the circuit 150 can reduce the diode conduction time of the MOSFETs by measuring the voltage across a MOSFET, such as LS1 or LS2, and predicting the rising edge of the gate-to-source voltage (Vgs) of the MOSFET based on the measured voltage. Reducing the diode conduction time also leads to reduced electromagnetic interference (EMI).

[0020] FIG. 2 illustrates an exemplary circuit that can implement adaptive zero voltage switching for near field communication in one embodiment. The description of FIG. 2 can refer to the components illustrated in FIG. 1. The embodiment illustrated in FIG. 2 can be an implementation of a circuit 150 for monitoring LS1 and reducing the diode conduction time of the body diode 200 of LS1. The implementation of the circuit 150 illustrated in FIG. 2 can also be applied to LS2 of the switching converter 124 of FIG. 1. In one embodiment, the circuit 150 can be implemented using the components illustrated in FIG. 2. In the embodiment illustrated in FIG. 2, the circuit 150 can include a comparator 202, a delay circuit 206, a delay circuit 208, an OR gate 210, an arbiter 212, a filter 214, and a counter 216.

[0021] An input of the comparator 202 may be connected across a low-side MOSFET in the switching converter 124, such as LS1 or LS2 (LS1 in FIG. 2). The comparator 202 may monitor the voltage at node AC1. A gate of LS1 may be applied with a gate-to-source voltage VGS_LS1. If VGS_LS1 is greater than the threshold voltage of LS1, LS1 may be turned on. When LS1 is turned on, current flows through LS1 and the voltage at node AC1 goes low. A voltage output by the comparator 202, which is the comparator output 204 or on1_comp signal, may indicate whether the voltage at node AC1 is above ground or below ground (e.g., above or below zero).

[0022] The circuit 150 may receive a gate-source voltage of LS1 (VGS_LS1) and a gate-source voltage of LS2 (VGS_LS2). The delay circuit 206 may add a delay (e.g., a trimmed delay) to VGS_LS1. The delay circuit 206 may output a delayed VGS_LS1 signal 207. In one embodiment, the delay applied by the delay circuit 206 may be predefined and fixed and may be equivalent to the propagation delay of the comparator 202. The delay circuit 208 may apply a programmable delay to the falling edge of VGS_LS2. Here, the programmable delay may depend on the delay signal 217. The delay circuit 208 may output a signal 209 that is a delayed version of the falling edge of VGS_LS2.

[0023] The arbiter 212 may be configured to check the arrival order of the signals VGS_LS1 and the comparator output 204 (or on1_comp) every cycle. If on1_comp arrives at the r1 input of the arbiter 212 before VGS_LS1 arrives at the r2 input of the arbiter 212, the arbiter 212 may output the signal g1. If on1_comp arrives at the r2 input of the arbiter 212 before VGS_LS1 arrives at the r1 input of the arbiter 212, the arbiter 212 may output the signal g2.

[0024] The filter 214 may be a digital filter configured to filter noise from the output of the arbiter 212. The filter 214 may also check whether either g1 or g2 is output by the arbiter 212 for more than one consecutive cycle. If g1 is output by the arbiter 212 for more than one cycle, the counter 216 may count down by decreasing the delay signal 217. If g2 is output by the arbiter 212 for more than one cycle, the counter 216 may count up by increasing the delay signal 217. The delay signal 217 may be applied to the delay circuit 208 to adjust the delay applied on the falling edge of VGS_LS2. In one embodiment, the system (e.g., the receiver 120) may eventually reach a steady state and the counter 216 may stop counting or alternately increase and decrease the delay signal 217 to maintain the delay signal 217.

[0025] The OR gate 210 may receive the comparator output 204 and the signal 209. The OR gate 210 may combine or join the comparator output 204 and the signal 209. The controller 122 may receive the ON1 output from the OR gate 210. ON1, which is a high voltage (e.g., a binary 1), may trigger a rising edge of a command signal 219 output by the controller 122. The driver 220 receives the command signal 219 and turns on LS1 by applying VGS_LS1 to the gate of LS1 (e.g., VGS_LS1 goes high). When LS1 turns on, the body diode 200 may be rectified, terminating the diode conduction time.

[0026] In one aspect, if the circuit 150 is deactivated or the applied delay is too long (e.g., after power-up when the system has not yet reached steady state), the comparator 202 can provide the comparator output 204 directly to the controller 122 to trigger the controller 122 to control the driver 220 to turn on LS1. The propagation delays of the comparator 202, the controller 122, and the driver 220 can contribute to the diode conduction time of the body diode 200 of LS1. Activating the circuit 150 can predict the on-time of LS1 and turn on LS1 earlier than if the circuit 150 is inactive. The earlier on-time can reduce the diode conduction time of the body diode 200 in LS1.

[0027] In one embodiment, the ON1 signal generated based on the delay of the applied delay circuit 208 and output by the OR gate 210 can replace the comparator output 204 (on1_comp) to trigger the rising edge of the command signal 219 at an earlier time compared to using on1_comp (or when the circuit 150 is deactivated) to trigger the rising edge of the command signal 219. By advancing the triggering of the rising edge of the command signal 219 that turns on LS1, the rising edge of the on1_comp signal can be timed to align with the VGS_LS1 signal.

[0028] Further, the arbiter 212 and counter 216, and optionally the filter 214, can be utilized to provide adaptive compensation for propagation delays and precise control over the alignment of the on1_comp and VGS_LS1 signals. For example, if the on1_comp signal lags the VGS_LS1 signal, the signal 207 can arrive at the arbiter 212 earlier than the comparator output 204. The arbiter 212 can output g2 to trigger the counter 216 to increase the delay signal 217 to increase the programmable delay applied by the delay circuit 208. The increased delay applied by the delay circuit 208 can delay the VGS_LS1 signal and align VGS_LS1 with the lagging on1_comp signal. If the VGS_LS1 signal lags the on1_comp signal, the comparator output 204 can arrive at the arbiter 212 earlier than the signal 207. The arbiter 212 can output g1 to trigger the counter 216 and decrement the delay signal 217 to decrease the programmable delay applied by the delay circuit 208. The decreased delay applied by the delay circuit 208 can trigger the rising edge of the VGS_LS1 signal earlier to align the lagging VGS_LS1 with the on1_comp signal. The adaptive matching can maintain the reduced diode conduction time of the body diode 200, leading to improved efficiency of the receiver 120.

[0029] FIG. 3 illustrates waveforms of signals in an implementation of adaptive zero voltage switching for near field communication in one embodiment. The description of FIG. 3 may refer to the components illustrated in FIG. 1 and FIG. 2. FIG. 3 illustrates multiple waveforms of various signals in an implementation of circuit 150. In the waveforms illustrated in FIG. 3, the voltage at node AC1 may begin to fall below ground at approximately time t1. The propagation delay of comparator 202 may cause comparator 202 to raise the on1_comp signal to a high voltage at approximately time t3. The description of FIG. 3 regarding the implementation of circuit 150 for LS1 may also be applied to the implementation of circuit 150 for LS2.

[0030] 3 also shows the waveform of signal 209 output by delay circuit 208. The rising edge of signal 209 is a delayed version of the falling edge of VGS_LS2. Signal 209 remains high for a period of time sufficient to be latched by controller 122. If delay signal 217 increases the delay applied by delay circuit 208, the rising edge of signal 209 is delayed a longer time. If delay signal 217 decreases the delay applied by delay circuit 208, signal 209 is delayed a shorter time.

[0031] 2, signals 209 and on1_comp are provided to OR gate 210, so that in response to one or both of signals 209 and on1_comp being high, the output of OR gate 210, i.e., the ON1 signal, can be high. Signals 209 and on1_comp can be combined by OR gate 210, so that the rising edge of the ON1 signal can be triggered relatively early to compensate for the propagation delay in controller 122 and driver 220. As shown in FIG. 3, when signal 209 is high and on1_comp remains low, OR gate 210 outputs ON1 as a high voltage, so that command signal 219 output by controller 122 also goes high. Thus, signal 209 can trigger the rising edge of command signal 219 to start turning on LS1 before the rising edge of on1_comp signal. After the propagation delay of driver 220, VGS_LS1 can start rising at approximately time t2 to turn on LS1.

[0032] At time t3, the on1_comp signal rises, allowing VGS_LS1 to exceed the threshold voltage Vth of LS1. Thus, LS1 is fully on, allowing the diode conduction time of the body diode 200 in LS1 to end. The diode conduction time may begin at t1 and end at t3, which is the difference between the propagation time of the comparator 202 (e.g., from the voltage at AC1 falling below ground to the rising edge of on1_comp) and the delay applied by the circuit 206. Thus, the example of FIG. 3 shows an implementation of the circuit 150 in which the propagation delays of the controller 122 and the driver 220 are eliminated, and the propagation delay of 202 is significantly reduced.

[0033] In one embodiment, if the on1_comp signal rises later than t3, the on1_comp signal lags the VGS_LS1 signal and the circuit 150 can increase the delay applied by the delay circuit 208 to increase the rising edge delay of the signal 209. In one embodiment, if the on1_comp signal rises earlier than t3, the VGS_LS1 signal lags the on1_comp signal and the circuit 150 can decrease the delay applied by the delay circuit 208 to decrease the rising edge delay of the signal 209. In one embodiment, a reduction of approximately 300 picoseconds (ps) results in an improvement in operating efficiency of over 0.7%.

[0034] 4 is a flow diagram of a process for implementing adaptive zero voltage switching for near field wireless communications, according to one embodiment. The process may include one or more operations, acts, or functions as illustrated by one or more blocks 402, 404, 406, and / or 408. Although illustrated in the diagram as separate blocks, various blocks may be divided into additional blocks, combined into fewer blocks, omitted, performed in a different order, or performed in parallel, depending on the desired application.

[0035] The process 400 may be performed by a wireless power transmission device (e.g., a receiver, such as the receiver 120 described herein, or a transceiver). The process 400 may begin at block 402, where a circuit may generate a first signal indicating that a voltage at a node between a first high-side (HS) transistor and a first low-side (LS) transistor of a switching converter is below ground. In one embodiment, the switching converter may be provided in a listener of a near field communication (NFC) power transmission system. In one embodiment, a rising edge of a gate-source voltage of the first LS transistor aligns with a rising edge of the first signal at a particular time.

[0036] Process 400 may continue from block 402 to block 404. In block 404, the circuit may delay a gate-to-source voltage of a second LS transistor in the switching converter to generate a second signal. In one embodiment, the delay applied to the gate-to-source voltage of the second LS transistor may be a fixed delay.

[0037] The process 400 may continue from block 404 to block 406. In block 406, the circuit may combine the first signal and the second signal to generate a third signal. The process 400 may continue from block 406 to block 408. In block 408, the controller may use the third signal to trigger a rising edge of the command signal to turn on the first LS transistor at a particular time. The first LS transistor being turned on at a particular time may reduce the diode conduction time of the body diode of the first LS transistor.

[0038] In one embodiment, the circuit can delay the gate-source voltage of the first LS transistor to generate the fourth signal. The circuit can generate the delay signal based on arbitration between the first signal and the fourth signal. The circuit can use the delay signal to adjust a delay applied to the gate-source voltage of the second LS transistor. Adjusting the delay can adjust a particular time. In one embodiment, the delay applied to the gate-source voltage of the first LS transistor can be a programmable delay.

[0039] In one embodiment, in response to arbitration indicating the first signal arrives at the arbiter before the fourth signal, the circuitry can generate a delay signal to decrease the delay, and in response to arbitration indicating the fourth signal arrives at the arbiter before the first signal, the circuitry can generate a delay signal to increase the delay.

[0040] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion thereof of instructions that includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be implemented substantially simultaneously or may even be implemented in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of those blocks, may be implemented by a special purpose hardware-based system that performs the specified functions or operations or a combination of special purpose hardware and computer instructions.

[0041] The terms used in this specification are used only to describe certain embodiments and are not intended to limit the present invention. Terms used in this specification that denote the singular are also intended to include the plural unless otherwise specified. It should also be noted that the term "comprises" used in this specification defines the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] The corresponding structures, materials, operations, and equivalents of all means or steps and functional elements recited in the appended claims are intended to encompass any structures, materials, or operations for achieving a function in combination with other elements specifically described. The description of the disclosed embodiments of the present invention has been provided for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. It will be apparent to those skilled in the art that many modifications and variations can be applied without departing from the scope and spirit of the invention. The above-described embodiments have been selected and described in order to best explain the principles and practical applications of the invention and to enable those skilled in the art to understand the invention in various embodiments with various modifications as appropriate for the particular applications contemplated.

Claims

1. A semiconductor device comprising: A controller; a switching converter including a first high-side (HS) transistor, a second HS transistor, a first low-side (LS) transistor, and a second LS transistor; 1. A circuit comprising: generating a first signal indicating that a voltage at a node between the first HS transistor and the first LS transistor is below ground; delaying a gate-source voltage of the second LS transistor to generate a second signal; a circuit configured to combine the first signal and the second signal to generate a third signal; Including, the controller is configured to use the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time, the first LS transistor being turned on at the specific time reducing a diode conduction time of a body diode of the first LS transistor; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the switching converter is provided in a listener of a power transmission system using near field communication (NFC).

3. The circuit comprises: delaying the gate-source voltage of the first LS transistor to generate a fourth signal; generating a delay signal based on arbitration between the first signal and the fourth signal; configured to use the delay signal to adjust a delay applied to a gate-to-source voltage of the second LS transistor; Adjusting the delay adjusts the specific time. The semiconductor device according to claim 1 .

4. 4. The semiconductor device according to claim 3, wherein the delay applied to the gate-source voltage of the first LS transistor is a fixed delay.

5. in response to an arbitration indicating that the first signal arrives at the arbiter before the fourth signal, the delay signal is generated to decrease the delay; in response to an arbitration indicating that the fourth signal arrives at the arbiter before the first signal, the delay signal is generated to increase the delay. The semiconductor device according to claim 3 .

6. 2. The semiconductor device of claim 1, wherein the delay applied to the gate-source voltage of the first LS transistor is a programmable delay.

7. 2. The semiconductor device according to claim 1, wherein a rising edge of a gate-source voltage of said first LS transistor is aligned with a rising edge of said first signal at said specific time.

8. A semiconductor device comprising: a comparator configured to generate a first signal indicative of a voltage at a node between a first high side (HS) transistor and a first low side (LS) transistor in the switching converter going below ground; a delay circuit configured to delay a gate-to-source voltage of a second LS transistor in the switching converter to generate a second signal; An OR gate, combining the first signal and the second signal to generate a third signal; an OR gate configured to send the third signal to a controller to trigger a rising edge of a command signal to turn on the first LS transistor at a particular time; Including, the first LS transistor being turned on at the particular time reduces a diode conduction time of a body diode of the first LS transistor; Semiconductor device.

9. The semiconductor device according to claim 8 , wherein the switching converter is provided in a listener of a power transmission system using near field communication (NFC).

10. the delay circuit is a first delay circuit, a second delay circuit configured to delay a gate-source voltage of the first LS transistor to generate a fourth signal; an arbiter configured to arbitrate between the first signal and the fourth signal; A counter, generating a delay signal based on arbitration between the first signal and the fourth signal; a counter configured to send the delay signal to the controller to adjust a delay applied to a gate-to-source voltage of the second LS transistor; Further comprising: Adjusting the delay adjusts the specific time. The semiconductor device according to claim 8.

11. 11. The semiconductor device according to claim 10, wherein the delay applied to the gate-source voltage of the first LS transistor is a fixed delay.

12. The semiconductor device according to claim 11 , wherein the fixed delay corresponds to a propagation delay of the comparator.

13. The counter is generating the delay signal to decrease the delay in response to an arbitration indicating that the first signal arrives at the arbiter before the fourth signal; configured to generate the delay signal to increase the delay in response to arbitration indicating that the fourth signal arrives at the arbiter before the first signal. The semiconductor device according to claim 10.

14. 9. The semiconductor device of claim 8, wherein the delay applied to the gate-source voltage of the second LS transistor is a programmable delay.

15. 9. The semiconductor device according to claim 8, wherein a rising edge of a gate-source voltage of said first LS transistor is aligned with a rising edge of said first signal at said specific time.

16. 1. A method for operating a wireless power transmission device, comprising: generating a first signal indicating that a voltage at a node between a first high side (HS) transistor and a first low side (LS) transistor in a switching converter is below ground; delaying a gate-to-source voltage of a second LS transistor in the switching converter to generate a second signal; combining the first signal and the second signal to generate a third signal; using the third signal to trigger a rising edge of a command signal to turn on the first LS transistor at a specific time; Including, the first LS transistor being turned on at the particular time reduces a diode conduction time of a body diode of the first LS transistor; method.

17. The method of claim 16 , wherein the switching converter is provided in a listener of a near field communication (NFC) power transfer system.

18. delaying a gate-source voltage of the first LS transistor to generate a fourth signal; generating a delayed signal based on arbitration between the first signal and the fourth signal; using the delay signal to adjust a delay applied to a gate-to-source voltage of the second LS transistor; Further comprising: Adjusting the delay adjusts the specific time.

17. The method of claim 16.

19. generating the delay signal to decrease the delay in response to an arbitration indicating that the first signal arrives at the arbiter before the fourth signal; generating the delay signal to increase the delay in response to an arbitration indicating that the fourth signal arrives at the arbiter before the first signal; 20. The method of claim 18.

20. 20. The method of claim 18, wherein a rising edge of a gate-to-source voltage of the first LS transistor aligns with a rising edge of the first signal at the particular time.

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