Image sensor

Abstract

To provide an image sensor having high performance and reliability.SOLUTION: An image sensor 100 has: a substrate; a first pixel PX1 arranged in the substrate and including first photoelectric conversion regions; a second pixel adjacent to the first pixel in a first horizontal direction X parallel to the substrate and the first pixel X and including second photoelectric conversion regions; a pixel isolation structure 140 extending within the substrate in a direction Z perpendicular to the circuit board, surrounding each of the pixels, and arranged between the pixels; a first floating diffusion region FD1 arranged adjacent to the substrate within the first pixel; a second floating diffusion region arranged adjacent to the substrate within the second pixel; and a first embedded connect 160 passing through an insulating layer 111 and an insulating layer 112, in contact with the first floating diffusion region and the second floating diffusion region, including a top face and a bottom face that are arranged within the substrate, having the top face located at a higher vertical level than a top face of the insulating layer, and located at an equivalent level to or higher vertical level than a bottom face of the insulating layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors that include photodiodes. [Background technology]

[0002] An image sensor is a device that converts an optical image signal into an electrical signal. The image sensor includes a number of pixels, each of which includes a photodiode region, that receives incident light and converts it into an electrical signal.

[0003] As the integration density of image sensors increases, the size of each pixel becomes smaller, and the electrical connection components of the pixel circuit for driving each pixel also become smaller, which can result in noise generation or a reduction in photoelectric conversion efficiency, such as conversion gain. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor with improved performance and reliability. [Means for solving the problem]

[0005] The image sensor according to the present invention, which has been made to achieve the above object, includes a substrate having a front surface and a rear surface facing each other, a first pixel disposed within the substrate and including a first photoelectric conversion region, a second pixel disposed within the substrate adjacent to the first pixel in a first horizontal direction parallel to the front surface of the substrate and including a second photoelectric conversion region, a pixel separating structure extending within the substrate in a vertical direction perpendicular to the front surface of the substrate, surrounding the first pixel and the second pixel, and disposed between the first pixel and the second pixel, and a first floating pixel disposed within the first pixel and adjacent to the front surface of the substrate. a diffusion region, a second floating diffusion region disposed within the second pixel adjacent to the front surface of the substrate, an insulating layer disposed on the front surface of the substrate, and a first buried connect penetrating the insulating layer and connecting to the first floating diffusion region and the second floating diffusion region, the first buried connect including an upper surface and a lower surface disposed within the substrate, the upper surface of the first buried connect being located at a vertical level higher than an upper surface of the insulating layer, and the upper surface of the first buried connect being located at the same vertical level as or higher than a lower surface of the insulating layer.

[0006] In addition, an image sensor according to an embodiment of the present invention includes a substrate having a front surface and a back surface facing each other, a first pixel disposed in the substrate and including a first photoelectric conversion region, a second pixel adjacent to the first pixel in the substrate in a first horizontal direction and including a second photoelectric conversion region, a pixel separating structure extending vertically from within the substrate to surround the first pixel and the second pixel and to be disposed between the first pixel and the second pixel, a first floating diffusion region disposed in the first pixel adjacent to the front surface of the substrate, a second floating diffusion region disposed in the second pixel adjacent to the front surface of the substrate, an insulating layer disposed on the front surface of the substrate, and a buried connect penetrating the insulating layer and connected to the first floating diffusion region and the second floating diffusion region, wherein a top of a lower surface of the buried connect is located at the same vertical level as or higher than a lower surface of the insulating layer, and an upper surface of the buried connect is located at a vertical level higher than the front surface of the substrate.

[0007] In addition, an image sensor according to an embodiment of the present invention includes a substrate having a front surface and a rear surface facing each other; a first pixel disposed in the substrate and including a plurality of first photoelectric conversion regions; a second pixel adjacent to the first pixel in a first horizontal direction within the substrate and including a plurality of second photoelectric conversion regions; a third pixel adjacent to the first pixel in a second horizontal direction intersecting the first horizontal direction within the substrate and including a plurality of third photoelectric conversion regions; a fourth pixel adjacent to the second pixel in the second horizontal direction within the substrate and including a plurality of fourth photoelectric conversion regions; a pixel separating structure extending vertically from within the substrate, surrounding each of the first pixel, the second pixel, the third pixel, and the fourth pixel, and extending in the first horizontal direction and the second horizontal direction; a first floating diffusion region disposed adjacent to the front surface of the substrate within the first pixel and shared by the plurality of first photoelectric conversion regions; a second floating diffusion region shared by a plurality of second photoelectric conversion regions; a third floating diffusion region disposed adjacent to the front surface of the substrate in the third pixel and shared by the plurality of third photoelectric conversion regions; a fourth floating diffusion region disposed adjacent to the front surface of the substrate in the fourth pixel and shared by the plurality of fourth photoelectric conversion regions; an insulating layer disposed on the front surface of the substrate; a buried connect including a portion penetrating the insulating layer and buried in the substrate, the buried connect contacting the first floating diffusion region to the fourth floating diffusion region; and a color filter and a lens disposed on the back surface of the substrate, wherein the buried connect comprises a material having an etching selectivity with the insulating layer, and a top of the lower surface of the buried connect is located at the same vertical level as or higher than a lower surface of the insulating layer, and an upper surface of the buried connect is located at a vertical level higher than the front surface of the substrate. Effect of the Invention

[0008] According to the image sensor of the present invention, a buried connect is included, and the buried connect connects the floating active regions of adjacent pixels separated by a pixel separating structure, thereby eliminating the need to form contacts separately connected to the floating active regions of adjacent pixels or reducing the number of contacts required, and reducing capacitance due to the contacts, thereby improving noise and photoelectric conversion efficiency, such as conversion gain. [Brief description of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a layout diagram showing an image sensor corresponding to one pixel in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line BB in FIG. 2. [Diagram 5] FIG. 5 is an enlarged cross-sectional view of an EX1 region in FIG. [Figure 6] 2 is an equivalent circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 7] FIG. 2 is a layout diagram illustrating an image sensor according to an embodiment of the present invention. [Figure 8] FIG. 2 is a layout diagram illustrating an image sensor according to an embodiment of the present invention. [Figure 9] FIG. 2 is a layout diagram illustrating an image sensor according to an embodiment of the present invention. [Figure 10] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view taken along line CC in FIG. [Figure 12] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 13]1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention. [Figure 17] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Next, a specific example of an embodiment of an image sensor according to the present invention will be described with reference to the drawings. The same components in the drawings are denoted by the same reference numerals, and duplicated explanations thereof will be omitted. The present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and the embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is only defined by the scope of the claims.

[0011] It will be understood that although first, second, etc. may be used to describe various elements, components and / or sections, the elements, components and / or sections are not limited by these terms. The terms used are merely used to distinguish one element, component or section from another element, component or section. Therefore, it goes without saying that a first element, a first component, or a first section referred to below is also a second element, a second component, or a second section within the technical spirit of the present invention. The terms used in the present specification are intended to describe the embodiments and are not intended to limit the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning that can be commonly understood by a person having ordinary skill in the art to which this invention belongs. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless expressly and specifically defined. Herein, items described in the singular may be provided in plural as shown in the drawings, and thus a description of a singular item provided in plural should be understood to apply to the remaining plural items, unless the context clearly indicates otherwise.

[0012] FIG. 1 is an oblique view showing a schematic configuration of an image sensor 100 according to an embodiment of the present invention, FIG. 2 is a layout diagram showing the image sensor 100 corresponding to one pixel PX in FIG. 1, FIG. 3 is a cross-sectional view taken along line AA in FIG. 2, FIG. 4 is a cross-sectional view taken along line BB in FIG. 2, and FIG. 5 is an enlarged cross-sectional view of the EX1 region in FIG. 4. 1 to 5, the image sensor 100 is a stacked type image sensor in which a first stack ST1, a second stack ST2, and a third stack ST3 are stacked in the vertical direction.

[0013] The active pixel region APR is disposed in the center of the image sensor 100, and a plurality of pixels PX are disposed in the active pixel region APR. The multiple pixels PX are regions that receive light from outside the image sensor 100 and convert it into an electrical signal. A plurality of pixels PX are arranged in a first stack ST1 and a second stack ST2, and for example, a photoelectric conversion region PD for receiving external light is arranged in the first stack ST1, and transistors constituting a pixel circuit PXC for converting photocharges accumulated in the photoelectric conversion region PD into an electrical signal are arranged in the second stack ST2. The pad region PDR is disposed on at least one side of the active pixel region APR, for example, on the four side surfaces of the active pixel region APR in a plan view. A plurality of pads PAD are arranged in the pad region PDR, and are configured to transmit and receive electrical signals to and from an external device or the like.

[0014] The peripheral circuit region PCR includes a logic circuit block and / or a memory element. For example, the logic circuit block includes a plurality of logic transistors LCT and provides a constant signal to each pixel PX in the active pixel area APR or controls an output signal at each pixel PX. For example, the logic transistor LCT may include at least one of a row decoder, a row driver, a column decoder, a timing generator, a correlated double sampler (CDS), an analog to digital converter, and an input / output buffer (I / O buffer). The active pixel region APR includes a plurality of pixels PX, and a plurality of photoelectric conversion regions PD are arranged within each of the plurality of pixels PX. In the active pixel region APR, a plurality of pixels PX are arranged in a matrix with columns and rows along a first direction X parallel to the top surface of the first semiconductor substrate 110 and a second direction Y parallel to the top surface of the first semiconductor substrate 110 and perpendicular to the first direction. Some of the pixels PX are optical black pixels (not shown). The optical black pixel serves as a reference pixel for the active pixel area APR and performs a function for automatically correcting the dark signal.

[0015] As used herein, terms such as "identical," "same," "planar," "coplanar," "parallel," and "perpendicular" include identity or similarity, including variations that may occur, for example, due to the manufacturing process. In this specification, the term "substantially" is used to emphasize the meaning, unless the context or other statements indicate otherwise.

[0016] In some example embodiments, as illustrated in FIG. 2, a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4 are arranged in a matrix. Each of the first to fourth pixels (PX1, PX2, PX3, PX4) in the first stack ST1 has a photoelectric conversion region FD and a floating diffusion region FD. For example, a first pixel PX1 has a first photoelectric conversion region PD1 and a first floating diffusion region FD1. The second pixel PX2 has a second photoelectric conversion region PD2 and a second floating diffusion region FD2. The third pixel PX3 has a third photoelectric conversion region PD3 and a third floating diffusion region FD3. The fourth pixel PX4 has a fourth photoelectric conversion region PD4 and a fourth floating diffusion region FD4.

[0017] In the exemplary embodiment, two photoelectric conversion regions PD are arranged in one pixel PX. For example, the first pixel PX1 has two first photoelectric conversion regions PD1. For example, the second pixel PX2 has two second photoelectric conversion regions PD2. For example, the third pixel PX3 has two third photoelectric conversion regions PD3. For example, the fourth pixel PX4 has two fourth photoelectric conversion regions PD4.

[0018] The first stack ST1 includes a first semiconductor substrate 110 having a front surface 110F and a back surface 110B, a photoelectric conversion region PD and a floating diffusion region FD formed inside the first semiconductor substrate 110, a dual transmission gate 150 disposed on the front surface 110F of the first semiconductor substrate 110, and a first front surface structure FS1, and a color filter CF and a microlens ML disposed on the back surface 110B of the first semiconductor substrate 110. The second stack ST2 includes a second semiconductor substrate 120 having a front surface 120F and a back surface 120B, a pixel transistor PXT disposed on the front surface 120F of the second semiconductor substrate 120, a second front surface structure FS2, and a back surface structure BS2 disposed on the back surface 120B of the second semiconductor substrate 120. The third stack ST3 includes a third semiconductor substrate 130 having a front surface 130F, a logic transistor LCT disposed on the front surface 130F of the third semiconductor substrate 130, and a third front surface structure FS3.

[0019] The second stack ST2 is arranged between the first stack ST1 and the third stack ST3, and is arranged, for example, so that the second front structure FS2 of the second stack ST2 faces the first front structure FS1 of the first stack ST1, and so that the rear structure BS2 of the second stack ST2 faces the third front structure FS3 of the third stack ST3. In the exemplary embodiment, the first to third semiconductor substrates (110, 120, 130) include P-type semiconductor substrates. For example, at least one of the first to third semiconductor substrates (110, 120, 130) is made of a P-type silicon substrate. In an exemplary embodiment, at least one of the first to third semiconductor substrates (110, 120, 130) includes a P-type bulk substrate and a P-type or N-type epilayer grown thereon, and in another embodiment, includes an N-type bulk substrate and a P-type or N-type epilayer grown thereon.

[0020] A pixel separating structure 140 is disposed in the first semiconductor substrate 110 of the first stack ST1. A plurality of pixels PX are defined by pixel separating structure 140. The pixel separating structure 140 includes a conductive layer 142 , an insulating liner 144 , and a top insulating layer 146 . The conductive layer 142 is disposed within a pixel trench 140T that extends through the first semiconductor substrate 110. The insulating liner 144 is disposed on the inner wall of the pixel trench 140T penetrating the first semiconductor substrate 110 and extends from the front surface 110F to the second surface 110F2 of the first semiconductor substrate 110 and is interposed between the conductive layer 142 and the first semiconductor substrate 110. An upper insulating layer 146 is disposed within a portion of the pixel trench 140T adjacent to the front surface 110F of the first semiconductor substrate 110.

[0021] In the exemplary embodiment, the pixel separating structure 140 extends through the first semiconductor substrate 110 . For example, pixel isolation structure 140 is a Front-Side Deep Trench Isolation (FDTI). Unlike what is shown, pixel separating structure 140 may not extend all the way through first semiconductor substrate 110 . For example, the pixel isolation structure 140 can be a back-side deep trench isolation (BDTI). In an exemplary embodiment, the conductive layer 142 may include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing film.

[0022] The insulating liner 144 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The upper insulating layer 146 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. A plurality of photoelectric conversion regions PD are arranged in the first semiconductor substrate 110 of the first stack ST1 in each of the plurality of pixels PX. The photoelectric conversion region PD is a region doped with n-type impurities. For example, the photoelectric conversion region PD has an impurity concentration difference between the upper and lower portions and has a potential gradient. Alternatively, the photoelectric conversion region PD may be formed in a form in which a plurality of impurity regions are stacked in the vertical direction.

[0023] As illustrated in FIGS. 2 and 4, a floating diffusion region FD is disposed in an internal region of the first semiconductor substrate 110 adjacent to a front surface 110F of the first semiconductor substrate 110 of the first stack ST1. The floating diffusion region FD is a region in which charges transferred from the adjacent photoelectric conversion region PD are stored. In the exemplary embodiment, when two photoelectric conversion regions PD are arranged in one pixel PX, the floating diffusion region FD is shared by the two photoelectric conversion regions PD. That is, when one pixel PX includes two photoelectric conversion regions PD, the floating diffusion region FD is a region in which the charges transferred from the two photoelectric conversion regions PD of the pixel PX are stored.

[0024] For example, the first floating diffusion region FD1 of the first pixel PX1 is shared by two first photoelectric conversion regions PD1. The second floating diffusion region FD2 of the second pixel PX2 is shared by two second photoelectric conversion regions PD2. The third floating diffusion region FD3 of the third pixel PX3 is shared by two third photoelectric conversion regions PD3. The fourth floating diffusion region FD4 of the fourth pixel PX4 is shared by two fourth photoelectric conversion regions PD4. The first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4 are separated by a pixel separating structure 140.

[0025] A ground region (not shown) is disposed in an internal region of the first semiconductor substrate 110 adjacent to the front surface 110F of the first semiconductor substrate 110 of the first stack ST. As illustrated in FIGS. 2 and 3, a dual transmission gate 150 is disposed on the front surface 110F of the first semiconductor substrate 110 of the first stack ST. The dual transmission gate 150 includes a first portion (150_1), a second portion (150_2), and a third portion (150_3), the first portion (150_1) and the second portion (150_2) being disposed within a transmission gate trench 150T extending from a front surface 110F of the first semiconductor substrate 110 into the first semiconductor substrate 110, and the third portion (150_3) being disposed on the front surface 110F of the first semiconductor substrate 110. The third portion (150_3) is surrounded by a first insulating layer 111 and a second insulating layer 112 on the front surface 110F of the first semiconductor substrate 110. The third portion (150_3) is integrally connected to the first portion (150_1) and the second portion (150_2), and the third portion (150_3) overlaps at least a portion of the first portion (150_1) and the second portion (150_2) in the vertical direction Z.

[0026] In Figure 3, the front surface 110F of the first semiconductor substrate 110 is illustratively shown as being arranged downward toward the second stack ST2, and the back surface 110B of the first semiconductor substrate 110 is illustrated as being arranged upward, so that the third portion (150_3) is positioned at a vertical level lower than the front surface 110F of the first semiconductor substrate 110. For example, the vertical distance between the third portion 150_3 and the second stack ST2 is shorter than the vertical distance between the front surface 110F of the first semiconductor substrate 110 and the second stack ST2. Specifically, two dual transmission gates 150 are disposed corresponding to the two first photoelectric conversion regions PD1 of the first pixel PX1, respectively. The dual transmission gate 150 is adjacent to the front surface 110F of the first semiconductor substrate 110. The two dual transmission gates 150 corresponding to the two photoelectric conversion regions PD of the first pixel PX1 share the first floating diffusion region FD1 of the first pixel PX1.

[0027] In the exemplary embodiment, a transmission gate insulating layer 154 is disposed on the inner walls of the transmission gate trench 150T. A transfer gate insulating layer 154 is interposed between the transfer gate electrode 152 and the first semiconductor substrate 110 and has a relatively uniform thickness. In the exemplary embodiment, spacers 156 are disposed on the sidewalls of the transmission gate electrode 152 of the third portion (150_3) of the dual transmission gate 150 and are disposed on the front surface 110F of the first semiconductor substrate 110.

[0028] As illustrated in FIGS. 3 and 4, a first front surface structure FS1 is disposed on the front surface 110F of the first semiconductor substrate 110 of the first stack ST1. The first front surface structure FS1 includes a first insulating layer 111 and a second insulating layer 112 disposed on a front surface 110F of the first semiconductor substrate 110. For example, the first insulating layer 111 and the second insulating layer 112 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. For example, the first insulating layer 111 includes silicon oxide, and the second insulating layer 112 includes silicon nitride. Meanwhile, each of the first and second insulating layers (111, 112) is formed in a laminated structure of a plurality of insulating layers (not shown), and an additional insulating liner (not shown) is further disposed between each of the plurality of insulating layers.

[0029] As illustrated in FIG. 4, a buried connect 160 is arranged to penetrate the first insulating layer 111 and the second insulating layer 112 of the first front structure FS1 of the first stack ST and to connect to the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3. The term "embedded" means that a structure, pattern and / or layer is formed at least partially beneath the upper surface of another structure, pattern and / or layer. In some implementations, a first structure, pattern and / or layer is said to be "embedded" in a second structure, pattern and / or layer, where the second structure, pattern and / or layer surrounds at least a portion of the first structure, pattern and / or layer. For example, a first structure, pattern and / or layer is considered to be embedded when it is at least partially embedded in a second structure, pattern and / or layer.

[0030] Specifically, referring to FIG. 5, the buried connect 160 penetrates the first insulating layer 111 and the second insulating layer 112 and is buried inside the first semiconductor substrate 110 from the front surface 110F of the first semiconductor substrate 110. For example, the buried connect 160 includes a portion surrounded by the first insulating layer 111 and the second insulating layer 112 and a portion buried within the first semiconductor substrate 110 .

[0031] In an exemplary embodiment, the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3, which are adjacent in the second horizontal direction (Y direction), are spaced apart in the second horizontal direction (Y direction) across the pixel separating structure 140. In the exemplary embodiment, the first floating diffusion region FD1 and the third floating diffusion region FD3 of the third pixel PX3 are electrically connected by a buried connect 160. Specifically, the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3 are in contact with the buried connect 160 and are electrically connected thereto.

[0032] Herein, items described as "electrically connected" mean that they are configured to allow electrical signals to be transmitted from one item to the other item. Thus, when an electrically conductive component (e.g., a wire, pad, internal electrical trace, etc.) is physically connected to an insulating component (e.g., a prepreg layer in a printed circuit board, an electrically insulating adhesive connecting two devices, an electrically insulating underfill or mold layer, etc.), the components are not electrically connected. Additionally, an item that is "directly electrically connected" means that it is electrically connected through one or more components, such as a wire, a pad, an internal electrical line, or a through via. Thus, components that are directly electrically connected are not electrically connected through an active device such as a transistor or diode. Elements that are directly electrically connected are both directly physically connected and directly electrically connected.

[0033] In the exemplary embodiment, buried connect 160 overlaps pixel separating structure 140 vertically (in the Z direction). For example, buried connect 160 may include a portion that is buried toward a portion of pixel separating structure 140 adjacent to front surface 110F of first semiconductor substrate 110. In the exemplary embodiment, the buried connect 160 includes a portion that overlaps in the vertical direction (Z direction) with each of the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3. The buried connect 160 includes a portion disposed between the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3. The buried connect 160 includes a portion that overlaps in the second horizontal direction (Y direction) with the first floating diffusion region FD1 of the first pixel PX1 and the third floating diffusion region FD3 of the third pixel PX3.

[0034] In the exemplary embodiment, the buried connect 160 includes an upper surface (160_1) disposed within the first semiconductor substrate 110 and a lower surface (160_2) opposite the upper surface (160_1). The first insulating layer 111 includes an upper surface (111_1) facing the front surface 110F of the first semiconductor substrate 110. The second insulating layer 112 includes an upper surface (111_1) of the first insulating layer 111 and a lower surface (112_1) opposite thereto. The upper surface (111_1) of the first insulating layer 111 is a contact surface with the front surface 110F of the first semiconductor substrate 110. The lower surface (112_1) of the second insulating layer 112 is a contact surface with the third insulating layer 113. The upper surface (160_1) of the buried connect 160 is located at a higher vertical level than the upper surface (111_1) of the first insulating layer 111. The upper surface (160_1) of the buried connect 160 is located at a higher vertical level than the front surface 110F of the first semiconductor substrate 110. In this specification, being located at a high vertical level means being located at an even higher vertical level in the +Z direction.

[0035] The lower surface (160_2) of the buried connect 160 is located at the same vertical level as the lower surface (112_1) of the second insulating layer 112 or at a higher vertical level. Specifically, the lower surface (160_2) of the buried connect 160 includes a portion located at the same vertical level as the lower surface (112_1) of the second insulating layer 112. Specifically, the lower surface (160_2) of the buried connect 160 includes a portion located at a higher vertical level than the lower surface (112_1) of the second insulating layer 112. In the exemplary embodiment, the lower surface (160_2) of the embedded connect 160 includes a recessed portion (160_2R). Specifically, the recessed portion (160_2R) of the buried connect 160 is recessed inside the buried connect 160. For example, the recessed portion (160_2R) of the lower surface (160_2) of the embedded connect 160 is recessed toward the upper surface (160_1).

[0036] In the exemplary embodiment, the recessed portion (160_2R) of the buried connect 160 overlaps the pixel separating structure 140 in the vertical direction (Z direction). Unlike the one shown in the figure, the buried connect 160 does not include a recessed portion (160_2R), and the lower surface (160_2) of the buried connect 160 may be located at the same vertical level as the lower surface (112_1) of the second insulating layer 112. The lower surface (160_2) of the buried connect 160 is located at a lower vertical level than the upper surface (111_1) of the first insulating layer 111. The lower surface (160_2) of the buried connect 160 is located at a lower vertical level than the front surface 110F of the first semiconductor substrate 110. The lower surface (160_2) of the buried connect 160 is located at a lower vertical level than the upper surface of the second insulating layer 112.

[0037] In the exemplary embodiment, the buried connect 160 has a corresponding etch selectivity with respect to the first insulating layer 111 and the second insulating layer 112, respectively. For example, buried connect 160 may include a material that has an etch selectivity with silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. For example, buried connect 160 may include polysilicon and / or doped polysilicon. For example, the buried connect 160 may include a metal such as W and / or Cu.

[0038] As illustrated in FIG. 2, the buried connect 160 overlaps vertically (in the Z direction) with the first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4. As described above, the buried connect 160 is connected to the first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4. The buried connect 160 contacts and is electrically connected to the first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4.

[0039] 3 and 4, the first front structure FS1 further includes a third insulating layer 113 and a fourth insulating layer 114 disposed on the first insulating layer 111 and the second insulating layer 112. The first front structure FS1 further includes a conductive via 116 penetrating the third insulating layer 113, and a wiring layer 117 and a via 119 disposed within the fourth insulating layer 114. In an exemplary embodiment, a contact 170 (see FIG. 2) that penetrates the third insulating layer 113 is disposed on the buried connect 160 that penetrates the first insulating layer 111 and the second insulating layer 112 . The contact 170 connects the buried connect 160 to the wiring layer 117 and the via 119 disposed inside the fourth insulating layer 114 . As described above, the buried connect 160 comes into contact with the first floating diffusion region FD1 to the fourth floating diffusion region FD4, so that the contact 170 is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4.

[0040] A second front surface structure FS2 is disposed on the front surface 120F of the second semiconductor substrate 120 of the second stack ST2. The second front surface structure FS2 includes a first insulating layer 121 and a second insulating layer 122 disposed on the front surface 120F of the second semiconductor substrate 120. The first insulating layer 121 covers the pixel transistor PXT disposed on the front surface 120F of the second semiconductor substrate 120. The second front structure FS2 further includes a conductive via 126 penetrating the first insulating layer 121, and a wiring layer 127 and a via 129 disposed within the second insulating layer 122. The conductive via 126, the wiring layer 127, and the via 129 are arranged to be electrically connected to the pixel transistor PXT. In an exemplary embodiment, the pixel transistor PXT includes a reset transistor RX, a selection transistor SX, and a source follower transistor SFX (see FIG. 6).

[0041] A back surface structure BS2 is disposed on the back surface 120B of the second semiconductor substrate 120 of the second stack ST2. The backside structure BS2 includes a third insulating layer 123 disposed on the backside surface 120B of the second semiconductor substrate 120. A third front surface structure FS3 is disposed on the front surface 130F of the third semiconductor substrate 130 of the third stack ST3. The third front surface structure FS3 includes a first insulating layer 131 and a second insulating layer 132 disposed on the front surface (130F) of the third semiconductor substrate 130. The first insulating layer 131 covers the logic transistor LCT disposed on the front surface 130F of the third semiconductor substrate 130. The third front structure FS3 further includes a conductive via 136 penetrating the first insulating layer 131, and a wiring layer 137 and a via 139 disposed within the second insulating layer 132. The conductive via 136, the wiring layer 137, and the via 139 are arranged to be electrically connected to the logic transistor LCT.

[0042] In an exemplary embodiment, the conductive vias (116, 126, 136), the wiring layers (117, 127, 137), and the vias (119, 129, 139) may include at least one of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), and tungsten nitride (WN).

[0043] As illustrated in FIGS. 3 and 4, the second stack ST2 is disposed so that the second front structure FS2 faces the first front structure FS1 of the first stack ST1. A first bonding layer BI1 is disposed between the first front structure FS1 and the second front structure FS2. The second stack ST2 is disposed so that the rear structure BS2 faces the third front structure FS3 of the third stack ST3. A second bonding layer BI2 is disposed between the rear structure BS1 and the third front structure FS3. Each of the first bonding layer BI1 and the second bonding layer BI2 is made of a stacked structure of multiple insulating layers, and may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0044] In the exemplary embodiment, a first bonding pad BP1 is disposed at the boundary between the first stack ST1 and the second stack ST2. The first bonding pad BP1 is surrounded by the first bonding layer BI1. The first bonding pad BP1 includes an upper pad portion in the first stack ST1 and a lower pad portion in the second stack ST2, and the upper pad portion and the lower pad portion are arranged to vertically overlap each other and adhere to each other. For example, an interface between the upper pad portion and the lower pad portion, for example a bonding interface, is disposed between the first front structure FS1 and the second front structure FS2. The first bonding pad BP1 may include copper. For example, the first stack ST1 and the second stack ST2 are laminated by a metal-oxide hybrid bonding method. In the exemplary embodiment, a second bonding pad BP2 is disposed at the boundary between the second stack ST2 and the third stack ST3. The second bonding pad BP2 is surrounded by a second bonding layer BI2. The second stack ST2 and the third stack ST3 are laminated by a metal-oxide hybrid bonding method. The second bonding pad BP2 may include copper.

[0045] In accordance with an embodiment of the present teachings, an image sensor 100 is provided that includes a buried connect 160 . The buried connects 160 connect the floating active areas FD of adjacent pixels PX that are spaced apart with a pixel separating structure 140 therebetween. Therefore, it is not necessary to form contacts separately connected to the floating active regions FD of the adjacent pixels PX, or the number of contacts required is reduced, thereby reducing capacitance due to the contacts. This improves photoelectric conversion efficiency, such as noise and conversion gain. That is, the embodiment according to the technical concept of the present invention provides an image sensor 100 with improved performance and reliability.

[0046] FIG. 6 is an equivalent circuit diagram of a pixel of the image sensor 100 according to an embodiment of the present invention. Referring to FIG. 6, a plurality of pixels PX are arranged in a matrix. Each of the plurality of pixels PX includes a transmission transistor TX and a pixel transistor (not shown). Here, the pixel transistors include a reset transistor RX, a selection transistor SX, and a source follower transistor SFX. The reset transistor RX includes a reset gate RG, the selection transistor SX includes a selection gate SG, the source follower transistor SFX includes a source follower gate (not shown), and the transmission transistor TX includes a transmission gate TG. The transmission gate TG corresponds to the dual transmission gate 150 described in FIGS.

[0047] Each of the plurality of pixels PX further includes a photoelectric conversion region PD and a floating diffusion region FD. The photoelectric conversion region PD corresponds to the photoelectric conversion region PD described with reference to FIGS. The photoelectric conversion region PD generates and accumulates photocharges in proportion to the amount of light incident from the outside, and may be a photodiode, a phototransistor, a photogate, a Pinned Photo Diode (PPD), or a combination thereof.

[0048] In the exemplary embodiment, each of the plurality of pixels PX includes two photoelectric conversion regions PD, two transfer transistors TX, and one floating diffusion region FD. The transmission gate TG transmits the charge generated in the photoelectric conversion region PD to the floating diffusion region FD. For example, each of the two transmission gates TG in one pixel PX transmits the charges generated in each of the two photoelectric conversion regions PD to the floating diffusion region FD. The floating diffusion region FD transfers and accumulates the charges generated in the photoelectric conversion region PD. The source follower transistor SFX is controlled by the amount of photocharge accumulated in the floating diffusion region FD.

[0049] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode is connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged and the floating diffusion region FD is reset.

[0050] The source follower transistor SFX is connected to a current source (not shown) located outside the multiple pixels PX and functions as a source follower buffer amplifier, amplifying the potential change at the floating diffusion region FD and outputting it to the output line VOUT. The selection transistor SX selects a plurality of pixels PX in units of a row, and when the selection transistor SX is turned on, the power supply voltage VDD is transmitted to the source electrode of the source follower transistor SFX.

[0051] 7 to 9 are layout diagrams showing image sensors (101, 102, 103) according to embodiments of the present invention. The following describes the differences from the image sensor 100 described with reference to FIGS. Referring to FIG. 7, the image sensor 101 includes a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Similar to the image sensor 100 described with reference to Figures 1 to 6, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the image sensor 101 each include two photoelectric conversion regions PD, and the two photoelectric conversion regions PD share one floating diffusion region FD.

[0052] In an exemplary embodiment, a first buried connect (161_1) is arranged to overlap in the vertical direction (Z direction) with a first floating diffusion region FD1 of a first pixel PX1 and a third floating diffusion region FD3 of a third pixel PX3 adjacent in a second horizontal direction (Y direction). Similarly, a second buried connect (161_2) is arranged to overlap in the vertical direction (Z direction) with the second floating diffusion region FD2 of the second pixel PX2 and the fourth floating diffusion region FD4 of the fourth pixel PX4 adjacent in the second horizontal direction (Y direction). The first buried connect (161_1) is connected to the first floating diffusion region FD1 and the third floating diffusion region FD3. The first buried connect (161_1) contacts the first floating diffusion region FD1 and the third floating diffusion region FD3.

[0053] The second buried connect (161_2) is connected to the second floating diffusion region FD2 and the fourth floating diffusion region FD4. The second buried connect (161_2) contacts the second floating diffusion region FD2 and the fourth floating diffusion region FD4. Unlike image sensor 100 which includes a buried connect 160 connected to all of the first floating diffusion region FD1 to the fourth floating diffusion region FD4, image sensor 101 may include two buried connects (161_1, 161_2) each connected to two floating diffusion regions FD.

[0054] A first contact (171_1) is disposed on the first buried connect (161_1). The first contact (171_1) is connected to the first floating diffusion region FD1 and the third floating diffusion region FD3 by the first buried connect (161_1). A second contact (171_2) is disposed on the second buried connect (161_2). The second contact (171_2) is connected to the second floating diffusion region FD2 and the fourth floating diffusion region FD4 by the second buried connect (161_2).

[0055] Referring to FIG. 8, the image sensor 102 includes a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Unlike the image sensor 100 described with reference to Figures 1 to 6, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the image sensor 102 each include one photoelectric conversion region PD and one floating diffusion region FD.

[0056] In an exemplary embodiment, an embedded connect 162 is arranged to overlap vertically (Z direction) with the first floating diffusion region FD1 of the first pixel PX1, the second floating diffusion region FD2 of the second pixel PX2, the third floating diffusion region FD3 of the third pixel PX3, and the fourth floating diffusion region FD4 of the fourth pixel PX4. The buried connect 162 is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4. The buried connect 162 contacts the first floating diffusion region FD1 to the fourth floating diffusion region FD4. A contact 172 is disposed on the buried connect 162 . The contact 172 is connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 by the buried connect 162.

[0057] Referring to FIG. 9, the image sensor 102 includes a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the image sensor 102 includes one photoelectric conversion region PD and one floating diffusion region FD.

[0058] In an exemplary embodiment, a first buried connect (163_1) is arranged to overlap in the vertical direction (Z direction) with a first floating diffusion region FD1 of a first pixel PX1 and a third floating diffusion region FD3 of a third pixel PX3 adjacent in a second horizontal direction (Y direction). Similarly, a second buried connect (163_2) is arranged to overlap in the vertical direction (Z direction) with the second floating diffusion region FD2 of the second pixel PX2 and the fourth floating diffusion region FD4 of the fourth pixel PX4 adjacent in the second horizontal direction (Y direction). The first buried connect (163_1) is connected to the first floating diffusion region FD1 and the third floating diffusion region FD3. The first buried connect (163_1) contacts the first floating diffusion region FD1 and the third floating diffusion region FD3.

[0059] The second buried connect (163_2) is connected to the second floating diffusion region FD2 and the fourth floating diffusion region FD4. The second buried connect (163_2) contacts the second floating diffusion region FD2 and the fourth floating diffusion region FD4. A first contact (173_1) is disposed on the first buried connect (163_1). The first contact (173_1) is connected to the first floating diffusion region FD1 and the third floating diffusion region FD3 by the first buried connect (163_1). A second contact (173_2) is disposed on the second buried connect (163_2). The second contact (173_2) is connected to the second floating diffusion region FD2 and the fourth floating diffusion region FD4 by the second buried connect (163_2).

[0060] FIG. 10 is a perspective view showing a schematic configuration of an image sensor 200 according to an embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line CC in FIG. The following describes the differences from the image sensor 100 described with reference to FIGS. 10 and 11, the image sensor 200 is a stacked type image sensor in which a first stack ST21 and a second stack ST22 are stacked in the vertical direction.

[0061] In the exemplary embodiment, the first stack ST21 includes a plurality of pixels PX, a photoelectric conversion region PD, and a plurality of pixel transistors. The peripheral circuit region PCR is disposed in the second stack ST22 and includes a logic circuit block and / or a memory element. For example, a logic circuit block may include a plurality of logic transistors LCT. The first stack ST21 includes a first semiconductor substrate 210, a first front structure FS21 arranged on a first surface 210F of the first semiconductor substrate 210, a color filter CF arranged on a second surface 210B of the first semiconductor substrate 210, and a microlens ML. The second stack ST22 includes a second semiconductor substrate 220 and a second front structure FS22 disposed on the first surface 220F of the second semiconductor substrate 220. For example, the second front structure FS22 in the second stack ST22 is disposed to face the first front structure FS21 in the first stack ST21 and to be in contact with each other.

[0062] In the exemplary embodiment, the first front surface structure FS1 includes a first insulating layer 111 and a second insulating layer 112 disposed on the front surface 110F of the first semiconductor substrate 110. The first front structure FS21 further includes a third insulating layer 213 and a fourth insulating layer 214 disposed on the first insulating layer 211 and the second insulating layer 212. The first front structure FS21 further includes a wiring layer 217 disposed within the fourth insulating layer 214. The second front structure FS22 includes a first insulating layer 221 and a second insulating layer 222 disposed on the first surface 220F of the second semiconductor substrate 220. The first insulating layer 221 covers the logic transistor LCT disposed on the first surface 220F of the second semiconductor substrate 220. The second front structure FS22 further includes a conductive via 226 penetrating the first insulating layer 221 and a wiring layer 227 disposed inside the second insulating layer 222. The conductive via 226 and the wiring layer 227 are disposed so as to be electrically connected to the logic transistor LCT.

[0063] The first stack ST21 and the second stack ST22 are arranged so that the first front structure FS21 and the second front structure FS22 face each other, for example, so that the fourth insulating layer 412 of the first front structure FS21 contacts the second insulating layer 222 of the second front structure FS22. A pixel separating structure 240 is disposed in the first semiconductor substrate 210 of the first stack ST21. A pixel separating structure 240 defines a plurality of pixels PX. The pixel separating structure 240 includes a conductive layer 242 , an insulating liner 244 , and a top insulating layer 246 . A plurality of photoelectric conversion regions (not shown) are arranged in each of the first stacks ST21 in the plurality of pixels PX. For example, one or more photoelectric conversion regions are arranged in each pixel PX. A floating diffusion region FD is disposed in an internal region of the first semiconductor substrate 210 adjacent to the first surface 210F of the first semiconductor substrate 210 of the first stack ST21. The floating diffusion regions FD arranged in adjacent pixels PX are separated by a pixel separating structure 240 therebetween.

[0064] In the exemplary embodiment, the buried connect 260 passes through the first insulating layer 111 and the second insulating layer 112 and is connected to the floating diffusion region FD of each of the adjacent pixels PX. For example, the buried connect 260 is connected to the floating diffusion region FD of each of a plurality of pixels PX adjacent in a first horizontal direction (X direction) and / or a second horizontal direction (Y direction). The buried connect 260 overlaps the pixel separating structure 240 vertically (in the Z direction). For the description related to the embedded connect 260, please refer to the embedded connect 160 described with reference to FIGS.

[0065] 12 to 16 are cross-sectional views illustrating a method for manufacturing the image sensor 100 according to the embodiment of the present invention. Specifically, FIGS. 12 to 16 are cross-sectional views corresponding to the cross section taken along line BB in FIG.

[0066] Referring to FIG. 12, a pixel separating structure 140 and floating diffusion regions FD1 and FD3 are formed in a first semiconductor substrate 110. Next, a first insulating layer 111 and a second insulating layer 112 are formed on the front surface 110F of the first semiconductor substrate 110. The first insulating layer 111 and the second insulating layer 112 are formed on the front surface 110F of the first semiconductor substrate 110 with the front surface 110F of the first semiconductor substrate 110 facing upwards. Next, a hard mask film HM is formed on the first insulating layer 111 and the second insulating layer 112. In an exemplary embodiment, the hard mask film HM may be the one used in a previous process. For example, the hard mask film HM may not be a newly formed film but may be a film that has been reused after a previous process has been performed.

[0067] Referring to FIG. 13, a photomask film (not shown) is formed on the hard mask film HM, and the hard mask film HM, the first insulating layer 111, and the second insulating layer 112 are patterned to form a buried connect trench 160T. The hard mask film HM, the first insulating layer 111, the second insulating layer 112, and a portion of the floating diffusion regions (FD1, FD3) in the first semiconductor substrate 110 are etched to form a buried connect trench 160T. The buried connect trench 160T exposes portions of the floating diffusion regions (FD1, FD3). In the exemplary embodiment, a portion of pixel separating structure 140 is etched together. Next, the hard mask film HM is removed.

[0068] Referring to FIG. 14, a buried connect layer 160L is formed in the buried connect trench 160T and on the first insulating layer 111 and the second insulating layer 112. In the exemplary embodiment, the portion overlapping the buried connect trench 160T in the vertical direction (Z direction) has a concave shape toward the front surface 110F of the first semiconductor substrate 110.

[0069] Referring to FIG. 15, a portion of the buried connect layer 160L formed on the first insulating layer 111 and the second insulating layer 112 is removed to form the buried connect 160. Specifically, the step of removing a portion of the buried connect layer 160L is performed using a planarization step (Chemical Mechanical Polishing: CMP). The step of performing the planarization process includes stopping the planarization process if the first insulating layer 111 and the second insulating layer 112 are exposed during the step of removing the buried connect layer 160L. Thereby, the lower surface (160_2) of the buried connect 160 is located at the same vertical level as the lower surface (112_1) of the second insulating layer 112 or at a higher vertical level (higher vertical level in the +Z direction). In some other embodiments, removing a portion of the buried connect layer 160L may be performed using an etch-back process.

[0070] Referring to FIG. 16, a third insulating layer 113 is formed on the buried connect 160 and the second insulating layer 112, and a wiring layer 117, a via 119, and a fourth insulating layer 114 surrounding the wiring layer 117 and the via 119 are formed on the third insulating layer 113. Next, the first bonding layer BI1 and the first bonding pad BP1 are formed. Subsequent processes are then performed to form the image sensor 100 described with reference to FIGS.

[0071] According to the method for manufacturing the image sensor 100 described with reference to FIGS. 12 to 16, the buried connect 160 of the present invention is manufactured using the hard mask film HM used in the previous step. Therefore, it is possible to provide the image sensor 100 with a simplified manufacturing process.

[0072] FIG. 17 is a block diagram showing a schematic configuration of an image sensor 1100 according to an embodiment of the present invention. Referring to FIG. 17, an image sensor 1100 includes a pixel array 1110, a controller 1130, a row driver 1120, and a pixel signal processing unit 1140. The image sensor 1100 includes at least one of the image sensors (100, 101, 102, 103, 200) described in FIGS.

[0073] The pixel array 1110 includes a plurality of unit pixels arranged two-dimensionally, and each unit pixel includes a photoelectric conversion element. The photoelectric conversion element absorbs light to generate electric charges, and an electric signal (output voltage) based on the generated electric charges is provided to the pixel signal processor 1140 through a vertical signal line. The unit pixels included in the pixel array 1110 provide output voltages one at a time on a row basis, so that the unit pixels belonging to one row of the pixel array 1110 are simultaneously activated by a selection signal output by the row driver 1120. A unit pixel belonging to a selected row provides an output voltage according to the absorbed light to an output line of the corresponding column.

[0074] The controller 1130 controls the row driver 1120 to cause the pixel array 1110 to absorb light and accumulate charge, or to temporarily store the accumulated charge, and to output an electrical signal based on the stored charge to the outside of the pixel array 1110. The controller 1130 also controls the pixel signal processor 1140 to measure the output voltage provided by the pixel array 1110 .

[0075] The pixel signal processing unit 1140 includes a correlated double sampler (CDS) 1142 , an analog-to-digital converter (ADC) 1144 , and a buffer 1146 . The correlated double sampler 1142 samples and holds the output voltage provided by the pixel array 1110 . The correlated double sampler 1142 double samples a specific noise level and a level due to the generated output voltage, and outputs a level corresponding to the difference. Correlated double sampler 1142 also receives the ramp signals generated by ramp signal generator 1148, compares them with each other, and outputs the comparison result.

[0076] The analog-to-digital converter 1144 converts the analog signal corresponding to the level received from the correlated double sampler 1142 into a digital signal. The buffer 1146 latches the digital signals, and the latched signals are sequentially output to the outside of the image sensor 1100 and transferred to an image processor (not shown).

[0077] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0078] 100 Image Sensor 110 First semiconductor substrate 111 to 114 (1st to 4th) insulating layers 116 Conductive Via 117 Wiring layer 120 Second semiconductor substrate 121 First insulating layer 122 Second insulating layer 126 Conductive Via 127 Wiring layer 129 Beer 130 Third semiconductor substrate 131 First insulating layer 132 Second insulating layer 136 Conductive Via 139 Beer 140 pixel isolation structure 140T Pixel Trench 142 Conductive Layer 144 Insulating Liner 146 Upper insulating layer 150 Dual Transmission Gate 152 Transmission gate electrode 154 Transmission Gate Insulation Layer 156 Spacer 150T Transmission Gate Trench 160 Embedded Connect 170 Contacts APR Active Pixel Area BI1, BI2 (1st, 2nd) bonding layers BP1, BP2 (1st, 2nd) bonding pads BS1, BS2 rear structure CF Color Filter FD, FD1 to FD4 (1st to 4th) floating diffusion regions FS1~FS3, FS21~FS23 (1st~3rd) Front structure ML Micro Lens PAD PCR peripheral circuit area PD, PD1 to PD4 (1st to 4th) photoelectric conversion regions PDR Pad Area PX, PX1~PX4 (1st~4th) pixels PXT Pixel Transistor ST1~ST3, ST21~ST23 (1st~3rd) stacks

Claims

1. a substrate including opposing front and back surfaces; a first pixel disposed within the substrate and including a first photoelectric conversion region; a second pixel adjacent to the first pixel in the substrate in a first horizontal direction parallel to the front surface of the substrate, the second pixel including a second photoelectric conversion region; a pixel separating structure extending in the substrate in a vertical direction perpendicular to the front surface of the substrate, surrounding each of the first pixel and the second pixel, and disposed between the first pixel and the second pixel; a first floating diffusion region disposed within the first pixel adjacent the front surface of the substrate; a second floating diffusion region disposed within the second pixel adjacent the front surface of the substrate; an insulating layer disposed on the front side of the substrate; a first buried connect penetrating the insulating layer and connected to the first floating diffusion region and the second floating diffusion region; the first buried connect includes an upper surface and a lower surface disposed within the substrate; the top surface of the first buried connect is located at a vertical level higher than a top surface of the insulating layer; The top surface of the first buried connect is located at a vertical level that is the same as or higher than a bottom surface of the insulating layer.

2. 2. The image sensor of claim 1, wherein the first floating diffusion region and the second floating diffusion region are spaced apart in the first horizontal direction with the pixel separating structure therebetween.

3. the first buried connect contacts the first floating diffusion region and the second floating diffusion region; The image sensor of claim 2 , wherein the first floating diffusion region and the second floating diffusion region are electrically connected by the first buried connect.

4. The image sensor of claim 1 , wherein the top surface of the first buried connect is located at a lower vertical level than the top surface of the insulating layer.

5. The image sensor of claim 1 , wherein the first buried connect comprises a material having an etching selectivity with respect to the insulating layer.

6. The image sensor of claim 5 , wherein the first buried connect comprises polysilicon.

7. The image sensor of claim 1 , wherein the top surface of the first buried connect includes a portion that is recessed within the first buried connect.

8. 2. The image sensor of claim 1, wherein the first buried connect includes a portion that vertically overlaps the pixel separating structure between the first pixel and the second pixel.

9. a third pixel adjacent to the first pixel in a second horizontal direction intersecting the first horizontal direction within the substrate, the third pixel including a third photoelectric conversion region; a fourth pixel adjacent to the second pixel in the second horizontal direction within the substrate and including a fourth photoelectric conversion region; a third floating diffusion region disposed within the third pixel adjacent the first surface of the substrate; a fourth floating diffusion region disposed within the fourth pixel adjacent the front surface of the substrate; The image sensor of claim 1 , wherein the first buried connect is further connected to the third floating diffusion region and the fourth floating diffusion region.

10. a third pixel adjacent to the first pixel in a second horizontal direction intersecting the first horizontal direction within the substrate, the third pixel including a third photoelectric conversion region; a fourth pixel adjacent to the second pixel in the second horizontal direction within the substrate and including a fourth photoelectric conversion region; a third floating diffusion region disposed within the third pixel adjacent the front surface of the substrate; a fourth floating diffusion region disposed within the fourth pixel adjacent the front surface of the substrate; 2. The image sensor of claim 1, further comprising: a second buried connect passing through the insulating layer and contacting the third floating diffusion region and the fourth floating diffusion region.

Images