Transmitting circuit having equalization function and training system including the same
The transmission circuit with an equalization function addresses the signal quality deterioration issue in semiconductor devices by selecting main and auxiliary driving units for data transmission and equalization, respectively, thereby improving signal quality without additional circuitry.
Patent Information
- Application Number
- JP2024150427
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-07
- Filing Date
- 2024-09-02
- Publication Date
- 2025-05-19
AI Technical Summary
The quality of transmission signals deteriorates due to the deterioration of the ability to drive the transfer signal when using the Low-Tapped Termination (LTT) method in semiconductor devices.
A transmission circuit with an equalization function is implemented, which includes a plurality of driving units connected to input/output pads. At least one main driving unit is selected for data transmission, and at least one auxiliary driving unit is selected for equalization, using a driving strength and equalization control circuit to generate selection signals.
This solution improves the quality of transmission signals by implementing an equalization function without the need for an additional equalization circuit, thereby enhancing signal quality without increasing circuit area.
Smart Images
Figure 2025077991000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor circuit, and more particularly to a transmission circuit having an equalization function and a training system including the same.
Background Art
[0002] A semiconductor device performs a termination operation for impedance matching with the outside. The semiconductor device performs the termination operation by one of CTT (Center-Tapped Termination), LTT (Low-Tapped Termination), and HTT (High-Tapped Termination).
[0003] In a semiconductor device, speed and power consumption act as major factors affecting its performance. Therefore, the LTT (Low-Tapped Termination) method is mainly used to satisfy high-speed and low-power operations.
[0004] However, with the application of the LTT (Low-Tapped Termination) method, a problem occurs in that the quality of the transmission signal deteriorates due to the deterioration of the ability to drive the transfer signal.
Summary of the Invention
Problems to be Solved by the Invention
[0005] Embodiments of the present invention provide a transmission circuit having an equalization function for improving the quality of a transmission signal, and a training system including the same.
Means for Solving the Problems
[0006] Embodiments of the present invention include a plurality of driving units connected to input / output pads. Among the plurality of driving units, at least one main driving unit corresponding to a predetermined driving strength is selected to perform a data transmission operation, and among the remaining driving units excluding the main driving unit, at least one auxiliary driving unit is selected to perform an equalization operation.
[0007] Embodiments of the present invention include a data driver configured to include a plurality of driving units connected to input / output pads and having different driving strengths, and at least one of the plurality of driving units is selected as a main driving unit according to a first impedance control signal, and at least one of the remaining driving units excluding the main driving unit is selected as an auxiliary driving unit, a driving strength and equalization control circuit configured to generate a plurality of main / auxiliary selection signals according to a plurality of strength control signals, a plurality of equalization control signals, and input data, and a free driver configured to output a result of logically combining the plurality of main / auxiliary selection signals and a first impedance adjustment signal as the first impedance control signal.
[0008] Embodiments of the present invention include a semiconductor device configured to include a plurality of driving units connected to input / output pads. Among the plurality of driving units, at least one main driving unit corresponding to a predetermined driving strength is selected to perform a data transmission operation, and among the remaining driving units excluding the main driving unit, at least one auxiliary driving unit is selected to perform an equalization operation, and a host configured to write write data having a predetermined pattern to the semiconductor device and perform a training operation while changing the auxiliary driving unit among the plurality of driving units according to read data.
Effects of the Invention
[0009] This technology can improve the quality of the transmission signal by implementing an equalization function without another equalization circuit.
Brief Description of the Drawings
[0010]
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Modes for Carrying Out the Invention
[0011] Hereinafter, embodiments of the present invention will be described in more detail based on the accompanying drawings.
[0012] FIG. 1 is a diagram showing the configuration of a transmission circuit 100 according to an embodiment of the present invention.
[0013] Referring to FIG. 1, the transmission circuit 100 according to an embodiment of the present invention may include a serialization circuit 101, a driving strength selection circuit 103, a free driver 105, and a data driver 107.
[0014] The serialization circuit 101 can receive an input of parallel data (DIN) and output pull-up data (RDO) and pull-down data (FDO). The serialization circuit 101 can be configured to serialize the parallel data (DIN) to generate serial data, that is, pull-up data (RDO) and pull-down data (FDO).
[0015] The driving strength selection circuit 103 can receive inputs of pull-up data (RDO), pull-down data (FDO), and a plurality of preliminary selection signals (PU_CTRL<0:M>, PD_CTRL<0:M>), and output a plurality of pull-up selection signals (SELPU<0:M>) and a plurality of pull-down selection signals (SELPD<0:M>).
[0016] The free driver 105 can receive inputs of a plurality of pull-up selection signals (SELPU<0:M>), a plurality of pull-down selection signals (SELPD<0:M>), a first impedance adjustment signal (PU_TRIM<0:N>), and a second impedance adjustment signal (PD_TRIM<0:N>), and output a plurality of first impedance control signals (PUCD<0:M><0:N>) and a plurality of second impedance control signals (PDCD<0:M><0:N>). The first impedance adjustment signal (PU_TRIM<0:N>) and the second impedance adjustment signal (PD_TRIM<0:N>) can be generated from an impedance matching circuit (not shown) within a semiconductor device including the transmission circuit 100 according to an embodiment of the present invention. The impedance matching circuit can adjust the values of the first impedance adjustment signal (PU_TRIM<0:N>) and the second impedance adjustment signal (PD_TRIM<0:N>) to match a predetermined driving impedance based on the resistance value of an external resistor connected to an external resistor pad of the semiconductor device.
[0017] The data driver 107 may have its output terminal connected to the input / output pad 109. The data driver 107 can drive the input / output pad 109 by a plurality of first impedance control signals (PUCD<0:M><0:N>) and a plurality of second impedance control signals (PDCD<0:M><0:N>).
[0018] FIG. 2 is a diagram showing the configuration of the driving strength selection circuit 103 in FIG. 1.
[0019] Referring to FIG. 2, the driving strength selection circuit 103 may include a plurality of sub-circuits 103-1 to 103-8.
[0020] The first sub-circuit 103-1 can receive inputs of pull-up data (RDO) and a preliminary selection signal (PU_CTRL<0>) and generate a pull-up selection signal (SELPU<0>). The second sub-circuit 103-2 can receive inputs of pull-up data (RDO) and a preliminary selection signal (PU_CTRL<1>) and generate a pull-up selection signal (SELPU<1>). The third sub-circuit 103-3 can receive inputs of pull-up data (RDO) and a preliminary selection signal (PU_CTRL<2>) and generate a pull-up selection signal (SELPU<2>). The fourth sub-circuit 103-4 can receive inputs of pull-up data (RDO) and a preliminary selection signal (PU_CTRL<3>) and generate a pull-up selection signal (SELPU<3>).
[0021] The fifth sub-circuit 103-5 can receive the input of pull-down data (FDO) and a preliminary selection signal (PD_CTRL<0>) and generate a pull-down selection signal (SELPD<0>). The sixth sub-circuit 103-6 can receive the input of pull-down data (FDO) and a preliminary selection signal (PD_CTRL<1>) and generate a pull-down selection signal (SELPD<1>). The seventh sub-circuit 103-7 can receive the input of pull-down data (FDO) and a preliminary selection signal (PD_CTRL<2>) and generate a pull-down selection signal (SELPD<2>). The eighth sub-circuit 103-8 can receive the input of pull-down data (FDO) and a preliminary selection signal (PD_CTRL<3>) and generate a pull-down selection signal (SELPD<3>).
[0022] The first sub-circuit 103-1 can include a plurality of logic gates 111 to 115. The first logic gate 111 and the second logic gate 112 can latch pull-up data (RDO). The third logic gate 113 can invert and output the output of the first logic gate 111. The fourth logic gate 114 and the fifth logic gate 115 can output the result of performing a logical AND operation on the output of the third logic gate 113 and a preliminary selection signal (PU_CTRL<0>) as a pull-up selection signal (SELPU<0>). The first sub-circuit 103-1 can output the pull-up data (RDO) as the pull-up selection signal (SELPU<0>) only when the preliminary selection signal (PU_CTRL<0>) is activated at a high level, and can maintain the pull-up selection signal (SELPU<0>) at a low level regardless of the level of the pull-up data (RDO) when the preliminary selection signal (PU_CTRL<0>) is deactivated at a low level. The second sub-circuit 103-2 to the eighth sub-circuit 103-8 can have a circuit configuration similar to that of the first sub-circuit 103-1.
[0023] Figure 3 is a diagram showing the configuration of the free driver 105 in Figure 1.
[0024] Referring to FIG. 3, the free driver 105 can include a plurality of logic circuits 105-1 to 105-8.
[0025] The first logic circuit 105-1 can receive inputs of a pull-up selection signal (SELPU<0>) and a first impedance adjustment signal (PU_TRIM<0:N>), and output a first impedance control signal (PUCD0<0:N>). The first logic circuit 105-1 can be composed of an AND logic for performing an AND operation on the pull-up selection signal (SELPU<0>) and the first impedance adjustment signal (PU_TRIM<0:N>) and outputting the result. When the pull-up selection signal (SELPU<0>) is activated to a high level, the first logic circuit 105-1 can output the first impedance adjustment signal (PU_TRIM<0:N>) as the first impedance control signal (PUCD0<0:N>).
[0026] The second logic circuit 105-2 can receive the inputs of the pull-up selection signal (SELPU<1>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD1<0:N>). The third logic circuit 105-3 can receive the inputs of the pull-up selection signal (SELPU<2>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD2<0:N>). The fourth logic circuit 105-4 can receive the inputs of the pull-up selection signal (SELPU<3>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD3<0:N>). Similar to the first logic circuit 105-1, the second to fourth logic circuits 105-2 to 105-4 can include AND logic. When the corresponding signal among the pull-up selection signals (SELPU<1:3>) is activated to the high level, the second to fourth logic circuits 105-2 to 105-4 can output the first impedance adjustment signal (PU_TRIM<0:N>) as the corresponding signal among the first impedance control signals (PUCD<1:3><0:N>).
[0027] The fifth logic circuit 105-5 can receive the inputs of the pull-down selection signal (SELPD<0>) and the second impedance adjustment signal (PD_TRIM<0:N>) and output the second impedance control signal (PDCD0<0:N>). The fifth logic circuit 105-5 can be composed of AND logic for performing an AND operation on the pull-down selection signal (SELPD<0>) and the second impedance adjustment signal (PD_TRIM<0:N>) and outputting the result. When the pull-down selection signal (SELPD<0>) is activated to the high level, the fifth logic circuit 105-5 can output the second impedance adjustment signal (PD_TRIM<0:N>) as the second impedance control signal (PDCD0<0:N>).
[0028] The sixth logic circuit 105-6 can receive an input of a pull-down selection signal (SELPD<1>) and a second impedance adjustment signal (PD_TRIM<0:N>) and output a second impedance control signal (PDCD1<0:N>). The seventh logic circuit 105-7 can receive an input of a pull-down selection signal (SELPD<2>) and a second impedance adjustment signal (PD_TRIM<0:N>) and output a second impedance control signal (PDCD2<0:N>). The eighth logic circuit 105-8 can receive an input of a pull-down selection signal (SELPD<3>) and a second impedance adjustment signal (PD_TRIM<0:N>) and output a second impedance control signal (PDCD3<0:N>).
[0029] Similar to the fifth logic circuit 105-5, the sixth to eighth logic circuits 105-6 to 105-8 can include AND logic. When the corresponding signal among the pull-down selection signals (SELPD<1:3>) is activated to a high level, the sixth to eighth logic circuits 105-6 to 105-8 can output the second impedance adjustment signal (PD_TRIM<0:N>) as the corresponding signal among the second impedance control signals (PDCD<1:3><0:N>).
[0030] Figure 4 is a diagram showing the configuration of the data driver 107 in Figure 1.
[0031] Referring to Figure 4, the data driver 107 can include a plurality of driving units commonly connected with the input / output pad 109 via a node (ND1), that is, pull-up driving units 107-1 to 107-4 and pull-down driving units 107-5 to 107-8.
[0032] The pull-up driving units 107-1 to 107-4 can be designed to have different driving strengths, that is, different impedances, by a plurality of first impedance control signals (PUCD<0:3><0:N>). The first pull-up driving unit 107-1 can drive the input / output pad 109 using the first impedance set by the first impedance control signal (PUCD0<0:N>). The first impedance can be, for example, 600 Ω (ohm). The second pull-up driving unit 107-2 can drive the input / output pad 109 using the second impedance set by the first impedance control signal (PUCD1<0:N>). The second impedance can be, for example, 300 Ω (ohm). The third pull-up driving unit 107-3 can drive the input / output pad 109 using the third impedance set by the first impedance control signal (PUCD2<0:N>). The third impedance can be, for example, 150 Ω (ohm). The fourth pull-up driving unit 107-4 can drive the input / output pad 109 using the fourth impedance set by the first impedance control signal (PUCD3<0:N>). The fourth impedance can be, for example, 120 Ω (ohm).
[0033] Since the pull-up driving units 107-1 to 107-4 have similar circuit configurations to each other, among them, for example, the configuration of the first pull-up driving unit 107-1 will be described. The first pull-up driving unit 107-1 can include a plurality of transistors 121 whose source terminals are commonly connected to the power supply terminal, and a resistor 122 whose one end is connected to the node (ND1) and the other end is commonly connected to the drain terminals of the plurality of transistors 121. The first impedance control signal (PUCD0<0:N>) can be input bit by bit to the gate terminals of the plurality of transistors 121.
[0034] The pull-down driving units 107-5 to 107-8 can be designed to have different impedances from each other by a plurality of second impedance control signals (PDCD<0:3><0:N>). The first pull-down driving unit 107-5 can drive the input / output pad 109 using a first impedance set by the second impedance control signal (PDCD0<0:N>). The second pull-down driving unit 107-6 can drive the input / output pad 109 using a second impedance set by the second impedance control signal (PDCD1<0:N>). The third pull-down driving unit 107-7 can drive the input / output pad 109 using a third impedance set by the second impedance control signal (PDCD2<0:N>). The fourth pull-down driving unit 107-8 can drive the input / output pad 109 using a fourth impedance set by the second impedance control signal (PDCD3<0:N>).
[0035] Since the pull-down driving units 107-5 to 107-8 have similar circuit configurations to each other, among them, for example, the configuration of the first pull-down driving unit 107-5 will be described. The first pull-down driving unit 107-5 can include a plurality of transistors 131 whose source terminals are commonly connected to the ground terminal, and a resistor 132 whose one end is connected to a node (ND1) and the other end is commonly connected to the drain terminals of the plurality of transistors 131. The second impedance control signal (PDCD0<0:N>) can be input bit by bit to the gate terminals of the plurality of transistors 131.
[0036] FIG. 5 is a diagram showing the configuration of a transmission circuit 200 according to another embodiment of the present invention.
[0037] The transmission circuit 200 according to another embodiment of the present invention includes a plurality of driving units connected to an input / output pad. Among the plurality of driving units, at least one main driving unit corresponding to a predetermined driving strength is selected to perform a data transmission operation, and among the remaining driving units excluding the main driving unit, at least one auxiliary driving unit is selected to perform an equalization operation.
[0038] Referring to FIG. 5, the transmission circuit 200 according to another embodiment of the present invention can include a serialization circuit 201, a driving strength and equalization control circuit 203, a free driver 205, a data driver 207, and a control signal generation circuit 208.
[0039] The serialization circuit 201 can receive an input of parallel data (DIN) and output pull-up data (RDO) and pull-down data (FDO). The serialization circuit 201 can be configured to serialize the parallel data (DIN) to generate serial data, that is, pull-up data (RDO) and pull-down data (FDO).
[0040] The driving strength and equalization control circuit 203 can receive inputs of pull-up data (RDO), pull-down data (FDO), a plurality of strength control signals (PUEN<0:M>), a plurality of equalization control signals (PUEQEN<0:M>), a plurality of preliminary selection signals (PD_CTRL<0:M>), and a delay control signal (DCTRL), and output a plurality of main / auxiliary selection signals (SELPUEQ<0:M>) and a plurality of pull-down selection signals (SELPD<0:M>).
[0041] The free driver 205 can receive inputs of a plurality of main / auxiliary selection signals (SELPUEQ<0:M>), a plurality of pull-down selection signals (SELPD<0:M>), a first impedance adjustment signal (PU_TRIM<0:N>), and a second impedance adjustment signal (PD_TRIM<0:N>), and output a plurality of first impedance control signals (PUCD<0:M><0:N>) and a plurality of second impedance control signals (PDCD<0:M><0:N>). The first impedance adjustment signal (PU_TRIM<0:N>) and the second impedance adjustment signal (PD_TRIM<0:N>) can be generated from an impedance matching circuit (not shown) within the semiconductor device including the transmission circuit 200 of the present invention. The impedance matching circuit can adjust the values of the first impedance adjustment signal (PU_TRIM<0:N>) and the second impedance adjustment signal (PD_TRIM<0:N>) to match a predetermined driving impedance based on the resistance value of an external resistor connected to an external resistor pad of the semiconductor device.
[0042] The data driver 207 can have its output terminal connected to the input / output pad 209. The data driver 207 can drive the input / output pad 209 with a plurality of first impedance control signals (PUCD<0:M><0:N>) and a plurality of second impedance control signals (PDCD<0:M><0:N>).
[0043] The control signal generation circuit 208 can generate a plurality of intensity control signals (PUEN<0:M>), a plurality of equalization control signals (PUEQEN<0:M>), a plurality of standby selection signals (PD_CTRL<0:M>), and a delay control signal (DCTRL) based on driving intensity information and an external control signal (EXT_CTRL).
[0044] FIG. 6 is a diagram showing the configuration of the driving intensity and equalization control circuit 203 of FIG. 5.
[0045] Referring to FIG. 6, the driving intensity and equalization control circuit 203 can include a plurality of sub-circuits 203-1 to 203-8.
[0046] The first sub-circuit 203-1 can receive inputs of pull-up data (RDO), intensity control signal (PUEN<0>), equalization control signal (PUEQEN<0>), and delay control signal (DCTRL), and output a main / auxiliary selection signal (SELPUEQ<0>). The second sub-circuit 203-2 can receive inputs of pull-up data (RDO), intensity control signal (PUEN<1>), equalization control signal (PUEQEN<1>), and delay control signal (DCTRL), and output a main / auxiliary selection signal (SELPUEQ<1>). The third sub-circuit 203-3 can receive inputs of pull-up data (RDO), intensity control signal (PUEN<2>), equalization control signal (PUEQEN<2>), and delay control signal (DCTRL), and output a main / auxiliary selection signal (SELPUEQ<2>). The fourth sub-circuit 203-4 can receive inputs of pull-up data (RDO), intensity control signal (PUEN<3>), equalization control signal (PUEQEN<3>), and delay control signal (DCTRL), and output a main / auxiliary selection signal (SELPUEQ<3>).
[0047] The fifth sub-circuit 203-5 can receive inputs of pull-down data (FDO) and preliminary selection signal (PD_CTRL<0>), and generate a pull-down selection signal (SELPD<0>). The sixth sub-circuit 203-6 can receive inputs of pull-down data (FDO) and preliminary selection signal (PD_CTRL<1>), and generate a pull-down selection signal (SELPD<1>). The seventh sub-circuit 203-7 can receive inputs of pull-down data (FDO) and preliminary selection signal (PD_CTRL<2>), and generate a pull-down selection signal (SELPD<2>). The eighth sub-circuit 203-8 can receive inputs of pull-down data (FDO) and preliminary selection signal (PD_CTRL<3>), and generate a pull-down selection signal (SELPD<3>).
[0048] FIG. 7 is a diagram showing the configuration and operation of the first sub-circuit 203-1 in FIG. 6.
[0049] Referring to FIG. 7, the first sub-circuit 203-1 can include a plurality of logic gates 211 to 213, 215, 216 and a delay circuit 214.
[0050] The first logic gate 211 and the second logic gate 212 can perform a logical AND operation on the pull-up data (RDO) and the intensity control signal (PUEN<0>) to generate an output signal (DO). The third logic gate 213 can perform a negative logical AND operation on the pull-up data (RDO) and the equalization control signal (PUEQEN<0>) and output it. The delay circuit 214 can delay the output of the third logic gate 213 by a delay time adjusted by the delay control signal (DCTRL) to generate an output signal (DO_PRE). When the equalization control signal (PUEQEN<0>) is at a high level, the delay circuit 214 can generate an output signal (DO_PRE) by inverting and delaying the rising edge of the pull-up data (RDO). When the equalization control signal (PUEQEN<0>) is at a low level, the output signal (DO_PRE) can be maintained at a high level regardless of the transition of the pull-up data (RDO). The fourth logic gate 215 and the fifth logic gate 216 can output the result of performing a logical AND operation on the output signal (DO) of the second logic gate 212 and the output signal (DO_PRE) of the delay circuit 214 as the main / auxiliary selection signal (SELPUEQ<0>).
[0051] FIG. 8 is a diagram showing the configuration of the free driver 205 in FIG. 5.
[0052] Referring to FIG. 8, the free driver 205 can include a plurality of logic circuits 205-1 to 205-8.
[0053] The first logic circuit 205-1 can receive the input of the main / auxiliary selection signal (SELPUEQ<0>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD0<0:N>). The second logic circuit 205-2 can receive the input of the main / auxiliary selection signal (SELPUEQ<1>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD1<0:N>). The third logic circuit 205-3 can receive the input of the main / auxiliary selection signal (SELPUEQ<2>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD2<0:N>). The fourth logic circuit 205-4 can receive the input of the main / auxiliary selection signal (SELPUEQ<3>) and the first impedance adjustment signal (PU_TRIM<0:N>) and output the first impedance control signal (PUCD3<0:N>). The fifth logic circuit 205-5 can receive the input of the pull-down selection signal (SELPD<0>) and the second impedance adjustment signal (PD_TRIM<0:N>) and output the second impedance control signal (PDCD0<0:N>). The sixth logic circuit 205-6 can receive the input of the pull-down selection signal (SELPD<1>) and the second impedance adjustment signal (PD_TRIM<0:N>) and output the second impedance control signal (PDCD1<0:N>). The seventh logic circuit 205-7 can receive the input of the pull-down selection signal (SELPD<2>) and the second impedance adjustment signal (PD_TRIM<0:N>) and output the second impedance control signal (PDCD2<0:N>). The eighth logic circuit 205-8 can receive the input of the pull-down selection signal (SELPD<3>) and the second impedance adjustment signal (PD_TRIM<0:N>) and output the second impedance control signal (PDCD3<0:N>). The first to eighth logic circuits 205-1 to 205-8 can be composed of AND logic for performing an AND operation on the input signals and outputting the result.
[0054] Figure 9 is a diagram showing the configuration of the control signal generation circuit 208 in Figure 5.
[0055] Referring to FIG. 9, the control signal generation circuit 208 can include an information setting circuit 208-1 and a signal generation circuit 208-3.
[0056] The information setting circuit 208-1 can generate a plurality of preliminary intensity control signals (PUEN_PRE<0:M>), a plurality of preliminary equalization control signals (EQEN_PRE<0:M>), a plurality of preliminary selection signals (PD_CTRL<0:M>), and a delay control signal (DCTRL) for selecting a main driving unit suitable for performing a data transmission operation and an auxiliary driving unit suitable for performing an equalization operation among a plurality of driving units 107-1 to 107-8 (see FIG. 4) according to the default driving intensity information. The information setting circuit 208-1 can adjust the values of the plurality of preliminary intensity control signals (PUEN_PRE<0:M>), the plurality of preliminary equalization control signals (EQEN_PRE<0:M>), and the delay control signal (DCTRL) according to an external control signal (EXT_CTRL) and generate a plurality of training mode signals (TRM<0:M>).
[0057] The signal generation circuit 208-3 can combine the plurality of preliminary intensity control signals (PUEN_PRE<0:M>), the plurality of preliminary equalization control signals (EQEN_PRE<0:M>), and the plurality of training mode signals (TRM<0:M>) to generate a plurality of intensity control signals (PUEN<0:M>) and a plurality of equalization control signals (PUEQEN<0:M>).
[0058] FIG. 10 is a diagram showing the configuration of the signal generation circuit 208-3 in FIG. 9.
[0059] Referring to FIG. 10, the signal generation circuit 208-3 can include a plurality of signal generation units 280-1 to 280-4. The first signal generation unit 280-1 can include a plurality of logic gates 281 to 288. The first logic gate 281 can invert and output a preliminary intensity control signal (PUEN_PRE<0>). The second logic gate 282 can invert and output a preliminary equalization control signal (EQEN_PRE<0>). The third logic gate 283 can invert and output a training mode signal (TRM<0>). The fourth logic gate 284 can output, as an intensity control signal (PUEN<0>), the result of performing a negative logical product operation on the outputs of the first logic gate 281, the second logic gate 282, and the third logic gate 283. The fifth logic gate 285 can invert and output a preliminary intensity control signal (PUEN_PRE<0>). The sixth logic gate 286 can perform a negative logical product operation on the output of the fifth logic gate 285 and the preliminary equalization control signal (EQEN_PRE<0>) and output the result. The seventh logic gate 287 can invert and output a training mode signal (TRM<0>). The eighth logic gate 288 can output, as an equalization control signal (PUEQEN<0>), the result of performing a negative logical product operation on the outputs of the sixth logic gate 286 and the seventh logic gate 287. The second to fourth signal generation units 280-2 to 280-4 can be configured in the same manner as the first signal generation unit 280-1.
[0060] As shown in the table of FIG. 10, the control signal generation circuit 208 described with reference to FIGS. 9 and 10 can vary the operation mode of the transmission circuit 200 by adjusting the values of a plurality of preliminary intensity control signals (PUEN_PRE<0:M>), a plurality of preliminary equalization control signals (EQEN_PRE<0:M>), and a plurality of training mode signals (TRM<0:M>).
[0061] Preliminary intensity control signal (PUEN_PRE ), (where "i" is an arbitrary natural number, and in the embodiments of the present invention, it is one of "0" to "3"), a pre - equalization control signal (EQEN_PRE ) and the training mode signal (TRM ) is all "0", the intensity control signal (PUEN ) becomes "0", and the equalization control signal (PUEQEN ) becomes "0", enabling the driving unit corresponding to the "i"-th one to be turned off (OFF).
[0062] Pre-strength control signal (PUEN_PRE ) is "1", the preliminary equalization control signal (EQEN_PRE ) is "0" or "1", the training mode signal (TRM ) is "0", the intensity control signal (PUEN ) becomes "1", and the equalization control signal (PUEQEN ) becomes "0", enabling the main driving unit corresponding to the "i" - th one to perform a transmission operation.
[0063] Standby strength control signal (PUEN_PRE ) is "0", the preliminary equalization control signal (EQEN_PRE ) is "1", the training mode signal (TRM ) is "0", the intensity control signal (PUEN ) becomes "1", and the equalization control signal (PUEQEN ) becomes "1", enabling the auxiliary driving unit corresponding to the "i" - th to perform the equalization operation.
[0064] Training mode signal (TRM ) is "1", the preliminary strength control signal (PUEN_PRE ) and a preliminary equalization control signal (EQEN_PRE ) Regardless of, the intensity control signal (PUEN ) becomes "1", and the equalization control signal (PUEQEN ) becomes "1", and the training operation using the auxiliary driving unit corresponding to the "i"-th can be performed. The training operation performs data writing and reading in cooperation with an external system, monitors the data obtained by the reading operation, and controls the equalization operation using the auxiliary driving unit according to the result by an external control signal (EXT_CTRL). The equalization operation control is performed by adjusting the delay control signal (DCTRL) by the external control signal (EXT_CTRL) to adjust the pulse width of the output signal of the auxiliary driving unit.
[0065] FIG. 11 is a diagram showing the configuration of a training system 300 according to an embodiment of the present invention.
[0066] Referring to FIG. 11, the training system 300 according to an embodiment of the present invention can include a semiconductor device 400 and a host 500.
[0067] The semiconductor device 400 can include the transmission circuit described based on FIG. 1 or FIG. 5. The semiconductor device 400 can include a plurality of driving units connected to input / output pads, that is, a plurality of pull-up driving units and a plurality of pull-down driving units, and an impedance matching circuit. In FIG. 11, only a plurality of pull-up driving units (PU) among the plurality of pull-up driving units and the plurality of pull-down driving units are shown. "PU600" is a pull-up driving unit designed to have a driving strength of 600 Ω and is referred to as the first pull-up driving unit. "PU300" is a pull-up driving unit designed to have a driving strength of 300 Ω and is referred to as the second pull-up driving unit. "PU150" is a pull-up driving unit designed to have a driving strength of 150 Ω and is referred to as the third pull-up driving unit. "PU120" is a pull-up driving unit designed to have a driving strength of 120 Ω and is referred to as the fourth pull-up driving unit.
[0068] The impedance matching circuit can adjust the values of impedance adjustment signals (PU_TRIM<0:N>, PD_TRIM<0:N>, see FIG. 5) to match a predetermined driving impedance based on the resistance value of an external resistor (RZQ) connected to an external resistor pad of the semiconductor device 400, and provide them to a plurality of pull-up driving units (PU).
[0069] The semiconductor device 400 can be configured to select at least one main driving unit corresponding to a predetermined driving strength among a plurality of driving units, perform a data transmission operation, and operate an auxiliary driving unit among the remaining driving units excluding the main driving unit to perform an equalization operation.
[0070] The host 500 can be configured to set the operation mode of the semiconductor device 400 to a training mode using an external control signal (EXT_CTRL), write data in a predetermined pattern (for example, "11110000"), monitor the data output by a read operation, and perform a training operation while changing an auxiliary driving unit among a plurality of pull-up driving units (PU) according to the result.
[0071] As shown in the table of FIG. 11, when the driving strength is set to "LTT150", among a plurality of pull-up driving units (PU), the second pull-up driving unit (PU300) can be set as the main driving unit (M), and the remaining pull-up driving units can be used as auxiliary driving units (A). On the other hand, when the training mode is unavailable, or before the training mode proceeds, the fourth pull-up driving unit (PU120) can be set as the default auxiliary driving unit (Adft).
[0072] When the driving intensity is set to "LTT100", among the plurality of pull-up driving units (PU), the first pull-up driving unit (PU600) and the second pull-up driving unit (PU300) are set as the main driving unit (M), and the remaining pull-up driving units can be used as auxiliary driving units (A). On the other hand, the fourth pull-up driving unit (PU120) can be set as the default auxiliary driving unit (Adft).
[0073] When the driving intensity is set to "LTT75", among the plurality of pull-up driving units (PU), the third pull-up driving unit (PU150) is set as the main driving unit (M), and the remaining pull-up driving units can be used as auxiliary driving units (A). On the other hand, the fourth pull-up driving unit (PU120) can be set as the default auxiliary driving unit (Adft).
[0074] When the driving intensity is set to "LTT50", among the plurality of pull-up driving units (PU), the second pull-up driving unit (PU300) and the third pull-up driving unit (PU150) are set as the main driving unit (M), and the remaining pull-up driving units can be used as auxiliary driving units (A). On the other hand, the fourth pull-up driving unit (PU120) can be set as the default auxiliary driving unit (Adft).
[0075] In the training mode, for each driving intensity, the remaining driving units except the main driving unit can be alternately selected as the auxiliary driving unit.
[0076] On the one hand, when the training mode is not available, or before the training mode proceeds, the fourth pull-up driving unit (PU120) can be set as the default auxiliary driving unit (Adft).
[0077] The semiconductor device 400 in FIG. 11 illustrates the case where the driving strength is set to "LTT150". The second pull-up driving unit (PU300) is set as the main driving unit to perform the data transmission operation. At the same time, the fourth pull-up driving unit (PU120), which is an extra driving unit, can be set as the auxiliary driving unit to perform the equalization operation.
[0078] That is, the embodiments of the present invention can perform the feed / forward equalization operation using the extra driving unit without providing another equalization circuit. Therefore, the quality of the transmitted signal can be improved without increasing the circuit area.
[0079] Thus, those skilled in the art to which the present invention pertains should understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the claims described below rather than the detailed description above. It must be analyzed that all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.
Claims
1. A plurality of driving units are connected to the input / output pads, Selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units, and performing a data transmission operation; a transmitting circuit configured to select at least one auxiliary driving unit from among the remaining driving units other than the main driving unit to perform an equalization operation.
2. 2. The transmission circuit of claim 1, wherein the plurality of driving units includes a plurality of pull-up driving units and a plurality of pull-down driving units, and the transmission circuit is configured to select the main driving unit from each of the plurality of pull-up driving units and the plurality of pull-down driving units to perform the data transmission operation.
3. The transmitting circuit of claim 2 , wherein the transmitting circuit is configured to select the auxiliary driving unit from among the plurality of pull-up driving units to perform the equalization operation.
4. The transmission circuit of claim 1, wherein the transmission circuit is configured to perform the equalization operation by operating the auxiliary driving unit to vary a pulse width of data transmitted by the data transmission operation.
5. a data driver including a plurality of driving units connected to an input / output pad and having different driving strengths, wherein at least one of the plurality of driving units is selected as a main driving unit and at least one of the remaining driving units other than the main driving unit is selected as an auxiliary driving unit in response to a first impedance control signal; a driving strength and equalization control circuit configured to generate a plurality of primary / auxiliary selection signals in response to a plurality of strength control signals, a plurality of equalization control signals and input data; a free driver configured to output a result of logically combining the plurality of primary / auxiliary selection signals and a first impedance adjustment signal as the first impedance control signal.
6. The transmitter circuit of claim 5 , further comprising a serialization circuit configured to serialize parallel data to generate the input data and provide the input data to the driving strength and equalization control circuit.
7. The transmitting circuit according to claim 5 , further comprising a control signal generating circuit configured to generate the plurality of intensity control signals and the plurality of equalization control signals according to driving intensity information and an external control signal.
8. The control signal generating circuit includes: An information setting circuit configured to generate a plurality of preliminary strength control signals and a plurality of preliminary equalization control signals for selecting the main driving unit and the auxiliary driving unit according to the driving strength information and the external control signal; and a signal generation circuit configured to combine the plurality of preliminary power control signals and the plurality of preliminary equalization control signals to generate the plurality of power control signals and the plurality of equalization control signals.
9. The data driver includes the driving units, which include a plurality of pull-up driving units and a plurality of pull-down driving units; The transmission circuit according to claim 5 , configured such that, during a data transmission operation, the main driving unit is selected from each of the plurality of pull-up driving units and the plurality of pull-down driving units.
10. The transmission circuit according to claim 9 , wherein the data driver is configured such that the auxiliary driving unit is selected from among the pull-up driving units during an equalization operation.
11. The transmission circuit according to claim 5 , wherein the data driver is configured to vary a pulse width of data transmitted in a data transmission operation by operating the auxiliary driving unit during an equalization operation.
12. the driving strength and equalization control circuit includes a plurality of sub-circuits; 6. The transmission circuit of claim 5, wherein each of the plurality of subcircuits is configured to generate a first signal by combining the input data and one of the plurality of intensity control signals, to delay a second signal by combining the input data and one of the plurality of equalization control signals to generate a third signal, and to combine the first signal and the third signal to generate one of the plurality of primary / auxiliary selection signals.
13. A semiconductor device including a plurality of driving units connected to an input / output pad, the semiconductor device being configured to select at least one main driving unit corresponding to a predetermined driving strength from the plurality of driving units to perform a data transmission operation, and to select at least one auxiliary driving unit from the remaining driving units excluding the main driving unit to perform an equalization operation; A training system comprising: a host configured to write write data having a predetermined pattern to the semiconductor device and perform a training operation while changing the auxiliary driving unit among the plurality of driving units based on read data.
14. The semiconductor device includes: a data driver connected to the input / output pad, the data driver including a plurality of driving units having different driving strengths, the data driver being configured to select the at least one main driving unit and the at least one auxiliary driving unit among the plurality of driving units in response to a first impedance control signal; a driving strength and equalization control circuit configured to generate a plurality of primary / auxiliary selection signals in response to a plurality of strength control signals, a plurality of equalization control signals and input data, and to adjust pulse widths of the plurality of primary / auxiliary selection signals in response to a delay control signal; 14. The training system of claim 13, further comprising: a free driver configured to output a result of a logical combination of the plurality of primary / auxiliary selection signals and a first impedance adjustment signal as the first impedance control signal.
15. The training system of claim 14 , further comprising a control signal generating circuit configured to generate the delay control signal, the plurality of intensity control signals and the plurality of equalization control signals according to driving intensity information and an external control signal.
16. The control signal generating circuit includes: an information setting circuit configured to generate a training mode signal, a plurality of preliminary strength control signals and a plurality of preliminary equalization control signals according to the driving strength information and the external control signal; and a signal generation circuit configured to combine the training mode signal, the plurality of preliminary power control signals, and the plurality of preliminary equalization control signals to generate the plurality of power control signals and the plurality of equalization control signals.
17. The data driver includes the driving units, which include a plurality of pull-up driving units and a plurality of pull-down driving units; The training system of claim 14, configured such that, during the data transmission operation, the primary driving unit is selected from each of the plurality of pull-up driving units and the plurality of pull-down driving units.
18. The training system of claim 17 , wherein the data driver is configured such that the auxiliary driving unit is selected from among the pull-up driving units during the equalization operation.
19. The training system according to claim 14 , wherein the data driver is configured to vary a pulse width of data transmitted by the data transmission operation by operating the auxiliary driving unit during the equalization operation.
20. the driving strength and equalization control circuit includes a plurality of sub-circuits; 15. The training system of claim 14, wherein each of the plurality of sub-circuits is configured to generate a first signal that combines the input data and one of the plurality of intensity control signals, delay a second signal that combines the input data and one of the plurality of equalization control signals to generate a third signal, and combine the first signal and the third signal to generate one of the plurality of primary / auxiliary selection signals.