Semiconductor device

Abstract

To provide a transistor with excellent electric characteristics, a transistor with stable electric characteristics, or a semiconductor device with a high integration degree.SOLUTION: In a top-gate transistor in which oxide semiconductor is used for a semiconductor layer for forming a channel, an element is introduced to the semiconductor layer in a self-aligning manner after a gate electrode is formed, and then, a side surface of the gate electrode is covered with a structure. The structure preferably contains silicon oxide. A first insulating layer is formed covering the semiconductor layer, the gate electrode, and the structure. On the first insulating layer, a second insulating layer is formed by a sputtering method. When the second insulating layer is formed, oxygen is introduced to the first insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a transistor and a semiconductor device, and a method for manufacturing the same. .

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices (liquid crystal display devices, light-emitting display devices, etc.), lighting devices, electro-optical devices, Power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like have semiconductor devices. There are cases. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. Since the film can be formed by a deposition method, it is possible to form the semiconductor of the transistor that constitutes a large display device. In addition, a transistor using an oxide semiconductor can be used in an amorphous silicon It is possible to improve and use some of the production equipment for transistors using Another benefit is reduced investment.

[0005] In addition, a transistor including an oxide semiconductor has an extremely low leakage current in an off-state. For example, it is known that a transistor using an oxide semiconductor has an extremely low leakage current. A low-power CPU that utilizes the low current characteristic has been disclosed (see Patent Document 1). Light. ). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0007] One of the objects is to provide a fine transistor. One of the objectives is to provide a transistor with high frequency characteristics. One object of the present invention is to provide a transistor having favorable electrical characteristics. Another object of the present invention is to provide a transistor with stable electrical characteristics. Another object of the present invention is to provide a transistor with low power consumption. It is an object of the present invention to provide a good transistor. Alternatively, a semiconductor device having at least one of these transistors is provided. An object of the present invention is to provide a semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including first to third oxide layers, an insulating layer, first to third electrodes, and a structure. a first oxide layer in contact with a second oxide layer, the second oxide layer in contact with a third oxide layer; The first to third oxide layers have a first region overlapping each other, and an insulating layer is formed on the first region. The structure has a first electrode through the layer, and a second oxide layer covering the side of the first electrode. a second oxide layer having a second region overlapping the first electrode and a second region overlapping the structure; a third region in contact with the second electrode, a fourth region in contact with the third electrode, and a fifth region in contact with the third electrode. The second oxide layer is an oxide semiconductor, and the third to fifth regions are included in the second region. The transistor contains elements different from the elements in the

[0010] The element different from the element contained in the second region is, for example, tungsten, titanium, aluminum, etc. The second oxide layer is CAAC-OS (C Axis Al ignited Crystalline Oxide Semiconductor It is preferable that the CAAC-OS is described in detail in the third embodiment. The second oxide layer preferably contains either In or Zn, or both. The first oxide layer and the third oxide layer are formed by mixing at least one of the metal elements contained in the second oxide layer. It is preferable that the metal element contains at least one kind of metal element and the same kind of metal element.

[0011] One aspect of the present invention includes a first step of forming a second oxide layer on a first oxide layer, and a second step of processing the second oxide layer into islands, and a third step of forming a third oxide layer covering the second oxide layer. a third step of forming a layer; and a fourth step of forming a first insulating layer covering the third oxide layer. A fifth step of forming a first electrode on the first insulating layer and a fifth step of forming a second insulating layer on the first insulating layer using the first electrode as a mask. Then, a portion of the third oxide layer and a portion of the first insulating layer are removed to expose a portion of the second oxide layer. a sixth step of removing an element from the second oxide layer; and a seventh step of introducing an element into at least a portion of the second oxide layer. An eighth step of forming a second insulating layer and processing the second insulating layer to cover the side surface of the first electrode. A ninth step of forming a structure, comprising providing a second electrode and a second electrode on the exposed area of ​​the second oxide layer. A tenth step of forming a third electrode and a third electrode, and a third insulating film covering the second electrode and the third electrode. In the eleventh step of forming the insulating layer and the fourth insulating layer covering the third insulating layer, A twelfth step of introducing oxygen into the edge layer, and a thirteenth step of performing a heat treatment after the twelfth step. and a step of forming a second oxide layer using an oxide semiconductor.

[0012] The twelfth step is preferably performed by a sputtering method. It is preferable that the compound contains

[0013] Another embodiment of the present invention is a semiconductor device including the above transistor or the above semiconductor device, an antenna, a buffer, The electronic device has a terminal, an operation switch, a microphone, or a speaker. Effect of the Invention

[0014] It is possible to provide a fine transistor or a transistor with a small parasitic capacitance. Alternatively, a transistor having high frequency characteristics can be provided. It is possible to provide a transistor having good electrical characteristics. Alternatively, a transistor with low power consumption can be provided. Alternatively, a highly reliable transistor can be provided. Thus, novel transistors can be provided. It is possible to provide a semiconductor device having either one of the above.

[0015] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0016] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram for explaining an energy band structure. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11]1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 22] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 23] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 24] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 25] Electron diffraction pattern of CAAC-OS. [Figure 26] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 27] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 31] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Diagram 32] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 2 is a block diagram showing an example of the configuration of a CPU. [Diagram 34] FIG. 1 is a circuit diagram showing an example of a memory element. [Diagram 35] FIG. 1 illustrates an example of an imaging apparatus. [Diagram 36] FIG. 1 illustrates an example of an imaging apparatus. [Figure 37] FIG. 1 illustrates an example of an imaging apparatus. [Figure 38] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 39] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Diagram 40] FIG. 1 is a circuit diagram showing an example of an imaging device. [Diagram 41] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Diagram 42] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Diagram 43] FIG. 1 is a cross-sectional view showing an example of the configuration of an imaging apparatus. [Diagram 44] FIG. 1 is a block diagram illustrating an example of a display device. [Diagram 45] FIG. 2 is a circuit diagram illustrating an example of a pixel circuit. [Figure 46] 1A and 1B illustrate an example of a display device. [Figure 47] 1A and 1B illustrate an example of a display device. [Figure 48] FIG. 2 is a diagram illustrating an example of a display module. [Figure 49] FIG. 1 is a block diagram illustrating an example of an RF tag. [Figure 50] FIG. 1 is a diagram explaining an example of how to use an RF tag. [Figure 51] FIG. 1 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. [Figure 52] 1A to 1C are diagrams illustrating examples of electronic devices. [Diagram 53] FIG. 2 is a top view showing an example of a film forming apparatus. [Figure 54] FIG. 1 is a cross-sectional view showing an example of a film forming apparatus. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. The repeated explanation may be omitted.

[0018] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily intended to facilitate understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in the actual manufacturing process, layers and resist masks are removed by processes such as etching. Although some losses may occur unintentionally, they may be omitted to make the data easier to understand.

[0019] In addition, in the drawings, in order to facilitate understanding of the invention, illustration of some components may be omitted. In addition, some hidden lines may be omitted.

[0020] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are merely given to indicate the order or sequence of steps or lamination. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is not necessary to confuse the constituent elements. In order to clarify the scope of the invention, ordinal numbers may be used in the claims. Even if a term is numbered in the first place, it may be numbered in the second place if a different ordinal number is used in the claims. In addition, even if a term is given an ordinal number in this specification, etc., In the claims, etc., ordinal numbers may be omitted.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0022] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "electrode B", it is not necessary for electrode B to be formed directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0023] The source and drain functions may also be different in some cases, such as when transistors of different polarities are used, or when When the direction of the current changes during operation of the circuit, the two are interchangeable depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be so.

[0024] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0025] In addition, in this specification, "electrically connected" means "something that has some electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. Therefore, even if it is expressed as "electrically connecting," in the actual circuit, In some cases, there are no physical connections and only wires running along the wiring.

[0026] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the In the region where a channel is formed (also called a "channel forming region"), , source (source region or source electrode) and drain (drain region or drain electrode Note that in one transistor, the channel length is In other words, the channel length of a transistor is not always the same. Therefore, in this specification, the channel length is defined as the area in which the channel is formed. The value is any one of the values, the maximum value, the minimum value or the average value.

[0027] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0028] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (also called the effective channel width) and the The channel width (also called the "apparent channel width") may differ from the When the gate electrode covers the side surface of the semiconductor layer, the effective channel width is For example, when the gate voltage is too high, the effect of the In a transistor in which the electrodes cover the side surfaces of the semiconductor layer, the channel region is formed on the side surfaces of the semiconductor layer. In this case, the effective channel width is larger than the apparent channel width. The channel width becomes larger.

[0029] In such a case, it may be difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known precisely, the effective It is difficult to measure channel width accurately.

[0030] Therefore, in this specification, the apparent channel width is defined as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when the term "channel width" is used, it refers to the actual In addition, the channel length, channel width, and effective channel The width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0031] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0032] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with less than 0.1 atomic percent can be considered impurities. The conductor's DOS (Density of State) increases and the carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, elements, group 13 elements, group 14 elements, group 15 elements, and elements other than the main components of oxide semiconductors Transition metals, particularly hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen, etc. In addition, the inclusion of impurities may cause oxygen vacancies. In this case, impurities that change the properties of a semiconductor include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0033] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. In addition, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. "Straight" refers to two straight lines that form an angle of 60° or more and 120° or less.

[0034] In this specification, the terms "same," "the same," and "equal" are used to refer to counting values ​​and measurement values. " or "uniform" (including their synonyms), unless expressly stated The measurements are subject to a margin of error of plus or minus 20%.

[0035] In this specification, when an etching process is performed after a photolithography process, In this case, unless otherwise specified, the resist mask formed in the photolithography process is It shall be removed after the etching process is completed.

[0036] In addition, in this specification, a high power supply potential VDD (hereinafter, simply referred to as "VDD" or "H potential") The low power supply potential VSS is a power supply potential that is higher than the low power supply potential VSS. VSS (hereinafter simply referred to as "VSS" or "L potential") is the potential lower than the high power supply potential VDD. The lowest power supply potential is also referred to as VDD or VSS. For example, if VDD is at ground potential, VSS is at a potential lower than ground potential, and V When SS is at ground potential, VDD is at a potential higher than ground potential.

[0037] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0038] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0039] (Embodiment 1) In this embodiment, a structure example of the transistor 100 of one embodiment of the present invention will be described with reference to the drawings. and explain.

[0040] FIG. 1A is a plan view of a transistor 100. FIG. 1B is a plan view of the transistor 100 shown in FIG. 1B is a cross-sectional view taken along dashed line L1-L2 and dashed line W1-W2 shown in FIG. 1, the cross-sectional view taken along the dashed line L1-L2 is a cross-sectional view of the transistor 100 in the channel length direction. 1 is a cross-sectional view, and the cross-sectional view taken along dashed line W1-W2 is a cross-sectional view of the channel width direction of the transistor 100. FIG.

[0041] The transistor 100 includes an oxide layer 104 (oxide layer 104a, oxide layer 104b, and oxide layer 104c). The insulating layer 105 includes an insulating layer 106, an electrode 109a, an electrode 109b, and a structure. The electrode 106 can function as a gate electrode. The insulating layer 105 can be a gate The electrode 109a can function as either a source electrode or a drain electrode. The electrode 109b can function as the other of the source electrode or the drain electrode. The transistor 100 is formed on a substrate 101 with an insulating layer 102 and an insulating layer 103 interposed therebetween. It is set up as such.

[0042] In FIG. 1B, an insulating layer 102 is provided on a substrate 101, and an insulating layer The insulating layer 103 has a protruding portion, and an island-shaped oxide layer 104 is formed on the protruding portion. On the oxide layer 104b, an oxide layer 104a and an island-shaped oxide layer 104b are provided. An insulating layer 105 is provided on the oxide layer 104c. An electrode 106 is provided on the layer 104b via an oxide layer 104c and an insulating layer 105. The structure 108 is provided on the oxide layer 104b adjacent to the side of the electrode 106. It is being done.

[0043] In addition, an electrode 109a is provided on the oxide layer 104b in contact with a part of the oxide layer 104b. In addition, an electrode 109b is provided on the oxide layer 104b and is in contact with another part of the oxide layer 104b. It is set up as such.

[0044] In the oxide layer 104, a region overlapping the structure 108 and an electrode 109a and an electrode 109b are The region overlapping with b contains a metal element different from the main component of the oxide layer 104. The metal element is also contained in a part of each of the insulating layer 105, the oxide layer 104, and the insulating layer 103. It may occur. The region containing the metal element is called region 135. The end of region 135 is indicated by a broken line in FIG. 1(B). In FIG. 1(B), region 135 is formed above the broken line indicating the end of region 135 .

[0045] In the oxide layer 104, region 135 can function as the source region or the drain region of the transistor 100. Therefore, the region sandwiched between region 135 of the oxide layer 104 can function as the channel formation region.

[0046] An insulating layer 107 is provided on the electrode 106. An insulating layer 110 is provided on the electrode 109a, the electrode 10 9b, the structure 108, and the insulating layer 107. An insulating layer 111 is provided on the insulating layer 110, and an insulating layer 112 is provided on the insulating layer 111 .

[0047] Electrodes 114a and 114b are provided on the insulating layer 112. The electrode 114a is electrically connected to the electrode 109a through the contact plug 113a in an opening provided in a part of the insulating layer 112, the insulating layer 111, and the insulating layer 110. The electrode 114 b is electrically connected to the electrode 109b through the contact plug 113b in an opening provided in a part of the insulating layer 112, the insulating layer 111, and the insulating layer 110.

[0048] As shown in FIG. 1(B), in the cross-sectional view in the channel width direction of the transistor 100, the electrode 106 covers the upper surface and the side surface of the oxide layer 104b. By the insulating layer 103 having a convex portion, not only the upper surface but also the side surface of the oxide layer 104b can be covered by the electrode 106 . ​​​​That is, the transistor 100 can be configured such that the oxide layer 104b is electrically connected to the gate of the electrode 106. The structure can electrically surround the semiconductor (the electric field of the conductive layer can electrically The structure of a transistor that is electrically surrounded is called a surrounded channel (sc Therefore, the oxide layer 104b has a channel structure. In the s-channel structure, the drain current (transistor current flowing between the source and drain of the transistor), and a larger on-current ( When a transistor is on, the current that flows between the source and drain can be obtained. In addition, a channel formation region is formed in the oxide layer 104b by the electric field of the electrode 106. Therefore, in the s-channel structure, the entire region of the transistor can be depleted. The off-state current of a transistor (the current that flows between the source and drain when the transistor is in the off state) ) can be further reduced. By reducing the channel width, The n-nel structure can increase the on-current and reduce the off-current. .

[0049] [Oxide layer 104] The oxide layer 104 is formed by stacking an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. It has a layered structure.

[0050] The oxide layer 104 is preferably made of an oxide semiconductor containing indium (In), for example. For example, when an oxide semiconductor contains indium, the carrier mobility (electron mobility) is In addition, the oxide semiconductor preferably contains an element M.

[0051] The element M is preferably aluminum, gallium, yttrium, tin or the like. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium However, the element M is the same as the above. In some cases, a combination of multiple elements may be used. For example, the element M has a bond energy with oxygen of The element M has a high energy. For example, the element M increases the energy gap of an oxide semiconductor. The oxide semiconductor preferably contains zinc. Conductors that contain zinc may be prone to crystallization.

[0052] However, the oxide layer 104 is not limited to an oxide containing indium. Indium-containing oxides, such as zinc tin oxide, gallium tin oxide, and gallium oxide, First, oxides containing zinc, oxides containing gallium, oxides containing tin, etc. may be used. do not have.

[0053] The oxide layer 104 is formed using, for example, an oxide semiconductor having a wide energy gap. The energy gap of the oxide semiconductor used in the layer 104 is, for example, 2.5 eV or more and 4.2 eV or more. eV or less, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3. It is less than 5 eV.

[0054] Oxide semiconductors are formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (MOCVD (Metal Organic Chemical Va) por deposition) method, ALD (Atomic Layer Deposit) method tion), thermal CVD or PECVD (Plasma Enhanced Chemical Vapor Deposition) (including but not limited to) Mical Vapor Deposition (MMD) BE (Molecular Beam Epitaxy) method or PLD (Pulsed The plasma CVD method is , high-quality films can be obtained at relatively low temperatures. MOCVD, ALD, or thermal CVD methods, etc. If a deposition method that does not use plasma is used, damage to the deposition surface is less likely to occur. Furthermore, a film with fewer defects can be obtained.

[0055] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0056] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of transistors and semiconductor devices can be improved. There are cases.

[0057] For example, when an In-Ga-Zn-O film is formed as the oxide layer 104 by thermal CVD, is trimethylindium (In(CH 3 ) 3 ), trimethylgallium (Ga(CH 3 ) 3 ), and dimethylzinc (Zn(CH 3 ) 2 ) is used. In addition, Without being limited thereto, triethylgallium (Ga(C 2 H 5 ) 3 )of Diethyl zinc (Zn(C) can also be used instead of dimethyl zinc. 2 H 5 ) 2 ) It is also possible.

[0058] For example, when an In-Ga-Zn-O film is formed as the oxide layer 104 by the ALD method, is In(CH 3 ) 3 Gas and O 3 The gases are introduced repeatedly in sequence to form an In-O layer, and then Then, Ga(CH 3 ) 3 Gas and O 3 The gas is introduced repeatedly in sequence to form a GaO layer, and then Then Zn(CH 3 ) 2 Gas and O 3 The gases are introduced repeatedly in sequence to form a ZnO layer. However, the order of these layers is not limited to this example. In addition, the In-Ga-O layer can be formed by using these gases. Alternatively, a mixed compound layer such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. 3 H obtained by bubbling water with an inert gas such as Ar 2 Even with O gas Good but without H 3 It is preferable to use In(CH 3 ) 3 Gas? And In(C 2 H 5 ) 3 Gas or tris(acetylacetonato)indium may also be used. Tris(acetylacetonato)indium is In(acac) 3 Also called. In addition, Ga(CH 3 ) 3 Instead of gas, Ga(C 2 H 5 ) 3 Gas and Tris (acetylacetone) Tris(acetylacetonato)gallium may also be used. a(acac) 3 Also called Zn(CH 3 ) 2 Gas or zinc acetate may also be used. The gas species are not limited to these.

[0059] When oxide semiconductors are deposited by sputtering, indium is used to reduce the number of particles. It is preferable to use a target containing M. Also, an oxide target having a high atomic ratio of element M is preferable. When using targets containing indium, the electrical conductivity of the target may be reduced. When using a ferrite core, the conductivity of the target can be increased, making DC and AC discharge easier. Therefore, it is easy to handle large-area substrates, and therefore the productivity of semiconductor devices is improved. It is possible.

[0060] In addition, when an oxide semiconductor is formed by sputtering, the atomic ratio of the target is In :M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1: 1:2, 1:4:4, 4:2:4.1, etc. would be good choices.

[0061] When an oxide semiconductor film is formed by a sputtering method, the atomic ratio of the target may deviate. In particular, zinc may be deposited as an oxide semiconductor having an atomic ratio of 0.1 to 0.25. The atomic ratio of the deposited film may be smaller than that of the target. In some cases, the ratio of the number of atoms of zinc to be used is between 40 atomic % and 90 atomic %. be.

[0062] The oxide layer 104a and the oxide layer 104c are formed by removing elements other than oxygen that constitute the oxide layer 104b. It is preferable that the metal layer is made of a material that contains one or more of the same metal elements. By using such a material, the interface between the oxide layer 104a and the oxide layer 104b and the oxide The interface state can be prevented from being generated at the interface between the nitride layer 104c and the oxide layer 104b. Therefore, scattering and capture of carriers at the interface are unlikely to occur, and the field effect of the transistor is improved. It is possible to improve the mobility. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. This becomes possible.

[0063] The thickness of the oxide layer 104a and the oxide layer 104c is preferably 3 nm or more and 100 nm or less. The thickness of the oxide layer 104b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0064] The oxide layer 104b is an In-M-Zn oxide (an oxide containing In, element M, and Zn). When the oxide layer 104a and the oxide layer 104c are also In-M-Zn oxides, The ZnO layer 104a and the oxide layer 104c are formed of In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio ], and the oxide layer 104b is In:M:Zn=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 The oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are larger than the oxide layer 104a. Preferably, y 1 / x 1 y 2 / x 2 More than 1.5 times larger than The oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are selected so that the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b are formed in a layer that is different from the oxide layer 104a. Preferably, y 1 / x 1 y 2 / x 2 The oxide layer 104a is more than twice as large as the oxide layer 104b. More preferably, y is selected from the oxide layer 104b and the oxide layer 104c. 1 / x 1 y 2 / x 2 The oxide layers 104a, 104c, and 104d are three times larger than the oxide layers 104a, 104c, and 104d. At this time, in the oxide layer 104b, y 1 x 1 If it is more than This is preferable because it can provide stable electrical characteristics to the transistor. 1 x 1 More than three times If the y 1 x 1 Less than three times It is preferable that the oxide layer 104a and the oxide layer 104c have the above-mentioned structure. As a result, the oxide layer 104a and the oxide layer 104c have less oxygen vacancies than the oxide layer 104b. It is possible to provide a layer in which such defects are unlikely to occur.

[0065] When the oxide layer 104a is an In-M-Zn oxide, the sum of In and M is 100 at When expressed as omic%, it is preferable that In is less than 50 atomic % and M is less than 50 atomic %. c%, and more preferably In is less than 25 atomic % and M is 75 atomic %. %. When the oxide layer 104b is an In-M-Zn oxide, the In and M When the sum of is 100 atomic %, In is preferably higher than 25 atomic %. , M is less than 75 atomic %, and more preferably In is higher than 34 atomic %; In the oxide layer 104c, M is less than 66 atomic %. When the sum of In and M is 100 atomic %, In is preferably 50 atomic %. %, M is more than 50 atomic %, and more preferably In is 25 atomic % or less. % or less, and M is higher than 75 atomic %. The same oxide as that of the material layer 104a may be used.

[0066] For example, the oxide layer 104a containing In or Ga and the oxide layer 104b containing In or Ga 104c, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4 In-Ga-Zn oxide formed using targets with atomic ratios of 1:9:6, etc. The material is formed using a target with an atomic ratio of In:Ga=1:9 or 7:93. The oxide layer 104b may be, for example, an In-Ga oxide. Formed using a target with an atomic ratio of n:Ga:Zn=1:1:1 or 3:1:2 The oxide layer 104a and the oxide layer 104b may be an In-Ga-Zn oxide. The atomic ratios of the oxide layer 104b and the oxide layer 104c are the same as the above atomic ratios, but with an error. Includes a fluctuation of plus or minus 20%.

[0067] The oxide layer 104b has a larger electron affinity than the oxide layer 104a and the oxide layer 104c. For example, the oxide layer 104b is made of the oxide layer 104a and the oxide layer The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or less, than that of 104c. The oxide having a larger valence energy than the surface energy is preferably 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0068] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the oxide layer 104c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0069] However, even if the oxide layer 104a and / or the oxide layer 104c is made of gallium oxide, For example, if gallium oxide is used as the oxide layer 104c, the electrode 105a or This can reduce the leakage current occurring between the electrode 105b and the electrode 109. That is, The off-state current of the transistor 100 can be reduced.

[0070] The oxide layer 104a and the oxide layer 104c have a smaller electron affinity than the oxide layer 104b. Therefore, when a gate voltage is applied, the oxide layer 104a is oxidized. Among the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c, the oxide layer 104b is It is easy for holes to form.

[0071] In addition, a transistor using an oxide semiconductor layer as the semiconductor layer in which a channel is formed ("OS transistor") In order to provide a transistor having stable electrical characteristics, The oxide layer 104b is made intrinsic or substantially intrinsic by reducing impurities and oxygen vacancies. It is preferable that the oxide semiconductor layer be an intrinsic oxide semiconductor layer. The channel formation region in b is an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. is preferred.

[0072] In addition, at least the oxide layer 104b of the oxide layer 104 is made of CAAC-OS. is preferred.

[0073] In addition, at least the oxide semiconductor layer used for the oxide layer 104b is a region that is not CAAC (A The total area of ​​the oxide semiconductor layer is less than 20%. It is preferable that there is.

[0074] The CAAC-OS has a dielectric anisotropy. The dielectric constant in the c-axis direction is larger than that in the b-axis direction. The transistor with the gate electrode aligned along the c-axis using CAAC-OS has Because of its large dielectric constant, the electric field generated by the gate electrode easily reaches the entire CAAC-OS. This makes it possible to reduce the subthreshold swing value (S value). Transistors that use a CAAC-OS layer are less susceptible to an increase in S value due to miniaturization.

[0075] In addition, the dielectric constant of CAAC-OS in the a-axis and b-axis directions is small, so This reduces the effect of the electric field between the gates. This reduces the channel length modulation effect and the short channel effect. , etc. are unlikely to occur, and the reliability of the transistor can be improved.

[0076] Here, the channel length modulation effect is a phenomenon in which the drain voltage increases when the drain voltage is higher than the threshold voltage. This refers to the phenomenon in which the depletion layer expands from the inside of the device, shortening the effective channel length. The channel effect is a phenomenon in which the shortening of the channel length leads to deterioration of electrical characteristics such as a decrease in threshold voltage. The smaller the transistor, the greater the degradation of electrical characteristics due to these phenomena. It is easy to occur.

[0077] [Energy band structure of oxide semiconductor layer] Here, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are stacked. The function and effect of the oxide layer 104 formed will be described with reference to the energy balance shown in FIG. The following explanation will be given using a band structure diagram. Figure 3(A) shows the A1-A2 dashed line in Figure 1(B). FIG. 3(A) shows the energy band structure of the transistor 1. 1 shows the energy band structure of the channel formation region of 00.

[0078] In Figure 3(A), Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are , the insulating layer 103, the oxide layer 104a, the oxide layer 104b, the oxide layer 104c, The energy of the conduction band minimum of the insulating layer 105 is shown.

[0079] Here, the electron affinity is the energy difference between the vacuum level and the top of the valence band (the "ionization potential"). It is also called the "energy gap". The top is a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the top of the valence band can be measured using ultraviolet photoelectron spectroscopy. Optical analysis (UPS: Ultraviolet Photoelectron Spectr This can be measured using a osscopy device (PHI VersaProbe).

[0080] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0081] Since the insulating layers 103 and 105 are insulators, Ec382 and Ec386 are Closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c .

[0082] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.05 eV, lower than Ec383b. 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level preferable.

[0083] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.05 eV, lower than Ec383b. 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level preferable.

[0084] Here, between the oxide layer 104a and the oxide layer 104b, there is a layer In some cases, the oxide layer 104b may have a mixed region with the oxide layer 104c. There may be a mixed region of the oxide layer 104b and the oxide layer 104c between them. The interface state density is low in the oxide layer 104a, the oxide layer 104b, and the The stack of the oxide layer 104c and the oxide layer 104b has a structure in which energy is continuously distributed near the interfaces of the stack. This results in a band structure in which the material changes (also called a continuous junction).

[0085] At this time, the electrons flow into the oxide layer 104a and the oxide layer 104c, but not into the oxide layer 104b. Therefore, the oxide layer 104a and the oxide layer 104b are mainly moved through the oxide layer 104a and the oxide layer 104b. The interface state density at the interface between the oxide layer 104b and the oxide layer 104c. By lowering the level density, the movement of electrons in the oxide layer 104b is inhibited. Therefore, the on-state current of the transistor 100 can be increased.

[0086] In addition, the interface or the vicinity of the interface between the oxide layer 104a and the insulating layer 103, and the oxide layer 104c At or near the interface between the semiconductor layer 104 and the insulating layer 105, there are trap levels 390 due to impurities and defects. However, due to the presence of the oxide layer 104a and the oxide layer 104c, This can keep the oxide layer 104b away from the trap levels.

[0087] When the transistor 100 has an s-channel structure, the oxide layer 104b A channel is formed throughout the oxide layer 104b. Therefore, the thicker the oxide layer 104b, the larger the channel region. That is, the thicker the oxide layer 104b, the higher the on-state current of the transistor 100. For example, it can be 20 nm or more, preferably 40 nm or more, and more preferably an oxide layer 104b having a region with a thickness of 60 nm or more, more preferably 100 nm or more; However, the productivity of a semiconductor device including the transistor 100 may decrease. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably 15 The oxide layer 104b may have a region with a thickness of 0 nm or less.

[0088] In order to increase the on-state current of the transistor 100, the thickness of the oxide layer 104c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 The oxide layer 104c may have a region of 100 nm or less. The oxide layer 104b in which the channel is formed is filled with elements other than oxygen (water) that constitute the adjacent insulator. The oxide layer has the function of blocking the intrusion of elements such as silicon and silicon oxide. It is preferable that 104c has a certain thickness. For example, it is preferable that the thickness is 0.3 nm or more. and an oxide layer 104c having a region with a thickness of at least 1 nm, more preferably at least 2 nm. The oxide layer 104c is formed by the outward diffusion of oxygen released from the insulating layer 103 and the like. In order to suppress diffusion, it is preferable that the material has an oxygen blocking property.

[0089] In order to increase reliability, the oxide layer 104a is thick and the oxide layer 104c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 If the oxide layer 104a has a region having a thickness of 60 nm or more, more preferably 60 nm or more, By increasing the thickness of the oxide layer 104a, the adjacent insulator and the oxide layer 104a can be prevented from being damaged. The distance from the interface with the oxide layer 104b where the channel is formed can be increased. However, the productivity of a semiconductor device having the transistor 100 may decrease. For example, the thickness is 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The oxide layer 104a may have the above-mentioned region.

[0090] Note that silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, it is preferable that the silicon concentration of the oxide layer 104b is low. Between the layer 104b and the oxide layer 104a, for example, secondary ion mass spectrometry (SIMS: 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 The silicon concentration is less than 100%. In addition, between the oxide layer 104b and the oxide layer 104c, a 1×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 2×10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0091] In order to reduce the hydrogen concentration in the oxide layer 104b, the oxide layer 104a and the oxide layer It is preferable to reduce the hydrogen concentration in the oxide layer 104a and the oxide layer 104c. , 2×10 in SIMS 20 atoms / cm 3 Less than or equal to 5×10 19 a toms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below are some more Preferably 5 x 10 18 atoms / cm 3 The hydrogen concentration range is as follows: In order to reduce the nitrogen concentration in the oxide layer 104b, the oxide layer 104a and the oxide layer 104c are It is preferable to reduce the nitrogen concentration in the oxide layer 104a and the oxide layer 104c. In S, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0092] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may cause the threshold voltage of the transistor to shift in the positive direction. The lower the copper concentration on the surface or inside of the oxide layer 104b, the more preferable. Layer 104b has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 It is preferred that the region stomach.

[0093] The above three-layer structure is an example. For example, a structure without the oxide layer 104a or the oxide layer 104c Alternatively, the oxide layer 104a may be formed on or under the oxide layer 104b. 104c, an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c are formed on or under the oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. Alternatively, the semiconductor layer may have a four-layer structure having any one of the semiconductors exemplified above. Above layer 104a, below oxide layer 104a, above oxide layer 104c, below oxide layer 104c The oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are It may be an n-layer structure (n is an integer of 5 or more) having any one of the semiconductors exemplified above. do not have.

[0094] In particular, the transistor 100 illustrated in this embodiment has an oxide The top and side surfaces of the oxide layer 104b are in contact with the oxide layer 104c, and the bottom surface of the oxide layer 104b is in contact with the oxide layer 104c. The oxide layer 104b is formed in contact with the oxide layer 104a (see FIG. 1B). By covering the oxide layer 104a and the oxide layer 104c, the influence of the trap states is reduced. This can further reduce the noise.

[0095] The band gaps of the oxide layer 104a and the oxide layer 104c are It is preferable that the band gap is wider than that of b.

[0096] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0097] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a semiconductor layer can have an extremely small off-state current. Specifically, when the source-drain voltage is 3.5 V and the temperature is 25°C, The off-state current per 1 μm of panel width is 1×10 -20 Less than A, 1×10 -22 Less than A or is 1×10 -24 That is, the on-off ratio can be increased by 20 orders of magnitude to less than 150 A. It can be up to 1000 digits.

[0098] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, a semiconductor device with low power consumption can be realized.

[0099] <Variation 1> In FIG. 2, the oxide layer 104 is not provided, and the oxide layer 104 is formed by dividing the oxide layer 104 into the oxide layer 104b and the oxide layer 104b. FIG. 2B shows a transistor 150 made of the same material as that shown in FIG. 1 is a cross-sectional view taken along dashed line L1-L2 and dashed line W1-W2. 0 has the same structure as transistor 100 except for the configuration of the oxide layer 104.

[0100] Figure 3(B) shows the energy band structure of the portion indicated by the dashed line B1-B2 in Figure 2(B). That is, FIG. 3B shows the energy of the channel formation region of the transistor 150. The transistor 150 does not have the oxide layer 104a. The oxide layer 104c is not provided and the oxide level 390 is easily affected by the trap level 390. It is possible to achieve a higher field effect mobility than when the layer 104b has a single-layer structure.

[0101] <Variation 2> The transistor 160 shown in FIG. 4 has a back gate electrode between the insulating layer 102 and the insulating layer 103. The transistor 100 differs from the transistor 100 in that an electrode 119 that functions as a 4(B) is a plan view of the transistor 160. Also, FIG. 4(B) is a plan view of the transistor 160 along the dashed line L1 shown in FIG. 1A is a cross-sectional view taken along line W1-W2 of the electrode 119. It can be formed using the same materials and methods as those described above.

[0102] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode is set to the same potential as the gate electrode. Alternatively, the back gate may be set to a ground potential (GND potential) or any other potential. By changing the potential of the electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The value voltage can be changed.

[0103] Both the electrode 106 and the electrode 119 can function as a gate electrode. The insulating layer 103 and the insulating layer 105 each function as a gate insulating layer. can be done.

[0104] When one of the electrodes 106 and 119 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 160, the electrode 106 is called the "gate electrode." When the term "electrode" is used, the electrode 119 is called a "back gate electrode." When the transistor 160 is used as a bottom gate type transistor, In addition, either the electrode 106 or the electrode 119 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0105] By providing the electrode 106 and the electrode 119 with the oxide layer 104 sandwiched therebetween, 6 and the electrode 119 are set to the same potential, the region in which carriers flow in the oxide layer 104 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 160 increases, the field effect mobility increases.

[0106] Therefore, the transistor 160 is a transistor having a large on-current relative to its area. That is, the area of ​​the transistor 160 required for the required on-current is Therefore, a highly integrated semiconductor device can be realized.

[0107] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0108] The electrodes 106 and 119 each have the function of blocking an electric field from the outside. Charges such as charged particles generated above the electrode 106 and below the electrode 119 are transferred to the oxide layer 104. This does not affect the channel formation region of the gate. As a result, stress tests (e.g., applying a negative charge to the gate) -GBT (Gate Bias-Temperature) stress test In addition, the electrodes 106 and 119 are resistant to the electric field generated from the drain electrode. This prevents the semiconductor layer from being affected by the drain voltage fluctuation. As a result, the fluctuation in the on-state current rise voltage can be suppressed. This is particularly noticeable when a potential is applied to the electrodes 106 and 119 .

[0109] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. It is possible to evaluate the characteristic changes (aging) of the stator in a short time. The amount of change in the threshold voltage of a transistor before and after the test is an important indicator for examining reliability. The smaller the change in threshold voltage before and after the BT stress test, the higher the reliability. It can be said that this is a high-performance transistor.

[0110] In addition, the electrode 106 and the electrode 119 are provided, and the electrode 106 and the electrode 119 are set to the same potential. This reduces the amount of variation in threshold voltage between multiple transistors. At the same time, the variation in electrical characteristics is reduced.

[0111] In addition, a transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0112] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0113] Also, for example, as shown in FIG. 4C, an insulating layer 116 is formed on the electrode 119, and the insulating layer An insulating layer 115 may be formed on the insulating layer 116, and an insulating layer 103 may be formed on the insulating layer 115. The edge layer 116 and the insulating layer 115 are formed of the same material and by the same method as the insulating layer 103. can be done.

[0114] The insulating layer 115 is made of hafnium oxide, aluminum oxide, tantalum oxide, aluminum By forming the insulating layer 115 from silicate or the like, it is possible to make the insulating layer 115 function as a charge trapping layer. By injecting electrons into the insulating layer 115, the threshold voltage of the transistor can be changed. It is possible to inject electrons into the insulating layer 115 by utilizing, for example, the tunnel effect. By applying a positive voltage to the electrode 119, tunnel electrons are injected into the insulating layer 115. You can enter.

[0115] <Variation 3> As shown in FIG. 5, a transistor 170 is provided with an electrode 119 between a substrate 101 and an insulating layer 102. FIG. 5A is a plan view of a transistor 170. FIG. 5B is a plan view of a transistor 170. 1(A) is a cross-sectional view taken along dashed dotted line L1-L2 and dashed dotted line W1-W2.

[0116] When the electrode 119 is provided between the substrate 101 and the insulating layer 102, the insulating layer 102 also functions as a gate insulator. It can function as an edge layer.

[0117] Also, for example, as shown in FIG. 5C, the insulating layer 102 and the insulating layer 116 are formed on the electrode 119. Then, an insulating layer 115 is formed on the insulating layer 116, and an insulating layer 103 is formed on the insulating layer 115. You may do so.

[0118] <Modification 4> As shown in FIG. 6, the insulating layer 105 and the oxide layer 104c are connected to an electrode 106. The structure 108 may be provided in the region overlapping the structure 109 as well as the region overlapping the structure 108. FIG. 6B is a plan view of the transistor 180. 1 and a cross-sectional view taken along dashed line W1-W2. An electrode 119 that can function as a gate electrode may be provided via an insulating layer.

[0119] <Variation 5> As shown in FIG. 7, the area that does not overlap with the electrode 106 and the structure 108 is a transistor 190. The insulating layer 105 in the region is etched to expose the oxide layer 104c, and the oxide layer 104c is etched to expose the oxide layer 104c. Alternatively, the entire transistor 190 may be left as is. FIG. 7A is a plan view of the transistor 190. FIG. 7B shows the dashed line L1-L2 and the dashed line W1-W2 shown in FIG. In addition, under the oxide layer 104, a gate electrode that can function as a back gate electrode is provided. The electrode 119 may be provided via an insulating layer.

[0120] <Variation 6> As shown in FIG. 8, the insulating layer 105 overlapping the structure 108 is removed, and The structure 108 and the oxide layer 104c may be in contact with each other. FIG. 8B is a plan view of the alternate long and short dashed lines L1-L2 and W shown in FIG. In addition, a back gate electrode is formed under the oxide layer 104. A functional electrode 119 may be provided through the insulating layer.

[0121] <Variation 7> As in the transistor 192 shown in FIG. 9, the oxide layer 104c overlapping the electrode 106 is 9A is a plan view of the transistor 192. FIG. are cross-sectional views taken along dashed lines L1-L2 and W1-W2 in FIG. In addition, an electrode 119 that can function as a back gate electrode is formed under the oxide layer 104. An insulating layer may be provided therebetween.

[0122] <Variation 8> As shown in FIG. 10, the oxide layer 104c extends beyond the edge of the structure 108, as in transistor 193. FIG. 10A is a plan view of the transistor 193. 10B is a graph showing the relationship between the dashed line L1-L2 and the dashed line W1-W2 shown in FIG. Also, under the oxide layer 104, an electrode 104 that can function as a back gate electrode is provided. 19 may be provided via an insulating layer.

[0123] <Variation 9> As in the transistor 194 shown in FIG. 11, the oxide layer 104a and the oxide layer 104c are 11A shows a transistor 194. FIG. 11B is a plan view of the dashed line L1-L2 and the dashed line L1-L2 shown in FIG. FIG. 2 is a cross-sectional view taken along dashed line W1-W2.

[0124] In addition, as in the case of a transistor 194a shown in FIG. An electrode 119 may be provided beneath layer 104, which may function as a back gate electrode. The layer 19 may be provided on the substrate 101 or on the insulating layer 102 .

[0125] <Modification 10> As in the transistor 195 shown in FIG. 13, a protrusion is not provided in the insulating layer 103, and the oxide Layer 104a and oxide layer 104c may be present beyond the edge of structure 108. FIG. 13A is a plan view of a transistor 194. FIG. 13B is a plan view of the transistor 194 shown in FIG. 1 is a cross-sectional view taken along dashed lines L1-L2 and W1-W2 shown in FIG. An electrode 119 that can function as a back gate electrode is provided under the material layer 104 via an insulating layer. It is okay.

[0126] In addition, as in the case of a transistor 195a shown in FIG. An electrode 119 may be provided beneath layer 104, which may function as a back gate electrode. The layer 19 may be provided on the substrate 101 or on the insulating layer 102 .

[0127] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. The channel forming region, source / drain region, etc. of a transistor such as the transistor 100 However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the circumstances, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. The semiconductors may include various semiconductors. In one embodiment of the present invention, various transistors, channel formation regions of transistors, or The source and drain regions of the transistors are made of, for example, silicon, germanium, silicon germanium, etc. Rumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide , gallium nitride, or an organic semiconductor. For example, in some cases or depending on the situation, various trans A channel forming region of a transistor, or a source / drain region of a transistor The above-mentioned materials do not necessarily include an oxide semiconductor.

[0128] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0129] (Embodiment 2) In this embodiment, an example of a method for manufacturing the transistor 100 will be described with reference to the drawings. The L1-L2 cross section in FIG. 15 to FIG. 20 is a cross section taken along the dashed line L1-L2 shown in FIG. 1(A). 15 to 20 correspond to the W1-W2 cross section shown in FIG. It corresponds to the cross section taken along line W1-W2.

[0130] First, an insulating layer 102 is formed on a substrate 101, and an insulating layer 103 is formed on the insulating layer 102. (See Figure 15(A)).

[0131] There is no particular restriction on the material used for the substrate 101, but it should be at least able to withstand the subsequent heat treatment. For example, barium borosilicate glass or aluminum Glass substrates such as borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used.

[0132] The substrate 101 may be a single crystal semiconductor substrate made of silicon or silicon carbide. Crystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, etc. In addition, it is possible to fabricate SOI substrates and semiconductor substrates with strained transistors, FIN type transistors, etc. Alternatively, a semiconductor element having a high electron mobility transistor may be used. High Electron Mobility Transistor (HEMT) or) applicable to gallium arsenide, aluminum gallium arsenide, indium gallium arsenide Alternatively, gallium nitride, indium phosphide, silicon germanium, etc. may be used. That is, the substrate 101 is not limited to being a simple support substrate, but may be a substrate on which other devices such as transistors are formed. In this case, the gate, source, or drain of the transistor 100 may be a substrate. At least one of the inputs may be electrically connected to the other device.

[0133] Note that a flexible substrate may be used as the substrate 101. In the case of using a flexible substrate, a transistor, a capacitor, and the like may be directly formed on the flexible substrate. Transistors, capacitors, etc. are manufactured on another manufacturing substrate, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the substrate from the substrate to the flexible substrate, A peeling layer may be provided between the transistor, the capacitor, and the like.

[0134] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used for the substrate 101, the more environmentally friendly it is. The flexible substrate used for the substrate 101 has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less Examples of resins that can be used include polyester, polyolefin, and polyamide ( nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for use as a flexible substrate.

[0135] The insulating layer 102 may be made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride. aluminum oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicon oxide Materials selected from oxides, nitrides, etc. are used in a single layer or in a laminated form. A mixture of multiple materials, such as oxide, nitride, and oxynitride, may also be used. good.

[0136] In this specification, the term "nitride oxide" refers to a compound that contains more nitrogen than oxygen. In addition, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of is, for example, measured by Rutherford Backscattering (RBS) spectroscopy. Measurements can be made using techniques such as kScattering Spectrometry. .

[0137] In particular, the insulating layer 102 is preferably formed using an insulating material that is difficult for impurities to permeate. For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulating materials containing tungsten, neodymium, hafnium or tantalum are used in single or multi-layered configurations. For example, aluminum oxide and nitride are insulating materials that are difficult for impurities to penetrate. Aluminum, aluminum oxide nitride, aluminum oxide nitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Examples of the insulating layer 102 include tantalum oxide, tantalum oxide, and silicon nitride. For example, highly insulating indium tin zinc oxide (In-Sn-Zn oxide) can be used. good.

[0138] By using an insulating material that is difficult for impurities to penetrate for the insulating layer 102, impurities from the substrate 101 side are prevented from being generated. The diffusion of impurities can be suppressed, and the reliability of the transistor can be improved. By using an insulating material that is difficult for objects to penetrate, the diffusion of impurities from the insulating layer 111 side is suppressed. This makes it possible to improve the reliability of the transistor.

[0139] The insulating layer 102 may be formed by laminating a plurality of insulating layers made of these materials. The method for forming the edge layer 102 is not particularly limited, and may be a sputtering method, a CVD method, an MBE method, or the like. Various methods such as PLD, ALD, and spin coating can be used. The thickness of the insulating layer 102 and the insulating layer 110 is 10 nm to 500 nm, preferably 50 nm. It may be set to 300 nm or more.

[0140] For example, when aluminum oxide is formed as the insulating layer 102 by using a thermal CVD method, , a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA) ) as a raw material gas and H as an oxidizing agent. 2 Two types of gases are used: TMA and O. The chemical formula is Al(CH 3 ) 3 Other material liquids include tris(dimethylamine). Aluminum tris(2,2,6,6) -tetramethyl-3,5-heptanedionate).

[0141] The insulating layer 103 can be formed using a material and a method similar to those of the insulating layer 102. In order to prevent an increase in the hydrogen concentration in the oxide layer 104, the hydrogen concentration in the insulating layer 103 is reduced. Specifically, the hydrogen concentration in the insulating layer 103 is preferably reduced by SIMS. , 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Below or less, more preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 1 8 atoms / cm 3 In order to prevent an increase in the nitrogen concentration in the oxide semiconductor, It is preferable to reduce the nitrogen concentration in the insulating layer 103. The nitrogen concentration in the sample was 5×10 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0142] The insulating layer 103 is an insulating layer from which oxygen is released by heating (an insulating layer containing excess oxygen). It is preferable to form the film using a material that is free of oxygen atoms as determined by TDS analysis. The amount of oxygen released converted to atoms is 1.0 × 10 18 atoms / cm 3 Above, preferably 3. 0×10 20 atoms / cm 3 It is preferable to use an insulating layer having the above properties.

[0143] The insulating layer containing excess oxygen can also be formed by performing a process of adding oxygen to the insulating layer. The process of adding oxygen includes heat treatment in an oxygen atmosphere, ion implantation equipment, ion doping equipment, etc. The oxygen addition can be performed by using a doping device or a plasma treatment device. As a gas, 16 O 2 or 18 O 2 Such as oxygen gas, nitrous oxide gas or ozone In this specification, the process of adding oxygen is referred to as "oxygen doping." Also called "processing."

[0144] The thickness of the insulating layer 103 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. nm or less.

[0145] In this embodiment, a glass substrate is used as the substrate 101. Aluminum oxide is used. Silicon oxynitride containing excess oxygen is used as the insulating layer 103. Use .

[0146] Next, an oxide layer 124a and an oxide layer 124b are formed on the insulating layer 103 (FIG. 15 First, an oxide layer 124a is formed on the insulating layer 103, and the oxide layer 124a is An oxide layer 124b is formed thereon.

[0147] In this embodiment, the oxide layer 124a is formed by sputtering. CAA containing In, Ga, and Zn was used with a target having an atomic ratio of n=1:3:4. The oxide layer 124b is formed of In:Ga:Zn=1:1:1. The CAAC-OS containing In, Ga, and Zn was formed using a target with the atomic ratio of In, Ga, and Zn. In addition, an oxygen doping treatment may be performed after the oxide layer 124a is formed. After the formation of 124b, an oxygen doping treatment may be performed.

[0148] Next, impurities such as moisture or hydrogen contained in the oxide layer 124a and the oxide layer 124b are removed. In order to further reduce the amount of oxidation and to highly purify the oxide layers 124a and 124b, It is preferable to carry out a heat treatment.

[0149] For example, under a reduced pressure atmosphere, under an inert gas atmosphere such as nitrogen or a rare gas, under an oxidizing gas atmosphere, Or ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter is used. The moisture content measured at 20 ppm (-55°C in terms of dew point) or less, preferably 1 ppm m or less, preferably 10 ppb or less, of air, the oxide layer 124a and the oxide The layer 124b is subjected to a heat treatment. The oxidizing gas atmosphere is oxygen, ozone, or nitriding gas. An atmosphere containing 10 ppm or more of oxidizing gas such as oxygen. Also, it is called an inert gas atmosphere. The above-mentioned oxidizing gases are less than 10 ppm, and the gas is filled with nitrogen or rare gases. It means atmosphere.

[0150] In addition, by performing a heat treatment, the impurities are released and oxygen contained in the insulating layer 103 is removed. The oxide semiconductor layer 124a and the oxide layer 124b are diffused. It is possible to reduce oxygen deficiency. An atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to supplement the oxygen Note that the heat treatment may be performed by removing the oxide layer 124a and the oxide layer 124 For example, the oxide layer 104a and the oxide layer 104b may be formed at any time after the formation of the oxide layer 104a and the oxide layer 104b. The heat treatment may be performed after the formation of the oxide layer 104b. It's okay to be.

[0151] There is no particular limitation on the heating device used for the heat treatment. The apparatus may be an apparatus for heating the workpiece by heat radiation or heat generation. For example, an electric furnace or a LR furnace may be used. TA (Lamp Rapid Thermal Anneal) equipment, GRTA (Gas Rapid Thermal Annealing (RTA) equipment The LRTA device uses a halogen lamp, Metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium The light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps is used to heat the material being treated. The GRTA device is a device that uses high-temperature gas to perform heat treatment.

[0152] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will lead to a decrease in productivity. Therefore, it is not desirable.

[0153] Note that an oxygen doping treatment may be performed after the oxide layer 124a is formed. Alternatively, oxygen doping may be performed after the insulating layer 103 is formed. A processing step may be performed.

[0154] Next, a resist mask is formed on the oxide layer 124b (not shown). The formation of the layer can be carried out by appropriately using a photolithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by printing or inkjet printing, it is possible to use a photomask. Since no additional wiring is required, manufacturing costs can be reduced.

[0155] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. The exposed area (or the unexposed area) is resist-deposited using a developer. The light irradiated to the photosensitive resist is KrF excimer laser light, ArF These include excimer laser light and EUV (Extreme Ultraviolet) light. In addition, immersion technology is used, in which the space between the substrate and the projection lens is filled with liquid (e.g., water) for exposure. Also, instead of the light, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, the photomask is not required. The mask is removed using dry etching such as ashing or a dedicated stripping solution. Dry etching and wet etching can be used. Alternatively, both the sizing and sizing methods may be used.

[0156] Using the resist mask as a mask, the oxide layer 124b and a part of the oxide layer 124a are At this time, a part of the insulating layer 103 is removed, and a protrusion is formed on the insulating layer 103. In addition, the oxide layer 124b and the oxide layer 124a may be removed (etched). The etching method may be a dry etching method or a wet etching method, or both may be used. In this manner, island-shaped oxide layers 104a and 104b are formed (FIG. See 15(C). ).

[0157] When the conductive layer, the semiconductor layer, and the insulating layer are etched by dry etching, A gas containing a halogen element can be used as the mixing gas. An example of a gas is chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ) or carbon tetrachloride (CCl 4 ) and other chlorine-based gases, carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ) or trifluoromethane (C HF 3 Fluorine gases such as hydrogen bromide (HBr) or oxygen can be used appropriately. In addition, an inert gas may be added to the etching gas used. Methane (CH 4 ), ethane (C 2 H 6 ), propane (C 3 H 8 ), or butane (C 4 H 10 ) and other hydrocarbon gases A mixture of active gases may also be used.

[0158] In addition, the dry etching method is parallel plate type RIE (Reactive Ion Etching). tching) method, ICP (Inductively Coupled Plasma) : Inductively Coupled Plasma) method, DF-CCP (Dual Frequency Capac Dual Frequency Excitation Capacitively Coupled Plasma The etching conditions ( For example, the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, The electrode temperature, etc. can be adjusted appropriately.

[0159] Next, an oxide layer 104a, an oxide layer 104b, and an oxide layer 124c are formed on the insulating layer 103. Then, an insulating layer 125 is formed on the oxide layer 124c (see FIG. 15D). The oxide layer 124c can be formed using the same material and method as the oxide layer 124a. In addition, the insulating layer 125 can be formed using the same material and method as the insulating layer 103. The thickness of the layer 125 is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less. The thickness of the oxide layer 124c is preferably 5 nm or more and 10 nm or less, and more preferably 5 nm or more and 10 nm or less. Doping treatment may be performed. In addition, oxygen doping treatment may be performed after the insulating layer 125 is formed. In addition, heat treatment may be performed after the insulating layer 125 is formed. Form silicon oxide as 125.

[0160] Next, the conductive layer 126 is formed over the insulating layer 125 (see FIG. 16A). Conductive materials for forming the conductive layer include aluminum, chromium, copper, silver, gold, platinum, and tin. Ta, Nickel, Titanium, Molybdenum, Tungsten, Hafnium, Vanadium, Niobium One metal element selected from manganese, magnesium, zirconium, beryllium, etc. Materials containing the above can be used. In addition, polycrystalline silicon containing impurity elements such as phosphorus can be used. The material used is a semiconductor with high electrical conductivity, such as nickel silicide, The conductive layer 126 may be formed by stacking a plurality of conductive layers made of these materials. This is also fine.

[0161] In addition, the conductive layer 126 is made of indium tin oxide (ITO). e) Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials containing oxygen such as indium zinc oxide and silicon-doped indium tin oxide Conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may also be used. In addition, a laminated structure combining the material containing the above-mentioned metal element and a conductive material containing oxygen is provided. In addition, the above-mentioned material containing the metal element and the conductive material containing nitrogen can be combined. In addition, the above-mentioned materials containing metal elements and materials containing oxygen can be used as lamination structures. A laminated structure in which a conductive material and a conductive material containing nitrogen are combined may also be used.

[0162] The method for forming the conductive layer 126 is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various methods for forming the conductive layer 126 can be used. Preferably, the thickness is 20 nm or less and 300 nm or less, more preferably, 30 nm or more and 200 nm or less. In this embodiment, the conductive layer 126 is made of titanium nitride and tungsten. Specifically, a 10-nm-thick titanium nitride layer is laminated with a 150-nm-thick tangential layer. Form a sten.

[0163] Next, the insulating layer 127 is formed over the conductive layer 126 (see FIG. 16A). The insulating layer 127 can be formed of the same material and by the same method as the insulating layer 125. The thickness of the insulating layer 127 is , preferably from 5 nm to 100 nm, and more preferably from 10 nm to 50 nm.

[0164] Next, a resist mask is formed on the insulating layer 127 by photolithography or the like (see FIG. (not shown), insulating layer 127, conductive layer 126, insulating layer 125, and oxide layer 124c, A part of the insulating layer 107, the electrode 106, the insulating layer 105, and An oxide layer 104c is formed (see FIG. 16(B)). After that, the resist mask is removed. Etching of insulating layer 127, conductive layer 126, insulating layer 125, and oxide layer 124c The etching method may be a dry etching method or a wet etching method, or may be a combination of both.

[0165] Next, the dopant 131 is introduced using the electrode 106 and the insulating layer 107 as a mask. (See FIG. 16C.) In FIG. 16C, the dopant 131 is indicated by an arrow. The introduction of the dopant 131 can be performed by ion implantation, plasma doping, plasma treatment, or the like. In FIG. 16(C), the area where the dopant 131 is introduced is The end of the dopant 131 is shown by a dashed line. The concentration of the metal element contained in the region 135 can be determined by the processing method and processing conditions. Cut.

[0166] The elements used for the dopant 131 include aluminum, sulfur, titanium, magnesium, Uses one or more of the metal elements tungsten, arsenic, antimony, vanadium, etc. Also, elements other than those mentioned above may be used as the dopant 131. The dose of the dopant 131 is 1×10 12 ions / cm 2 More than 1×10 16 ion s / cm 2 Less than or equal to 1×10 13 ions / cm 2 More than 1×10 15 ions / cm 2 The acceleration voltage during the introduction of the dopant 131 is 5 kV or more and 50 kV or less. Preferably, the voltage is 10 kV or more and 30 kV or less. Tungsten is used as the material 31. The electrode 106 and the insulating layer 107 are used as a mask. When the dopant 131 is introduced, the region 135 is self-aligned adjacent to the channel forming region. It can be established as follows.

[0167] When the dopant 131 is introduced into the oxide layer 104, oxygen vacancies (also called “Vo”) are formed. When a metal element is used as the dopant 131, the metal element reacts with the oxygen contained in the oxide layer 104. The introduced dopants 131 are bonded to form a metal oxide. In the region (region 135) where the 04 dopant 131 is introduced, Vo increases.

[0168] When hydrogen (H) bonds to Vo to form VoH, the carrier density in the region increases, The resistivity is reduced. After the introduction of the dopant 131, a heat treatment may be performed. The treatment is preferably carried out at a temperature of 200° C. to 500° C., more preferably at a temperature of 300° C. to 450° C. The heat treatment is preferably carried out at a temperature of 350° C. or higher and 400° C. or lower. oH is more likely to be formed.

[0169] In addition, helium, neon, argon, krypton, xenon, and lanthanum are used as dopants 131. A rare gas element such as don may also be used.

[0170] In addition, when a metal element is used as the dopant 131, the element is It is preferable to use an element having a high electrical conductivity. For example, It is preferable that the oxide of the metal element is a metal oxide that can be regarded as a conductor or a semiconductor.

[0171] Region 135 in oxide layer 104 can function as a conductor or an n-type semiconductor. The region 135 in FIG. 04 is a region of the oxide layer 104 that overlaps with the electrode 106 (channel formation region). Therefore, the region 135 in the oxide layer 104 has a higher carrier density and a lower resistivity than the region 135 in the oxide layer 104. The resistance of the oxide layer 104 is lower than that of the region overlapping with the electrode 106 (channel forming region). There may be cases where this occurs.

[0172] In this embodiment, tungsten is used as the dopant 131. 31 is introduced into a part of the oxide layer 104 by ion implantation. As a result, a region containing tungsten oxide is formed in the oxide layer 104.

[0173] Next, the insulating layer 128 is formed (see FIG. 17(A)). The insulating layer 128 can be formed of the same material and by the same method as the oxide layer 10. 4c, which is thicker than the total thickness of the insulating layer 105, the electrode 106, and the insulating layer 107. It is preferable to do so.

[0174] In this embodiment, silicon oxide is formed as the insulating layer 128 by a CVD method.

[0175] Next, the insulating layer 128 is etched by anisotropic dry etching to expose the side of the electrode 106. A structure 108 is formed adjacent to the surface (see FIG. 17(B)). At times, portions of the oxide layer 104b are exposed.

[0176] At this time, a part of the exposed oxide layer 104b is etched, and the oxide layer 104 has a protruding portion. In some cases, an oxide layer 14b is formed. FIG. 21A shows a transistor 100 having a protrusion formed in a region 04b. 21(B) is a plan view of the star 100. Also, FIG. 21(B) is a plan view of the star 100 along the dashed line L1- L2 and a cross-sectional view taken along dashed line W1-W2.

[0177] Next, the conductive layer 129 is formed (see FIG. 17C). The conductive layer 129 can be formed of the same material and by the same method as the electrode 106. , preferably 5 nm or more and 500 nm or less, and more preferably 10 nm or more and 200 nm or less; The thickness of the conductive layer 129 is more preferably 15 nm or more and 100 nm or less. A 20 nm thick tungsten film is used.

[0178] Next, a portion of the conductive layer 129 is selectively removed by using a photolithography method or the like to form the electrode 1 18A. An insulating film is formed on the electrode 106. By providing the edge layer 107, the electrode 106 is removed when a part of the conductive layer 129 is removed. It can be protected from being removed.

[0179] At this time, the electrodes 109a and 109b are made of an oxide such as tungsten or titanium. When the electrode 109a and the electrode The V in the oxide layer 104 in contact with the oxide layer 109b increases. In the region 135, the carrier density in the region where the electrodes 109a and 109b contact is When hydrogen is bonded to Vo to form VoH, the The carrier density in the region is further increased, further decreasing the resistivity.

[0180] Therefore, the carrier density in the oxide layer 104 is higher than that in the region overlapping with the structure 108. The carrier density in the region where the pole 109a and the electrode 109b contact each other may become high. In the oxide layer 104, the resistivity of the region overlapping the structure 108 is higher than that of the electrode 109a and the structure 108. In addition, the resistivity of the region where the oxide layer 104 is in contact with the electrode 109b may become low. In the above, the resistance of the region where the electrodes 109a and 109b contact each other is higher than the resistance of the region where the electrodes 109a and 109b overlap each other. The resistance of the area may be lower.

[0181] Next, the insulating layer 110 is formed (see FIG. 18(B)). It can be formed of the same material and by the same method as the insulating layer 107. The insulating layer 110 is formed of silicon oxide by the CVD method.

[0182] Next, the insulating layer 111 is formed on the insulating layer 110 (see FIG. 18(C)). 1 can be formed using the same material and method as the insulating layer 127 (insulating layer 107). Note that the insulating layer 111 is preferably formed using an insulating material that is difficult for impurities to permeate. In this embodiment, the insulating layer 111 is formed of aluminum oxide by sputtering. In addition, a gas containing oxygen is used as the sputtering gas. When the insulating layer 111 is formed by this, the interface between the insulating layer 111 and the surface on which it is formed and the vicinity thereof are both Specifically, a mixed layer is formed at the interface between the insulating layer 111 and the insulating layer 110 and At and adjacent thereto, a mixed layer 145 is formed.

[0183] The mixed layer 145 contains a part of the sputtering gas. Since a gas containing oxygen is used as the tartering gas, the mixed layer 145 contains oxygen. Thus, the mixed layer 145 has excess oxygen.

[0184] Next, a heat treatment is performed. The heat treatment is preferably performed at a temperature of 200° C. or higher and 500° C. or lower, more preferably The temperature is preferably 300° C. or higher and 450° C. or lower, and more preferably 350° C. or higher and 400° C. or lower. The temperature of the heat treatment performed at this time is the same as that of the heat treatment performed after the introduction of the dopant 131. The temperature should be less than or equal to 100°C.

[0185] By the heat treatment, the excess oxygen contained in the mixed layer 145 is oxidized to the insulating layer 110, the structure 108, etc. The oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are diffused through the insulating layer 104a. By using materials that are difficult for oxygen to permeate as the edge layer 111 and the insulating layer 102, the mixed layer 1 The excess oxygen contained in 45 is absorbed into the oxide layer 104b via the insulating layer 110 and the structure 108. The excess oxygen in the mixed layer 145 can be effectively diffused into the mixed layer 145. This is indicated by an arrow in Figure 19.

[0186] Next, an insulating layer 112 is formed on the insulating layer 111. The insulating layer 112 has the same structure as the insulating layer 110. The insulating layer 112 can be formed by using a material and a method. Resins with heat resistance such as styrene resins, benzocyclobutene resins, polyamides, and epoxy resins. In addition to the above organic materials, low-dielectric-constant materials (low- k materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating multiple insulating layers made of these materials, , an insulating layer 112 may be formed.

[0187] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0188] The method for forming the insulating layer 112 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), printing The insulating layer 112 may be baked by a baking method (screen printing, offset printing, etc.). By combining this process with other heat treatment processes, it becomes possible to efficiently manufacture transistors. .

[0189] The surface of the insulating layer 112 is polished by chemical mechanical polishing (CMP). Polishing (CMP) processing may be performed. By performing the treatment, the unevenness of the sample surface is reduced, and the insulating layer and conductive layer that will be formed later are covered. The coverage can be improved.

[0190] Next, the insulating layer 112, the insulating layer 111, and the insulating layer 110 are formed by photolithography or the like. and an opening 126 overlapping a part of the electrode 109a by selectively removing a part of the insulating layer 107. a, an opening 126b overlapping a part of the electrode 109b, and an opening 126b overlapping a part of the electrode 106 26c is formed (see FIG. 20(A)). The removal (etching) of a portion of the insulating layer 107 can be performed by a dry etching method or a wet etching method. Anisotropic dry etching may be used, or both may be used. An opening with a large aspect ratio can be formed.

[0191] When the openings 126a, 126b, and 126c are formed, the electrodes 109a and The electrode 109b and a portion of the electrode 106 are removed, and the electrodes 109a, 109b, and A recess may be formed in the electrode 106 (see FIG. 21(B)).

[0192] Next, the contact plugs 113a are formed in the openings 126a, 126b, and 126c. , contact plug 113b, and contact plug 113c are formed. The plug 113a, the contact plug 113b, and the contact plug 113c are For example, a highly embeddable conductive material such as tungsten or polysilicon may be used. Although not shown, the side and bottom surfaces of the material may be covered with a titanium layer, a titanium nitride layer or the like. Alternatively, the barrier layer (diffusion prevention layer) may be formed by laminating these layers. In this case, the barrier layer These may also be referred to as electrodes.

[0193] Next, a conductive layer is formed on the insulating layer 112, and the conductive layer is then photolithographically removed. A part of the contact plug 113a is selectively removed to leave an electrode 114a overlapping the contact plug 113a and a contact plug An electrode 114b overlaps the contact plug 113b, and an electrode 114c overlaps the contact plug 113c. The conductive layer 4c is formed using the same material and method as the conductive layer 129. The method can be used to form the sintered body.

[0194] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0195] (Embodiment 3) Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, and nc-OS. (nanocrystalline oxide semiconductor), pseudo Amorphous-like Oxide Semiconductor (a-like OS) Examples include amorphous oxide semiconductors and amorphous oxide semiconductors.

[0196] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0197] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0198] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Therefore, its physical properties are similar to those of an amorphous oxide semiconductor.

[0199] [CAAC-OS] CAAC-OS is an oxide having multiple crystal parts (also called "pellets") aligned along the c-axis. It is one of the compound semiconductors.

[0200] Transmission Electron Microscope (TEM) A bright-field image and a diffraction pattern of CAAC-OS were obtained by a combined analysis ("High When observing a high-resolution TEM image, multiple pellets can be seen. On the other hand, high-resolution TEM images show that the boundaries between pellets, i.e., grain boundaries, Therefore, CAAC-OS is a crystal It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0201] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0202] FIG. 22(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 22(A). From FIG. 22(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the “formation surface”). ) or the unevenness of the top surface, and is parallel to the surface on which the CAAC-OS is formed or the top surface. .

[0203] As shown in Figure 22(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 22(B) and Figure 22(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0204] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 22(D)). The inclination between the pellets observed in FIG. 22(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0205] FIG. 23(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 23(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 23(B), Fig. 23(C), and Fig. 23(D), respectively. 23(D). From Fig. 23(B), Fig. 23(C) and Fig. 23(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0206] Next, the CA analyzed by X-ray diffraction (XRD) Explain AC-OS. For example, InGaZnO 4 CAAC-OS with crystals of When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 24(A). A peak may appear at a diffraction angle (2θ) of about 31°. nO 4 Since the crystal orientation of CAAC-OS is attributed to the (009) plane of the crystal, it is considered that the crystal of CAAC-OS has a c-axis orientation. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0207] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0208] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4 In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. And InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0209] Next, we will explain the CAAC-OS analyzed by electron diffraction. nO 4 For CAAC-OS with a crystal of 100 nm, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 25(A) is generated. This diffraction pattern is also called a "folded pattern." 4 The spots due to the (009) plane of the crystal are included. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the upper surface. On the other hand, the same specimen was subjected to a probing process perpendicular to the specimen surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident is shown in FIG. 25(B), a ring-shaped diffraction pattern is observed. Therefore, by electron diffraction, However, it was found that the a-axis and b-axis of the pellets contained in CAAC-OS did not have any orientation. In addition, the first ring in FIG. 25(B) is made of InGaZnO 4 The (010) face of the crystal This is thought to be due to the (100) plane and the like. The defect is thought to be due to the (110) surface.

[0210] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0211] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0212] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0213] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 pieces / cm 3 less than , and more preferably 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially intrinsic oxide semiconductor with low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0214] [nc-OS] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0215] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0216] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0217] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0218] [a-like OS] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. In a-like OS, porosity may be observed in high-resolution TEM images. In addition, in the high-resolution TEM image, there are areas where the crystals can be clearly seen and areas where the crystals can be clearly seen. and an area in which no crystal part can be confirmed.

[0219] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0220] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0221] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0222] The determination of which part is regarded as one crystal part can be made as follows. For example, InGaZnO 4 The unit cell of this crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the "d value") of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the stripes is 0.28 nm or more and 0.30 nm or less are called InGaZnO 4 Crystal part of The lattice fringes can be considered as InGaZnO 4 It corresponds to the ab plane of the crystal .

[0223] Figure 26 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown in FIG. 26 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 2.6 nm in the The cumulative electron dose for nc-OS and CAAC-OS was 4.2 × 1 0 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of In terms of the total electron dose, as shown in (2) and (3) in Fig. 26, the nc The sizes of the crystal parts of the -OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that the size is on the order of nm.

[0224] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0225] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0226] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, Single-crystal InGaZnO with a helical crystal structure 4 The density of is 6.357g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0227] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0228] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0229] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0230] (Embodiment 4) In this embodiment, an example of a semiconductor device using a transistor disclosed in this specification will be described. He explains.

[0231] 27(A) to 27(C) are cross-sectional views of the semiconductor device 400. The transistor 100 and the transistor 281 are included. It is possible to replace it with other transistors shown in the above embodiment. 27(A) is a cross-sectional view of the transistor 100 and the transistor 281 in the channel length direction, and FIG. FIG. 27C is a cross-sectional view in the channel width direction of the transistor 281 in FIG. FIG.

[0232] The semiconductor device 400 uses an n-type semiconductor as a substrate 401. A channel forming region 283, a high concentration p-type impurity region 285, an insulating layer 286, an electrode 287, and a structure A low concentration p-type The impurity region 284 is provided. The insulating layer 286 can function as a gate insulating layer. The transistor 281 has a channel forming region 283 formed on a substrate. It forms part of 401.

[0233] The low concentration p-type impurity region 284 is formed by forming the electrode 287 after forming the electrode 287 and before forming the structure 288. The impurity element is introduced by using the mask as the mask. The low concentration p-type impurity region 284 can be formed by self-alignment. After the formation of the low concentration p-type impurity region 288, the high concentration p-type impurity region 285 is formed. 4 has the same conductivity type as the high concentration p-type impurity region 285, and the concentration of the impurity that gives the conductivity type is The low concentration p-type impurity region 284 is lower than the high concentration p-type impurity region 285. In some cases, it may not be necessary to provide it.

[0234] The transistor 281 is electrically isolated from other transistors by an element isolation layer 414. The element isolation region is formed by the LOCOS method (Local Oxidation of Silicon). silicon) and STI (Shallow Trench Isolation) etc. can be used.

[0235] The transistor 281 can function as a p-channel transistor. An insulating layer 403 is formed on the capacitor 281, and an insulating layer 404 is formed on the insulating layer 403. The insulating layer 403 and the insulating layer 404 are formed using the same material and method as the insulating layer 111. Note that the insulating layers 403 and 404 can be resistant to oxygen, hydrogen, water, and alkali. It is formed using insulating materials that have the function of preventing the diffusion of impurities such as metals and alkaline earth metals. It is preferable that either the insulating layer 403 or the insulating layer 404 be omitted. An insulating layer may be further laminated.

[0236] The semiconductor device 400 also has an insulating layer 405 having a flat surface on the insulating layer 404. The insulating layer 405 can be formed using a material and a method similar to those of the insulating layer 112. The surface of the insulating layer 405 may be subjected to CMP treatment.

[0237] In addition, an electrode 413a, an electrode 413b, and an electrode 413c are formed on the insulating layer 405. The electrodes 413a, 413b, and 413c are similar to the electrode 109a. It can be made using materials and methods.

[0238] The electrode 413a is connected to the high concentration p-type impurity region 285 via a contact plug 406a. The electrode 413b is electrically connected to one of the electrodes via a contact plug 406b. The electrode 413c is electrically connected to the other of the p-type impurity regions 285. It is electrically connected to the electrode 287 via the lug 406c.

[0239] An insulating layer 407 is formed to cover the electrodes 413a, 413b, and 413c. The insulating layer 407 can be formed using the same material and method as the insulating layer 405. In addition, the surface of the insulating layer 407 may be subjected to CMP treatment.

[0240] In addition, the insulating layer 102 is formed on the insulating layer 407. This can be understood by taking into consideration the above embodiment. The electrode 109b is connected to the electrode 413b via the contact plug 112d. and is electrically connected to

[0241] <Variation 1> An n-channel transistor may be provided on the substrate 401. FIG. 8(B) is a cross-sectional view of the semiconductor device 410. The semiconductor device 410 is a semiconductor device 400 The transistor 282 is an n-channel type transistor. 1 is a cross-sectional view of the transistor 100, the transistor 281, and the transistor 282 in the channel length direction. 28(B) is an enlarged view of transistor 282.

[0242] In the transistor 282, a channel forming region 1283 is formed in the well 220. The transistor 282 includes a channel forming region 1283, a high concentration n-type impurity region 1285, and an insulating layer. The insulating layer 286 is disposed between the insulating layer 286 and the structure 288. A low concentration n-type impurity region 1284 is provided in the region overlapping with 88 .

[0243] The low concentration n-type impurity region 1284 is formed by forming the electrode 287 and before forming the structure 288. 7 as a mask to introduce impurity elements. That is, the low concentration n-type impurity region 1284 can be formed by self-alignment. After the formation of 88, a high concentration n-type impurity region 1285 is formed. 1284 has the same conductivity type as the high concentration n-type impurity region 1285, and is an impurity that imparts the conductivity type. The concentration of the low concentration n-type impurity region 128 is lower than that of the high concentration n-type impurity region 1285. Item 4 may not be provided depending on the circumstances.

[0244] <Variation 2> A further transistor 100 may be provided above the transistor 100. 4 is a cross-sectional view of a semiconductor device 420. The semiconductor device 420 is a semiconductor device having a transistor on the semiconductor device 410. The transistor 100a has a similar configuration to the transistor 100. The transistor 100a The insulating layer 407a is provided on the insulating layer 112, and the insulating layer 102a is provided therebetween. The insulating layer 407a and the insulating layer 102a are made of the same material as the insulating layer 407 and the insulating layer 102, respectively. The transistor 100a can be provided by any of the following materials and methods. It can be prepared in the same manner as above.

[0245] The semiconductor device 420 also includes a capacitance element 141 and a capacitance element 142. One electrode 413c constituting 41 is used to form electrodes 413a and 413b. The electrode 413a and the electrode 413b can be provided in the same layer by using a part of the conductive layer. The other electrode 109c constituting the capacitor 141 is connected to the electrode 109a and the electrode 109b. The same layer as the electrodes 109a and 109b is formed by using a part of the conductive layer for forming the electrodes 109a and 109b. The insulating layer between the electrode 109c and the electrode 413c can be provided as a layer. 41 can function as a dielectric layer.

[0246] <Variation 3> 30(A) to 30(C) are cross-sectional views of the semiconductor device 430. The semiconductor device 430 is The transistor 281 of the semiconductor device 400 is replaced with a Fin-type transistor 291. By using a fin-type transistor, the effective channel width The on-state characteristics of the transistor can be improved. Since the contribution of the electric field of the gate electrode to the can be improved.

[0247] [Semiconductor Circuits] The transistor disclosed in the present specification and the like is used in an OR circuit, an AND circuit, a NAND circuit, and an N Logic circuits such as OR circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits, It can be used in various semiconductor circuits such as integrating circuits, differentiating circuits, and memory elements.

[0248] In this embodiment, a peripheral circuit and a pixel circuit will be described with reference to FIGS. An example of a CMOS circuit that can be used is shown below. In the diagrams, etc., it is preferable to use OS transistors in the circuit symbols of transistors. It is marked with "OS."

[0249] The CMOS circuit shown in FIG. 31(A) includes a p-channel transistor 281 and an n-channel The transistors 282 are connected in series and the gates of the transistors 282 are connected to each other. 2 shows an example of a circuit configuration.

[0250] The CMOS circuit shown in FIG. 31B includes a p-channel transistor 281 and an n-channel 2 shows an example of the configuration of an analog switch circuit in which the above transistors 282 are connected in parallel.

[0251] The CMOS circuit shown in FIG. 31C includes a transistor 281a, a transistor 281b, 1 shows an example of a configuration of a NAND circuit using a transistor 282a and a transistor 282b. The NAND circuit is a combination of the potentials input to the input terminals IN_A and IN_B. The output potential changes depending on the combination.

[0252] [Storage device] In the circuit shown in FIG. 32(A), one of the source and drain of the transistor 289 is connected to a transistor A memory device structure in which the gate of the transistor 1281 and one electrode of the capacitance element 257 are connected In addition, the circuit shown in FIG. FIG. 1 shows an example of the configuration of a memory device in which one of the drains is connected to one of the electrodes of a capacitor 257. do.

[0253] The circuits shown in FIG. 32(A) and FIG. 32(B) are the source or drain of the transistor 289. The charge input from the other input can be held at node 256. By using an OS transistor for 289, the charge of node 256 can be held for a long period of time. It is possible.

[0254] In FIG. 32A, a p-channel transistor is shown as a transistor 1281. However, an n-channel transistor may be used. Alternatively, the transistor 281 or the transistor 282 may be used. An OS transistor may be used as 1281.

[0255] Here, the semiconductor device (memory device) shown in FIG. 32(A) and FIG. 32(B) will be described in detail. Let me explain in detail.

[0256] The semiconductor device shown in FIG. 32A includes a transistor 1281 using a first semiconductor and a The semiconductor device includes a transistor 289 and a capacitor 257 .

[0257] The transistor 289 is an OS transistor as described in the above embodiment. The small off-current of the capacitor 289 allows long-term storage in a specific node of the semiconductor device. It is possible to retain the contents, i.e., no refresh operation is required or It is possible to reduce the frequency of refresh operations to an extremely low level, resulting in a semiconductor with low power consumption. It becomes a device.

[0258] In FIG. 32A, a wiring 251 is a source or drain of a transistor 1281. The wiring 252 is electrically connected to the other of the source and drain of the transistor 1281. The wiring 253 is electrically connected to the source or drain of the transistor 289. The wiring 254 is electrically connected to the gate of the transistor 289. The gate of the transistor 1281, the source of the transistor 289, or One of the drains and one of the electrodes of the capacitor 257 are electrically connected to a node 256. In addition, the wiring 255 is electrically connected to the other electrode of the capacitor 257.

[0259] The semiconductor device shown in FIG. 32A has a characteristic of being able to hold charge applied to the node 256. By having this, it is possible to write, hold, and read information, as shown below.

[0260] [Write operation, hold operation] The writing and holding of data will be described. First, the potential of the wiring 254 is changed by the transistor 289 is turned on. As a result, the potential of the wiring 253 is set to the node 256. That is, a predetermined charge is applied to node 256 (write). The charges that give two different potential levels (hereinafter, "Low-level charge" and "High-level charge") Then, the potential of the wiring 254 is changed to the potential of the transistor. By setting the node 256 to a potential at which the transistor 289 is turned off, a charge is held in the node 256 .

[0261] Note that the high level charge provides a higher potential to the node 256 than the low level charge. In addition, when a p-channel transistor is used as the transistor 1281, Both the high-level charge and the low-level charge are greater than the threshold voltage of the transistor. The charge is set to a value that gives a higher potential than the charge of the transistor 1281. When a transistor is used, both the high-level charge and the low-level charge are The potential is lower than the threshold voltage of the transistor. Both of the charge levels are charges that provide a potential that turns off the transistor.

[0262] Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is maintained for a long period of time. It is held as such.

[0263] [Read operation] Next, reading of information will be described. A predetermined potential different from the potential of the wiring 252 is applied to the wiring 251. With a constant potential applied, the wire 255 is supplied with a read potential V R Given node 256, The information stored in the

[0264] The potential given by the high-level charge is V H , the voltage given by the low level charge V rank L Then, the read potential V Ris {(Vth-V H )+(Vth+V L )} / 2 When data is not being read, the potential of the wiring 255 is set to the transistor If a p-channel transistor is used in the 1281, V H A higher potential is used, and the transistor If an n-channel transistor is used for the 1281, V L If we use a lower potential, stomach.

[0265] For example, when a p-channel transistor is used as the transistor 1281, The Vth of the 1281 is -2V, and the V H 1V, V L If we set it to -1V, then V R -2V The potential written to node 256 is V H When V is connected to wire 255, R Given When this voltage is applied to the gate of transistor 1281, V R +V H , i.e. -1V is applied. Since -1V is higher than Vth, the transistor 1281 is not turned on. The potential of the wiring 252 does not change. L When Wiring 255 to V R is applied to the gate of transistor 1281. R +V L , i.e. Since -3V is lower than Vth, transistor 1281 is turned on. As a result, the potential of the wiring 252 changes.

[0266] In addition, when an n-channel transistor is used as the transistor 1281, The Vth of the 1281 is 2V, and the V H 1V, V LIf we set it to -1V, then V R Let's set it to 2V. The potential written to node 256 is V H When V is connected to wire 255, R is given and V is applied to the gate of transistor 1281. R +V H , i.e. 3V is applied. 3V is V th, the transistor 1281 is turned on. The potential written to node 256 changes. L When V is connected to wire 255, R is applied to the gate of transistor 1281. R +V L , i.e. 1V is applied. Since 1V is lower than Vth, the transistor 1281 does not turn on. Therefore, the potential of the wiring 252 does not change.

[0267] By determining the potential of the wiring 252, the data stored in the node 256 can be read out. can be done.

[0268] The semiconductor device shown in FIG. 32B differs from the semiconductor device shown in FIG. 32A in that it does not include the transistor 1281. In this case, the operation is the same as that of the semiconductor device shown in FIG. It is possible to write and retain more information.

[0269] The reading of data in the semiconductor device shown in FIG. 32B will be described. When a potential that turns on the transistor 289 is applied to the wiring 253, which is in a floating state, and the capacitor 257 are electrically connected, and charge is redistributed between the wiring 253 and the capacitor 257 . As a result, the potential of the wiring 253 changes. The amount of change in the potential of the wiring 253 is Depending on the potential (or charge stored at node 256), it can take on different values.

[0270] For example, the potential of the node 256 is V, the capacitance of the capacitor 257 is C, and the capacitance of the wiring 253 is If the component is CB and the potential of the wiring 253 before the charge is redistributed is VB0, The potential of the wiring 253 after the power supply is turned on is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is such that the potential of the node 256 is V1 and V0 (V1>V0). If we assume two states, the potential of the wiring 253 when the potential V1 is held (=(CB× VB0+C×V1) / (CB+C) is the voltage of the wire 253 when the potential V0 is maintained. It can be seen that the value is higher than the value (=(CB×VB0+C×V0) / (CB+C)).

[0271] Then, by comparing the potential of the wiring 253 with a predetermined potential, information can be read out. .

[0272] The above-described semiconductor device includes a transistor including an oxide semiconductor and having an extremely low off-state current. By applying this, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary or can be performed very infrequently. Since the power supply can be reduced, a semiconductor device with low power consumption can be realized. Even if there is no potential (but the potential is preferably fixed), It is possible to retain the stored contents.

[0273] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the above-mentioned problems. There is no limit to the number of times that data can be rewritten, which is an issue with semiconductors, and reliability has been dramatically improved. Furthermore, information can be written depending on whether the transistor is conductive or non-conductive. This allows high speed operation.

[0274] 〔CPU〕 In this embodiment, a semiconductor device using the above-described transistor will be described with reference to a CPU. FIG. 33 is a block diagram showing an example of a CPU configuration that uses the above-mentioned transistor in part. FIG.

[0275] The CPU shown in FIG. 33 includes an ALU 1191 (ALU: Arithmetic logic unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 33 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 33 is regarded as one core, and a multi-core processor including multiple cores is used. Alternatively, the CPU may be configured to operate each core in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It may be a bit, etc.

[0276] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0277] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0278] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0279] In the CPU shown in FIG. 33, a register 1196 is provided with a memory cell. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0280] In the CPU shown in FIG. 33, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the storage element in register 1196 . When data retention in the capacitive element is selected, data rewrite to the capacitive element is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0281] FIG. 34 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 730 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706. The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708, a transistor 709, and a transistor 710. 730 may include other elements such as diodes, resistors, inductors, etc., as needed. It may also have.

[0282] Here, the circuit 702 can use the above-mentioned storage device. When the supply of the power supply voltage is stopped, the gate of the transistor 709 in the circuit 702 is supplied with the ground potential ( 0 V), or a potential at which the transistor 709 is turned off is continuously input. The gate of the transistor 709 is grounded via a load such as a resistor.

[0283] The switch 703 is configured using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is of the opposite conductivity type to the transistor 713 (e.g., p-channel type Here, the first terminal of the switch 703 is The terminal corresponds to one of the source and drain of the transistor 713, and the second terminal of the switch 703. The resistor 702 corresponds to the other of the source and drain of the transistor 713, and the switch 703 corresponds to the other of the source and drain of the transistor 713. A control signal RD input to the gate of the transistor 713 controls the voltage between the first terminal and the second terminal. Conduction or non-conduction (i.e., the on or off state of transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The switch 704 is turned on by a control signal RD input to the gate of the transistor 714. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on-state of the transistor 714) ON or OFF state) is selected.

[0284] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. On the other hand, the transistor 710 is electrically connected to the gate of the transistor 710. One of the source and drain of the transistor 710 is connected to a low power supply potential. The other is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703. The first terminal (one of the source and drain of the transistor 713) is electrically connected to the first terminal (one of the source and drain of the transistor 713). The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is 704 (one of the source and drain of the transistor 714). The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is The switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. 2 terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704 A terminal (either the source or drain of the transistor 714) and an input terminal of the logic element 706 The connection portion is electrically connected to one of a pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential (V DD, etc.) can be input to the other of the pair of electrodes of the capacitor 707. The other side is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 is supplied with a low power supply potential. The signal is electrically connected to a wiring (for example, a GND line) that can supply a signal.

[0285] Note that the capacitors 707 and 708 are formed by actively reducing the parasitic capacitance of transistors and wirings. It is also possible to omit it by using it in a more practical way.

[0286] A control signal WE is input to the gate electrode of the transistor 709. The switch 704 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive or non-conductive state between the terminals is selected, and the first terminal and the second terminal of one switch are connected to each other. When the terminals are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. become.

[0287] The other of the source and drain of the transistor 709 is connected to a data input terminal of the circuit 701. In FIG. 34, a signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other of the source and drain of the transistor 713 is 6, the logical value of which is inverted to become an inverted signal, and the inverted signal is input to the circuit 701 via the circuit 720. Be encouraged.

[0288] In FIG. 34, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input terminal is input to the circuit 701 via the logic element 706 and the circuit 720. The second terminal of the switch 703 (transistor The signal output from the other of the source and drain of the transistor 713 can be inverted in logical value. For example, the signal input from the input terminal may be input to the circuit 701. When there is a node that holds a signal with the logic value of the signal that has been inverted, the switch 703 The signal output from the second terminal (the other of the source and drain of the transistor 713) is The node can be input.

[0289] The transistor 709 in FIG. 34 is the same as the transistor 150 illustrated in the first embodiment. A control signal WE can be input to the gate electrode, and a back gate electrode A control signal WE2 can be input to the control signal WE2. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the source potential of the transistor 709. The control signal WE2 is set to a potential smaller than the threshold potential of the transistor 709. This is a potential signal for controlling the value voltage. When the gate voltage of the transistor 709 is 0V, The drain current of the transistor 709 can be further reduced. It is also possible to use transistors without gates.

[0290] In addition, in FIG. 34, among the transistors used in the memory element 730, the transistor The transistors other than 709 are formed on a layer or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon transistor in which a channel is formed. The memory element 73 may be a transistor in which a channel is formed in a conductive substrate. All the transistors used in 0 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 730 may be a transistor other than the transistor 709. The transistors are classified into a transistor in which a channel is formed using an oxide semiconductor layer and a transistor in which a channel is formed using a semiconductor layer other than an oxide semiconductor. A transistor having a channel formed in a conductive layer or substrate 1190 is combined with the It may be used.

[0291] For example, a flip-flop circuit can be used for the circuit 701 in FIG. In addition, the logic element 706 may be, for example, an inverter or a clocked inverter. can be done.

[0292] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 730, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. The data can be stored in node M2.

[0293] As described above, a transistor in which a channel is formed in an oxide semiconductor layer has a low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-current is significantly higher than that of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 709, Even when the power supply voltage is not supplied to the memory element 730, the signal held in the capacitor element 708 is retained for a long time. In this way, the memory element 730 retains the stored data even when the supply of the power supply voltage is stopped. It is possible to retain data.

[0294] In addition, by providing the switches 703 and 704, after the power supply voltage is resumed, Furthermore, the time required for the circuit 701 to hold the original data again can be shortened.

[0295] In the circuit 702, the signal held at node M2 ​​is fed to the gate of transistor 710. Therefore, after the supply of the power supply voltage to the storage element 730 is resumed, the node M 2 to the state (on or off) of transistor 710. Therefore, the signal held at node M2 ​​can be read out from the circuit 702. Even if the corresponding potential fluctuates slightly, the original signal can still be read out accurately.

[0296] Such a memory element 730 may be a memory device such as a register or cache memory of a CPU. By using this in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the device can quickly return to the state it was in before the power supply was stopped. Therefore, the entire CPU, or one or more logical circuits that make up the CPU, This allows for short-term power outages on roads, and increases the frequency of power outages. , power consumption can be reduced.

[0297] In this embodiment, the memory element 730 is used as a CPU. 0 is DSP (Digital Signal Processor), custom LSI , PLD (Programmable Logic Device) and other LSIs, RF ( It can also be applied to Radio Frequency (RF) tags.

[0298] [Imaging device] An imaging device will be described as an example of a semiconductor device including the above-described transistor.

[0299] <Configuration example of imaging device 600> 35A is a plan view showing a configuration example of an imaging device 600. The imaging device 600 has a pixel 621, the first circuit 260, the second circuit 270, the third circuit 280, and the fourth circuit In this specification, the first circuit 260 to the fourth circuit 290 These may be referred to as "peripheral circuits" or "drive circuits." For example, the first circuit 260 can be considered part of the peripheral circuit.

[0300] 35B is a diagram showing a configuration example of the pixel section 621. The pixel section 621 has p columns and q rows (p and q is a natural number equal to or greater than 2), a plurality of pixels 622 (imaging element) arranged in a matrix. In FIG. 35B, n is a natural number between 1 and p, and m is a natural number between 1 and q. is a natural number.

[0301] For example, if the pixels 622 are arranged in a 1920 x 1080 matrix, a so-called full-width Resolution of 1080p (also called "2K resolution", "2K1K", "2K", etc.) It is possible to realize an imaging device 600 capable of capturing an image. When arranged in a 6 x 2160 matrix, it becomes what is known as ultra-high definition (4K resolution). An imaging device 60 capable of imaging at a resolution of 1080p (1080p), which is also called "4K2K" or "4K" 0 can be realized. For example, pixel 622 can be arranged in a matrix of 8192 x 4320. When arranged in a grid, it produces what is known as super high-definition (8K resolution, 8K4K, It is possible to realize an imaging device 600 capable of capturing images at a resolution of 1080p (also called 8K). By increasing the number of display elements, an imaging device 600 capable of imaging at a resolution of 16K or 32K can be realized. It is also possible to realize

[0302] The first circuit 260 and the second circuit 270 are connected to a plurality of pixels 622 and The first circuit 260 has a function of supplying a signal for driving the pixel 6. The third circuit may have a function of processing the analog signal output from the second circuit. 280 may have a function of controlling the operation timing of peripheral circuits. The clock signal may be generated by the external clock. The third circuit 280 may have a function of converting a frequency. (e.g., a ramp signal, etc.) may be provided.

[0303] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier circuit, or a converter circuit. The transistors and the like used in the peripheral circuits are connected to the pixel driving circuit 61, which will be described later. It may be formed by using a part of the semiconductor formed to fabricate 0. A semiconductor device such as an IC may be used in part or in whole.

[0304] In addition, the peripheral circuits may be omitted from among the first circuit 260 to the fourth circuit 290. For example, the function of either the first circuit 260 or the fourth circuit 290 may be omitted. In addition to the other of the first circuit 260 or the fourth circuit 290, One of the circuits 290 may be omitted. Also, for example, the second circuit 270 or the third circuit The function of one of the circuits 270 and 280 is added to the other of the second circuit 270 or the third circuit 280. Either the second circuit 270 or the third circuit 280 may be omitted. Adding the functions of other peripheral circuits to any one of the circuits 260 to 290 Other peripheral circuits may be omitted.

[0305] As shown in FIG. 36, the first circuit 260 to the fourth circuit 261 are arranged along the outer periphery of the pixel portion 621. In addition, in a pixel portion 621 of the imaging device 600, a pixel 62 By arranging the pixels 622 at an angle, the row direction and the column direction can be This allows the pixel interval (pitch) in the direction to be shortened. This can improve the quality of the captured image.

[0306] In addition, as shown in FIG. 37, a pixel 37A shows an upper part of the first circuit 260 to the fourth circuit 290. 37B is a top view of an imaging device 600 in which a pixel portion 621 is formed on the substrate 610. 37(A) is a perspective view for explaining the configuration of the imaging device 600 shown in FIG.

[0307] By providing the pixel portion 621 above the first circuit 260 to the fourth circuit 290, The area occupied by the pixel section 621 relative to the size of the image device 600 can be increased. This can improve the light receiving sensitivity of the imaging device 600. In addition, the resolution of the imaging device 600 can be improved. In addition, the reproducibility of the image captured by the imaging device 600 can be improved. The integration density of the imaging device 600 can be improved.

[0308] [Color filters, etc.] The pixels 622 included in the imaging device 600 are used as sub-pixels, and each of the pixels 622 By providing filters (color filters) that transmit light of different wavelengths, a color image display can be It is possible to obtain information to realize the display.

[0309] FIG. 38(A) is a plan view showing an example of a pixel 623 for acquiring a color image. 38(A) is a pixel 622 provided with a color filter that transmits light in the red (R) wavelength range. (hereinafter, also referred to as "pixel 622R"), a color filter that transmits light in the green (G) wavelength range A pixel 622 (hereinafter also referred to as “pixel 622G”) in which A pixel 622 (hereinafter also referred to as "pixel 622B") provided with a light-transmitting color filter. The pixels 622R, 622G, and 622B are grouped together as a single pixel 623. and make it function.

[0310] The color filters used in the pixel 623 are limited to red (R), green (G), and blue (B). First, a color filter that transmits cyan (C), yellow (Y), and magenta (M) light is used. A pixel 623 may detect light in at least three different wavelength ranges. By providing 2, a full-color image can be obtained.

[0311] FIG. 38(B) shows a color filter that transmits red (R), green (G), and blue (B) light, respectively. In addition to the pixel 622 having the color filter, a color filter that transmits yellow (Y) light is provided. FIG. 38(C) illustrates a pixel 623 having a pixel 622 that is cyan ( C), pixel 6 provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition to the pixel 22, the pixel 622 has a color filter that transmits blue (B) light. A pixel 623 is illustrated. A single pixel 623 is configured to detect light of four or more different wavelength ranges. By providing the pixel 622, the color reproducibility of the acquired image can be further improved.

[0312] In addition, the pixel number ratio (or light receiving area ratio) of the pixel 622R, the pixel 622G, and the pixel 622B ) does not necessarily have to be 1:1:1. The light area ratio may be a Bayer array of red:green:blue = 1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0313] Although the number of pixels 622 used for the pixel 623 may be one, it is preferable to use two or more. For example, By providing two or more pixels 622 that detect light in the same wavelength range, redundancy is increased, and the imaging device It can improve the reliability of the 600.

[0314] In addition, it acts as a filter by absorbing or reflecting light with wavelengths shorter than those of visible light, and by blocking infrared light. By using an IR (IR: Infrared) filter that transmits infrared light, infrared light is detected. It is possible to realize an imaging device 600. In addition, a filter having a wavelength longer than the wavelength of visible light can be used. UV (Ultra Viol) et) By using a filter, an imaging device 600 that detects ultraviolet light can be realized. In addition, a scintillator that converts radiation into ultraviolet light or visible light is used as a filter. In this way, the imaging device 600 can function as a radiation detector for detecting X-rays, gamma rays, etc. can.

[0315] In addition, ND (Neutral Density) filters (light reducing filters) are also available. When a large amount of light is incident on the photoelectric conversion element (light receiving element), This can prevent the phenomenon of output saturation (hereinafter also referred to as "output saturation"). By combining ND filters with different amounts of light, the dynamic range of the imaging device can be expanded. It can be made bigger.

[0316] In addition to the above-mentioned filter, a lens may be provided in the pixel 622. An example of the arrangement of the pixel 622, the filter 624, and the lens 625 will be described with reference to a cross-sectional view. By providing the lens 625, the incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in FIG. 39(A), a lens 625 and a filter 626 are formed in a pixel 622. 24 (filter 624R, filter 624G, filter 624B), and the pixel driving circuit A structure in which light 660 is incident on the photoelectric conversion element 601 through 610 or the like can be used.

[0317] However, as shown in the area surrounded by the two-dot chain line, a part of the light 660 indicated by the arrow is connected to the wiring group 626. The light may be blocked by parts of the Therefore, as shown in FIG. 39(B), a lens 625 and A filter 624 is formed to allow the photoelectric conversion element 601 to efficiently receive incident light. By irradiating light 660 from the photoelectric conversion element 601 side, imaging with high light reception sensitivity can be performed. An apparatus 600 can be provided.

[0318] 40(A) to 40(C) show a pixel driving circuit 61 that can be used in the pixel section 621. 40A shows an example of a pixel driver circuit 610 including a transistor 602, a transistor The photoelectric conversion element 601 includes a transistor 604 and a capacitor 606 , and is connected to the photoelectric conversion element 601 . One of the source and drain of the transistor 602 is electrically connected to the photoelectric conversion element 601. The other of the source and drain of the transistor 602 is connected to a node 607 (charge storage portion). The transistor 604 is electrically connected to the gate of the transistor 604 via a ground potential.

[0319] The transistor 602 is preferably an OS transistor. Since the off-current can be made extremely small, the capacitor 606 can be made small. Alternatively, as shown in FIG. 40(B), the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, the potential of the node 607 changes. Therefore, it is possible to realize an imaging device that is less susceptible to the effects of noise. The transistor 604 may be an OS transistor.

[0320] The photoelectric conversion element 601 is a diode in which a pn-type or pin-type junction is formed on a silicon substrate. Alternatively, an amorphous silicon film or a microcrystalline silicon film may be used. Alternatively, a diode-connected transformer may be used. A variable resistor utilizing the photoelectric effect may also be used. It may be formed using tungsten, selenium, etc.

[0321] In addition, materials capable of absorbing radiation and generating electric charges are used as photoelectric conversion elements. The material capable of absorbing radiation and generating a charge may be iodine. Examples include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0322] The pixel driving circuit 610 shown in FIG. A photoelectric conversion element including a transistor 604, a transistor 605, and a capacitor 606. 40C is connected to a pixel driving circuit 601. The figure shows a case where a photodiode is used as the transistor 601. One of the gate and drain is electrically connected to the cathode of the photoelectric conversion element 601, and the other is The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. The source or drain of the transistor 603 is electrically connected to the node 6 The other end is electrically connected to a wiring 608. The gate of the transistor 604 is electrically connected to the node 607, and either the source or the drain is connected to the wiring 6 09, and the other is electrically connected to one of the source and drain of the transistor 605. The other of the source and drain of the transistor 605 is electrically connected to a wiring 608. One electrode of the capacitor 606 is electrically connected to a node 607. The other electrode is electrically connected to a wiring 611 .

[0323] The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 functions as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. Moreover, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0324] Next, the operation of the pixel driving circuit 610 shown in FIG. The starter 603 is turned on, and VDD is supplied to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held at the node 607. When the transistor 602 is turned on, the photoelectric conversion element 601 receives a light amount The potential of the node 607 changes (storage operation). Then, the transistor 602 is turned off. Then, the potential of the node 607 is held. Next, when the transistor 605 is turned on, A potential corresponding to the potential of the node 607 is output to the wiring 609 (selection operation). By detecting the potential, the amount of light received by the photoelectric conversion element 601 can be known.

[0325] The transistors 602 and 603 are preferably OS transistors. As described above, the off-state current of an OS transistor can be extremely small. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. In addition, the transistors 602 and 603 can be OS transistors. When the potential of the node 607 is used, the potential of the node 607 is unlikely to fluctuate. It is possible to realize an imaging device.

[0326] A pixel 62 using any one of the pixel driving circuits 610 shown in FIG. 40(A) to FIG. 40(C) By arranging 2 in a matrix, a high-resolution imaging device can be realized.

[0327] For example, when the pixel driving circuits 610 are arranged in a 1920×1080 matrix, Full HD (also called "2K resolution", "2K1K", "2K") It is possible to realize an imaging device capable of imaging with a resolution. When 0 is arranged in a 4096 x 2160 matrix, it becomes what is known as Ultra Hi-Vision ( It is also called "4K resolution," "4K2K," or "4K." For example, the pixel driving circuit 610 can be used to realize an 8192×432 When arranged in a matrix of 0, it becomes what is known as super high vision ("8K resolution" or "8 To realize an imaging device capable of capturing images at a resolution of 1080p (also called "4K", "8K", etc.) By increasing the number of pixel driving circuits 610, it is possible to realize a camera capable of capturing images at a resolution of 16K or 32K. It is also possible to realize an imaging device.

[0328] A structural example of a pixel 622 using the above-mentioned transistor is shown in FIG. FIG.

[0329] The pixel 622 shown in FIG. 41 uses an n-type semiconductor as the substrate 401. The p-type semiconductor 221 of the photoelectric conversion element 601 is provided in the substrate 401. The portion functions as the n-type semiconductor 223 of the photoelectric conversion element 601 .

[0330] The transistor 604 is provided on the substrate 401. In addition, a p-type semiconductor wafer is formed on a portion of the substrate 401. The well 220 is formed in the same manner as the formation of the p-type semiconductor 221. Also, the well 220 and the p-type semiconductor 221 can be formed simultaneously. For example, the transistor 282 described above may be used as the transistor 604. can.

[0331] In addition, an insulating layer 403 and an insulating layer 404 are formed on the photoelectric conversion element 601 and the transistor 604. The insulating layers 403 to 405 are formed on the substrate 401 ( An opening 224 is formed in the region overlapping with the n-type semiconductor 223, and the insulating layer 403 to the insulating layer 40 An opening 225 is formed in the region where the p-type semiconductor 221 of the semiconductor substrate 5 overlaps with the p-type semiconductor 221 of the semiconductor substrate 5. A contact plug 406 is formed in the opening 225. The openings 224 and 225 can be provided in the same manner as the contact plugs 113a described above. There are no particular restrictions on the number or arrangement of the openings 225. Therefore, the layout can be designed with a high degree of freedom. This makes it possible to realize a simple imaging device.

[0332] In addition, an electrode 421, an electrode 422, and an electrode 429 are formed on the insulating layer 405. The electrode 421 is connected to an n-type semiconductor via a contact plug 406 provided in the opening 224. 223 (substrate 401). The electrode 429 is provided in the opening 225. The insulating layer 404 is electrically connected to the p-type semiconductor 221 via a contact plug 406 . The electrode 422 can function as one electrode of the capacitor element 606 .

[0333] An insulating layer 407 is formed to cover the electrodes 421, 429, and 422. The insulating layer 407 can be formed using a material and method similar to that of the insulating layer 405. In addition, a CMP process may be performed on the surface of the insulating layer 407. By performing the CMP process, the sample This reduces surface irregularities and improves the coverage of the insulating layer and conductive layer that will be formed later. The electrodes 421, 422, and 429 are made of the same material and have the same structure as the electrode 114a described above. The present invention can be formed by the above-mentioned methods and methods.

[0334] Further, the insulating layer 102 is formed on the insulating layer 407, and the electrode 427 and the electrode The electrode 119 and the electrode 273 are formed. The electrode 427 is connected to the The electrode 119 is electrically connected to the back gate of the transistor 602. The electrode 273 can function as the other electrode of the capacitor 606. The transistor 602 can be, for example, the transistor 160 described above.

[0335] In addition, the electrode 109a is electrically connected to the electrode 427 via a contact plug.

[0336] <Variation 1> An example of the configuration of the pixel 622 different from that shown in FIG. 41 is shown in FIG. 42. FIG. 42 is a cross-sectional view of a part of the pixel 622. FIG.

[0337] In the pixel 622 shown in FIG. 42, a transistor 604 and a transistor 605 are provided on a substrate 401. The transistor 604 can function as an n-channel transistor. The transistor 605 can function as a p-channel transistor. The transistor 604 may be, for example, the transistor 282 described above. As the transistor 605, for example, the above-mentioned transistor 281 can be used.

[0338] Electrodes 413a to 413d are formed over the insulating layer 405. The electrode 413b is electrically connected to either the source or drain of the transistor 604. The electrode 413 is electrically connected to the other of the source and drain of the transistor 604. The electrode 413c is electrically connected to the gate of the transistor 604. The electrode 413d is electrically connected to one of the source and drain of the transistor 605. The transistor 604 is electrically connected to the other of the source and drain of the transistor 605 .

[0339] The electrode 109b and the electrode 413c are electrically connected via a contact plug 112d. In addition, an insulating layer 415 is formed on the electrode 114a, the electrode 114b, and the insulating layer 112. The insulating layer 415 can be formed using the same material and method as the insulating layer 111. do.

[0340] In addition, in the pixel 622 shown in FIG. 42, a photoelectric conversion element 601 is provided on the insulating layer 415. In addition, an insulating layer 442 is provided on the photoelectric conversion element 601, and an electrode 48 is provided on the insulating layer 442. The insulating layer 442 is formed using the same material and method as the insulating layer 415. It is possible.

[0341] The photoelectric conversion element 601 shown in FIG. 42 includes an electrode 686 formed of a metal material or the like and a transparent conductive In FIG. 42, a selenium-based material is used for the photoelectric conversion layer 6 The photoelectric conversion element 601 using a selenium-based material is The photoelectric conversion element has a high external quantum efficiency due to the avalanche phenomenon. This allows for a highly sensitive sensor with a large amplification of electrons relative to the amount of incident light. However, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 681 can be easily thinned. .

[0342] The selenium-based material may be amorphous or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0343] Although the photoelectric conversion layer 681 is illustrated as a single layer, the selenium-based material is a material having a hole injection layer on the light receiving surface side. Gallium oxide or cerium oxide is provided as an electron injection blocking layer, and an electron injection blocking layer is provided on the electrode 686 side. The stop layer may be made of nickel oxide or antimony sulfide.

[0344] The photoelectric conversion layer 681 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon can be utilized in the same way as in the case of a single layer of selenium. It is possible to form a photoelectric conversion element that can be used.

[0345] In addition, CIS and CIGS are p-type semiconductors, and sulfur from n-type semiconductors is used to form the junction. Cadmium oxide, zinc sulfide, or the like may be provided in contact with the metal.

[0346] In order to generate the avalanche phenomenon, a relatively high voltage (e.g., 10 It is preferable to apply a voltage of 100 V or more to the OS transistor. Because it has high withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with high drain withstand voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0347] The transparent conductive layer 682 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite The light-transmitting conductive layer 682 is not limited to a single layer, but may be a stack of different films. In FIG. 42, the light-transmitting conductive layer 682 and the wiring 487 are connected to the electrode 488 and 489. The conductive layer 682 and the wiring 487 may be in direct contact with each other.

[0348] In addition, the electrode 686 and the wiring 487 may be configured by laminating a plurality of conductive layers. For example, the electrode 686 is made of two layers, a conductive layer 686a and a conductive layer 686b, and the wiring 487 is made of a conductive The conductive layer 686a may be a conductive layer 487b. The conductive layer 487a is formed by selecting a low resistance metal or the like, and the conductive layer 686b and the conductive layer It is preferable to form 487b by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 681. With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. However, some metals may cause electrolytic corrosion when in contact with the transparent conductive layer 682. Even if such a metal is used for the conductive layer 487a, electrolytic corrosion is prevented by passing through the conductive layer 487b. can be prevented.

[0349] The conductive layer 686b and the conductive layer 487b are made of, for example, molybdenum or tungsten. The conductive layer 686a and the conductive layer 487a may be made of, for example, aluminum. Aluminum, titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0350] The insulating layer 442 may have a multi-layer structure. The partition wall 477 can be formed using an organic resin or the like. To block light and / or to determine the area of ​​the light receiving part per pixel, It may be colored.

[0351] In addition, the photoelectric conversion element 601 is made of a pi film using an amorphous silicon film or a microcrystalline silicon film. Alternatively, an n-type diode element may be used. The photodiode includes an n-type semiconductor layer, It has a structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated in this order. It is preferable to use amorphous silicon for the semiconductor layer. The conductor layers are made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. Silicon can be used as the photoelectric conversion layer. The cathode has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0352] In addition, pn-type and pin-type diode elements are arranged so that the p-type semiconductor layer becomes the light receiving surface. By using a p-type semiconductor layer as a light receiving surface, the output current of the photoelectric conversion element 601 is The flow can be increased.

[0353] The photoelectric conversion element 601 formed using the above-mentioned selenium-based material or amorphous silicon is Manufactured using general semiconductor manufacturing processes such as film processing, lithography processing, and etching processing You can do it.

[0354] <Variation 2> An example of the configuration of the pixel 622 different from that shown in FIG. 42 is shown in FIG. 43. FIG. 43 is a cross-sectional view of a part of the pixel 622. FIG.

[0355] The pixel 622 shown in FIG. 43 includes a substrate 520 on which a pixel driving circuit and the like are provided, and a photoelectric conversion element The substrate 520 is formed by bonding a substrate 530 on which a substrate 601 and other components are provided. On the plate 411, a transistor 602, a transistor 604, a transistor 605, etc. The substrate 411 has a structure similar to that of the substrate 401, and is a substrate on which an insulating layer 415 has been formed. The structure of the substrate 520 can be understood with reference to FIG. The substrate 530 is formed by forming an insulating layer 407 and an electrode layer 408 on the substrate 401 on which the photoelectric conversion element 601 is provided. The structure of the substrate 530 can be understood with reference to FIG. I can understand it.

[0356] The substrate 520 and the substrate 530 are stacked so that the insulating layer 415 and the insulating layer 407 face each other. The electrode 114a and the electrode 429 are electrically connected via a contact plug 408. The pixel 622 shown in FIG. 43 detects light incident from the substrate 401 side. The substrate 520 on which the photoelectric conversion element 601 and the like are provided is superimposed on the substrate 530 on which the photoelectric conversion element 601 and the like are provided. This makes it possible to increase the area of ​​the photoelectric conversion element 601 that occupies one pixel.

[0357] [Display device] As an example of a semiconductor device using the above-described transistor, a display device will be described. Display devices (such as liquid crystal display devices and light-emitting display devices) are devices that have display elements. or may have a variety of elements.

[0358] The display device may be, for example, an EL (electroluminescence) element (including organic and inorganic materials). EL elements, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips ED chip, green LED chip, blue LED chip, etc.), transistor (depending on the current Light-emitting transistors), electron emitters, display elements using carbon nanotubes, liquid crystal Elements, electronic ink, electrowetting elements, electrophoretic elements, MEMS (micro Display elements using electro-mechanical systems (e.g., grating light Glow valve (GLV), digital micromirror device (DMD), DMS (Digital Micromirror Device) Micro Shutter), MIRASOL (registered trademark), IMOD (Interference Modulation) MEMS display element using the shutter method, MEMS display element using the optical interference method S display element, piezoelectric ceramic display, etc.), or at least quantum dots, etc. It has one.

[0359] In addition, display devices use electrical or magnetic effects to adjust contrast, brightness, and reflectivity. The display device may have a display medium that changes reflectance, transmittance, etc. It may be a display (PDP).

[0360] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E Examples include LCDs (electronic-emitter displays).

[0361] An example of a display device using quantum dots in each pixel is a quantum dot display. Note that quantum dots are not used as display elements, but as backlights for liquid crystal displays and the like. By using quantum dots, it is possible to achieve high color purity. This can be done.

[0362] An example of a display device using a liquid crystal element is a liquid crystal display device (transmissive liquid crystal display, semi-transparent liquid crystal display, etc.). Transmissive LCD, Reflective LCD, Direct-view LCD, Projection LCD LCD display).

[0363] In order to realize a semi-transmissive or reflective LCD, the pixel voltage must be A part or the whole of the electrode may function as a reflective electrode. For example, A part or the whole of the pixel electrode may be made of aluminum, silver, or the like. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This further reduces power consumption.

[0364] Examples of display devices using electronic ink, electronic liquid powder, or electrophoretic elements include Examples include electronic paper.

[0365] When using LED chips in display elements, etc., the electrodes of the LED chip and the nitride semiconductor Graphene or graphite may be placed underneath. In this way, the graphene or graphite layer may be provided. By this, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal, etc. is formed thereon. Furthermore, a p-type GaN semiconductor layer having crystals can be formed on the substrate. By providing the above-mentioned material, an LED chip can be constructed. An AlN layer may be provided between the n-type GaN semiconductor layer having the crystal structure. The GaN semiconductor layer may be formed by MOCVD. This means that the GaN semiconductor layer on the LED chip can be formed by sputtering. It is.

[0366] In addition, in a display element using MEMS, the space in which the display element is sealed (for example, An element substrate on which display elements are arranged and an opposing substrate arranged opposite the element substrate. By placing a desiccant, MEMS and other components can be protected from moisture. This can prevent the mechanism from becoming difficult to move and from deteriorating.

[0367] <Pixel circuit configuration example> Next, a more specific example of the configuration of the display device will be described with reference to FIG. FIG. 3 is a block diagram for explaining the configuration of a display device 3100. The display device 3100 includes: The display device 3131 includes a display area 3131, a circuit 3132, and a circuit 3133. The circuit 3132 includes, for example, For example, the circuit 3133 functions as a signal line driver circuit. It works.

[0368] The display devices 3100 are arranged in parallel with each other, and the potential is controlled by a circuit 3132. m scanning lines 3135 are arranged approximately in parallel to each other and are connected to a circuit 3133. The display area 3131 further includes n signal lines 3136 whose potentials are controlled by the signal lines 3136. has a plurality of pixels 3130 arranged in a matrix of m rows and n columns. Note that m and n are Both are natural numbers greater than or equal to 2.

[0369] In the display area 3131, each scanning line 3135 corresponds to one row of the pixels 3130. The signal lines 3136 are electrically connected to the n pixels 3130 arranged in the pixel array 3130. 3130, m pixels 3130 arranged in any one column are electrically connected to each other.

[0370] As shown in FIG. 44B, the display area 3131 is sandwiched between the circuit 3132 and the substrate 3133. A circuit 3152 may be provided in the display area 313 as shown in FIG. A circuit 3153 may be provided at a position facing the circuit 3133 with the circuit 1 in between. In FIG. 44C, the circuit 3152 is connected to the scanning line 3135 in the same manner as the circuit 3132. However, the present invention is not limited to this example. For example, the circuit 31 connected to the scanning line 3135 may be 32 and the circuit 3152 may be changed every few lines. In FIG. 44(C), the circuit 3153 is replaced by the circuit 3133, the signal line 3136 is connected to the signal line 3136. However, the present invention is not limited to this. For example, the circuit 3133 and the circuit 3153 connected to the signal line 3136 may be changed every few lines. In addition, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 are It may have a function other than driving 0.

[0371] In addition, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 are referred to as a drive circuit section. The pixel 3130 includes a pixel circuit 3137 and a display element. 3137 is a circuit for driving a display element. The transistors in the driver circuit are The transistors constituting the transistor path 3137 can be formed at the same time. A part or the whole of the display device 3100 may be formed on another substrate and electrically connected to the display device 3100 . For example, a part or the whole of a driving circuit portion may be formed using a single crystal substrate, and the display device 3100 may be formed using a single crystal substrate. Electrical connection may also be made.

[0372] FIG. 45(A1), FIG. 45(A2), FIG. 45(B1), and FIG. 45(B2) show a display device. 3 shows a circuit configuration that can be used for pixel 3130 of 3100.

[0373] [An example of a pixel circuit for a light-emitting display device] FIG. 45(A1) and FIG. 45(A2) show pixel circuits that can be used in a light-emitting display device. An example is shown in FIG. 45(A1) and FIG. 45(A2). The pixel circuit 3137 shown in FIG. a capacitor 3233, a transistor 3232, and a transistor 3434 FIG. 45(A2) shows a transistor 3431, a transistor 3232, and a transistor This is a circuit diagram when a transistor having a back gate electrode is used for the transistor 3434. In addition, the pixel circuit 3137 is electrically connected to a light-emitting element 3125 that can function as a display element. This is being continued.

[0374] A data signal is applied to one of the source electrode and the drain electrode of the transistor 3431. The pixel electrodes 3134 are electrically connected to the n-th signal line 3136 (hereinafter, referred to as signal line DL_n) in the n-th column. The gate electrode of the transistor 3431 is connected to the m-th scanning line 31 to which a gate signal is applied. 35 (hereinafter referred to as scanning line GL_m).

[0375] The transistor 3431 has a function of controlling writing of a data signal to a node 3435. do.

[0376] One of a pair of electrodes of the capacitor 3233 is electrically connected to the node 3435, and the other is The source electrode of the transistor 3431 and the The other of the drain electrodes is electrically connected to node 3435 .

[0377] The capacitor 3233 serves as a storage capacitor for storing data written to the node 3435. It has functions.

[0378] One of the source electrode and the drain electrode of the transistor 3232 is connected to the potential supply line VL_a. The other end is electrically connected to a node 3437. The gate electrode of 3232 is electrically connected to a node 3435 .

[0379] One of the source electrode and the drain electrode of the transistor 3434 is connected to the potential supply line VL_c. The other end is electrically connected to a node 3437. The gate electrode of 3434 is electrically connected to the scanning line GL_m.

[0380] One of the anode and the cathode of the light emitting element 3125 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 3437.

[0381] The light-emitting element 3125 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the present invention is not limited to this, and examples thereof include inorganic materials. An inorganic EL element may also be used.

[0382] For example, the potential supply line VL_a has a function of supplying VDD. b has the function of supplying VSS. In addition, the potential supply line VL_c has the function of supplying VSS. has.

[0383] Here, the operation of a display device having the pixel circuit 3137 of FIG. 45(A1) and FIG. 45(A2) will be described. First, the pixel circuits 3137 in each row are selected in sequence by the circuit 3132. The transistor 3431 is turned on to write a data signal (potential) to the node 3435. Next, the transistor 3434 is turned on to set the potential of the node 3437 to VSS. do.

[0384] Then, the transistor 3431 is turned off to transmit the data signal written to the node 3435. Next, the transistor 3434 is turned off. The amount of current flowing between the source and drain depends on the data signal written to node 3435. Therefore, the light emitting element 3125 emits light with a luminance according to the amount of current flowing. By sequentially performing the above for each row, an image can be displayed.

[0385] In addition, the pixels 3130 are each used as a sub-pixel, and different pixels are generated from each sub-pixel. By emitting light in a certain wavelength range, a color image can be displayed. A pixel 3130 that emits light in the long wavelength range, a pixel 3130 that emits light in the green wavelength range, and a pixel 3130 that emits light in the blue wavelength range. A pixel 3130 that emits light in the region is used as one pixel.

[0386] The wavelength range of the light to be combined is not limited to red, green, and blue, but may include cyan, yellow, and magenta. A sub-pixel that emits light of at least three different wavelength ranges in one pixel may be used. By providing the pixel element, a full color image can be displayed.

[0387] In addition to red, green, and blue, a subpixel that emits light in the yellow wavelength range may be added. In addition to cyan, yellow, and magenta, a subpixel that emits light in the blue wavelength range may be added. By providing sub-pixels that emit light in four or more different wavelength ranges in one pixel, This can further improve the color reproducibility of the image.

[0388] In addition, the ratio of the number of red, green, and blue pixels (or the light-emitting area ratio) used in one pixel is not necessarily 1. For example, the pixel ratio (ratio of light-emitting area) of red:green:blue is 1:1:2. The pixel number ratio (light emitting area ratio) may be red:green:blue=1:2:3.

[0389] In addition, by combining red, green, and blue color filters with the sub-pixels that emit white light, It is also possible to realize a full color display. It is also possible to use LEDs that emit light in the red, green, or blue wavelength ranges. Each subpixel is combined with a color filter that transmits light in the red, green, or blue wavelength range. This may be allowed.

[0390] [An example of a pixel circuit for a liquid crystal display device] FIG. 45(B1) and FIG. 45(B2) show pixel circuits that can be used in a liquid crystal display device. An example is shown in FIG. 45(B1) and FIG. 45(B2). FIG. 45B2 shows a transistor 343 FIG. 1 is a circuit diagram showing a case where a transistor having a back gate electrode is used. The circuit 3137 is electrically connected to a liquid crystal element 3432 that can function as a display element. .

[0391] The potential of one of the pair of electrodes of the liquid crystal element 3432 is appropriately set according to the specifications of the pixel circuit 3137. The liquid crystal contained in the liquid crystal element 3432 is set according to the data written to the node 3436. The alignment state is set by the liquid crystal element A common potential may be applied to one of the pair of electrodes of 3432.

[0392] The mode of the liquid crystal element 3432 may be, for example, TN mode, STN mode, VA mode, ASM(Axially Symmetric Aligned Micro-cell ) mode, OCB (Optically Compensated Birefring ence) mode, FLC (Ferroelectric Liquid Crystal l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, MVA mode, PVA (Patterned Vertical Al ignment) mode, IPS mode, FFS mode, or TBA (Transve Alternatively, a 3D bend alignment mode may be used. ECB (Electrically Controlled Birefringe) nce) mode, PDLC (Polymer Dispersed Liquid Crystal ystal) mode, PNLC (Polymer Network Liquid Cr However, there are various modes, including but not limited to these. Various modes can be used.

[0393] In the pixel circuit 3137 in the mth row and the nth column, One of the in-electrodes is electrically connected to the signal line DL_n, and the other is electrically connected to the node 3436. The gate electrode of the transistor 3431 is electrically connected to the scanning line GL_m. The transistor 3431 has a function of controlling writing of a data signal to the node 3436. Possesses the ability.

[0394] One of the pair of electrodes of the capacitor 3233 is a wiring to which a specific potential is supplied (hereinafter, referred to as a “capacitor line”). CL), and the other is electrically connected to node 3436. The other of the pair of electrodes of the liquid crystal element 3432 is electrically connected to a node 3436 . The value of the potential of the capacitance line CL is appropriately set according to the specifications of the pixel circuit 3137. The element 3233 functions as a storage capacitor that stores data written to the node 3436. has.

[0395] Here, an example of the operation of a display device having the pixel circuit 3137 of FIG. 44(C) will be described. First, the circuit 3132 sequentially selects the pixel circuits 3137 in each row, and the transistors 34 31 is turned on to write a data signal to node 3436.

[0396] Next, the transistor 3431 is turned off, and the data signal written to the node 3436 is The transparency of the liquid crystal element 3432 is maintained in response to the data signal written to the node 3436. By performing this process row by row, an image can be displayed in the display area 3131. do.

[0397] <Example of display device configuration> The transistor described in the above embodiment is used as a part of a driver circuit including a transistor. The entire display can be integrated onto the same substrate as the pixel section to form a system-on-panel. Regarding a structural example of a display device in which the transistor described in the above embodiment can be used, This will be explained using Figures 46 and 47.

[0398] [Liquid crystal display device and EL display device] As an example of the display device, a display device using a liquid crystal element and a display device using an EL element are described. In FIG. 46A, a pixel portion 400 provided on a first substrate 4001 is A sealant 4005 is provided to surround the second substrate 4002, and the second substrate 4006 is used for sealing. In FIG. 46A, a sealant 4005 on a first substrate 4001 In a region different from the surrounded region, a single crystal semiconductor or a polycrystalline semiconductor is formed on a separately prepared substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 made of a conductor are mounted. In addition, the signal line driver circuit 4003, the scanning line driver circuit 4004, or the pixel portion 4002 Various signals and potentials are applied via FPC (Flexible Printed Circuit). It is supplied by FPC4018a and FPC4018b.

[0399] In FIG. 46B and FIG. 46C, a pixel portion 40 provided on a first substrate 4001 A sealant 4005 is provided so as to surround the gate electrode 4002 and the scanning line driver circuit 4004. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed on the first substrate 4001. The display element is sealed by a sealant 4005 and a second substrate 4006 . In FIG. 46B and FIG. 46C, the sealant 4005 on the first substrate 4001 In a region different from the region surrounded by the ion implantation, a single crystal semiconductor or a multilayer semiconductor is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a crystalline semiconductor is mounted. In 46(C), a signal line driver circuit 4003, a scanning line driver circuit 4004, or a pixel Various signals and potentials are provided to the portion 4002 through an FPC 4018 .

[0400] In addition, in FIG. 46(B) and FIG. 46(C), a signal line driver circuit 4003 is separately formed. Although an example in which the scanning line is mounted on the first substrate 4001 is shown, the present invention is not limited to this configuration. The driver circuit may be formed separately and mounted, or may be a part of the signal line driver circuit or a scanning line driver circuit. Alternatively, only a part of the above may be formed separately and mounted.

[0401] The method of connecting the separately formed drive circuit is not particularly limited, and may be a wire bond. ing, COG (Chip On Glass), TCP (Tape Carrier) Package), COF (Chip On Film), etc. can be used. 46(A) is a substrate on which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are mounted by COG. FIG. 46(B) is an example in which a signal line driver circuit 4003 is mounted by COG. FIG. 46C shows an example in which a signal line driver circuit 4003 is implemented using TCP.

[0402] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "IC" may also refer to a module in which an IC or the like including the above is mounted.

[0403] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be used.

[0404] 47(A) and 47(B) are cross-sectional views of the region indicated by the dashed line N1-N2 in FIG. 46(B). The display device shown in FIG. 47(A) and FIG. 47(B) has an electrode 401. 5, and the electrode 4015 is connected to a terminal of the FPC 4018 and an anisotropic conductive layer 4019. The electrode 4015 is electrically connected to the insulating layer 4112 and the insulating layer 4113. 11, and electrically connected to the wiring 4014 in an opening formed in the insulating layer 4110. is.

[0405] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The conductive layer is made of the same material.

[0406] A pixel portion 4002 and a scanning line driver circuit 4004 provided on a first substrate 4001 are In FIG. 47(A) and FIG. 47(B), the pixel portion 4002 includes a A transistor 4010 included in the scanning line driver circuit 4004 and a transistor 401 In FIG. 47A, a transistor 4010 and a transistor 401 are illustrated. 11, an insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided, and as shown in FIG. In (B), a partition wall 4510 is formed on an insulating layer 4112 .

[0407] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4102. It has an electrode 4017 formed thereon, and an insulating layer 4103 formed on the electrode 4017 . The electrode 4017 can function as a back-gate electrode.

[0408] The transistors 4010 and 4011 are the same as those described in the above embodiment modes. The transistors described in the above embodiments can be used. Therefore, the present invention shown in Fig. 47(A) and Fig. 47(B) is The display device according to the embodiment can be made to have high reliability.

[0409] In addition, in FIG. 47(A) and FIG. 47(B), the transistor 4010 and the transistor As the transistor 4011, a transistor having a structure similar to that of the transistor 160 described in the above embodiment is used. The example shows the case where a transistor is used.

[0410] The display devices shown in FIGS. 47A and 47B further include a capacitor 4020. The capacitor 4020 is connected to one of the source electrode and the drain electrode of the transistor 4010. The electrode 4021 has a region where the electrode 4021 overlaps with the insulating layer 4103 interposed therebetween. It is formed from the same conductive layer as electrode 4017.

[0411] In general, the capacitance of a capacitor provided in a display device is determined by the capacitance of a transistor disposed in a pixel portion. The capacitance is set so that the charge can be held for a predetermined period, taking into consideration the current flow and other factors. The capacitance may be set in consideration of the off-state current of the transistor and the like.

[0412] For example, by using an OS transistor in a pixel portion of a liquid crystal display device, the capacitance of a capacitor can be reduced. The capacity of the liquid crystal display can be reduced to 1 / 3 or less, or even 1 / 5 or less. By using a resistor, the formation of a capacitive element can be omitted.

[0413] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. FIG. 47(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal element 4013, which is a display element, a first electrode layer 4030 and a second electrode layer 4040 are 031 and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between the alignment films 4003 and 4008. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a A first electrode layer 4030 and a second electrode layer 4031 are provided on the second substrate 4006 side. Overlapping via layer 4008.

[0414] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. and the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0415] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0416] Moreover, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the isotropic phase to the isotropic phase. Therefore, a liquid crystal composition containing 5% by weight or more of a chiral agent is used to improve the temperature range. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. The speed is short (less than 1 msec), alignment processing is unnecessary because it is optically isotropic, and the The field angle dependency is small. Also, since there is no need to provide an alignment film, rubbing processing is also unnecessary. The electrostatic breakdown caused by the rubbing process can be prevented, and the liquid during the manufacturing process can be prevented. This reduces defects and damage to the liquid crystal display device, thereby improving the productivity of the liquid crystal display device. It is possible to do so.

[0417] In addition, a pixel is divided into several regions (subpixels), each of which is illuminated in a different direction. It is said to be a multi-domain or multi-domain design that is designed to defeat molecules. The method can be used.

[0418] The specific resistance of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 11 Ω cm or more, and more preferably 1×10 12 In addition, this specification The resistivity values ​​stated herein are those measured at 20°C.

[0419] The OS transistor used in this embodiment has a low current value in an off state (off-state current value). Therefore, the retention time of electrical signals such as image signals can be extended. When the power is on, the write interval can be set longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0420] In addition, OS transistors have a relatively high field-effect mobility, enabling high-speed operation. Therefore, by using the above transistor in a pixel portion of a display device, a high-quality image can be displayed. In addition, a driver circuit section and a pixel section can be separately manufactured on the same substrate. This makes it possible to reduce the number of parts in the display device.

[0421] In addition, in display devices, they are used as black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, etc. For example, a polarizing substrate and a positioning member may be provided. Circularly polarized light produced by a retardation substrate may be used. Either may be used.

[0422] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element is a light-emitting diode (EL element) that is disposed between a pair of electrodes. The EL element has a layer containing a light-emitting compound (also called an "EL layer"). When a potential difference larger than the threshold voltage is generated, holes are injected into the EL layer from the anode side, and the cathode Electrons are injected from the electrode side. The injected electrons and holes recombine in the EL layer, forming a The contained luminescent material emits light.

[0423] EL elements are also classified according to whether the luminescent material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0424] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. is called a child.

[0425] In addition to the light-emitting compound, the EL layer may be formed by using a material having a high hole-injecting property and a material having a high hole-transporting property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0426] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0427] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0428] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. A transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. There are two types of structures: top emission (top emission) where the light is emitted from the top surface of the substrate, and bottom emission ( Bottom emission) structure and dual emission structure that emits light from both sides ) structure, and any light emitting element having any emission structure can be applied.

[0429] FIG. 47(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is provided in the pixel portion 4002. The light-emitting element 4513 is electrically connected to the transistor 4010. The first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 513 can be changed as appropriate.

[0430] The partition 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the side of the opening is a continuous curved It is preferable to form the inclined surface so that the inclined surface is formed with a certain rate.

[0431] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0432] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 40 The space sealed by 05 is sealed with a filler 4514. A protective film (lamination film) that is highly airtight and has little outgassing so as not to be exposed to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. It is.

[0433] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, poly Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (ethylene vinyl acetate) or the like can be used. Agents may also be included.

[0434] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0435] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0436] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves visibility of the displayed image.

[0437] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) for applying a voltage to the display element In the case of the electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the light reflecting property can be selected depending on the pattern structure of the electrode layer.

[0438] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0439] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0440] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, Its derivatives are also included.

[0441] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0442] By using the transistor described in the above embodiment, a display device with high reliability can be provided. In addition, by using the transistor described in the above embodiment, high definition and Therefore, it is possible to provide a display device having a large area and good display quality. It is possible to provide a display device in which the above-mentioned problem is reduced.

[0443] [Display module] As an example of a semiconductor device using the above-mentioned transistor, a display module will be described. The display module 6000 shown in FIG. 2, touch sensor 6004 connected to FPC 6003, and touch sensor 6005 connected to FPC 6005 A display panel 6006, a backlight unit 6007, a frame 6009, a printer The backlight unit 6007 includes a backlight substrate 6010 and a battery 6011. The battery 6011, the touch sensor 6004, etc. may not be provided.

[0444] The semiconductor device of one embodiment of the present invention includes, for example, a touch sensor 6004, a display panel 6006, It can be used for an integrated circuit mounted on a printed circuit board 6010. For example, The display device described above can be used for the panel 6006.

[0445] The upper cover 6001 and the lower cover 6002 are connected to the touch sensor 6004 and the display panel 6 The shape and dimensions can be changed appropriately to suit sizes such as 006.

[0446] The touch sensor 6004 is a resistive or capacitive touch sensor connected to the display panel 6 The display panel 6006 can be used by being superimposed on the display panel 6006. For example, a touch sensor electrode can be provided in each pixel of the display panel 6006. It is also possible to provide a touch panel function using a capacitance method. By providing an optical sensor in each pixel of the panel 6006, the function of an optical touch sensor can be added. It is also possible to do the following.

[0447] The backlight unit 6007 includes a light source 6008. The unit 6007 may be provided at its end and configured to use a light diffusion plate. When a light-emitting display device or the like is used for 6006, the backlight unit 6007 is omitted. It is possible.

[0448] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing the display panel 6006 from being damaged. It also functions as an electromagnetic shield to block electromagnetic waves generated. 009 may have a function as a heat sink.

[0449] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. A battery 6011 is used as a power source for supplying power to the power supply circuit. If a commercial power source is used as the power source, , the battery 6011 can be omitted.

[0450] In addition, components such as polarizing plates, retardation plates, and prism sheets are added to the display module 6000. It may also be provided as such.

[0451] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0452] [RF tag] As an example of a semiconductor device using the above-mentioned transistor, an RF tag will be described.

[0453] The RF tag according to one embodiment of the present invention has an internal memory circuit (memory device) and stores information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems. requires high reliability.

[0454] The structure of an RF tag will be described with reference to FIG. 49. FIG. 49 is a block diagram showing an example of the structure of an RF tag. FIG.

[0455] As shown in FIG. 49, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The above-mentioned transistor may be used for the communicator 801. 0 is a rectifier circuit 805, a constant voltage circuit 806, a demodulator circuit 807, a modulator circuit 808, a logic circuit The demodulation circuit 807 includes a memory circuit 810 and a ROM 811. The semiconductor of a rectifying transistor has a function that can sufficiently suppress reverse current. For example, an oxide semiconductor may be used. This reduces the rectification caused by the reverse current. This suppresses the decrease in the input of the demodulation circuit, and prevents the output of the demodulation circuit from being saturated. The output of the demodulation circuit can be made closer to linear. Electromagnetic coupling method in which coils are placed opposite each other and communication is performed by mutual induction, and communication is performed by induced electromagnetic fields. RF tags are broadly divided into three types: electromagnetic induction, which transmits information, and radio wave, which transmits information using radio waves. 00 can be used in either method.

[0456] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit may include a limiter circuit. When the internally generated voltage is large, the power above a certain level is controlled so as not to be input to the downstream circuit. This is a circuit for

[0457] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0458] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0459] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0460] The above-mentioned circuits can be selected or omitted as appropriate.

[0461] The above-described memory device can be used for the memory circuit 810. This device is suitable for RF tags because it can retain information even when the power is cut off. Furthermore, in the memory device according to one embodiment of the present invention, the power (voltage) required for writing data is The difference in maximum communication distance when reading and writing data is therefore Furthermore, it is possible to prevent malfunctions due to insufficient power when writing data. Alternatively, the occurrence of erroneous writing can be suppressed.

[0462] Further, the memory device according to one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0463] An example of the use of the RF tag according to one embodiment of the present invention will be described with reference to FIG. The applications are wide-ranging, but examples include banknotes, coins, securities, bearer bonds, driver's licenses, and resident cards. (See Figure 50(A)), recording media such as DVD software and video tapes (See Figure 5 0(B). ), containers such as plates, cups and bottles (see Fig. 50(C)), wrapping paper, boxes and rings. Packaging materials for bottles, moving objects such as bicycles (see Figure 50(D)), personal items such as bags and glasses, etc. Perishables, plants, animals, the human body, clothing, household items, medical products including medicines and pharmaceuticals, or electronic equipment (For example, liquid crystal display devices, EL display devices, television devices, or mobile phones.) Articles or tags attached to each article (see Figure 50(E) and Figure 50(F)), etc. It can be used by installing it in

[0464] The RF tag 800 according to one embodiment of the present invention can be attached to or embedded in the surface of an article. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. The RF tag 8 according to one embodiment of the present invention is embedded in the organic resin and fixed to each article. In order to achieve a small size, thinness, and light weight, the 00 is designed to conform to the design of the item even after being attached to the item. In addition, the information contained in banknotes, coins, securities, bearer bonds, or certificates is not The RF tag 800 according to one embodiment of the present invention can provide an authentication function. By utilizing this function, it is possible to prevent counterfeiting. The RF tag 800 according to one embodiment of the present invention is attached to products, clothing, household goods, electronic devices, etc. By adding this function, the efficiency of systems such as inspection systems can be improved. By attaching an RF tag 800 according to one aspect of the present invention to a moving object, it is possible to prevent theft, etc. As described above, the RF tag 8 according to one embodiment of the present invention can improve security. 00 can be used for each of the applications mentioned above.

[0465] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0466] (Embodiment 5) <Package using lead frame type interposer> Figure 51(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 51(A) is a perspective view of a semiconductor device according to one embodiment of the present invention. The corresponding chip 551 is connected to the terminals on the interposer 550 by wire bonding. The terminal 552 is connected to the chip 551 of the interposer 550. The chip 551 is placed on the surface that is covered with the mold resin 553. Although it may be sealed, it is preferable that the sealing be performed while leaving a portion of each terminal 552 exposed.

[0467] An example of the configuration of an electronic device in which a package is mounted on a circuit board is shown in FIG. The electronic device shown in FIG. 1(B) is installed in, for example, a mobile phone. The device includes a printed wiring board 561, a package 562, and a battery 564 mounted on the printed wiring board 561. In addition, a panel 560 on which a display element is provided is provided with a printed wiring board 561, which is connected to an FPC. Implemented by 563.

[0468] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0469] (Embodiment 6) In this embodiment, an example of an electronic device using a semiconductor device according to one embodiment of the present invention will be described. Reveal.

[0470] Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. , lighting equipment, desktop or notebook personal computers, word processors The data is stored on recording media such as DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images, portable CD players, radios, tapes Recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets , transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable games Fixed game machines such as pachinko machines, calculators, electronic organizers, electronic books, electronic translators, voice Input devices, video cameras, digital still cameras, electric shavers, microwave ovens, and other high-frequency devices Heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans, hair dryers, air conditioners Air conditioning equipment such as conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, and clothes dryers , futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for storing DNA, flashlights Examples of such items include lights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. , emergency exit lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, electricity Storage systems, power leveling and industrial equipment such as power storage devices for smart grids. In addition, electric motors using electricity from non-aqueous secondary batteries and engines using fuel are also used. The moving object that propels the vehicle may also be included in the category of electronic equipment. For example, electric vehicles (EVs), hybrid vehicles (HEVs) that combine internal combustion engines and electric motors, Plug-in hybrid electric vehicles (PHEVs), tracked vehicles that replace these tires and wheels with tracks , motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts , small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes planetary probes, spacecraft, etc.

[0471] The portable game machine 2900 shown in FIG. 52(A) includes a housing 2901, a housing 2902, a display unit 2903, and a 903, display unit 2904, microphone 2905, speaker 2906, operation key 2907 The portable game machine shown in FIG. 52(A) has two display units 2903 and The display unit 2903 has a display unit 2904, but the number of the display units is not limited to this. A touch screen is provided as an input device, and is operated by a stylus 2908 or the like. It is possible.

[0472] The information terminal 2910 shown in FIG. 52(B) includes a housing 2911, a display unit 2912, a microphone 29 17, speaker unit 2914, camera 2913, external connection unit 2916, and operation buttons The display unit 2912 includes a display panel using a flexible substrate and The information terminal 2910 is equipped with a touch screen. Used as a tablet information terminal, tablet personal computer, e-book terminal, etc. There can be.

[0473] A notebook personal computer 2920 shown in FIG. 52C includes a housing 2921, a display unit, and a 2922, a keyboard 2923, and a pointing device 2924.

[0474] The video camera 2940 shown in FIG. 52(D) includes a housing 2941, a housing 2942, and a display unit 29 43, an operation key 2944, a lens 2945, and a connection part 2946. The display unit 2944 and the lens 2945 are provided in the housing 2941. The display unit 2943 is provided in the housing The housing 2941 and the housing 2942 are connected to a connection portion 2946. The angle between the housing 2941 and the housing 2942 is adjusted by the connection 2946. The angle of the housing 2942 relative to the housing 2941 can be changed. You can change the orientation of the image displayed on the display unit 2943 and switch between displaying and hiding the image. It can be done.

[0475] FIG. 52E shows an example of a bangle-type information terminal. The information terminal 2950 has a housing 2951. The display unit 2952 is supported by a housing 2951 having a curved surface. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide an information terminal 2950 that is flexible, lightweight, and easy to use.

[0476] FIG. 52F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, Display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal The information terminal 2960 is equipped with a mobile phone, an e-mail, a text browsing and creation device, etc. It supports a variety of applications such as music playback, Internet communication, and computer games. It can be executed.

[0477] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by touching the The operation button 2965 is used for setting the time, In addition to the settings, it can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation of the operation button 2965 You can also set the functions.

[0478] In addition, the information terminal 2960 is capable of performing short-range wireless communication according to a communication standard. For example, by communicating with a wireless headset, you can talk hands-free. The information terminal 2960 also includes an input / output terminal 2966, and can be connected to other information terminals. Data can be exchanged directly through the connector. 6. Note that charging can be done wirelessly without going through the input / output terminal 2966. This may be done by line power supply.

[0479] Figure 52(G) shows an electric refrigerator-freezer as an example of a household electrical appliance. The appliance 70 has a housing 2971, a refrigerator door 2972, a freezer door 2973, and the like.

[0480] FIG. 52(H) is an external view showing an example of an automobile. The automobile 2980 includes a body 2981, It has wheels 2982, a dashboard 2983, and lights 2984, etc.

[0481] The electronic devices described in this embodiment include the above-described transistors or the above-described semiconductor devices. It is equipped with.

[0482] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0483] (Embodiment 7) In this embodiment, a deposition chamber in which a sputtering target can be installed is provided. The deposition apparatus (sputtering apparatus) shown in this embodiment is a flat deposition apparatus. Used in parallel plate type sputtering equipment and facing target type sputtering equipment It is possible.

[0484] When forming a film using a facing target sputtering device, damage to the surface to be formed is small. Therefore, it is easy to obtain a film with high crystallinity. In some cases it may be preferable to use a target-type sputtering device.

[0485] The film formation method using a parallel plate sputtering device is called PESP (Parallel It can also be called "opposing target sputtering". The deposition method using a vapor deposition sputtering device is called VDSP (Vapor Deposition Sputtering). It can also be called "n Sputtering."

[0486] First, the structure of a film formation apparatus that reduces the amount of impurities mixed into the film during film formation is shown in FIG. 53 and FIG. This will be explained using 54.

[0487] FIG. 53 is a schematic top view of a single-wafer multi-chamber film forming apparatus 2700. As shown in FIG. The film forming apparatus 2700 includes a cassette port 2761 for accommodating a substrate and a and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing alignment. The substrate is loaded from the supply chamber 2701 to the atmospheric substrate transfer chamber 2702, A load lock chamber 2 that switches the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced from reduced pressure to atmospheric pressure, or reduced from atmospheric pressure to atmospheric pressure. and a transfer chamber 2703b for transferring substrates in a vacuum. 04, a substrate heating chamber 2705 for heating the substrate, and a film forming chamber in which a target is disposed and a film is formed. The film forming chamber 2706 includes a film forming chamber 2706a, a film forming chamber 2706b, and a film forming chamber 2706c. The film forming chambers 706a, 2706b, and 2706c are to be described later with reference to the configuration of the film forming chambers. It is possible.

[0488] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. b is connected to a transfer chamber 2704, which is connected to a substrate heating chamber 2705, a film forming chamber 27 06a, and is connected to the film formation chamber 2706b and the film formation chamber 2706c.

[0489] A gate valve 2764 is provided at the connection between the chambers, and the atmosphere side substrate supply chamber 27 Except for the atmospheric side substrate transfer chamber 2701 and the atmospheric side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. In addition, the atmospheric side substrate transfer chamber 2702 and the transfer chamber 2704 are connected to a transfer robot 2763. and capable of transporting a substrate.

[0490] In addition, it is preferable that the substrate heating chamber 2705 also serves as a plasma processing chamber. In addition, since the substrate can be transported between processes without being exposed to the atmosphere, there is no risk of impurities being present on the substrate. It is possible to suppress the adsorption of substances. In addition, the order of film formation and heat treatment can be freely configured. In addition, the transfer chamber, film formation chamber, load lock chamber, unload lock chamber and substrate heating chamber The number is not limited to the above, and the optimum number can be set according to the installation space and process conditions. It can be done.

[0491] Next, the dashed dotted line X1-X2, the dashed dotted line Y1-Y2, and the dashed dotted line Y1-Y2 of the film forming apparatus 2700 shown in FIG. A cross section corresponding to the dashed line Y2-Y3 is shown in FIG.

[0492] FIG. 54(A) shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704. The chamber 2705 has a number of heated stages 2765 capable of housing substrates. The substrate heating chamber 2705 is connected to a vacuum pump 2770 via a valve. The dry pump 2770 may be, for example, a dry pump or a mechanical booster pump. etc. can be used.

[0493] In addition, the heating mechanism that can be used in the substrate heating chamber 2705 is, for example, a resistance heating element. Alternatively, the heating mechanism may be a mechanism for heating the device using a medium such as a heated gas. The heating mechanism may be one that heats by thermal conduction or thermal radiation. For example, GRTA, LR An RTA such as a TA can be used.

[0494] The substrate heating chamber 2705 is connected to a refiner 278 via a mass flow controller 2780. 1. The mass flow controller 2780 and the refiner 2781 are connected to the gas Although the number of types of substrates is equal, only one is shown for ease of understanding. The gas introduced has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) can be used. .

[0495] The transfer chamber 2704 has a transfer robot 2763. The transfer robot 2763 transfers the The transfer chamber 2704 can transfer the substrate to the vacuum pump 2 through a valve. 770 and a cryopump 2771 are connected. The transfer chamber 2704 is evacuated to a low or medium vacuum (approximately 0.1 to several hundred Pa) from atmospheric pressure. The vacuum is pumped using Pump 2770, and the valve is switched to change the vacuum from medium to high or ultra-high. (0.1 Pa to 1×10 -7 The pumping speed is up to 100 rpm using the Cryopump 2771. .

[0496] In addition, for example, two or more cryopumps 2771 are connected in parallel to the transfer chamber 2704. With this configuration, even if one cryopump is in regeneration, The remaining cryopumps can be used to pump the remaining gas. This is the process of releasing molecules (or atoms) stored in the cryopump. If the ion pump accumulates too many molecules (or atoms), its pumping capacity decreases. Regeneration will occur periodically.

[0497] FIG. 54(B) shows the film forming chamber 2706b, the transfer chamber 2704, and the load lock chamber 2703a. A cross section is shown.

[0498] Here, the film formation chamber (sputtering chamber) will be described in detail with reference to FIG. 54(B). The deposition chamber 2706b shown in FIG. 54(B) includes a target 2766a and a target 2766 b, a target shield 2767a, a target shield 2767b, and a magnet Unit 2790a, magnet unit 2790b, substrate holder 2768, and power supply Although not shown, the target 2766a and the target 2766 b are fixed to the target holder via a backing plate. A power supply 2791 is electrically connected to the get 2766a and the target 2766b. The magnet unit 2790a and the magnet unit 2790b are The target sheet is disposed on the back of the target 2766a and the target 2766b. The target shield 2767a and the target shield 2767b are respectively The substrate holder 2766a is disposed so as to surround the end of the target 2766b. The substrate holder 2768 supports a substrate 2769. The substrate holder 2768 is a variable member 278. The target 27 is fixed to the film forming chamber 2706b via the variable member 2784. The substrate is heated to a region between the target 2766a and the target 2766b (also called the inter-target region). For example, the substrate holder 2768 supporting the substrate 2769 can be moved. Placing the 768 in the inter-target region may reduce damage caused by plasma. In addition, the substrate holder 2768 may be a substrate holder (not shown) for holding the substrate 2769. A holding mechanism and a heater for heating the substrate 2769 from the rear side may be provided.

[0499] In addition, the target shield 2767 prevents sputtering from the target 2766. The target shield 2767 prevents particles from accumulating in unwanted areas. It is desirable to process the surface so that the deposited sputtered particles do not peel off. For example, the surface roughness To increase the effect, blasting or roughening the surface of the Target Shield 2767 is also possible. good.

[0500] The deposition chamber 2706b is connected to a mass flow controller 27 via a gas heating mechanism 2782. 80, and the gas heating mechanism 2782 is purified via a mass flow controller 2780. The gas is introduced into the deposition chamber 2706b by a gas heating mechanism 2782. The gas can be heated to a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. In addition, the gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2 The number of gases 781 is equal to the number of gases, but only one is shown for ease of understanding. The gas introduced into 2706b has a dew point of -80°C or less, preferably -100°C or less. Gases can be used, such as oxygen gas, nitrogen gas, and rare gases (such as argon gas). etc.) are used.

[0501] In addition, when a refiner is provided immediately before the gas inlet, the arrangement from the refiner to the deposition chamber 2706b is The length of the pipe is 10m or less, preferably 5m or less, and more preferably 1m or less. By limiting the length to 10m or less, 5m or less, or 1m or less, the effects of gas released from the piping can be reduced. The reduction can be achieved depending on the length. In addition, the gas piping is It is recommended to use metal piping with the inside coated with chrome or the like. The above piping is made of, for example, SUS3 Compared to 16L-EP piping, the amount of gas containing impurities released is smaller, and the amount of impurities that enter the gas is reduced. In addition, the pipe joints are equipped with high-performance ultra-small metal gasket joints (UPG joints). In addition, by constructing the piping entirely from metal, it is possible to reduce the cost compared to using resin, etc. This is preferable because it can reduce the effects of released gas and external leakage.

[0502] The deposition chamber 2706b is connected to a turbo molecular pump 2772 and a vacuum pump 2773 via a valve. It is connected to 2770.

[0503] Further, the film formation chamber 2706b is provided with a cryotrap 2751.

[0504] Cryotrap 2751 adsorbs molecules (or atoms) with relatively high melting points, such as water. The turbomolecular pump 2772 is a mechanism that can pump large molecules (or atoms). ) and requires little maintenance, making it highly productive. The pumping capacity for water is low. Therefore, in order to increase the pumping capacity for water, etc., a cryotrap is used. The cryotrap 2751 is connected to the deposition chamber 2706b. The temperature of the refrigerator is set to 100 K or less, preferably 80 K or less. If the 751 has multiple refrigerators, changing the temperature of each refrigerator will allow for more efficient exhaust. For example, the temperature of the first stage refrigerator is set to 100K or less, and the second stage refrigerator is set to 100K or less. The temperature of the first refrigerator should be set to 20K or less. In some cases, a higher vacuum can be achieved by using a sublimation pump. In addition, by using an ion pump instead of a cryopump or turbomolecular pump, In some cases, a high vacuum can be achieved.

[0505] The method of exhausting the film forming chamber 2706b is not limited to this, and may be the same as that of the transport chamber 2704. The same configuration as the evacuation method (the evacuation method of a cryopump and a vacuum pump) may be used. The exhaust method for the transfer chamber 2704 is the same as that for the film forming chamber 2706b (a turbo molecular pump and a It is also possible to use an empty pump as an exhaust method.

[0506] In addition, the back pressure ( It is preferable that the total pressure and the partial pressure of each gas molecule (atom) are as follows. Since there is a possibility that impurities may be mixed into the film being formed, the back pressure of the film forming chamber 2706b, etc. It is also necessary to pay attention to the partial pressure of each gas molecule (atom).

[0507] The back pressure (total pressure) of each of the above mentioned chambers is 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, and more preferably 1×10 -5 The mass-to-charge ratio (m / z The partial pressure of a gas molecule (atom) with a mass of 18 is 3 × 10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. In addition, the m The partial pressure of a gas molecule (atom) with z = 28 is 3 x 10 -5 Pa or less, preferably 1×1 0 -5 Pa or less, more preferably 3×10 -6 In addition, the above-mentioned The partial pressure of a gas molecule (atom) with m / z 44 is 3 x 10 -5 Pa or less, preferably 1× 10 -5Pa or less, more preferably 3×10 -6 Pa or less.

[0508] The total pressure and partial pressure in the vacuum chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also called Q-mass) manufactured by ULVAC, Inc. ee Just use CGM-051.

[0509] The above-mentioned transfer chamber 2704, substrate heating chamber 2705, and film forming chamber 2706b are externally It is desirable to have a configuration with little leakage or internal leakage.

[0510] For example, the above-mentioned transfer chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b The crate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s The leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. The leak rate of a gas molecule (atom) with a mass of 28 is 1×10 -5 Pa·m 3 / s or less, preferred Or 1×10 -6 Pa·m 3 / s or less. Also, gas molecules with m / z of 44 (atomic child) leak rate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa. m 3 / s or less.

[0511] The leak rate was calculated from the total and partial pressures measured using the mass spectrometer mentioned above. It can be derived.

[0512] The leak rate depends on external and internal leaks. External leaks occur due to tiny holes or seals. An internal leak is when gas flows into the vacuum system from outside due to a valve failure or other reasons. This is caused by leakage from partitions such as valves and gas released from internal components. In order to keep the above values ​​or less, measures must be taken to prevent both external and internal leaks. There is.

[0513] For example, the opening and closing part of the deposition chamber 2706b may be sealed with a metal gasket. Sketches are metals coated with iron fluoride, aluminum oxide, or chromium oxide. It is recommended to use a metal gasket. Metal gaskets have a higher adhesion than O-rings and reduce external leakage. Also, metals coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivation material, gas emissions containing impurities released from the metal gasket are suppressed. This makes it possible to reduce internal leakage.

[0514] In addition, the film forming apparatus 2700 is made of aluminum, which emits less gas containing impurities. Cr, Ti, Zr, Ni or Vanadium is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. The alloys containing copper, nickel, etc. are strong, heat resistant, and easy to machine. In order to reduce the surface area, the surface irregularities of the component can be reduced by polishing, etc. Gas can be reduced.

[0515] Alternatively, the components of the film forming apparatus 2700 may be replaced with iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0516] The members of the film forming apparatus 2700 are preferably made of metal, for example, quartz. When installing a viewing window, the surface is treated with iron fluoride or acid to suppress gas emission. It is advisable to thinly coat the surface with aluminum oxide or chromium oxide.

[0517] The adsorbates present in the deposition chamber are adsorbed to the inner walls, etc., and do not affect the pressure in the deposition chamber. This causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate is proportional to the evacuation speed. Although there is no relation between the amount of adsorbed matter and the amount of the adsorbed matter, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb the adsorbed material and evacuate the gas beforehand. The deposition chamber may be baked. This will increase the desorption rate of adsorbed substances by about 10 times. Baking can be performed at temperatures between 100℃ and 450℃. When removing adsorbed substances while introducing an inert gas into the deposition chamber, the substances cannot be desorbed by simply evacuating the chamber. The desorption rate of water and other impurities can be further increased. By heating the mixture to the same temperature as the heating, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas. Instead of the inert gas, oxygen or the like may be used. For example, when forming an oxide film, In some cases, it may be preferable to use oxygen, which is the main component. It is preferable to carry out the above steps.

[0518] Alternatively, the pressure in the deposition chamber can be increased by introducing an inert gas such as a heated rare gas or oxygen. It is preferable to increase the pressure and evacuate the deposition chamber again after a certain period of time has elapsed. By introducing the gas, it is possible to desorb the adsorbed substances in the film formation chamber, and the impurities present in the film formation chamber are reduced. This treatment can be repeated 2 to 30 times, preferably 5 to 15 times. It is effective to repeat the process within the following range: By introducing an inert gas or oxygen, preferably at a temperature of 50° C. or higher and 200° C. or lower, The pressure in the deposition chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less. More preferably, the pressure is set to 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or more. The film formation chamber is then heated for 5 to 300 minutes, preferably for 5 to 120 minutes. Thereafter, evacuation is preferably performed for a period of 10 minutes or more and 120 minutes or less.

[0519] Also, the desorption speed of the adsorbed substances can be further increased by forming a dummy film. The film formation is performed by forming a film on a dummy substrate using a method such as sputtering. A film is deposited on the plate and the inner wall of the deposition chamber, and impurities in the deposition chamber and substances adsorbed on the inner wall of the deposition chamber are removed from the film. It is preferable to use a dummy substrate that emits less gas. By performing the above, it is possible to reduce the impurity concentration in the film to be formed later. The film formation may be performed simultaneously with baking.

[0520] Next, the transfer chamber 2704 and the load lock chamber 2703a shown in FIG. The details of the atmospheric substrate transfer chamber 2702 and the atmospheric substrate supply chamber 2701 shown in FIG. The following description will be made based on the above. Note that FIG. 54(C) shows the atmospheric side substrate transfer chamber 2702 and the atmospheric side substrate A cross section of plate supply chamber 2701 is shown.

[0521] The transfer chamber 2704 shown in FIG. 54(B) is similar to the transfer chamber 2704 shown in FIG. 54(A). Please refer to the above.

[0522] The load lock chamber 2703a includes a substrate transfer stage 2752. The pressure in the load lock chamber 2703a is increased from a reduced pressure state to atmospheric pressure. When the pressure in the atmosphere-side substrate transfer chamber 2702 becomes atmospheric pressure, the transfer robot 276 3 to the substrate transfer stage 2752. 3a is evacuated to a reduced pressure state, and then the transfer robot installed in the transfer chamber 2704 2763 receives the substrate from the substrate delivery stage 2752 .

[0523] The load lock chamber 2703a is connected to a vacuum pump 2770 and a cryogenic It is connected to the vacuum pump 2770 and the cryopump 277 The exhaust system of 1 can be connected by referring to the connection method of the transfer chamber 2704. The unload lock chamber 2703b shown in FIG. It can have a configuration similar to that of the lock chamber 2703a.

[0524] The atmospheric substrate transfer chamber 2702 includes a transfer robot 2763. This allows the transfer of substrates between the cassette port 2761 and the load lock chamber 2703a. In addition, above the atmospheric substrate transfer chamber 2702 and the atmospheric substrate supply chamber 2701, HEPA filter (High Efficiency Particulate Air Filter) A mechanism for cleaning dust or particles such as a filter may be provided. .

[0525] The atmosphere side substrate supply chamber 2701 has a plurality of cassette ports 2761. The 2761 can accommodate multiple boards.

[0526] The target surface temperature is 100° C. or less, preferably 50° C. or less, and more preferably room temperature. In sputtering equipment that can handle large-area substrates, the temperature is set to about 25°C. However, targets of a size corresponding to a large area are often used. It is difficult to fabricate the targets without any seams. Although they are arranged in a large shape, there are inevitably small gaps. As the surface temperature of the target rises, zinc and other substances evaporate from the tiny gaps, gradually filling the gaps. If the gap widens, the backing plate or the backing plate may become damaged. The metal of the bonding material used to bond the electrode and the target is sputtered. This increases the impurity concentration. Therefore, the target must be cooled sufficiently. It is preferable that

[0527] Specifically, a metal having high electrical conductivity and high heat dissipation properties (e.g., In addition, a water channel is formed in the backing plate, and a sufficient amount of By flowing cooling water, the target can be cooled efficiently.

[0528] In addition, when the target contains zinc, the plasma damage is reduced by forming the film in an oxygen gas atmosphere. This reduces the image and makes it possible to obtain an oxide in which zinc is less likely to volatilize.

[0529] By using the above-mentioned film formation apparatus, the hydrogen concentration can be measured by secondary ion mass spectrometry (SIMS:Se In condary ion mass spectrometry, 2 0 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is more preferred: Or 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 An oxide semiconductor film can be formed as follows.

[0530] In addition, the nitrogen concentration was 5×10 19 atoms / cm 3 Less than, preferably is 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The oxide semiconductor It is possible to form a membrane.

[0531] In addition, the carbon concentration was 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The oxide semiconductor It is possible to form a membrane.

[0532] In addition, thermal desorption spectroscopy (TDS) Gas molecules (atoms) with m / z of 2 (such as hydrogen molecules) by NMR spectroscopy, m Gas molecules (atoms) with m / z 18, gas molecules (atoms) with m / z 28, and gas molecules (atoms) with m / z The amount of gas molecules (atoms) released with a mass of 44 is 1×10 19 pieces / cm 3 The following are the preferred Or 1×10 18 pieces / cm 3 An oxide semiconductor film can be formed as follows.

[0533] By using the above-described film formation apparatus, impurities can be prevented from being mixed into the oxide semiconductor. By forming a film in contact with the oxide semiconductor using the above-mentioned film formation apparatus, This can prevent impurities from being mixed into the oxide semiconductor from a film in contact with the oxide semiconductor.

[0534] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0535] 100 Transistors 101 Substrate 102 Insulating layer 103 Insulating layer 104 Oxide layer 105 Insulating layer 106 Electrode 107 Insulating layer 108 Structure 109 Electrode 110 Insulating layer 111 Insulating layer 112 Insulating layer 115 Insulating Layer 116 Insulating Layer 119 Electrode 125 Insulating layer 126 Conductive Layer 127 Insulating Layer 128 Insulating Layer 129 Conductive Layer 131 Dopant 135 areas 141 Capacitive element 142 Capacitive element 145 Mixed layer 150 Transistors 160 Transistors 170 Transistors 180 Transistors 190 Transistors 191 Transistor 192 Transistors 193 Transistor 194 Transistors 195 Transistors 220 wells 221 p-type semiconductors 223 n-type semiconductor 224 Aperture 225 Aperture 251 Wiring 252 Wiring 253 Wiring 254 Wiring 255 Wiring 256 nodes 257 Capacitive element 260 circuits 270 circuits 273 Electrode 280 circuits 281 Transistor 282 Transistor 283 Channel Formation Region 284 Low concentration p-type impurity region 285 High concentration p-type impurity region 286 Insulating Layer 287 Electrode 288 Structure 289 Transistor 290 circuits 291 Transistor 382 Ec 386 Ec 390 Trap Levels 400 Semiconductor equipment 401 Substrate 402 Insulator 403 Insulating layer 404 Insulating layer 405 Insulation Layer 406 Contact plug 407 Insulating Layer 408 Contact plug 410 Semiconductor devices 411 Substrate 414 Element isolation layer 415 Insulating layer 420 Semiconductor Devices 421 Electrode 422 Electrode 427 Electrode 429 Electrode 430 Semiconductor Devices 442 Insulating layer 477 Bulkhead 487 Wiring 488 Electrode 489 Contact plug 520 Substrate 530 Substrate 550 Interposer 551 Chip 552 Terminal 553 Molding resin 560 Panel 561 Printed Wiring Board 562 packages 563 FPC 564 Battery 600 Imaging device 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitor 607 nodes 608 Wiring 609 Wiring 610 Pixel driving circuit 611 Wiring 621 Pixel section 622 pixels 623 pixels 624 Filter 625 Lens 626 Wiring group 660 light 681 Photoelectric conversion layer 682 Transparent conductive layer 686 Electrode 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Elements 707 Capacitive element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Memory Element 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1281 Transistor 1283 Channel formation region 1284 Low concentration n-type impurity region 1285 High concentration n-type impurity region 2700 Film deposition equipment 2701 Atmospheric side substrate supply chamber 2702 Atmospheric side substrate transfer chamber 2704 Delivery Room 2705 ​​Substrate heating chamber 2751 Cryotrap 2752 Stage 2761 Cassette Port 2762 Alignment Port 2763 Transport Robot 2764 Gate valve 2765 Heating Stage 2766 Target 2767 Target Shield 2768 PCB Holder 2769 Circuit Board 2770 Vacuum Pump 2771 Cryopump 2772 Turbomolecular Pump 2780 Mass Flow Controller 2781 Refiner 2782 Gas heating mechanism 2784 Variable parts 2791 Power supply 2900 Portable Game Console 2901 Case 2902 Case 2903 Display section 2904 Display section 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Case 2912 Display section 2913 Camera 2914 Speaker section 2915 Button 2916 External connection part 2917 Mike 2920 Notebook Personal Computer 2921 Case 2922 Display section 2923 Keyboard 2924 Pointing Device 2940 Video Camera 2941 Case 2942 Case 2943 Display section 2944 Operation key 2945 Lens 2946 Connection 2950 Information terminal 2951 Case 2952 Display section 2960 Information terminal 2961 Case 2962 Display section 2963 Band 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 Icons 2970 Electric refrigerator 2971 Case 2972 Refrigerator door 2973 Freezer door 2980 Automobiles 2981 Body 2982 wheels 2983 Dashboard 2984 Light 3100 display device 3125 Light emitting element 3130 pixels 3131 Display area 3132 Circuit 3133 Circuit 3135 Scan Lines 3136 Signal Line 3137 Pixel circuit 3152 Circuit 3153 Circuit 3232 Transistor 3233 Capacitive element 3431 Transistor 3432 Liquid crystal elements 3434 Transistor 3435 nodes 3436 nodes 3437 nodes 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Capacitive element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4102 Insulating layer 4103 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4510 Bulkhead 4511 Light-emitting layer 4513 Light emitting element 4514 Filling material 5100 pellets 5120 PCB 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Sensor 6005 FPC 6006 Display Panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 100a transistor 102a Insulating layer 104a Oxide layer 104b Oxide layer 104c oxide layer 105a electrode 105b electrode 109a electrode 109b electrode 109c electrode 112d Contact plug 113a Contact plug 113b Contact plug 113c contact plug 114a electrode 114b electrode 114c electrode 118a Oxide semiconductor layer 118b Oxide semiconductor layer 124a oxide layer 124b Oxide layer 124c oxide layer 126a aperture 126b aperture 126c aperture 194a Transistor 195a Transistor 2703a Load Lock Chamber 2703b Unloading lock room 2706a Deposition chamber 2706b Deposition chamber 2706c Deposition chamber 2766a Target 2766b Target 2767a Target Shield 2767b Target Shield 2790a Magnet Unit 2790b Magnet unit 281a Transistor 281b Transistor 282a Transistor 282b Transistor 383a Ec 383b Ec 383c Ec 4018b FPC 406a contact plug 406b contact plug 406c contact plug 407a Insulating layer 413a electrode 413b Electrode 413c electrode 413d electrode 487a Conductive layer 487b Conductive layer 622B pixels 622G pixels 622R pixels 624B Filter 624G Filter 624R Filter 686a Conductive layer 686b Conductive layer

Claims

[Claim 1] A semiconductor device comprising a first oxide layer, a second oxide layer, an insulating layer, a first electrode, a second electrode, and a structure; the first oxide layer is in contact with the second oxide layer; the second oxide layer is in contact with the third oxide layer; the first oxide layer, the second oxide layer and the third oxide layer have first regions overlapping each other; the first electrode is disposed on the first region via the insulating layer; the structure is provided on the second oxide layer to cover a side surface of the first electrode; the second oxide layer has a second region overlapping the first electrode, a third region overlapping the structure, a fourth region in contact with the second electrode, and a fifth region in contact with the third electrode; the second oxide layer is an oxide semiconductor; A transistor in which the third to fifth regions contain an element different from an element contained in the second region.

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