Light emitting package and display device

Abstract

To provide a simplified light emitting chip capable of reducing a processing time while protecting a light emitting stacked structure.SOLUTION: A simplified light emitting chip includes: a first LED sub-unit; a second LED sub-unit arranged on the first LED sub-unit; a third LED sub-unit arranged on the second LED sub-unit; a first bonding layer arranged between the first and second LED sub-units; a second bonding layer that is arranged between the second and the third LED sub-units; and a first connection electrode that is electrically connected to and overlaps with at least one of the first, the second, and third LED sub-units. Therein: the first connection electrode includes a first side surface and a second side surface that face each other, the first side surface having a first length, and the second side surface having a second length; a difference between the length of the first side surface and the length of the second side surface in the first connection electrode is larger than a thickness of at least one of the LED sub-units.SELECTED DRAWING: Figure 1C

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a light-emitting chip for a display and a method for manufacturing the same, and more specifically, to a micro light-emitting chip having a stacked structure and a method for manufacturing the same.

Background Art

[0002] Light-emitting diodes (LEDs), which are inorganic light sources, are used in various technical fields such as displays, in-vehicle lamps, and general lighting. Light-emitting diodes have characteristics such as long life, low power consumption, and high responsiveness, and are rapidly spreading as a replacement for existing light sources.

[0003] Light-emitting diodes have mainly been used as light sources for the backlights of display devices. However, recently, micro-LED displays that can directly display images using light-emitting diodes have been developed.

[0004] Generally, display devices realize various colors using a mixture of blue, green, and red light. A display device includes pixels having sub-pixels corresponding to each of blue, green, and red colors, and the color of a certain pixel is determined based on the colors of its sub-pixels, and an image can be displayed by a combination of pixels.

[0005] Since LEDs can emit various colors depending on their constituent materials, display devices can usually arrange individual LED chips that emit blue, green, and red light on a two-dimensional plane. However, if one LED chip is provided for each sub-pixel, the number of LED chips that need to be mounted to form a display device becomes very large, for example, hundreds of thousands or more, millions or more, and the mounting work may take a great deal of time and effort. Furthermore, since the sub-pixels are arranged on the two-dimensional plane of the display device, a relatively large area is required for one pixel including the sub-pixels for blue, green, and red light. If the light-emitting area of each sub-pixel is reduced, there is a problem that the luminance of the sub-pixel deteriorates.

[0006] In addition, since micro-LEDs generally have a very small surface area of about 10,000 square μm or less, various technical problems have arisen due to this small size. For example, an array of micro-LEDs may be formed on a substrate, and the substrate may be cut to individualize the micro-LEDs into individual micro-LED chips. Thereafter, the micro-LED chips may be mounted on another substrate such as a printed circuit board, and various transfer techniques may be used in the process. However, in these transfer steps, each micro-LED chip is generally difficult to handle due to its small size and fragile structure.

[0007] The above information disclosed in this "background" is only for understanding the background of the concept of the present invention, and thus may include information that does not fall within the prior art.

Summary of the Invention

Problems to be Solved by the Invention

[0008] A light-emitting chip configured according to the principles of the present invention and some exemplary embodiments can protect the light-emitting layer structure during various transfer processes.

[0009] A light-emitting chip, such as a micro-LED, configured according to the principles of the present invention and some exemplary embodiments, and a display using the same have a simplified structure and can shorten the time of the mounting process during manufacturing.

[0010] Additional features of the concept of the present invention are described in the following description, and will become apparent in part from the description or can be learned by practice of the concept of the present invention.

Means for Solving the Problems

[0011] The light-emitting chip according to an exemplary embodiment includes a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a first bonding layer disposed between the first and second LED sub-units, a second bonding layer disposed between the second and third LED sub-units, and a first connection electrode that is electrically connected to and overlaps at least one of the first, second, and third LED sub-units. The first connection electrode has opposing first and second side surfaces, the first side surface has a first length, and the second side surface has a second length. The difference between the length of the first side surface and the length of the second side surface in the first connection electrode is greater than the thickness of at least one of the LED sub-units.

[0012] The light-emitting chip may further include a substrate on which the first LED sub-unit is disposed, and a passivation layer that at least partially surrounds the first connection electrode and exposes a side surface of the substrate.

[0013] Also, the first side surface may face the outside of the light-emitting chip, and the second side surface may face the center of the light-emitting chip.

[0014] The passivation layer may expose a side surface of the first LED sub-unit and cover at least one side surface of the second and third LED sub-units.

[0015] The passivation layer may include at least one of an epoxy molding compound and a polyimide film, and the passivation layer may cover an upper surface of the third LED sub-unit.

[0016] The passivation layer may transmit light emitted from the first, second, and third LED sub-units.

[0017] A thickness of a part of the passivation layer that overlaps the third LED sub-unit may be about 100 μm or less.

[0018] The light-emitting chip further includes a second connection electrode electrically connected to the first LED sub-unit, a third connection electrode electrically connected to the second LED sub-unit, and a fourth connection electrode electrically connected to the third LED sub-unit. The first connection electrode is electrically connected to each of the first, second, and third LED sub-units, and each of the first, second, third, and fourth connection electrodes may have an elongated shape protruding in a direction away from the substrate such that their respective upper surfaces are disposed above the upper surface of the third LED sub-unit.

[0019] At least one lower surface of the first, second, third, and fourth connection electrodes may have an area larger than its upper surface.

[0020] At least one of the first, second, third, and fourth connection electrodes may overlap with the respective side surfaces of the first, second, and third LED sub-units.

[0021] The first connection electrode may be electrically connected to each of the first, second, and third LED sub-units via first, second, and third lower contact electrodes respectively, and the first, second, and third lower contact electrodes may be disposed on different planes from each other.

[0022] The third LED sub-unit may include a first-type semiconductor layer, an active layer, a second-type semiconductor layer, and an upper contact electrode in ohmic contact with the first-type semiconductor layer. The first-type semiconductor layer may include a recess, and the upper contact electrode may be formed in the recess of the first-type semiconductor layer.

[0023] The light-emitting chip may further include a substrate. The first LED sub-unit may include a first LED light-emitting laminate. The second LED sub-unit may include a second LED light-emitting laminate. The third LED sub-unit may include a third LED light-emitting laminate. The areas of the first, second, and third LED light-emitting laminates overlapping with the substrate may sequentially decrease. At least one of the light-emitting laminates may include micro-LEDs with a surface area of about 10,000 square μm or less.

[0024] The difference in length between the first side surface and the second side surface of the first connection electrode may be in the range of about 3 μm to about 16 μm.

[0025] A light-emitting package according to another exemplary embodiment includes a light-emitting chip. The light-emitting chip includes a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a plurality of connection electrodes respectively disposed on the first, second, and third LED sub-units, a circuit board disposed on a first surface facing the light-emitting chip and respectively connected to the connection electrodes, and a molding layer substantially covering all of the outer surface of the light-emitting chip.

[0026] The light-emitting chip may further include a passivation layer disposed between the plurality of connection electrodes. The passivation layer and the molding layer may include the same material.

[0027] The light-emitting chip may further include a passivation layer disposed between the plurality of connection electrodes. The passivation layer and the molding layer may include different materials.

[0028] A part of the molding layer disposed on the light-emitting chip may have a thickness of less than about 100 μm.

[0029] At least one of the plurality of connection electrodes may have opposing first and second side surfaces, each having a first length and a second length, and the difference between the first length and the second length may be at least about 3 μm.

[0030] At least one of the plurality of connection electrodes may overlap with respective side surfaces of the first, second, and third LED sub-units.

[0031] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Brief Description of the Drawings

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the concept of the invention.

[0033]

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Embodiments for Carrying Out the Invention

[0034] In the following description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable terms that are non-limiting examples of an apparatus or method that employs one or more of the inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments can be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Further, the various exemplary embodiments may be different but need not be exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept of the present invention.

[0035] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of various details of several ways in which the concepts of the present invention can be actually implemented. Thus, unless otherwise specified, features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments can be combined, separated, exchanged, and / or rearranged in other ways without departing from the concepts of the present invention.

[0036] The use of cross-hatching and / or shading in the accompanying drawings is generally for clarifying the boundaries between adjacent elements. Therefore, regardless of the presence or absence of cross-hatching or shading, unless otherwise specified, it does not convey or indicate preferences or requirements regarding specific materials, material properties, dimensions, ratios, commonalities between the illustrated elements, and / or other characteristics, attributes, and properties of the elements. Further, in the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for purposes of clarification and / or explanation. If the exemplary embodiments can be implemented differently, they may be executed in a different order from the described order. For example, two processes described consecutively may be executed substantially simultaneously or in an order reverse to the described order. Also, like reference numerals indicate like elements.

[0037] When an element such as a layer is "above", "connected to", or "coupled to" another element or layer, it may be directly above, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is "directly above", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" may refer to a physical, electrical, and / or fluid connection, regardless of the presence of intervening elements. Further, the D1 axis, D2 axis, and D3 axis are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the D1 axis, D2 axis, and D3 axis may be orthogonal to each other, or may represent different directions that are not orthogonal to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, for example, XYZ, XYY, YZ, and ZZ. In this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] In this specification, terms such as "first", "second", etc. may be used to describe various types of elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element described below could be called the second element without departing from the teachings of the present disclosure.

[0039] In this specification, for the purpose of explanation, spatially relative terms such as "beneath", "below", "under", "lower", "above", "upper", "over", "higher", "side" (such as, for example, "sidewall") etc. can be used to describe the relationship between an element shown in the drawings and other elements. Spatially relative terms are intended to encompass different orientations of the device in use, operation and manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an upward and a downward orientation. Further, the device may be in other orientations (for example, rotated 90 degrees or otherwise), and in such cases, the spatially relative descriptors used in this specification will be interpreted accordingly.

[0040] The terms used in this specification are for the purpose of describing particular embodiments and are not intended to be limiting. The singular forms "a", "an" and "the" used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprises", "comprising", "includes" and / or "including" as used in this specification specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. Also, in this specification, the terms "substantially", "about" and other similar terms are used as terms of approximation and not of degree, and should be noted as being utilized to account for the inherent deviations of measured, calculated and provided values that would be recognized by those of ordinary skill in the art.

[0041] In this specification, various exemplary embodiments are described with reference to cross-sectional views and / or exploded views that are schematic views of idealized exemplary embodiments and / or intermediate structures. Therefore, for example, variations from the shapes in the figures are expected as a result of manufacturing techniques and / or tolerances. Accordingly, the exemplary embodiments disclosed herein should not necessarily be construed as being limited to the shapes of the specific illustrated regions, but include, for example, shape deviations resulting from manufacturing. Thus, the regions illustrated in the drawings are essentially schematic, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and in such cases, are not necessarily intended to be limiting.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined as in a commonly used dictionary are to be interpreted as having a meaning that coincides with the meaning in the context of the relevant art unless explicitly so defined herein, and are not to be interpreted in an idealized or overly formal sense.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As used herein, a light-emitting laminate structure, a light-emitting chip, or a light-emitting package according to an exemplary embodiment may include a micro LED having a surface area of less than about 10,000 square μm, as is known in the art. In other exemplary embodiments, the micro LED may have a surface area of less than about 4,000 square μm or less than about 2,500 square μm, depending on the specific application.

[0044] FIG. 1A is a schematic diagram of a light-emitting chip configured according to an exemplary embodiment of the present invention. FIG. 1B is a perspective plan view of the light-emitting chip of FIG. 1A according to the exemplary embodiment, FIGS. 1C and 1D are cross-sectional views taken along line A-A' and line B-B' of the light-emitting chip of FIG. 1B according to the exemplary embodiment, respectively, and FIG. 1E is an SEM image of the light-emitting chip of FIG. 1A according to the exemplary embodiment.

[0045] Referring to FIGS. 1A and 1B, a light-emitting chip 100 according to an exemplary embodiment includes a light-emitting laminate structure, a first connection electrode 20ce, a second connection electrode 30ce, a third connection electrode 40ce, and a fourth connection electrode 50ce formed on the light-emitting laminate structure, and a passivation layer 90 surrounding the connection electrodes 20ce, 30ce, 40ce, and 50ce. An array of the light-emitting chips 100 may be formed on a substrate 11. The light-emitting chip 100 shown in FIG. 1A exemplarily shows a single chip separated from the array, which will be described in detail below. In some exemplary embodiments, the light-emitting chip 100 including the light-emitting laminate structure may be further processed to form a light-emitting package, which will be described in more detail later.

[0046] Referring to FIGS. 1A to 1D, the light-emitting chip 100 according to the illustrated exemplary embodiment includes a light-emitting stack structure, which may include a first LED subunit, a second LED subunit, and a third LED subunit disposed on a substrate 11. The first LED subunit may include a first LED light-emitting stack (hereinafter referred to as the first light-emitting stack) 20, the second LED subunit may include a second LED light-emitting stack (hereinafter referred to as the second light-emitting stack) 30, and the third LED subunit may include a third LED light-emitting stack (hereinafter referred to as the third light-emitting stack) 40. In the drawings, a light-emitting stack structure including three light-emitting stacks 20, 30, and 40 is shown, but the concept of the present invention is not limited to a specific number of light-emitting stacks formed in the light-emitting stack structure. For example, in some exemplary embodiments, the light-emitting stack structure may include two or more light-emitting stacks therein. Hereinafter, the light-emitting chip 100 will be described with reference to a light-emitting stack structure including three light-emitting stacks 20, 30, and 40 according to an exemplary embodiment.

[0047] The substrate 11 may include a light-transmissive insulating material for transmitting light. However, in some exemplary embodiments, the substrate 11 may be formed semi-transparent to transmit only light having a specific wavelength or may be formed partially transparent to transmit only a part of light having a specific wavelength. Also, the substrate 11 may be a growth substrate on which the third light-emitting stack 40 can be epitaxially grown, for example, a sapphire substrate or the like. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the substrate 11 may include various other transparent insulating materials. For example, the substrate 11 may be glass, quartz, silicon, an organic polymer, or an organic-inorganic composite material, such as silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3) or may include a silicon substrate or the like. As another example, in some exemplary embodiments, the substrate 11 may be a printed circuit board or a composite substrate that includes electrical wiring therein to provide a light emission signal and a common voltage to each of the light emitting laminates formed thereon.

[0048] Each of the first, second, and third light emitting laminates 20, 30, and 40 is configured to emit light toward the substrate 11. Therefore, for example, the light emitted from the first light emitting laminate 20 may pass through the second and third light emitting laminates 30 and 40. According to an exemplary embodiment, the light emitted from each of the first, second, and third light emitting laminates 20, 30, and 40 may have different wavelength bands, and the light emitting laminate disposed farther from the substrate 11 may emit light having a longer wavelength band. For example, the first, second, and third light emitting laminates 20, 30, and 40 may emit red light, green light, and blue light, respectively. However, the concept of the present invention is not limited thereto. As another example, the first, second, and third light emitting laminates 20, 30, and 40 may emit red light, blue light, and green light, respectively. As yet another example, in another exemplary embodiment, one or more light emitting laminates may emit light having substantially the same wavelength band. As yet another example, when the light emitting laminate structure includes micro LEDs having a surface area of less than about 10,000 square μm as known in the art or less than about 4,000 square μm or 2,500 square μm in other exemplary embodiments, due to the small form factor of the micro LEDs, the light emitting laminate disposed far from the substrate 11 may emit light having a shorter wavelength band than the light emitted from the one disposed close to the substrate 11 without adversely affecting the operation. In this case, since the micro LEDs can be operated at a low operating voltage, it may not be necessary to provide another color filter between the light emitting laminates. Hereinafter, the first, second, and third light emitting laminates 20, 30, and 40 will be exemplarily described as emitting red light, green light, and blue light, respectively, according to an exemplary embodiment.

[0049] The first light-emitting laminate 20 includes a first-type semiconductor layer 21, an active layer 23, and a second-type semiconductor layer 25. According to an exemplary embodiment, the first light-emitting laminate 20 may include, without being limited thereto, semiconductor materials that emit red light, such as aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), and gallium phosphide (GaP).

[0050] The first upper contact electrode 21n is disposed on the first-type semiconductor layer 21 and forms an ohmic contact with the first-type semiconductor layer 21. The first lower contact electrode 25p may be disposed under the second-type semiconductor layer 25 of the first light-emitting laminate 20. According to an exemplary embodiment, a part of the first-type semiconductor layer 21 may be patterned, and the first upper contact electrode 21n may be disposed in the patterned region of the first-type semiconductor layer 21 to increase the level of ohmic contact therebetween. The first upper contact electrode 21n may have a single-layer structure or a multilayer structure and may include, without being limited thereto, Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or alloys thereof, such as Au-Te alloy and Au-Ge alloy. In an exemplary embodiment, the first upper contact electrode 21n has a thickness of about 100 nm and may include a metal having a high reflectivity to increase the downward light-emitting efficiency toward the substrate 11.

[0051] The second light-emitting laminate 30 includes a first-type semiconductor layer 31, an active layer 33, and a second-type semiconductor layer 35. According to an exemplary embodiment, the second light-emitting laminate 30 may include, without being limited thereto, semiconductor materials that emit green light, such as indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), aluminum gallium phosphide (AlGaP), etc. A second lower contact electrode 35p is disposed under the second-type semiconductor layer 35 of the second light-emitting laminate 30.

[0052] The third light-emitting laminate 40 includes a first-type semiconductor layer 41, an active layer 43, and a second-type semiconductor layer 45. According to an exemplary embodiment, the third light-emitting laminate 40 may include, without being limited thereto, a semiconductor material that emits blue light, such as gallium nitride (GaN), indium gallium nitride (InGaN), zinc selenide (ZnSe), etc. A third lower contact electrode 45p is disposed on the second-type semiconductor layer 45 of the third light-emitting laminate 40.

[0053] According to an exemplary embodiment, each of the first-type semiconductor layers 21, 31, and 41 and each of the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light-emitting laminates 20, 30, and 40 may have a single-layer structure or a multilayer structure, and in some exemplary embodiments, may include superlattice layers. Further, the active layers 23, 33, and 43 of the first, second, and third light-emitting laminates 20, 30, and 40 may have a single quantum well structure or a multiple quantum well structure.

[0054] Each of the first, second, and third lower contact electrodes 25p, 35p, and 45p may include a transparent conductive material for transmitting light. For example, the lower contact electrodes 25p, 35p, 45p are not limited thereto and may include transparent conductive oxides (TCOs) such as tin oxide (SnO), indium oxide (InO 2 ), zinc oxide (ZnO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), etc.

[0055] A first adhesive layer 61 is disposed between the first light-emitting laminate 20 and the second light-emitting laminate 30, and a second adhesive layer 63 is disposed between the second light-emitting laminate 30 and the third light-emitting laminate 40. The first adhesive layer 61 and the second adhesive layer 63 may include a non-conductive material that transmits light. For example, the first adhesive layer 61 and the second adhesive layer 63 may each include OCA (Optical Clear Adhesive), and without being limited thereto, may include epoxy, polyimide, SU8, SOG (Spin-on Glass), BCB (Benzocyclobutene), etc.

[0056] According to the illustrated exemplary embodiments, the first insulating layer 81 and the second insulating layer 83 are disposed on at least a part of the side surfaces of the first, second, and third light-emitting laminate bodies 20, 30, and 40. At least one of the first insulating layer 81 and the second insulating layer 83 may include various organic or inorganic insulating materials such as polyimide, SiO 2 , SiNx, Al 2 O 3 . For example, at least one of the first insulating layer 81 and the second insulating layer 83 may include a distributed Bragg reflector (DBR). As another example, at least one of the first and second insulating layers 81 and 83 may include an organic polymer colored black. In some exemplary embodiments, an electrically floating metal reflective layer may be further disposed on the first and second insulating layers 81 and 83 to reflect the light emitted from the light-emitting laminate bodies 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, at least one of the first and second insulating layers 81 and 83 may have a single-layer structure or a multilayer structure formed of two or more insulating layers having different refractive indices from each other.

[0057] According to the exemplary embodiments, each of the first, second, and third light-emitting laminate bodies 20, 30, and 40 may be independently driven. More specifically, a common voltage may be applied to one of the first and second type semiconductor layers of each light-emitting laminate body, and respective light-emitting signals may be applied to the other of the first and second type semiconductor layers of each light-emitting laminate body. For example, according to the illustrated exemplary embodiments, the first type semiconductor layers 21, 31, 41 of each light-emitting laminate body may be n-type, and the second type semiconductor layers 25, 35, 45 of each light-emitting laminate body may be p-type. In this case, the third light-emitting laminate body 40 may have a reverse lamination order such that the p-type semiconductor layer 45 is disposed on the active layer 43 in order to simplify the manufacturing process as compared with the first light-emitting laminate body 20 and the second light-emitting laminate body 30. Hereinafter, according to the illustrated exemplary embodiments, the first type semiconductor layer and the second type semiconductor layer may be interchangeably referred to as p-type and n-type, respectively.

[0058] Further, each of the first, second, and third lower contact electrodes 25p, 35p, and 45p respectively connected to the p-type semiconductor layers 25, 35, and 45 of the light-emitting laminate may be connected to the fourth contact portion 50C, and the fourth contact portion 50C may be connected to the fourth connection electrode 50ce to receive a common voltage from the outside. On the other hand, the n-type semiconductor layers 21, 31, and 41 of the light-emitting laminate may be connected to the first contact portion 20c, the second contact portion 30c, and the third contact portion 40c respectively, and may receive corresponding light-emitting signals via the first, second, and third connection electrodes 20ce, 30ce, and 40ce respectively. In this way, each of the first, second, and third light-emitting laminates 20, 30, and 40 can be independently driven while having a common p-type light-emitting laminate structure.

[0059] The light-emitting chip 100 according to the illustrated exemplary embodiment has a common p-type structure, but the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the first-type semiconductor layers 21, 31, and 41 of each light-emitting laminate may be p-type, and the second-type semiconductor layers 25, 35, and 45 of each light-emitting laminate may be n-type to form a common n-type light-emitting laminate structure. Further, in some exemplary embodiments, the stacking order of each light-emitting laminate may be variously changed without being limited to that shown in the drawings. Hereinafter, the light-emitting chip 100 according to the illustrated exemplary embodiment will be described with reference to the common p-type light-emitting laminate structure.

[0060] According to the illustrated exemplary embodiment, the first contact portion 20c includes a first pad 20pd and a first bump electrode 20bp electrically connected to the first pad 20pd. The first pad 20pd is disposed on the first upper contact electrode 21n of the first light-emitting laminate 20 and is connected to the first upper contact electrode 21n through a first contact hole 20CH defined by penetrating the first insulating layer 81. Further, at least a part of the first bump electrode 20bp may overlap the first pad 20pd, and in the overlapping portion between the first bump electrode 20bp and the first pad 20pd, the first bump electrode 20bp is connected to the first pad 20pd through a first through hole 20ct with the second insulating layer 83 interposed therebetween. In this case, the first pad 20pd and the first bump electrode 20bp may have substantially the same shape so as to overlap each other without being limited thereto.

[0061] The second contact portion 30c includes a second pad 30pd and a second bump electrode 30bp electrically connected to the second pad 30pd. The second pad 30pd is disposed on the first-type semiconductor layer 31 of the second light-emitting laminate 30 and is connected to the first-type semiconductor layer 31 through a second contact hole 30CH defined by penetrating the first insulating layer 81. Note that at least a part of the second bump electrode 30bp may overlap the second pad 30pd. The second bump electrode 30bp may be connected to the second pad 30pd through a second through hole 30ct with the second insulating layer 83 interposed therebetween in the overlapping portion between the second bump electrode 30bp and the second pad 30pd.

[0062] The third contact portion 40C includes a third pad 40pd and a third bump electrode 40bp electrically connected to the third pad 40pd. The third pad 40pd is disposed on the first-type semiconductor layer 41 of the third light-emitting laminate 40, and is connected to the first-type semiconductor layer 41 through a third contact hole 40CH defined by penetrating the first insulating layer 81. Note that at least a part of the third bump electrode 40bp may overlap with the third pad 40pd. The third bump electrode 40bp may be connected to the third pad 40pd through a third through hole 40ct with a second insulating layer 83 interposed therebetween in a portion where the third bump electrode 40bp overlaps with the third pad 40pd.

[0063] The fourth contact portion 50c includes a fourth pad 50pd and a fourth bump electrode 50bp electrically connected to the fourth pad 50pd. The fourth pad 50pd is connected to the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light-emitting laminates 20, 30, and 40 through a first sub-contact hole 50CHa and a second sub-contact hole 50CHb defined by the first, second, and third lower contact electrodes 25p, 35p, and 45p of the first, second, and third light-emitting laminates 20, 30, and 40. In particular, the fourth pad 50pd is connected to the first lower contact electrode 25p through the second sub-contact hole 50CHb, and is connected to the second and third lower contact electrodes 35p and 45p through the first sub-contact hole 50CHa. Thus, since the fourth pad 50pd is connected to the second and third lower contact electrodes 35p and 45p through one first sub-contact hole 50CHa, the manufacturing process of the light-emitting chip 100 can be simplified, and the area occupied by the contact holes of the light-emitting chip 100 can be reduced. Note that at least a part of the fourth bump electrode 50bp may overlap with the fourth pad 50pd. The fourth bump electrode 50bp may be connected to the fourth pad 50pd through a fourth through hole 50ct with a second insulating layer 83 interposed therebetween in a portion where the fourth bump electrode 50bp overlaps with the fourth pad 50pd.

[0064] The concept of the present invention is not limited to the specific structures of the contact portions 20C, 30C, 40C, and 50C. For example, in some exemplary embodiments, the bump electrodes 20bp, 30bp, 40bp, or 50bp may be omitted from at least one of the contact portions 20C, 30C, 40C, and 50C. In this case, the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C may be connected to their respective connection electrodes 20ce, 30ce, 40ce, and 50ce. In some exemplary embodiments, the bump electrodes 20bp, 30bp, 40bp, and 50bp may be omitted from each of the contact portions 20C, 30C, 40C, and 50C, and the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C may be directly connected to their respective connection electrodes 20ce, 30ce, 40ce, and 50ce.

[0065] According to an exemplary embodiment, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be formed at various positions. For example, when the light-emitting chip 100 has a substantially rectangular shape as shown in the drawing, the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be arranged to surround each corner of the substantially rectangular shape. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the light-emitting chip 100 may be formed to have various shapes, and the first, second, third, and fourth contact portions 20C, 30C, 40C, and 50C may be formed at other locations according to the shape of the light-emitting device.

[0066] The first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are insulated from each other with spaces therebetween. Further, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp are insulated from each other with spaces therebetween. According to an exemplary embodiment, each of the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp may cover at least a part of the side surfaces of the first, second, and third light-emitting laminates 20, 30, and 40, thereby facilitating on-site dissipation of heat generated from the first, second, and third light-emitting laminates 20, 30, and 40.

[0067] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape protruding away from the substrate 11, and the upper surface of each of the connection electrodes 20ce, 30ce, 40ce, and 50ce is provided on the upper surface of the first light-emitting laminate 20. The connection electrodes 20ce, 30ce, 40ce, and 50ce may include, without limitation, metals such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. For example, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or a plurality of different metal layers to reduce the stress applied thereto due to the elongated shape of the connection electrodes 20ce, 30ce, 40ce, and 50ce. In another exemplary embodiment, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include Cu, an additional metal may be deposited or plated thereon to suppress oxidation of Cu. In some exemplary embodiments, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include Cu / Ni / Sn, Cu may prevent Sn from penetrating into the light-emitting laminate structure. In some exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce may include a seed layer for forming a metal layer during a plating process, which will be described in more detail below.

[0068] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light-emitting layer structure and an external wiring or electrode described later. According to an exemplary embodiment, when the light-emitting chip 100 includes a micro-LED having a surface area of less than about 10,000 square μm as known in the art or less than about 4,000 square μm or 2,500 square μm in other exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one portion of the first, second, and third light-emitting layer bodies 20, 30, and 40, as shown in the drawings. More specifically, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on a side surface of the light-emitting layer structure. By doing so, since the area of the lower surface of the connection electrode is larger than its upper surface, a larger contact area can be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting layer structure. Therefore, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be formed more stably on the light-emitting layer structure body. For example, one side surface L1, L2, L3, L4 facing the outside of the connection electrodes 20ce, 30ce, 40ce, and 50ce and the other side surface L1', L2', L3', L4' facing the center of the light-emitting chip 100 may have different lengths (or heights). More specifically, the length of one side surface facing the outside of the connection electrode may be greater than the length of the other side surface facing the center of the light-emitting chip 100. For example, the difference in the lengths of two opposing surfaces L, L' of the connection electrode may be greater than at least one thickness (or height) of the light-emitting layer bodies 20, 30, and 40. In this way, the contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting layer structure can be increased, and the structure of the light-emitting chip 100 can be strengthened. Also, since the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least two steps formed on the side surface of the light-emitting layer structure, heat generated from the light-emitting layer structure can be more efficiently dissipated to the outside.

[0069] According to an exemplary embodiment, the difference in length between one side surface L1, L2, L3, or L4 facing the outside of the connection electrode and the other side surface L1', L2', L3', L4' facing the center of the light-emitting chip 100 may be about 3 μm. In this case, the light-emitting laminate structure may be formed thinly. In particular, the first light-emitting laminate 20 may have a thickness of about 1 μm, the second light-emitting laminate 30 may have a thickness of about 0.7 μm, the third light-emitting laminate 40 may have a thickness of about 0.7 μm, and the first and second adhesive layers may each have a thickness of about 0.2 μm to about 0.3 μm, but is not limited thereto. According to another exemplary embodiment, the difference in length between one side surface L1, L2, L3, or L4 facing the outside of the connection electrode and the other side surface L1', L2', L3', L4' facing the center of the light-emitting chip 100 may be about 10 μm to 16 μm. In this case, the light-emitting laminate structure may be formed relatively thickly and may have a more stable structure. In particular, the first light-emitting laminate 20 may have a thickness of about 4 μm to 5 μm, the second light-emitting laminate 30 may have a thickness of about 3 μm, the third light-emitting laminate 40 may have a thickness of about 3 μm, and the first adhesive layer and the second adhesive layer may each have a thickness of about 3 μm, but is not limited thereto. According to still another exemplary embodiment, the difference in length between one side surface L1, L2, L3, or L4 facing the outside of the connection electrode and the other side surface L1', L2', L3', L4' facing the center of the light-emitting chip 100 may be about 25% of the length of the longest side surface. However, the concept of the present invention is not limited to a specific difference in length between the opposing surfaces of the connection electrode, and the difference in length between the opposing surfaces of the connection electrode may be various.

[0070] In some exemplary embodiments, at least one of the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap with the respective side surfaces of the light-emitting laminates 20, 30, and 40, thereby balancing the temperature between the respective light-emitting laminates 20, 30, and 40 and efficiently dissipating the heat generated inside to the outside. Further, when the connection electrodes 20ce, 30ce, 40ce, and 50ce include a reflective material such as metal, the connection electrodes 20ce, 30ce, 40ce, and 50ce can reflect the light emitted from at least one or more of the light-emitting laminates 20, 30, and 40 to improve the effectiveness of the light.

[0071] Generally, during manufacturing, an array of a plurality of light-emitting chips is formed on a substrate. Thereafter, the substrate is cut along scribe lines to individualize (separate) each light-emitting chip, and the light-emitting chip may be transferred to another substrate or tape using various transfer techniques for further processing of the light-emitting chip such as in a package. In this case, when the light-emitting chip includes connection electrodes such as metal bumps or pillars protruding from the light-emitting structure to the outside, various problems may occur in subsequent processes such as the transfer step because the exposed light-emitting chip has a structure that exposes the connection electrodes to the outside. Further, when the light-emitting chip includes micro LEDs having a surface area of less than about 10,000 square μm, less than about 4,000 square μm, or less than about 2,500 square μm depending on the application, handling of the light-emitting chip may become difficult due to its small form factor.

[0072] For example, when the connection electrode has a substantially elongated shape such as a rod shape, due to the protruding structure of the connection electrode, the adsorption area of the light-emitting chip may not be sufficiently ensured, making it difficult to transport by the conventional vacuum method. Furthermore, the exposed connection electrode is directly subjected to various stresses in subsequent processes, such as when the connection electrode contacts the manufacturing apparatus, which may damage the structure of the light-emitting chip. As another example, when transferring the light-emitting chip by attaching an adhesive tape to the upper surface of the light-emitting chip (for example, the surface facing the substrate), the contact area between the light-emitting chip and the adhesive tape may be limited to the upper surface of the connection electrode. In this case, unlike when the adhesive tape is attached to the lower surface of the chip (for example, the substrate), the adhesive force between the light-emitting chip and the adhesive tape becomes weak, and there is a possibility that the light-emitting chip may be unintentionally peeled off from the adhesive tape during transfer. As another example, when transporting the light-emitting chip by the conventional pick-and-place method, the ejection pin may directly contact a part of the light-emitting chip disposed between the connection electrodes, damaging the upper structure of the light-emitting structure. In particular, the ejection pin may collide with the central part of the light-emitting chip, possibly causing physical damage to the light-emitting laminate at the topmost part of the light-emitting chip. Such an impact on the light-emitting chip by the ejection pin is shown in FIG. 1E, where the central part of the light-emitting chip 100 is recessed by the ejection pin.

[0073] According to an exemplary embodiment, the passivation layer 90 may be formed on the light-emitting stacked structure. The thickness of the portion of the passivation layer 90 overlapping with the first light-emitting stacked body 20 may be 100 μm or less. More specifically, as shown in FIG. 1A, the passivation layer 90 may be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and may cover at least the side surfaces of the light-emitting stacked structure. For example, the passivation layer 90 may also cover the upper surface of the first light-emitting stacked body 20. According to the illustrated exemplary embodiment, the passivation layer 90 may expose the side surfaces of the substrate 11, the first and second insulating layers 81, 83, and the third light-emitting stacked body 40. The passivation layer 90 may be formed to be substantially flush with the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce and may include an epoxy molding compound (EMC) formed in various colors such as black or transparent. However, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the passivation layer 90 may include polyimide (PID), and in this case, the PID may be provided as a dry film rather than a liquid type in order to enhance the flatness level when applied to the light-emitting stacked structure. In some exemplary embodiments, the passivation layer 90 may include a photosensitive material. In this way, the passivation layer 90 can protect the light-emitting structure from external impacts that may be applied in subsequent processes, and can provide a sufficient contact area to the light-emitting chip 100 to facilitate handling in subsequent transfer processes. Further, the passivation layer 90 can prevent light from leaking toward the side surfaces of the light-emitting chip 100 and can prevent or at least suppress interference of light emitted from adjacent light-emitting chips 100.

[0074] FIG. 2 is a schematic cross-sectional view of a light-emitting stacked structure according to an exemplary embodiment. Since the light-emitting stacked structure according to the illustrated exemplary embodiment is substantially the same as that included in the above-described light-emitting chip 100, redundant descriptions of substantially the same elements forming the light-emitting stacked structure are omitted to avoid redundancy.

[0075] Referring to FIG. 2, the first, second, and third lower contact electrodes 25p, 35p, and 45p according to an exemplary embodiment may be connected to a common line to which a common voltage Sc is applied. The light emission signal lines SR, SG, and SB may be connected to the first-type semiconductor layers 21, 31, and 41 of the first, second, and third light emitting laminate bodies 20, 30, and 40, respectively. In this case, the light emission signal line is connected to the first-type semiconductor layer 21 of the first light emitting laminate body 20 via the first upper contact electrode 21n. Also, in the illustrated exemplary embodiment, a common voltage Sc is applied to the first, second, and third lower contact electrodes 25p, 35p, and 45p via a common line, and a light emission signal is applied to the first-type semiconductor layers 21, 31, and 41 of the first, second, and third light emitting laminate bodies 20, 30, and 40 via the light emission signal lines, respectively. In this way, the first, second, and third light emitting laminate bodies 20, 30, and 40 can be individually controlled to emit light selectively.

[0076] Note that FIG. 2 shows a light emitting laminate body having a p-common structure, but the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the common voltage Sc may be applied to the first-type (or n-type) semiconductor layers 21, 31, and 41 of the first, second, and third light emitting laminate bodies 20, 30, and 40, and the light emission signal may be applied to the second-type (or p-type) semiconductor layers 25, 35, and 45 of the first, second, and third light emitting laminate bodies 20, 30, and 40.

[0077] The light-emitting laminate structure according to the exemplary embodiment can display lights of various colors according to the operating states of the respective light-emitting laminates 20, 30, and 40. However, a conventional light-emitting device can display various colors by a combination of a plurality of light-emitting cells that emit light of a single color. More specifically, a conventional light-emitting device generally includes light-emitting cells that emit lights of different colors, for example, red, green, and blue, which are arranged at intervals along a two-dimensional plane in order to realize a full-color display. Therefore, in a conventional light-emitting cell, a relatively large area may be occupied. However, the light-emitting laminate structure according to the exemplary embodiment can emit lights of different colors by laminating a plurality of light-emitting laminates 20, 30, and 40, thereby providing a high level of integration and enabling full-color implementation through a much smaller area than that in a conventional light-emitting device.

[0078] In addition, when manufacturing a display device by mounting the light-emitting chip 100 on another substrate, for example, due to its laminated structure, the number of chips to be mounted can be significantly reduced as compared with a conventional light-emitting device. Thus, the manufacture of a display device employing the light-emitting chip 100 can be substantially simplified, particularly when hundreds of thousands or millions of pixels are formed in one display device.

[0079] According to an exemplary embodiment, the light-emitting laminate structure may further include various additional components for improving the purity and efficiency of the light emitted therefrom. For example, in some exemplary embodiments, a wavelength-pass filter may be formed between adjacent light-emitting laminates to prevent or at least suppress light having a shorter wavelength from moving toward a light-emitting laminate that emits a longer wavelength. Further, in some exemplary embodiments, uneven portions may be formed on the light-emitting surface of at least one light-emitting laminate in order to balance the brightness of light between the light-emitting laminates. For example, since green light is generally more visible than red light or blue light, in some exemplary embodiments, uneven portions may be formed on the light-emitting laminates that emit red light or blue light to improve their light efficiency and balance the visibility between the lights emitted from the light-emitting laminates.

[0080] Hereinafter, based on exemplary embodiments, a method for forming the light-emitting chip 100 will be described with reference to the drawings.

[0081] FIGS. 3A, 4A, 5A, 6A, 7A, and 8A are plan views showing the manufacturing process of the light-emitting chip of FIG. 1A according to exemplary embodiments. FIGS. 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views taken along line A-A' of the corresponding plan views shown in FIGS. 3A, 4A, 5A, 6A, 7A, and 8A according to exemplary embodiments. FIG. 9 is a schematic cross-sectional view of the light-emitting chip of FIG. 1A according to exemplary embodiments. FIGS. 10, 11, 12, and 13 are cross-sectional views schematically showing the manufacturing process of the light-emitting chip of FIG. 1A according to exemplary embodiments.

[0082] Returning to FIG. 2, the first-type semiconductor layer 41, the third active layer 43, and the second-type semiconductor layer 45 of the third light-emitting laminate 40 may be sequentially grown on the substrate 11, for example, by a MOCVD (Metal Organic Chemical Vapor Deposition) method or an MBE (Molecular Beam Epitaxy) method. The third lower contact electrode 45p may be formed on the third p-type semiconductor layer 45, for example, by a physical vapor deposition method or a chemical vapor deposition method, and may contain a transparent conductive oxide (TCO) such as tin oxide (SnO), indium oxide (InO 2 ), zinc oxide (ZnO), indium tin oxide (ITO), indium tin zinc oxide (ITZO). When the third light-emitting laminate 40 emits blue light according to an exemplary embodiment, the substrate 11 includes Al 2 O 3 (for example, a sapphire substrate), and the third lower contact electrode 45p is tin oxide (SnO), indium oxide (InO 2) It may contain transparent conductive oxides (TCOs) such as zinc oxide (ZnO), indium tin oxide (ITO), and indium tin zinc oxide (ITZO). Similarly, for the first light-emitting laminate 20 and the second light-emitting laminate 30, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer may be sequentially grown on a temporary substrate to form them, and a lower contact electrode containing a transparent conductive oxide (TCO) may be formed on the second-type semiconductor layer by, for example, chemical vapor deposition method or the like.

[0083] According to an exemplary embodiment, the first and second light-emitting laminates 20 and 30 may be adjacent to each other with a first adhesive layer 61 interposed therebetween, and at least one of the temporary substrates of the first and second light-emitting laminates 20 and 30 may be removed by, for example, a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, in order to improve the light extraction efficiency, uneven portions may be formed on the exposed light-emitting laminate. Thereafter, the first and second light-emitting laminates 20 and 30 are made adjacent to the third light-emitting laminate 40 with a second adhesive layer 63 interposed therebetween, and the remaining one of the temporary substrates of the first and second light-emitting laminates 20 and 30 may be removed by, for example, a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, in order to improve the light extraction efficiency, uneven portions may be formed on the remaining exposed light-emitting laminate. In this way, a light-emitting laminate structure as shown in FIG. 2 may be formed.

[0084] In another exemplary embodiment, the second adhesive layer 63 may be formed on the third light-emitting laminate 40. Then, the second light-emitting laminate 30 may be adjacent to the third light-emitting laminate 40 with the second adhesive layer 63 interposed therebetween, and the temporary substrate of the second light-emitting laminate 30 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. Thereafter, the first adhesive layer 61 may be formed on the second light-emitting laminate 30. Thereby, the first light-emitting laminate 20 may be adjacent to the second light-emitting laminate 30 with the first adhesive layer 61 interposed therebetween. When the first light-emitting laminate 20 is coupled to the second light-emitting laminate 30 coupled to the third light-emitting laminate 40, the temporary substrate of the first light-emitting laminate 20 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. In some exemplary embodiments, in order to improve the light extraction efficiency, uneven portions may be formed on one or more surfaces of one light-emitting laminate before or after being coupled to another light-emitting laminate.

[0085] Referring to FIGS. 3A and 3B, various portions of each of the first, second, and third light-emitting laminates 20, 30, and 40 may be patterned through an etching process or the like to expose a part of the first-type semiconductor layer 21, the first lower contact electrode 25p, the first-type semiconductor layer 31, the second lower contact electrode 35p, the third lower contact electrode 45p, and the first-type semiconductor layer 41. According to the illustrated exemplary embodiment, the first light-emitting laminate 20 has the smallest area among the light-emitting laminates 20, 30, and 40. However, the concept of the present invention is not limited to the relative sizes of the light-emitting laminates 20, 30, and 40.

[0086] Referring to FIGS. 4A and 4B, a part of the upper surface of the first-type semiconductor layer 21 of the first light-emitting laminate 20 may be patterned, for example, through wet etching, and the first upper contact electrode 21n may be formed thereon. As described above, the first upper contact electrode 21n may be formed with a thickness of about 100 nm, for example, in the patterned region of the first-type semiconductor layer 21 to improve the ohmic contact therebetween.

[0087] Referring to FIGS. 5A and 5B, a first insulating layer 81 may be formed to cover the light-emitting laminates 20, 30, and 40, and a part of the first insulating layer 81 may be removed to form first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH. The first contact hole 20CH is defined on the first n-type contact electrode 21n so as to expose a part of the first n-type contact electrode 21n.

[0088] Also, the second contact hole 30CH may expose a part of the first-type semiconductor layer 31 of the second light-emitting laminate 30. The third contact hole 40CH may expose a part of the first-type semiconductor layer 41 of the third light-emitting laminate 40. The fourth contact hole 50CH may expose a part of the first, second, and third lower contact electrodes 25p, 35p, and 45p. The fourth contact hole 50CH may include a second sub-contact hole 50CHb that exposes a part of the first lower contact electrode 25p and a first sub-contact hole 50CHa that exposes the second and third lower contact electrodes 35p and 45p. However, in some exemplary embodiments, a single first sub-contact hole 50CH may expose each of the first, second, and third lower contact electrodes 25p, 35p, and 45p.

[0089] Referring to FIGS. 6A and 6B, the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed on the first insulating layer 81 in which the first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH are formed. Note that the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd can be formed, for example, by forming a conductive layer on substantially the entire surface of the substrate 11 and patterning the conductive layer using a photolithography process or the like.

[0090] The first pad 20pd is formed to overlap with the region where the first contact hole 20CH is formed, and the first pad 20pd can be connected to the first upper contact electrode 21n of the first light-emitting laminate 20 via the first contact hole 20CH. The second pad 30pd is formed to overlap with the region where the second contact hole 30CH is formed, and the second pad 30pd can be connected to the first-type semiconductor layer 31 of the second light-emitting laminate 30 via the second contact hole 30CH. The third pad 40pd is formed to overlap with the region where the third contact hole 40CH is formed, and the third pad 40pd can be connected to the first-type semiconductor layer 41 of the third light-emitting laminate 40 via the third contact hole 40CH. Further, the fourth pad 50pd is formed to overlap with the region where the fourth contact hole 50CH is formed, more specifically, the region where the first sub-contact hole 50CHa and the second sub-contact hole 50CHb are formed, and the fourth pad 50pd can be connected to the first, second, and third lower contact electrodes 25p, 35p, and 45p of the first, second, and third light-emitting laminates 20, 30, and 40 via the first sub-contact hole 50CHa and the second sub-contact hole 50CHb.

[0091] Referring to FIGS. 7A and 7B, the second insulating layer 83 may be formed on the first insulating layer 81. The second insulating layer 83 may include silicon oxide and / or silicon nitride. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the first insulating layer 81 and the second insulating layer 83 may include an inorganic material. Next, the second insulating layer 83 is patterned to form first, second, third, and fourth through holes 20ct, 30ct, 40ct, and 50ct therein.

[0092] The first through hole 20ct formed in the first pad 20pd exposes a part of the first pad 20pd. The second through hole 30ct formed in the second pad 30pd exposes a part of the second pad 30pd. The third through hole 40ct formed in the third pad 40pd exposes a part of the third pad 40pd. The fourth through hole 50ct formed in the fourth pad 50pd exposes a part of the fourth pad 50pd. In the illustrated exemplary embodiment, the first, second, third, and fourth through holes 20ct, 30ct, 40ct, and 50ct may be respectively defined in the regions where the first, second, third, and fourth pads 20pd, 30pd, 40pd, and 50pd are formed.

[0093] Referring to FIGS. 8A and 8B, the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp are formed on the second insulating layer 83 in which the first, second, third, and fourth through holes 20ct, 30ct, 40ct, and 50ct are formed. The first bump electrode 20bp is formed to overlap with the region where the first through hole 20ct is formed, and the first bump electrode 20bp is connected to the first pad 20pd through the first through hole 20ct. The second bump electrode 30bp may be formed to overlap with the region where the second through hole 30ct is formed, and the second bump electrode 30bp may be connected to the second pad 30pd through the second through hole 30ct. The third bump electrode 40bp is formed to overlap with the region where the third through hole 40ct is formed, and the third bump electrode 40bp may be connected to the third pad 40pd through the third through hole 40ct. Also, the fourth bump electrode 50bp is formed to overlap with the region where the fourth through hole 50ct is formed, and the fourth bump electrode 50bp is connected to the fourth pad 50pd through the fourth through hole 50ct. Note that the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp may be formed, for example, by forming and patterning a conductive layer including at least one of Ni, Ag, Au, Pt, Ti, Al, Cr, Wi, TiW, Mo, Cu, TiCu, etc. on the substrate 11.

[0094] Returning to FIGS. 1B to 1D, on the light-emitting laminate structure, first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce are formed at intervals from each other. The first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce may be electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, to transmit an external signal to each of the light-emitting laminates 20, 30, and 40. More specifically, according to the illustrated exemplary embodiment, the first connection electrode 20ce may be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n via the first pad 20pd, and may be electrically connected to the first-type semiconductor layer 21 of the first light-emitting laminate 20. Also, the second connection electrode 30ce may be connected to the second bump electrode 30bp via the second pad 30pd, and may be electrically connected to the first-type semiconductor layer 31 of the second light-emitting laminate 30. Also, the third connection electrode 40ce may be connected to the third bump electrode 40bp connected to the third pad 40pd, and may be electrically connected to the first-type semiconductor layer 41 of the third light-emitting laminate 40. Also, the fourth connection electrode 50ce may be connected to the fourth bump electrode 50bp connected to the fourth pad 50pd, and may be electrically connected to the second-type semiconductor layers 25, 35, and 45 of the light-emitting laminates 20, 30, and 40 via the first, second, and third lower contact electrodes 25p, 35p, and 45p, respectively.

[0095] The forming methods of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce are not particularly limited. For example, according to an exemplary embodiment, a seed layer may be formed as a conductive surface on the light-emitting layer structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is disposed at a desired position where the connection electrode is to be formed. According to an exemplary embodiment, the seed layer may be deposited to have a thickness of about 1000 Å without being limited thereto. Next, the seed layer may be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof, and the seed layer may be removed. In some exemplary embodiments, in order to prevent or at least suppress the oxidation of the plated metal, an additional metal may be deposited or plated on the plated metal (e.g., the connection electrode) by electroless nickel immersion gold (ENIG) or the like. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0096] According to an exemplary embodiment, when the bump electrodes 20bp, 30bp, 40bp, and 50bp are omitted from the contact portions 20C, 30C, 40C, and 50C, the pads 20pd, 30pd, 40pd, and 50pd may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. For example, after forming the through holes 20ct, 30ct, 40ct, and 50ct that partially expose the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C, a seed layer is formed as a conductive surface on the light-emitting laminate structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is disposed at a desired position where the connection electrodes are to be formed. In this case, the seed layer may overlap at least a part of each of the pads 20pd, 30pd, 40pd, and 50pd. According to an exemplary embodiment, the seed layer may be deposited to a thickness of about 1000 Å without being limited thereto, and then the seed layer may be plated with a metal such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or an alloy thereof, and the seed layer may be removed. In some exemplary embodiments, in order to prevent or at least suppress the oxidation of the plated metal, an additional metal may be deposited or plated on the plated metal (e.g., the connection electrode) by electroless nickel immersion gold (ENIG) or the like. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0097] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape that protrudes away from the substrate 11. In another exemplary embodiment, the connection electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or a plurality of different metal layers in order to reduce the stress applied thereto from the elongated shape of the connection electrodes 20ce, 30ce, 40ce, and 50ce. However, the concept of the present invention is not limited to the specific shape of the connection electrodes 20ce, 30ce, 40ce, and 50ce, and in some exemplary embodiments, the connection electrodes may have various shapes.

[0098] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light-emitting layer structure and external wiring or electrodes. Also, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on the side surface of the light-emitting layer structure. In this way, the lower surface of the connection electrode may have a width larger than that of its upper surface, providing a larger contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting layer structure, and enabling the light-emitting chip 100 to have a more stable structure that can withstand various subsequent processes together with the passivation layer 90. In this case, one side surface L facing the outside of the connection electrodes 20ce, 30ce, 40ce, and 50ce and the other side surface L' facing the center of the light-emitting chip 100 may have different lengths. For example, the difference in the lengths of the two opposing surfaces of the connection electrode may be in the range of about 3 μm to about 16 μm without being limited thereto.

[0099] And the passivation layer 90 is disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce. The passivation layer 90 may be formed to be substantially flush with the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce by a polishing process or the like. According to an exemplary embodiment, the passivation layer 90 may include, without being limited thereto, a black epoxy molding compound (EMC). For example, in some exemplary embodiments, the passivation layer 90 may include a photosensitive polyimide dry film (PID). In this way, the passivation layer 90 can protect the light-emitting structure from external impacts that may be applied in subsequent processes, and can provide a sufficient contact area with the light-emitting chip 100 to facilitate handling in subsequent transfer processes. Further, the passivation layer 90 can prevent light from leaking toward the side surface of the light-emitting chip 100, and can prevent or at least suppress interference of light emitted from adjacent light-emitting chips 100.

[0100] FIG. 10 illustrates a state in which a plurality of light-emitting chips 100 disposed on a substrate 11 are subjected to a singulation process for separating each light-emitting chip 100. Referring to FIG. 11, according to an exemplary embodiment, a laser beam Laser may be emitted between the light-emitting laminate structures to form a separation path that partially separates the light-emitting laminate structures from each other. Referring to FIG. 12, a first bonding layer 95 is attached to the substrate 11, and in a state of being attached to the first bonding layer 95, the substrate 11 may be cut or broken using various known methods in the art to singulate each of the light-emitting chips 100. For example, the substrate 11 may be cut by dicing it through a scribing line formed thereon, or may be cut by applying a mechanical force to break the substrate 11 along the separation path formed during the laser irradiation process. Note that the first bonding layer 95 may be a tape, but the concept of the present invention is not limited thereto as long as the first bonding layer 95 can stably attach the light-emitting chip 100 and peel off the light-emitting chip 100 in a subsequent process. Also, in the above description, the first bonding layer 95 has been described as being attached onto the substrate 11 after the laser irradiation step, but in some exemplary embodiments, the first bonding layer 95 may be attached onto the substrate 11 before the laser irradiation step.

[0101] FIGS. 14, 15, 16A, and 17 are cross-sectional views schematically showing a manufacturing process of a light-emitting package according to an exemplary embodiment. FIG. 16B is a schematic plan view of the light-emitting package of FIG. 16A according to an exemplary embodiment. The light-emitting chip 100 according to an exemplary embodiment may be transferred and packaged by various methods known in the art. Hereinafter, the light-emitting chip 100 will be exemplarily described as being transferred by attaching a second adhesive layer 13 onto the substrate 11 using a carrier substrate 11c, but the concept of the present invention is not limited to a specific transfer method.

[0102] Referring to FIG. 14, according to an exemplary embodiment, the fragmented light-emitting chip 100 may be transferred and disposed on the carrier substrate 11c by the intervening second adhesive layer 13 therebetween. In this case, when the light-emitting chip includes a connection electrode protruding outward from the light-emitting laminate structure, various problems may occur in subsequent processes, particularly in the transfer process, due to the uneven structure as described above. Further, when the light-emitting chip includes a micro LED, since its surface area is less than about 10,000 square μm, less than about 4,000 square μm, or less than about 2,500 square μm, depending on the application, handling of the light-emitting chip may become difficult due to its small form factor. However, by providing the light-emitting chip 100 according to an exemplary embodiment having the passivation layer 90 disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce, not only is the handling of the light-emitting chip 100 in subsequent processes such as transfer and packaging facilitated, but also the light-emitting structure can be protected from external impacts and light interference between adjacent light-emitting chips 100 can be prevented.

[0103] The carrier substrate 11c is not particularly limited as long as it can stably mount the light-emitting chip 100 thereon with the second adhesive layer 13. The second adhesive layer 13 may be a tape, but the concept of the present invention is not limited to this as long as the second adhesive layer 13 can stably attach the light-emitting chip 100 to the carrier substrate 11c and the light-emitting chip 100 can be peeled off in a subsequent process. In some exemplary embodiments, the light-emitting chip 100 of FIG. 13 may be directly transferred to the circuit board 11p without being transferred to another carrier substrate 11c. In this case, the carrier substrate 11c shown in FIG. 14 may be the substrate 11, and the second adhesive layer 13 shown in FIG. 14 may be the first adhesive layer 95 shown in FIG. 13.

[0104] The light-emitting chip 100 may be mounted on the circuit board 11p. According to an exemplary embodiment, the circuit board 11p may include an upper circuit electrode 11pa, a lower circuit electrode 11pc, and an intermediate circuit electrode 11pb disposed therebetween, which are electrically connected to each other. The upper circuit electrode 11pa may correspond to each of the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce. In some exemplary embodiments, the upper circuit electrode 11pa may be surface-treated by ENIG to facilitate electrical connection with the connection electrodes of the light-emitting chip 100 by being partially melted at a high temperature.

[0105] According to the illustrated exemplary embodiment, the light-emitting chips 100 may be spaced apart from each other on the carrier substrate 11c, at a desired pitch, preferably considering the pitch P (see FIG. 16B) of the upper circuit electrodes 11pa of the circuit board 11p, which is mounted on a final target device such as a display device.

[0106] According to an exemplary embodiment, the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce of the light-emitting chip 100 may be joined to the upper circuit electrodes 11pa of the circuit board 11p, respectively, by, for example, anisotropic conductive film (ACF) bonding. When the light-emitting chip 100 is bonded to the circuit board by ACF bonding, which can be performed at a lower temperature compared to other bonding methods, the light-emitting chip 100 can be prevented from being exposed to a high temperature during bonding. However, the concept of the present invention is not limited to a specific bonding method. For example, in some exemplary embodiments, the light-emitting chip 100 may be bonded to the circuit board 11p using anisotropic conductive paste (ACP), solder, ball grid area (BGA), or microbumps containing at least one of Cu and Sn. In this case, since the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce and the passivation layer 90 are substantially flush with each other from a polishing process or the like, the adhesion of the light-emitting chip 100 to the anisotropic conductive film is enhanced, and a more stable structure can be formed when bonded to the circuit board 11p.

[0107] Referring to FIG. 15, a molding layer 91 is formed between the light-emitting chips 100. According to an exemplary embodiment, the molding layer 91 may transmit a part of the light emitted from the light-emitting chip 100, and may also reflect, diffract and / or absorb a part of the external light, so as to prevent the external light from being reflected in a direction in which it can be visually recognized by the user by the light-emitting chip 100. Further, the molding layer 91 may cover at least a part of the light-emitting chip 100 to protect the light-emitting chip 100 from external moisture and stress. Furthermore, together with the passivation layer 90 formed on the light-emitting chip 100, the molding layer 91 provides further protection to the light-emitting package by strengthening the structure of the light-emitting package.

[0108] According to an exemplary embodiment, when the molding layer 91 covers the upper surface of the substrate 11 facing away from the circuit board 11p, the molding layer 91 may have a thickness of less than about 100 μm in order to transmit at least 50% of the light emitted from the light-emitting chip 100. In an exemplary embodiment, the molding layer 91 may include an organic polymer or an inorganic polymer. In some exemplary embodiments, the molding layer 91 may further include pillars such as silica or alumina. In some exemplary embodiments, the molding layer 91 may include the same material as the passivation layer 90. The molding layer 91 may be formed by various methods known in the art, such as a lamination method, a plating method and / or a printing method. For example, the molding layer 91 may be formed by a vacuum lamination process in which an organic polymer sheet is disposed on the light-emitting chip 100 and high temperature and pressure are applied in a vacuum in order to improve the light uniformity by providing a substantially planar upper surface of the light-emitting package.

[0109] In some exemplary embodiments, the substrate 11 may be removed from the light-emitting chip 100 before the molding layer 91 is formed thereon. When the substrate 11 is a patterned sapphire substrate, in order to improve the light efficiency, concavo-convex portions may be formed on the first-type semiconductor layer 41 of the third light-emitting laminate 40 in contact with the substrate 11. In another exemplary embodiment, as is known in the art, concavo-convex portions may be formed on the first-type semiconductor layer 41 of the third light-emitting laminate 40 by etching or patterning.

[0110] Referring to FIGS. 16A and 16B, the light-emitting chip 100 disposed on the circuit board 11p may be cut into a desired shape to form a light-emitting package 110. For example, the light-emitting package 110 shown in FIG. 16B includes four light-emitting chips 100 (2×2) disposed on the circuit board 11p. However, the concept of the present invention is not limited to the number of light-emitting chips formed in the light-emitting package 110 being a specific number. For example, in some exemplary embodiments, the light-emitting package 110 may include one or more light-emitting chips 100 formed on the circuit board 11p. Further, the concept of the present invention is not limited to a specific arrangement of one or more light-emitting chips 100 in the light-emitting package 110. For example, one or more light-emitting chips 100 in the light-emitting package 110 may be in an n×m array, where n and m are natural numbers greater than zero. According to an exemplary embodiment, the circuit board 11p may include scan lines and data lines for independently driving each of the light-emitting chips 100 included in the light-emitting package 110.

[0111] Referring to FIG. 17, the light-emitting package 110 may be mounted on a target substrate 11b of a final device such as a display device. The target substrate 11b may include target electrodes 11s respectively corresponding to the lower circuit electrodes 11pc of the light-emitting package 110. According to an exemplary embodiment, the display device may include a plurality of pixels, and each of the light-emitting chips 100 may be arranged to correspond to each pixel. More specifically, each of the light-emitting laminates of the light-emitting chip 100 according to an exemplary embodiment may correspond to each sub-pixel of one pixel. Since the light-emitting chip 100 includes the light-emitting laminates 20, 30, and 40 stacked in the vertical direction, the number of chips that need to be transferred for each sub-pixel can be significantly reduced compared to that in a conventional light-emitting device. Also, since the lengths of the opposing surfaces of the connection electrodes are different, the connection electrodes can be stably formed on the light-emitting laminate structure, and its internal structure can be strengthened. Further, the light-emitting chip 100 according to some exemplary embodiments includes a passivation layer 90 between the connection electrodes, so that the light-emitting chip 100 can be protected from external impacts.

[0112] In this specification, specific exemplary embodiments and implementations have been described, but other embodiments and modifications will be apparent from this description. Accordingly, the concept of the present invention is not limited to such embodiments, but also applies to the broader scope of the appended claims and various obvious changes and equivalents that are apparent to those skilled in the art.

Claims

1. A first LED subunit; A second LED subunit disposed on the first LED subunit; a third LED subunit disposed on the second LED subunit; a first bonding layer disposed between the first and second LED subunits; a second bonding layer disposed between the second and third LED subunits; and a first connection electrode electrically connected to and overlapping at least one of the first, second and third LED subunits, the first connection electrode having opposing first and second side surfaces, the first side surface having a first length and the second side surface having a second length; Including, A light-emitting chip, wherein a difference between a length of the first side surface and a length of the second side surface of the first connection electrode is greater than a thickness of at least one of the LED subunits.

2. A substrate on which the first LED subunit is disposed; a passivation layer at least partially surrounding the first connection electrode and exposing a side surface of the substrate; The light-emitting chip according to claim 1 , further comprising:

3. The light-emitting chip according to claim 1 , wherein the first side faces the outside of the light-emitting chip, and the second side faces the center of the light-emitting chip.

4. The light-emitting chip as claimed in claim 2 , wherein the passivation layer exposes a side surface of the first LED subunit and covers at least one side surface of the second and third LED subunits.

5. the passivation layer includes at least one of an epoxy molding compound and a polyimide film; The light-emitting chip as claimed in claim 2 , wherein the passivation layer covers an upper surface of the third LED subunit.

6. The light-emitting chip as claimed in claim 5 , wherein the passivation layer transmits light emitted from the first, second and third LED subunits.

7. The light-emitting chip as claimed in claim 2 , wherein a thickness of a part of the passivation layer overlapping the third LED subunit is less than or equal to about 100 μm.

8. A second connection electrode electrically connected to the first LED subunit; a third connection electrode electrically connected to the second LED subunit; a fourth connection electrode electrically connected to the third LED subunit; Further comprising: the first connection electrode is electrically connected to each of the first, second and third LED subunits; The light-emitting chip described in claim 1, wherein each of the first, second, third and fourth connection electrodes has an elongated shape protruding in a direction away from the substrate so that each of their upper surfaces is positioned above the upper surface of the third LED subunit.

9. The light-emitting chip according to claim 8 , wherein a lower surface of at least one of the first, second, third and fourth connection electrodes has an area larger than that of an upper surface thereof.

10. The light-emitting chip as claimed in claim 8 , wherein at least one of the first, second, third and fourth connecting electrodes overlaps a side surface of each of the first, second and third LED subunits.

11. the first connection electrode is electrically connected to the first, second, and third LED subunits via first, second, and third lower contact electrodes, respectively; The light-emitting chip according to claim 1 , wherein the first, second and third lower contact electrodes are disposed on different planes.

12. the third LED subunit includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer, and an upper contact electrode in ohmic contact with the first-type semiconductor layer; the first type semiconductor layer includes a recess; The light-emitting chip according to claim 1 , wherein the upper contact electrode is formed in the recess of the first-type semiconductor layer.

13. Further comprising a substrate; the first LED subunit includes a first LED light emitting stack; the second LED subunit includes a second LED light emitting stack; the third LED subunit includes a third LED light emitting stack; The first, second and third LED light-emitting stacks have successively smaller overlapping areas with the substrate, 10. The light-emitting chip of claim 1, wherein at least one of the light-emitting stacks includes a micro-LED having a surface area of ​​about 10,000 square microns or less.

14. The light-emitting chip as claimed in claim 1 , wherein a difference in length between the first side surface and the second side surface of the first connecting electrode is in a range of about 3 μm to about 16 μm.

15. Equipped with a light-emitting chip, The light emitting chip includes: A first LED subunit; A second LED subunit disposed on the first LED subunit; a third LED subunit disposed on the second LED subunit; A plurality of connection electrodes disposed on each of the first, second, and third LED subunits; a circuit board having a first surface facing the light emitting chip and a plurality of upper electrodes connected to the connection electrodes; a molding layer covering substantially all of the outer surface of the light emitting chip; Including the luminous package.

16. The light emitting chip further includes a passivation layer disposed between the plurality of connecting electrodes; 16. The luminescent package of claim 15, wherein the passivation layer and the molding layer comprise the same material.

17. The light emitting chip further includes a passivation layer disposed between the plurality of connecting electrodes; 16. The light emitting package of claim 15, wherein the passivation layer and the molding layer comprise different materials.

18. 16. The light emitting package of claim 15, wherein the portion of the molding layer disposed on the light emitting chip has a thickness of less than about 100 [mu]m.

19. At least one of the plurality of connection electrodes has opposing first and second side surfaces having first and second lengths, respectively; 16. The luminescent package of claim 15, wherein the difference between the first length and the second length is at least about 3 μm.

20. The light emitting package according to claim 15 , wherein at least one of the plurality of connecting electrodes overlaps a side surface of each of the first, second and third LED subunits.

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