Light emitting device and display device, manufacturing method for light emitting device

Abstract

To form a plurality of LEDs (light emitting diodes) on a substrate.SOLUTION: A light emitting device comprises: a main substrate 1; a mask 6 that is positioned in an upper direction from the main substrate, a mask 5 and open portions K1 and K2; and a semiconductor substrate 10 that has a base semiconductor 8 positioned at a position in the upper direction from the mask; and a chemical compound semiconductor portion 9 that is positioned in the upper direction from the semiconductor substrate, and includes a first light emitting portion L1, The semiconductor substrate comprises a first hole H1 that penetrates trough the main substrate in a thickness direction, and is overlapped with the first light emitting portion below the first light emitting portion.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to light emitting devices and the like. [Background technology]

[0002] For example, Patent Document 1 discloses a method for forming a plurality of LEDs (light emitting diodes) on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent: US 10,381,507 B2 Summary of the Invention

[0004] The light-emitting device according to the present disclosure comprises a semiconductor substrate having a main substrate, a mask located above the main substrate and including a mask portion and an opening, and a base semiconductor portion located above the mask, and a compound semiconductor portion located above the semiconductor substrate and having a first light-emitting portion, the semiconductor substrate including a first hole penetrating the main substrate in a thickness direction and overlapping with the first light-emitting portion below the first light-emitting portion. [Brief description of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view showing a configuration of a light-emitting device according to an embodiment of the present invention. [Diagram 2] 4 is a flowchart showing an example of a method for manufacturing a light-emitting device according to the present embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of a manufacturing apparatus for a light-emitting device according to the present embodiment. [Figure 4] FIG. 1 is a cross-sectional view showing a configuration of a display device according to an embodiment of the present invention. [Diagram 5] 2 is a cross-sectional view of the light-emitting device according to the first embodiment taken along the X direction. FIG. [Figure 6]4 is a cross-sectional view of the light-emitting device according to the first embodiment taken along the Y direction. [Figure 7] FIG. 2 is a plan view of the light-emitting device according to the first embodiment. [Figure 8] 4 is a plan view showing another configuration of the light emitting device according to the first embodiment. FIG. [Figure 9] 4 is a plan view showing another configuration of the light emitting device according to the first embodiment. FIG. [Figure 10] 4 is a flowchart showing an example of a method for manufacturing the light emitting device according to the first embodiment. [Figure 11] 1A to 1C are cross-sectional views showing an example of a method for manufacturing the light-emitting device according to Example 1. [Figure 12] 6 is a flowchart showing another example of the method for manufacturing the light emitting device according to the first embodiment. [Figure 13] 13A to 13C are cross-sectional views illustrating a method for manufacturing the light-emitting device of FIG. [Figure 14] 4 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion. FIG. [Figure 15] 2 is a schematic cross-sectional view showing the configuration of a base semiconductor portion and a compound semiconductor portion. FIG. [Figure 16] 1 is a cross-sectional view showing a configuration of a display device according to a first embodiment. [Figure 17] 1 is a cross-sectional view showing a configuration of a display device according to a first embodiment. [Figure 18] 1 is a block diagram showing a configuration of a display device according to a first embodiment. [Figure 19] FIG. 2 is a cross-sectional view showing an example of a driving substrate. [Figure 20] 10 is a cross-sectional view of a light-emitting device according to a second embodiment taken along the X direction. [Figure 21] 11 is a cross-sectional view of the light-emitting device according to the second embodiment taken along the Y direction. FIG. [Figure 22] FIG. 11 is a plan view of a light-emitting device according to a second embodiment. [Figure 23] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Figure 24] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Diagram 25] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Figure 26] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Figure 27] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Figure 28] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Figure 29] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Diagram 30] 10 is a cross-sectional view showing another configuration of the light-emitting device according to the second embodiment. [Diagram 31] 11 is a cross-sectional view of a light-emitting device according to a third embodiment taken along the X direction. FIG. [Diagram 32] 11 is a cross-sectional view of the light-emitting device according to Example 3 taken along the Y direction. [Diagram 33] FIG. 11 is a plan view of a light-emitting device according to a third embodiment. [Diagram 34] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the third embodiment. FIG. [Diagram 35] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the third embodiment. FIG. [Diagram 36] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the third embodiment. FIG. [Figure 37] FIG. 11 is a plan view showing another configuration of the light emitting device according to the third embodiment. [Figure 38] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the fourth embodiment. [Figure 39] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the fourth embodiment. [Diagram 40] 13 is a flowchart showing a method for manufacturing a light emitting device according to Example 5. [Diagram 41] FIG. 11 is a cross-sectional view showing the configuration of a light-emitting device according to Example 5. [Diagram 42] 13 is a flowchart showing another method for manufacturing the light emitting device according to the fifth embodiment. [Diagram 43]11 is a cross-sectional view showing another configuration of the light-emitting device according to the fifth embodiment. [Diagram 44] 11 is a cross-sectional view showing another configuration of the light-emitting device according to the fifth embodiment. [Diagram 45] FIG. 13 is a schematic plan view showing a display device according to a seventh embodiment. [Figure 46] FIG. 13 is a schematic diagram showing a configuration of an electronic device according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Light Emitting Devices] FIG. 1 is a cross-sectional view showing the configuration of a light-emitting device according to this embodiment. As shown in FIG. 1, the light-emitting device 30 according to this embodiment includes a main substrate 1, a mask 6 located above the main substrate 1 and including a mask portion 5 and an opening K1, a semiconductor substrate 10 including a base semiconductor portion 8 located above the mask 6, and a compound semiconductor portion 9 located above the semiconductor substrate 10 and having a first light-emitting portion L1. The semiconductor substrate 10 may include a main substrate 1 (e.g., a free-standing substrate of a bulk crystal) and a semiconductor portion (e.g., a semiconductor layer), and the main substrate 1 may be a semiconductor or a non-semiconductor. In the light-emitting device 30, the direction from the main substrate 1 (e.g., a free-standing substrate of a bulk crystal) to the base semiconductor portion 8 is the upward direction (therefore, it may be different from the vertical upward direction or the upward direction in the drawing). The mask 6 may be a mask pattern including a mask portion 5 and an opening K1. The opening K1 is a region where the mask portion 5 does not exist, and the opening K1 may not be surrounded by the mask portion 5.

[0007] The semiconductor substrate 10 includes a first hole H1 that penetrates the main substrate 1 in the thickness direction and overlaps with the first light emitting portion L1 below the first light emitting portion L1. In other words, the first hole H1 overlaps with the first light emitting portion L1 in a plan view (visualized in the normal direction of the main substrate 1). Two components overlap in a plan view means that at least a part of one component overlaps with the other component in a visualized view (including a perspective visualized view) in the normal direction of the main substrate 1. The two components may overlap while being separated from each other (for example, in the vertical direction). A first electrode E1 may be provided above the compound semiconductor portion 9. The first hole H1 has an opening KR that becomes a light emission surface on the back surface 1U (lower surface) of the main substrate 1.

[0008] In the light-emitting device 30, even if the main substrate 1 and the base semiconductor section 8 have different lattice constants, threading dislocations (defects) in the base semiconductor section 8 and the compound semiconductor section 9 are reduced on the mask section 5, thereby improving the light-emitting efficiency (for example, the ratio of the amount of light to the amount of charge injected from the first electrode E1) of the first light-emitting section L1 included in the compound semiconductor section 9. Threading dislocations are dislocations (defects) that extend from the base semiconductor section 8 to the compound semiconductor section 9, and they impede charge transfer and cause heat generation.

[0009] The light emitting device 30 has rigidity because it includes the main substrate 1. Furthermore, by providing the first wavelength conversion layer J1 in the first hole H1, light having a longer wavelength (for example, in the visible light range) than the light generated in the first light emitting portion L1 can be emitted from the opening KR.

[0010] The base semiconductor portion 8 and the compound semiconductor portion 9 include, for example, a nitride semiconductor. The nitride semiconductor can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor that includes gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be a doped type (for example, an n-type including a donor) or a non-doped type.

[0011] The base semiconductor portion 8 including a nitride semiconductor can be formed by an ELO (Epitaxial Lateral Overgrowth) method, but other methods may be used as long as they can achieve low defects. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of the base semiconductor portion 8 is used as the main substrate 1, a nitride semiconductor is used for the base portion 4, an inorganic compound film is used for the mask portion 5, and the base portion 4 is exposed in the opening K1, so that the base semiconductor portion 8 can be grown in the lateral direction (Y direction) on the mask portion 5.

[0012] Hereinafter, the main substrate 1 and the base portion 4 may be collectively referred to as the base substrate, and the main substrate 1, the base portion 4, and the mask 6 may be collectively referred to as the template substrate 7. In addition, the base semiconductor portion formed by the ELO method may be referred to as the ELO semiconductor layer.

[0013] When the base semiconductor portion 8 is formed using the ELO method, a template substrate 7 including a main substrate 1 and a mask 6 on the main substrate 1 may be used. The template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K1. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the base semiconductor portion 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0014] [Manufacture of light-emitting devices] Fig. 2 is a flow chart showing an example of a method for manufacturing a light emitting device according to this embodiment. In the method for manufacturing a light emitting device shown in Fig. 2, after a step of preparing a template substrate (substrate for ELO growth) 7, a step of forming a base semiconductor portion 8 using the ELO method is performed to obtain a semiconductor substrate 10. Next, a step of forming a compound semiconductor portion 9 is performed, and then a step of etching the main substrate 1 from its back surface 1U to form a first hole H1 is performed.

[0015] Fig. 3 is a block diagram showing an example of a manufacturing apparatus for a light-emitting device according to the present embodiment. The manufacturing apparatus 70 for a light-emitting device in Fig. 3 includes a semiconductor forming section 72 for forming a base semiconductor section 8 and a compound semiconductor section 9 on a template substrate 7, a substrate processing section 73 for etching the main substrate 1 from its rear surface 1U, and a control section 74 for controlling the semiconductor forming section 72 and the substrate processing section 73.

[0016] The semiconductor forming unit 72 may include an MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor forming unit 72 and the substrate processing unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above-mentioned program and a recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0017] [Display Device] Fig. 4 is a cross-sectional view showing the configuration of a display device according to this embodiment. As shown in Fig. 4, the display device 50 includes a light-emitting device 30 and a driving substrate TK disposed on the opposite side of the main substrate 1 in the light-emitting device 30 and electrically connected to the first electrode E1. The light emission intensity of the first light-emitting portion L1 is controlled by a pixel circuit included in the driving substrate TK (described later). The driving substrate TK may be configured such that a pixel circuit including a plurality of transistors is formed on a glass substrate or a resin substrate, or may be configured such that a pixel circuit including a plurality of transistors is formed on a silicon substrate. The pixel circuit may also include a CMOS (Complementary Metal Oxide Semiconductor) circuit.

[0018] Example 1 (Overall composition) FIG. 5 is a cross-sectional view of the light emitting device according to the first embodiment taken along the X direction. FIG. 6 is a cross-sectional view of the light emitting device according to the first embodiment taken along the Y direction. FIG. 7 is a plan view of the light emitting device according to the first embodiment. As shown in FIGS. 5, 6, and 7, the light emitting device 30 according to the first embodiment includes a semiconductor substrate 10, a compound semiconductor portion 9 located on the semiconductor substrate 10, and first and second electrodes E1 and E2. The semiconductor substrate 10 includes a main substrate 1, an underlayer portion 4 located on the main substrate 1, a mask 6 located on the underlayer portion 4 and including a mask portion 5 and openings K1 and K2, and a base semiconductor portion 8 located on the mask 6. The compound semiconductor portion 9 includes a first light emitting portion L1. The first electrode E1 is located above the compound semiconductor portion 9, and the second electrode E2 is located above the base semiconductor portion 8. The base semiconductor portion 8 and the compound semiconductor portion 9 include nitride semiconductors (e.g., GaN-based semiconductors). The X direction is the <11-20> direction (a-axis direction) of the base semiconductor portion 8, the Y direction is the <1-100> direction (m-axis direction) of the base semiconductor portion 8, and the Z direction is the <11-20> direction (a-axis direction) of the base semiconductor portion 8. <0001> In other words, the X direction is the <11-20> direction in the crystal structure of a nitride semiconductor (for example, a GaN-based semiconductor), the Y direction is the <1-100> direction in the crystal structure of a nitride semiconductor (for example, a GaN-based semiconductor), and the Z direction is the <1-100> direction in the crystal structure of a nitride semiconductor (for example, a GaN-based semiconductor). <0001> The direction is the direction from the mask 6 to the substrate 1. The structure below the mask 6 (for example, the main substrate 1 and the base portion 4) may be referred to as the base substrate UK. The base substrate and mask 6 may be collectively referred to as the template substrate 7. The base portion 4 may be an underlayer. The mask 6 may be a mask layer. The base semiconductor portion 8 may be a base semiconductor layer. The compound semiconductor portion 9 may be a compound semiconductor layer or a device layer.

[0019] The main substrate 1 is a heterogeneous substrate having a different lattice constant from the base semiconductor portion 8. The main substrate 1 may be a light-shielding substrate, for example, a silicon substrate. The main substrate 1 includes a first hole H1 that penetrates between the lower surface and the upper surface and overlaps with the first light-emitting portion L1 in a plan view. The first hole H1 may have a tapered shape that tapers toward the base semiconductor portion 8.

[0020] A first wavelength conversion layer J1 that emits light having a wavelength longer than the received light wavelength is provided in the first hole H1. The first wavelength conversion layer J1 converts the light (e.g., ultraviolet light) received from the first light emitting portion L1 into visible light, for example, by photoluminescence. The converted visible light is emitted to the outside through the first hole H1. The first wavelength conversion layer J1 may contain at least one of a fluorescent material and a phosphorescent material. The first hole H1 has an opening KR that serves as an emitting surface for visible light on the back surface (lower surface) 1U of the main substrate 1. The shape of the opening KR is a rectangle (see FIG. 7), a rhombus, a circle, an ellipse, etc., but is not limited thereto. In the first embodiment, at least a part of the bottom of the first hole H1 is included in the base portion 4. As shown in FIG. 5, the entire bottom of the first hole H1 may be located within the base portion 4.

[0021] The base semiconductor portion 8 includes a first portion HD located on the opening K1 and a second portion SD (low defect portion) located on the mask portion 5 and having a lower threading dislocation density than the first portion HD. The second portion SD overlaps with the first light emitting portion L1 in a plan view. The threading dislocation density of the second portion SD is, for example, 5×10 6 / cm 2 This is as follows. As a result, the light emission efficiency of the first light emitting portion L1 can be increased. The threading dislocations extend in the thickness direction of the base semiconductor portion 8 and reach the surface layer thereof.

[0022] In the first embodiment, the first and second electrodes E1 and E2 are aligned in the Y direction. The first electrode E1 is, for example, an anode (p-electrode), and the second electrode E2 is, for example, a cathode (n-electrode). The first electrode E1 overlaps the first light-emitting portion L1 in a plan view. This shortens the current path between the first electrode E1 and the first light-emitting portion L1. The first and second electrodes E1 and E2 are light-reflective. This reflects light from the first light-emitting portion L1 toward the first electrode E1 toward the main substrate 1, thereby improving the light utilization efficiency.

[0023] The light emitting device 30 includes a first pad P1 connected to the first electrode E1 and a second pad P2 connected to the second electrode E2. In a plan view, at least a part of the second pad P2 does not overlap with the first hole H1. Therefore, when the driving substrate TK and the light emitting device 30 are joined, the influence of the pressure on the second pad P2 on the compound semiconductor portion 9 and the base semiconductor portion 8 (for example, the occurrence of defects such as cracks inside the base semiconductor portion 8) is reduced. In addition, since the positions of the upper surfaces of the first and second pads P1 and P2 are aligned, mounting on the driving substrate TK (see FIG. 4) is facilitated. The first and second electrodes E1 and E2 do not contact the base semiconductor portion 8, and an insulating film DF can be located between the first and second electrodes E1 and E2 and the base semiconductor portion 8. The insulating film DF may be transparent.

[0024] In FIG. 6, the second electrode E2 is in contact with the base semiconductor portion 8. If the second electrode E2 is a cathode, the base semiconductor portion 8 can be made of an n-type semiconductor. The second electrode E2 may have a recess EH, and an insulating layer DL may be provided in the recess EH. By providing the insulating layer DL in the recess EH, the upper surface of the second pad P2 can be flattened. A light-shielding layer QY may be provided in the gap between two pairs of the first electrode E1 and the second electrode E2 adjacent to each other in the Y direction. A part of the light-shielding layer QY may be located within the base semiconductor portion 8. The light-shielding layer QY may be light-absorbing or may have a lower refractive index than the base semiconductor portion 8.

[0025] The compound semiconductor section 9 has a second light-emitting section L2 and a third light-emitting section L3, and the main substrate 1 includes a second hole H2 which is a through hole in the thickness direction (Z direction) and overlaps with the second light-emitting section L2 in a planar view, and a third hole H3 which is a through hole in the thickness direction and overlaps with the third light-emitting section L3 in a planar view.

[0026] The first to third light emitting sections L1 to L3 are aligned in the X direction, and the first to third holes H1 to H3 are also aligned in the X direction. The first to third light emitting sections L1 to L3 may each have an emission peak wavelength in a wavelength range (visible light range) of 430 to 640 [nm]. The light emitting device 30 includes a third electrode E3 and a fourth electrode E4, and the third electrode E3 overlaps the second light emitting section L2 in a plan view, and the first and third electrodes E1 and E3 are aligned in the X direction. The third and fourth electrodes E3 and E4 are aligned in the Y direction, and the second and fourth electrodes E2 and E4 are aligned in the X direction.

[0027] The light emitting device 30 includes a first partition portion QF located in a gap between the first and second light emitting portions L1 and L2 in a plan view. The first partition portion QF has a light blocking property (e.g., a property of absorbing light having an emission wavelength of the first and second light emitting portions L1 and L2) and overlaps with the opening portion K1 of the mask 6 in a plan view. The first partition portion (light blocking layer) QF may have a lower refractive index than the base semiconductor portion 8.

[0028] The light emitting device 30 includes a second partition portion QS located in the gap between the second and third light emitting portions L2 and L3 in a planar view. The second partition portion QS has a light blocking property (e.g., a property of absorbing light of the emission wavelength of the second and third light emitting portions L2 and L3) and overlaps with the center of the mask portion 5 in a planar view. The first and second partition portions QF and QS are shaped such that the Y direction is the longitudinal direction. The second partition portion (light blocking layer) QS may have a lower refractive index than the base semiconductor portion 8.

[0029] The base semiconductor portion 8 includes a first region 8F and a second region 8S that are separated from each other. The first region 8F overlaps with the opening K1 in a plan view, and the second region 8S overlaps with the opening K2 in a plan view. The first and second regions 8F and 8S each have an elongated shape, and a second partition portion QS is disposed between the first and second regions 8F and 8S.

[0030] The first and second partition portions QF and QS have a function of reducing the crosstalk phenomenon in which light generated in the light-emitting portion L1 enters a hole other than the hole H1 (e.g., hole H2) or enters the active layer of another light-emitting portion (e.g., light-emitting portion L2). From this point of view, the first and second partition portions QF and QS may be films with low light transmittance (not only light-absorbing films but also light-reflective films may be used), and specifically may be metal films such as Al, Ag, Cu, Cr, Au, etc., or may be semiconductor films, dielectric films, resin films (e.g., light-absorbing black photoresist), etc.

[0031] FIG. 8 is a plan view showing another configuration of the light emitting device according to the first embodiment. In FIG. 7, the first light emitting units L1 are arranged in a straight line in the Y direction, but the present invention is not limited thereto. As shown in FIG. 8, the first light emitting units L1 may be arranged in a staggered manner in the Y direction. The first light emitting units L1 may emit light of the same color. In FIG. 8, the openings K1 and K3 are arranged in a staggered manner in the Y direction. FIG. 9 is a plan view showing another configuration of the light emitting device according to the first embodiment. In FIG. 7, the first to third light emitting units L1 to L3 are arranged in the X direction (the <11-20> direction of the base semiconductor unit 8), but the present invention is not limited thereto. As shown in FIG. 9, the first to third light emitting units L1 to L3 may be arranged in the Y direction (the <1-100> direction of the base semiconductor unit 8). A third partition (light shielding layer) QT may be provided in the gap between the first light emitting unit L1 and the second light emitting unit L2 arranged in the Y direction, and in the gap between the second light emitting unit L2 and the third light emitting unit L3. The third partition portion QT may be light absorbing and may have a lower refractive index than the base semiconductor portion 8.

[0032] (Manufacturing method) FIG. 10 is a flowchart showing an example of a method for manufacturing a light-emitting device according to Example 1. FIG. 11 is a cross-sectional view showing an example of a method for manufacturing a light-emitting device according to Example 1. In the method for manufacturing a light-emitting device shown in FIG. 10 and FIG. 11, after a step of preparing a template substrate 7, a step of forming a base semiconductor portion 8 using an ELO method is performed to obtain a semiconductor substrate 10. Next, a step of forming a compound semiconductor portion 9 is performed, followed by a step of forming first and second electrodes E1 and E2, followed by a step of forming first and second pads P1 and P2. Then, a step of etching the semiconductor substrate 10 from the rear surface 1U of the main substrate 1 to form a first hole H1 penetrating the main substrate 1 in the semiconductor substrate 10 is performed. Then, a step of forming a first wavelength conversion layer J1 in the first hole H1 is performed. Note that when a through hole such as the first hole H1 is formed in the main substrate 1, it can be formed by a method such as wet etching or dry etching. More specifically, for example, the through hole may be formed by the Bosch method. Also, the through holes such as the second hole H2 and the third hole H3 can be formed by the above method.

[0033] FIG. 12 is a flow chart showing another example of the method for manufacturing the light emitting device according to the first embodiment. FIG. 13 is a cross-sectional view showing the method for manufacturing the light emitting device of FIG. 12. As shown in FIG. 12 and FIG. 13, after the step of forming the first and second pads P1 and P2, the step of bonding the driving substrate TK may be performed, and then the main substrate 1 may be etched. For example, when a silicon substrate (generally having a thickness of about 300 μm to 2.0 mm) is used as the main substrate 1, it is not easy to form a through hole in a thick silicon substrate. Therefore, after bonding the driving substrate TK to the opposite side of the silicon substrate, the silicon substrate (main substrate 1) may be thinned (for example, to a thickness of 300 μm or less) by a method such as wet etching, dry etching, polishing, or CMP (Chemical Mechanical Polishing), and then a through hole having an opening KR may be formed.

[0034] (Main board) A heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor can be used as the main substrate 1. Examples of heterogeneous substrates include single crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrate, silicon carbide (SiC) substrate, etc. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation may be used as long as the ELO-based semiconductor portion 8 can be grown by the ELO method.

[0035] (Base part) As the base portion 4, a buffer portion 2 and a seed portion 3 can be provided in this order from the main substrate 1 side. The buffer portion 2 may be a buffer layer. The seed portion 3 may be a seed layer. The buffer portion 2 has a function of, for example, reducing the main substrate 1 and the seed portion 3 from directly contacting each other and melting each other. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, the two (the main substrate and the seed portion) melt together, so that melting is reduced by providing the buffer portion 2 including at least one of an AlN layer and a SiC (silicon carbide) layer. The AlN layer, which is an example of the buffer portion 2, can be formed to a thickness of about 10 nm to about 5 μm using, for example, an MOCVD apparatus. The buffer portion 2 may have at least one of the effects of increasing the crystallinity of the seed portion 3 and alleviating the internal stress of the base semiconductor portion 8 (alleviating the warpage of the light-emitting device 30). When a main substrate 1 that does not melt with the seed portion 3 is used, it is also possible to configure without providing the buffer portion 2 (i.e., to configure the base portion 4 with the seed portion). 5, the base portion 4 is not limited to a configuration in which it overlaps with the entire mask portion 5 in a plan view. Since it is sufficient that the base portion 4 is exposed from the openings K1 and K2 of the mask 6, the base portion 4 may be formed locally (for example, in a slit shape extending in the Y direction) so as to overlap with the openings K1 and K2 in a plan view (described later).

[0036] At least one of the buffer portion 2 (e.g., aluminum nitride or silicon carbide) and the seed portion 3 (e.g., GaN-based semiconductor) can be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). The use of a sputtering device has the advantages of low-temperature deposition and large-area deposition, as well as cost reduction.

[0037] (mask) The openings K1 and K2 of the mask 6 function as growth initiation holes that expose the seed portion 3 and start the growth of the base semiconductor portion 8, and the mask portion 5 of the mask 6 functions as a selective growth mask that causes the base semiconductor portion 8 to grow laterally. The openings K1 and K2 are portions where there is no mask portion 5, and the openings K1 and K2 do not necessarily have to be surrounded by the mask portion 5.

[0038] The mask 6 may be, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0039] For example, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the underlayer 4 by using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned by using a photolithography method to form a resist having a plurality of stripe-shaped openings. After that, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including K1 and K2), and the resist is removed by organic cleaning to form the mask 6. As another example, a silicon nitride film may be formed by using a sputtering device or a PECVD (Plasma Enhanced Chemical Vapor Deposition) device. The silicon nitride film can withstand the film formation temperature of about 1000° C. of the base semiconductor portion 8 even if it is thinner than the silicon oxide film. The thickness of the silicon nitride film can be about 20 nm to 4 μm.

[0040] The openings K1 and K2 have an elongated shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the ELO base semiconductor portion 8. The width of the openings K1 and K2 is about 0.1 μm to 20 μm. The smaller the width of each opening, the smaller the number of threading dislocations propagating from each opening to the ELO base semiconductor portion 8. Also, the second portion LD can be made larger.

[0041] A small amount of silicon oxide film may decompose and evaporate during the formation of the ELO-based semiconductor portion 8 and may be incorporated into the ELO-based semiconductor portion 8. However, silicon nitride film and silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0042] Therefore, the mask 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminate film in which a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4, or may be a laminate film in which a silicon nitride film and a silicon oxide film are formed in this order on the base portion 4, or may be a laminate film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the base portion.

[0043] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then introducing the mask into the film formation device again to form a film of the same type. A good quality mask 6 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method again.

[0044] (Specific example of template substrate) The main substrate 1 is a silicon substrate having a (111) surface, and the buffer portion 2 of the base portion 4 is an AlN layer (about 30 nm to 300 nm, for example, 150 nm). 0.6 Ga 0.4 A graded layer was formed in which an N layer (eg, 300 nm) and a GaN layer (eg, 1 to 2 μm) as a second layer were formed in this order.

[0045] The mask 6 is a silicon oxide film (SiO 2 A laminated body in which a silicon oxide film (SiN) and a silicon nitride film (SiN) were formed in this order was used. The thickness of the silicon oxide film was, for example, 0.3 μm, and the thickness of the silicon nitride film was, for example, 70 nm. The silicon oxide film and the silicon nitride film were each formed by a plasma chemical vapor deposition (CVD) method.

[0046] (Base semiconductor part) In Example 1, the base semiconductor portion 8 was a GaN layer, and an MOCVD apparatus was used to perform ELO deposition of gallium nitride (GaN) on the above-mentioned template substrate 7. An example of the ELO deposition conditions was: substrate temperature: 1120° C., growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH 3 : 15 slm, V / III=6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material) can be adopted.

[0047] In this case, the first and second regions 8F and 8S (base semiconductor portion 8) are selectively grown (vertical growth) on the seed portion 3 (the GaN layer, which is the second layer) exposed in the openings K1 and K2, and then grow laterally on the mask portion 5. Then, the lateral growth of the first and second regions 8F and 8S (base semiconductor portion 8) growing laterally from both sides on the mask portion 5 is stopped before they meet.

[0048] The width (size in the X direction) of the mask portion 5 was 50 μm, the width (size in the X direction) of the openings K1 and K2 was 5 μm, the lateral width (size in the X direction) of the ELO base semiconductor portion 8 was 53 μm, the width (size in the X direction) of the second partial LD ​​was 24 μm, and the layer thickness of the ELO base semiconductor portion 8 was 5 μm. The aspect ratio of the ELO base semiconductor portion 8 was 53 μm / 5 μm=10.6, which is an extremely high aspect ratio. The width of the mask portion 5 can be set according to the specifications of the compound semiconductor portion 9, etc. (for example, about 10 μm to 200 μm).

[0049] In the formation of the ELO base semiconductor portion 8 in Example 1, the lateral film formation rate is increased. The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the openings K1 and K2, and then a laterally grown layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0050] FIG. 14 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion (ELO semiconductor layer). As shown in FIG. 14, it is preferable to form an initial growth layer SL on a seed portion 3, and then grow the base semiconductor portions 8A and 8B laterally from the initial growth layer SL. The initial growth layer SL serves as the starting point for the lateral growth of the base semiconductor portions 8A and 8B. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the base semiconductor portions 8A and 8B in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0051] Here, it is preferable to stop the deposition of the initial growth layer SL just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions are switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, the lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that the consumption of material in the thickness direction growth of the base semiconductor portion 8 is reduced, and the base semiconductor portions 8A and 8B can be grown laterally at high speed. The initial growth layer SL can be formed to a thickness of, for example, 0.1 μm or more and 4.0 μm or less.

[0052] (Compound semiconductor part and electrodes) FIG. 15 is a schematic cross-sectional view showing the configuration of the base semiconductor section and the compound semiconductor section. In the first embodiment, a compound semiconductor section 9 constituting an LED (light emitting diode) is formed on a base semiconductor section 8. The base semiconductor section 8 is, for example, an n-type doped with silicon or the like. The compound semiconductor section 9 includes, in order from the bottom side, an active layer 34, an electron blocking layer 35, and a p-type semiconductor layer 36. The active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer. The first light emitting section L1 is included in the active layer 34. The electron blocking layer 35 is, for example, an AlGaN layer. The p-type semiconductor layer 36 is, for example, a p-type GaN layer. The first electrode E1, which is an anode, is disposed so as to be in contact with the p-type semiconductor layer 36, and the second electrode E2, which is a cathode, is disposed so as to be in contact with the base semiconductor section 8. The first electrode E1, the base semiconductor portion 8, the active layer 34, the electron blocking layer 35, the p-type semiconductor layer 36, and the second electrode E2 form a light emitting element ED (a so-called micro LED). An n-type semiconductor layer may be provided between the base semiconductor portion 8 and the active layer 34.

[0053] The first electrode E1 and the second electrode E2 may have a single-layer structure or a multi-layer structure containing at least one of Al, Ag, Cr, Pd, Pt, Au, Ni, Ti, V, W, Cu, Zn, Sn, and In, or may contain an alloy layer. When the emission wavelength of the compound semiconductor portion 9 is shorter than 420 nm (when the emission spectrum contains emission with a wavelength shorter than 420 nm), the light reflectance can be improved by making at least one of the first and second electrodes E1 and E2 contain Ag. At least one of the first and second electrodes E1 and E2 may have a laminated structure of a transparent conductive film (such as ITO (Indium Tin Oxide)) on the compound semiconductor portion 9 and a light-reflective metal film (such as Ag, Al, Ti).

[0054] The protective layer DF has a function of electrically isolating the first and second electrodes E1 and E2. The protective layer DF may have an effect of treating a side surface caused by removing a part of the compound semiconductor portion 9 by etching or the like, or a damaged layer formed on the side surface.

[0055] The base semiconductor portion 8 (ELO semiconductor layer) and the compound semiconductor portion 9 can be successively formed in the same film formation apparatus (for example, an MOCVD apparatus), or the substrate on which the base semiconductor portion 8 has been formed can be temporarily removed from the film formation apparatus, and the compound semiconductor portion 9 can be formed in a different apparatus. In this case, the compound semiconductor portion 9 may be formed after forming an n-type GaN layer (for example, with a thickness of about 0.1 μm to about 3 μm) on the base semiconductor portion 8 to serve as a buffer during regrowth.

[0056] (wavelength conversion layer) The first to third wavelength conversion layers J1 to J3 can be made of a material containing at least one of a fluorescent material and a phosphorescent material. For example, by using a material that converts ultraviolet light into blue light as the first wavelength conversion layer J1, a material that converts ultraviolet light into green light as the second wavelength conversion layer J2, and a material that converts ultraviolet light into red light as the third wavelength conversion layer J3, red light is emitted from the opening (light-emitting surface) KR of the first hole H1, green light is emitted from the opening (light-emitting surface) KG of the second hole H2, and blue light is emitted from the opening (light-emitting surface) KB of the third hole H3. The first to third wavelength conversion layers J1 to J3 can be formed by photolithography, inkjet printing, or the like.

[0057] For example, the first hole H1 formed in the semiconductor substrate 10 functions as a container that holds the first wavelength conversion layer J1 (including at least one of a fluorescent material and a phosphorescent material) in the first hole H1. Light from the active layer 34 is converted to a desired wavelength by the first wavelength conversion layer J1 in the first hole H1. The minimum film thickness of the first wavelength conversion layer J1 is determined by the characteristics (e.g., particle shape, size, conversion efficiency) of the fluorescent material and phosphorescent material used in the first wavelength conversion layer J1. The main substrate 1 can be polished and thinned after the base semiconductor portion 8 and the compound semiconductor portion 9 are formed, but the final thickness of the main substrate 1 is preferably thicker than the minimum film thickness of the first wavelength conversion layer J1. The same applies to the second and third holes H2 and H3 and the second and third wavelength conversion layers J2 and J3.

[0058] (Display device) 16 and 17 are cross-sectional views showing a configuration of a display device according to a first embodiment. FIG. 18 is a block diagram showing a configuration of a display device according to a first embodiment. As shown in FIGS. 16 to 18, a display device 50 includes a light-emitting device 30 and a drive substrate TK disposed on the opposite side of the main substrate 1 in the light-emitting device 30 and electrically connected to the first and second pads P1 and P2. The drive substrate TK includes a high-potential power source PH, a low-potential power source PL, a plurality of pixel circuits XC, first and second driver circuits D1 and D2, and a control circuit DC. The pixel circuit XC includes, for example, a conductive pad PK, a write transistor WT, a drive transistor DT, and a capacitance (capacitor) CP, and the light emission intensity of the first light-emitting unit L1 (the current value of the light-emitting element ED) is controlled by the drive transistor DT.

[0059] When the light-emitting device 30 is mounted on the drive substrate TK, the high-potential power supply PH of the drive substrate TK is connected to the conductive pad PK via the channel of the drive transistor DT, the conductive pad PK is connected to the first electrode E1 (anode) via the first pad P1, and the low-potential power supply PL of the drive substrate TK is connected to the second electrode E2 (cathode) via the second pad P2.

[0060] In the pixel circuit XC, during a period when the scanning line GL is selected by the first driver D1 (scan driver), a display voltage (a voltage corresponding to the grayscale data DT) from the data line YL connected to the second driver D2 (data driver) is written to the capacitance CP via the write transistor WT, and a current corresponding to this display voltage flows through the channel of the drive transistor DT, the conductive pad PK, the first pad P1, the first electrode E1, and the active layer 34 to the second electrode E2, causing the first light-emitting portion L1 of the active layer 34 to emit light with an intensity corresponding to the grayscale data DT (video data input to the control circuit DC). The light (e.g., ultraviolet light) from the first light-emitting portion L1 is converted into visible light by the first wavelength conversion layer J1, and as a result, visible light (e.g., red light) with an intensity corresponding to the grayscale data DT can be obtained. The same is true for the second and third light-emitting portions L2 and L3.

[0061] The driving substrate TK may include a silicon substrate, and the pixel circuit XC may be formed on the silicon substrate. In this case, the channel of each transistor (DT, WT, etc.) may include silicon (e.g., amorphous silicon, polysilicon).

[0062] Fig. 19 is a cross-sectional view showing an example of a drive substrate. As shown in Fig. 19, the pixel circuit XC of the drive substrate TK may include a CMOS circuit 27 including an n-channel MOS transistor 25 and a p-channel MOS transistor 26 formed on a substrate 24.

[0063] The main substrate 1 of the light emitting device 30 and the substrate 24 of the driving substrate TK may be made of the same material. For example, when a silicon substrate is used for each of the light emitting device 30 and the driving substrate TK (i.e., the thermal expansion coefficients of the main substrate 1 and the substrate 24 of the driving substrate TK are the same), the bonding accuracy of the light emitting device 30 to the driving substrate TK is improved, and the yield is improved. In addition, it is also possible to bond the light emitting device 30 with a large light emitting surface (display surface) to the driving substrate TK.

[0064] In the display device 50 of the first embodiment, the opening KR of the first hole H1 can be the light-emitting surface of a red subpixel, the opening KG of the second hole H2 can be the light-emitting surface of a green subpixel, and the opening KB of the third hole H3 can be the light-emitting surface of a blue subpixel, and these three subpixels form one pixel. As an example, if the width of the first region 8F (base semiconductor portion 8) is about 53 μm, the subpixel pitch in the X direction is about 28 μm, and the subpixel pitch in the Y direction is about 84 μm, it is possible to form a display device (micro LED display) with a pixels per inch (PPI) of about 900.

[0065] According to the first embodiment, even if a heterogeneous substrate is used for the main substrate 1, for example, the crystallinity of the first light-emitting portion L1 located above the first hole H1 formation region can be improved, and the light-emitting efficiency of the first light-emitting portion L1 can be increased. Furthermore, by forming, for example, a part of the first hole H1 in the main substrate 1, which is a growth substrate, the first hole H1 can function as a container for holding the first wavelength conversion layer J1, and the main substrate 1 (for example, a silicon substrate) with low light transmittance can function as a light shielding structure for mitigating the crosstalk phenomenon (light interference between adjacent light-emitting portions). This simplifies the extraction structure of the light generated in the first light-emitting portion L1, and also increases the extraction efficiency.

[0066] Example 2 FIG. 20 is a cross-sectional view of the light-emitting device according to Example 2 along the X direction. FIG. 21 is a cross-sectional view of the light-emitting device according to Example 2 along the Y direction. FIG. 22 is a plan view of the light-emitting device according to Example 2. In the light-emitting device 30 of Example 2, at least a part of the bottom of the first hole H1 is included in the base part 4, and a transparent resin layer TL in contact with the bottom of the first hole H1 and a first wavelength conversion layer J1 are provided in the first hole H1. The transparent resin layer TL and the first wavelength conversion layer J1 are in contact with each other, and the contact surface of the transparent resin layer TL and the first wavelength conversion layer J1 is located in the main substrate 1. The transparent resin layer TL can be made of a material having a smaller refractive index than the base part 4. The same applies to the second and third holes H2 and H3. This can suppress the light (stray light) propagated in the base part 4 from entering the first to third wavelength conversion layers J1 to J3.

[0067] In the second embodiment, as shown in FIGS. 21 and 22, at least a part of the first pad P1 does not overlap the first hole H1 in a plan view. This can reduce the effect of the pressure on the first pad P1 on the compound semiconductor portion 9 and the base semiconductor portion 8. Also, at least a part of the first pad P1 does not overlap the first light emitting portion L1. This can reduce the effect of the pressure on the first pad P1 on the first light emitting portion L1 of the compound semiconductor portion 9. The first pad P1 does not contact the base semiconductor portion 8, and the insulating film DF can be located between the first pad P1 and the base semiconductor portion 8. This can prevent the formation of a short circuit path. The insulating film DF may be transparent.

[0068] 23 and 24 are cross-sectional views showing another configuration of the light-emitting device of Example 2. In the light-emitting device 30 of Fig. 23, at least a part of the bottom of the first hole H1 is included in the mask 6. This makes it possible to prevent light (stray light) propagated within the base portion 4 from being incident on the first to third wavelength conversion layers J1 to J3.

[0069] In the light emitting device 30 of FIG. 24, the first hole H1 penetrates the mask 6, and at least a part of the bottom of the first hole H1 is included in the base semiconductor section 8. The bottom of the first hole H1 may be the lower surface of the base semiconductor section 8. The transparent resin layer TL may be made of a material having a smaller refractive index than the mask 6. This makes it possible to suppress the incidence of light (stray light) propagated inside the mask 6 into the first to third wavelength conversion layers J1 to J3. In addition, for example, there is no change in the refractive index in the optical path from the first light emitting section L1 to the bottom of the hole H1. Therefore, the light emitted from the first light emitting section L1 is unlikely to be reflected or scattered in this optical path and efficiently reaches the hole H1, thereby improving the light extraction efficiency.

[0070] Fig. 25 is a cross-sectional view showing another configuration of the light emitting device according to Example 2. In Fig. 20 and other figures, the bottom surface of the first partition portion QF is located on the base semiconductor portion 8, and the bottom surface of the second partition portion QS is located on the upper surface of the mask portion 5, but this is not limiting. As shown in Fig. 25, the first and second light-shielding partition portions QF and QS may also be configured to penetrate the mask 6 and the base portion 4 and reach the upper surface of the main substrate 1.

[0071] Fig. 26 is a cross-sectional view showing another configuration of the light emitting device according to Example 2. In Fig. 20 and other figures, the first and second partition portions QF and QS are light-shielding, but this is not limited thereto. As shown in Fig. 26, the first and second partition portions QF and QS may be made of a light-transmitting material whose refractive index for the emission wavelength of each light emitting portion is smaller than that of the base semiconductor portion 8. In this way, light incident on the first and second partition portions QF and QS at an angle exceeding the critical angle is totally reflected, so that the propagation of light (stray light) within the base semiconductor portion 8 can be suppressed.

[0072] Fig. 27 is a cross-sectional view showing another configuration of the light emitting device according to Example 2. In Fig. 20 and other figures, the first to third wavelength conversion layers J1 to J3 are provided, but the present invention is not limited to this. For example, as shown in Fig. 27, it is also possible to configure the first to third light emitting sections L1 to L3 to have a blue light emission wavelength, not provide a wavelength conversion layer in the third hole H3, and allow blue light from the third light emitting section L3 to exit from the third hole H3. Note that a transparent resin layer TL may be provided in the third hole H3.

[0073] Fig. 28 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2. As shown in Fig. 28, a third electrode E3 (light-reflecting electrode) that overlaps with the second light-emitting portion L2 in a plan view is provided, and the distance between the first electrode E1 (light-reflecting electrode) and the first wavelength conversion layer J1 can be made larger than the distance between the third electrode E3 and the second wavelength conversion layer J2. In this case, the transparent resin layer TL of the first hole H1 may be made thicker than the transparent resin layer TL of the second hole H2, or the depth of the first hole H1 may be made smaller than the depth of the second hole H2.

[0074] In addition, a fifth electrode E5 (light reflecting electrode) that overlaps with the third light emitting portion L3 in a plan view can be provided, and the distance between the third electrode E3 and the second wavelength conversion layer J2 can be made greater than the distance between the fifth electrode E5 and the third wavelength conversion layer J3. In this way, when the emission wavelength of the first wavelength conversion layer J1>the emission wavelength of the second wavelength conversion layer J2>the emission wavelength of the third wavelength conversion layer J3, an optical resonance effect can be obtained.

[0075] Fig. 29 is a cross-sectional view showing another configuration of the light emitting device according to Example 2. As shown in Fig. 29, an optical layer CL may be provided in the first hole H1, located closer to the light output surface than the first wavelength conversion J1. The optical layer CL may have at least one of a light diffusion function and a polarization function. For example, the optical layer CL having a light diffusion function improves the viewing angle characteristics (the change in luminance due to the viewing angle becomes smaller). In addition, the optical layer CL having a polarization function (for example, a circular polarization function) can reduce the influence of external light.

[0076] Fig. 30 is a cross-sectional view showing another configuration of the light emitting device according to Example 2. As shown in Fig. 30, in the first hole H1, for example, a light reflecting film LF (for example, a metal film) may be provided on the hole wall located closer to the light emitting surface side than the first wavelength conversion J1. This can improve the light utilization efficiency.

[0077] Example 3 FIG. 31 is a cross-sectional view of the light emitting device according to Example 3 along the X direction. FIG. 32 is a cross-sectional view of the light emitting device according to Example 3 along the Y direction. FIG. 33 is a plan view of the light emitting device according to Example 3. As shown in FIGS. 31 to 33, the first and second light emitting portions L1 and L2 are adjacent to each other in the X direction, the first electrode E1 is an anode (p electrode) overlapping the first light emitting portion L1 in a plan view, the second electrode E2 is a cathode (n electrode) adjacent to the first electrode E1 in the X direction, the third electrode E3 is an anode overlapping the second light emitting portion L2 in a plan view, and the fourth electrode E4 is a cathode adjacent to the third electrode E3 in the X direction. In Example 3, the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 are arranged in this order in the X direction, that is, in the <11-20> direction of the base semiconductor portion 8 including a GaN-based semiconductor, and the anodes are not adjacent to each other in the X direction.

[0078] In a plan view, the first electrode E1 overlaps with the second portion SD (the portion located on the mask portion 5) of the base semiconductor portion 8, and at least a portion of the first pad P1 connected to the first electrode E1 does not overlap with the first hole H1.

[0079] In a plan view, the opening K1 of the mask 6 is located between the first and second light-emitting portions L1 and L2, the first partition portion QF is located so as to overlap with the opening K1, and the third partition portion QT extending in the X direction is located between the first light-emitting portions L1 adjacent to each other in the Y direction. The third partition portion QT may have a light-shielding property, and may have a lower refractive index than the base semiconductor portion 8.

[0080] Fig. 34 and Fig. 35 are cross-sectional views showing another configuration of the light-emitting device according to Example 3. In Fig. 34, the first electrode E1, the second electrode E2, the fourth electrode E4, and the third electrode E3 are arranged in this order in the X direction, and the cathodes are adjacent to each other in the X direction. In Fig. 35, the second electrode E2, the first electrode E1, the third electrode E3, and the fourth electrode E4 are arranged in this order in the X direction, and the anodes are adjacent to each other in the X direction.

[0081] Fig. 36 is a cross-sectional view showing another configuration of the light emitting device according to Example 3. Fig. 37 is a plan view showing another configuration of the light emitting device according to Example 3. As shown in Figs. 36 and 37, the second electrode E2, which is a cathode, may be provided so as to overlap with the opening K1 of the mask 6 in a planar view. The first light emitting portion L1 overlaps with the second portion LD in a planar view, and the first electrode E1 overlaps with the first light emitting portion L1 in a planar view.

[0082] 36 and 37, the first and second electrodes E1 and E2 are aligned in the X direction. The first and second electrodes E1 and E2 are light reflective. In plan view, at least a portion of the first pad P1 does not overlap with the first hole H1, and at least a portion of the second pad P2 does not overlap with the first hole H1.

[0083] Example 4 38 and 39 are cross-sectional views showing another configuration of the light emitting device according to the fourth embodiment. In FIG. 38, the base portion 4 is locally provided so as to overlap the opening K1 of the mask 6 in a plan view. For example, the base portion 4 is patterned to have a slit shape extending in the Y direction so as to overlap the opening K1. The bottom of the first hole H1 is included in the base semiconductor portion 8. By locally providing the base portion 4, it is possible to reduce warping of the light emitting device 30 and improve the bonding accuracy to the driving substrate TK. The main substrate 1 may be a silicon substrate, and the local base portion 4 may include a buffer portion (including at least one of AlN and SiC, for example) and a seed portion (GaN-based semiconductor), or the main substrate 1 may be a silicon substrate, and the local base portion 4 may include a seed portion (for example, AlN, 6H-SiC). As shown in FIG. 39, the lower surface of the base semiconductor portion 8 may be the bottom of the first hole H1.

[0084] Example 5 FIG. 40 is a flow chart showing a method for manufacturing a light emitting device according to Example 5. FIG. 41 is a cross-sectional view showing a configuration of a light emitting device according to Example 5. In Examples 1 to 4, the light emitting device 30 includes a mask 6, but is not limited thereto. As shown in FIG. 40, the mask can be removed after forming a compound semiconductor portion 9 on a semiconductor substrate 10 including the mask. The mask can be removed by using an etchant such as hydrofluoric acid or buffered hydrofluoric acid, for example, by a wet etching method. The light emitting device 30 in FIG. 41 includes a base substrate UK including a main substrate 1, a semiconductor substrate 10 having a base semiconductor portion 8 located above the base substrate UK, and a compound semiconductor portion 9 located above the semiconductor substrate 10 and having a first light emitting portion L1. The semiconductor substrate 10 does not include a mask. In this embodiment, the mask is removed before forming the electrodes, but the mask may be removed by a method such as a wet etching method after the electrodes are formed and the electrodes are protected with a resist or the like.

[0085] The base semiconductor portion 8 includes a connection region 8C that contacts the underlying substrate UK and a non-connection region (non-contact region) 8D that is separated from the underlying substrate UK. The semiconductor substrate 10 includes a first hole H1 that penetrates the main substrate 1 in the thickness direction (Z direction) and overlaps with the first light emitting portion L1 in a planar view below the first light emitting portion L1. The first light emitting portion L1 overlaps with the non-connection region 8D above the non-connection region 8D in a planar view.

[0086] The base semiconductor portion 8 includes a first portion HD and a second portion SD in which the density of dislocations extending in the thickness direction (Z direction) is lower than that of the first portion HD. The first light emitting portion L1 is above the second portion SD and overlaps with the second portion SD in a plan view.

[0087] FIG. 42 is a flowchart showing another manufacturing method of the light emitting device according to the fifth embodiment. FIG. 43 is a cross-sectional view showing another configuration of the light emitting device according to the fifth embodiment. In FIG. 42, a compound semiconductor section 9 is formed on a semiconductor substrate 10 including a mask, a first electrode E1 and a first pad P1 are formed, and a first hole H1 penetrating the main substrate 1 is formed, and then the mask of the semiconductor substrate 10 is removed by etching or the like. Then, a first wavelength conversion layer J1 is formed in the first hole H1. In the light emitting device 30 of FIG. 43, a part of the transparent resin layer TL is disposed in a hollow portion TS generated by removing the mask, the lower surface of the base semiconductor section 8 contacts the transparent resin layer TL and the hollow portion TS, and the base portion 4 of the base substrate UK contacts the hollow portion TS. The remaining part of the transparent resin layer TL and the first wavelength conversion layer J1 are provided in the first hole H1. The first light-emitting portion L1 overlaps with the non-connection region 8D above the non-connection region 8D in a planar view, and the first light-emitting portion L1 overlaps with the second portion SD above the second portion SD in a planar view.

[0088] FIG. 44 is a cross-sectional view showing another configuration of the light-emitting device according to Example 5. In the light-emitting device 30 of FIG. 44, the base portion 4 is locally arranged in a slit shape, and for example, the bottom of the first hole H1 is located on the lower surface of the base semiconductor portion 8. In this case, after the first hole H1 reaching the lower surface of the base semiconductor portion 8 is formed in the semiconductor substrate 10, the mask 6 is removed by etching or the like to expose the bottom of the base semiconductor portion 8. The first light-emitting portion L1 overlaps the non-connected region 8D above the non-connected region 8D in a planar view, and the first light-emitting portion L1 overlaps the second portion SD above the second portion SD in a planar view. In this case, the process is shortened because the step of removing the base portion 4 is not necessary. In addition, the distance (in the Z direction) from the first light-emitting portion L1 to the bottom of the first hole H1 is shortened, and the light extraction efficiency from the first hole H1 is improved.

[0089] Example 6 In the first to fifth embodiments, the base semiconductor portion 8 may be a GaN layer, but is not limited thereto. The base semiconductor portion 8 in the first to fifth embodiments may be an InGaN layer, which is a GaN-based semiconductor layer. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable that indium is incorporated into the InGaN layer at an In composition level of 1% or more, since this further reduces the reactivity with the mask portion 5. As the gallium source gas, triethylgallium (TEG) is preferably used.

[0090] Example 7 Fig. 45 is a schematic plan view showing a display device of Example 7. As shown in Fig. 45, a plurality of light emitting devices 30 of Examples 1 to 6 may be mounted on a driving substrate TK to form a display device 50. A plurality of light emitting devices 30 may be arranged in a matrix. The driving substrate TK may include first and second driver circuits D1 and D2 and a control circuit DC that controls these circuits (see Fig. 18). In this way, large display devices can be manufactured with a good yield.

[0091] Example 8 Fig. 46 is a schematic diagram showing the configuration of an electronic device according to Example 8. An electronic device 90 in Fig. 46 includes a display device 50 including the light emitting device 30 of Examples 1 to 6, and a control unit 80 including a processor. Examples of the electronic device 90 include a communication device, an information processing device, a medical device, an electric vehicle (EV), a monitor, a television, and the like.

[0092] The above-mentioned embodiments and examples are described for the purpose of illustration and explanation, and are not intended to be limiting. Based on these examples and explanations, it is clear to those skilled in the art that many variations are possible.

[0093] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0094] 1 Main Board 4 Base 5 Mask section 6. Mask 8 Base Semiconductor Section 9. Compound Semiconductor Department 10. Semiconductor Substrate 30 Light-emitting devices 50 Display Devices L1 First light emitting part L2 Second light emitting part K1 / K2 opening E1 1st electrode E2 2nd electrode J1 First wavelength conversion layer H1 Hall 1 H2 Hall 2 TK drive board UK base board

Claims

1. a template substrate having a first surface and a second surface opposite the first surface; a base semiconductor portion including a nitride semiconductor, the base semiconductor portion being located on the second surface and including a first portion and a second portion having a lower density of dislocations extending in a thickness direction than the first portion; a compound semiconductor portion located on the base semiconductor portion and having a first light emitting portion; A first electrode and a second electrode, the template substrate has a first hole formed in a thickness direction from the first surface and overlapping with the first light emitting portion in a plan view; a light-emitting device, wherein the first electrode and the second electrode are aligned in a <1-100> direction of the nitride semiconductor or in a <11-20> direction of the nitride semiconductor;

2. the template substrate has a main substrate including the first surface; The light emitting device of claim 1 , wherein the first hole penetrates the main substrate in a thickness direction.

3. The light-emitting device according to claim 1 , wherein the first hole, the first light-emitting portion, and the second portion overlap in a plan view.

4. The light-emitting device according to claim 1 , wherein the first hole does not overlap the first portion in a plan view.

5. The light-emitting device according to claim 1 , wherein an entire bottom of the first hole overlaps with the second portion and the first light-emitting portion in a plan view.

6. the first electrode is an anode and the second electrode is a cathode; The light-emitting device according to claim 1 , wherein the first electrode overlaps with the first light-emitting portion and the first hole in a plan view.

7. the base semiconductor portion has two second portions, disposed adjacent to the first portion, and each second portion has a lower density of dislocations extending in a thickness direction than the first portion; the compound semiconductor portion has a second light emitting portion, In the plan view, the first light-emitting portion overlaps the first hole and one of the two second portions, The light-emitting device according to claim 1 , wherein the template substrate has a second hole formed in a thickness direction from the first surface and overlapping with the second light-emitting portion and the other of the two second portions in the plan view.

8. The light-emitting device according to claim 7 , further comprising a partition portion located between the first light-emitting portion and the second light-emitting portion in a plan view and overlapping with the first portion.

9. a first wavelength conversion layer located in the first hole and emitting light having a wavelength longer than a light receiving wavelength; a second wavelength conversion layer located in the second hole and emitting light having a longer wavelength than the light receiving wavelength; The light emitting device of claim 7 , wherein the emission wavelength of the first wavelength-converting layer is greater than the emission wavelength of the second wavelength-converting layer.

10. 3. The light-emitting device according to claim 1, wherein the first portion has a longitudinal direction aligned with a <1-100> direction of the nitride semiconductor.

11. The threading dislocation density of the second portion is 5×10 ６ / cm ２ 3. The light emitting device according to claim 1, wherein:

12. a template substrate having a first surface and a second surface opposite the first surface; a base semiconductor portion located on the second surface, the base semiconductor portion having a connection region connected to the template substrate and a non-connection region not connected to the template substrate, the base semiconductor portion including a nitride semiconductor; a compound semiconductor portion located on the base semiconductor portion and having a first light emitting portion; A first electrode and a second electrode, the base semiconductor portion includes a connection region that is connected to the template substrate and a non-connection region that is not connected to the template substrate, the template substrate includes a first hole formed in a thickness direction of the main substrate from the first surface and overlapping with the first light-emitting portion in a plan view; a light-emitting device, wherein the first electrode and the second electrode are aligned in a <1-100> direction of the nitride semiconductor or in a <11-20> direction of the nitride semiconductor;

13. A display device comprising the light emitting device according to claim 1 or 12 and a drive substrate on which the light emitting device is mounted.

14. preparing a template substrate having a first surface and a second surface located opposite to the first surface, and a base semiconductor portion located on the second surface, the base semiconductor portion including a first portion and a second portion having a lower density of dislocations extending in a thickness direction than the first portion, the base semiconductor portion including a nitride semiconductor; forming a compound semiconductor section having a first light emitting section on the base semiconductor section; forming a first electrode and a second electrode; forming a first hole in a thickness direction from the first surface of the template substrate; The first hole is formed so as to overlap with the first light emitting portion in a plan view; The first electrode and the second electrode are formed to be aligned in a <1-100> direction of the nitride semiconductor or a <11-20> direction of the nitride semiconductor.

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