Display device

Abstract

To provide: a display device with suppressed consumption power; a display device of a self-light-emitting type with suppressed consumption power; and a display device of a self-light-emitting type with suppressed consumption power, capable of being usable for a long time even in a dark place.SOLUTION: A circuit is formed using a thin film transistor including a highly purified oxide semiconductor, so that a pixel can be kept in a constant state (state in which a video signal is written). As a result, stable operation is facilitated even in the case of displaying a still image. In addition, since the operation intervals of a driving circuit can be made long, the consumption power of the display device can be reduced. Moreover, when a luminous material is used for a pixel portion of a display device of a self-light-emitting type and light of a light-emitting element is accumulated, the use for a long time becomes possible even in a dark place.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device and an electronic device having the display device. A display device and a display device configured with a field effect transistor and a light emitting element using the body This relates to electronic devices that have [Background technology]

[0002] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Thin-film transistors are used in displays such as LCD TVs. Silicon-based semiconductors are used as semiconductor thin films that can be applied to thin-film transistors. Although semiconductor materials are well known, oxide semiconductors are attracting attention as other materials.

[0003] Zinc oxide or a material containing zinc oxide is known as an oxide semiconductor material. And the electron carrier concentration is 10 18 / cm 3 Amorphous oxide (oxide semiconductor) Thin film transistors formed from the above have been disclosed (Patent Documents 1 to 3).

[0004] A field effect transistor using an oxide semiconductor can be applied to, for example, a display device. There are two types of display devices: a self-luminous display device that emits light to display images, and a backlight that selectively emits light. A transparent display device displays an image by partially transmitting light into the screen, while a reflective display device displays an image by reflecting external light. There are display devices of this type.

[0005] The characteristics of self-luminous display devices and transmissive display devices are that they are less susceptible to external light and produce vivid colors. He is skilled in expressing himself visually.

[0006] A feature of reflective display devices is that they do not require a built-in light source, making it easy to reduce power consumption. Of course, the displayed image can be rewritten, making it an ideal electronic paper alternative to print media. As such, it is attracting attention in a society that aims to conserve resources.

[0007] However, in environments with little external light, the visibility of reflective display devices decreases, and Lighting is required for this purpose. When lighting is used, it is possible to use a reflective display device that consumes less power. Therefore, we have developed a system that can reduce power consumption while improving visibility in dark places. To achieve this, materials that store external light, such as phosphorescent fluorescent materials and phosphorescent materials, are applied to reflective display devices. The invention is disclosed in Patent Documents 4 and 5. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165527 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165529 [Patent Document 4] Japanese Patent Application Laid-Open No. 2006-3924 [Patent Document 5] Japanese Patent Application Laid-Open No. 2008-116855 Summary of the Invention [Problem to be solved by the invention]

[0009] The oxide semiconductor tends to deviate from the stoichiometric composition during the thin film formation process. The electrical conductivity of oxide semiconductors changes depending on the amount of oxygen. Hydrogen that is mixed in during the thin film formation of the polymer forms an oxygen (O)-hydrogen (H) bond and becomes an electron donor. Furthermore, since OH is a polar molecule, it is a factor that changes the electrical conductivity of oxide semiconductors. This is a factor that can cause fluctuations in the characteristics of active devices such as thin film transistors fabricated by do.

[0010] The electron carrier concentration is 10 18 / cm 3 Even if it is less than 100%, in the case of an oxide semiconductor, The thin film transistor disclosed in the patent document is n-type, and the on-off ratio is 10 3 Only good The reason for the low on-off ratio of such thin film transistors is that the off-current is high. This is due to the fact that

[0011] When a thin film transistor with a high off-state current is used in a pixel portion of a display device, a signal applied to the pixel In order to maintain the voltage, it is necessary to provide an additional capacitance. This causes a problem that the aperture ratio decreases and the power consumption of the display device increases.

[0012] In order to reduce the power consumption of a self-luminous or transmissive display device, the display device has If the energy supplied to the light-emitting element is reduced, the display will become dark or disappear. The impact on display quality is significant.

[0013] Furthermore, the reflective display device using the phosphorescent material disclosed in the above patent document is suitable for use in environments with little external light. Even in the dark, it is possible to display with low power consumption, but it is necessary to irradiate the phosphorescent material with external light in advance. The material must store light, making it unsuitable for long-term use in dark places.

[0014] The present invention has been made under such technical background. Therefore, the object of the present invention is to provide a method for manufacturing a semiconductor device using a semiconductor laser. It is an object of the present invention to provide a display device with reduced power consumption. Another object of the present invention is to provide a self-luminous display device that can be used for a long time even in a dark place. One of the objects of the present invention is to provide a self-luminous display device that can be used in a wide range of applications and has reduced power consumption. . [Means for solving the problem]

[0015] One aspect of the present invention is to provide a semiconductor device having stable electrical characteristics (for example, an extremely reduced off-state current). Specifically, the display device is a self-luminous display device that uses a thin film transistor having an oxide semiconductor. By removing impurities that act as electron donors in the conductor, intrinsic or substantially intrinsic It is a semiconductor that is an oxide semiconductor with a larger energy gap than silicon semiconductors. The thin film transistors in which the panel region is formed constitute a driving circuit for the light emitting element. do.

[0016] That is, in one embodiment of the present invention, the amount of hydrogen contained in the oxide semiconductor is 5×10 19 / cm 3 below , preferably 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 The following By removing hydrogen or OH bonds contained in the oxide semiconductor, the carrier concentration is reduced to 1×10 1 4 / cm 3 Less than 1 x 10 12 / cm 3 The channel of the oxide semiconductor film is The thin film transistors in which the regions are formed constitute a driving circuit for the light emitting element.

[0017] The energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As a result, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration is kept at 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Make it so that it is as follows.

[0018] Such a highly purified oxide semiconductor is used in the channel formation region of a thin film transistor. By doing so, even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. In the gate voltage range of -5V to -20V, the drain current is 1×10 - 13 It acts to keep it below A.

[0019] Another embodiment of the present invention focuses on power consumption by a driver circuit included in a self-luminous display device. That is, the frequency with which the drive circuit operates is reduced, thereby reducing the power consumed by the display device. In addition, a light-storing layer is provided in the pixel portion of a self-luminous display device, and a light-emitting element is provided in the light-storing layer. The light emitted by the phosphorescent layer is stored and supplied to the light emitting element while the light emitted by the phosphorescent layer displays an image. This can be achieved by reducing the energy consumption of the display device.

[0020] That is, one aspect of the present invention is a power supply line for supplying pulsed DC power to a pixel, and a power supply line for supplying pulsed DC power to a pixel. a first light emitting element to which power is supplied from the power supply line, and a second light emitting element that controls opening and closing of a circuit connecting the power supply line and the light emitting element; The pixel also has a signal line for supplying a video signal, and a thin film transistor and a second thin film transistor that controls the opening and closing of a circuit that connects the transistors. The channel formation region of the second thin film transistor has a band gap of 2 eV or more, and The element concentration is 5 x 10 19 / cm 3 The channel width is 1 Off-state current per μm is 1×10 -16 The second thin-film transistor suppressed to less than A / μm The capacitor maintains the first thin film transistor in an on state, and connects the power supply line and the light emitting element. A display device that displays still images.

[0021] In one embodiment of the present invention, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 Less than The display device is one of the above.

[0022] In addition, one aspect of the present invention is to provide a method for reducing a period during which output of a scanning line signal is stopped during a display period of a still image. The display device has the above structure.

[0023] Another embodiment of the present invention is a light-emitting element including a pair of electrodes and a light-emitting organic substance between the pair of electrodes. The display device has a layer including:

[0024] Another embodiment of the present invention is the above display device including a luminous layer in a pixel.

[0025] Another embodiment of the present invention is an electronic device including the display device.

[0026] In this specification, the term "luminous material" refers to a material that absorbs external energy such as light and emits light. A material that generates relatively stable and long-lived excitons, and the excitons last for a relatively long time. This refers to materials that emit light and then deactivate over a period of time. The material continues to emit light even after the external energy source is discontinued.

[0027] In this specification, a pixel refers to an element, such as a thin film, provided in each pixel of a display device. The display is controlled by electrical signals from transistors, electrodes that function as pixel electrodes, and wiring. A pixel is a group of elements that are made up of elements that control the color of the image. Each pixel may contain one color element whose brightness can be controlled. Therefore, for example, in the case of a color display device consisting of RGB color components, A small unit is composed of three pixels: an R pixel, a G pixel, and a B pixel. The pixels are what allow an image to be obtained.

[0028] In this specification, when it is stated that A and B are connected, it means that A and B are electrically connected. This includes cases where A and B are electrically connected and cases where A and B are directly connected. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0029] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element. Therefore, the light-emitting layer containing an organic compound, which is a light-emitting material sandwiched between the electrodes, is one of the EL layers. This is an aspect.

[0030] In addition, in this specification, when a substance A is dispersed in a matrix made of another substance B, The substance B that composes the matrix is ​​called the host material, and the substance A that is dispersed in the matrix is ​​called the guest material. In addition, Substance A and Substance B may each be a single substance. It may be a mixture of two or more substances.

[0031] In this specification, the term "light emitting device" refers to an image display device, a light emitting device, or a light It also refers to a light source (including lighting devices) that has a connector, such as an FPC (Flexible Printed Circuit). le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packaging) e) is attached to the module, and the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) on a substrate on which a light emitting element is formed. s) All modules in which ICs (integrated circuits) are directly mounted using this method are also included in the light-emitting device. Let's say. [Effects of the Invention]

[0032] According to one embodiment of the present invention, a circuit is formed using a thin film transistor including a highly purified oxide semiconductor. By configuring the display device, the operation of the circuitry included in the display device can be stabilized. The current is 1×10 -13 A or less, the signal applied to the pixel of the display device It is no longer necessary to provide an additional capacitor for holding the voltage. Since the aperture ratio is increased, the light-emitting element can be This suppresses the driving voltage and reduces the power consumption of the display device.

[0033] Furthermore, a pixel using a thin film transistor according to one embodiment of the present invention can be used in a constant state (when a video signal is This allows the data to be stored in a stable state even when displaying still images. In addition, the operation interval of the drive circuit can be extended, so that the display device can be operated Power consumption can be reduced.

[0034] According to one embodiment of the present invention, a display device that can be used even in an environment with weak external light can be provided. Furthermore, it is possible to provide a display device that can display images while suppressing power consumption. [Brief explanation of the drawings]

[0035] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a pixel according to an embodiment; [Figure 2] 1A and 1B illustrate a structure of a display device according to an embodiment. [Figure 3] 5A and 5B are diagrams illustrating a writing period and a holding period to a pixel according to an embodiment. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a pixel according to an embodiment; [Figure 5] 1A and 1B are a top view and a cross-sectional view of a thin film transistor according to an embodiment; [Figure 6] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 7] 1A and 1B are a top view and a cross-sectional view of a thin film transistor according to an embodiment; [Figure 8] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 9] 1 is a cross-sectional view of a thin film transistor according to an embodiment. [Figure 10] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 11] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 12] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 13] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 14] 1 is a cross-sectional view of a thin film transistor according to an embodiment. [Figure 15] 2A and 2B are diagrams illustrating an equivalent circuit of a pixel according to an embodiment. [Figure 16] FIG. 2 is a cross-sectional view of a pixel according to the embodiment. [Figure 17] 1 is a cross-sectional view of a light emitting device according to an embodiment. [Figure 18]FIG. 2 is a cross-sectional view of a pixel according to the embodiment. [Figure 19] 1A to 1C illustrate electronic devices according to an embodiment. [Figure 20] 1A to 1C illustrate electronic devices according to an embodiment. [Figure 21] FIG. 1 is a longitudinal cross-sectional view of an inverted staggered thin film transistor including an oxide semiconductor. [Figure 22] 22 is an energy band diagram (schematic diagram) taken along the line AA' in FIG. 21. [Figure 23] (A) shows a state in which a positive potential (+VG) is applied to the gate (G1), and (B) shows a state in which a negative potential (-VG) is applied to the gate (G1). [Figure 24] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 25] FIG. 1 is a block diagram illustrating a configuration of a display device according to an embodiment. [Figure 26] 1A to 1C illustrate a configuration of a driver circuit and a shift register according to an embodiment. [Figure 27] 4 is a timing chart illustrating the operation of a shift register. [Figure 28] 4 is a timing chart illustrating the operation of a shift register. DETAILED DESCRIPTION OF THE INVENTION

[0036] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0037] (Embodiment 1) In this embodiment, a thin film transistor and a pixel electrode using a highly purified oxide semiconductor are Examples of constituent pixels will be described below with reference to FIGS.

[0038] First, a top view of a pixel is shown in FIG. 1(A). The structure of the TFT shown in FIG. 1(A) is as follows: As an example, a bottom gate structure is shown, where the channel is located from the gate wiring. On the opposite side of the oxide semiconductor layer that will become the gate region, wiring will be placed to become the source and drain electrodes of the TFT. The pixel 10 shown in FIG. 1A has a so-called inverted staggered structure. 0 is a first wiring 101 that functions as a scanning line, a second wiring 102 that functions as a signal line, A has an oxide semiconductor layer 103, a capacitance line 104, and a pixel electrode 105. The thin film has a third wiring 102B for electrically connecting the thin film layer 103 and the pixel electrode 105. A membrane transistor 106 is constructed.

[0039] The first wiring 101 also functions as a gate of the thin film transistor 106. The wiring 102A serves as one of the source electrode or drain electrode and one electrode of the storage capacitor. The third wiring 102B is a wiring that functions as a source electrode or a drain electrode. The capacitance line 104 is also a wiring that functions as the other electrode of the storage capacitor. The first wiring 101 and the capacitance line 104 are provided in the same layer, and the second wiring 10 2A and the third wiring 102B are provided in the same layer. The thin film 04 is provided so as to partially overlap with the thin film 04, forming a storage capacitor for the light-emitting element. The oxide semiconductor layer 103 of the thin film transistor 106 is a wiring that branches off from the first wiring 101. It is provided on the wiring via a gate insulating film (not shown).

[0040] FIG. 1(B) shows the cross-sectional structure between the dashed line A1 and A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), a gate electrode is formed on a substrate 111 via an underlayer 112. The first wiring 101 and the capacitor line 104 are provided. A gate insulating film 113 is provided to cover the line 104. An oxide semiconductor layer 103 is provided on the second wiring. The oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B are provided. An acid film functioning as a passivation film is formed on the wiring 102A and the third wiring 102B. An oxide insulating layer 114 is provided. An opening is formed in the oxide insulating layer 114. The pixel electrode 105 and the third wiring 102B are connected in the opening. The wiring 102B and the capacitance line 104 form a capacitance element with the gate insulating film 113 as a dielectric. are.

[0041] FIG. 1(C) shows a cross-sectional view of the dashed line B1-B2 in FIG. 1(A). 1 shows a configuration in which an insulating layer 121 is provided between the capacitance line 104 and the second wiring 102A. .

[0042] When the second wiring 102A is provided on the first wiring 101 and the capacitance line 104, the gate insulating film Depending on the film thickness of 113, the first wiring 101, the second wiring 102A, and the capacitance line 104 may be Therefore, a parasitic capacitance occurs between the first wiring 102A and the second wiring 102B. Thus, the provision of the insulating layer 121 reduces parasitic capacitance and reduces defects such as malfunctions. can be done.

[0043] The pixels shown in FIGS. 1A to 1C are formed by disposing a plurality of pixels on a substrate 200 as shown in FIG. In FIG. 2, the pixel section 201 is arranged on the substrate 200. 202, a scanning line driver circuit 203, and a signal line driver circuit 204. The pixel 201 is supplied with a first wiring 101 connected to a scanning line driving circuit 203. The scanning signal determines whether each row is in a selected state or a non-selected state. The pixel 201 selected by the signal is connected to the second wiring 204. 102A, a video voltage (video signal, image signal, video signal) is supplied from the second wiring 102A. Signals, also called video data, are supplied.

[0044] In FIG. 2, a scanning line driving circuit 203 and a signal line driving circuit 204 are provided on a substrate 200. However, either the scanning line driver circuit 203 or the signal line driver circuit 204 The pixel portion 202 may be provided on the substrate 200. Alternatively, only the pixel portion 202 may be provided on the substrate 200. It may also be configured so that

[0045] In FIG. 2, a pixel section 202 has a plurality of pixels 201 arranged in a matrix (stripe arrangement). It should be noted that the pixels 201 do not necessarily need to be arranged in a matrix. For example, the pixels 201 may be arranged in a delta arrangement or a Bayer arrangement. The display method in the unit 202 is either a progressive method or an interlace method. The color elements controlled by pixels when displaying colors are RGB (R The number of colors is not limited to three, but may be more than three, for example, RGBW (W is white), or RGB plus one or more colors such as yellow, cyan, or magenta. The size of the display area may differ for each dot of the color element.

[0046] In FIG. 2, the first wiring 101 and the second wiring 102A are arranged in a number equal to the number of pixels in the row and column directions. The first wiring 101 and the second wiring 102A are shared between pixels. The pixel 201 may be driven.

[0047] In FIG. 1A, the second wiring 102A of the TFT is shown as having a rectangular shape. However, the shape of the third wiring 102B is such that it surrounds the third wiring 102B (specifically, U-shaped or C-shaped), and the This increases the area of ​​the region through which carriers move, and reduces the current that flows when the thin film transistor is turned on (ON). The amount of current (also referred to as current) may be increased.

[0048] Note that the on-state current described in this specification refers to the current that flows when a thin film transistor is in an on-state (also called a conductive state). ) refers to the current that flows between the source and drain when n-channel thin-film transistors In a transistor, when the voltage applied between the gate and source is greater than the threshold voltage (Vth), This refers to the current that flows between the source and drain.

[0049] The aperture ratio is the ratio of the area through which light passes to the unit area. When the area occupied by the non-transmitting material becomes large, the aperture ratio decreases and the area that transmits light becomes smaller. In a display device, the area occupied by the material is increased, and the aperture ratio is improved. The area occupied by the overlapping wiring, the capacitance line, and the size of the thin film transistor are reduced. This will improve the rate of speaking.

[0050] In particular, in the case of a self-luminous display device, the observer observes from a position facing the display of the display device. The ratio of the light-emitting area of ​​a possible light-emitting element to the pixel area is called the aperture ratio.

[0051] A thin film transistor has at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region. A current can flow through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is unclear which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the source or drain. The region that functions as a source or drain is sometimes not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Alternatively, they may be referred to as the first region and the second region. There is a match.

[0052] Next, the oxide semiconductor layer 103 will be described.

[0053] In the oxide semiconductor used in this embodiment, hydrogen or OH bonds are removed. The body contains 5 x 10 hydrogen 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 below, More preferably, 5 × 10 17 / cm 3 The carrier concentration is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The oxide semiconductor film having the following channel shape is The hydrogen concentration in the oxide semiconductor layer is measured by applying the method to the semiconductor layer. Secondary ion mass spectrometry (SIMS) This can be done by endoscopic examination.

[0054] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably or 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Make it so that it is as follows. That is, the carrier concentration of the oxide semiconductor layer is made as close to zero as possible.

[0055] In this way, the hydrogen contained in the oxide semiconductor layer was thoroughly removed, resulting in a highly purified oxide semiconductor. By using an oxide semiconductor layer in a channel formation region of a thin film transistor, the off-state current value Extremely small thin film transistors can be provided.

[0056] For example, the channel length of a thin-film transistor using a highly purified oxide semiconductor layer is 3 μm. Even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. When the gate voltage is in the range of -5V to -20V (off state), the drain current is 1× 10 -13 It acts to keep it below A.

[0057] The characteristics of a thin film transistor using a highly purified oxide semiconductor layer are shown in FIGS. 21 shows an inverted staggered thin film transistor using an oxide semiconductor. The vertical cross section of the gate electrode (GE1) is shown. An organic layer (OS) is provided, and a source electrode (S) and a drain electrode (D) are provided thereon. are.

[0058] FIG. 22 shows an energy band diagram (schematic diagram) in the cross section A-A' shown in FIG. 22(A) shows the case where the voltage between the source and drain is equipotential (VD = 0 V), and Fig. 22(B) shows the case where a positive potential (VD>0V) is applied to the drain relative to the source.

[0059] FIG. 23 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. 21. Figure 23(A) shows the state where a positive potential (+VG) is applied to the gate (G1), and the source The figure shows the on-state where carriers (electrons) flow between the gate and drain. is the state in which a negative potential (-VG) is applied to the gate (G1), and the transistor is in the off state (minority capacitance This shows the case where the rear does not flow.

[0060] Figure 24 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0061] Conventional oxide semiconductors are generally n-type, and in this case the Fermi level (Ef) is It is located closer to the conduction band, away from the intrinsic Fermi level (Ei) located in the center of the gap. In oxide semiconductors, some of the hydrogen atoms act as donors, which is one of the reasons for the n-type structure. It is known that this can occur.

[0062] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. By removing impurities other than the main components of the oxide semiconductor and purifying it to the utmost, In other words, it is made into an intrinsic (type i) or intended to be made into an intrinsic type. By removing as many impurities as possible, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. By doing so, the Fermi level (Ef) is Ei).

[0063] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The electron affinity function is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the interface between the layers, no Schottky barrier is formed for electrons.

[0064] In other words, when the work function of the metal (φM) and the electron affinity of the oxide semiconductor (χ) are almost equal, When the two come into contact, the energy band diagram (schematic diagram) shown in Figure 22(A) is displayed. .

[0065] In FIG. 22(B), the black circles (●) represent electrons, and when a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, then flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and drain voltage. When a voltage is applied, the barrier height of FIG. 22(A) without voltage application, i.e., the barrier The barrier height (h) is smaller than half the band gap (Eg).

[0066] At this time, the electrons are transferred to the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable part on the oxide semiconductor side at the interface with the oxide semiconductor.

[0067] In addition, in FIG. 23(B), when a negative potential is applied to the gate electrode (G1), the minority capacitance Since the rear hole is substantially zero, the current is close to zero.

[0068] For example, if the channel width W of a thin-film transistor is 1×10 4 μm and a channel length of 3 μm Even if the off-state current is 10 -13 A or less, and the subthreshold swing value (S value ) is 0.1V / dec. (gate insulating film thickness 100nm).

[0069] In this way, it is possible to purify the oxide semiconductor to the extent possible so that it does not contain impurities other than the main component. As a result, the thin film transistor can operate satisfactorily.

[0070] In this way, a thin film transistor with an extremely small current value in the off state (off current value) can be When a memory circuit (memory element) is manufactured using this, the off-current value is small and there is almost no leakage. Therefore, the time for which an electric signal such as a video signal is held can be extended.

[0071] Specifically, the thin film transistor having the above-mentioned oxide semiconductor layer has a channel width of 1 μm. The off-state current per -16 A / μm or less, and furthermore, 1aA / μm (1× 10 -18 It is possible to reduce the resistance to less than 1 / μm.

[0072] The transistor with an extremely small current value in the off state (off current value) is used as the switch in the pixel section. It is used as a switching transistor (for example, the switching transistor 6401 in FIG. 15). By doing so, it is possible to lengthen the retention time of electrical signals such as video signals. For example, the interval between writes should be 10 seconds or more, preferably 30 seconds or more. More preferably, the writing interval can be set to 1 minute or more and less than 10 minutes. This can enhance the effect of suppressing power consumption.

[0073] The difficulty in flowing an off-state current through a transistor can be expressed as an off-state resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and the off resistivity is It can be calculated from the off-state current.

[0074] Specifically, if the values ​​of the off-state current and drain voltage are known, the transistor can be calculated from Ohm's law. The resistance value when the transistor is off (off resistance R) can be calculated. The cross-sectional area A and the length of the channel formation region (corresponding to the distance between the source and drain electrodes) L are Then, the off-resistivity ρ can be calculated from the formula ρ=RA / L (R is the off-resistance).

[0075] Here, the cross-sectional area A is defined as follows: A = dW. The length L of the channel forming region is the channel length L. As described above, the off-state resistivity can be calculated from the off-state current.

[0076] The off-state resistivity of the transistor including the oxide semiconductor layer of this embodiment is 1×10 9 Ω m More than 1×10 is preferable, and 10 Ω·m or more is more preferable.

[0077] The pixel configuration shown in FIG. 15 is one example of this embodiment, for example, when a storage capacitor is used as a driving transistor. It can also be provided between the gate of the transistor 6402 and the power supply line 6407. The capacitance can be determined by sandwiching an insulating layer between a pair of electrodes as a dielectric. Considering the off-current of the switching transistor 6401, etc., a charge can be held for a predetermined period. Set it to

[0078] For example, in a thin film transistor using low-temperature polysilicon, the off-current is 1×10 -12 A Therefore, the design is carried out with the assumption that the oxide semiconductor In the thin film transistor, the storage capacity is larger than that of the thin film transistor having low-temperature polysilicon. When the capacitance is the same (about 0.1 pF), the voltage retention period is 5 Stretch it out to about twice its size In addition, in the case of a transistor using amorphous silicon, the channel width is 1 μm. The off-state current per m is 1×10 -13 A / μm or more. When the capacitance is about 0.1 pF, a transistor using a high-purity oxide semiconductor has a higher capacitance than a Compared to transistors using ruthenium silicon, the voltage retention period is 10 4 More than double It can be postponed.

[0079] For example, a pixel having a transistor using low-temperature polysilicon typically displays a 60 This is done at frames per second (16 msec per frame). Similarly, if the rate is reduced (the interval between writes is extended), the pixel voltage decreases and the display On the other hand, when a transistor including the above-described oxide semiconductor layer is used, In this case, the off-state current is small, so the retention period for one signal write is 10 5 double 160 It can be set to about 0 seconds.

[0080] As described above, the display device of this embodiment can display a still image with a small number of times of writing image signals. Since the retention period can be extended, it is possible to write signals more quickly, especially when displaying still images. This reduces the frequency of writing, thereby reducing power consumption. For example, the number of times that a pixel is written during the display period of one still image can be set to 1 or n times. Note that n is between 2 and 10. 3 This reduces the power consumption of the display device. This can be achieved.

[0081] Furthermore, in this embodiment, when a still image is displayed, the voltages supplied to the signal lines and scanning lines are By operating the driver circuit unit to stop the output of the signal, not only the pixel unit but also the driver The power consumption of the circuit section can also be reduced.

[0082] Figure 3 shows the relationship between the write period and the hold period (also called one frame period). In FIG. 3, periods 251 and 252 correspond to the retention period, and periods 261 and 262 correspond to the write period. The period corresponds to the loading period. Since the retention period (period 251, period 252) can be made long, it is especially suitable for displaying still images. When displaying, the frequency of writing signals can be significantly reduced. When displaying still images with little switching between images, it is possible to reduce the number of times signals are written to the pixels. This allows for lower power consumption.

[0083] The voltage applied to the gate of the driving transistor connected to the EL element is The voltage applied to the gate of the driving transistor is maintained For example, the refresh operation may be performed appropriately taking into consideration the ratio of the driving transistors that are maintained. The voltage value (initial value) immediately after writing a signal to the gate of the The refresh operation can be performed when the voltage drops to a predetermined level. It is preferable to set the pressure so that flickering is not noticeable compared to the initial value. If the display object is a video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. It is preferable to perform a refresh operation (rewrite) every time the display object If the value is a character, the reset is performed every time the value is 10% lower than the initial value, preferably 3% lower. A fresh operation (rewrite) is preferable.

[0084] The top view and cross-sectional view of a pixel without a storage capacitor are shown in FIG. 4(A) The configuration shown in Figs. 4(A) and (B) is the same as that shown in Figs. 1(A) and (B). This corresponds to a diagram in which the measurement lines are omitted. From the top view shown in FIG. 4(A) and the cross-sectional view shown in FIG. 4(B), As can be seen, by using a thin film transistor having an oxide semiconductor layer, the pixel electrode 10 5, that is, the aperture ratio can be improved. As can be seen from the graph, the use of a thin film transistor having an oxide semiconductor layer reduces the capacitance line and the area occupied by the pixel electrode 105 can be increased, i.e., the aperture The rate can be improved.

[0085] As in this embodiment, when a highly purified oxide semiconductor layer is used, the off-state current is extremely small. By applying a small thin film transistor to the pixel section, the pixel can be displayed without providing a storage capacitor in the pixel section. It is possible to provide a display device capable of displaying images (especially moving images). Even if the voltage is high, the storage capacitor can hold the voltage for a long period of time, making it possible to display still images, etc. It is possible to provide a display device with reduced power consumption. A display device having a high-definition display portion can be provided.

[0086] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0087] (Embodiment 2) This embodiment shows an example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 410 described in this embodiment is the same as the thin film transistor 10 described in Embodiment 1. It can be used as 6.

[0088] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment is shown in FIGS. This will be explained using Figure 6.

[0089] 5(A) and (B) show an example of the top view and cross-sectional structure of a thin film transistor. The thin film transistor 410 shown in FIG. 1 is a thin film transistor with a top gate structure. .

[0090] FIG. 5A is a top view of a thin film transistor 410 having a top gate structure, and FIG. FIG. 6 is a cross-sectional view taken along line C1-C2 in FIG. 5(A).

[0091] The thin film transistor 410 is formed on a substrate 400 having an insulating surface, an insulating layer 407, an oxide semiconductor The conductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer the source electrode layer 415b, the gate insulating layer 402, and the gate electrode layer 411; The drain electrode layer 415a and the source or drain electrode layer 415b are connected to the wiring layer 4 14a and a wiring layer 414b are provided in contact with each other and are electrically connected.

[0092] The thin film transistor 410 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0093] 6A to 6E, a thin film transistor 410 is fabricated on a substrate 400. The process will be explained.

[0094] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0095] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0096] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, a substrate made of crystallized glass may also be used. A plastic substrate or the like can also be used as appropriate.

[0097] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The insulating layer 407 in contact with the conductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or the like. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The method for forming the film 07 can be a plasma CVD method, a sputtering method, or the like. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the sputtering method is used. It is preferable to deposit the insulating layer 407 by using a silicon dioxide film.

[0098] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A target of silicon semiconductor is introduced and an insulating layer 407 is formed on the substrate 400. The substrate 400 may be at room temperature or may be heated. .

[0099] For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the distance between the substrate and the target is 108° C. The distance between the two (TS distance) was 60 mm, the pressure was 0.4 Pa, the high frequency power supply was 1.5 kW, and oxygen and and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere. A silicon oxide film is formed by F sputtering. The film thickness is 100 nm. Instead of quartz (preferably synthetic quartz) as a target for forming a silicon oxide film, A silicon target can be used as the sputtering gas. and argon gas mixture.

[0100] In this case, it is preferable to form the insulating layer 407 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0101] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 Since compounds containing hydrogen atoms such as O are exhausted, the insulating film formed in the processing chamber is The concentration of impurities contained in the edge layer 407 can be reduced.

[0102] The insulating layer 407 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. High-purity gas is used in which impurities have been removed to a concentration of ppm, preferably ppb. It is desirable that

[0103] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and direct sputtering. DC sputtering using a current source, and pulsed DC sputtering using a pulsed bias. RF sputtering is mainly used to form insulating films. The DC sputtering method is mainly used when forming metal films.

[0104] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0105] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0106] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0107] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 400 side. nitride insulation such as silicon oxide, aluminum nitride, or aluminum oxide nitride layers; The insulating layer may have a stacked structure of the insulating layer and the oxide insulating layer.

[0108] For example, a spat containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A silicon nitride layer is formed by introducing a target gas and using a silicon target. Even if the silicon nitride layer is formed, the remaining moisture in the processing chamber is removed, just like the silicon oxide layer. It is preferable to coat the surface.

[0109] When forming a silicon nitride layer, the substrate may also be heated during film formation.

[0110] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. First, nitrogen-containing gas is introduced into the processing chamber, and the silicon target is heated. A silicon nitride layer is formed using a gas containing oxygen, and then the same silicon target is grown. The silicon oxide layer is formed using a nozzle. The silicon nitride layer and the silicon oxide layer are exposed to the atmosphere. Since it can be formed continuously without exposure, there is no risk of impurities such as hydrogen or moisture on the silicon nitride layer surface. This can prevent the adsorption of impurities.

[0111] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the insulating layer 407. .

[0112] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, a substrate on which an insulating layer 407 is formed in a preheating chamber of a sputtering device The substrate 400 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 400 are desorbed and exhausted. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. This preheating process can be omitted. This may be performed on the substrate 400 before the insulating layer 402 is formed, or after the source electrode layer or the drain electrode layer is formed later. The substrate 4 is formed with the drain electrode layer 415a and the source or drain electrode layer 415b. You can do the same for 00.

[0113] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using a high frequency power supply under atmospheric pressure to form plasma near the substrate and This is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of the argon atmosphere. Good too.

[0114] The oxide semiconductor film is formed by sputtering. nO-based non-single crystal film, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga- Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, I n-Sn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn In this embodiment, the oxide semiconductor film is an In-Ga-Z The film is formed by sputtering using a target for forming an nO-based oxide semiconductor film. The oxide semiconductor film is formed under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. It is formed by sputtering in an atmosphere of nitrogen (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is preferably contained in an amount of 2% by weight to 10% by weight. The film may be formed using a target containing the following:

[0115] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0116] The oxide semiconductor film was prepared by sputtering using a target containing zinc oxide as the main component. A metal oxide target can be used. Another example is a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: As the molar ratio, In2O3:Ga2O3:ZnO=1:1:1, In:Ga:Zn =1:1:0.5 [atomic ratio]). In, Ga, and As a target for forming oxide semiconductor films containing Zn, In:Ga:Zn=1:1:1 [at or In:Ga:Zn=1:1:2 [atomic ratio] A target can also be used. The filling rate of the target for oxide semiconductor film formation is 90% or more. The filling rate is 100% or less, preferably 95% or more and 99.9% or less. By using a film formation target, the formed oxide semiconductor film becomes a dense film.

[0117] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the metal oxide as a target. An oxide semiconductor film is formed on the substrate 400 as a result of the treatment. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump It is preferable to use a pump or a titanium sublimation pump. A turbo pump with a cold trap may also be used. The evacuated processing chamber contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor film formed in the processing chamber is exhausted, the oxide semiconductor film is preferably exhausted. The concentration of impurities contained in the conductive film can be reduced. You may do so.

[0118] An example of the film formation conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions are as follows: argon flow rate 30 sccm; pulsed direct current (DC ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm or more and 30 nm or more in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately depending on the application.

[0119] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer 4 In order to form the island-shaped oxide semiconductor layer 412, The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the PET method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0120] The etching of the oxide semiconductor film here can be performed by either dry etching or wet etching. Either one or both may be used.

[0121] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0122] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur or the like can be used.

[0123] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0124] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0125] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0126] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0127] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by etching.

[0128] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer, resulting in an oxide semiconductor layer. Therefore, the oxide semiconductor layer 412 can be dehydrated or dehydrogenated.

[0129] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0130] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0131] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0132] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the crystallinity is high. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. In some cases, it becomes a conductive film. In addition, microcrystalline parts (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where an oxide semiconductor film having a thickness of 20 nm or less (typically, 2 nm or more and 4 nm or less) is formed, There are also cases where this is the case.

[0133] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0134] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the film formation, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, and then the source electrode and After forming the gate insulating layer on the drain electrode, the insulating layer may be formed.

[0135] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film can be formed by a galvanizing method or a vacuum deposition method. , Ta, Ti, Mo, W, or an alloy containing the above elements as components, or Examples include alloy films that combine the elements mentioned above. The material may be selected from one or more of thorium, beryllium, and thorium. The conductive film may have a single layer structure or a stacked structure of two or more layers. Single layer structure of aluminum film containing corn, and two layer structure of titanium film laminated on aluminum film A Ti film is laminated on top of the aluminum film, and a Ti film is then formed on top of that. In addition, titanium (Ti), tantalum (Ta), Tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium A film of a single or multiple combinations of elements selected from the group consisting of Cr, ... A film containing fluorine may also be used.

[0136] A resist mask is formed on the conductive film by a second photolithography process, and selective etching is performed. The source or drain electrode layer 415a is then After the electrode layer 415b is formed, the resist mask is removed (see FIG. 6(B)). When the ends of the formed source electrode layer and drain electrode layer are tapered, the gate electrode layer stacked thereon can be easily formed. This is preferable because it improves the coverage of the insulating layer.

[0137] In this embodiment, the source or drain electrode layer 415a As the electrode layer 415b, a titanium film having a thickness of 150 nm is formed by sputtering.

[0138] Note that the oxide semiconductor layer 412 is removed during etching of the conductive film. The respective materials and etching conditions are selected so that the insulating layer 407 underneath is not exposed. Adjust as appropriate.

[0139] In this embodiment, a Ti film is used as the conductive film, and an In—Ga -Zn-O based oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as an etchant. The mixture used was hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2.

[0140] Note that in the second photolithography step, only a part of the oxide semiconductor layer 412 is etched. In some cases, the oxide semiconductor layer has a groove (depression). The drain electrode layer 415a and the source or drain electrode layer 415b are formed by The resist mask may be formed by an ink-jet method. When the film is formed by this method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0141] The exposure to light when forming the resist mask in the second photolithography process is done using ultraviolet light or KrF laser. The source electrode layers adjacent to each other on the oxide semiconductor layer 412 are exposed to the laser beam or ArF laser beam. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the second photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0142] Next, the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 415 a) A gate insulating layer 402 is formed over the source or drain electrode layer 415b (FIG. 6 See (C). ).

[0143] Here, the oxide semiconductor (high-temperature) that has been made i-type or substantially i-type by removing impurities is Since the gate electrode (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating film and the highly purified oxide semiconductor is important. The velum (GI) is required to be of high quality.

[0144] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state density is reduced and the interface characteristics are improved. Because it is possible.

[0145] In addition, the insulating film obtained by the high density plasma CVD device can be formed with a consistent thickness. In addition, the insulating film obtained by the high density plasma CVD equipment can precisely control the thickness of thin films.

[0146] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. Even if the insulating film is one in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by In any case, it is important that the quality of the gate insulating film is good, and that the oxidation Any material may be used as long as it can reduce the interface state density with the compound semiconductor and form a good interface.

[0147] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth). Therefore, the present invention aims to remove impurities, particularly hydrogen and water, from the oxide semiconductor as much as possible, and to provide a gate electrode as described above. By improving the interface characteristics with the gate insulating film, a thin film transistor that is stable even in BT tests is obtained. This allows you to obtain a gista.

[0148] The gate insulating layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer.

[0149] The gate insulating layer is formed using a high-density plasma CVD apparatus. The CVD equipment is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of 1000kJ / s or more. For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is The film is formed as follows.

[0150] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and insulating materials such as glass are An insulating film is formed on a substrate having a surface. After that, the supply of monosilane gas is stopped and the substrate is exposed to the atmosphere. Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and rare gases without exposing it to heat. It may be performed on the surface of the insulating film by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is carried out after the insulating film is formed. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0151] The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is The ratio of the rare gas introduced into the chamber is in the range of 1:10 to 1:200. Helium, argon, krypton, xenon, etc. can be used, but among them, It is preferred to use argon.

[0152] The insulating film obtained through the above process sequence is different from the insulating film obtained using a conventional parallel plate PCVD device. The etching rates are significantly different when the same etchant is used. The insulating film obtained by the parallel plate PCVD equipment is 10% or more or 20% slower and more highly The insulating film obtained using a high-density plasma CVD apparatus can be said to be a dense film.

[0153] In this embodiment, a silicon oxynitride film (SiO ) having a thickness of 100 nm is used as the gate insulating layer 402. The gate insulating layer 402 is also called xNy, where x>y>0. The CVD equipment was supplied with monosilane (SiH4), nitrous oxide (N2O), and argon as deposition gases. Argon (Ar) was used, and the flow rates of each were SiH4 / N2O / Ar = 250 / 2500 / 2500 (sccm), deposition pressure 30 Pa, deposition temperature 325 °C, 5 kW microphone A microwave power is applied to generate plasma, and a film is formed.

[0154] Alternatively, the gate insulating layer 402 may be formed by a sputtering method. When forming a silicon oxide film, a silicon target or a quartz target is used as the target. The sputtering was performed using oxygen or a mixture of oxygen and argon as the sputtering gas. When a sputtering method is used, the gate insulating layer 402 does not contain a large amount of hydrogen. can.

[0155] The gate insulating layer 402 is provided with a source or drain electrode layer 415a, a source electrode layer 415b, a drain electrode layer 415c, a gate insulating layer 402d, and a gate insulating layer 402e. Alternatively, a silicon oxide layer and a silicon nitride layer may be stacked from the drain electrode layer 415b side. For example, the first gate insulating layer may be an oxide film having a thickness of 5 nm to 300 nm. Silicon oxide layer (SiO x (x>0) and forming a second gate insulating layer on the first gate insulating layer. As the edge layer, a silicon nitride layer ( SiN y (y>0)) may be laminated. For example, the pressure is 0.4 Pa, and the high frequency power is 1.5 kJ. W, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere A silicon oxide layer with a thickness of 100 nm can be formed by RF sputtering under atmospheric conditions.

[0156] Next, a resist mask is formed by a third photolithography process and selectively etched. The source electrode layer or the drain electrode layer 402 is removed by etching. 15a, openings 421a and 421b reaching the source electrode layer or the drain electrode layer 415b are formed. (See Figure 6(D)).

[0157] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. A gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process. The resist mask may be formed by an ink-jet method. When formed by the ink jet method, no photomask is used, which reduces manufacturing costs.

[0158] The gate electrode layer 411 and the wiring layers 414a and 414b are made of molybdenum, titanium, Metals such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a laminated layer using a material or an alloy material containing these as the main component. Cut.

[0159] For example, a two-layer laminate structure of a gate electrode layer 411 and wiring layers 414a and 414b may be Two-layer laminate structure with a molybdenum layer on an aluminum layer, or molybdenum on a copper layer Two-layer structure with a layer stacked on top of a copper layer, or a titanium nitride layer or tantalum nitride layer stacked on top of a copper layer A two-layer structure, preferably a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated, is used. The layer stack structure is composed of a tungsten layer or tungsten nitride layer, and a layer of aluminum and silicon. A titanium nitride layer or titanium alloy layer is laminated on the aluminum and titanium alloy. It is preferable that the gate electrode layer be formed using a light-transmitting conductive film. Examples of the conductive film having light-transmitting properties include a light-transmitting conductive oxide. It can be done.

[0160] In this embodiment, the gate electrode layer 411 and the wiring layers 414a and 414b are formed by sputtering. A titanium film having a thickness of 150 nm is formed by the method.

[0161] Next, a second heat treatment (preferably 2 In this embodiment, the heating temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 410 .

[0162] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heating under reduced pressure can shorten the heating time.

[0163] Through the above steps, the oxide semiconductor layer 41 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2 can be formed (see FIG. 6(E)). The transistor 410 can be used as the thin film transistor 106 in Embodiment 1. can be done.

[0164] In addition, a protective insulating layer and a planarizing insulating layer for planarization are provided over the thin film transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like may be used as the protective insulating layer. A silicon nitride oxide layer, a silicon nitride oxide layer, or an aluminum oxide layer may be formed as a single layer or a stacked layer. can.

[0165] The planarization insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphor glass), BP SG (phosphorus boron glass) can be used. A planarizing insulating layer may be formed by stacking a plurality of insulating films.

[0166] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0167] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, an SOG method, or the like depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0168] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0169] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0170] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0171] (Embodiment 3) This embodiment shows an example of a thin film transistor that can be applied to the display device disclosed in this specification. Note that the same parts as those in the second embodiment or parts and steps having similar functions are the same as those in the second embodiment. 2, and the repeated explanation will be omitted. The thin film transistor 460 described in this embodiment is the same as the thin film transistor of Embodiment 1. It can be used as the controller 106.

[0172] One mode of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment is shown in FIGS. This will be explained using FIG.

[0173] 7(A) and (B) show an example of the top and cross-sectional structure of a thin film transistor. The thin film transistor 460 shown in FIG. 1 is a top-gate thin film transistor. .

[0174] FIG. 7A is a top view of a thin film transistor 460 having a top gate structure, and FIG. FIG. 8 is a cross-sectional view taken along line D1-D2 in FIG. 7(A).

[0175] The thin film transistor 460 is formed by forming an insulating layer 457, a source electrode 458, a gate electrode 459, a gate electrode 459a, a gate electrode 459b, a gate electrode 459c, a gate electrode 459d, a gate electrode 459e, a gate electrode 459f, a gate electrode 459g ... a drain or electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, the source or drain electrode layer 465b, the wiring layer 468, the gate insulating layer 452, and the gate The electrode layer 461 (461a, 461b) includes a source electrode layer or a drain electrode layer 465a. (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also formed as a gate insulating layer. An opening provided in 452 electrically connects to the wiring layer.

[0176] 8A to 8E, a thin film transistor 460 is fabricated on a substrate 450. The process will be explained.

[0177] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0178] In this embodiment, a silicon oxide layer is formed as the insulating layer 457 by a sputtering method. The substrate 450 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A target gas is introduced, and a silicon target or quartz (preferably synthetic quartz) is used to form a substrate 45 A silicon oxide layer is formed on the insulating layer 457. is carried out using a mixed gas of oxygen and argon.

[0179] For example, the purity is 6N, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the substrate The distance between the plate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high frequency power 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1 1) A silicon oxide film is formed by RF sputtering in a 100 MPa atmosphere. The target for forming the silicon oxide film is quartz (preferably A silicon target can be used instead of a target made of synthetic quartz.

[0180] In this case, it is preferable to form the insulating layer 457 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl groups, or moisture. The processing chamber evacuated using a pump contains, for example, hydrogen atoms and water (H2O) Since compounds containing fluorine atoms are exhausted, the compounds formed in the processing chamber and contained in the insulating layer 457 This can reduce the concentration of impurities.

[0181] The insulating layer 457 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. preferable.

[0182] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 450 side. and nitride insulating layers such as silicon oxide layers, aluminum nitride layers, and aluminum oxide nitride layers. The insulating film may have a stacked structure with the oxide insulating layer.

[0183] For example, a spat containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A silicon nitride layer is formed by introducing a target gas and using a silicon target. Even if the silicon nitride layer is formed, the remaining moisture in the processing chamber is removed, just like the silicon oxide layer. It is preferable to coat the surface.

[0184] Next, a conductive film is formed on the insulating layer 457, and a conductive film is formed by a first photolithography process. A resist mask is formed on the film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After the electrode layers 465a1 and 465a2 are formed, the resist mask is removed (see FIG. 8(A)). The source and drain electrode layers 465a1 and 465a2 are separated in the cross-sectional view. Although the source electrode layer and the drain electrode layer are shown as a continuous film, they are not formed. The end of the gate insulating layer is preferably tapered to improve coverage with the gate insulating layer to be laminated thereon. stomach.

[0185] The source electrode layer or drain electrode layer 465a1, 465a2 may be made of Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements , and alloy films combining the above elements. Using one or more materials selected from zirconium, beryllium, and thorium The conductive film may have a single layer structure or a stacked structure of two or more layers. For example, Single layer structure of aluminum film containing silicon, two-layer structure of titanium film laminated on aluminum film Structure: Ti film, aluminum film layered on top of the Ti film, and Ti film on top of that In addition, titanium (Ti) and tantalum (Ta ), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), A film, alloy film, or film made of a single or multiple combinations of elements selected from candium (Sc) Alternatively, a nitride film may be used.

[0186] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method.

[0187] Next, an oxide semiconductor layer 462 is formed to a thickness of 2 nm to 200 nm.

[0188] The formed oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 4. 8B). In this embodiment, the oxide semiconductor film is formed of In- The film is formed by sputtering using a Ga-Zn-O oxide semiconductor film formation target. do.

[0189] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the metal oxide as a target. An oxide semiconductor film is formed on the substrate 450. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump It is preferable to use a pump or a titanium sublimation pump. A turbo pump with a cold trap may also be used. The evacuated processing chamber contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor film formed in the processing chamber is exhausted, the oxide semiconductor film is preferably exhausted. The concentration of impurities contained in the conductive film can be reduced. You may do so.

[0190] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0191] An example of the film formation conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, DC power 0.5 kW, oxygen and argon (oxygen flow rate 15 scc The conditions are as follows: argon flow rate 30 sccm; pulsed direct current (DC ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. The oxide semiconductor film is preferably 5 nm or more and 30 nm or more in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected appropriately depending on the application.

[0192] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 462 by etching.

[0193] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer, resulting in an oxide semiconductor layer. Therefore, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0194] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. For example, the first heat treatment may be performed at a temperature of 650°C to 70°C. The substrate is placed in an inert gas atmosphere heated to 0°C, and after heating for several minutes, the substrate is GRTA can also be performed by moving the sample and removing it from the inert gas heated to a high temperature. This allows high-temperature heat treatment in a short time.

[0195] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0196] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film may crystallize to form a microcrystalline or polycrystalline film.

[0197] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0198] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the film formation, a source electrode and a drain electrode are further laminated on the oxide semiconductor layer, and then the source electrode is This may be done either after forming a gate insulating layer on the gate and drain electrodes or after forming a gate insulating layer on the gate and drain electrodes.

[0199] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask The source or drain electrode layer 465b and the wiring layer 465c are removed (see FIG. 8C). The source electrode layer 68 is formed by the same material and process as the source electrode layer 465a1 and the drain electrode layer 465a2. It is sufficient to form it.

[0200] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method. and the source or drain electrode layers 465a1 and 465a2. In this example, the same titanium film is used for the source electrode layer 465a1 and the drain electrode layer 46b. The source or drain electrode layer 465b and the source or drain electrode layer 465a2 have a selectivity in etching. Therefore, the source electrode layer 465a1 and the drain electrode layer 465a2 are not connected to the source electrode The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465a. The wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0201] Note that the conductive film was etched so that the oxide semiconductor layer 462 was not removed. The material and etching conditions are adjusted appropriately.

[0202] In this embodiment, a Ti film is used as the conductive film, and an In—Ga -Zn-O based oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as an etchant. The mixture used was hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2.

[0203] Note that in the third photolithography step, only a part of the oxide semiconductor layer 462 is etched. In some cases, the oxide semiconductor layer has a groove (depression). A resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional materials are used, the manufacturing cost can be reduced.

[0204] Next, the insulating layer 457, the oxide semiconductor layer 462, the source or drain electrode layer 465 a1, 465a2, and a gate insulating layer 452 on the source or drain electrode layer 465b. Form.

[0205] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 452 can be formed as a single layer or a stacked layer. In order to prevent a large amount of ZnO from being contained, the gate insulating layer 452 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen or The process is carried out using a mixed gas of oxygen and argon.

[0206] The gate insulating layer 452 is provided between the source and drain electrode layers 465a1 and 465a2, A silicon oxide layer and a silicon nitride layer were stacked on the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, the high frequency power supply is 1.5 kW, Oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed on the substrate by RF sputtering.

[0207] Next, a resist mask is formed by a fourth photolithography process and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 reaching the wiring layer 468. Although not shown, when the opening 423 is formed, the source electrode layer or the drain electrode layer is formed. An opening may be formed that reaches the drain electrode layer 465b. Alternatively, the opening to the drain electrode layer 465b is formed after an interlayer insulating layer is further laminated. In this example, a wiring layer connected to the wiring layer is formed in the opening.

[0208] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a photolithography process. The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs.

[0209] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium It is formed by using a metal material such as aluminum or an alloy material containing these as the main component, in a single layer or in a laminated form. It is possible.

[0210] In this embodiment, gate electrode layer 461 (461a, 461b) and wiring layer 464 are formed of silicon dioxide. A titanium film having a thickness of 150 nm is formed by a tartering method.

[0211] Next, a second heat treatment (preferably 2 In this embodiment, the heating temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 460 .

[0212] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heating under reduced pressure can shorten the heating time.

[0213] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2 can be formed (see FIG. 8E). The transistor 460 is a thin film transistor used in each pixel of the pixel portion 202 in Embodiment 1. It can be used for.

[0214] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, the source insulating layer 452, the protective insulating layer, and the planarizing insulating layer may be formed. An opening reaching the source or drain electrode layer 465b is formed in the opening. A wiring layer electrically connected to the drain electrode layer 465b is formed.

[0215] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0216] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0217] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0218] (Fourth embodiment) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. Note that the same parts as those in the second embodiment or parts and steps having similar functions are shown in the second embodiment. The same as in the second embodiment may be applied, and the repeated explanation will be omitted. The thin film transistors 425 and 426 described in this embodiment are the same as those in Embodiment 1. It can be used as a film transistor 106.

[0219] The thin film transistor of this embodiment will be described with reference to FIG.

[0220] 9(A) and 9(B) show an example of a cross-sectional structure of a thin film transistor. The thin film transistors 425 and 426 each have an oxide semiconductor layer sandwiched between a conductive layer and a gate electrode layer. It is one of the thin film transistors with this structure.

[0221] 9(A) and 9(B), a silicon substrate is used as the substrate, and the silicon substrate 42 Thin film transistors 425 and 426 are provided on an insulating layer 422 provided on the substrate 400. are.

[0222] In FIG. 9A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 so as to overlap with at least the entire oxide semiconductor layer 412. .

[0223] 9B, the conductive layer between the insulating layer 422 and the insulating layer 407 is a conductive layer such as the conductive layer 424. The oxide semiconductor layer 412 is processed by etching as shown in FIG. This is an example of partial overlap.

[0224] The conductive layers 427 and 424 may be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), An element selected from Cr, Nd, and Sc, or any of the above an alloy containing the above elements as a component, an alloy film containing a combination of the above elements, or an alloy film containing the above elements as a component The nitride may have a single layer structure or a laminated structure. For example, a single tungsten layer or a laminated structure of a tungsten nitride layer and a tungsten layer. can be used.

[0225] The conductive layers 427 and 424 are connected to the gate electrode layers of the thin film transistors 425 and 426. It may be the same as or different from 411 and may function as a second gate electrode layer. Alternatively, the potentials of the conductive layers 427 and 424 may be fixed potentials such as GND and 0V. Good too.

[0226] The conductive layers 427 and 424 control the electrical characteristics of the thin film transistors 425 and 426. It is possible.

[0227] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0228] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0229] (Embodiment 5) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 390 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0230] An example of a cross-sectional structure of the thin film transistor of this embodiment is shown in FIGS. The thin film transistor 390 shown in Figures 10(A) to 10(E) is one of bottom gate structures. It is also called an inverted staggered thin film transistor.

[0231] The thin film transistor 390 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0232] 10(A) to 10(E), a thin film transistor 390 is fabricated on a substrate 394. The process will be explained.

[0233] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography A gate electrode layer 391 is formed by this process. The end of the gate electrode layer is tapered. This is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0234] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0235] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0236] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, a substrate made of crystallized glass may also be used. A plastic substrate or the like can also be used as appropriate.

[0237] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. , which has the function of preventing the diffusion of impurity elements from the substrate 394, and the silicon nitride film, silicon oxide film, The insulating film is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by a laminated structure.

[0238] The material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0239] For example, the gate electrode layer 391 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer structure with a molybdenum layer on a copper layer, two-layer structure with a nitride layer on a copper layer Two-layer structure consisting of a titanium nitride layer or a tantalum nitride layer, a titanium nitride layer and a molybdenum layer or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated. The three-layer laminate structure is preferably a tungsten layer or a tungsten nitride layer. layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride It is preferable that the conductive film has a stack of a titanium layer and a silicon layer. The gate electrode layer can also be formed using a light-transmitting conductive film. An example of such a material is a conductive oxide.

[0240] Next, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0241] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer 397 can be formed as a single layer or a stacked layer. In order to prevent a large amount of silicon from being contained, the gate insulating layer 397 is formed by sputtering. When forming a silicon oxide film by sputtering, it is preferable to A silicon target or a quartz target is used as the sputtering target, and oxygen or The process is carried out using a mixed gas of oxygen and argon.

[0242] The gate insulating layer 397 is formed by stacking a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, a layered structure can be formed by sputtering as the first gate insulating layer. A silicon nitride layer (SiN) with a thickness of 50 nm or more and 200 nm or less is formed. y (y>0) On the first gate insulating layer, an oxide film having a thickness of 5 nm to 300 nm is formed as a second gate insulating layer. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. .

[0243] In addition, the gate insulating layer 397 and the oxide semiconductor film 393 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent this, a gate electrode is placed in the preheating chamber of the sputtering equipment as a pretreatment for film formation. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which up to a gate insulating layer 397 is formed The plate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is between 150 and 300°C. The exhaust means installed in the preheating chamber is a cryopump. It is preferable that the preheating step is omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b are The same may be done to the formed substrate 394.

[0244] Next, an oxide semiconductor film 39 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. 3 is formed (see FIG. 10(A)).

[0245] Note that before the oxide semiconductor film 393 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 397 to generate plasma. It is preferable to remove the dust particles that are sputtered. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of argon atmosphere. Either may be used.

[0246] The oxide semiconductor film 393 is formed by a sputtering method. n-Ga-Zn-O non-single crystal film, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-S nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn In this embodiment, the oxide semiconductor film 39 is a Zn—O-based or Zn—O-based oxide semiconductor film. 3 was deposited by sputtering using an In-Ga-Zn-O oxide semiconductor film deposition target. The oxide semiconductor film 393 is formed by annealing under a rare gas (typically, argon) atmosphere. , or in an atmosphere of rare gas (typically argon) and oxygen. When the sputtering method is used, the SiO2 The film may be formed using a target containing 2% by weight or more and 10% by weight or less.

[0247] Zinc oxide was used as a target for forming the oxide semiconductor film 393 by a sputtering method. A metal oxide target containing the metal oxide as the main component can be used. Another example of the target is a target for forming an oxide semiconductor film containing In, Ga, and Zn ( The composition ratio was In2O3:Ga2O3:ZnO=1:1:1 [molar ratio], In:Ga Zn=1:1:0.5 [atomic ratio]) can be used. and as a target for forming an oxide semiconductor film containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or In:Ga:Zn=1:1:2 [atomic ratio] composition ratio A target having a filling factor of 90% can also be used for forming an oxide semiconductor film. % or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for semiconductor film formation, the oxide semiconductor film formed becomes a dense film. .

[0248] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to room temperature or a temperature below 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering gas from which hydrogen and moisture have been removed is heated. A gas is introduced, and an oxide semiconductor film 393 is formed on a substrate 394 using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps are used. It is preferable that the exhaust means be a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) such as HO are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the treatment chamber can be reduced. In addition, sputtering is performed while removing residual moisture from the processing chamber using a cryopump. Therefore, the substrate temperature when the oxide semiconductor film 393 is formed is set to room temperature or lower than 400° C. It is possible.

[0249] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust (also called crumbs or dust) and make the film thickness distribution uniform. The thickness of the film is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material.

[0250] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and DC sputtering. DC sputtering using a power supply, and pulsed DC sputtering using a pulsed bias. The RF sputtering method is mainly used to form insulating films, and The C sputtering method is mainly used to form metal films.

[0251] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0252] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0253] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0254] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 3 10B). In addition, an island-shaped oxide semiconductor layer 399 is formed. A resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0255] In addition, when a contact hole is formed in the gate insulating layer 397, the process is performed using an oxide semiconductor This can be done when layer 399 is formed.

[0256] Note that the etching of the oxide semiconductor film 393 here can be performed by dry etching or wet etching. Alternatively, either etching or both may be used.

[0257] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0258] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur or the like can be used.

[0259] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0260] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0261] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0262] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0263] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate electrode 396 are formed. It is preferable to remove resist residues and the like adhering to the surface of the insulating layer 397.

[0264] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum deposition. An element selected from the group consisting of r, Cu, Ta, Ti, Mo, and W, or a composite containing the above elements. Examples of the metal include gold and alloy films made of a combination of the above elements. a material selected from one or more of aluminum, zirconium, beryllium, and thorium; The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: Ti film, aluminum film on top of the Ti film, and T In addition, titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , scandium (Sc), or a film or alloy film made of a single or multiple combinations of elements selected from the group consisting of Alternatively, a nitride film may be used.

[0265] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 395a and the drain electrode layer 395b by etching, a resist The mask is removed (see FIG. 10(C)).

[0266] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer is formed on the oxide semiconductor layer 399. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0267] Note that the conductive film was etched so that the oxide semiconductor layer 399 was not removed. The material and etching conditions are adjusted appropriately.

[0268] In this embodiment, a Ti film is used as the conductive film, and an In—Ga -Zn-O based oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as an etchant. The mixture used was hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2.

[0269] Note that in the third photolithography step, only a part of the oxide semiconductor layer 399 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 95a, a resist mask for forming the drain electrode layer 395b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0270] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0271] Exposed oxides by plasma treatment with gases such as N2O, N2, or Ar It is also possible to remove adsorbed water and other substances adhering to the surface of the semiconductor layer. Plasma treatment may be performed using a gas.

[0272] When plasma treatment is performed, a protective film that is in contact with a part of the oxide semiconductor layer is formed without being exposed to the air. An oxide insulating layer 396 is formed as an oxide insulating layer to serve as an insulating film (see FIG. 10D). In this embodiment, the oxide semiconductor layer 399 is formed between the source electrode layer 395a and the drain electrode layer 395b. In a region where the oxide semiconductor layer 399 does not overlap with the oxide insulating layer 396, It is formed so that

[0273] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source electrode The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated at room temperature or below 100°C. The sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon oxide layer containing defects is deposited using a silicon semiconductor target.

[0274] For example, a silicon target with a purity of 6N and doped with boron (resistivity 0.01 Ωcm), the distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0. 4 Pa, direct current (DC) power supply 6 kW, pulse DC in oxygen (oxygen flow rate 100%) atmosphere A silicon oxide film is formed by sputtering. The film thickness is 300 nm. As a target for forming a silicon nitride film, a quartz target (preferably Preferably, synthetic quartz can be used. The sputtering gas is oxygen or oxygen and This is done using a mixed gas of argon and argon.

[0275] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 399 and the oxide insulating layer 396 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0276] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., which contain hydrogen atoms, are exhausted. The impurity concentration in the oxide insulating layer 396 can be reduced.

[0277] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can also be used.

[0278] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 40° C. in a state where the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Heat treatment may be performed at 0° C. In this embodiment, the oxide insulating layer 396 has many defects. Therefore, the heat treatment reduces hydrogen, moisture, and hydroxyl groups contained in the oxide semiconductor layer 399. Alternatively, impurities such as hydride are diffused into the oxide insulating layer 396 to form a layer in the oxide semiconductor layer 399. The impurities contained therein can be further reduced.

[0279] Through the above steps, the oxide semiconductor layer 39 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced is formed. 2, a thin film transistor 390 having the same structure as in FIG. 10(E) can be formed.

[0280] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0281] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is formed by an oxide insulating film. The protective insulating layer 398 is formed on the oxide insulating layer 396. The protective insulating layer 398 may be a silicon nitride film, a nitride oxide film, or the like. A silicon film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0282] The substrate 394 on which the oxide insulating layer 396 has been formed is heated at 100°C to 4 The temperature was raised to 00°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture had been removed was introduced. In this case, a silicon nitride film is formed using a silicon semiconductor target. Similarly to the oxide insulating layer 396, a protective insulating layer 398 is formed while removing residual moisture in the treatment chamber. It is preferable to coat the surface.

[0283] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the formation of the protective insulating layer 398. By heating the plate 394, hydrogen or moisture contained in the oxide semiconductor layer is oxidized to form an oxide insulating film. In this case, a heat treatment is performed after the oxide insulating layer 396 is formed. You don't have to.

[0284] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and silicon nitride layer are processed in the same processing chamber using a common silicon nitride layer. A silicon target can be used for film formation. First, a gas containing oxygen is introduced, and then the process is A silicon oxide layer is formed using a silicon target mounted in the chamber, followed by a nitrogen-containing layer. The gas is switched to the silicon nitride layer using the same silicon target. The silicon layer and silicon nitride layer can be formed successively without exposure to the atmosphere, so oxidation This can prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the silicon layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396 and a nitride layer is formed as the protective insulating layer 398. After the silicon layer is stacked, hydrogen or moisture contained in the oxide semiconductor layer is removed by an oxide insulating layer. It is preferable to perform a heat treatment (at a temperature of 100° C. to 400° C.) to diffuse the metal into the silicon dioxide.

[0285] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. In addition, the temperature rises from room temperature to a heating temperature of 100°C or more and 200°C, and the temperature rises from the heating temperature to room temperature. The temperature may be lowered several times. Alternatively, the heating may be carried out under reduced pressure. When the heating treatment is carried out under reduced pressure, the heating time can be shortened. This heat treatment allows a normally-off thin film transistor to be obtained. This improves the reliability of the display device.

[0286] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, a reaction By removing residual moisture in the atmosphere, the concentrations of hydrogen and hydride in the oxide semiconductor layer are reduced. can be reduced.

[0287] The above process is carried out at temperatures below 400°C, so the thickness is less than 1mm and the length is 1m. It can also be applied to manufacturing processes that use glass substrates at temperatures above 400°C. All processes can be carried out at the same temperature, which reduces the energy required to manufacture a display panel. No need to consume ghee.

[0288] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0289] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0290] (Sixth embodiment) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 310 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0291] An example of a cross-sectional structure of the thin film transistor of this embodiment is shown in FIGS. The thin film transistor 310 shown in Figures 11(A) to 11(E) is one of bottom gate structures. It is also called an inverted staggered thin film transistor.

[0292] The thin film transistor 310 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0293] 11(A) to 11(E), a thin film transistor 310 is fabricated on a substrate 300. In FIG. 11(E), a protective insulating layer is formed on the thin film transistor 310. The formed structure is shown below.

[0294] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 311 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0295] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0296] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0297] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, crystallized glass or the like may also be used.

[0298] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. , which has the function of preventing the diffusion of impurity elements from the substrate 300, and is a silicon nitride film, a silicon oxide film, A laminated structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film It can be formed.

[0299] The material of the gate electrode layer 311 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0300] For example, the gate electrode layer 311 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer laminated structure with a molybdenum layer on a copper layer, two-layer laminated structure with a molybdenum layer on a copper layer, copper layer Two-layer laminated structure with titanium nitride layer or tantalum nitride layer on top, titanium nitride layer and molybdenum nitride layer Two-layer laminated structure consisting of a tungsten nitride layer and a tungsten layer, or two-layer laminated structure consisting of a tungsten nitride layer and a tungsten layer It is preferable to have a three-layer laminate structure. a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, It is preferable to use a laminated layer including a titanium nitride layer or a titanium layer.

[0301] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0302] The gate insulating layer 302 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer in a single layer or For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a laminate, for example, the thickness is 50 nm to 2 a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0303] In this embodiment, the gate insulating layer 302 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0304] Next, an oxide semiconductor film 33 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 302. Form 0.

[0305] Before the oxide semiconductor film 330 was formed by sputtering, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating layer 302 is removed. It is preferable to remove nitrogen, helium, oxygen, etc. instead of argon atmosphere. It may be used.

[0306] The oxide semiconductor film 330 is an In—Ga—Zn—O based non-single crystal film, an In—Sn—Zn—O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O system, In-Sn-O system, In-Zn-O system, Sn-Zn-O system, Al-Z In—O-based, In—O-based, Sn—O-based, and Zn—O-based oxide semiconductor films are used. In this embodiment, the oxide semiconductor film 330 is formed on a target for forming an In—Ga—Zn—O-based oxide semiconductor film. The cross section at this stage corresponds to Figure 11(A). The oxide semiconductor film 330 is grown in a rare gas (typically, argon) atmosphere and an oxygen atmosphere. Formed by sputtering under an atmosphere of rare gas (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is preferably contained in an amount of 2% by weight or more and 10% by weight or more. % by weight or less may be used for film formation.

[0307] The oxide semiconductor film 330 is formed by sputtering using zinc oxide as a target. A metal oxide target containing the metal oxide as the main component can be used. Another example of the target is a target for forming an oxide semiconductor film containing In, Ga, and Zn ( The composition ratio was In2O3:Ga2O3:ZnO=1:1:1 [molar ratio], In:Ga Zn=1:1:0.5 [atomic ratio]) can be used. and as a target for forming an oxide semiconductor film containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or In:Ga:Zn=1:1:2 [atomic ratio] composition ratio A target having a filling factor of 90% can also be used for forming an oxide semiconductor film. % or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for semiconductor film formation, the oxide semiconductor film formed becomes a dense film. .

[0308] The oxide semiconductor film 330 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. High-purity gas is used, in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0309] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is preferably maintained at 100°C or more and 600°C or less. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by heating is reduced. The removed sputtering gas is introduced, and a metal oxide is used as a target to deposit a layer on the gate insulating layer 302. In order to remove residual moisture in the treatment chamber, an adsorption-type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a displacement pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the cryopump. The chamber may contain, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (HO), etc. (more preferably, carbon Since the oxide semiconductor film formed in the treatment chamber is exhausted, the oxide semiconductor film is not included in the treatment chamber. This reduces the concentration of impurities.

[0310] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particles) generated during film formation are This is preferable because it can reduce the amount of dust (also called crumbs or dust) and make the film thickness distribution uniform. The thickness of the film is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material.

[0311] Next, the oxide semiconductor film 330 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0312] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature is set to 750° C. or higher, preferably 400° C. or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the processing equipment, and the oxide semiconductor layer was heated to 450 K under a nitrogen atmosphere. After heat treatment at 20°C for 1 hour, the oxide semiconductor layer was dehydrated without being exposed to the air. The oxide semiconductor layer 331 is obtained by preventing re-entry of oxygen and hydrogen (see FIG. 11B).

[0313] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0314] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0315] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0316] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the crystallinity is high. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. In some cases, it becomes a conductive film. In addition, microcrystalline parts (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where an oxide semiconductor film having a thickness of 20 nm or less (typically, 2 nm or more and 4 nm or less) is formed, There are also cases where this is the case.

[0317] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 330 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0318] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer formation. After the film formation, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, and then the source electrode and After forming a protective insulating film on the drain electrode, the step may be performed at any time.

[0319] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. This may be done before or after the membrane 330 has been subjected to a dehydration or dehydrogenation treatment.

[0320] Note that the etching of the oxide semiconductor film here is not limited to wet etching, but may be dry etching. Etching may also be used.

[0321] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0322] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive film can be formed by sputtering or vacuum deposition. An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements, Examples include alloy films made up of the above elements. Using a material selected from one or more of zinc, beryllium, and thorium The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing silicon, and a two-layer structure of titanium film laminated on aluminum film. The structure is a Ti film, an aluminum film is layered on top of the Ti film, and a Ti film is layered on top of that. In addition, titanium (Ti) and tantalum (Ta) are added to Al. , Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc (Scandium), or a film or alloy film made of a single or multiple combinations of elements selected from A nitride film may also be used.

[0323] When a heat treatment is performed after forming the conductive film, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that:

[0324] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 315a and the drain electrode layer 315b by etching, a resist The mask is removed (see FIG. 11(C)).

[0325] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer adjacent to each other on the oxide semiconductor layer 331 is formed by laser light or ArF laser light. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0326] Note that the conductive film was etched so that the oxide semiconductor layer 331 was not removed. The material and etching conditions are adjusted appropriately.

[0327] In this embodiment, a Ti film is used as the conductive film, and an In—Ga -Zn-O based oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as an etchant. The mixture used was hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2.

[0328] Note that in the third photolithography step, only a part of the oxide semiconductor layer 331 is etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 15a, a resist mask for forming the drain electrode layer 315b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0329] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be The oxide conductive layer can function as a source region and a drain region.

[0330] The oxide conductive layer is formed as a source region and a drain region by forming an oxide semiconductor layer and a source electrode layer. By providing the source and drain electrode layers between the source and drain regions, the resistance of the source and drain regions can be reduced. This allows the transistor to operate at high speed.

[0331] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0332] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0333] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer was removed without being exposed to the air. An oxide insulating layer 316 is formed as an insulating film.

[0334] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide insulating method such as sputtering. The layer 316 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 316 . When hydrogen is contained in the oxide insulating layer 316, the hydrogen penetrates into the oxide semiconductor layer or The region where oxygen is extracted from the oxide semiconductor layer and a channel is formed in the oxide semiconductor layer is called a region where The opposite side (the so-called back channel side) becomes low resistance (N-type), and the parasitic channel Therefore, the oxide insulating layer 316 should be a film containing as little hydrogen as possible. Therefore, it is important that the deposition method does not involve the use of hydrogen.

[0335] In this embodiment, a 200-nm-thick oxide insulating layer is formed by a sputtering method as the oxide insulating layer 316. The substrate temperature during film formation is set to be between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under atmospheric pressure. The oxide insulating layer 316 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any of these substances and blocks them from entering from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0336] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0337] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 316 can be reduced.

[0338] The oxide insulating layer 316 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of ppm or ppb. It is preferable.

[0339] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A portion of the oxide layer (channel formation region) is heated in contact with the oxide insulating layer 316 .

[0340] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively treated with an oxygen-excess As a result, the channel formation region 313 overlapping with the gate electrode layer 311 becomes i-type. The high-resistance source region 314a overlaps the source electrode layer 315a, and the drain electrode layer 315 By the above process, a thin film is formed in a self-aligned manner. A transistor 310 is formed (see FIG. 11(D)).

[0341] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and therefore the reliability of the display device can be improved.

[0342] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) forming a high-resistance drain region 314b (or a high-resistance source region 314a) in This improves the reliability of the thin film transistor. By forming the drain electrode layer 315b, the high-resistance drain region 314b is 14b, a structure in which the conductivity can be changed stepwise from the first region to the channel forming region 313. Therefore, a line that supplies a high power supply potential Vdd to the drain electrode layer 315b can be provided. When the device is connected to a line, a high-voltage power supply is provided between the gate electrode layer 311 and the drain electrode layer 315b. Even when voltage is applied, the high-resistance drain region acts as a buffer, making it difficult for localized electric field concentration to occur. In this case, the withstand voltage of the transistor can be improved.

[0343] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably formed of an oxide semiconductor. When the oxide layer is thin, 15 nm or less, it is formed throughout the entire thickness direction. When the thickness of the conductor layer is thicker, between 30 nm and 50 nm, a part of the oxide semiconductor layer, The resistance of the region in contact with the source electrode layer or the drain electrode layer and its vicinity is reduced, forming a high-resistance source region. Alternatively, a high-resistance drain region is formed, and the region of the oxide semiconductor layer close to the gate insulating film is It can also be an i-type.

[0344] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, a protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. This is a preferred method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films, An aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film. (See Figure 11(E)).

[0345] In this embodiment, the protective insulating layer 303 is formed on the substrate 3 up to the oxide insulating layer 316. 00 is heated to a temperature of 100℃ to 400℃, and high-purity nitrogen from which hydrogen and moisture have been removed is obtained. A sputtering gas is introduced and a silicon nitride film is formed using a silicon semiconductor target. In this case, similarly to the oxide insulating layer 316, the remaining moisture in the treatment chamber is removed and the treatment chamber is maintained. A protective insulating layer 303 is preferably deposited.

[0346] A planarization insulating layer for planarization may be provided over the protective insulating layer 303.

[0347] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0348] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0349] (Embodiment 7) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 360 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0350] An example of a cross-sectional structure of the thin film transistor of this embodiment is shown in FIGS. The thin film transistor 360 shown in 12(A) to 12(D) is a channel protection type (channel strip type). It is one of the bottom-gate structures known as inverted staggered thin-film transistors (also known as top-gate thin-film transistors). It is also called.

[0351] The thin film transistor 360 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0352] 12(A) to 12(D), a thin film transistor 360 is fabricated on a substrate 320. The process will be explained.

[0353] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 361 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0354] The material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0355] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0356] In this embodiment, the gate insulating layer 322 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0357] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer by a second photolithography process. In terms of form, it is a target for forming an In-Ga-Zn-O-based oxide semiconductor film as an oxide semiconductor film. The film is formed by sputtering using the above.

[0358] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0359] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0360] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0361] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor The layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. This prevents water and hydrogen from re-entering the oxide semiconductor layer, thereby obtaining the oxide semiconductor layer 332. See Figure 12(A).

[0362] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0363] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0364] In this embodiment, the oxide insulating layer 366 is formed by a sputtering method using an oxide film having a thickness of 200 nm. The substrate temperature during film formation is set to be between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under atmospheric pressure. The oxide insulating layer 366 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any of these substances and blocks them from entering from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0365] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0366] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 366 can be reduced.

[0367] The oxide insulating layer 366 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of ppm or ppb. It is preferable.

[0368] Next, a second heat treatment (preferably 2 For example, the heating may be performed at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. A second heat treatment is carried out at 250°C for 1 hour in a nitrogen atmosphere. A part of the oxide semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 366. do.

[0369] In this embodiment, an oxide insulating layer 366 is further provided and a part of the oxide semiconductor is exposed. The oxide insulating layer 332 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed regions of the oxide semiconductor layer 332 that are not covered by 66 are filled with nitrogen, an inert gas, Heat treatment under a nitrogen atmosphere or reduced pressure can lower the resistance. Heat treatment is carried out in an atmosphere at 250°C for 1 hour.

[0370] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 332 provided with the oxide insulating layer 366 As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 12( In Fig. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and white areas.

[0371] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process. After selectively etching the silicon dioxide film to form the source electrode layer 365a and the drain electrode layer 365b, The resist mask is removed (see FIG. 12(C)).

[0372] The source electrode layer 365a and the drain electrode layer 365b may be made of Al, Cr, Cu, or T. An element selected from the group consisting of a, Ti, Mo, and W, or an alloy containing the above elements, or Examples include alloy films that combine elements of different materials. Conductive films can have a single layer structure or two or more layers. The laminated structure may be formed as follows.

[0373] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively treated with an oxygen-excess As a result, the channel formation region 363 overlapping with the oxide insulating layer 366 becomes an i-type The high-resistance source region 364a overlaps the source electrode layer 365a, and the drain electrode layer 36 By the above steps, a thin film is formed on the high-resistance drain region 364b. A film transistor 360 is formed.

[0374] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and therefore the reliability of the display device can be improved.

[0375] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) By forming a high-resistance drain region 364b (or a high-resistance source region 364a) in As a result, the reliability of the thin film transistor can be improved. By forming the drain region 364b, the high resistance drain region 364b and the channel region 364b are formed from the drain electrode layer. It is possible to provide a structure in which the conductivity can be changed stepwise toward the channel forming region 363. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential Vdd. When the transistor is operated in this state, a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if the electric field is increased, the high-resistance drain region 364b acts as a buffer, making it difficult for local electric field concentration to occur. The withstand voltage of the transistor can be improved.

[0376] Next, a protective insulating layer is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See FIG. 12(D)).

[0377] Note that an insulating film is further formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. An oxide insulating layer may be formed and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0378] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0379] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0380] (Embodiment 8) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 350 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0381] An example of a cross-sectional structure of a thin film transistor of this embodiment mode is shown in FIGS.

[0382] The thin film transistor 350 is described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor with a multi-gate structure having multiple channel forming regions may be used. A data can also be formed.

[0383] 13(A) to 13(D), a thin film transistor 350 is fabricated on a substrate 340. The process will be explained.

[0384] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography is performed. In this embodiment, the gate electrode layer 351 is formed by a process. Then, a tungsten film having a thickness of 150 nm is formed by sputtering.

[0385] Next, a gate insulating layer 342 is formed over the gate electrode layer 351. A silicon oxynitride layer having a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Form.

[0386] Next, a conductive film is formed on the gate insulating layer 342, and a second photolithography process is performed. A resist mask is formed over the conductive film, and selective etching is performed to form a source electrode layer 355a After the drain electrode layer 355b is formed, the resist mask is removed (see FIG. 13A). .).

[0387] Next, an oxide semiconductor film 345 is formed (see FIG. 13B). As the oxide semiconductor film 345, an In-Ga-Zn-O-based oxide semiconductor film formation target is used. The oxide semiconductor film 345 is formed by a third photolithography process. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer.

[0388] In this case, the oxide semiconductor film 345 is formed while removing residual moisture in the treatment chamber. In order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345, This is the case.

[0389] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The concentration of impurities in the oxide semiconductor film 345 can be reduced.

[0390] The oxide semiconductor film 345 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. High-purity gas is used, in which impurities such as chlorine have been removed to concentrations of ppm or ppb. It is preferable that

[0391] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor The layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. This prevents water and hydrogen from re-entering the oxide semiconductor layer, thereby obtaining the oxide semiconductor layer 346. See Figure 13(C).

[0392] In the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. do.

[0393] Next, an oxide insulating layer 356 serving as a protective insulating film in contact with the oxide semiconductor layer 346 is formed.

[0394] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide insulating method such as sputtering. The layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 356. When hydrogen is contained in the oxide insulating layer 356, the hydrogen penetrates into the oxide semiconductor layer or The region where oxygen is extracted from the oxide semiconductor layer and a channel is formed in the oxide semiconductor layer is called a region where The opposite side (the so-called back channel side) becomes low resistance (N-type), and the parasitic channel Therefore, the oxide insulating layer 356 should be a film containing as little hydrogen as possible. Therefore, it is important that the deposition method does not involve the use of hydrogen.

[0395] In this embodiment, the oxide insulating layer 356 is formed by a sputtering method using an oxide film having a thickness of 200 nm. The substrate temperature during film formation is set to be between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering under atmospheric pressure. The oxide insulating layer 356 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any of these substances and blocks them from entering from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0396] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0397] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 356 can be reduced.

[0398] The oxide insulating layer 356 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of ppm or ppb. It is preferable.

[0399] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. The body layer is heated while in contact with oxide insulating layer 356.

[0400] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for the purpose of reducing the resistance, the oxide semiconductor film is made to have an oxygen-excess state. As a result, an i-type oxide semiconductor layer 352 is formed. 0 is formed.

[0401] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and therefore the reliability of the display device can be improved.

[0402] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, In this embodiment, a silicon nitride film is formed as a protective insulating layer 3. The film 43 is formed using a silicon nitride film (see FIG. 13(D)).

[0403] Further, a planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0404] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0405] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0406] (Embodiment 9) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 380 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0407] In this embodiment mode, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment Mode 6 is shown in FIG. 4. Figure 14 is the same as Figure 11 except for some differences in the process, so the same parts are The same reference numerals are used and detailed explanations of the same parts are omitted.

[0408] According to the sixth embodiment, a gate electrode layer 381 is formed on the substrate 370, and a first gate insulating layer 382 is formed on the substrate 370. In this embodiment, a gate insulating layer 372a and a second gate insulating layer 372b are stacked. The first gate insulating layer 372a is a nitride insulating layer, and the second gate insulating layer 3 An oxide insulating layer is used for 72b.

[0409] The oxide insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. As the nitride insulating layer, an aluminum oxynitride layer, or the like can be used. a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A layer or the like can be used.

[0410] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 nm. A silicon nitride layer (SiN y (y> 0)) is formed on the first gate insulating layer 372a as a second gate insulating layer 372b. A silicon oxide layer (SiO ) having a thickness of 5 nm to 300 nm (100 nm in this embodiment) x (x>0)) is laminated to form a gate insulating layer with a thickness of 150 nm.

[0411] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is formed into island-like layers by a photolithography process. In this embodiment, the oxide semiconductor film is formed of In-Ga-Z The film is formed by sputtering using a target for forming an nO-based oxide semiconductor film.

[0412] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0413] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0414] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0415] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and 750°C or lower, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is protected from exposure to the atmosphere, preventing water and hydrogen from re-entering the oxide semiconductor layer. After that, the same furnace is filled with high-purity oxygen gas, high-purity N2O gas, or ultra-dry gas. Dry air (dew point below -40°C, preferably below -60°C) is introduced to cool the material. It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the device is preferably 6N (99.9999%) or more. or 7N (99.99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0416] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Use an RTA (Rapid Thermal Anneal) device such as an LRTA devices can be used with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp. Heat is generated by heat conduction or heat radiation from heating elements such as TA devices, lamps, and resistance heating elements. The GRTA is a device that uses high-temperature gas to heat the object to be treated. The gas used is a rare gas such as argon or nitrogen, which is suitable for heating. The RTA method uses an inert gas that does not react with the material being treated. Heat treatment may be performed at up to 750°C for several minutes.

[0417] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0418] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0419] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance As a result, the oxide semiconductor layer 382 is entirely i-type.

[0420] Next, a conductive film is formed over the gate insulating layer 372b and the oxide semiconductor layer 382. Furthermore, a resist mask is formed over the conductive film by a photolithography process, and selective etching is performed. A source electrode layer 385a and a drain electrode layer 385b are formed by etching, and then a sputtering method is performed. An oxide insulating layer 386 is formed.

[0421] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed.

[0422] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., compounds containing hydrogen atoms are exhausted. The impurity concentration in the oxide insulating layer 386 can be reduced.

[0423] The oxide insulating layer 386 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of ppm or ppb. It is preferable.

[0424] Through the above steps, the thin film transistor 380 can be formed.

[0425] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is carried out in a nitrogen gas atmosphere. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0426] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and therefore the reliability of the display device can be improved.

[0427] Next, a protective insulating layer 373 is formed over the oxide insulating layer 386. In this embodiment, As the edge layer 373, a silicon nitride film having a thickness of 100 nm is formed by sputtering.

[0428] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and water. It does not contain impurities such as hydrogen, hydrides, or hydroxides, and blocks these from entering from the outside. It has the effect of checking.

[0429] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside In addition, even after the device is completed as a display device, It is possible to prevent the intrusion of impurities such as moisture from the outside, improving the long-term reliability of the device. This can be done.

[0430] In addition, a protective insulating layer 373 made of a nitride insulating layer and a first gate insulating layer 372a are provided between the protective insulating layer 373 and the first gate insulating layer 372a. The insulating layer is removed, and the protective insulating layer 373 and the first gate insulating layer 372a are in contact with each other. The structure may be such that:

[0431] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be removed as much as possible. and the re-mixing of the impurities is prevented, thereby maintaining the impurity concentration in the oxide semiconductor layer at a low level. It is possible.

[0432] Note that a planarization insulating layer may be provided over the protective insulating layer 373 for planarization.

[0433] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to the pixel of the display device, This allows the storage capacitor provided in the pixel to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displaying.

[0434] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0435] (Embodiment 10) This embodiment provides another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor described in this embodiment is the same as the thin film transistor described in any of Embodiments 2 to 8. can be applied to.

[0436] In this embodiment mode, a light-transmitting conductive film is formed in the gate electrode layer, the source electrode layer, and the drain electrode layer. Therefore, the other steps can be carried out in the same manner as in the above embodiment. The description of the same parts as those in the embodiment, or parts having similar functions, and repeated steps will be omitted. Also, detailed explanations of the same parts will be omitted.

[0437] For example, the gate electrode layer, the source electrode layer, and the drain electrode layer may be made of a material that is transparent to visible light. Photoconductive materials, such as In-Sn-O, In-Sn-Zn-O, and In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O Zn-O and Zn-O metal oxides can be used, with a film thickness of 50 nm to 300 nm. The metal oxide used in the gate electrode layer, the source electrode layer, and the drain electrode layer is appropriately selected within the range. The deposition method of the oxide is sputtering, vacuum deposition (electron beam deposition, etc.), arc deposition, etc. Discharge ion plating method, spray method, and sputtering method are used. In this case, the film is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and the film is transparent. Conductive film with high crystallization inhibitor SiO x (X>0) and heating in the subsequent process It is preferable to suppress crystallization during the treatment.

[0438] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0439] In addition, the pixel where the thin film transistor is arranged has a pixel electrode layer or other electrode layer (capacitor The transparent electrode layer and other wiring layers (such as the capacitor wiring layer) are transparent to visible light. By using a conductive film, a display device having a high aperture ratio can be realized. The gate insulating layer, oxide insulating layer, protective insulating layer, and planarizing insulating layer present therein are also transparent to visible light. It is preferable to use a membrane having the following properties:

[0440] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes As a metal oxide applied to the wiring layer, a conductive film that is semi-transparent to visible light is used. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0441] As described above, by providing a thin film transistor with light-transmitting properties, the aperture ratio can be improved. In particular, in small display panels of 10 inches or less, increasing the number of gate wiring To achieve high resolution in the displayed image, it is necessary to realize a high aperture ratio even when the pixel size is reduced. Furthermore, by using a light-transmitting film as a component of a thin film transistor, high density Even if a group of thin film transistors is arranged, a large aperture ratio can be obtained, and the area of ​​the display area can be reduced. In addition, the same materials are used in the same process as the components of thin film transistors. If a storage capacitor is formed using the same, the storage capacitor can also be made translucent, which further increases the aperture ratio. It can be improved.

[0442] Furthermore, by applying a highly purified oxide semiconductor layer to a thin film transistor, A thin film transistor with reduced current can be provided. By applying a thin film transistor with reduced off-state current to a pixel of a display device, This allows the storage capacitor provided in the element to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displayed.

[0443] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0444] (Embodiment 11) In this embodiment, examples of light-emitting elements that can be applied to the display device disclosed in this specification are shown in FIGS. This will be explained below with reference to FIG.

[0445] In this embodiment, an electroluminescent display element is used as a display element of a pixel of the display device. The light-emitting element using electroluminescence is exemplified as follows. They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0446] An organic EL element has an anode, a cathode, and a layer containing an organic compound between them. The potential is increased to a value higher than the potential at which holes are injected from the anode and electrons are injected from the cathode into the layer containing the organic compound. When electrons and holes (carriers) recombine in the layer containing the organic compound, energy is generated. The generated energy excites the luminescent organic compound, which then reacts with the base Due to this mechanism, organic EL elements are considered to be current-excited light-emitting devices. This is an example of an optical element.

[0447] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0448] FIG. 15 is an equivalent circuit diagram showing an example of a pixel configuration.

[0449] The structure and operation of a pixel will be described. An example in which two n-channel transistors are used in the pixel is shown.

[0450] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, and a light emitting element 6404. The switching transistor 6401 has a gate that runs The first electrode (one of the source electrode and the drain electrode) is connected to the signal line 64 05, and the second electrode (the other of the source electrode and the drain electrode) is connected to the driving transistor The driving transistor 6402 has a gate connected to a switch The second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (image element) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0451] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0452] DC power is supplied to the power supply line 6407. In particular, pulsed DC power is supplied to the power supply line 640 7, the light emitting element 6404 can emit light in a pulsed manner. By displaying a loop-like image, multiple still images can be displayed in sequence. Such a display can be used, for example, to display a clock that ticks away seconds. DC power may be supplied.

[0453] In this embodiment, a thin film transistor having a highly purified oxide semiconductor layer and a reduced off-state current is Since the transistor is applied to the pixel portion, the switching transistor 6401 is turned off. During this state, the potential written to the gate of the driving transistor 6402 is held. It should be noted that even if a capacitor is provided between the gate of the driving transistor 6402 and the power supply line 6407, good.

[0454] As an example of a method for driving the light emitting element 6404, a method for performing analog gray scale driving will be described. The gate of the driving transistor 6402 is connected to the forward voltage of the light emitting element 6404. A voltage equal to or higher than the Vth of the capacitor 6402 is applied. This refers to the voltage when the device is driven at a certain temperature, and includes at least the forward threshold voltage. A video signal (image signal) that causes the transistor 6402 to operate in the saturation region is input. This allows current to flow through the light emitting element 6404. In order to operate in the above-mentioned region, the potential of the power supply line 6407 is set to the gate of the driving transistor 6402. By converting the video signal into an analog signal, the video signal is input to the light emitting element 6404. A current corresponding to the signal flows, and analog gradation driving can be performed.

[0455] Note that an oxide semiconductor layer that is not crystallized by laser has little variation in characteristics within the substrate surface. Therefore, the characteristics of a plurality of thin film transistors arranged in a display area using the oxide semiconductor layer The driving transistor 6402 has little variation in characteristics, and the light emitting element 640 The current flowing through the gate electrode 4 can be precisely controlled according to the gate voltage written. A display device according to one embodiment of the present invention is capable of high-quality display with little display unevenness.

[0456] In addition, the voltage input voltage driving method allows for area gradation display using multiple pixels and for displaying different luminescent colors. Color representation by combining multiple pixels (e.g., R, G, B) (e.g., R+G, G +B, R+B, R+G+B, etc. are possible. In the case of voltage input voltage drive system, The gate of the transistor 6402 is connected to the driving transistor 6402 to determine whether the driving transistor 6402 is sufficiently turned on or not. In other words, the driving transistor 64 is turned on or off. The driving transistor 6402 is operated in the linear region. , a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to a voltage greater than (power supply line voltage + Vth of the driving transistor 6402). Apply the above voltage.

[0457] In addition, whether the light emitting element 6404 is driven by analog gradation or by voltage input voltage, For example, the off-state current per 1 μm of the channel width of the switching transistor 6401 is 1× 10 -16 Since the gate voltage of the driving transistor 6402 is suppressed to less than A / μm, Therefore, even if the number of times of writing image signals is small, the still image on the display The frequency of writing signals can be reduced, It is possible to reduce power consumption. The pixel configuration shown in FIG. 15 is not limited to this. For example, if a switch, a resistor, a capacitor, a transistor, or A logic circuit or the like may be added.

[0458] Next, the cross-sectional structure of the pixel will be described with reference to FIG. 16. The driving TFTs 7011, 7021, and 7001 shown in (C) are made of highly purified acid. A thin film transistor having a nitride semiconductor layer may be applied, for example, in the second embodiment to the third embodiment. The thin film transistor described in the tenth embodiment can be used.

[0459] The light-emitting element exemplified in this embodiment has a structure in which an EL layer is sandwiched between a first electrode and a second electrode. Has.

[0460] The first and second electrodes of the light-emitting element, which serve as cathodes, are made of a material with a small work function. For example, specifically, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr. Potassium earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), as well as Yb and E The anode electrode is preferably made of a material with a large work function, such as rare earth metals such as r. For example, titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., ITO, IZO (insulated oxide) Transparent conductive materials such as zinc oxide (ZnO) and ZnO are preferred. When forming the hole injection layer in contact with the anode, or when forming the hole injection layer in contact with the anode, the work function of the electrode material The electron injection layer and hole injection layer can be made of, for example, an organic compound and a metal. Composite materials of oxides, metal oxides, organic compounds and alkali metals, alkaline earth metals, or In addition to composite materials with these compounds, they can also be formed by appropriately combining them.

[0461] The EL layer formed on the first electrode may be composed of a single layer or a plurality of layers stacked together. When the EL layer is composed of multiple layers, the layers are an anode, a hole injection layer, A hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and a cathode are laminated in this order in contact with each other. It is not necessary to provide all of these layers. In addition, a plurality of EL layers separated by intermediate layers functioning as charge generating layers are connected to a first electrode and a second electrode. The electrode may be provided between the electrodes.

[0462] In order to extract light from the light emitting element, at least one of the first electrode and the second electrode is The light emitted from the light-emitting element formed on the substrate is extracted. The light emitting elements are classified according to the direction. Injection from the bottom, which is taken out from the surface on the substrate side, and injection from the surface on the substrate side and the opposite side There are three typical structures of light-emitting elements: dual-side emission, dual-side emission, and which light-emitting element has which emission structure. It can also be applied to

[0463] When the EL layer is laminated on the first electrode, the periphery of the first electrode is covered with a partition wall. For example, organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, The partition wall is formed using organic polysiloxane. Also, the partition wall is formed using a photosensitive resin material. It is preferable that the first electrode is covered with a separator while leaving a separator on the periphery of the first electrode. When an opening is formed in a light-transmitting resin material, the sidewall from the partition to the opening has a continuous curvature. This is because the inclined surface has a certain angle and the step of forming a resist mask can be omitted.

[0464] A color filter can also be formed between the substrate and the light emitting element. Droplet ejection methods such as inkjet printing, printing, and etching using photolithography technology The formation may be performed by a coating method or the like.

[0465] In addition, it is preferable to form an overcoat layer on the color filter and then form a protective insulating layer thereon. By providing an overcoat layer, the unevenness caused by the color filter can be smoothed. Forming an insulating film can prevent impurities from diffusing from the color filter to the light-emitting element. .

[0466] The light emitting element is formed on the protective insulating layer, overcoat layer and insulating layer on the thin film transistor. When forming the thin film transistor, the insulating layer is penetrated through the protective insulating layer, the overcoat layer and the insulating layer. A contact hole reaching the source electrode layer or the drain electrode layer is formed. When the contact holes are laid out and formed at positions overlapping the partition walls, the aperture ratio can be reduced. This is preferable because it can be suppressed.

[0467] The structure of a pixel having a light-emitting element with a bottom emission structure will be described. FIG. 16A shows a cross-sectional view of a cut surface including T7011 and the light-emitting element 7012.

[0468] The driving TFT 7011 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. a gate electrode layer, a gate insulating layer, and a gate electrode layer; The wiring layers are provided so as to be electrically connected to each other.

[0469] An insulating layer 7031 is formed to cover the driving TFT 7011, and an opening is formed on the insulating layer 7031. A color filter 7033 having an aperture is provided. The overcoat layer 7034 and the insulating layer 7035 are formed to cover the color filter 7033. 035. The drain electrode of the driving TFT 7011 and the conductive film 701 7 is an overcoat layer 7034, an insulating layer 7035, and an opening formed in the insulating layer 7031. The first light-emitting element 7012 is electrically connected to the conductive film 7017 through the opening. The electrode 7013 is provided in contact with the electrode 7013 .

[0470] The light-emitting element 7012 has an EL layer 7014 between a first electrode 7013 and a second electrode 7015. It is held in place.

[0471] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive film can be used.

[0472] Here, the case where the first electrode 7013 of the light-emitting element 7012 is used as a cathode will be described. When the first electrode 7013 is used as a cathode, a metal having a small work function is suitable. In FIG. 16A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through (preferably 5 For example, an aluminum film or M film having a thickness of 20 nm is used. A g-Ag alloy film is used for the first electrode 7013 .

[0473] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7017 and the first electrode 7013 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0474] The second electrode 7015 formed on the EL layer 7014 is made of a material having a large work function. In addition, a shielding film 7016, for example, a metal that blocks light, is preferably provided on the second electrode 7015. In this embodiment, an ITO film is used as the second electrode 7015. A Ti film is used as the shielding film 7016 .

[0475] The color filter 7033 is covered with an overcoat layer 7034, and a protective insulating layer 7035 is formed on the overcoat layer 7034. In FIG. 16(A), the overcoat layer 7034 is shown as being thin. However, the overcoat layer 7034 flattens the unevenness caused by the color filter 7033. There are.

[0476] Also, a layer formed on the overcoat layer 7034 and the protective insulating layer 7035 and a drain electrode The contact hole reaching the pole layer 7030 is arranged at a position overlapping with the partition wall 7019. .

[0477] In the case of the pixel structure shown in FIG. 16(A), light emitted from the light emitting element 7012 is The light is then emitted to the first electrode 7013 side, passes through the color filter 7033, and exits the display device. do.

[0478] In FIG. 16A, the gate electrode layer, the source electrode layer, and the drain electrode layer are formed of a light-transmitting material. 1 shows an example in which the driving TFT 7011 is configured using a conductive film having A part of the light emitted from the element 7012 is reflected by the color filter 7033 and the driving TFT 701. It passes through 1 and is ejected.

[0479] Next, the configuration of a pixel having a light-emitting element with a dual emission structure will be described. FIG. 16B shows a cross-sectional view of a cut surface including the application TFT 7021 and the light-emitting element 7022.

[0480] The driving TFT 7021 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. a gate electrode layer, a gate insulating layer, and a gate electrode layer; The wiring layers are provided so as to be electrically connected to each other.

[0481] An insulating layer 7041 is formed to cover the driving TFT 7021. A color filter 7043 having an aperture is provided. The overcoat layer 7044 and the insulating layer 7045 are formed to cover the color filter 7043. 045. The drain electrode of the driving TFT 7021 and the conductive film 702 7 is an overcoat layer 7044, an insulating layer 7045, and an opening formed in the insulating layer 7041. The first light-emitting element 7022 is electrically connected to the conductive film 7027 through the opening. The electrode 7023 is provided in contact with the electrode 7023 .

[0482] The light-emitting element 7022 has an EL layer 7024 between a first electrode 7023 and a second electrode 7025. It is held in place.

[0483] Here, the case where the first electrode 7023 of the light-emitting element 7022 is used as a cathode will be described. Note that the light-transmitting conductive film 7027 is the same as the conductive film 7017 shown in FIG. The first electrode 7023 may be formed in the same manner as the first electrode 7013 shown in FIG. The EL layer 7024 may be formed in the same manner as the EL layer 7014 shown in FIG. Since they can be formed in the same manner, detailed explanations will be omitted here.

[0484] The second electrode 7025 formed on the EL layer 7024 functions as an anode here. A material with a large work function, for example, a transparent conductive material such as ITO, IZO, or ZnO, is preferred. In this embodiment, the second electrode 7025 is formed of ITO.

[0485] The color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are The color filter 7033 and the overcoat layer 703 included in the pixel illustrated in FIG. 16(A) 4 and the protective insulating layer 7035 may be formed in a similar manner.

[0486] In the case of the pixel structure shown in FIG. 16(B), light emitted from the light emitting element 7022 is As shown in the figure, the light is emitted to both the first electrode 7023 side and the second electrode 7025 side, and the first electrode 70 The light from the 23 side passes through the color filter 7043 and exits the display device.

[0487] In FIG. 16B, the gate electrode layer, the source electrode layer, and the drain electrode layer are formed of a light-transmitting material. 1 shows an example in which the driving TFT 7021 is configured using a conductive film having A part of the light emitted from the element 7022 is reflected by the color filter 7043 and the driving TFT 702. It passes through 1 and is ejected.

[0488] Also, a drain electrode layer is formed on the overcoat layer 7044 and the insulating layer 7045. The contact hole reaching 7040 is arranged at a position overlapping with the partition wall 7029. The layout is such that the contact hole reaching the drain electrode layer and the partition wall 7029 overlap each other. This makes the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side almost the same. This can be done.

[0489] However, if both display surfaces of the light-emitting element with a dual emission structure are to be used for full color display, the second Since light from the electrode 7025 side does not pass through the color filter 7043, a separate color filter is required. It is preferable that a sealing substrate provided with a metal layer be provided above the second electrode 7025 .

[0490] Next, the configuration of a pixel having a light-emitting element with a top emission structure will be described. FIG. 16C shows a cross-sectional view of a cut surface including the application TFT 7001 and the light-emitting element 7002.

[0491] The driving TFT 7001 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. a gate electrode layer, a gate insulating layer, and a gate electrode layer; The wiring layers are provided so as to be electrically connected to each other.

[0492] An insulating layer 7051 is formed to cover the driving TFT 7001, and an opening is formed on the insulating layer 7051. An insulating layer 7053 having an opening is provided. The first electrode 7003 is The driving TFT 7001 is formed on an insulating layer 7055 formed to cover the driving TFT 7001. The drain electrode and the first electrode 7003 are formed on the insulating layer 7055 and the insulating layer 7051. The electrical connection is made through the opening.

[0493] The insulating layer 7053 is made of polyimide, acrylic, benzocyclobutene, polyamide, ethylene In addition to the above resin materials, low dielectric constant materials (e.g., epoxy) can be used. low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) In addition, a plurality of insulating films made of these materials can be stacked. The insulating layer 7053 may be formed by the method described above. Depending on the material, sputtering, SOG, spin coating, dipping, spray coating, Droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife A roll coater, a curtain coater, a knife coater, etc. can be used. By forming 7053, for example, unevenness caused by the driving TFT can be made flat.

[0494] The light-emitting element 7002 has an EL layer 7004 between a first electrode 7003 and a second electrode 7005. In the light-emitting element 7002 illustrated in FIG. 16C, the first electrode 700 The case where 3 is used as a cathode will be explained.

[0495] The first electrode 7003 may be made of the same material as the first electrode 7013 shown in FIG. However, in the light-emitting element having a top emission structure shown in FIG. 16(C), the first electrode 7003 It is preferable that the electrode does not have light transmission properties and has high reflectivity. By using an electrode having such a structure, the light extraction efficiency can be improved.

[0496] The first electrode 7003 is, for example, an aluminum film or a film containing aluminum as a main component. An alloy film made of titanium or an aluminum film laminated with a titanium film is preferable. In this example, a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order is used as the first electrode 7003. do.

[0497] The EL layer 7004 may be formed in the same manner as the EL layer 7014 shown in FIG. The second electrode 7005 may be formed in the same manner as the second electrode 7025 shown in FIG. 16(B). Therefore, a detailed description will be omitted here.

[0498] In the case of the pixel structure shown in FIG. 16(C), light emitted from the light emitting element 7002 is The light is emitted toward the second electrode 7005 as shown.

[0499] When full color display is performed using the structure of FIG. 16C, for example, the light emitting element 7002 is One adjacent light-emitting element is a red light-emitting element and the other is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element was added to create a total of four types of light-emitting elements. A light-emitting display device capable of full-color display may be manufactured.

[0500] In addition, all of the light emitting elements arranged in the structure of FIG. 16(C) are white light emitting elements. A sealing substrate having a color filter or the like is disposed above each light-emitting element including element 7002. A light emitting display device capable of full color display may be manufactured by using a structure in which the light emitting element is placed. By forming elements that emit light in different colors and combining them with color filters and color conversion layers, Color display is possible.

[0501] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be formed to emit an area color light.

[0502] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0503] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0504] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0505] Next, the appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a display device will be described. The surface will be explained with reference to Fig. 17. Fig. 17(A) shows a thin film formed on a first substrate. A panel in which the transistor and the light-emitting element are sealed between the second substrate and the panel by a sealing material. 17(B) is a top view, and corresponds to a cross-sectional view taken along line HI in FIG. 17(A).

[0506] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0507] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 17B, a thin film transistor 4510 included in a pixel portion 4502 and a signal A thin film transistor 4509 included in a signal line driver circuit 4503a is shown as an example. An insulating layer 4542 is provided on the transistors 4509 and 4510. The source electrode of the thin film transistor 4510 is connected to the contact hole 542. The drain electrode layer and the first electrode layer 4517 of the light-emitting element 4511 are electrically connected to each other. are.

[0508] The thin film transistors 4509 and 4510 are the high-performance thin film transistors described in any of Embodiments 1 to 10. A thin film transistor having a purified oxide semiconductor layer is used.

[0509] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4542. A conductive layer 4540 is provided in a position overlapping with the channel formation region. By placing it at a position overlapping the channel formation region of the nitride semiconductor layer, BT stress test (Bias and temperature stress test) Threshold voltage of thin-film transistor 4509 before and after In this specification, the BT stress test (bias Temperature stress test is a test in which a high gate voltage is applied to a thin film transistor in a high temperature atmosphere. The conductive layer 4540 is connected to the gate of the thin film transistor 4509. The second gate electrode layer may be the same as or different from the first gate electrode layer. The potential of the conductive layer 4540 can be set to GND, 0 V, or in a floating state. It's okay to have it.

[0510] The light-emitting element 4511 includes a first electrode layer 4517, an electroluminescent layer 4512, a second electrode layer 4513, and a second electrode layer 4514. The laminated structure of the light emitting element 4513 is not limited to the structure shown. The configuration of the light emitting element 4511 can be changed as appropriate in accordance with the direction of light.

[0511] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0512] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0513] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0514] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0515] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film as the source electrode layer and the drain electrode layer of the first insulating film.

[0516] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0517] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be light-transmitting. In this case, use a glass plate, plastic plate, polyester film or acrylic film. A light-transmitting material such as polyethylene is used.

[0518] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0519] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0520] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0521] With the above structure, a thin film transistor having a highly purified oxide semiconductor layer and reduced off-state current can be obtained. A display device using a thin film transistor with reduced off-current can be provided. Since this is applied to the pixel, the period during which the storage capacitor provided in the pixel can store the voltage can be extended. As a result, it is possible to provide a display device that operates stably when displaying still images and consumes less power. .

[0522] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0523] (Embodiment 12) In this embodiment mode, one mode of a display device in which a luminous layer is provided in a pixel portion will be described with reference to FIG. explain.

[0524] Figure 18 is a cross-sectional view of a pixel part of a bottom emission structure, and shows the driving TFT 7211 provided in the pixel, 7 is a cross-sectional view of a section including a light-emitting element 7212. FIG.

[0525] The driving TFT 7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. a gate electrode layer, a gate insulating layer, and a gate electrode layer; The wiring layers are provided so as to be electrically connected to each other.

[0526] An insulating layer 7231 is formed to cover the driving TFT 7211, and an opening is formed on the insulating layer 7231. The light-transmitting conductive film 7217 is a light-storing layer. An overcoat layer 7234 formed over the layer 7233 and an insulating layer 7235 formed on the layer 7233. The drain electrode 7230 and the conductive film 7217 of the driving TFT 7211 are through openings formed in the overcoat layer 7234, the insulating layer 7235, and the insulating layer 7231. The first electrode 7212 of the light-emitting element 7212 is formed on the conductive film 7217 and electrically connected to the conductive film 7217. 213 is located adjacent to it.

[0527] The driving TFT 7211 and the light emitting element 7212 are manufactured by the method explained in the eleventh embodiment. Therefore, detailed description will be omitted here.

[0528] The luminous layer 7233 contains a luminous material and stores the light emitted by the adjacent light-emitting element. Even after the light is turned off, the luminous material contained in the luminous layer 7233 continues to emit light. In this study, copper activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. Phosphors that have activators added to sulfides such as SrS as the base material, and rare earth activated aluminum Potassium earth aluminates CaAl2O4:Eu, CaAl2O4:Nd, Sr4Al 14 O 25 :Eu, Sr4Al 14 O 25:Dy, SrAl2O4:Eu, and SrAl 2O4:Dy or the like may also be used.

[0529] The time that the luminous layer 7233 continues to emit light can be changed depending on the type of luminous material used. The amount of time that light continues to be emitted, or the so-called afterglow time, varies depending on the type of phosphorescent material, so it is necessary to select the appropriate material depending on the application. For example, if the display content does not need to be rewritten frequently, For the display device, a phosphorescent material with a long afterglow time can be selected and used. In this case, a phosphorescent material with a short decay time can be selected and used. When the particles are inorganic particles, the particle size is 1 nm or more and 10 μm or less, preferably 10 nm or more and 5 μm or less. If the particle size is 1 nm or less, the phosphorescence effect is lost, and if the particle size is 10 μm or less, the phosphorescence effect is lost. If there is more than this, the flatness of the phosphorescent layer will be impaired, making it difficult to fabricate the light-emitting element. is.

[0530] In this embodiment, the luminous layer 7233 contains a binder polymer in which a luminous material is dispersed. The dispersion liquid is then subjected to a droplet ejection method such as an inkjet method, a printing method, a spin coating method, and a photolithography method. The method is appropriately selected to form the insulating film, such as an etching method using lithography technology.

[0531] The phosphorescent layer 7233 is covered with an overcoat layer 7234. It is covered with an insulating layer 7235. In FIG. 18, the overcoat layer 7234 is shown as having a thin film thickness. However, the overcoat layer 7234 has the function of flattening the unevenness of the luminous layer 7233. do.

[0532] The position where the luminous layer is provided is not limited to between the user of the display device and the light emitting element. A light-emitting element having a dual emission structure in which an EL layer is sandwiched between a pair of light-transmitting electrodes has light-transmitting properties. In this way, when the light emitting element has light transmission properties, the phosphorescent layer is not visible to the user of the display device. In other words, it can be placed between the luminous layer and the user of the display device. A light emitting element can be placed between the user of the display device and the phosphorescent layer. For example, the luminous layer does not necessarily have to be translucent, which broadens the range of luminous materials that can be selected. Specifically, it will be possible to use phosphorescent materials with particle sizes of 100 μm or less.

[0533] With the above-described structure, a thin film transistor having a luminous layer and a highly purified oxide semiconductor layer is formed in the pixel portion. The display device can provide a thin film transistor having a reduced off-current. Since a transistor is applied to the pixel, the period during which the storage capacitor provided in the pixel can store the voltage As a result, the operation when displaying still images etc. is stable and the display consumes less power. The device can be provided.

[0534] Furthermore, one embodiment of the present invention provides a self-luminous display device that can display an image with excellent visibility even in an environment with weak external light. Furthermore, since the pixel portion has a luminous layer using a luminous material, the luminous It is possible to provide a display device in which flicker is not noticeable even when the light emission interval of the optical element is long. In addition, even in an environment with weak external light, the light-emitting element is driven to provide energy to the phosphorescent material. Therefore, it is possible to provide a display device that can be used continuously for a long period of time.

[0535] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0536] (Embodiment 13) In this embodiment, an example of an electronic device including the display device described in the above embodiment is We will explain about this.

[0537] FIG. 19(A) shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in FIG. 19(A) can be used to play a program or data recorded on a recording medium. It also has the function of reading out data and displaying it on the display, and of sharing information with other portable gaming machines via wireless communication. The portable gaming machine shown in FIG. 19(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0538] FIG. 19B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 19(B) can have: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Function, function to acquire various information from the antenna, image taken or acquired from the antenna It has the function of saving the captured information, displaying the captured image or the information obtained from the antenna on the display. It should be noted that the digital camera with television reception function shown in FIG. The functions of the mobile camera are not limited to these, and the mobile camera may have a variety of functions.

[0539] FIG. 19C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has the functions of processing television radio waves and converting them into image signals, It has functions such as converting signals suitable for display and converting the frame frequency of image signals. It should be noted that the functions of the television receiver shown in FIG. 19(C) are not limited to these. It can have a variety of functions.

[0540] FIG. 20A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, pointing devices 9681, external connection points The computer shown in FIG. 20(A) can store various information. (still images, videos, text images, etc.) on the display, Functions for controlling processing by means of a program, communication functions such as wireless or wired communication, the ability to connect to various computer networks using the communication function, It can have a function to transmit or receive data, etc. The functions possessed by the computer are not limited to these, and the computer may have a variety of functions.

[0541] Next, FIG. 20B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, microphone 9638, etc. The mobile phone shown in has the function of displaying various information (still images, videos, text images, etc.), Functions for displaying the calendar, date, time, etc. on the display, and for operating or It has the function of editing, the function of controlling the processing by various software (programs), etc. The functions of the mobile phone shown in FIG. 20(B) are not limited to these. It can have a variety of functions.

[0542] Next, FIG. 20C shows an electronic paper (also called an E-book), which includes a housing 9630, a display The electronic pen 9630 shown in FIG. The user can display various information (still images, videos, text images, etc.), a calendar, , the function to display the date or time on the display unit, and the function to operate or edit the information displayed on the display unit Functions, functions to control processing by various software (programs), etc. The functions of the electronic paper shown in FIG. 20(C) are not limited to these. It can have a variety of functions.

[0543] In the electronic device described in this embodiment, in a plurality of pixels constituting a display portion, Therefore, the period during which the voltage can be maintained by the storage capacitor can be extended. and a display device capable of reducing power consumption when displaying still images, etc. In addition, by improving the aperture ratio, it is possible to effectively use a high-definition display. The display device can be configured as follows.

[0544] Furthermore, one embodiment of the present invention provides a self-luminous display device that can display an image with excellent visibility even in an environment with weak external light. In addition, when a phosphorescent layer using a phosphorescent material is applied to the pixel portion, It is possible to provide a display device in which flicker is not noticeable even if the light emission interval of the light emitting element is long. In addition, even in an environment with weak external light, the light-emitting element is driven to provide energy to the phosphorescent material. Therefore, it is possible to provide a display device that can be used continuously for a long period of time.

[0545] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0546] (Embodiment 14) In this embodiment mode, a block diagram of a display device and a procedure for stopping and starting the operation in a driver circuit are shown. First, a block diagram of the display device will be described with reference to FIG.

[0547] A display device 1000 described in this embodiment includes a display panel 1001, a signal generating circuit 1002, It has a memory circuit 1003, a comparison circuit 1004, a selection circuit 1005, and a display control circuit 1006. do.

[0548] The display panel 1001 includes, for example, a driver circuit portion 1007 and a pixel portion 1008 . The gate line driving circuit 1009A and the signal line driving circuit 1009B are included. 1009A and a signal line driver circuit 1009B drive a pixel portion 1008 having a plurality of pixels. The gate line driver circuit 1009A and the signal line driver circuit 1009B are driver circuits for The pixel portion 1008 and the pixel portion 1009 are configured with thin film transistors formed on the same substrate. It may also be something like this.

[0549] The gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 are The thin film transistors that are formed in part or all of them are n-channel transistors whose semiconductor layer is an oxide semiconductor. The gate line driving circuit 1007 uses a thin film transistor of the FET type. The signal line driver circuit 1009A and the signal line driver circuit 1009B may be formed on the same substrate. Alternatively, the light emitting device may be provided on a separate substrate.

[0550] The signal generating circuit 1002 includes a gate line driving circuit 1009A and a signal line driving circuit 1006B. From 09B, a pulse signal for outputting a signal for display in the pixel section 1008 is generated. The signal generating circuit 1002 outputs to the driving circuit section 1007 via wiring. A circuit for converting image signals (also called video voltages, video signals, or video data) into This is a circuit for outputting to the memory circuit 1003 via wiring. To generate and output a control signal for driving 007 and an image signal to be supplied to the pixel unit This is the circuit.

[0551] Specifically, the signal generating circuit 1002 outputs control signals to a gate line driving circuit 1009A, The signal line driver circuit 1009B is supplied with a high power supply potential Vdd and a low power supply potential Vss. Also, a start pulse for the gate line driving circuit is supplied to the gate line driving circuit 1009A. SP, a clock signal CK is generated and output to a signal line driving circuit 1009B. The signal generating circuit 1 generates and outputs a start pulse SP and a clock signal CK for the circuit. 002 outputs image signal data for displaying moving images or still images to a memory circuit 1003. To exert effort.

[0552] The moving image is created by switching multiple images time-divided over multiple frame periods at high speed. Specifically, it refers to an image that is recognized as a moving image by the human eye 60 times per second (60 By switching images more than one frame, the human eye perceives it as a moving image with less flicker. On the other hand, still images are different from moving images in that they are composed of multiple frames. Although it operates by switching multiple images time-divided over a period at high speed, it is For example, the image signal does not change between the nth frame and the (n+1)th frame. This means that.

[0553] The signal generating circuit 1002 is also a circuit that generates other signals such as image signals and latch signals. The signal generating circuit 1002 may also include a gate line driving circuit 1009A and / or a signal The signal line driver circuit 1009B is provided with a reset signal to stop the output of the pulse signal of each driver circuit. Each signal may be a first clock signal, a second clock signal, or a The signal may be a signal composed of multiple signals such as a clock signal.

[0554] The high power supply potential Vdd is a potential higher than the reference potential, and the low power supply potential is a potential higher than the reference potential. Note that both high and low power supply potentials are at levels where a transistor operates. It is desirable that the potential be as low as possible.

[0555] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible to do this.

[0556] The image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal. In this case, the signal is converted into a digital signal via an A / D converter or the like and stored in the memory circuit 1003. It is sufficient to configure it to output.

[0557] The memory circuit 1003 includes a plurality of frame memory circuits for storing image signals for a plurality of frame periods. The number of frame memories included in the memory circuit 1003 is not particularly limited. Any element capable of storing image signals for multiple frame periods is acceptable. The frame memory is, for example, a DRAM (Dynamic Random Access Memory). ss Memory), SRAM (Static Random Access Mem It may be configured using a memory element such as a memory cell.

[0558] The frame memory 1010 may be configured to store an image signal for each frame period. The number of frame memories is not particularly limited. The image signal of 0 is selectively read out by the comparison circuit 1004 and the selection circuit 1005. That is why.

[0559] The comparison circuit 1004 compares the image signals of successive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out the image signals, comparing them, and detecting the difference. When a difference is detected by the comparison of the image signals in the comparison circuit 1004, the difference is detected. On the other hand, the image in the comparator circuit 1004 is judged to be a moving image. When a difference is not detected by comparing the signals, the difference is not detected in the consecutive frames. In other words, the comparison circuit 1004 detects the difference between the still and the still images. whether the image signals for successive frame periods are image signals for displaying moving images, or It is judged whether the signal is an image signal for displaying a still image. When the difference obtained by the comparison exceeds a certain level, it is determined that a difference has been detected. It may be set as follows.

[0560] The selection circuit 1005 includes a plurality of switches, for example, switches formed of thin film transistors. When an image signal for displaying a moving image is determined by detecting a difference in the comparison circuit, The image signal is selected from the frame memory 1010 in which the image signal is stored, and the display control circuit The comparison circuit 1004 outputs the difference between the frames to the comparison circuit 1006. If no difference in the image signal is detected, the image displayed between the frames is a still image. In this case, the image signal for the frame period is not output to the display control circuit 1006. This can be done as follows.

[0561] The display control circuit 1006 receives an image signal, a high power supply potential Vdd, a low power supply potential Vss, a start signal, Regarding the control signals of the pulse SP, clock signal CK, and reset signal Res, 1007. 4, if it is determined to be a moving image, that is, if the difference between the image signals of consecutive frame periods is extracted, The image signal is supplied from the selection circuit 1005 and is transmitted to the drive circuit 1006 via the display control circuit 1006. The control signal is supplied to the drive circuit unit 1007 via the display control circuit 1006. On the other hand, the comparator circuit 1004 judges that the image is a still image, i.e., a continuous frame. When the difference between the image signals in the frame period is not extracted, the image signal is supplied from the selection circuit 1005. Therefore, the image signal is not supplied from the display control circuit 1006 to the driver circuit 1007. The display control circuit 1006 stops supplying the control signal to the drive circuit unit 1007 .

[0562] In addition, when it is determined that the image is a still image, if the period during which the image is determined to be a still image is short, the control Of the signals, the high power supply potential Vdd and the low power supply potential Vss may not be stopped. The power consumption caused by frequently stopping and restarting the high power supply potential Vdd and the low power supply potential Vss is This is preferable because it can reduce the increase.

[0563] The image signal and the control signal are stopped when each pixel of the pixel unit 1008 can hold an image signal. It is desirable to supply the image signal again after the retention period of each pixel. The display control circuit 1005 then supplies the image signal and control signal that it previously supplied again. It is sufficient to have a configuration like this.

[0564] The supply of a signal means supplying a predetermined potential to a wiring. and a wiring to which a predetermined fixed potential is supplied, for example, a low power supply potential Vs s is connected to the wiring to which the signal is supplied. This refers to cutting off the electrical connection to the wiring connected to the board and leaving it in a floating state.

[0565] As described above, a thin film transistor having an oxide semiconductor layer has a channel length of 10 μm. In this case, the off-state current per 1 μm of channel width is 1 aA (1 × 10 -18 A) Below (this is expressed as 1 aA / μm), so the retention period can be made longer. Therefore, in this embodiment, when displaying a still image, it is necessary to reduce power consumption. A multiplier effect is expected.

[0566] As mentioned above, the video signal is compared to determine whether it is a moving image or a still image, and the clock signal and start pulse are By selectively restarting or stopping the supply of control signals such as pulses to the drive circuit, low power consumption is achieved. Electrification can be achieved.

[0567] Next, the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit section 1007 are An example of the configuration of the shift register that constitutes this is shown in FIG.

[0568] The shift register shown in FIG. 26A includes first pulse output circuits 10_1 to N-th pulse output circuits 10_2. The shift register shown in FIG. 26A has an output circuit 10_N (N is a natural number of 3 or more). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to the first wiring 1 1 transmits a first clock signal CK1, a second clock signal CK2 from the second wiring 12, and a third clock signal CK3 from the third wiring 13. The third clock signal CK3 is transmitted from the wiring 13, and the fourth clock signal CK 4 is supplied to the first pulse output circuit 10_1. The first start pulse SP1 (first start pulse) is input. In the output circuit 10_n (n is a natural number in the range of 2≦n≦N), A signal (called the previous stage signal OUT(n-1)) (n≧2 is a natural number) is input. The pulse output circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages later. Similarly, in the n-th pulse output circuit 10_n of the second stage or later, the (n The signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) ) is input. Therefore, the pulse output circuit of each stage outputs the pulse of the next stage and / or the two stages before. The first output signal (OUT(1)(SR) to OUT(N)( SR), the second output signal (OUT(1) to OUT(N)) is output, which is input to another circuit, etc. As shown in FIG. 26(A), the last two stages of the shift register are Since the subsequent signal OUT(n+2) is not input, for example, The second start pulse SP2 is output from the first wiring 18, and the third start pulse SP3 is output from the seventh wiring 19. Alternatively, a signal generated separately within a shift register may be input. For example, the (N+1)th pulse output circuit 10 that does not contribute to the pulse output to the pixel unit may be _(N+1), (N+2)-th pulse output circuit 10_(N+2) (also called dummy stage) ), the second start pulse (SP2) and the third start pulse (SP3) are output from the dummy stage. A signal equivalent to P3) may be generated.

[0569] The first clock signal (CK1) to the fourth clock signal (CK4) are generated at regular intervals. The first clock signal (CK1) through the fourth clock signal (CK2) are signals that alternate between H and L. The clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal CK controls the driving of the G It is also called CK or SCK, but here we will explain it as CK.

[0570] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be modified to include the connection relationships shown in the drawings or text. This also includes matters other than those in charge.

[0571] Each of the first pulse output circuit 10_1 to N-th pulse output circuits 10_N has a first input input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal It has an input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 26(B)). ).

[0572] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 26(A) and 26(B) are electrically connected to any one of the first to fourth wirings 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 _2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. is connected.

[0573] 26(A) and 26(B), the first pulse output circuit 10_1 has a fourth input terminal A start pulse is input to the fifth input terminal 24, and a subsequent signal OUT(3) is input to the fifth input terminal 25. The first output terminal 26 outputs the first output signal OUT(1)(SR), and the second output terminal 27 outputs the second output signal OUT(1)(SR). The second output signal OUT(1) is output from the input terminal 27.

[0574] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0575] In FIG. 26C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the power supply line 52. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 51 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 51, and the second terminal of the transistor 38 is electrically connected to the power supply line 51. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 51. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. do.

[0576] In FIG. 26C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is defined as a node NA. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is called a node Let's call it NB.

[0577] When the pulse output circuit in FIG. 26(C) is the first pulse output circuit 10_1, A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The subsequent signal OUT(3) is input, and the first output signal OUT(1) is output from the first output terminal 26. )(SR) is output, and the second output terminal 27 outputs the second output signal OUT(1). This will be the case.

[0578] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. 26(C) is A timing chart is shown in FIG. 27. When the shift register is a gate line driving circuit, In FIG. 27, period 61 corresponds to the vertical blanking period, and period 62 corresponds to the gate selection period.

[0579] As shown in Figures 26 and 27, a plurality of n-channel transistors are used. In the driver circuit, the operation of changing from a still image display to a moving image display or the operation of changing from a still image display to a moving image display This is the operation of rewriting the light to the TFT that drives the EL element (hereinafter referred to as the refresh operation). ) Refer to Figure 28 for the procedure for supplying or stopping the potential of each wiring to the drive circuit unit. FIG. 28 shows the wiring that supplies a high power supply potential (Vdd) to the shift register, A wiring for supplying a power supply potential (Vss), a wiring for supplying a start pulse (SP), and a first A wiring for supplying the fourth clock signal (CK1) through a wiring for supplying the fourth clock signal (CK4) FIG. 10 is a diagram showing changes in potential of a wiring before and after a period (T1).

[0580] In the display device of this embodiment, the display of moving images and still images or the refresh operation As a result, it is possible to display a still image without constantly operating the drive circuit section. As shown in FIG. 28, a high power supply potential (Vdd), a first clock signal, and a A fourth clock signal (CK1) to a fourth clock signal (CK4), and control signals such as a start pulse are provided. There is a period during which the control signal is supplied and a period during which the control signal is not supplied. 1 is a period during which a control signal is supplied, i.e., a period during which a moving image is displayed and a period during which a refresh operation is performed. The period T2 shown in FIG. 28 corresponds to the period during which the control signal is not supplied. That is, it corresponds to the period during which a still image is displayed.

[0581] In FIG. 28, the period during which the high power supply potential (Vdd) is supplied is not limited to the period T1. The first clock is set to a period T1 and a period T2. During the period in which the signal (CK1) to the fourth clock signal (CK4) are supplied, the high power supply potential (V dd) is supplied until the high power supply potential (Vdd) is stopped. There are.

[0582] As shown in FIG. 28, the first clock signal (CK1) to the fourth clock signal (CK 4) Before the period T1 begins, the signal is set to a high potential and then to a constant cycle of the clock signal. After the period T1 is over, the clock signal is set to a low potential and then the clock signal starts oscillating. It is sufficient to configure the process to end.

[0583] As described above, in the display device of this embodiment, a high power supply voltage is applied to the shift register during the period T2. a first clock signal (CK1) to a fourth clock signal (CK4), and The supply of control signals such as a start pulse is stopped. During this period, In this case, the signal output from the shift register is controlled by controlling the conduction or non-conduction of each transistor. Therefore, the power consumption and the pulse signal input to the shift register are reduced. The power consumed in the pixel unit driven by the shift register can be reduced. It becomes possible.

[0584] Please note that the above refresh operation may cause deterioration in the quality of the displayed still image. In the display device of this embodiment, the EL element provided in each pixel The above-mentioned oxide semiconductor is used as a switching element for controlling the voltage applied to the driving TFT. This allows for a significant reduction in off-state current. This reduces fluctuations in the voltage applied to the TFTs that drive the EL elements provided in each pixel. In other words, the operation of the shift register stops when a still image is displayed. Even if the period is long, the deterioration of the image quality can be reduced. Even if the duration is 3 minutes, the quality of the displayed still image can be maintained. For example, A display device that rewrites 60 times per second and refreshes once every 3 minutes Compared to display devices, it is possible to reduce power consumption to approximately 1 / 10,000.

[0585] The above-mentioned stopping of the high power supply potential (Vdd) means stopping the low power supply potential (Vs s), and the high power supply potential (Vdd) is stopped when the high power supply potential is supplied. The potential of the wiring to which the potential is supplied may be set in a floating state.

[0586] Note that the potential of the wiring to which the high power supply potential (Vdd) is supplied is increased, that is, When increasing the power supply potential from a low power supply potential (Vss) to a high power supply potential (Vdd), It is preferable to control the potential change so that it is gentle. If the change in potential is steep, it will become noise and an incorrect pulse will be output from the shift register. The shift register may be a shift register included in the gate line driving circuit. In some cases, the illegal pulse is a signal that turns on a transistor. The pulse changes the voltage applied to the TFT that drives the EL element, causing the image to change. In view of the above, in FIG. 28, the high power supply potential (Vdd) In particular, the rising edge of the signal is slower than the falling edge. In the display device of this embodiment, when a still image is displayed in the pixel section, The supply of high power supply potential (Vdd) to the load register is stopped and resupplied as needed. In other words, the change in the potential of the wiring that supplies the high power supply potential (Vdd) is reflected in the pixel as noise. If the noise affects the display area, it will directly lead to deterioration of the displayed image. In a display device, a change in the potential of the wiring (especially an increase in the potential) is reflected in the pixel area as noise. It is important to control the intrusion of [Explanation of symbols]

[0587] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 17 Wiring 18 Wiring 51 Power line 52 Power line 61 period 62 period 100 pixels 101 Wiring 102 Wiring 102A wiring 102B wiring 103 Oxide semiconductor layer 104 Capacitance Line 105 pixel electrode 106 Thin-film transistor 108 Substrate temperature 111 Substrate 112 Base film 113 Gate insulating film 114 Oxide insulating layer 121 Insulating layer 200 boards 201 pixels 202 Pixel section 203 Scanning line driving circuit 204 Signal line driver circuit 251 period 252 period 261 period 300 boards 302 Gate insulating layer 303 Protective Insulation Layer 310 Thin-film transistor 311 Gate electrode layer 313 Channel formation region 314a High-resistivity source region 314b High-resistivity drain region 315a Source electrode layer 315b drain electrode layer 316 Oxide insulating layer 320 board 322 Gate insulating layer 323 Protective Insulation Layer 330 Oxide semiconductor film 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 PCB 342 Gate insulating layer 343 Protective Insulation Layer 345 Oxide semiconductor film 346 Oxide semiconductor layer 350 Thin-Film Transistors 351 Gate electrode layer 352 Oxide semiconductor layer 355a Source electrode layer 355b drain electrode layer 356 Oxide insulating layer 360 Thin Film Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel formation region 364a High-resistance source region 364b High-resistivity drain region 365a Source electrode layer 365b drain electrode layer 366 Oxide insulating layer 370 PCB 372a Gate insulating layer 372b Gate insulating layer 373 Protective Insulation Layer 380 Thin Film Transistors 381 Gate electrode layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide insulating layer 390 Thin-Film Transistors 391 gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Film 394 PCB 395a Source electrode layer 395b Drain electrode layer 396 Oxide insulating layer 397 Gate insulating layer 398 Protective Insulation Layer 399 Oxide semiconductor layer 400 boards 402 Gate insulating layer 407 Insulating Layer 410 Thin Film Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Drain electrode layer 415b Drain electrode layer 420 silicon substrate 422 Insulating layer 423 Aperture 424 Conductive Layer 425 Thin-film transistor 427 Conductive Layer 438 Wiring layer 450 board 452 Gate insulating layer 457 Insulating Layer 460 Thin Film Transistor 461 Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Drain electrode layer 465a1 Drain electrode layer 465a2 Drain electrode layer 465b Drain electrode layer 468 Wiring layer 472a Gate insulating layer 1008 Pixel section 1009B Signal line driver circuit 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4542 Insulation layer 6400 pixels 6401 Switching transistor 6402 Drive transistor 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Driving TFT 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7011 Driving TFT 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7021 Driving TFT 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Conductive film 7029 Bulkhead 7030 Drain electrode layer 7031 Insulation layer 7033 Color Filter 7034 Overcoat layer 7035 Insulation layer 7040 Drain electrode layer 7041 Insulation layer 7043 Color Filter 7044 Overcoat layer 7045 Insulation layer 7051 Insulation layer 7053 Insulation layer 7055 Insulation layer 7211 Driving TFT 7212 Light-emitting element 7217 Conductive film 7230 Drain electrode 7231 Insulation layer 7233 Glow-in-the-dark layer 7234 Overcoat layer 7235 Insulation layer 9630 chassis 9631 Display section 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device

Claims

1. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region located on the second insulating layer and functioning as wiring; a fifth conductive layer having a region located on the second insulating layer and functioning as wiring; the fourth conductive layer is electrically connected to the second conductive layer through a first opening in the second insulating layer; the fifth conductive layer is electrically connected to the third conductive layer through a second opening in the second insulating layer; the first opening of the second insulating layer does not overlap with the oxide semiconductor layer; the second opening of the second insulating layer does not overlap with the oxide semiconductor layer; the first conductive layer has a region overlapping at least the entire oxide semiconductor layer, the first conductive layer has an overlap with the first opening in the second insulating layer; the first conductive layer has a laminated structure, the second conductive layer and the third conductive layer each have a single-layer structure containing titanium; the fourth conductive layer and the fifth conductive layer each have a laminated structure, the first insulating layer has a laminated structure of a first film having nitrogen and silicon, and a second film having an area located on the first film and having oxygen and silicon; The second insulating layer has a laminated structure of a third film having oxygen and silicon, and a fourth film having a region located on the third film and having nitrogen and silicon.

2. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region located on the second insulating layer and functioning as wiring; a fifth conductive layer having a region located on the second insulating layer and functioning as wiring; the fourth conductive layer is electrically connected to the second conductive layer through a first opening in the second insulating layer; the fifth conductive layer is electrically connected to the third conductive layer through a second opening in the second insulating layer; the first opening of the second insulating layer does not overlap with the oxide semiconductor layer; the second opening of the second insulating layer does not overlap with the oxide semiconductor layer; the first conductive layer has a region overlapping at least the entire oxide semiconductor layer, the first conductive layer has an overlap with the first opening in the second insulating layer; the fourth conductive layer has a region extending in a direction parallel to a channel length direction of the transistor, the fifth conductive layer has a region extending in a direction parallel to a channel length direction of the transistor, the first conductive layer has a laminated structure, the second conductive layer and the third conductive layer each have a single-layer structure containing titanium; the fourth conductive layer and the fifth conductive layer each have a laminated structure, the first insulating layer has a laminated structure of a first film having nitrogen and silicon, and a second film having an area located on the first film and having oxygen and silicon; The second insulating layer has a laminated structure of a third film having oxygen and silicon, and a fourth film having a region located on the third film and having nitrogen and silicon.

Images