Display board and manufacturing method thereof, and display device

Abstract

To provide a display board and its manufacturing method, and a display device.SOLUTION: A display board includes a base board, a shift register unit, a first clock signal line, and a second clock signal line. The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit. For the first pole of the voltage regulator transistor of the voltage regulator circuit of the shift register unit, a first source drain electrode layer has a first transfer electrode, the first transfer electrode has a first part and a second part, the first part is connected to the first pole of a first noise reduction transistor and the first pole of the voltage regulator transistor, and the second part is connected to the gate of the first control transistor of the first control circuit. The wiring of the shift register unit is simpler, and is advantageous to improvement of the space utilization rate of the display board, thus allowing realization of the narrow frame of the display board to be easier.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] In recent years, display devices have been developing rapidly. In particular, AMOLED (Active-matrix organic light-emitting diode) display devices have attracted attention due to their advantages such as bright colors, good viewing angles, high contrast, high response speeds, and low power consumption. AMOLED display devices have a wide application space in multiple display fields such as mobile displays, in-vehicle displays, and medical displays. Flexible AMOLED display devices are mainly applied to the field of deformable screen displays. With the gradual development of technology and the update of people's needs for display devices, more new challenges are faced in the shape design of the screen.

Summary of the Invention

Means for Solving the Problems

[0003] At least one embodiment of the present disclosure provides a display substrate. The display substrate includes a base substrate having a display area and a peripheral area located on at least one side of the display area, a shift register unit, a first clock signal line, and a second clock signal line disposed in the peripheral area of the base substrate. The first clock signal line and the second clock signal line extend along a first direction on the base substrate and are configured to provide a first clock signal and a second clock signal to the shift register unit, respectively. The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit. The input circuit is configured to input an input signal to a first node in response to the first clock signal. The first control circuit is connected to the first node and the second node and is configured to control the level of the second node in response to the level of the first node and the first clock signal. The second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal. The voltage regulator circuit is connected to the first node and a third node and is configured to stabilize the level of the third node. The output circuit is connected to the third node and is configured to output an output signal to an output terminal under the control of the level of the third node. The first control circuit includes a first control transistor, the second control circuit includes a first noise reduction transistor, and the voltage regulator circuit includes a voltage regulator transistor. The gate of the first control transistor, the first pole of the first noise reduction transistor, and the first pole of the voltage regulator transistor are all connected to the first node. The first pole of the first noise reduction transistor and the first pole of the voltage regulator transistor are located in a first source-drain electrode layer including a first transfer electrode. The first transfer electrode includes a first portion extending parallel to a second direction different from the first direction and a second portion integrally formed with the first portion and extending in the first direction.The first end of the first portion is connected to the first pole of the first noise reduction transistor, the second end of the first portion is connected to the first pole of the voltage regulator transistor, and the second portion is connected to the gate of the first control transistor that is not in the same layer.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the first transfer electrode further includes a third portion extending parallel to the second direction, the third portion is connected to the second portion, the third portion is arranged side by side with the first portion in the first direction, the input circuit includes an input transistor, and the orthographic projection of the active layer of the input transistor on the base substrate is located between the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the first noise reduction transistor on the base substrate, and the first pole of the input transistor is connected to the end of the third portion.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the first transfer electrode includes the first node.

[0006] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second transfer electrode, the first control circuit further includes a second control transistor, the second transfer electrode includes a first portion and a second portion parallel to the second direction, the end of the first portion of the second transfer electrode is connected to the first pole of the second control transistor, the second portion of the second transfer electrode is connected to the first pole of the first control transistor, and the second transfer electrode includes the second node.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projection of the active layer of the second control transistor on the base substrate is located on the side away from the display area of the orthographic projection of the active layer of the first control transistor on the base substrate.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the second control circuit further includes a second noise reduction transistor, an active layer of the second noise reduction transistor and an active layer of the first noise reduction transistor are located in a continuous first semiconductor layer, and the first semiconductor layer extends along a first direction. A gate of the second noise reduction transistor and a gate of the first noise reduction transistor extend in a second direction and are arranged side by side in the first direction. The display substrate further includes a first connection wiring and a second connection wiring that extend along the second direction. The first connection wiring and the second connection wiring are arranged in parallel. The first connection wiring and the second connection wiring overlap with the first transfer electrode respectively. A first end of the first connection wiring is connected to the gate of the second noise reduction transistor. A second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode that is not in the same layer. A first end of the second connection wiring is connected to the gate of the first noise reduction transistor. A second end of the second connection wiring is connected to the second clock signal line to receive the second clock signal.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, a positive projection of the active layer of the second noise reduction transistor and the active layer of the first noise reduction transistor on the base substrate is located closer to the display region than a positive projection of the active layer of the first control transistor on the base substrate.

[0010] For example, in the display substrate according to at least one embodiment of the present disclosure, the shift register unit further includes a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located between the active layer of the first control transistor and the gate of the first control transistor. The second insulating layer and the third insulating layer are located between the first transfer electrode and the gate of the first control transistor. The gate of the first control transistor is connected to a second portion of the first transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer. The second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer.

[0011] For example, in the display substrate according to at least one embodiment of the present disclosure, a positive projection of the active layer of the voltage regulator transistor on the base substrate is located on a side away from the display area of the positive projection of the active layer of the first control transistor on the base substrate.

[0012] For example, in the display substrate according to at least one embodiment of the present disclosure, an included angle between the first direction and the second direction is between 70° and 90°.

[0013] For example, in the display substrate according to at least one embodiment of the present disclosure, the first clock signal and the second clock signal line are located on a side away from the display area of the shift register unit.

[0014] For example, the display substrate according to at least one embodiment of the present disclosure further includes a first power line configured to provide a first voltage to the shift register unit. The first power line extends in the first direction on the base substrate and is connected to the second control circuit. A positive projection of the first power line on the base substrate is located on a side close to the display area of the positive projection of the shift register unit on the base substrate.

[0015] For example, the display substrate according to at least one embodiment of the present disclosure further includes a second power supply line, the second power supply line extends in the first direction on the base substrate, and is configured to provide a second voltage to the shift register unit. A positive projection of the second power supply line on the base substrate is located between positive projections of the first clock signal line and the second clock signal line on the base substrate and a positive projection of the shift register unit on the base substrate. A gate of the voltage regulator transistor is connected to the second power supply line to receive the second voltage.

[0016] For example, in the display substrate according to at least one embodiment of the present disclosure, the second power supply line includes a protruding portion protruding in the second direction, and a second pole of the second control transistor is connected to the protruding portion on the second power supply line to receive the second voltage.

[0017] For example, in the display substrate according to at least one embodiment of the present disclosure, the input transistor includes a first gate and a second gate arranged side by side. The first gate and the second gate of the input transistor are connected to a gate of the second control transistor, and the gate of the second control transistor is further connected to the first clock signal line. The first clock signal line provides the first clock signal to the gate of the second control transistor and the first gate and the second gate of the input transistor.

[0018] For example, the display substrate according to at least one embodiment of the present disclosure further includes a third transfer electrode extending in the first direction. A first end of the third transfer electrode is connected to the gate of the second control transistor and the first gate and the second gate of the input transistor through a via hole penetrating an insulating layer, and a second end of the third transfer electrode is connected to a second pole of the first control transistor.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the shift register unit further includes an output control circuit, and the output control circuit is configured to control the level of the output terminal by controlling according to the level of the second node. The output control circuit includes an output control transistor and a first capacitor. A positive projection of the first capacitor on the base substrate is located on a side closer to the display area of the positive projection of the active layer of the output control transistor on the base substrate, and the positive projection of the first capacitor on the base substrate at least partially overlaps with the positive projection of the first power line on the base substrate.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the shape of the first capacitor is rectangular.

[0021] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fourth transfer electrode. The fourth transfer electrode is connected to a first pole of the second noise reduction transistor and a first pole of the output control transistor. A gate of the second noise reduction transistor is connected to a gate of the output control transistor, and the fourth transfer electrode also includes the second node.

[0022] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fifth transfer electrode. The output circuit includes an output transistor and a second capacitor. A positive projection of the second capacitor on the base substrate is located on a side away from the display area of the positive projection of the first power line on the base substrate. A first pole of the output transistor is connected to a first end of the fifth transfer electrode, and a gate of the first noise reduction transistor is connected to the fifth transfer electrode through a via hole penetrating an insulating layer.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, the second capacitor is rectangular.

[0024] For example, a display substrate according to at least one embodiment of the present disclosure further includes a sixth transfer electrode extending along the second direction, where the gate of the output transistor is connected to a first end of the sixth transfer electrode through a via hole penetrating an insulating layer, a second end of the sixth transfer electrode is connected to a second pole of the voltage regulator transistor, and the sixth transfer electrode includes the third node.

[0025] For example, a display substrate according to at least one embodiment of the present disclosure further includes a seventh transfer electrode, a first end of the seventh transfer electrode is connected to a second pole of the output control transistor, a second end of the seventh transfer electrode is connected to a second pole of the output transistor, and the second pole of the output transistor is connected to a second pole of an input transistor of a lower shift register unit adjacent to the shift register unit.

[0026] For example, in a display substrate according to at least one embodiment of the present disclosure, at least a part of the active layer of the output control transistor and the active layer of the output transistor are located in a continuous second semiconductor layer, and the second semiconductor layer extends in the first direction. The gates of the output control transistor and the output transistor extend in the second direction and are arranged side by side in the first direction. A first pole of the output control transistor is connected to the first power line to receive the first voltage.

[0027] At least one embodiment of the present disclosure further provides a display device including the display substrate described in any of the above embodiments.

[0028] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, including the steps of: providing a base substrate including a display area and at least a peripheral area surrounding the display area; forming a shift register unit, a first clock signal line, a second clock signal line, a first power line, and a second power line in the peripheral area of the base substrate. In the step of forming, a semiconductor layer is formed on the base substrate, and the semiconductor layer is patterned to form active layers of a plurality of transistors of each circuit of the shift register; a first insulating material layer is formed on a side of the active layers of the plurality of transistors away from the base substrate, and the first insulating material layer is patterned to form a first insulating layer including via holes; a first conductive material layer is formed on a side of the first insulating layer away from the base substrate, and the first conductive material is patterned to form gates of the plurality of transistors, a plurality of connection wirings, and first electrodes of a plurality of capacitors of each circuit; a second insulating material layer is formed on a side of the gates of the plurality of transistors away from the base substrate, and the second insulating material layer is patterned to form a second insulating layer including via holes; a second conductive material layer is formed on a side of the second insulating layer away from the base substrate, and the second conductive material is patterned to form second electrodes of the plurality of capacitors; a third insulating material layer is formed on a side of the second insulating layer and the second capacitor electrode plates of the plurality of capacitors away from the base substrate, and the third insulating material layer is patterned to form a third insulating layer including via holes; a third conductive material layer is formed on a side of the third insulating layer away from the base substrate, and the third conductive material is patterned to form first and second electrodes of the plurality of transistors, a plurality of transfer electrodes, the first clock signal line, the second clock signal line, the first power line, and the second power line. The first and second electrodes of each transistor are connected to the active layer of each transistor through via holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer. Each of the transistors and each of the capacitors are connected through the plurality of connection wirings or the plurality of transfer electrodes, andThey are connected to each other via via holes penetrating through the second insulating layer and the third insulating layer, and are also connected to the first power line, the second power line, the first clock signal line, and the second clock signal line.

[0029] To clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

[0030]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0031] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, hereinafter, with reference to the drawings of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments of the present disclosure described, all other embodiments obtained by those skilled in the art without creative labor shall fall within the protection scope of the present disclosure.

[0032] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the present disclosure do not indicate any order, number, or importance, but are only used to distinguish different components. Similarly, similar terms such as "one", "1", or "the" do not limit the number, but mean that at least one exists. Similar terms such as "comprise" or "include" mean that the elements or members described before the term include the elements or members listed after the term and their equivalents, but do not exclude other elements or members. Similar terms such as "connect" or "couple" are not limited to physical or mechanical connections, and include electrical connections regardless of direct or indirect connections. "Above", "below", "left", "right", etc. are only used to indicate relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0033] The following describes the present disclosure by way of several specific embodiments. To ensure that the following description of the embodiments of the present invention is clear and concise, detailed descriptions of known functions and known members may be omitted. When any member of the embodiments of the present invention appears in one or more drawings, the member is represented by the same reference numeral in each drawing.

[0034] In the display technology field, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes a plurality of rows of grid lines and a plurality of columns of data lines intersecting the grid lines. The grid lines can be driven by a bound integrated drive circuit. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the grid line drive circuit can be directly integrated on the thin film transistor array substrate to form a gate driver on array (GOA) to drive the grid lines. For example, by using a GOA including a plurality of cascaded shift register units to provide a switching state voltage signal (scanning signal) to a plurality of rows of grid lines in the pixel array, for example, the plurality of rows of grid lines are controlled to be turned on in sequence, and a data signal is provided from the data line to the pixel units of the corresponding row in the pixel array to form the gradation voltage required for each gray scale of the display image formed in each pixel unit, and thus a frame image is displayed. The size of the GOA directly affects the size of the frame of the display panel. The smaller the frame of the display panel, the higher the screen occupation ratio, and thus the better the display effect. The overall circuit structure of the display panel will be described below with reference to the drawings.

[0035] FIG. 1A is a schematic diagram of the overall circuit structure of the display panel. For example, as shown in FIG. 1A, the display panel includes a base substrate 101, and the base substrate 101 includes a display area (i.e., a pixel array area) 102 and a peripheral area 106 located around the display area 102. For example, the peripheral area 106 surrounds the display area 102. The display area 102 includes pixel units 103 arranged in an array, and the peripheral area 106 includes shift register units 104. A plurality of cascaded shift register units 104 constitute a gate driving circuit to provide, for example, a gate scanning signal shifted row by row to the pixel units 103 arranged in the array in the display area 102 of the display panel. The peripheral area 106 further includes a light emission control unit 105. A plurality of cascaded light emission control units 105 constitute a light emission control array to provide, for example, a light emission control signal shifted row by row to the pixel units 103 arranged in the array in the display area 102 of the display panel.

[0036] As shown in FIG. 1A, the display panel further includes a data driving chip IC located in the peripheral area 106, and the data driving chip IC is configured to provide a data signal to the pixel units 103 arranged in the array. Data lines D1 - DN (where N is an integer greater than 1) connected to the data driving chip IC penetrate the display area 102 in the vertical direction (for example, the vertical direction in the figure) to provide data signals to the pixel units 103 in each column respectively. Grid lines G1 - GM (where M is an integer greater than 1) connected to the shift register units 104 penetrate the display area 102 in the horizontal direction (for example, the horizontal direction in the figure), and light emission control lines E1 - EM (where M is an integer greater than 1) connected to the light emission control units 105 penetrate the display area 102 in the horizontal direction to provide a gate scanning signal and a light emission control signal to the pixel units 103 arranged in the array.

[0037] For example, each pixel unit 103 may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art. The pixel circuit operates under the control of a data signal transmitted by a data line, a gate scanning signal transmitted by a grid line, and a light-emitting control signal transmitted by a light-emitting control line E1-EM to drive the light-emitting element to emit light and realize operations such as display. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0038] FIG. 1B is a circuit structure diagram of a shift register unit. FIG. 1C is a signal timing diagram when the shift register unit shown in FIG. 1B is operating. Hereinafter, the operation process of the shift register unit will be briefly described with reference to FIGS. 1B and 1C.

[0039] As shown in FIG. 1B, the shift register unit 104 includes eight transistors (input transistor T1, first control transistor T2, second control transistor T3, output control transistor T4, output transistor T5, first noise reduction transistor T7, second noise reduction transistor T6, and voltage regulator transistor T8) and two capacitors (first capacitor C1 and second capacitor C2). For example, when a plurality of shift register units 104 are cascade-connected, the second pole of the input transistor T1 in the first-stage shift register unit is connected to an input terminal IN configured to receive a trigger signal as an input signal through a trigger signal line GSTV (not shown), and the input terminal IN connected to the second pole of the input transistor T1 in each other stage of the shift register unit 104 (for example, excluding the first-stage shift register unit) is electrically connected to the output terminal of the previous-stage shift register unit 104 to receive the output signal output by the output terminal GOUT of the previous-stage shift register unit 104 as an input signal, whereby a shift output is realized to scan the array of pixel units 103 in the display area 102, for example, row by row.

[0040] Also, in the example shown in FIG. 1B, the shift register unit 104 further includes a first clock signal terminal CK and a second clock signal terminal CB. GCK represents the first clock signal line, and GCB represents the second clock signal line. For example, the first clock signal terminal CK is connected to the second clock signal line GCB or the first clock signal line GCK to receive the first clock signal. For example, when the first clock signal terminal CK is connected to the first clock signal line GCK, the first clock signal line GCK provides the first clock signal. When the first clock signal terminal CK is connected to the second clock signal line GCB, the second clock signal line GCB provides the first clock signal. Specifically, it is determined according to the actual situation, and the embodiments of the present disclosure do not limit this. The second clock signal terminal CB is connected to the second clock signal line GCB or the first clock signal line GCK to receive the second clock signal. Hereinafter, taking the case where the first clock signal terminal CK is connected to the first clock signal line GCK to receive the first clock signal and the second clock signal terminal CB is connected to the second clock signal line GCB to receive the second clock signal as an example for description, the embodiments of the present disclosure do not limit this. For example, the first clock signal line GCK and the second clock signal line GCB can use a pulse signal with a duty cycle greater than 50%, and the two are, for example, spaced at half-cycle intervals. VGH represents the first power line and the first voltage provided by the first power line. For example, the first voltage is a DC high level. VGL represents the second power line and the second voltage provided by the second power line. For example, the second voltage is a DC low level, and the first voltage is greater than the second voltage. N1, N2, and N3 represent the first node, the second node, and the third node in the circuit schematic diagram, respectively.

[0041] As shown in FIG. 1B, the gate of the input transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, the second pole of the input transistor T1 is connected to the input terminal IN, and the first pole of the input transistor T1 is connected to the first node N1. For example, when the shift register unit 104 is the first-stage shift register unit, the input terminal IN is connected to a trigger signal line GSTV (not shown) to receive a trigger signal. When the shift register unit 104 is a shift register unit of each stage other than the first stage, the input terminal IN is connected to the output terminal GOUT of the upper shift register unit.

[0042] The gate of the first control transistor T2 is connected to the first node N1, the second pole of the first control transistor T2 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, and the first pole of the first control transistor T2 is connected to the second node N2.

[0043] The gate of the second control transistor T3 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, the second pole of the second control transistor T3 is connected to the second power supply line VGL to receive the second voltage, and the first pole of the second control transistor T3 is connected to the second node N2.

[0044] The gate of the output control transistor T4 is connected to the second node N2, the first pole of the output control transistor T4 is connected to the first power supply line VGH to receive the first voltage, and the second pole of the output control transistor T4 is connected to the output terminal GOUT.

[0045] The first pole of the first capacitor C1 is connected to the second node N2, and the second pole of the first capacitor C1 is connected to the first power supply line VGH.

[0046] The gate of the output transistor T5 is connected to the third node N3, the first pole of the output transistor T5 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB), and the second pole of the output transistor T5 is connected to the output terminal GOUT.

[0047] The first pole of the second capacitor C2 is connected to the third node N3, and the second pole of the second capacitor C2 is connected to the output terminal GOUT.

[0048] The gate of the first noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB) to receive the second clock signal, and the first pole of the first noise reduction transistor T7 is connected to the first node N1.

[0049] The gate of the second noise reduction transistor T6 is connected to the second node N2, the first pole of the second noise reduction transistor T6 is connected to the first power supply line VGH to receive the first voltage, and the second pole of the second noise reduction transistor T6 is connected to the second pole of the first noise reduction transistor T7.

[0050] The gate of the voltage regulator transistor T8 is connected to the second power supply line VGL to receive the second voltage, the first pole of the voltage regulator transistor T8 is connected to the first node N1, and the second pole of the voltage regulator transistor T8 is connected to the third node N3.

[0051] The transistors in the shift register unit 104 shown in FIG. 1B are all described by taking P-type transistors as an example. That is, each transistor turns on (on level) when the gate is connected to a low level and turns off (off level) when connected to a high level. In this case, the first pole of the transistor may be the source electrode, and the second pole of the transistor may be the drain electrode. In other embodiments, the first pole and the second pole of the transistor can be exchanged.

[0052] The shift register unit includes, but is not limited to, the arrangement shown in FIG. 1B. For example, each transistor in the shift register unit 104 may be an N-type transistor, or a mixture of P-type and N-type transistors may be used. Together with this, the polarities of the ports of the selected type of transistor may be connected according to the polarities of the ports of the corresponding transistors in the embodiments of the present disclosure.

[0053] However, all the transistors used in the shift register unit may be thin film transistors or field effect transistors or other switching devices having the same characteristics. Here, thin film transistors are taken as an example for description. For example, the active layer (channel region) of the transistor may use semiconductor materials such as polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium zinc oxide (IGZO), etc., and the gate, source electrode, drain electrode, etc. may use metal materials such as metal aluminum or aluminum alloy. Since the source electrode and the drain electrode of the transistor used here may be symmetric in structure, there may be no structural distinction. In the embodiments of the present disclosure, in order to distinguish the two poles other than the gate of the transistor, it is directly described that one pole is the first pole and the other pole is the second pole. Also, in the embodiments of the present disclosure, the electrodes of the capacitor may use metal electrodes, or one of the electrodes may use a semiconductor material (such as doped polysilicon).

[0054] Figure 1C is a signal timing diagram when the shift register unit 104 shown in Figure 1B is operating. Hereinafter, the operation process of the shift register will be described in detail with reference to Figures 1B and 1C. For example, the operation principle of the shift register unit 104 will be described as an example, and the operation principles of the remaining shift register units 104 (excluding the first-stage shift register unit) of each stage are similar to it, and detailed descriptions are omitted here. However, the difference in the operation principles between the first-stage shift register unit and the shift register unit 104 is that the input end of the first-stage shift register unit is connected to the trigger signal line GSTV, and the input end of the shift register unit 104 is connected to the output end of the previous-stage shift register unit. As shown in Figure 1C, the operation process of the shift register unit 104 includes four stages, which are the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4, and the timing waveforms of each signal at each stage are shown in Figure 1C.

[0055] In the input stage t1, as shown in FIG. 1C, the first clock signal provided at the first clock signal terminal CK is a low-level signal, the second clock signal provided at the second clock signal terminal CB is a high-level signal, the input terminal IN receives a trigger signal (e.g., input signal Vin) provided by the output terminal of the previous shift register unit, and for example, the input signal Vin is equal to the low-level signal VL provided by the second power supply line VGL. Since the first clock signal is a low-level signal, the input transistor T1 is turned on, and the input signal is transmitted to the first node N1 through the input transistor T1. Since a threshold loss occurs when the input transistor T1 transmits a low-level signal, the voltage of the first node N1 is Vin - Vth1, that is, VL - Vth1, where Vth1 represents the threshold voltage of the input transistor T1. Since the gate of the voltage regulator transistor T8 receives the low-level signal VL provided by the second power supply line VGL, the voltage regulator transistor T8 is in an on state, and thereby, the voltage VL - Vth1 is transmitted to the third node N3 through the voltage regulator transistor T8. For example, the threshold voltage of the voltage regulator transistor T8 is represented by Vth8. Similarly, since a threshold loss occurs when the voltage regulator transistor T8 transmits a low-level signal, the voltage of the third node N3 is VL - VthN1, where VthN1 is the smaller one of Vth1 and Vth8. The voltage of the third node N3 controls the output transistor T5 to turn on, and the second clock signal is written to the output terminal GOUT through the output transistor T5 and used as an output signal. That is, in the input stage t1, the output signal is the high-level second clock signal, that is, the high-level signal VH provided by the first power supply line VGH.

[0056] In the input stage t1, since the first clock signal is a low-level signal, the second control transistor T3 is turned on, and the low-level signal VL provided by the second power line VGL is transmitted to the second node N2 through the second control transistor T3. Since the voltage of the first node N1 is VL - Vth1, the first control transistor T2 is turned on, and the low-level first clock signal is transmitted to the second node N2 through the first control transistor T2. For example, the threshold voltage of the first control transistor T2 is represented by Vth2, the threshold voltage of the second control transistor T3 is represented by Vth3. When Vth3 < Vth2 + Vth1, the voltage of the second node N2 is VL - Vth2 - Vth1; when Vth3 > Vth2 + Vth1, the voltage of the second node N2 is VL - Vth3. In this case, both the output control transistor T4 and the first noise reduction transistor T6 are turned on. Since the second clock signal is a high-level signal, the second noise reduction transistor T7 is turned off.

[0057] In the output stage t2, the first clock signal provided at the first clock signal terminal CK is a high-level signal, the second clock signal provided at the second clock signal terminal CB is a low-level signal, and the input signal Vin provided by the output terminal of the previous shift register unit received at the input terminal IN is a high-level signal. The output transistor T5 is turned on, and the second clock signal is written to the output terminal GOUT via the output transistor T5 and used as an output signal. In the input stage t1, the voltage at one end connected to the output terminal GOUT of the second capacitor C2 is the high-level signal VH provided by the first power supply line VGH, and the voltage at one end connected to the third node N3 of the second capacitor C2 is VL - VthN1. However, in the output stage t2, the voltage at one end connected to the output terminal GOUT of the second capacitor C2 becomes the low-level signal VL provided by the second power supply line VGL. Due to the bootstrap action of the second capacitor C2, the voltage at one end connected to the third node N3 of the second capacitor C2 becomes 2VL - VthN1 - VH, that is, the voltage of the third node N3 becomes 2VL - VthN1 - VH. In this case, the voltage regulator transistor T8 is turned off, and the output transistor T5 can be turned on more effectively, and the output signal is the low-level signal VL provided by the second power supply line VGL.

[0058] In the output stage t2, since the first clock signal is a high-level signal, both the input transistor T1 and the second control transistor T3 are turned off. The voltage of the first node N1 remains VL - VthN1, the first control transistor T2 is turned on, and the high-level first clock signal is transmitted to the second node N2 via the first control transistor T2, that is, the voltage of the second node N2 is the high-level signal VH. Thereby, both the output control transistor T4 and the second noise reduction transistor T6 are turned off. Since the second clock signal is a low-level signal, the first noise reduction transistor T7 is turned on.

[0059] In buffer stage t3, both the first clock signal provided at the first clock signal terminal CK and the second clock signal provided at the second clock signal terminal CB are high-level signals, and the input signal Vin provided by the output terminal of the previous shift register unit received by the input terminal IN is a high-level signal. The output transistor T5 is turned on, and the second clock signal is written to the output terminal GOUT via the output transistor T5 and used as an output signal. In this case, the output signal is the high-level second clock signal, i.e., the high-level signal VH. Due to the bootstrap action of the second capacitor C2, the voltage of the third node N3 becomes VL - VthN1.

[0060] In buffer stage t3, since the first clock signal is a high-level signal, both the input transistor T1 and the second control transistor T3 are turned off. The voltage of the third node N3 becomes VL - VthN1. In this case, the voltage regulator transistor T8 is turned on, and the voltage of the first node N1 is also VL - VthN1. The first control transistor T2 is turned on, and the high-level first clock signal is transmitted to the second node N2 via the first control transistor T2, i.e., the voltage of the second node N2 is the high-level signal VH, whereby both the second noise reduction transistor T6 and the output control transistor T4 are turned off. Since the second clock signal is a high-level signal, the second noise reduction transistor T7 is turned off.

[0061] In the first sub-stage t41 of the stabilization stage t4, the first clock signal provided at the first clock signal terminal CK is a low-level signal, the second clock signal provided at the second clock signal terminal CB is a high-level signal, and the input signal Vin provided by the output terminal of the previous shift register unit received at the input terminal IN is a high-level signal. For example, the input signal Vin is equal to the high-level signal VH provided by the first power supply line VGH. Since the first clock signal is a low-level signal, the input transistor T1 is turned on, and the input signal Vin is transmitted to the first node N1 through the input transistor T1. Since no threshold loss occurs when the input transistor T1 transmits a high-level signal, the voltage of the first node N1 is the input signal Vin (i.e., the high-level signal VH), and the first control transistor T2 is turned off. Since the voltage regulator transistor T8 is in the on state, the voltage of the third node N3 is the same as that of the first node N1, that is, the voltage of the third node N3 is VH, and the output transistor T5 is turned off. Since the first clock signal is a low-level signal, the second control transistor T3 is turned on, the voltage of the second node N2 is VL - Vth1, both the second noise reduction transistor T6 and the output control transistor T4 are turned on, and the high-level signal VH is transmitted to the output terminal GOUT through the output control transistor T4, that is, the output signal is the high-level signal VH.

[0062] In the second sub-stage t42 of the stabilization stage t4, the first clock signal provided at the first clock signal terminal CK is a high-level signal, the second clock signal provided at the second clock signal terminal CB is a low-level signal, and the input signal Vin provided by the output terminal of the previous shift register unit received at the input terminal IN is a high-level signal. The voltages of the first node N1 and the third node N3 are the input signal Vin (i.e., the high-level signal VH provided by the first power supply line VGH), and both the first control transistor T2 and the output transistor T5 are turned off. Since the first clock signal is a high-level signal, both the input transistor T1 and the second control transistor T3 are turned off, and due to the maintaining effect of the first capacitor C1, the voltage of the second node N2 remains VL-Vth3. Both the output control transistor T4 and the first noise reduction transistor T6 are turned on, and the high-level signal VH is transmitted to the output terminal GOUT through the output control transistor T4, and the output signal is the high-level signal VH.

[0063] In the second sub-stage t42, since the second clock signal is a low-level signal, the second noise reduction transistor T7 is turned on, and the high-level signal VH is transmitted to the third node N3 and the first node N1 through the first noise reduction transistor T6 and the second noise reduction transistor T7 so that the voltages of the first node N1 and the third node N3 are maintained at a high level.

[0064] In the third sub-stage t43 of the stabilization stage t4, both the first clock signal provided at the first clock signal terminal CK and the second clock signal provided at the second clock signal terminal CB are high-level signals, and the input signal Vin provided by the output terminal of the previous shift register unit received by the input terminal IN is a high-level signal. The voltages of the first node N1 and the third node N3 are high-level signals VH, and the first control transistor T2 and the output transistor T5 are turned off. Since the first clock signal is a high-level signal, both the input transistor T1 and the second control transistor T3 are turned off, the voltage of the second node N2 remains VL-Vth3, and both the output control transistor T4 and the first noise reduction transistor T6 are turned on. The high-level signal VH is transmitted to the output terminal GOUT through the output control transistor T4, and the output signal is a high-level signal VH.

[0065] FIG. 1D is a schematic layout diagram of the shift register unit 104 shown in FIG. 1B on the display substrate. As shown in FIG. 1D, the display substrate includes the input transistor T1 to the voltage regulator transistor T8 of the shift register unit 104, the first capacitor C1, the second capacitor C2, the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGH, and the second power supply line VGL.

[0066] For example, as shown in FIG. 1D, the voltage regulator transistor T8 is located on the side close to the display area of the first control transistor T2 and the second power supply line VGL (for example, the output terminal GOUT in FIG. 1D extends to the display area 102), and the first noise reduction transistor T7 and the second noise reduction transistor T6 are located on the side away from the display area of the first control transistor T2 and the second power supply line VGL. Therefore, it is necessary to connect the first pole of the voltage regulator transistor T8 and the first pole of the first noise reduction transistor T7 using one connection wiring and two transfer lines. Moreover, since the connection wiring further overlaps a plurality of wirings (for example, the second power supply line VGL, the active layer of the first control transistor T2, etc.), the circuit parasitic capacitance increases and the space utilization rate is very low. Note that the parasitic capacitance may include planar parasitic capacitance, spatial parasitic capacitance, and the like. In the display substrate, when the orthographic projections in the direction perpendicular to the base substrate of, for example, transfer electrodes, connection wirings, gates, etc., located in different layers overlap, planar parasitic capacitance can be formed. Also, when, for example, transfer electrodes, connection wirings, gates, etc., located in the same layer are arranged side by side and opposed in the planar direction, spatial parasitic capacitance (also called 3D parasitic capacitance) can be formed. The gate of the first noise reduction transistor T7 is connected to the first pole of the output transistor T5 and overlaps a plurality of wirings (for example, the first power supply line VGL, the transfer line between the first pole of the first control transistor T2 and the gate of T6), so the circuit parasitic capacitance and the complexity of the wirings increase. Therefore, due to the arrangement pattern and connection method of each transistor of the display substrate shown in FIG. 1D, the overlap of the wirings increases and the number of connection wirings increases. Conversely, the circuit parasitic capacitance and the complexity of the wirings increase, the space utilization rate decreases, the occupied space of the gate drive circuit increases, which is disadvantageous for realizing the narrow border design of the display panel. Also, due to unnecessary overlap, the parasitic capacitance becomes excessive, problems such as signal interference are likely to occur, and it affects the display quality of the display panel. Therefore, it is advantageous for improving the space utilization rate of the display panel with a more concise wiring layout of the gate drive circuit, thereby making it easier to realize the narrow border of the display panel, increase the screen occupation ratio, and achieve a better display effect.

[0067] At least one embodiment of the present disclosure provides a display substrate, the display substrate including a base substrate having a display area and a peripheral area located on at least one side of the display area, a shift register unit installed on the peripheral area of the base substrate, a first clock signal line, and a second clock signal line.The first clock signal line and the second clock signal line extend along a first direction on a base substrate and are each configured to provide a first clock signal and a second clock signal to a shift register unit. The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit. The input circuit is configured to input an input signal to a first node in response to the first clock signal. The first control circuit is connected to the first node and the second node and is configured to control the level of the second node in response to the level of the first node and the first clock signal. The second control circuit is connected to the first node and the second node and is configured to control the level of the first node under the control of the level of the second node and the second clock signal. The voltage regulator circuit is connected to the first node and a third node and is configured to stabilize the level of the third node. The output circuit is connected to the third node and is configured to output an output signal to an output terminal under the control of the level of the third node. The first control circuit includes a first control transistor. The second control circuit includes a first noise reduction transistor. The voltage regulator circuit includes a voltage regulator transistor. The gate of the first control transistor, the first pole of the first noise reduction transistor, and the first pole of the voltage regulator transistor are all connected to the first node. The first pole of the first noise reduction transistor and the first pole of the voltage regulator transistor are located in a first source-drain electrode layer. The first source-drain electrode layer includes a first transfer electrode. The first transfer electrode includes a first portion extending parallel to a second direction different from the first direction and a second portion integrally formed with the first portion and extending in the first direction. A first end of the first portion is connected to the first pole of the first noise reduction transistor. A second end of the first portion is connected to the first pole of the voltage regulator transistor. The second portion is connected to the gate of the first control transistor that is not in the same layer.

[0068] At least one embodiment of the present disclosure further provides a display device corresponding to the above display substrate and a method for manufacturing the display substrate.

[0069] The circuit connection and structural layout of the optimized shift register unit of the display substrate provided by the above embodiments of the present disclosure reduce the number and complexity of overlapping wirings of the shift register unit to a certain extent, increase the space utilization rate of the shift register unit, are advantageous for realizing the narrow bezel design of the display panel, and ensure the display quality of the display panel.

[0070] Hereinafter, embodiments and some examples of the present disclosure will be described in detail with reference to the drawings.

[0071] At least one embodiment of the present disclosure provides a display substrate. FIG. 2 is a schematic layout diagram of the shift register unit 104 shown in FIG. 1B on the display substrate.

[0072] For example, as shown in FIG. 2, the display substrate 1 includes a base substrate 101, a shift register unit 104 installed on the base substrate 101, a first power line VGH, a second power line VGL, and a plurality of clock signal lines (for example, the first clock signal line GCK and the second clock signal line GCB shown in the figure). For example, the first power line VGH, the second power line VGL, and the plurality of clock signal lines extend along the first direction X on the base substrate 10 and are configured to provide a first voltage, a second voltage, and a plurality of clock signals (for example, the first clock signal or the second clock signal, etc.) to the shift register unit 104 respectively.

[0073] It should be noted that the first power line VGH, the second power line VGL, and the plurality of clock signal lines may all be installed in parallel along the first direction X, or may intersect at a predetermined angle (for example, 20° or less) with each other. The embodiments of the present disclosure do not limit this.

[0074] However, extending in the first direction refers to the extending direction of the main lines of the first power line, the second power line, and the plurality of clock signal lines, and does not include protrusions or corners branched from the main lines of each signal line.

[0075] For example, the first power supply line VGH is configured to provide a first voltage to a plurality of cascaded shift register units 104 included in the gate driving circuit, and the second power supply line VGL is configured to provide a second voltage to the plurality of cascaded shift register units 104 included in the gate driving circuit. For example, the first voltage is greater than the second voltage. For example, the first voltage is a DC high level and the second voltage is a DC low level.

[0076] For example, the base substrate 101 can use, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure are not limited thereto.

[0077] For example, the display substrate 1 includes a pixel array region (i.e., the display region 102 shown in FIG. 1A, hereinafter referred to as the pixel array region 102) and a peripheral region 106 outside the pixel array region (shown in FIG. 1A). For example, the first power supply line VGH, the second power supply line VGL, the plurality of clock signal lines, and the shift register unit 104 are located within the peripheral region 106 and on one side of the base substrate 101 (located between the pixel array region 102 and the side of the base substrate 101 as shown in FIG. 1A), for example, located on the left side of the base substrate 101 as shown in FIG. 1A. Note that it may also be located on the right side or both the left and right sides of the base substrate 101, and the embodiments of the present disclosure are not limited thereto.

[0078] For example, the first clock signal line GCK and the second clock signal line GCB are located on the side away from the display area 102 of the shift register unit 104. For example, the orthographic projection of the first power supply line VGH on the base substrate 101 is located on the side closer to the display area 102 of the orthographic projection of the shift register unit 104 on the base substrate 101. For example, the orthographic projection of the second power supply line VGL on the base substrate 101 is located between the orthographic projection of the first clock signal line CGK and the second clock signal line CGB on the base substrate 101 and the orthographic projection of the shift register unit 104 on the base substrate 101. By arranging the wirings as described above, the connection between the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGL, the second power supply line VGH and other wirings of the shift register 104 can be facilitated.

[0079] Note that the positions of the wirings as described above are merely exemplary, and it is only necessary to realize that the installation of the wirings is advantageous for the connection to the shift register unit 104. The embodiments of the present disclosure are not limited thereto.

[0080] For example, the pixel array area 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel driving circuit, and may further include, for example, a light emitting element (not shown).

[0081] For example, a plurality of cascaded shift register units 104 constitute a gate driving circuit. For example, the output terminals GOUT of the plurality of shift register units 104 are respectively connected to the gate scanning signal terminals of the pixel driving circuits of each row located in the pixel array area 102 to provide output signals (for example, gate scanning signals) to the pixel circuits of each row, thereby realizing driving the light emitting element to emit light. For example, the pixel driving circuit may be a pixel circuit having a circuit structure such as 7T1C, 2T1C, 4T2C, 8T2C, etc. in the art, and detailed description thereof is omitted here.

[0082] FIG. 2 shows only a single-stage shift register unit 104 in the gate driving circuit. For example, as shown in FIG. 2, the first clock terminal CK (shown in FIG. 1B) of the shift register unit 104 is connected to the first clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB (shown in FIG. 1B) of the shift register unit 104 is connected to the second clock signal line GCB to receive the second clock signal. The first clock signal terminal CK of the shift register unit in the next stage of the shift register unit 104 is connected to the second clock signal line GCB to receive the first clock signal, and the second clock signal terminal CB is connected to the first clock signal line GCK to receive the second clock signal. Hereinafter, the same operation is performed in the same manner. For example, when the shift register unit 104 is used as the shift register unit in the next stage of the first-stage shift register unit, the first clock signal terminal CK of the shift register unit at the Xth (X is an even number greater than 1) stage is connected to the first clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB of the shift register unit at the Xth stage is connected to the second clock signal line GCB to receive the second clock signal. The first clock terminal CK of the shift register unit 104 at the (X - 1)th stage is connected to the second clock signal line GCB to receive the first clock signal, and the second clock signal terminal CB of the shift register unit 104 at the (X - 1)th stage is connected to the first clock signal line GCK to receive the second clock signal. However, the connection method between each stage of the shift register unit and the clock signal line may further use other connection methods in this field, and the embodiments of the present disclosure do not limit this. For example, the input terminal of the first-stage shift register unit is connected to the trigger signal line GSTV to receive the trigger signal as the input signal, and the input terminals of the other-stage shift register units are connected to the output terminal GOUT of the previous-stage shift register unit (for example, the input terminal of the second-stage shift register unit is the first-stage shift register unit). Hereinafter, the structure of the shift register unit 104 shown in FIG. 2 is taken as an example for description, and the embodiments of the present disclosure do not limit this.

[0083] For example, as shown in FIG. 1B, in some examples, the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, a second control circuit 1045, and a voltage regulator circuit 1046. In some other examples, the shift register unit 104 further includes an output control circuit 1044.

[0084] The input circuit 1041 is configured to input an input signal to a first node N1 in response to a first clock signal. For example, the input circuit 1041 is connected to an input terminal IN, a first node N1, and a first clock signal terminal CK. The first clock signal terminal CK is turned on under the control of the received first clock signal, connects the input terminal IN to the first node N1, and is thus configured to input the input signal to the first node N1. For example, the input circuit 1041 is implemented as the input transistor T1 described above, and the connection method of the input transistor T1 can be referred to the above description, and the detailed description is omitted here.

[0085] The output circuit 1043 is connected to a third node N3 and is configured to output an output signal to an output terminal GOUT. For example, the output circuit 1043 is connected to a third node N3, an output terminal GOUT, and a second clock signal terminal CB. It is turned on under the control of the level of the third node N3, connects the second clock signal terminal CB and the output terminal GOUT, and outputs a second clock signal to the output terminal GOUT. For example, it is configured to output a low level of the second clock signal. For example, the output circuit 1043 is implemented as the output transistor T5 and the second capacitor C2, and the connection method between the output transistor T5 and the second capacitor C2 can be referred to the above description, and the detailed description is omitted here.

[0086] The first control circuit 1042 is connected to the first node N1 and the second node N2, and is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal. For example, the first control circuit is connected to the first node N1, the second node N2, and the first clock signal terminal CK, and is turned on by the control of the level of the first node N1, and connects the second node N2 to the first clock signal terminal CK, thereby providing the first clock signal provided by the first clock signal terminal CK to the second node N2. For example, the first control circuit 1042 is implemented as the first control transistor T2 and the second control transistor T3, and the connection method between the first control transistor T2 and the second control transistor T3 can refer to the above description, and the detailed description is omitted here. However, the first control circuit 1042 is not limited to being connected to the first node N1, and may be connected to another independent voltage terminal (providing the same voltage as the voltage of the first node N1) or separately installed and connected to the same circuit as the input circuit, and the embodiments of the present disclosure do not limit this. The connection of other circuits of the shift register unit is similar thereto, and the detailed description is omitted here.

[0087] The second control circuit 1045 is connected to the first node N1 and the second node N2, and is configured to control the level of the first node N1 under the control of the level of the second node N2 and the second clock signal. For example, the second control circuit 1045 is connected to the first node N1, the second node N2, the first power supply line VGH, and the second clock signal terminal CB. The level of the second node N2 and the second clock signal terminal CB are turned on under the control of the received second clock signal, connecting the first power supply line VGH to the first node N1, thereby charging the potential of the first node N1 to a high level, avoiding the output circuit 1042 from being turned on in the non-output stage, and configured to avoid incorrect output. For example, the second control circuit 1045 is implemented as the above-mentioned first noise reduction transistor T6 and second noise reduction transistor T7. The connection method between the first noise reduction transistor T6 and the second noise reduction transistor T7 can refer to the above description, and detailed description is omitted here.

[0088] The voltage regulator circuit 1046 is connected to the first node N1 and the third node N3, and is configured to stabilize the level of the third node N3. For example, the voltage regulator circuit 1046 is connected to the first node N1, the third node N3, and the second power supply line VGL. It is turned on under the control of the second voltage provided by the second power supply line VGL, and is configured to connect the first node N1 and the third node N3. For example, the voltage regulator circuit 1046 is implemented as a voltage regulator transistor T8. For specific description, reference can be made to the description of the voltage regulator transistor T8 in FIG. 1B above, and detailed description is omitted here.

[0089] The output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2. For example, the output control circuit 1044 is connected to the second node N2, the first power supply line VGH, and the output terminal GOUT. Under the control of the level of the second node N2, the output terminal GOUT is connected to the first power supply line VGH, and the first voltage provided by the first power supply line VGH is output to the output terminal GOUT to control the output terminal GOUT to a high level, thereby avoiding incorrect output in the non-output stage of the shift register unit. For example, the output control circuit 1044 is implemented as the above output control transistor T4 and the first capacitor C1. The connection method between the output control transistor T4 and the first capacitor C1 can be referred to the above description, and the detailed description is omitted here.

[0090] For example, the voltage regulator transistor T8 is always in the on state under the control of the second voltage provided by the second power supply line VGL, so that the third node N3 is connected to the first node N1 through the voltage regulator transistor T8, and the level of the third node N3 is prevented from leaking through the input transistor T1, the first control transistor T2, and the second noise reduction transistor T7 connected to the first node N1, and at the same time, the stress of the level of the third node N3 on the first control transistor T1 is reduced, which is beneficial to maintaining the level of the third node N3, so that the output transistor T5 can be fully turned on in the output stage.

[0091] FIG. 3, FIG. 4, FIG. 5, and FIG. 7 respectively show a plan view of each layer wiring of the shift register unit of the display substrate shown in FIG. 2, and FIG. 6 shows a distribution diagram of via holes of the shift register unit of the display substrate shown in FIG. 2. FIG. 3 is a plan view of the semiconductor layer of the display substrate according to at least one embodiment of the present disclosure, FIG. 4 is a plan view of the first conductive layer of the display substrate according to at least one embodiment of the present disclosure, FIG. 5 is a plan view of the second conductive layer of the display substrate according to at least one embodiment of the present disclosure, FIG. 6 is a distribution diagram of via holes of the display substrate according to at least one embodiment of the present disclosure, FIG. 7 is a plan view of the third conductive layer of the display substrate according to at least one embodiment of the present disclosure, and FIG. 8 is a cross-section along the A-B direction of the display substrate shown in FIG. 2.

[0092] For example, the display substrate 1 further includes a first insulating layer 350 (for example, a first gate insulating layer), a second insulating layer 360 (for example, a second gate insulating layer), and a third insulating layer 370 (for example, an interlayer insulating layer), and is located between the layer structures shown in FIGS. 3, 4, 5, and 7. For example, the first insulating layer 350 (shown in FIG. 8) is located between the semiconductor layer 310 shown in FIG. 3 and the first conductive layer 320 shown in FIG. 4, the second insulating layer 360 (shown in FIG. 8) is located between the first conductive layer 320 shown in FIG. 4 and the second conductive layer 330 shown in FIG. 5, and the third insulating layer 370 (shown in FIG. 8) is located between the second conductive layer 330 shown in FIG. 5 and the third conductive layer 340 shown in FIG. 7.

[0093] For example, as shown in FIG. 8, the display substrate 1 further includes a fourth insulating layer 380, which is located on the third conductive layer 340 and is used to protect the third conductive layer 340.

[0094] For example, as shown in FIG. 8, the display substrate 1 further includes a barrier layer 390 and a buffer layer 3100. The buffer layer 3100 is located on the side closer to the base substrate 101 of the first insulating layer 350, and the barrier layer 390 is located between the buffer layer 3100 and the base substrate 101. The barrier layer 390 and the buffer layer 3100 can provide a flat surface for forming the gate driving circuit, and can avoid impurities that may exist in the base substrate 101 from diffusing into the gate driving circuit and affecting the performance of the display substrate.

[0095] For example, one or more of the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, the fourth insulating layer 380, the barrier layer 390, and the buffer layer 3100 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, and the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, the fourth insulating layer 380, the barrier layer 390, and the buffer layer 3100 may be the same or different, and the embodiments of the present disclosure do not limit this.

[0096] Note that the display substrate shown in FIG. 2 is described by taking the layout design of a certain stage of the shift register in the gate driving circuit and the first power line, the second power line, and the signal line connected thereto as an example. The implementation forms of the layouts of the remaining stages of the shift register can refer to the layout mode shown in FIG. 2, and detailed descriptions are omitted here. Of course, other layout modes may also be used, and the embodiments of the present disclosure do not limit this. Of course, each stage of the shift register in the remaining gate driving circuits may refer to the layout mode shown in FIG. 2, or other layout modes may also be used, and the embodiments of the present disclosure do not limit this.

[0097] Hereinafter, with reference to FIGS. 2 to 8, the display substrate according to at least one embodiment of the present disclosure will be described in detail.

[0098] For example, the active layers A1 of the input transistor T1 to the active layer A8 of the voltage regulator transistor T8 shown in FIG. 2 may be formed by the semiconductor layer 310 shown in FIG. 3. The semiconductor layer 310 may be formed by patterning a semiconductor material. For example, as shown in FIG. 3, the semiconductor layer 310 may be in a short rod shape, curved, or bent shape as needed, and is used to manufacture the active layers A1 of the input transistor T1 to the active layer A8 of the voltage regulator transistor T8. Each active layer can include a source electrode region, a drain electrode region, and a channel region located between the source electrode region and the drain electrode region. For example, the channel region has semiconductor characteristics, and the source electrode region and the drain electrode region are located on both sides of the channel region and are doped with impurities, so they have conductivity. For example, the source electrode region is a part of the active layer, and the metal electrode (for example, the one located in the third conductive layer 340) in contact with the source electrode region corresponds to the source electrode (or the first pole) of the transistor. The drain electrode region is a part of the active layer, and the metal electrode (for example, the one located in the third conductive layer 340) in contact with the drain electrode region corresponds to the drain electrode (or the second pole) of the transistor. For example, the source electrode region is connected to the corresponding metal electrode (the first pole) through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370, and the drain electrode region is connected to the corresponding metal electrode (the second pole) through a via hole penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0099] For example, as shown in FIG. 3, taking the first control transistor T2 as an example, the active layer A2 of the first control transistor T2 includes a source electrode region S2, a drain electrode region D2, and a channel region P2. For example, as shown in FIG. 4, the first control transistor T2 further includes a gate G2, where the gate G2 is located in the first conductive layer 320. Taking the voltage regulator transistor T8 as an example, as shown in FIG. 3, the active layer A8 of the voltage regulator transistor T8 includes a source electrode region S8, a drain electrode region D8, and a channel region P8. For example, as shown in FIG. 4, the voltage regulator transistor T8 further includes a gate G8, where the gate G8 is located in the first conductive layer 320. Since other transistors are similar thereto, detailed description thereof is omitted here.

[0100] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polysilicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon, etc. The embodiments of the present disclosure are not limited thereto. However, the source electrode region and the drain electrode region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited thereto.

[0101] In addition, in some other examples, the first pole and the second pole of each transistor may be located in other conductive layers and are connected to the corresponding active layer through via holes in the insulating layer located between them and the semiconductor layer. The embodiments of the present disclosure are not limited thereto.

[0102] FIG. 4 shows the first conductive layer 320 of the display substrate. Since the first conductive layer 320 is disposed on the first insulating layer 350, it is insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include the first electrode CE11 of the first capacitor C1, the first electrode CE21 of the second capacitor C2, the gates G1 to G8 of the input transistor T1 to the voltage regulator transistor T8, and each wiring directly connected to the gates (for example, the first connection wiring L1 and the second connection wiring L2). As shown in FIG. 4, the gates G1 to G8 of the input transistor T1 to the voltage regulator transistor T8 are the portions surrounded by the broken lines, that is, the portions where the semiconductor layer structure of each transistor overlaps with the wiring on the first conductive layer 320.

[0103] For example, the material of the first conductive layer 320 may include a metal material or an alloy material, and is, for example, a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a structure in which a plurality of metal layers are stacked (for example, a structure in which three metal layers of titanium, aluminum, and titanium are stacked (Ti / Al / Ti)).

[0104] FIG. 5 shows the second conductive layer 330 of the display substrate. The second conductive layer 330 is disposed on the second insulating layer 360, thereby being insulated from the first conductive layer 320. The second conductive layer 330 includes the second electrodes CE12 to CE22 of the first capacitor C1 to the second capacitor C2. The second electrode CE12 overlaps at least partially with the first electrode CE11 to form the first capacitor C1, and the second electrode CE22 overlaps at least partially with the first electrode CE21 to form the second capacitor C2.

[0105] For example, the material of the second conductive layer 330 may include a metal material or an alloy material, and is, for example, a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a stacked structure in which a plurality of metal layers are stacked (for example, a structure in which three metal layers of titanium, aluminum, and titanium are stacked (Ti / Al / Ti)).

[0106] FIG. 7 shows the third conductive layer 340 of the display substrate, and the second conductive layer 330 is disposed on the third insulating layer 360, thereby being insulated from other conductive layers. The third conductive layer 340 includes a plurality of signal lines (for example, the first clock signal line GCK and the second clock signal line GCB), the first power supply line VGH, the second power supply line VGL, and the like. However, the third conductive layer 340 further includes a first pole (for example, a source electrode connected to the source electrode region of the active layer) and a second pole (for example, a drain electrode connected to the drain electrode region of the active layer) of each transistor, and is connected to the first transfer electrode E1, the second transfer electrode E2, the third transfer electrode E3, the fourth transfer electrode E4, the fifth transfer electrode E5, the sixth transfer electrode E6, the seventh transfer electrode E7, etc. between each transistor, capacitor, and signal line.

[0107] For example, the material of the third conductive layer 340 may include a metal material or an alloy material, and is, for example, a single-layer or multi-layer structure of a metal formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a laminated structure in which a plurality of metal layers are laminated (for example, a structure in which three metal layers of titanium, aluminum, and titanium are laminated (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0108] As shown in FIGS. 3, 4, 5, and 7, the plurality of signal lines, the first power supply line VGH, and the second power supply line VGL are connected to the transistors and capacitors to be connected thereto in each of the remaining layers through at least one via hole shown in FIG. 6, and are also connected between each transistor and capacitor through at least one via hole, or are bridged through a transfer electrode, and detailed description thereof is omitted here.

[0109] FIG. 2 is a schematic diagram showing the laminated positional relationship of the semiconductor layer 310 shown in FIG. 3 above, the first conductive layer 320 shown in FIG. 4, the second conductive layer 330 shown in FIG. 5, and the third conductive layer 340 shown in FIG. 7, and their connection through a plurality of via holes shown in FIG. 6.

[0110] As shown in FIG. 2, the gate G2 of the first control transistor T2 (shown in FIG. 4), the first pole SD71 of the first noise reduction transistor T7 (shown in FIG. 7), and the first pole SD81 of the voltage regulator transistor T8 (shown in FIG. 7) are all connected to the first node N1. The first pole SD71 of the first noise reduction transistor T7 (shown in FIG. 7) and the first pole SD81 of the voltage regulator transistor T8 (shown in FIG. 7) are both located in the first source-drain electrode layer, and the first source-drain electrode layer includes the first transfer electrode E1 (shown in FIG. 7). That is, the first pole SD71 of the first noise reduction transistor T7 (shown in FIG. 7) and the first pole SD81 of the voltage regulator transistor T8 (shown in FIG. 7) are located in and integrally formed with the first source-drain electrode layer that is continuous with the first transfer electrode E1 (shown in FIG. 7), thereby reducing the number of wirings and improving the space occupancy rate of the display substrate.

[0111] For example, as shown in FIGS. 3, 6, and 7, the first pole SD71 of the first noise reduction transistor T7 is connected to the active layer A7 of the first noise reduction transistor T7 through a via hole H71 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first pole SD81 of the voltage regulator transistor T8 is connected to the active layer A8 of the voltage regulator transistor T8 through a via hole H81 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0112] For example, as shown in FIG. 7, the first source-drain electrode layer is located in the third conductive layer 340 of the display substrate.

[0113] For example, as shown in FIG. 7, the first transfer electrode E1 includes a first portion E11 extending parallel to a second direction Y different from the first direction X, and a second portion E12 integrally formed with the first portion and extending in the first direction. The first end of the first portion E11 is connected to the first pole SD71 of the first noise reduction transistor T7, and the second end of the first portion E11 is connected to the first pole SD81 of the voltage regulator transistor T8. The second portion E12 is connected to the gate G2 of the first control transistor T2 that is not in the same layer (shown in FIG. 4). However, the positions of the first end of the first portion E11 and the first pole SD71 of the first noise reduction transistor T7 are considered to be the same, that is, they are integrally formed. Therefore, the symbol of the first end of the first portion E11 is not shown in FIG. 7. Similarly, the symbol of the second end of the first portion E11 is not shown in FIG. 7.

[0114] For example, as shown in FIGS. 4, 6, and 7, the second portion E12 of the first transfer electrode E1 is connected to the gate G2 of the first control transistor T2 through a via hole GH1 penetrating the second insulating layer 360 and the third insulating layer 370.

[0115] For example, as shown in FIGS. 2 and 7, the first transfer electrode E1 is a broken line located between the first noise reduction transistor T7, the voltage regulator transistor T8, and the first control transistor T2 and extending along the first direction X and the second direction Y. One end (i.e., the first end of the first portion E11) of the first portion E11 of the first transfer electrode E1 extending in the second direction Y is the first pole SD71 of the first noise reduction transistor T7, and the other end (i.e., the second end of the first portion E11) of the first portion E11 of the first transfer electrode E1 extending in the second direction Y is the first pole SD81 of the voltage regulator transistor T8. The second portion E12 of the first transfer electrode E1 extending along the first direction X is drawn out from the first portion of the first transfer electrode E1, and the second portion of the first transfer electrode E1 is connected to the gate of the first control transistor T2, so that the first portion E11 and the second portion E12 form a substantially inverted "T" shape. Since the first portion E11 of the first transfer electrode E1 extending in the second direction Y is connected to the first pole SD71 of the first noise reduction transistor T7 and the first pole SD81 of the voltage regulator transistor T8, and the second portion E12 of the first transfer electrode E1 is connected to the gate G2 of the first control transistor T2, the number of transfer electrodes and the complexity of the wiring can be reduced, the space utilization rate of the display substrate can be improved, and the generation of parasitic capacitance of the display substrate can be reduced. As shown in FIG. 2, the first transfer electrode E1 can reduce the generation of parasitic capacitance (e.g., spatial parasitic capacitance) by separating the first pole SD71 of the first noise reduction transistor T7 and the first pole SD81 of the voltage regulator transistor T8 far apart in the second direction Y. The first transfer electrode E1 can reduce the generation of parasitic capacitance (e.g., spatial parasitic capacitance) by separating the gate of the first control transistor T2 from the first noise reduction transistor T7 and the voltage regulator transistor T8 far apart in the first direction X.

[0116] For example, in other embodiments, as shown in FIGS. 2 and 7, the position of the voltage regulator transistor T8 can be moved closer to the first noise reduction transistor T7. If necessary, the length of the output transistor T5 in the second direction Y can be shortened so that the first pole SD81 of the voltage regulator transistor T8 and the second portion E12 of the first transfer electrode E1 are positioned on a straight line along the first direction X. In such a case, the second portion E12 and the first portion E11 of the first transfer electrode E1 can be formed in an "L" shape, reducing the number of transfer electrodes and the complexity of the wiring, and realizing an improvement in the space utilization rate of the display substrate. However, since the distance between the voltage regulator transistor T8, the first noise reduction transistor T7, and the output transistor T5 is shortened, compared with the structure shown in FIG. 2, the parasitic capacitance in the space between the voltage regulator transistor T8, the first noise reduction transistor T7, and the output transistor T5 may increase. The first transfer electrode E1 of the embodiments of the present disclosure is not limited to the inverted "T" shape shown in FIG. 2.

[0117] For example, the included angle between the first direction and the second direction is between 70° and 90°, including 70° and 90°. For example, the included angle between the first direction and the second direction is 70°, 90°, or 80°, etc., and can be set according to the actual situation, and the embodiments of the present disclosure do not limit this. For example, the included angle between the first direction and the second direction may further be 75°, 85°, etc.

[0118] For example, as shown in FIG. 3, the orthographic projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101 is located closer to the display region 102 of the orthographic projection of the active layer A2 of the first control transistor T2 on the base substrate 101. That is, in the first direction Y, the active layer A7 of the first noise reduction transistor T7 is located on the right side of the active layer A2 of the first control transistor T2. For example, the orthographic projection of the active layer A8 of the voltage regulator transistor T8 on the base substrate 101 is located on the side away from the display region 102 of the orthographic projection of the active layer A2 of the first control transistor T2 on the base substrate 101. That is, in the first direction Y, the active layer A8 of the voltage regulator transistor T8 is located on the left side of the active layer A2 of the first control transistor T2. Thereby, the complexity of the wiring of the first transfer electrode E1 can be reduced, the space utilization rate of the display substrate can be improved, and the overlap between the first transfer electrode E1 and other wirings can be reduced.

[0119] For example, in other embodiments, the orthographic projection of the active layer A8 of the voltage regulator transistor T8 on the base substrate 101 may be further located between the orthographic projection of the active layer A2 of the first control transistor T2 on the base substrate 101 and the orthographic projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101, and the embodiments of the present disclosure are not limited thereto.

[0120] For example, as shown in FIG. 7, the first transfer electrode E1 further includes a third portion E13 extending parallel to the second direction Y. The third portion E13 is connected to the second portion E12 (that is, the third portion E13 extends from the second portion E12 in a direction close to the input transistor T1 along the second direction Y), and the third portion E13 and the first portion E11 are arranged side by side in the first direction. The first pole SD11 of the input transistor T1 is connected to the end of the third portion E13. However, the position of the end of the third portion E13 and the first pole SD11 of the input transistor T1 is regarded as the same, that is, integrally formed, and therefore, the symbol of the end of the third portion E13 is not shown in FIG. 7.

[0121] For example, the third portion E13 of the first transfer electrode E1 may not be parallel to the second direction Y. For example, the third portion E13 of the first transfer electrode E1 intersects the second direction Y at a predetermined angle. For example, the intersecting angle is 20° or less.

[0122] For example, in other embodiments, as shown in FIGS. 2 and 7, the input transistor T1 may be moved in a direction closer to the first control transistor T2. The first pole SD11 of the input transistor T1 and the second portion E12 of the first transfer electrode E1 are located on a straight line along the first direction X. In such a case, the first pole SD11 of the input transistor T1 can be directly connected to the second portion E12 of the first transfer electrode E1, eliminating the need to design the third portion E13 of the first transfer electrode E1. Similarly, the complexity of the wiring of the first transfer electrode E1 can be reduced, the space utilization rate of the display substrate can be improved, and the overlap between the first transfer electrode E1 and other wirings can be reduced. However, when the distance between the input transistor T1 and the first control transistor T2 and the second control transistor T3 is shortened, compared with the structure shown in FIG. 2, the parasitic capacitance in the space between the input transistor T1 and the first control transistor T2 and the second control transistor T3 may increase.

[0123] For example, as shown in FIGS. 3, 6, and 7, the first pole SD11 of the input transistor T1 is connected to the active layer A1 of the input transistor T1 through a via hole H11 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0124] For example, as shown in FIG. 3, the orthographic projection of the active layer A1 of the input transistor T1 on the base substrate 101 is located between the orthographic projection of the active layer A2 of the first control transistor T2 on the base substrate 101 and the orthographic projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101. That is, the active layer A1 of the input transistor T1 is located between the active layer A2 of the first control transistor T2 and the active layer A7 of the first noise reduction transistor T7 in the second direction Y. Thereby, the overlap between the third portion E13 of the first transfer electrode E1 and other wirings is reduced, and the complexity of the wiring is reduced, so that the wiring of the shift register unit becomes more compact, saving space and reducing the generation of parasitic capacitance.

[0125] For example, as shown in FIGS. 2 and 7, the first transfer electrode E1 includes a first node N1. For example, the first transfer electrode E1 is implemented as the first node N1 and is used to connect the first pole SD71 of the first noise reduction transistor T7, the first pole SD81 of the voltage regulator transistor T8, and the gate G2 of the first control transistor T2 (shown in FIG. 4). For example, the first transfer electrode E1 is located in the third conductive layer 340.

[0126] For example, as shown in FIGS. 2 and 7, the display substrate further includes a second transfer electrode E2. The second transfer electrode E2 includes a first portion E21 extending along the first direction X and a second portion E22 parallel to the second direction Y. The second portion E22 extends from the first portion E21, and the second portion E22 and the first portion E21 form a substantially "L" shape. Thereby, the end of the first portion E21 of the second transfer electrode E2 is connected to the first pole SD31 of the second control transistor T3, and the second portion E22 of the second transfer electrode E2 is connected to the first pole SD21 of the first control transistor T2. Since the installation form of the second transfer electrode E2 does not need to overlap other wirings, the generation of parasitic capacitance is reduced. However, the position of the end of the first portion E21 is regarded as the same as the position of the first pole SD31 of the second control transistor T3, that is, they are integrally formed. Therefore, the symbol of the end of the first portion E21 is not shown in FIG. 7.

[0127] For example, the second portion E22 of the second transfer electrode E2 may not be parallel to the second direction Y. For example, the second portion E22 of the second transfer electrode E2 and the second direction Y intersect at a predetermined angle. For example, the intersection angle is 20° or less.

[0128] For example, as shown in FIGS. 3, 6, and 7, the first pole SD31 of the second control transistor T3 is connected to the active layer A3 of the second control transistor T3 through a via hole H31 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first pole SD21 of the first control transistor T2 is connected to the active layer A2 of the first control transistor T2 through a via hole H21 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0129] For example, as shown in FIGS. 2 and 7, the second transfer electrode E2 includes a second node N2. For example, the second transfer electrode E2 is implemented as the second node N2 and is used to connect the first pole SD31 of the second control transistor T3 and the first pole SD31 of the second control transistor T3. For example, the second transfer electrode E2 is located in the third conductive layer 340.

[0130] For example, as shown in FIG. 3, the orthographic projection of the active layer A3 of the second control transistor T3 on the base substrate 101 is located on the side away from the display region 101 of the orthographic projection of the active layer A2 of the first control transistor T2 on the base substrate 101. That is, in the second direction Y, the active layer A3 of the second control transistor T3 is located on the left side of the active layer A2 of the first control transistor T2. Thereby, the complexity of the wiring of the second transfer electrode E2 can be reduced, the space utilization rate of the display substrate can be improved, and the overlap between the second transfer electrode E2 and other wirings can be reduced.

[0131] For example, as shown in FIG. 3, the active layer A6 of the second noise reduction transistor T6 and the active layer A7 of the first noise reduction transistor T7 are located in a single continuous first semiconductor layer, and the first semiconductor layer extends along a first direction. That is, the active layer A6 of the second noise reduction transistor T6 and the active layer A7 of the first noise reduction transistor T7 are integrally formed. For example, as shown in FIGS. 2 and 3, as long as it does not affect the layout of other structures and does not unnecessarily increase the width of the shift register unit, the active layer A6 of the second noise reduction transistor T6 may be offset from the active layer A7 of the first noise reduction transistor T7 by a predetermined distance in the first direction, and the embodiments of the present disclosure do not limit this.

[0132] For example, as shown in FIGS. 2 and 4, the gate G6 of the second noise reduction transistor T6 and the gate G7 of the first noise reduction transistor T7 extend along a second direction Y and are arranged side by side in a first direction X. For example, the gate G6 of the second noise reduction transistor T6 and the gate G7 of the first noise reduction transistor T7 may be parallel. For example, both extend along the second direction Y. Also, the extending direction of the gate G6 of the second noise reduction transistor T6 and the extending direction of the gate G7 of the first noise reduction transistor T7 may not be parallel. For example, they intersect at a predetermined angle. For example, the intersecting angle is 20° or less, or the angles between both and the horizontal line are 20° or less. The embodiments of the present disclosure do not limit this. As long as the second noise reduction transistor T6 and the first noise reduction transistor T7 are integrally installed and arranged one above the other, it is acceptable.

[0133] For example, as shown in FIG. 4, the display substrate further includes a first connection wiring L1 and a second connection wiring L2 that extend along a second direction Y. The first connection wiring L1 and the second connection wiring L2 are installed in parallel and overlap with a first transfer electrode E1 (shown in FIG. 7). A first end L11 of the first connection wiring L1 is connected to a gate G6 of a second noise reduction transistor T6, and a second end L12 of the first connection wiring L1 is connected to an end E221 of a second portion E22 of a second transfer electrode E2 that is not in the same layer. A first end L21 of the second connection wiring L2 is connected to a gate G7 of a first noise reduction transistor T7, and a second end L22 of the second connection wiring L2 is connected to a second clock signal line GCB to receive a second clock signal. Therefore, both the first connection wiring L1 and the second connection wiring L2 have a linear structure without any bends, thereby making the wiring structure of the display substrate simpler and saving wiring space.

[0134] For example, in other embodiments, the extending directions of the first connection wiring L1 and the second connection wiring L2 may not be parallel. For example, the first connection wiring L1 and the second connection wiring L2 intersect at a predetermined angle. For example, the intersecting angle is 20° or less, or the angles between both of them and the horizontal line are 20° or less.

[0135] For example, as shown in FIGS. 4, 6, and 7, the second end L12 of the first connection wiring L1 is connected to an end E221 of a second portion E22 of a second transfer electrode E2 through a via hole GH2 that penetrates a second insulating layer 360 and a third insulating layer 370. The second end L22 of the second connection wiring L2 is connected to a second clock signal line GCB through a via hole GH7 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0136] For example, as shown in FIG. 2, a gate G8 of a voltage regulator transistor T8 is connected to a second power supply line VGL to receive a second voltage. For example, as shown in FIGS. 4, 6, and 7, the gate G8 of the voltage regulator transistor T8 is connected to the second power supply line VGL through a via hole GH8 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0137] For example, as shown in FIG. 7, the second power line VGL includes a protruding portion E01 protruding in the second direction Y. For example, the second power line VGL and the protruding portion E01 are integrally formed, and the protruding portion E01 is located in the third conductive layer 340. The second pole SD32 of the second control transistor T3 is connected to the protruding portion E01 of the second power line VGL to receive a second voltage. For example, the protruding portion E01 of the second power line VGL is integrally formed with the second pole SD32 of the second control transistor T3. Also, for example, the protruding portion E01 of the second power line VGL is used as the second pole SD32 of the second control transistor T3. For example, as shown in FIGS. 3, 6, and 7, the second pole SD32 of the second control transistor T3 is connected to the active layer A3 of the second control transistor T3 through a via hole H32 penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0138] For example, as shown in FIG. 4, the gate G1 of the input transistor T1 includes a first gate G11 and a second gate G12 arranged side by side to form a substantially "U" - shaped double - gate structure, whereby the input transistor T1 is firmly closed when it is turned off, reducing the leakage current. In this case, the active layer A1 of the input transistor T1 extends along the first direction X and has a strip shape (shown in FIG. 3), and the first gate G11 and the second gate G12 of the input transistor T1 are connected to the gate G3 of the second control transistor T3. The gate G3 of the second control transistor T3 is further connected to the first clock signal line GCK to provide a first clock signal to the gate G3 of the second control transistor T3 and the first gate G11 and the second gate G12 of the input transistor T1. Thereby, the wiring density is increased and the wiring space is saved. Of course, the gate of the input transistor T1 may include only a single gate and overlap with the active layer of the input transistor T1, and the embodiments of the present disclosure do not limit this.

[0139] For example, the structure having the source layer A1 of the input transistor T1 may be exchanged with the structure of the gate G1 of the input transistor T1, or a double gate structure may be formed on the input transistor T1. For example, the active layer A1 has a substantially "U" shaped structure, and the gate G1 has a strip shape along the second direction Y.

[0140] For example, as shown in FIGS. 4, 6, and 7, the gate G3 of the second control transistor T3 is connected to the first clock signal line GCK through a via hole GH6 penetrating the second insulating layer 360 and the third insulating layer 370.

[0141] For example, as shown in FIG. 7, the display substrate further includes a third transfer electrode E3. The third transfer electrode E3 extends along the first direction X, and the first end E31 of the third transfer electrode E3 is connected to the gate G3 of the second control transistor T3 (shown in FIG. 4), the first gate G11, and the second gate G12 of the input transistor T1. The second end of the third transfer electrode E3 is connected to the second pole SD22 of the first control transistor T2 and integrally formed. In the first direction X, since the second pole SD22 of the first control transistor T2 is adjacent to the gate G3 of the second control transistor T3 (shown in FIG. 4), compared with other transfer electrodes (for example, the first transfer electrode E1 and the second transfer electrode E2), the length of the third transfer electrode E3 is short, thereby enhancing the wiring compactness of the display substrate, reducing the occupied space of the third transfer electrode E3 and its overlap with other wirings, and reducing the complexity of the wiring of the display substrate. However, the positions of the second end of the third transfer electrode E3 and the second pole SD22 of the first control transistor T2 are considered to be the same, that is, integrally formed, so they are not indicated by reference numerals in the figure.

[0142] For example, the third transfer electrode E3 may not be parallel to the first direction X. For example, the third transfer electrode E3 intersects the first direction X at a predetermined angle. For example, the intersecting angle is 20° or less.

[0143] For example, as shown in FIGS. 4, 6, and 7, the first end E31 of the third transfer electrode E3 is connected to the gate G3 of the second control transistor T3 and the first gate G11 and the second gate G12 of the input transistor T1 through a via hole GH3 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0144] For example, as shown in FIGS. 3, 6, and 7, the second pole SD22 of the first control transistor T2 is connected to the active layer A2 of the first control transistor T2 through a via hole H22 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0145] For example, as shown in FIGS. 2 and 3, the orthographic projection of the first capacitor C1 on the base substrate 101 is located on the side closer to the display region 102 of the orthographic projection of the active layer A4 of the output control transistor T4 on the base substrate 101, and the orthographic projection of the first capacitor C1 on the base substrate 101 and the orthographic projection of the first power line VGH on the base substrate 101 at least partially overlap. That is, by positioning the first capacitor C1 on the right side of the output control transistor T4 in the second direction Y, the first capacitor C1 is placed closer to the display region to leave more space for other parts in the shift register unit 104, such as transistors, transfer electrodes, power lines, etc., thereby reducing the overlap of the wiring. Thereby, the space occupied by the first capacitor C1 is reduced.

[0146] For example, in other embodiments, when permitted for the design space of the shift register unit, the orthographic projection of the first capacitor C1 on the base substrate 101 and the orthographic projection of the first power line VGH on the base substrate 101 may not overlap. However, when the orthographic projection of the first capacitor C1 on the base substrate 101 and the orthographic projection of the first power line VGH on the base substrate 101 at least partially overlap, the normal operation of the first capacitor C1 is not affected.

[0147] For example, as shown in FIG. 2, the shape of the first capacitor C1 is rectangular. As shown in FIGS. 4 and 5, both the first electrode CE11 and the second electrode CE12 of the first capacitor C1 are rectangular. A second insulating layer 360 is provided between the first electrode CE11 and the second electrode CE12.

[0148] For example, as shown in FIGS. 4, 6, and 7, the first electrode CE11 of the first capacitor C1 is connected to the gate G4 of the output control transistor T4. For example, the first electrode CE11 of the first capacitor C1 and the gate G4 of the output control transistor T4 may be integrally formed. The second electrode CE12 of the first capacitor C1 is connected to the first power line VGH through a via hole GH9 that penetrates the third insulating layer 370.

[0149] For example, in another example, the second electrode CE12 of the first capacitor C1 may be further located in the third conductive layer 340. In this case, a second insulating layer 360 and a third insulating layer 370 are provided between the first electrode CE11 and the second electrode CE12.

[0150] Also, for example, in another example, the first electrode CE11 of the first capacitor C1 may be further located in the first conductive layer 320. In this case, a first insulating layer 350 and a second insulating layer 360 are provided between the first electrode CE11 and the second electrode CE12.

[0151] For example, as shown in FIG. 7, the display substrate further includes a fourth transfer electrode E4. The fourth transfer electrode E4 is connected to the first electrode SD61 of the second noise reduction transistor T6 and the first electrode SD41 of the output control transistor T4. For example, the fourth transfer electrode E4 extends from the first electrode SD61 of the second noise reduction transistor T6 in a direction close to the output control transistor T4 along the first direction X, and then bends in the second direction Y and is connected to the first electrode SD41 of the output control transistor T4 to reduce the complexity and occupied space of the wiring.

[0152] For example, as shown in FIG. 4, the gate G6 of the second noise reduction transistor T6 is connected to and integrally formed with the gate G4 of the output control transistor T4. For example, the connection wiring between the gate G6 of the second noise reduction transistor T6 and the gate G4 of the output control transistor T4 extends from the gate G6 of the second noise reduction transistor T6 in a direction close to the output control transistor along the first direction X, and then bends in the second direction Y and is connected to the gate G4 of the output control transistor T4. The orthographic projection of the connection wiring between the gate G6 of the second noise reduction transistor T6 and the gate G4 of the output control transistor T4 on the base substrate does not overlap with the orthographic projection of the fourth transfer electrode E4 (shown in FIG. 7) on the base substrate. Thereby, the overlap between the connection wiring between the second noise reduction transistor T6 and the output control transistor T4 and other wirings is reduced, thereby reducing the wiring complexity and improving the space utilization rate.

[0153] For example, as shown in FIGS. 2 and 7, both the fourth transfer electrode E4 and the second node N2 are provided. The fourth transfer electrode E4 is used to connect the first pole SD61 of the second noise reduction transistor T6 and the first pole SD41 of the output control transistor T4. The fourth transfer electrode E4 is located in the third conductive layer 340.

[0154] For example, as shown in FIGS. 3, 6, and 7, the first pole SD61 of the second noise reduction transistor T6 is connected to the active layer A6 of the second noise reduction transistor T6 through a via hole H61 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The first pole SD41 of the output control transistor T4 is connected to the active layer A4 of the output control transistor T4 through a via hole H41 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0155] For example, as shown in FIG. 2, the orthographic projection of the second capacitor C2 on the base substrate 101 is located between the orthographic projection of the first power line VGH on the base substrate 101 and the orthographic projections of the active layer A4 of the output control transistor T4 (shown in FIG. 3) and the active layer A5 of the output transistor T5 (shown in FIG. 3) on the base substrate 101. Thereby, the second capacitor C2 is placed closer to the display area to reduce wiring overlap, leaving more space for other parts in the shift register unit 104, such as transistors, transfer electrodes, power lines, etc.

[0156] For example, as shown in FIG. 4, the first electrode CE21 of the second capacitor C2 is connected to the gate G5 of the output transistor T5. For example, the first electrode CE21 of the second capacitor C2 and the gate G5 of the output transistor T5 may be integrally formed.

[0157] For example, as shown in FIG. 2, the shape of the second capacitor C2 is rectangular. For example, as shown in FIGS. 4 and 5, both the first electrode CE21 and the second electrode CE22 of the second capacitor C2 are rectangular. A second insulating layer 360 is provided between the first electrode CE21 and the second electrode CE22.

[0158] For example, in another example, the second electrode CE22 of the second capacitor C2 may be further located in the third conductive layer 340. In this case, a second insulating layer 360 and a third insulating layer 370 are provided between the first electrode CE21 and the second electrode CE22.

[0159] Also, for example, in another example, the first electrode CE21 of the second capacitor C2 may be further located in the first conductive layer 320. In this case, a first insulating layer 350 and a second insulating layer 360 are provided between the first electrode CE21 and the second electrode CE22.

[0160] For example, as shown in FIGS. 4 and 7, the display substrate further includes a fifth transfer electrode E5. The first pole SD51 of the output transistor T5 is connected to the first end E51 of the fifth transfer electrode E5, and the gate G7 of the first noise reduction transistor T7 is connected to the fifth transfer electrode E5. For example, the orthographic projection of the fifth transfer electrode E5 on the base substrate 101 does not overlap with the orthographic projections of the first transfer electrode E1 and the fourth transfer electrode E4 on the base substrate 101. Thereby, the fifth transfer electrode E5 does not overlap with other wirings, thereby reducing the complexity of the wirings and improving the space utilization rate.

[0161] For example, as shown in FIGS. 3, 6, and 7, the first pole SD51 of the output transistor T5 is connected to the active layer A5 of the output transistor T5 through a via hole H51 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0162] For example, as shown in FIGS. 4, 6, and 7, the gate G7 of the first noise reduction transistor T7 is connected to the fifth transfer electrode E5 through a via hole GH4 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0163] For example, as shown in FIG. 7, the display substrate further includes a sixth transfer electrode E6 that extends parallel along the second direction Y. The gate G5 of the output transistor T5 is connected to the first end E61 of the sixth transfer electrode E6, and the second end of the sixth transfer electrode E6 is connected to the second pole SD82 of the voltage regulator transistor T8. For example, the orthographic projection 101 of the sixth transfer electrode E6 on the base substrate does not overlap with the orthographic projection of the first transfer electrode E1 on the base substrate 101. Thereby, the occupied space of the sixth transfer electrode E6 is reduced, the overlap with other wirings is reduced, and the generation of parasitic capacitance is reduced. However, the positions of the second end of the sixth transfer electrode E6 and the second pole SD82 of the voltage regulator transistor T8 are considered to be the same, integrally formed, and not indicated by reference numerals in the figure.

[0164] For example, the sixth transfer electrode E6 may not be parallel to the second direction Y. For example, the sixth transfer electrode E6 and the second direction Y intersect at a predetermined angle. For example, the intersecting angle is 20° or less.

[0165] For example, as shown in FIGS. 4, 6, and 7, the gate G5 of the output transistor T5 is connected to the first end E61 of the sixth transfer electrode E6 through a via hole GH5 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0166] For example, as shown in FIGS. 3, 6, and 7, the second pole SD82 of the voltage regulator transistor T8 is connected to the active layer A8 of the voltage regulator transistor T8 through a via hole H82 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0167] For example, as shown in FIGS. 2 and 7, the sixth transfer electrode E6 includes a third node N3. For example, the sixth transfer electrode E6 is implemented as the third node N3 and is configured to be connected to the second pole SD82 of the voltage regulator transistor T8 and the gate G5 of the output transistor T5 (shown in FIG. 4). The sixth transfer electrode E6 is located in the third conductive layer 340.

[0168] For example, as shown in FIG. 7, the display substrate further includes a seventh transfer electrode E7. The first end E71 of the seventh transfer electrode E7 is connected to the second pole SD42 of the output control transistor T4, and the second end E72 of the seventh transfer electrode E7 is connected to the second pole SD52 of the output transistor T5. For example, the seventh transfer electrode E7 extends along the first direction X. For example, the orthographic projection of the seventh transfer electrode E7 on the base substrate is located between the orthographic projections of the first power line VGH, the active layer A4 of the output control transistor T4 (shown in FIG. 3), and the active layer A5 of the output transistor T5 (shown in FIG. 3) on the base substrate. Thereby, the occupied space of the seventh transfer electrode E7 is reduced, the overlap with other wirings is reduced, thereby reducing the generation of parasitic capacitance and reducing the complexity of the wirings of the display substrate.

[0169] For example, as shown in FIGS. 4, 6, and 7, the seventh transfer electrode E7 is connected to the second electrode CE22 of the second capacitor C2 through a via hole GH10 penetrating the third insulating layer 370.

[0170] For example, as shown in FIGS. 3, 6, and 7, the second electrode SD42 of the output control transistor T4 is connected to the active layer A4 of the output control transistor T4 through a via hole H42 penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. The second electrode SD52 of the output transistor T5 is connected to the active layer A5 of the output transistor T5 through a via hole H52 penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0171] For example, as shown in FIG. 7, the second electrode SD52 of the output transistor T5 is connected to the second electrode SD12 of the input transistor T1 of the lower shift register unit adjacent to the shift register unit 104, and the output signal of the second electrode SD52 of the output transistor T5 is used as the input signal of the second electrode SD12 of the input transistor T1 of the lower shift register unit.

[0172] For example, as shown in FIGS. 3, 6, and 7, the second electrode SD12 of the input transistor T1 is connected to the active layer A1 of the input transistor T1 through a via hole H12 penetrating the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370.

[0173] For example, as shown in FIGS. 4, 6, and 7, the second electrode SD12 of the input transistor T1 and the second electrode SD42 of the output control transistor T4 are connected to the output terminal GOUT of the shift register unit through a via hole GH11 penetrating the second insulating layer 360 and the third insulating layer 370, and the output signal is output to the output terminal.

[0174] For example, as shown in FIG. 3, a part of the active layer A4 of the output control transistor T4 and a part of the active layer A5 of the output transistor T5 (the part of the active layer A5 located in the same column as the active layer A4 in the first direction X) are located in one continuous second semiconductor layer, and the second semiconductor layer extends along the first direction X. Without affecting the layout of other structures and without unnecessarily increasing the width of the shift register unit, the active layer A4 of the output control transistor T4 may be shifted by a predetermined distance in the first direction from a part of the active layer A5 of the output transistor T5, and the embodiments of the present disclosure do not limit this.

[0175] For example, as shown in FIGS. 3 and 7, the active layer A5 of the output transistor T5 includes two parts. A part of it and the active layer A4 of the output control transistor T4 are located in one continuous second semiconductor layer extending in the first direction X, and the other part is located closer to the voltage regulator transistor T8 of the active layer A4 of the output control transistor T4 (for example, located below the active layer A7 of the first noise reduction transistor T7 in FIG. 3). Also, a part of the first pole SD51 and a part of the second pole SD52 closer to the voltage regulator transistor T8 of the output transistor T5 (for example, two first poles SD51 and second poles SD52 extending along the second direction Y away from the output control transistor T4 in FIG. 7) are longer than the lengths of the first pole SD51 and the second pole SD52 at other positions. Thereby, the width of the output transistor T5 in the second direction Y can be increased to enhance the signal output capability of the output transistor T5.

[0176] For example, in other embodiments, a portion of the active layer A5 of the output transistor T5 that is located closer to the voltage regulator transistor T8 of the active layer A4 of the output control transistor T4 (for example, located below the active layer A7 of the first noise reduction transistor T7 in FIG. 3) extends in a direction closer to the active layer A4 of the output control transistor T4 and is connected to other portions of the active layer A5. For example, as shown in FIG. 4, the gate G4 of the output control transistor T4 and the gate G5 of the output transistor T5 extend along the second direction Y and are arranged side by side in the first direction X. For example, the gate G4 of the output control transistor T4 and the gate G5 of the output transistor T5 may be parallel, for example, both extending along the second direction Y, and also, the extending direction of the gate G4 of the output control transistor T4 and the extending direction of the gate G5 of the output transistor T5 may not be parallel, for example, intersecting at a predetermined angle. For example, the intersecting angle is 20° or less, or the angles between both and the horizontal line are 20° or less. However, the embodiments of the present disclosure are not limited thereto, and the output control transistor T4 and the output transistor T5 may be integrally installed and arranged vertically side by side.

[0177] For example, as shown in FIG. 7, the first pole SD41 of the output control transistor T4 is connected to the first power supply line VGH to receive a first voltage, thereby reducing the occupied space of the connection wiring and the complexity of the wiring.

[0178] In the embodiments of the present disclosure, for example, the first transfer electrode E1, the second transfer electrode E2, the third transfer electrode E3, the fourth transfer electrode E4, the fifth transfer electrode E5, the sixth transfer electrode E6, and the seventh transfer electrode E7 are all located in the third conductive layer 340. The first transfer electrode E1 is used to connect the electrodes of the first noise reduction transistor T7, the voltage regulator transistor T8, and the first control transistor T2, and includes a first node N1. The second transfer electrode E2 is used to connect the electrodes of the first control transistor T2 and the second control transistor T3. The second transfer electrode E2 includes a second node N2. The third transfer electrode E3 is used to connect the electrodes of the second control transistor T3, the input transistor T1, and the first control transistor T2. The fourth transfer electrode E4 is used to connect the electrodes of the second noise reduction transistor T6 and the output control transistor T4. The fifth transfer electrode E5 is used to connect the electrodes of the first noise reduction transistor T7 and the output transistor T5. The sixth transfer electrode E6 is used to connect the electrodes of the output transistor T5 and the voltage regulator transistor T8. The sixth transfer electrode E6 includes a third node N3. The seventh transfer electrode E7 is used to connect the electrodes of the output transistor T5 and the output control transistor T4. According to the needs such as the wiring layout in the shift register 104, without affecting the circuit function, the first transfer electrode E1, the second transfer electrode E2, the third transfer electrode E3, the fourth transfer electrode E4, the fifth transfer electrode E5, the sixth transfer electrode E6, and the seventh transfer electrode E7 may be disposed in other layers. For example, the seventh transfer electrode E7 is disposed in the second conductive layer 330.

[0179] For example, in some embodiments of the present disclosure, the line width of each layer of wiring is generally 3 microns, for example, and the spacing between wirings located in the same layer is greater than 3 microns, for example. For example, the spacing between the wirings is related to the accuracy of the exposure apparatus, for example. The higher the accuracy of the exposure apparatus, the smaller the spacing. Specifically, it can be determined according to the actual situation, and the embodiments of the present disclosure do not limit this. In the embodiments of the present disclosure, in order to avoid wiring adhesion and signal short - circuit in the actual process, it is necessary to provide a necessary spacing between the wirings in the same layer.

[0180] For example, as shown in FIG. 4, the spacing between the orthographic projection of each wiring of the first conductive layer 320 on the base substrate 101 and the orthographic projection of each wiring of the second conductive layer 330 on the base substrate 101 is generally 1.5 microns, for example. For example, the gate of the transistor in the first conductive layer 320 must exceed the active layer of the semiconductor layer 310 by 2 microns or more, for example. For example, as shown in FIGS. 2, 3, and 4, the orthographic projection of the first gate and the second gate of the first transistor T1 on the base substrate 101 exceeds both sides of the orthographic projection of the active layer A1 of the first transistor T1 on the base substrate 101 by 2 microns or more in the second direction Y. The embodiments of the present disclosure do not limit this.

[0181] For example, as shown in FIGS. 3 to 5, the distance between the orthographic projection of the active layer (for example, active layers A1 to A8) of each transistor in the semiconductor layer 310 on the base substrate 10 and the orthographic projection of each connection wiring (for example, the first connection line L1 and the second connection line L2) in the first conductive layer 320 on the base substrate 101 is 1.5 microns or more, thereby avoiding the occurrence of the channel effect between the connection wiring and the active layer of each transistor in the semiconductor layer 310. For example, the distance between the orthographic projection of the semiconductor layer 310 on the base substrate 10 and the orthographic projection of the second conductive layer 330 on the base substrate 10 is not limited and may be installed overlapping. For example, in some embodiments of the present disclosure, a predetermined distance (this distance is smaller than the distance between the wirings of the same layer) is ensured as much as possible between the wirings of different layers, reducing unnecessary overlap and avoiding interference due to excessive parasitic capacitance.

[0182] For example, as shown in FIGS. 2 and 6, for the via holes connecting the source electrode or drain electrode of the transistors T1 to T8 of the input transistor - voltage regulator transistor and the active layer, such as via holes H11, H12 to H81, H82, there are differences in the number of via holes H11, H12 to H81, H82 in FIG. 6. The via holes H41 and H42 of the output control transistor T4 are plural in the second direction Y (for example, six each in FIG. 6), and the via holes H51 and H52 of the output transistor T5 are arranged in plural rows in the first direction X and plural in the second direction Y, thereby increasing the strength and tightness of the connection between the source electrode or drain electrode of the transistor and the active layer and reducing the possibility of leakage current generation. For example, the first pole (such as SD11, SD21, etc. in FIG. 7) or the second pole (such as SD12, SD22, etc. in FIG. 7) of the input transistor T1, the first control transistor T2, the second control transistor T3, the first noise reduction transistor T7, and the second noise reduction transistor T6 are each connected to the corresponding active layer (such as A1, A2, etc. in FIG. 3) through one via hole (such as H11, H12, etc.). For example, two via holes H81 connect the drain electrode region D8 (shown in FIG. 3) of the voltage regulator transistor T8 and the first pole SD81 (shown in FIG. 7) of the voltage regulator transistor T8, and two via holes H82 connect the source electrode region S8 (shown in FIG. 3) of the voltage regulator transistor T8 and the second pole SD82 (shown in FIG. 7) of the voltage regulator transistor T8. By providing two via holes H81 and two via holes H82, the strength and tightness of the connection between the source electrode or drain electrode of the transistor and the active layer can be increased, and the possibility of leakage current generation can be reduced. For example, the number of via holes GH1 - GH11 connecting the first conductive layer 320 and the third conductive layer 340 is not the same either. The number of each of the via holes GH1 - GH3 is one, the number of each of GH4 - GH9 and GH11 is two, and the number of GH10 is six.For example, when two via holes GH4 connect the gate G7 of the first noise reduction transistor T7 and the fifth transfer electrode E5, the strength and tightness of the connection between the gate G7 and the fifth transfer electrode E5 can be increased, and the possibility of generating leakage current can be reduced. That is, when permitted with respect to the layout space of the shift register unit, increasing the number of via holes can increase the strength and tightness of the electrode connection and reduce the possibility of generating leakage current.

[0183] However, the number of via holes shown in FIG. 3 (for example, via holes H11, H12 to via holes H81, H82, via holes GH1 to via holes GH11) can vary according to the requirements during the design of the transistors, connection wirings, etc. of the shift register unit, and the embodiments of the present disclosure do not limit this.

[0184] For example, as shown in FIGS. 6 and 7, the width of each wiring of the third conductive layer 340 needs to cover the corresponding via holes (for example, via holes H11, H12 to via holes H81, H82, via holes GH1 to via holes GH11). For example, the size of the via hole (for example, the diameter of the via hole) exceeds 1 micron, for example, the size of the via hole is 2.0 to 2.5 microns, and the width of each wiring covering the via holes of the third conductive layer 340 is 4 to 5 microns. For example, the width of the wirings corresponding to the via holes (H41, H42, H51, H52) of the output control transistor T4 and the output transistor T5 exceeds 1 micron above and below the via holes, for example, 4.0 to 4.5 microns. Since there are many corresponding via holes between the output control transistor T4 and the output transistor T5, the width of the wiring connected to other transistors and located in the third conductive layer 340 only needs to meet the requirement of covering the via holes by more than 1 micron at the position of the via holes. For example, the width of the wiring between the via holes may be narrow.

[0185] For example, as shown in FIG. 7, the intervals between wirings such as the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGH, and the second power supply line VGL located in the third conductive layer 340 are 3 microns or more. To meet the requirements of driving capabilities, the line widths of the first clock signal line GCK and the second clock signal line GCB are 9 microns or more. The line width of the second power supply line VGL may be 6, 9, or 10 microns. The line width of the first power supply line VGH is, for example, 10 microns. The second voltage provided by the second power supply line VGL is generally -7V, for example.

[0186] For example, in some examples, the thicknesses of the first conductive layer 320 and the second conductive layer 330 are 2000 to 300 angstroms, and the thickness of the third conductive layer 340 is 5000 to 8000 angstroms. The embodiments of the present disclosure are not limited thereto.

[0187] At least one embodiment of the present disclosure further provides a display device. FIG. 9 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 9, the display device 2 includes a display substrate 1 according to any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 2.

[0188] However, the display device 2 may be any product or component having a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet PC, a notebook computer, a digital frame, a navigator, etc. The display device 2 may further include other components, such as a data driving circuit, a timing controller, etc. The embodiments of the present disclosure are not limited thereto.

[0189] However, for the sake of clarity and brevity, all the constituent units of the display device are not disclosed in the embodiments of the present disclosure. To realize the substrate function of the display device, those skilled in the art can provide and install other structures not shown according to specific needs. The embodiments of the present disclosure are not limited thereto.

[0190] The technical effects of the display device 2 according to the above embodiment can be referred to the technical effects of the display substrate 1 according to the embodiments of the present disclosure, and detailed description thereof will be omitted here.

[0191] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. FIG. 10 is a flowchart of a method for manufacturing a display substrate according to at least one embodiment of the present disclosure. For example, the manufacturing method can be applied to the manufacturing of the display substrate according to any embodiment of the present disclosure. For example, it can be applied to the manufacturing of the display substrate shown in FIG. 2.

[0192] As shown in FIG. 10, the manufacturing method of the display substrate includes steps S100 to S200.

[0193] Step S100: Provide a base substrate including a display area and a peripheral area surrounding at least the display area.

[0194] Step S200: Form a shift register unit, a first clock signal line, a second clock signal line, a first power line, and a second power line on the peripheral area of the base substrate.

[0195] In step S100, for example, the base substrate 101 may use, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure do not limit this. For example, an insulating material is deposited on the base substrate 101 and a barrier layer 390 is formed by a patterning process. For example, the insulating material may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the patterning process includes coating a photoresist layer on the insulating material, exposing the photoresist layer using a mask, developing the exposed photoresist layer to obtain a photoresist pattern, etching the insulating material using the photoresist pattern, and then selectively removing the photoresist pattern. Also, for example, an insulating material is deposited on the barrier layer 390 and a buffer layer 3100 is formed by a patterning process.

[0196] In step S200, the step of forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line, and a second power supply line in the peripheral region of the base substrate includes forming a semiconductor layer on the base substrate, patterning the semiconductor layer to form active layers (active layers A1 to A8) of a plurality of transistors (input transistor T1 to voltage regulator transistor T8) of each circuit of the shift register. A first insulating material layer is formed on the side of the active layers of the plurality of transistors away from the base substrate, the first insulating material layer is patterned to form a first insulating layer 350 having via holes, a first conductive material layer is formed on the side of the first insulating layer away from the base substrate, the first conductive material is patterned to form gates (gates G1 to G8) of the plurality of transistors, a plurality of connection wirings (first connection wiring L1, second connection wiring L2), and first electrodes (first electrode CE11 and first electrode CE21) of a plurality of capacitors (first capacitor C1 and second capacitor C2) of each circuit (input circuit 1041, output circuit 1043, first control circuit 1042, output control circuit 1044, second control circuit 1045, and voltage regulator circuit 1046). A second insulating material layer is formed on the side of the gates of the plurality of transistors away from the base substrate, the second insulating material layer is patterned to form a second insulating layer 360 having via holes, a second conductive material layer is formed on the side of the second insulating layer away from the base substrate, the second conductive material is patterned to form second electrodes (second electrode CE12 and second electrode CE22) of the plurality of capacitors. A third insulating material layer is formed on the side of the second insulating layer and the second capacitor electrode plates of the plurality of capacitors away from the base substrate, the third insulating material layer is patterned to form a third insulating layer 370 having via holes, a third conductive material layer is formed on the side of the third insulating layer away from the base substrate, the third conductive material is patterned to form first electrodes (first electrode SD11 to first electrode SD81) and second electrodes (second electrode SD12 to second electrode SD82) of the plurality of transistors, a plurality of transfer electrodes (first transfer electrode E1 to seventh transfer electrode E7), a first clock signal line GCK, a second clock signal line GCB, a first power supply line VGH, and a second power supply line VGL.

[0197] For example, the material of the semiconductor layer may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The materials of the first insulating material, the second insulating material, and the third insulating material may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The first conductive material, the second conductive material, and the third conductive material may include a metal material or an alloy material.

[0198] For example, the first pole and the second pole of each transistor are connected to the active layer (active layers A1 to A8) of each transistor through via holes (e.g., via hole H11, via holes H12 to H81, via hole H82) that penetrate the first insulating layer, the second insulating layer, and the third insulating layer. Each transistor and each capacitor are connected to each other through a plurality of connection wirings or a plurality of transfer electrodes and via holes (e.g., via hole GH1 to via hole GH11) that penetrate the second insulating layer and the third insulating layer, and are connected to the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGH, and the second power supply line VGL.

[0199] For example, a fourth insulating material layer is formed on the side of the third conductive layer 340 away from the base substrate, and the fourth insulating layer 380 is formed by a patterning process. For example, the fourth insulating material may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials.

[0200] Regarding the installation of the connection structure between each transistor and capacitor of the shift register unit 104 and the first power supply line VGH, the second power supply line VGL, the plurality of clock signal lines, the connection wirings, and the transfer electrodes, reference can be made to the descriptions in FIGS. 2 to 8, and detailed descriptions are omitted here.

[0201] However, in multiple embodiments of the present disclosure, the flow of the manufacturing method of the display substrate may include more or fewer operations, and these operations may be executed sequentially or in parallel. Although the flow of the manufacturing method described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above may be executed only once, or may be executed multiple times under certain conditions.

[0202] For the technical effects of the manufacturing method of the display substrate according to the above embodiments, reference can be made to the technical effects of the display substrate according to the embodiments of the present disclosure, and detailed descriptions are omitted here.

[0203] The following points need to be explained.

[0204] (1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure. For other structures, normal designs can be referred to.

[0205] (2) Without contradiction, new embodiments can be obtained by combining the embodiments and features of the embodiments of the present disclosure with each other.

[0206] The above are only exemplary embodiments of the present disclosure and do not limit the protection scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, a base substrate having a display area and a peripheral area located on at least one side of the display area; a shift register unit disposed in a peripheral region of the base substrate, a first clock signal line, and a second clock signal line; the first clock signal line and the second clock signal line extend along a first direction in the base substrate and are configured to provide a first clock signal and a second clock signal to the shift register unit, respectively; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the first control circuit is connected to the first node and the second node and configured to control a level of the second node in response to a level of the first node and the first clock signal; the second control circuit is connected to the first node and the second node, and is configured to control the level of the first node under control of the level of the second node and the second clock signal; the voltage regulator circuit is connected to the first node and a third node and configured to stabilize a level of the third node; the output circuit is connected to the third node and is configured to output an output signal to an output terminal under control of a level of the third node; the first control circuit comprises a first control transistor, the second control circuit comprises a first noise reduction transistor, the voltage regulator circuit comprises a voltage regulator transistor, a gate of the first control transistor, a first pole of the first noise reduction transistor and a first pole of the voltage regulator transistor are all connected to the first node; a first pole of the first noise reduction transistor and a first pole of the voltage regulator transistor are located in a first source-drain electrode layer having a first transfer electrode; a first end of the first portion connected to a first pole of the first noise reduction transistor, a second end of the first portion connected to a first pole of the voltage regulator transistor, and a gate of the first control transistor that is not in the same layer.

2. the first transfer electrode further includes a third portion extending parallel to the second direction, the third portion being connected to the second portion, and the third portion being arranged side by side with the first portion in the first direction; the input circuit includes an input transistor, an orthogonal projection of an active layer of the input transistor on the base substrate is located between an orthogonal projection of an active layer of the first control transistor on the base substrate and an orthogonal projection of an active layer of the first noise reduction transistor on the base substrate; 2. The display substrate according to claim 1, wherein a first electrode of the input transistor is connected to an end of the third portion.

3. The display substrate according to claim 1 , wherein the first transfer electrode comprises the first node.

4. a second transfer electrode, and the first control circuit further comprises a second control transistor; the second transfer electrode includes a first portion and a second portion parallel to the second direction, an end of the first portion of the second transfer electrode is connected to a first pole of the second control transistor, and the second portion of the second transfer electrode is connected to a first pole of the first control transistor; The display substrate according to claim 1 , wherein the second transfer electrode comprises the second node.

5. The display substrate according to claim 4 , wherein an orthogonal projection of an active layer of the second control transistor on the base substrate is located on a side away from the display region of an orthogonal projection of an active layer of the first control transistor on the base substrate.

6. the second control circuit further comprises a second noise reduction transistor; an active layer of the second noise reduction transistor and an active layer of the first noise reduction transistor are located in a continuous first semiconductor layer, and the first semiconductor layer extends in a first direction, and a gate of the second noise reduction transistor and a gate of the first noise reduction transistor extend in a second direction and are arranged side by side in the first direction; the display substrate further includes a first connection wiring and a second connection wiring extending in the second direction, the first connection wiring and the second connection wiring being arranged in parallel, and the first connection wiring and the second connection wiring each overlap with the first transfer electrode; a first end of the first connection wiring is connected to a gate of the second noise reduction transistor, and a second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode that is not in the same layer; 6. The display substrate according to claim 4, wherein a first end of the second connection wiring is connected to a gate of the first noise reduction transistor, and a second end of the second connection wiring is connected to the second clock signal line to receive the second clock signal.

7. 7. The display substrate of claim 6, wherein the orthogonal projections of the active layer of the second noise reduction transistor and the active layer of the first noise reduction transistor on the base substrate are located on a side closer to the display area than the orthogonal projection of the active layer of the first control transistor on the base substrate.

8. the shift register unit further includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer is located between an active layer of the first control transistor and a gate of the first control transistor, the second insulating layer and the third insulating layer are located between the first transfer electrode and the gate of the first control transistor, a gate of the first control transistor is connected to a second portion of the first transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer; and 8. The display substrate according to claim 6, wherein a second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer.

9. 9. The display substrate according to claim 1, wherein the orthogonal projection of the active layer of the voltage regulator transistor on the base substrate is located on a side away from the display area of ​​the orthogonal projection of the active layer of the first control transistor on the base substrate.

10. The display substrate of claim 1 , wherein an included angle between the first direction and the second direction is between 70° and 90°.

11. The display substrate according to claim 1 , wherein the first clock signal line and the second clock signal line are located on a side of the shift register unit that is away from the display area.

12. a first power supply line configured to provide a first voltage to the shift register unit; the first power supply line extends in the first direction on the base substrate and is connected to the second control circuit; The display substrate according to claim 4 , wherein an orthogonal projection of the first power supply line on the base substrate is located on a side closer to the display area than an orthogonal projection of the shift register unit on the base substrate.

13. Further comprising a second power supply line; the second power supply line extends in the first direction on the base substrate and is configured to provide a second voltage to the shift register unit; an orthogonal projection of the second power supply line on the base substrate is located between an orthogonal projection of the first clock signal line and the second clock signal line on the base substrate and an orthogonal projection of the shift register unit on the base substrate; 13. The display substrate of claim 4, wherein a gate of the voltage regulator transistor is connected to the second power line to receive the second voltage.

14. the second power line includes a protruding portion protruding in the second direction, 14. The display substrate of claim 13, wherein a second electrode of the second control transistor is connected to a protrusion of the second power line to receive the second voltage.

15. the input transistor comprises a first gate and a second gate arranged side by side; a first gate and a second gate of the input transistor are connected to a gate of the second control transistor; 15. A display substrate according to claim 12, wherein the gate of the second control transistor is further connected to the first clock signal line, the first clock signal line providing the first clock signal to the gate of the second control transistor and the first gate and the second gate of the input transistor.

16. a third transfer electrode extending in the first direction; 16. The display substrate of claim 15, wherein a first end of the third transfer electrode is connected to a gate of the second control transistor and a first gate and a second gate of the input transistor through a via hole penetrating an insulating layer, and a second end of the third transfer electrode is connected to a second electrode of the first control transistor.

17. The shift register unit further includes an output control circuit; the output control circuit is configured to control a level of the output terminal by control based on a level of the second node; the output control circuit comprises an output control transistor and a first capacitor; A display substrate according to any one of claims 12 to 16, wherein the orthogonal projection of the first capacitor on the base substrate is located on a side closer to the display area than the orthogonal projection of the active layer of the output control transistor on the base substrate, and the orthogonal projection of the first capacitor on the base substrate at least partially overlaps with the orthogonal projection of the first power supply line on the base substrate.

18. The display substrate of claim 17 , wherein the first capacitor is rectangular in shape.

19. Further comprising a fourth transfer electrode; the fourth transfer electrode is connected to a first electrode of the second noise reduction transistor and a first electrode of the output control transistor; a gate of the second noise reduction transistor is connected to a gate of the output control transistor; 19. A display substrate according to claim 17 or 18, wherein the fourth transfer electrode also comprises the second node.

20. Further comprising a fifth transfer electrode; the output circuit includes an output transistor and a second capacitor, and an orthogonal projection of the second capacitor on the base substrate is located on a side away from the display area of ​​an orthogonal projection of the first power line on the base substrate; 20. A display substrate according to claim 17, wherein a first electrode of the output transistor is connected to a first end of the fifth transfer electrode, and a gate of the first noise reduction transistor is connected to the fifth transfer electrode through a via hole penetrating an insulating layer.

21. 21. The display substrate of claim 20, wherein the second capacitor is rectangular.

22. a sixth transfer electrode extending in the second direction; a gate of the output transistor is connected to a first end of the sixth transfer electrode through a via hole penetrating an insulating layer, and a second end of the sixth transfer electrode is connected to a second pole of the voltage regulator transistor; 22. The display substrate of claim 20, wherein the sixth transfer electrode comprises the third node.

23. Further comprising a seventh transfer electrode; a first end of the seventh transfer electrode is connected to a second pole of the output control transistor, and a second end of the seventh transfer electrode is connected to a second pole of the output transistor; 23. The display substrate according to claim 20, wherein a second electrode of the output transistor is connected to a second electrode of an input transistor of a lower-stage shift register unit adjacent to the shift register unit.

24. an active layer of the output control transistor and at least a portion of an active layer of the output transistor are located in a continuous second semiconductor layer, and the second semiconductor layer extends in the first direction; 24. A display substrate according to claim 20, wherein a gate of the output control transistor and a gate of the output transistor extend in the second direction and are arranged side by side in the first direction, and a first electrode of the output control transistor is connected to the first power supply line to receive the first voltage.

25. A display device comprising the display substrate according to claim 1 .

26. 26. The display device according to claim 25, further comprising pixel units arranged in an array, wherein an output signal output by the output circuit of the shift register unit serves as a gate scanning signal to drive the pixel units to emit light.

27. A method for manufacturing a display substrate, comprising the steps of: providing a base substrate comprising a display area and a peripheral area surrounding at least the display area; forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line, and a second power supply line in a peripheral region of the base substrate, forming a semiconductor layer on a base substrate, and patterning the semiconductor layer to form active layers of a plurality of transistors in each circuit of the shift register unit; forming a first insulating material layer on a side of the active layers of the plurality of transistors away from the base substrate, and patterning the first insulating material layer to form a first insulating layer having via holes; forming a first conductive material layer on a side of the first insulating layer away from the base substrate, and patterning the first conductive material layer to form gates of the plurality of transistors, a plurality of connecting wires, and first poles of a plurality of capacitors in each circuit; forming a second insulating material layer on a side of the gates of the plurality of transistors away from the base substrate, and patterning the second insulating material layer to form a second insulating layer having via holes. forming a second conductive material layer on a side of the second insulating layer away from the base substrate and patterning the second conductive material layer to form second poles of the plurality of capacitors; forming a third insulating material layer on a side of the second insulating layer and second capacitor plates of the plurality of capacitors away from the base substrate and patterning the third insulating material layer to form a third insulating layer having via holes; forming a third conductive material layer on a side of the third insulating layer away from the base substrate and patterning the third conductive material layer to form first and second poles of the plurality of transistors, a plurality of transfer electrodes, the first clock signal line, the second clock signal line, the first power supply line and the second power supply line, a first pole and a second pole of each transistor are connected to an active layer of each transistor through a via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and each transistor and each capacitor are connected to each other through the plurality of connection wirings or the plurality of transfer electrodes and through a via hole penetrating the second insulating layer and the third insulating layer, and are connected to the first power supply line, the second power supply line, the first clock signal line, and the second clock signal line.

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