Display device and head-mounted display device including the same

Abstract

To provide a display device and head-mounted display device including the display device.SOLUTION: A display device includes: a first monocrystalline semiconductor substrate that has a plurality of first transistors formed; and a second monocrystalline semiconductor substrate that is arranged on the first monocrystalline semiconductor substrate, and has a plurality of second transistors formed. The second monocrystalline semiconductor substrate includes: a display area that has a plurality of sub-pixels including a light emitting element arranged; a plurality of first through-holes where a first conductivity via electrically connected to a plurality of data lines coupled to the plurality of sub-pixels is arranged; and a plurality of second through-holes where a second conductivity via electrically connected to a gate driving unit electrically connected to the sub-pixel is arranged. An area on a plane surface of the first monocrystalline semiconductor substrate is smaller than that on the plane surface of the second monocrystalline semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a display device and a head-mounted display device including the same. [Background technology]

[0002] A head mounted display device (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses on a nearby area in front of the user's eyes. Head mounted display devices can realize virtual reality (VR) or augmented reality (AR).

[0003] A head mounted display device magnifies an image displayed by a small display device using multiple lenses. Therefore, a display device applied to a head mounted display device needs to provide a high resolution image, for example, an image having a resolution of 3000 PPI (Pixels Per Inch) or more. For this reason, a high resolution small organic light emitting display device, OLEDoS (Organic Light Emitting Diode on Silicon), is used as a display device applied to a head mounted display device. OLEDoS is a device that displays an image by arranging an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a CMOS (Complementary Metal Oxide Semiconductor) is arranged. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide an ultra-small display device including a plurality of single crystal semiconductor substrates different from one another, and a head mounted display device including the same.

[0005] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS An object of the present invention is to provide a display device capable of minimizing the layout area of ​​a through hole connecting two different semiconductor substrates, and a head mounted display device including the same.

[0006] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] According to one embodiment of the present invention, there is provided a display device comprising: a first single crystal semiconductor substrate having a plurality of first transistors formed thereon; and a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon, the second single crystal semiconductor substrate comprising a display region in which a plurality of sub-pixels each including a light-emitting element are disposed; a plurality of first through holes in which first conductive vias are disposed and electrically connected to a plurality of data lines connected to the plurality of sub-pixels; and a plurality of second through holes in which second conductive vias are disposed and electrically connected to a gate driver electrically connected to the sub-pixels, the planar area of ​​the first single crystal semiconductor substrate being smaller than the planar area of ​​the second single crystal semiconductor substrate.

[0008] The number of the plurality of first through holes may be greater than the number of the plurality of second through holes.

[0009] The number of the first through holes may be equal to the number of pixel columns of the sub-pixels arranged in the display region.

[0010] The second single crystal semiconductor substrate may further include a circuit board disposed on a plurality of pads disposed in a non-display region surrounding the display region of the second single crystal semiconductor substrate, the second single crystal semiconductor substrate further including a plurality of third through holes overlapping the pads.

[0011] The plurality of first through holes may overlap the circuit board in a thickness direction.

[0012] The plurality of third through holes may overlap the circuit board and the first single crystal semiconductor substrate.

[0013] The plurality of first through holes may not overlap the pad.

[0014] The semiconductor device may further include a circuit board disposed on a lower surface of the first single crystal semiconductor substrate, the first single crystal semiconductor substrate further including a plurality of third through holes in which conductive vias connected to the circuit board are disposed.

[0015] The semiconductor memory device may further include a drive circuit portion disposed on the circuit board.

[0016] A width measured in one direction of the first single crystal semiconductor substrate may be greater than a width measured in the one direction of the display region.

[0017] The plurality of first through holes and the plurality of second through holes may be disposed in a non-display area around the display area.

[0018] The data line may be disposed on the second single crystal semiconductor substrate to extend in a first direction and be electrically connected to at least a portion of the first transistors, and may further include a plurality of scan lines extending on the second single crystal semiconductor substrate in a second direction intersecting the first direction and electrically connected to the gate driver.

[0019] The first through holes may be arranged in parallel with the data lines in the first direction.

[0020] The number of the first through holes may be the same as the number of the data lines.

[0021] The semiconductor device may further include an interconnect layer disposed between the second single crystal semiconductor substrate and the first single crystal semiconductor substrate, the interconnect layer being connected to the first conductive via and the second conductive via, respectively.

[0022] According to one embodiment for solving the above problem, there is provided a head mounted display device which is worn on a user's body and includes a frame corresponding to a left eye and a right eye, a plurality of display devices arranged on the frame, and lenses respectively arranged on the plurality of display devices, the display devices including a first single crystal semiconductor substrate having a plurality of first transistors formed thereon, and a second single crystal semiconductor substrate arranged on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon, the second single crystal semiconductor substrate including a display region in which a plurality of sub-pixels each including a light-emitting element are arranged, a plurality of first through holes in which first conductive vias electrically connected to a plurality of data lines connected to the plurality of sub-pixels are arranged, and a plurality of second through holes in which second conductive vias electrically connected to a gate driver electrically connected to the sub-pixels are arranged, and an area of ​​the first single crystal semiconductor substrate in a plane is smaller than an area of ​​the second single crystal semiconductor substrate in a plane.

[0023] The number of the first through holes may be equal to the number of pixel columns of the sub-pixels arranged in the display region.

[0024] A width measured in one direction of the first single crystal semiconductor substrate may be greater than a width measured in the one direction of the display region.

[0025] The plurality of first through holes and the plurality of second through holes may be disposed in a non-display area around the display area.

[0026] The second single crystal semiconductor substrate may further include a circuit board disposed on a plurality of pads disposed in a non-display region surrounding the display region of the second single crystal semiconductor substrate, the second single crystal semiconductor substrate may further include a plurality of third through holes overlapping the pads, and the plurality of first through holes may overlap the circuit board in a thickness direction.

[0027] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0028] The display device according to an embodiment includes two different single crystal semiconductor substrates, and a manufacturing process for the lower single crystal semiconductor substrate can be performed in multiple units per unit wafer substrate, thereby improving manufacturing yield.

[0029] In addition, in the display device according to the embodiment, the circuit units are disposed on two different single crystal semiconductor substrates, and the number of through holes connecting the two circuit units may be minimized. The display device may be able to ease a high degree of integration on a single crystal semiconductor substrate having a small area.

[0030] The effects of the embodiments are not limited to the above examples, and more diverse effects are included in the present specification. [Brief description of the drawings]

[0031] [Figure 1] 1 is an exploded perspective view of a display device according to an embodiment; [Diagram 2] 2 is a plan view showing an example of a drive unit shown in FIG. 1. [Diagram 3] 2 is a plan view showing an example of a display unit shown in FIG. 1. [Figure 4] 4 is a plan view showing the arrangement of a plurality of wirings arranged in the display unit of FIG. 3. [Diagram 5] 1 is a block diagram showing a display device according to an embodiment. [Figure 6] FIG. 4 is an equivalent circuit diagram of a sub-pixel according to an embodiment. [Figure 7] 1 is a schematic cross-sectional view of a display device according to an embodiment. [Figure 8] FIG. 2 is a schematic diagram showing a rear view of a display device according to an embodiment. [Figure 9] 2 is a schematic cross-sectional view of a drive according to one embodiment; [Figure 10] 3 is a plan view illustrating first electrodes, light-emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to an embodiment. [Figure 11]11 is a plan view illustrating first electrodes, light emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to another embodiment. [Figure 12] 2 is a cross-sectional view showing a portion of a display area and a non-display area of ​​a display unit according to an embodiment. [Figure 13] 2 is a cross-sectional view showing a portion of a display area and a non-display area of ​​a display unit according to an embodiment. [Figure 14] 11 is a schematic cross-sectional view of a display device according to another embodiment. [Figure 15] 11 is a schematic cross-sectional view of a display device according to another embodiment. [Figure 16] 11 is a schematic cross-sectional view of a display device according to still another embodiment. [Figure 17] FIG. 17 is a schematic diagram showing the display device of FIG. 16 as viewed from the back. [Figure 18] 1 is a perspective view showing a head mounted display device according to an embodiment; [Figure 19] FIG. 19 is an exploded perspective view showing an example of the head mounted display device of FIG. 18. [Figure 20] 1 is a perspective view showing a head mounted display device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The advantages and features of the present invention, as well as the methods for achieving them, will become clear from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0033] When an element or layer is referred to as "on" another element or layer, this includes the case where it is directly on top of or has other layers or elements intervening therebetween. Similarly, when it is referred to as "below," "left," and "right," this includes the case where it is directly adjacent to another element or has other layers or materials intervening therebetween. Like reference numbers refer to like elements throughout the specification.

[0034] Although the terms "first" and "second" are used to describe various components, it is to be understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is to be understood that the first component referred to below may be the second component within the technical concept of the present invention.

[0035] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0036] FIG. 1 is an exploded perspective view of a display device according to an embodiment.

[0037] Referring to FIG. 1, a display device 10 according to an embodiment is a device for displaying moving images or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), etc. For example, the display device 10 may be applied to a television, a notebook computer, a monitor, a billboard, or a display unit of the Internet of Things (IOT). Alternatively, the display device 10 may be applied to a smart watch, a watch phone, or a head mounted display for realizing virtual reality and augmented reality.

[0038] The display device 10 according to the embodiment may include a driver unit 100, a display unit 200, and a circuit board 300. The display device 10 may further include a protective layer 900 disposed around the driver unit 100.

[0039] The actuator 100 may have a planar shape similar to a rectangle. For example, the actuator 100 may have a planar shape similar to a rectangle having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The actuator 100 may have a side in the first direction DR1 and another side in the second direction DR2 that are different in length from each other. In the actuator 100, a corner where the one side in the first direction DR1 and the other side in the second direction DR2 meet may be rounded or right-angled to have a predetermined curvature. The planar shape of the actuator 100 is not limited to a rectangle, and may be formed as another polygon, circle, ellipse, or the like.

[0040] The display unit 200 may be disposed on the driver 100. In the display device 10, the driver 100 and the display unit 200 may be joined to each other. Unlike the driver 100, the display unit 200 may have a shape similar to a square. For example, the driver 100 may have a planar shape similar to a square in which one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1 have the same length. The planar shape of the display unit 200 is not limited to a rectangle, and may be formed into other polygonal shapes, a circle, an ellipse, or the like. The planar shape of the display device 10 may follow the planar shape of the display unit 200, but is not limited thereto.

[0041] According to an embodiment, the display device 10 may have a planar area of ​​the display unit 200 larger than the planar area of ​​the driver 100. The display device 10 may include a driver 100 and a display unit 200 including different substrates, and the areas may be different from each other. The elements formed in the driver 100 and the elements formed in the display unit 200 may be different from each other, and the elements may be formed separately on different substrates. The display device 10 may be manufactured by forming a plurality of elements having different sizes, line widths, manufacturing processes, etc. on different substrates and then bonding them, which is advantageous in improving product performance and manufacturing yield. This will be described in more detail below with reference to other drawings.

[0042] The circuit board 300 may be electrically connected to a plurality of pads in the pad region of the display unit 200 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is unfolded in FIG. 1, the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the lower surface of the driver 100. The other end of the circuit board 300 may be connected to a plurality of pads in the pad region of the display unit 200 using a conductive adhesive member. In another embodiment, the circuit board 300 may be attached to the lower surface of the driver 100.

[0043] Although not shown in the drawings, the display device 10 may further include a heat dissipation layer overlapping the driver 100 and the display unit 200 in the third direction DR3. The heat dissipation layer may be disposed on the lower surface of the driver 100 and may dissipate heat generated in the driver 100 and the display unit 200. The heat dissipation layer may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0044] The protective layer 900 may surround the driver 100 and be disposed on the lower surface of the display unit 200. The protective layer 900 may reduce a step due to an area difference between the driver 100 and the display unit 200, and may also protect the driver 100 and the display unit 200.

[0045] Fig. 2 is a plan view showing an example of the drive section shown in Fig. 1. Fig. 3 is a plan view showing an example of the display section shown in Fig. 1. Fig. 4 is a plan view showing the arrangement of a plurality of wirings arranged in the display section in Fig. 3.

[0046] 2 to 4, the driver 100 of the display device 10 may include a driving circuit element of the display device 10. The driver 100 may include a first single crystal semiconductor substrate 110, a driving circuit unit 400 formed on the first single crystal semiconductor substrate 110, and a data driver 700.

[0047] The first single crystal semiconductor substrate 110 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (GiGe) substrate. A plurality of first transistors may be formed on the first single crystal semiconductor substrate 110, and the plurality of first transistors may be electrically connected to each other to form the driving circuit unit 400 and the data driving unit 700. The first transistors may be formed by a semiconductor process. For example, the plurality of transistors may be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0048] In the drawings, the driving circuit unit 400 is disposed above the driving unit 100, and the data driver 700 and the first pad area PDA1 are disposed below the driving circuit unit 400. However, the present invention is not limited to this. The positions of the driving circuit unit 400 and the data driver 700 of the driving unit 100 may be variously changed depending on the design structure of a plurality of circuit elements formed on the first single crystal semiconductor substrate 110.

[0049] The first pad area PDA1 may include a plurality of first pads PD1 arranged in a first direction DR1. The plurality of first pads PD1 may be electrically connected to a plurality of second pads PD2 of the display unit 200, and thus may be electrically connected to the circuit board 300. The first pads PD1 may transmit an electrical signal applied from the circuit board 300 to the driving circuit unit 400, the gate drivers 610 and 620, and the data driver 700.

[0050] The display unit 200 may include a second single crystal semiconductor substrate 210, and a plurality of pixels PX and gate drivers 610, 620 formed on the second single crystal semiconductor substrate 210. The display unit 200 may include a display area DAA in which the plurality of pixels PX are arranged and a non-display area NA therearound. The gate drivers 610, 620 and a second pad area PDA2 may be arranged in the non-display area NA.

[0051] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of second transistors may be formed on the second single crystal semiconductor substrate 210, and the plurality of second transistors may be electrically connected to each other to form gate drivers 610 and 620 and a pixel circuit unit for emitting light from the plurality of pixels PX. The second transistors may be formed by a semiconductor process. For example, the plurality of transistors may be formed as CMOS transistors.

[0052] In the display area DAA, a plurality of pixels PX including a light-emitting element may be arranged. Each of the pixels PX may include three sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 constitute one pixel PX to display a color. However, without being limited thereto, one pixel PX may include three or more sub-pixels. The sub-pixels SP may be arranged in a matrix shape in a first direction DR1 and a second direction DR2. Each of the sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit (the pixel circuit of FIG. 6) including a plurality of second transistors formed on the second single crystal semiconductor substrate 210. Each of the sub-pixels SP1, SP2, and SP3 includes a light-emitting element, and the light-emitting element may emit light in response to an electrical signal applied from a pixel circuit arranged in the display area DAA.

[0053] Some of the sub-pixels SP1, SP2, and SP3 arranged in the display area DAA of the display unit 200 may overlap with the driver 100 in the thickness direction, and the other parts may not overlap with the driver 100. The driver 100 may have an area smaller than the display unit 200 and may be arranged adjacent to one side of the display unit 200. As a result, only some of the sub-pixels SP1, SP2, and SP3 overlap with the driver 100 in the thickness direction.

[0054] The display area DAA may include a plurality of scan lines GL extending in a first direction DR1 and arranged in a second direction DR2, and a plurality of data lines DL extending in the second direction DR2 and arranged in the first direction DR1. The plurality of scan lines GL may include different types of scan lines, for example, first to third scan lines (GWL, GCL, GBL in FIG. 5) and light emission control lines (EL1, EL2 in FIG. 5). The plurality of scan lines GL and data lines DL may be connected to the plurality of sub-pixels SP1, SP2, SP3 of the display area DAA, respectively. The plurality of scan lines GL may be electrically connected to the gate drivers 610 and 620 of the display unit 200, and the plurality of data lines DL may be electrically connected to the data driver 700 of the driver 100. The data lines DL may be electrically connected to the data driver 700 of the driver 100 through first through holes TSV1.

[0055] Each of the sub-pixels SP1, SP2, and SP3 can be electrically connected to a scan line GL and a data line DL. Each of the sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a scan signal from the scan line GL, and can cause a light-emitting element to emit light in response to the data voltage.

[0056] The non-display area NA may be disposed to surround the display area DAA. The non-display area NA may be an area in which the pixels PX are not disposed and therefore light is not emitted. The non-display area NA may be disposed with the gate drivers 610 and 620, the second pad area PDA2, and a number of through holes TSV1, TSV2, and TSV3.

[0057] The gate driver 610, 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the second single crystal semiconductor substrate 210, and the emission driver 620 may include a plurality of emission transistors formed on the second single crystal semiconductor substrate 210. The plurality of scan transistors and the plurality of emission transistors may be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed as CMOS transistors.

[0058] The scan driver 610 may be disposed on one side, that is, the left side, of the display area DAA in a first direction DR1, and the emission driver 620 may be disposed on the other side, that is, the right side, of the display area DAA in the first direction DR1. Each of the scan lines GL may be electrically connected to one of the scan driver 610 and the emission driver 620. For example, the first to third scan lines (GWL, GCL, and GBL in FIG. 5) of the scan lines GL may be connected to the scan driver 610, and the emission control lines (EL1 and EL2 in FIG. 5) may be connected to the emission driver 620.

[0059] The second pad area PDA2 may be disposed on a lower side, which is one side of the display area DAA in the second direction DR2. A plurality of second pads PD2 arranged in the first direction DR1 may be disposed in the second pad area PDA2. The second pads PD2 may be electrically connected to the first pads PD1 of the driver 100, and a circuit board 300 may be attached thereon. The second pad PD2 is electrically connected to the circuit board 300, and may transmit an electrical signal applied from the circuit board 300 to the driver 100.

[0060] The display device 10 according to an embodiment may include a plurality of through holes TSV1, TSV2, and TSV3 that form paths through which elements disposed in the driver 100 and the display unit 200 are electrically connected to each other. The plurality of through holes TSV1, TSV2, and TSV3 may be formed to penetrate the second single crystal semiconductor substrate 210 of the display unit 200. The driver circuit unit 400 and the data driver 700 disposed in the driver 100 may be electrically connected to the display unit 200 and the circuit board 300 via connection wiring disposed in the through holes TSV1, TSV2, and TSV3.

[0061] The multiple through holes TSV1, TSV2, TSV3 may include multiple first through holes TSV1, second through holes TSV2, and third through holes TSV3 arranged in the non-display area NA.

[0062] The first through holes TSV1 may be disposed on one side of the display area DAA of the non-display area NA. For example, the first through holes TSV1 may be disposed on the lower side of the display area DAA. In some embodiments, the first through holes TSV1 may be disposed in the second pad area PDA2 and may be disposed so as not to overlap with the second pad PD2. The first through holes TSV1 may be disposed to correspond to the data lines DL disposed in the display area DAA. The number of the first through holes TSV1 may be the same as the number of the data lines DL and the number of pixel columns of the sub-pixels SP1, SP2, and SP3 disposed in the display area DAA. Each of the data lines DL may correspond to the first through holes TSV1 and be electrically connected to the connection wiring disposed in the first through holes TSV1. Each of the sub-pixels SP1, SP2, and SP3 may receive a data signal from the data line DL connected to the driver 100 via the first through holes TSV1.

[0063] The second through holes TSV2 may be disposed in the gate drivers 610 and 620 of the non-display area NA. Some of the second through holes TSV2 may be disposed to overlap the scan driver 610, and the other may be disposed to overlap the light emitting driver 620. The second through holes TSV2 may have connection wiring for connecting the gate drivers 610 and 620 to the driver 100, and may receive signals for driving the gate drivers 610 and 620 from the driver 100. For example, the gate drivers 610 and 620 may be connected to connection wiring connected to the driver circuit unit 400 of the driver 100 via the second through holes TSV2, and may receive timing signals applied to the gate drivers 610 and 620.

[0064] The third through holes TSV3 may be arranged to overlap the second pads PD2 of the non-display area NA. The third through holes TSV3 may be arranged to correspond to the second pads PD2, and the number of the third through holes TSV3 may be the same as the number of the second pads PD2. The second pads PD2 may be electrically connected to the first pads PD1 of the driving unit 100 via the connection wiring arranged in the third through holes TSV3.

[0065] FIG. 5 is a block diagram illustrating a display device according to an embodiment.

[0066] 5, the driving circuit unit 400 may include a timing control circuit. The driving circuit unit 400 may further include various circuits involved in driving the display device 10, such as a gamma circuit and a logic circuit. The driving circuit unit 400 may include driving circuit transistors formed on the first single crystal semiconductor substrate 110.

[0067] The driving circuit unit 400 receives digital video data and timing signals from the outside. The timing control circuit may generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 in response to the timing signals. The timing control circuit may output the scan timing control signal SCS to the scan driver 610 of the gate driver 600 and output the light emission timing control signal ECS to the light emission driver 620 of the gate driver 600. The timing control circuit may output the digital video data and the data timing control signal DCS to the data driver 700.

[0068] The power supply unit 501 can generate a plurality of panel driving voltages in response to an external power supply voltage. For example, the power supply unit 501 can generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT and supply them to a plurality of pixels PX.

[0069] The scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit unit 400 are supplied to the pixels PX. The first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT of the power supply unit 501 can also be supplied to the pixels PX.

[0070] The gate driver 610, 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the second single crystal semiconductor substrate 210, and the emission driver 620 may include a plurality of emission transistors formed on the second single crystal semiconductor substrate 210. The plurality of scan transistors and the plurality of emission transistors may be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed as CMOS transistors.

[0071] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the driver circuit unit 400. The first scan signal output unit 611 may generate a write scan signal in response to the scan timing control signal SCS of the driver circuit unit 400 and sequentially output the write scan signal to the first scan line GWL. The second scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the second scan line GCL. The third scan signal output unit 613 may generate a bias scan signal in response to the scan timing control signal SCS and sequentially output the bias scan signal to the third scan line GBL.

[0072] The light emission driving unit 620 may include a first light emission signal output unit 621 and a second light emission signal output unit 622. The first light emission signal output unit 621 and the second light emission signal output unit 622 may each receive a light emission timing control signal ECS from the driving circuit unit 400. The light emission driving unit 620 may generate a light emission control signal in response to the light emission timing control signal ECS and sequentially output the light emission control signal to the first and second light emission control lines EL1 and EL2.

[0073] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the driver circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by a write scan signal from the scan driver 610, and a data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0074] The display area DAA of the display unit 200 may include a plurality of pixels PX, a plurality of data lines DL, a plurality of scan lines GWL, GCL, GBL, and a plurality of emission control lines EL. The plurality of scan lines may include a first scan line GWL, a second scan line GCL, and a third scan line GBL. The plurality of scan lines GWL, GCL, GBL, and the emission control lines EL1, EL2 may extend in a first direction DR1 and be spaced apart from each other in a second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1.

[0075] FIG. 6 is an equivalent circuit diagram of one pixel according to an embodiment.

[0076] 6, the sub-pixel SP1 may be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first light-emitting control line EL1, the second light-emitting control line EL2, and the data line DL. The sub-pixel SP1 may also be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be a lower voltage than the third driving voltage VINT. The second driving voltage VDD may be a higher voltage than the third driving voltage VINT.

[0077] The sub-pixel SP1 includes a plurality of transistors T1 to T6, a light emitting element (LE), a first capacitor C1, and a second capacitor C2.

[0078] The light emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light emitting element LE is proportional to the driving current Ids. The light emitting element LE may be disposed between the fourth transistor T4 and the first driving voltage line VSL. A first electrode of the light emitting element LE may be coupled to the drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode electrode, and the second electrode of the light emitting element LE may be a cathode electrode. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0079] The first transistor T1 may be a driving transistor that controls a source-drain current (Ids, hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode in response to a voltage applied to a gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0080] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Thus, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0081] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal of the control scan line GCL to connect the first node N1 to the second node N2. As a result, the gate electrode and source electrode of the first transistor T1 are connected to each other, so that the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0082] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first light emission control signal of the first light emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0083] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Thus, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0084] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second light emission control signal of the second light emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Thus, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0085] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 has one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0086] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL, and includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0087] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0088] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, each of some of the first to sixth transistors T1 to T6 may be a P-type MOSFET, and the remaining transistors may be an N-type MOSFET.

[0089] 6 illustrates an example in which the subpixel SP includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the subpixel SP is not limited to the case shown in FIG 6. For example, the numbers of transistors and capacitors of the subpixel SP are not limited to the case shown in FIG 6.

[0090] Fig. 7 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 8 is a schematic diagram showing a rear surface of a display device according to an embodiment. Fig. 7 shows a schematic arrangement of routing wiring RM1, RM2, and RM3 that electrically connects between a display unit 200 and a driver 100, and Fig. 8 shows an arrangement of a first through hole TSV1 and a second through hole TSV2 as viewed from the rear surface of the display device 10.

[0091] 7 and 8 in addition to Fig. 4, a display device 10 according to an embodiment may include a driving unit 100 including a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110, and a display unit 200 including a second single crystal semiconductor substrate 210 and a pixel circuit unit 220 and a display element layer 230 disposed on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 overlapping each other in a third direction DR3 that is a thickness direction of the display device 10.

[0092] The driver 100 may include circuit elements necessary for emitting light from the light emitting elements included in the display element layer 230 of the display unit 200. As described above, the driver circuit layer 120 of the driver 100 may include the driver circuit unit 400 and the data driver 700, and the circuit elements constituting these, for example, transistors and capacitors, may be formed on the first single crystal semiconductor substrate 110 using CMOS.

[0093] The display unit 200 may include a plurality of light emitting elements that emit light so as to display an image on the display device 10. The light emitting elements may be electrically connected to circuit elements formed in the driver 100 to emit light. The display unit 200 may also include a pixel circuit unit 220 in which circuit elements constituting a pixel circuit electrically connected to each of the sub-pixels SP1, SP2, and SP3, a plurality of wirings, and gate drivers 610 and 620 are arranged. The pixel circuit unit 220 may include circuit elements constituting a pixel circuit, for example, the first to sixth transistors T1 to T6 of FIG. 6, scan transistors constituting the gate drivers 610 and 620, a plurality of scan wirings GL, and a data line DL. The pixel circuit unit 220 may also include a plurality of terminals (DTD, GTD in FIG. 12) connected to through holes TSV1, TSV2, and TSV3 arranged in the non-display area NA of the display unit 200.

[0094] The protective layer 900 may be disposed around the driver 100. The protective layer 900 may surround the driver 100 and be disposed on the lower surface of the display unit 200. The protective layer 900 is formed to cover the driver 100 during the manufacturing process of the display device 10, and fills the step between the driver 100 and the display unit 200. When the first single crystal semiconductor substrate 110 is attached to the lower surface of the second single crystal semiconductor substrate 210 having a different area during the manufacturing process of the display device 10, the protective layer 900 fills the step between the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210, and an additional process may be performed on the second single crystal semiconductor substrate 210.

[0095] In one embodiment, the thickness of the protective layer 900 may be greater than or thicker than the thickness of the first single crystal semiconductor substrate 110. The protective layer 900 may be thicker than the first single crystal semiconductor substrate 110 of the driver 100 and the driver circuit layer 120 disposed thereon, or may be equal to the sum of their thicknesses. The protective layer 900 may be formed thicker than the driver 100, with one portion being in direct contact with the lower surface of the display unit 200 and the other portion being in direct contact with the lower surface of the driver 100. Therefore, the driver 100 and the display unit 200 may be completely covered by the protective layer 900 on the lower surface of the display device 10.

[0096] Furthermore, the protective layer 900 has the same planar area as the second single crystal semiconductor substrate 210, and the side surfaces of the protective layer 900 are aligned with the side surfaces of the second single crystal semiconductor substrate 210. The protective layer 900 may be divided together with the second single crystal semiconductor substrate 210 when the second single crystal semiconductor substrate 210 is divided into wafer substrates in the manufacturing process of the display device 10, and the planar area of ​​the protective layer 900 may be the same as the planar area of ​​the second single crystal semiconductor substrate 210. Even if the display device 10 includes the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210 having different planar areas, the protective layer 900 can compensate for all partial steps to ensure structural stability.

[0097] According to an embodiment, the display device 10 may have a planar area of ​​the driver 100 or the first single crystal semiconductor substrate 110 smaller than the planar area of ​​the display unit 200 or the second single crystal semiconductor substrate 210. The plurality of transistors formed in the driver 100 may be formed by a semiconductor microfabrication process and may have a very small size, line width, etc. The driver 100 has the advantage that a large number of circuit elements can be arranged with a high degree of integration, and power consumption can be reduced by miniaturizing the size of the elements.

[0098] In addition, since the driving unit 100 includes only circuit elements formed by CMOS on the first single crystal semiconductor substrate 110 and does not include light emitting elements, it is sufficient to secure a space for arranging elements formed by a micro-process. The first single crystal semiconductor substrate 110 may have an area smaller than that of the second single crystal semiconductor substrate 210, and a large number of driving units 100 can be manufactured on one wafer substrate on which the process of forming the driving circuit layer 120 is performed, thereby improving the manufacturing yield. In particular, since the driving unit 100 is manufactured through a high-cost semiconductor process, it is possible to achieve a cost reduction effect by improving the manufacturing yield of the driving unit 100. In addition, since the display unit 200 can have a large number of light emitting elements formed on the second single crystal semiconductor substrate 210 having a relatively large area, it is possible to realize a display device with high resolution.

[0099] According to an embodiment, the display device 10 may include a connecting wiring layer 500 disposed between the second single crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connecting wiring layer 500 may be disposed on a lower surface of the second single crystal semiconductor substrate 210. The connecting wiring layer 500 may include a plurality of routing wires RM1, RM2, and RM3, and the routing wires RM may connect the pixel circuit unit 220 and the circuit board 300 disposed on the display unit 200 to the driving unit 100. The driving circuit layer 120 of the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 via the routing wires RM1, RM2, and RM3 of the connecting wiring layer 500 to transmit an electrical signal for light emission.

[0100] The first routing wiring RM1 may be coupled to the data lines DL arranged in the display unit 200 and the data driver 700 arranged in the driver 100. The first routing wiring RM1 may be disposed in first through holes TSV1 formed in the second single crystal semiconductor substrate 210, and may include data routing wiring GDL of the connecting wiring layer 500. The first through holes TSV1 are disposed in the non-display area NA of the display unit 200, and may not overlap with the driver 100 in the thickness direction.

[0101] In one embodiment, the plurality of first through holes TSV1 are disposed in the second pad area PDA2 of the non-display area NA of the display unit 200, and may not overlap the driver 100 in the thickness direction, but may overlap the circuit board 300 in the thickness direction. A portion of the first routing wiring RM1 is disposed in the first through hole TSV1, and a data routing wiring GDL is disposed in the connection wiring layer 500, and may connect the first through hole TSV1 that does not overlap the driver 100 and the data driver 700. As described above, the display unit 200 may have a larger planar area than the driver 100, and the driver 100 disposed on the rear surface of the display unit 200 may not overlap the non-display area NA of the display unit 200. Thus, the routing wiring RM1, RM2, RM3 may include wiring that connects the through holes TSV1, TSV2, TSV3 and the driver 100.

[0102] According to an embodiment, the number of the first through holes TSV1 may be the same as the number of pixel columns of the sub-pixels SP1, SP2, and SP3 arranged in the display area DAA. For example, the sub-pixels SP1, SP2, and SP3 may be arranged in the first direction DR1 and the second direction DR2 in the display area DAA, and when the number of pixel columns arranged in the first direction DR1 is 4000, the number of the first through holes TSV1 may also be the same, 4000. The first through holes TSV1 correspond 1:1 to the pixel columns of the sub-pixels SP1, SP2, and SP3 arranged in the first direction DR1, and also correspond 1:1 to the data lines DL and the first routing wiring RM1 arranged in the first direction DR1. One data line DL arranged in parallel with one pixel column may be connected to the data driver 700 via the first routing wiring RM1 arranged in one first through hole TSV1. The first routing wires RM1 and the first through holes TSV1 can be arranged in numbers equal to the number of pixel columns and the number of data lines DL, respectively.

[0103] In addition, the data lines DL may extend in the second direction DR2 and be connected to the first through holes TSV1 in parallel even in the non-display area NA without being bent. In the display device 10, the data lines DL may be maintained at a constant interval in the display area DAA and the non-display area NA of the display unit 200, and a fan-out structure in which the data lines DL are bent and narrowed in the non-display area NA may be omitted. The spacing between the first through holes TSV1 and the data routing lines GDL may also be maintained constant, similar to the data lines DL. The driving unit 100 of the display device 10 may have a width such that the data lines DL and the data routing lines GDL spaced apart at equal intervals can be arranged extending in parallel. For example, the driving unit 100 of the display device 10 may have a width measured in the first direction DR1 larger than the width measured in the first direction DR1 of the display area DAA. In the display device 10, the data lines DL are connected to the driving unit 100 through the first through holes TSV1 and may be arranged in parallel without a fan-out structure, thereby minimizing interference between adjacent wirings.

[0104] The second routing wiring RM2 may be connected to the gate drivers 610 and 620 disposed in the display unit 200 and the driving circuit unit 400 disposed in the driving unit 100. The second routing wiring RM2 may be disposed in a second through hole TSV2 formed in the second single crystal semiconductor substrate 210 and may include a control routing wiring TCL of the connection wiring layer 500. The second through holes TSV2 are disposed in the non-display area NA of the display unit 200 and may not overlap the driving unit 100 and the circuit board 300 in the thickness direction. In some embodiments, the second through holes TSV2 may be disposed to overlap the scan driver 610 and the light emitting driver 620, respectively.

[0105] The second routing wiring RM2 is partially disposed within the second through hole TSV2, and the control routing wiring TCL is disposed in the connection wiring layer 500, and may connect between the second through hole TSV2 that does not overlap with the driver 100 and the driver 100.

[0106] The gate drivers 610 and 620 are electrically connected to the driver circuit unit 400 of the driver 100 and may receive timing control signals. Unlike the first through holes TSV1 and the first routing wires RM1, the second through holes TSV2 and the second routing wires RM2 may not be arranged in a 1:1 correspondence with the number of the scan wires GL. In one embodiment, the number of the second through holes TSV2 and the second routing wires RM2 may be less than the number of the first through holes TSV1 and the first routing wires RM1, respectively.

[0107] The third routing wiring RM3 may be connected to the second pad PD2 disposed in the display unit 200 and the first pad PD1 disposed in the driving unit 100. The third routing wiring RM3 may be disposed in a third through hole TSV3 formed in the second single crystal semiconductor substrate 210. The third through hole TSV3 is disposed to overlap the second pad PD2 and the circuit board 300 in the second pad area PDA2, and a portion of the third routing wiring RM3 may be disposed in the connecting wiring layer 500 and disposed to overlap the driving unit 100. The third routing wiring RM3 may be a wiring that transmits a signal applied from the circuit board 300 to the driving unit 100.

[0108] The routing wirings RM1, RM2, and RM3 may include connecting wirings ("RML1", "RML2", and "RML3" in FIGS. 12 and 13) arranged in the connecting wiring layer 500 and conductive vias ("RVA1", "RVA2", and "RVA3" in FIGS. 12 and 13) arranged in the through holes TSV1, TSV2, and TSV3 of the second single crystal semiconductor substrate 210. The routing wirings RM1, RM2, and RM3 are wirings that electrically connect layers arranged above and below the second single crystal semiconductor substrate 210 based on the second single crystal semiconductor substrate 210, and the arrangement and design of the through holes formed in the second single crystal semiconductor substrate 210 may change depending on the arrangement of the layers electrically connected to the routing wirings RM.

[0109] In the display device 10, the driving unit 100 has an area smaller than that of the display unit 200 and partially overlaps with the display area DAA, but may not overlap with the through-holes TSV1, TSV2, and TSV3 arranged in the non-display area NA. As a result, the driving unit 100 may partially overlap with the connection wiring ("RML1", "RML2", and "RML3" in FIG. 12 and FIG. 13) that is connected to the conductive vias RVA1, RVA2, and RVA3 of the routing wirings RM1, RM2, and RM3 arranged in the through-holes TSV1, TSV2, and TSV3. As illustrated in FIG. 8, the driving unit 100 may partially overlap with the data routing wiring GDL and the control routing wiring TCL.

[0110] The display device 10 may include a driver 100 and a display unit 200 including different single crystal semiconductor substrates 110 and 210, routing wires RM1, RM2, and RM3 connecting the driver 100 and the display unit 200, and through holes TSV1, TSV2, and TSV3 in which the wirings RM1, RM2, and RM3 are arranged. The through holes TSV1, TSV2, and TSV3 are arranged to penetrate the second single crystal semiconductor substrate 210 of the display unit 200, and therefore need to have a predetermined diameter and a certain interval. In the display device 10, the driver circuit unit 400, the gate drivers 610 and 620, and the data driver 700 connected to a plurality of sub-pixels SP1, SP2, and SP3 are appropriately divided and arranged in the driver 100 and the display unit 200, and the number of routing wires RM1, RM2, and RM3 connecting the driver 100 and the display unit 200 may be appropriately minimized. The number of the through holes TSV1, TSV2, TSV3 can be reduced to a level that allows them to be arranged in the non-display area NA of the display unit 200, and the area in which the through holes TSV1, TSV2, TSV3 are arranged can also be minimized. Since the display device 10 has a small number of through holes TSV1, TSV2, TSV3, even if the area of ​​the non-display area NA in which the through holes TSV1, TSV2, TSV3 are arranged is small, the through holes TSV1, TSV2, TSV3 can be arranged with a necessary and sufficient diameter and interval. This can also reduce interference between the routing wirings RM1, RM2, RM3 arranged in the through holes TSV1, TSV2, TSV3.

[0111] Hereinafter, the structures of the driving circuit layer 120 of the driving unit 100 and the display element layer 230 of the display unit 200 will be described in detail with further reference to other drawings.

[0112] FIG. 9 is a schematic cross-sectional view of a drive unit according to one embodiment.

[0113] 9, the driver 100 may include a first single crystal semiconductor substrate 110 and a driver circuit layer 120 disposed thereon. FIG 9 is a schematic cross-sectional view of a data driver 700 among the circuit units disposed in the driver 100.

[0114] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with a first type impurity. A plurality of well regions WA may be disposed on an upper surface of the first single crystal semiconductor substrate 110. The plurality of well regions WA may be regions doped with a second type impurity. The second type impurity may be different from the first type impurity described above. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Or, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0115] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the first transistor PTR1, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0116] A lower insulating film BINS may be disposed between the gate electrode GE and the well region WA. A side insulating film SINS may be disposed on a side surface of the gate electrode GE. The side insulating film SINS may be disposed on the lower insulating film BINS.

[0117] The source region SA and the drain region DA may each be a region doped with a first type impurity. The gate electrode GE of the first transistor PTR1 may overlap the well region WA in a third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side of the gate electrode GE.

[0118] Each of the well regions WA further includes a first low concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The first low concentration impurity region LDD1 and the second low concentration impurity region LDD2 may increase the distance between the source region SA and the drain region DA. Therefore, the length of the channel region CH of each of the first transistors PTR1 may be increased, thereby preventing punch-through and hot carrier phenomena due to a short channel.

[0119] The first single crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driver 100. The first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may constitute the driver circuit unit 400 or the data driver 700.

[0120] After the driving circuit layer 120 is formed on the silicon wafer substrate, a process for reducing the thickness of the first single crystal semiconductor substrate 110 is performed. The first single crystal semiconductor substrate 110 may have a thickness thinner than that of a wafer substrate on which a semiconductor process for forming the driving circuit layer 120 is performed. In some embodiments, the thickness of the first single crystal semiconductor substrate 110 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0121] The drive circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The drive circuit layer 120 may include wiring electrically connected to a plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0122] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be disposed on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 may be an insulating layer disposed on the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer disposed on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be formed of silicon carbonitride (SiCN), silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In the drawings, the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each formed of a single layer having a predetermined thickness, but are not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which at least one layer is stacked on top of each other.

[0123] The plurality of contact electrodes CTE may be disposed on the first single crystal semiconductor substrate 110. The plurality of contact electrodes CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the first transistors PTR1 formed on the first single crystal semiconductor substrate 110 via holes penetrating the semiconductor insulating layers SINS1 and SINS2. The plurality of contact electrodes CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The plurality of contact electrodes CTE may have an upper surface exposed without being covered by the semiconductor insulating layers SINS1 and SINS2.

[0124] The first interlayer insulating layer INS1 may be disposed on the contact electrodes CTE and the semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may be formed of silicon carbonitride (SiCN) or silicon oxide (SiO x)-based inorganic film, but is not limited thereto. In the drawings, the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are each formed of one layer, but are not limited thereto. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may each have a structure in which at least one layer is stacked on top of each other, and these may be disposed between a plurality of first to eighth conductive layers ML1 to ML8 described below.

[0125] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are electrically connected to the contact electrodes CTE to form the driving circuit unit 400 or the data driver 700 of the driver 100. The first transistors PTR1 formed on the first single crystal semiconductor substrate 110 are electrically connected to each other via the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 to form the driving circuit unit 400 and the data driver 700 of the driver 100.

[0126] The first conductive layer ML1 may be coupled to the contact electrode CTE through the first via VA1. The first conductive layer ML1 may be disposed on the contact electrode CTE, and the first via VA1 may be disposed between the first conductive layer ML1 and the contact electrode CTE to contact them, respectively. The second conductive layer ML2 may be coupled to the first conductive layer ML1 through the second via VA2. The second conductive layer ML2 may be disposed on the first conductive layer ML1, and the second via VA2 may be disposed between the first conductive layer ML1 and the second conductive layer ML2 to contact them, respectively.

[0127] The third conductive layer ML3 may be connected to the second conductive layer ML2 through the third via VA3. The fourth conductive layer ML4 may be connected to the third conductive layer ML3 through the fourth via VA4, the fifth conductive layer ML5 may be connected to the fourth conductive layer ML4 through the fifth via VA5, and the sixth conductive layer ML6 may be connected to the fifth conductive layer ML5 through the sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be sequentially arranged on the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be arranged between them. The third to sixth vias VA6 may be in contact with different metal layers arranged above and below them, respectively. The seventh via VA7 may be arranged on the sixth conductive layer ML6. The seventh via VA7 may be in contact with the seventh conductive layer ML7 and the sixth conductive layer ML6 arranged thereon, respectively.

[0128] The first to sixth conductive layers ML1-ML6 and the first to seventh vias VA1-VA7 may be disposed on the first interlayer insulating layer INS1. The first to sixth conductive layers ML1-ML6 and the first to seventh vias VA1-VA7 may constitute a first drive circuit layer that is disposed on the first interlayer insulating layer INS1 of the drive circuit layer 120.

[0129] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through the seventh via VA7. The seventh conductive layer ML7 may be disposed on the first interlayer insulating layer INS1 and the sixth conductive layer ML6, and the seventh via VA7 may be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 and contact them, respectively. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through the eighth via VA8. The eighth conductive layer ML8 may be disposed on the seventh conductive layer ML7, and the eighth via VA8 may be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 and contact them, respectively. The upper surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2, and may be electrically connected to the routing wiring RM disposed in the display unit 200 described above.

[0130] The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 may be disposed in the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 may constitute a second drive circuit layer of the drive circuit layer 120 disposed in the second interlayer insulating layer INS2.

[0131] Although the drawings illustrate a structure in which the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are sequentially stacked on one another, their arrangement and connection may be modified in various ways according to the circuits of the driving circuit unit 400 and the data driver 700 of the driver 100. The connection structure illustrated in the drawings is only one example, and the connection of the driving circuit layer 120 arranged in the driving unit 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 does not necessarily have to include the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8, and some of these layers may be omitted or a greater number of layers may be arranged.

[0132] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are made of substantially the same material, for example, the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these.

[0133] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360 Å, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may each be approximately 1440 Å, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 may each be approximately 1150 Å.

[0134] The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be approximately 6000 Å.

[0135] FIG. 10 is a plan view illustrating first electrodes, light emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to an embodiment.

[0136] 10, each of the pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first to third sub-pixels SP1, SP2, and SP3 may include light-emitting regions EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first light-emitting region EA1, the second sub-pixel SP2 may include a second light-emitting region EA2, and the third sub-pixel SP3 may include a third light-emitting region EA3.

[0137] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a quadrangular planar shape such as a rectangle, a square, or a diamond. For example, the first light-emitting region EA1 may have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. Also, each of the second light-emitting region EA2 and the third light-emitting region EA3 may have a rectangular planar shape with a long side in the first direction DR1 and a short side in the second direction DR2.

[0138] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be an area defined by a pixel defining film PDL. For example, each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be an area defined by a first pixel defining film PDL1.

[0139] The length in the first direction DR1 of the third light-emitting region EA3 may be smaller than the length in the first direction DR1 of the first light-emitting region EA1 and may be smaller than the length in the first direction DR1 of the second light-emitting region EA2. The length in the first direction DR1 of the first light-emitting region EA1 and the length in the first direction DR1 of the second light-emitting region EA2 may be substantially the same.

[0140] In each of the pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in the second direction DR2. The first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different from each other.

[0141] Although the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 each have a rectangular planar shape in the drawings, the present invention is not limited thereto. For example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each have a polygonal, circular, or elliptical planar shape other than a rectangular shape.

[0142] The first light-emitting area EA1 may emit a first color light, the second light-emitting area EA2 may emit a second color light, and the third light-emitting area EA3 may emit a third color light. Here, the first color light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. For example, the blue wavelength band refers to a wavelength band in which the main peak wavelength of the light is approximately 370 nm to 460 nm, the green wavelength band refers to a wavelength band in which the main peak wavelength of the light is approximately 480 nm to 560 nm, and the red wavelength band refers to a wavelength band in which the main peak wavelength of the light is approximately 600 nm to 750 nm.

[0143] The first electrode AND of the light-emitting element may have a rectangular planar shape. The planar shapes of the first electrodes AND of the light-emitting element may be different among the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. The first electrode AND of the third subpixel SP3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. The length in the first direction DR1 of the first electrode AND of the third subpixel SP3 may be shorter than the length in the second direction DR2 of the first electrodes AND of the first subpixel SP1 and the second subpixel SP2. The length in the second direction DR2 of the first electrode AND of the first subpixel SP1 may be longer than the length in the second direction DR2 of the first electrode AND of the second subpixel SP2.

[0144] A first electrode AND of the light emitting element may be connected to a reflective electrode layer (RL in FIG. 12) through an electrode via VAP. The electrode via VAP may overlap the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 in the third direction DR3.

[0145] At least one trench TRC may be a structure for cutting at least one charge generation layer of the light emitting stack IL between the adjacent light emitting regions EA1, EA2, EA3. At least one trench TRC may be disposed between the first light emitting region EA1 and the second light emitting region EA2, between the first light emitting region EA1 and the third light emitting region EA3, and between the second light emitting region EA2 and the third light emitting region EA3. More specifically, at least one trench TRC may be disposed between the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2, between the first electrode AND of the first subpixel SP1 and the first electrode AND of the third subpixel SP3, and between the first electrode AND of the second subpixel SP2 and the first electrode AND of the third subpixel SP3.

[0146] FIG. 11 is a plan view illustrating first electrodes, light emitting regions, and pixel defining layers of a plurality of sub-pixels arranged in a display area of ​​a display unit according to another embodiment.

[0147] Referring to Figure 11, except that the planar shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are different from those of the embodiment of Figure 10, the embodiment of Figure 11 is substantially the same as that of Figure 10, and therefore, descriptions overlapping with those of the embodiment of Figure 10 will be omitted.

[0148] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be arranged in a hexagonal structure having a hexagonal planar shape. In this case, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in a first direction DR1, the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in a first diagonal direction DD1, and the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in a second diagonal direction DD2. The first diagonal direction DD1 is a direction between the first direction DR1 and the second direction DR2, and indicates a direction inclined at 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 may be a direction perpendicular to the first diagonal direction DD1.

[0149] 10 and 11 show an example in which each of the pixels PX includes three light emitting areas EA1, EA2, and EA3, but the present invention is not limited thereto, that is, each of the pixels PX may include four light emitting areas.

[0150] In addition, the arrangement of the light emitting regions of the pixels PX is not limited to that shown in the drawings. For example, the light emitting regions of the pixels PX may be arranged in a stripe structure in which the light emitting regions are arranged in a first direction DR1, in a PenTile structure in which the light emitting regions are arranged in a diamond shape, or in a hexagonal structure in which light emitting regions having a hexagonal planar shape are arranged.

[0151] 12 and 13 are cross-sectional views showing a part of a display area and a non-display area of ​​a display unit according to an embodiment. In FIG. 12 and FIG. 13, schematic cross-sectional structures of the display area DAA, the non-display area NA, and the pad area PDA are disclosed.

[0152] 12 and 13, the display unit 200 may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, and a cover layer DCL. Although not shown in the drawings, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The connecting wiring layer 500 may be disposed between the second single crystal semiconductor substrate 210 and the first single crystal semiconductor substrate 110 of the semiconductor backplane SBP. Alternatively, the connecting wiring layer 500 may be disposed between the light-emitting element layer EML and the first single crystal semiconductor substrate 110.

[0153] The semiconductor backplane SBP includes a second single crystal semiconductor substrate 210 including a plurality of second transistors PTR2, a plurality of semiconductor insulating layers disposed on the plurality of second transistors PTR2, and a plurality of contact electrodes CTE electrically connected to the plurality of pixel transistors, respectively. The plurality of second transistors PTR2 may be the first to sixth transistors T1 to T6 constituting the pixel circuit of FIG. 6, or may be scan transistors of the gate drivers 610 and 620.

[0154] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. A plurality of well regions WA may be disposed on an upper surface of the second single crystal semiconductor substrate 210. The plurality of well regions WA may be regions doped with second type impurities. The second type impurities may be different from the first type impurities described above. For example, if the first type impurities are p-type impurities, the second type impurities may be n-type impurities. Or, if the first type impurities are n-type impurities, the second type impurities may be p-type impurities.

[0155] The second single crystal semiconductor substrate 210 may include a plurality of second transistors PTR2, similar to the first single crystal semiconductor substrate 110. The structure of the second transistor PTR2 is similar to that of the first transistor PTR1, and therefore will not be described in detail.

[0156] In the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driving unit 100 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 of the display unit 200 may be formed on different wafer substrates. According to an embodiment, in the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 may have different sizes, line widths, etc.

[0157] For example, in the display device 10, the minimum line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be smaller than the minimum line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The semiconductor process performed on the first wafer substrate to form the first transistor PTR1 may be a process having a higher resolution than the semiconductor process performed on the second wafer substrate to form the second transistor PTR2, and thus the size of the manufactured elements such as transistors may be smaller. In other words, the semiconductor process performed on the first wafer substrate may be a finer process than the semiconductor process performed on the second wafer substrate.

[0158] As described above, the first single crystal semiconductor substrate 110 of the driving unit 100 may have a smaller planar area than the second single crystal semiconductor substrate 210 of the display unit 200, and small-sized elements may be arranged with a high degree of integration, thereby reducing power consumption and improving manufacturing yield. On the other hand, the second single crystal semiconductor substrate 210 of the display unit 200 may have a larger planar area than the first single crystal semiconductor substrate 110, and a process with a relatively large line width may be performed. The second transistor PTR2 arranged on the second single crystal semiconductor substrate 210 may be formed with a larger area than when formed on the first single crystal semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit does not require a high degree of integration. As a result, the semiconductor process performed on the first wafer substrate may be performed by a high-cost process with a small line width, and the semiconductor process performed on the second wafer substrate may be performed by a low-cost process with a relatively large line width.

[0159] In an exemplary embodiment, the transistors PTR1 and PTR2 may have different lengths of channel regions CH, and the minimum line width or length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width or length of the channel region CH of the second transistor PTR2. The minimum line width or length of the channel region CH of the first transistor PTR1 may be 100 nm or less, or may range from 2 nm to 80 nm. The minimum line width or length of the channel region CH of the second transistor PTR2 may be 100 nm or more, or may range from 100 nm to 5 μm.

[0160] The second single crystal semiconductor substrate 210 may include a plurality of through holes TSV1, TSV2, TSV3 spaced apart from each other. The through holes TSV1, TSV2, TSV3 may penetrate the second single crystal semiconductor substrate 210 from the upper surface to the lower surface, and may also penetrate a plurality of semiconductor insulating layers SINS3, SINS4 and interlayer insulating layers INS3, INS4, INS5 disposed on the second single crystal semiconductor substrate 210. Conductive vias RVA1, RVA2, RVA3 of the routing wirings RM1, RM2, RM3 may be disposed in the through holes TSV1, TSV2, TSV3. The through holes TSV1, TSV2, TSV3 may form connection paths of the routing wirings RM1, RM2, RM3 that electrically connect the driving unit 100 to the pixel circuit unit 220 and the second pad PD2 of the display unit 200. In some embodiments, the through holes TSV1, TSV2, and TSV3 of the second single crystal semiconductor substrate 210 may be formed by a TSV (Through Silicon Via) process for forming holes penetrating a wafer substrate. The display element layer 230 and the driver 100 may be electrically connected to each other via routing wirings RM1, RM2, and RM3 through the through holes TSV1, TSV2, and TSV3 formed in the second single crystal semiconductor substrate 210 without additional wires.

[0161] The second single crystal semiconductor substrate 210 is subjected to a process of reducing its thickness after the actuator 100 is bonded onto the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness thinner than that of the wafer substrate on which a process for forming a conductive layer is performed. In some embodiments, the second single crystal semiconductor substrate 210 may have a thickness of 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0162] The pixel circuit unit 220 may be disposed on the second single crystal semiconductor substrate 210. The pixel circuit unit 220 may include a semiconductor backplane SBP and a part of a light emitting element backplane EBP.

[0163] A third semiconductor insulating layer SINS3 may be disposed on the second single crystal semiconductor substrate 210. The third semiconductor insulating layer SINS3 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0164] The fourth semiconductor insulating film SINS4 may be disposed on the third semiconductor insulating layer SINS3. The fourth semiconductor insulating film SINS4 may be formed of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0165] Each of the contact electrodes CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of the second transistor PTR2 through a hole penetrating the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4. The contact electrodes CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these materials.

[0166] The light-emitting element backplane EBP may include third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7, and a plurality of routing conductive layers RMT. The routing conductive layer RMT may include wiring electrically connected to a plurality of second transistors PTR2 formed on the second single crystal semiconductor substrate 210, a plurality of scan lines GL and data lines DL arranged in the display unit 200, and a plurality of terminals DTD and GTD.

[0167] A third interlayer insulating layer INS3 may be disposed on the plurality of contact electrodes CTE and the semiconductor insulating layers SINS3, SINS4. A fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3. A fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, and a seventh interlayer insulating layer INS7 may be sequentially disposed on the fourth interlayer insulating layer INS4. A plurality of routing conductive layers RMT may be disposed between the fifth interlayer insulating layer INS5 to the seventh interlayer insulating layer INS7. The third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 may be formed of silicon carbonitride (SiCN), or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In the drawings, the third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 are each formed as one layer, but are not limited thereto. The third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 may each have a structure in which at least one layer is stacked on top of each other, and these may be disposed between a plurality of first to eighth conductive layers ML1 to ML8 described below.

[0168] The routing conductive layer RMT may include a structure similar to the conductive layers ML1 to ML8 and the vias VA1 to VA8 of the driving circuit layer 120. The routing conductive layer RMT may include at least one conductive layer and vias disposed between them, and may constitute wiring or terminals DTD and GTD disposed in the display unit 200. For example, the routing conductive layer RMT disposed in the display area DAA of the pixel circuit unit 220 may be electrically connected to the second transistor PTR2. The routing conductive layer RMT illustrated in the drawing may be connected to the second transistors PTR2 to constitute the pixel circuit of FIG. 6. The routing conductive layer RMT may serve as a connecting wiring that connects the second transistor PTR2 to other circuit elements. Although not illustrated in the drawing, a part of the routing conductive layer RMT disposed in the display area DAA of the pixel circuit unit 220 may serve as a scan wiring GL or a data line DL, or as a connecting wiring that constitutes the gate drivers 610 and 620.

[0169] The pixel circuit unit 220 may include a plurality of terminals DTD, GTD disposed in the non-display area NA. The plurality of terminals DTD may include a data terminal DTD electrically connected to the data line DL, and a gate terminal GTD connected to the gate drivers 610, 620. The data terminal DTD may be electrically connected to the data line DL and a first routing line RM1, and the gate terminal GTD may be electrically connected to the gate drivers 610, 620 and a second routing line RM2.

[0170] The interconnect layer 500 may be disposed on the lower surface of the second single crystal semiconductor substrate 210. The interconnect layer 500 may include an interlayer insulating layer RINS and a plurality of interconnects RML1, RML2, and RML3.

[0171] An interlayer insulating layer RINS may be disposed on the lower surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be made of silicon carbonitride (SiCN) or silicon oxide (SiO xIn the drawings, the interlayer insulating layers RINS are formed of a single layer, but the present invention is not limited thereto, and may have a structure in which at least one layer is stacked on top of each other, and these may be disposed between the connecting wires RML1, RML2, and RML3.

[0172] The connecting wirings RML1, RML2, RML3 may form routing wirings RM1, RM2, RM3 together with a plurality of conductive vias RVA1, RVA2, RVA3. The connecting wirings RML1, RML2, RML3 may include at least one conductive layer and one or more vias connecting the conductive layers to each other. The connections and structures of the connecting wirings RML1, RML2, RML3 are the same as those described above for the plurality of conductive layers ML1 to ML8 and vias VA1 to VA8. The connecting wirings RML1, RML2, RML3 may be electrically connected to the pixel circuit unit 220 or the second pad PD2 through the conductive vias RVA1, RVA2, RVA3 arranged in the through holes TSV1, TSV2, TSV3 of the second single crystal semiconductor substrate 210, and may be electrically connected to the driving circuit layer 120 of the driving unit 100.

[0173] According to an embodiment, the display unit 200 of the display device 10 may include a first through hole TSV1, a second through hole TSV2, and a third through hole TSV3 penetrating the second single crystal semiconductor substrate 210. The first to third through holes TSV1, TSV2, and TSV3 may be disposed in the non-display area NA. As described above, the first through hole TSV1 and the third through hole TSV3 may be disposed in the pad area PDA of the display unit 200, and the second through hole TSV2 may be disposed to overlap the gate drivers 610 and 620 in the non-display area NA.

[0174] The first through hole TSV1 may have a first routing wiring RM1 arranged therein, which connects the data terminal DTD connected to the data line DL and the driving circuit layer 120 of the driving unit 100. The first through hole TSV1 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5, and may penetrate from the lower surface of the data terminal DTD to the lower surface of the second single crystal semiconductor substrate 210. The first conductive via RVA1 may be arranged from the lower surface of the data terminal DTD to the lower surface of the second single crystal semiconductor substrate 210, and may be connected to the data terminal DTD and the first connecting wiring RML1, respectively. The first connecting wiring RML1 may be the data routing wiring GDL described above with reference to FIG. 8.

[0175] The second through hole TSV2 may be disposed with a second routing wiring RM2 connecting the gate terminal GTD connected to the gate drivers 610 and 620 and the driving circuit layer 120 of the driver 100. The second through hole TSV2 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5, and may penetrate from the lower surface of the gate terminal GTD to the lower surface of the second single crystal semiconductor substrate 210. The second conductive via RVA2 may be disposed from the lower surface of the gate terminal GTD to the lower surface of the second single crystal semiconductor substrate 210 and connected to the gate terminal GTD and the second connecting wiring RML2, respectively. The second connecting wiring RML2 may be the control routing wiring TCL described above with reference to FIG. 8.

[0176] The through holes and conductive vias arranged in the non-display area NA shown in Fig. 12 may be the first through hole TSV1 or the second through hole TSV2, and the first conductive via RVA1 or the second conductive via RVA2, respectively. The terminals shown in Fig. 12 may be the data terminal DTD or the gate terminal GTD. The first routing wiring RM1 and the second routing wiring RM2, and the first through hole TSV1 and the second through hole TSV2 are only different in their arranged positions, numbers, and connection relationships, and have substantially the same cross-sectional structure.

[0177] The third through hole TSV3 may have a third routing wiring RM3 arranged therein, which connects the second pad PD2 arranged in the pad area PDA of the display unit 200 and the first pad PD1 of the driving unit 100. The third through hole TSV3 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5, and may penetrate from the lower surface of the second pad PD2 to the lower surface of the second single crystal semiconductor substrate 210. The third conductive via RVA3 may be arranged from the lower surface of the second pad PD2 to the lower surface of the second single crystal semiconductor substrate 210, and may be connected to the second pad PD2 and the third connecting wiring RML3, respectively.

[0178] In the display device 10, the circuit unit formed in the driving unit 100 can be formed by a high-cost fine semiconductor process, and can be formed with a high degree of integration on the first single crystal semiconductor substrate 110 having a small area. The manufacturing process of the driving unit 100 can have a high yield per unit wafer substrate, and the power consumption can be reduced by having a small size of the circuit element (e.g., the first transistor). In addition, by arranging the pixel circuit for emitting the light emitting element, some circuit elements, and wiring in the display unit 200, it is possible to prevent the degree of integration of the first single crystal semiconductor substrate 110 from being excessively increased. In addition, by optimizing the number of through holes TSV1, TSV2, and TSV3 in which the routing wiring RM1, RM2, and RM3 connecting them are arranged, the space in which the through holes TSV1, TSV2, and TSV3, which require a certain diameter and spacing, are arranged, can be minimized.

[0179] The reflective electrode layer RL may be disposed on the seventh interlayer insulating layer INS7. The reflective electrode layer RL may include at least one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode RL may include first to fourth reflective electrodes RL1, RL2, RL3, and RL4 as shown in FIG.

[0180] Each of the first reflective electrodes RL1 may be disposed on the seventh interlayer insulating layer INS7 and connected to a via penetrating the seventh interlayer insulating layer INS7. The first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0181] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0182] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrodes RL2. The third reflective electrodes RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0183] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrodes RL4 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the fourth reflective electrodes RL4 may include titanium (Ti).

[0184] The second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element, and the thickness of the second reflective electrode RL2 may be greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å.

[0185] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7. The eighth interlayer insulating layer INS8 may be disposed between adjacent reflective electrode layers RL. The eighth interlayer insulating layer INS8 may be disposed on the reflective electrode layer RL in the first subpixel SP1. The eighth interlayer insulating layer INS8 may be formed of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0186] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the reflective electrode layer RL. The ninth interlayer insulating layer INS9 may be formed of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0187] In at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 may not be arranged below the first electrode AND, taking into account the resonance distance of the light emitted from the light-emitting element LE.

[0188] For example, the first electrode AND of the third subpixel SP3 may be disposed directly on the fourth reflective electrode RL4, and the first electrode AND of the third subpixel SP3 may not overlap the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9. The first electrode AND of the second subpixel SP2 may be disposed on the ninth interlayer insulating layer INS9, but the ninth interlayer insulating layer INS9 may be disposed directly on the fourth reflective electrode RL4. That is, the first electrode AND of the second subpixel SP2 may not overlap the eighth interlayer insulating layer INS8. The first electrode AND of the first subpixel SP1 may be disposed on the ninth interlayer insulating layer INS9 and may overlap the eighth interlayer insulating layer INS8.

[0189] In one embodiment, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 according to the main wavelength of the emitted light, it is possible to set whether to include the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, in FIG. 12, the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3. However, the present invention is not limited thereto, and the distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 can be modified and designed in various ways.

[0190] In addition, although the drawings illustrate an example in which the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 are disposed, a tenth interlayer insulating layer may be further disposed under the first electrode AND of the subpixel SP. In this case, the ninth interlayer insulating layer INS9 and the tenth interlayer insulating layer may be disposed under the first electrode AND of the second subpixel SP2, and the eighth interlayer insulating layer INS8, the ninth interlayer insulating layer INS9, and the tenth interlayer insulating layer may be disposed under the first electrode AND of the first subpixel SP1.

[0191] Each of the electrode vias VAP may be connected to the fourth reflective electrode RL4 exposed through the eighth interlayer insulating layer INS8 and / or the ninth interlayer insulating layer INS9 in the first subpixel SP1 and the second subpixel SP2. The electrode via VAP may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The thickness of the electrode via VAP in the second subpixel SP2 may be smaller than the thickness of the electrode via VAP in the first subpixel SP1.

[0192] The display element layer 230 may be disposed on the light-emitting element backplane EBP. The display element layer 230 may include a light-emitting element layer EML, a sealing layer TFE, an optical layer OPL, and a cover layer DCL. The display element layer 230 may include a light-emitting element electrically connected to the pixel circuit unit 220 and the driving unit 100 to emit light.

[0193] The light-emitting element layer EML may be disposed on the reflective layer IL and the ninth interlayer insulating layer INS9. The light-emitting element layer EML may include a light-emitting element including a first electrode AND, a light-emitting stack IL, and a second electrode CAT, respectively, a pixel defining film PDL, and a plurality of trenches TRC.

[0194] The first electrode AND of each light emitting element may be disposed on the ninth interlayer insulating layer INS9 or the reflective electrode layer RL and connected to the electrode via VAP. The first electrode AND of each light emitting element LE may be connected to the second transistor PTR2 through the electrode via VAP, the first to fourth reflective electrodes RL1 to RL4, the routing conductive layer RMT, and the contact electrode CTE. The first electrode AND of each light emitting element may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first electrode AND of each light emitting element may be titanium nitride (TiN).

[0195] The pixel definition film PDL may be disposed on a portion of the first electrode AND of each light-emitting element. The pixel definition film PDL may cover an edge of the first electrode AND of each light-emitting element. The pixel definition film PDL serves to divide the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0196] The first light-emitting region EA1 can be defined as a region in the first subpixel SP1 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The second light-emitting region EA2 can be defined as a region in the second subpixel SP2 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The third light-emitting region EA3 can be defined as a region in the third subpixel SP3 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light.

[0197] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 may be disposed on an edge of the first electrode AND of each light-emitting element LE, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be formed of silicon oxide (SiO x The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0198] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as one pixel defining layer, the height of the one pixel defining layer increases, and the first inorganic encapsulation layer TFE1 may be cut due to step coverage. Step coverage refers to the ratio of the degree to which the thin film is applied to a sloped portion to the degree to which the thin film is applied to a flat portion. The lower the step coverage, the higher the possibility that the thin film will be cut at the sloped portion.

[0199] To prevent the first inorganic sealing layer TFE1 from being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure having a step-shaped difference. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second pixel defining film PDL2 and the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined by the first direction DR1 and the second direction DR2.

[0200] Each of the trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In each of the trenches TRC, a part of the eighth interlayer insulating layer INS8 may be recessed, and the ninth interlayer insulating layer INS9 may penetrate the trenches TRC.

[0201] At least one trench TRC may be disposed between the adjacent sub-pixels SP1, SP2, and SP3. Although two trenches TRC are disposed between the adjacent sub-pixels SP1, SP2, and SP3 in the examples shown in Figs. 12 and 13, the present invention is not limited thereto.

[0202] The luminescent stack IL may include multiple intermediate layers. Although the luminescent stack IL is illustrated in the drawings as having a three-tandem structure including a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3, the present invention is not limited thereto. For example, the luminescent stack IL may have a two-tandem structure including two intermediate layers.

[0203] In the three-tandem structure, the light-emitting stack IL may have a tandem structure including multiple intermediate layers IL1, IL2, IL3 that emit different light from each other. For example, the light-emitting stack IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0204] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked.

[0205] A first charge generation layer may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2 to supply charges to the second intermediate layer IL2 and to supply electrons to the first intermediate layer IL1. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first intermediate layer IL1 and a P-type charge generation layer that supplies holes to the second intermediate layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0206] A second charge generation layer may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3 to supply charges to the third intermediate layer IL3 and to supply electrons to the second intermediate layer IL2. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second intermediate layer IL2 and a P-type charge generation layer that supplies holes to the third intermediate layer IL3.

[0207] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel definition film PDL, and may be disposed on the bottom surface of the trench TRC in each of the trenches TRC. The trench TRC may separate the first intermediate layer IL1 between the adjacent sub-pixels SP1, SP2, and SP3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. The trench TRC may separate the second intermediate layer IL2 between the adjacent sub-pixels SP1, SP2, and SP3. A cavity or an empty space may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. The third intermediate layer IL3 may be disposed so as not to be separated by the trench TRC, and to cover the second intermediate layer IL2 in each of the trenches TRC. That is, in the 3-tandem structure, each of the trenches TRC may be a structure for cutting the first and second intermediate layers IL1 and IL2, the first charge generation layer, and the second charge generation layer of the light emitting element layer EML between the adjacent subpixels SP1, SP2, and SP3. Also, in the 2-tandem structure, each of the trenches TRC may be a structure for cutting the charge generation layer and the lower intermediate layer disposed between the lower intermediate layer and the upper intermediate layer.

[0208] In order to stably cut the first and second intermediate layers IL1, IL2 of the light emitting element layer EML between the adjacent sub-pixels SP1, SP2, SP3, the height of each of the trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the trenches TRC refers to the length of each of the trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut the first to third intermediate layers IL1, IL2, IL3 of the light emitting element layer EML between the adjacent sub-pixels SP1, SP2, SP3, other structures may be present instead of the trenches TRC. For example, a reverse tapered partition wall may be disposed on the pixel defining layer PDL instead of the trenches TRC.

[0209] The number of intermediate layers IL1, IL2, IL3 that emit different light from each other is not limited to that shown in the drawings. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the intermediate layers and charge to the other intermediate layer.

[0210] 12 and 13 show an example in which the first to third intermediate layers IL1, IL2, and IL3 are all disposed in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, but the present invention is not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first light-emitting region EA1, and may not be disposed in the second light-emitting region EA2 and the third light-emitting region EA3. The second intermediate layer IL2 may be disposed in the second light-emitting region EA2, and may not be disposed in the first light-emitting region EA1 and the third light-emitting region EA3. The third intermediate layer IL3 may be disposed in the third light-emitting region EA3, and may not be disposed in the first light-emitting region EA1 and the second light-emitting region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0211] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO that transmits light, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive metallic material, the microcavities increase the light output efficiency in each of the first to third sub-pixels SP1, SP2, and SP3.

[0212] The encapsulating layer TFE may be disposed on the light-emitting element layer EML. The encapsulating layer TFE may include at least one inorganic encapsulating layer TFE1, TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulating layer TFE may also include at least one organic film to protect the light-emitting element layer EML from foreign matter such as dust. For example, the encapsulating layer TFE may include a first inorganic encapsulating layer TFE1, an organic encapsulating layer TFE2, and a second inorganic encapsulating layer TFE3.

[0213] The first inorganic sealing layer TFE1 may be disposed on the second electrode CAT, the organic sealing layer TFE2 may be disposed on the first inorganic sealing layer TFE1, and the second inorganic sealing layer TFE3 may be disposed on the organic sealing layer TFE2. The first inorganic sealing layer TFE1 and the second inorganic sealing layer TFE3 may be formed of silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), and an aluminum oxide layer (AlO x ) may be formed as a multi-layer in which one or more inorganic films are alternately laminated. The organic encapsulation layer TFE2 may be a monomer. Alternatively, the organic encapsulation layer TFE2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0214] The adhesive layer ADL may be disposed on the sealing layer TFE. The adhesive layer ADL may be a layer for adhering the sealing layer TFE to a layer disposed thereon. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may also be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0215] The optical layer OPL may include a color filter layer CFL, a plurality of lenses LNS, and a filler layer FIL. The color filter layer CFL may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0216] The first color filter CF1 may overlap the first light-emitting area EA1. The first color filter CF1 may transmit a first color light, i.e., light in a red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. The first color filter CF1 may transmit the first color light among the light emitted from the first light-emitting area EA1.

[0217] The second color filter CF2 may overlap the second light-emitting area EA2. The second color filter CF2 may transmit light of a second color, i.e., light in a green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. The second color filter CF2 may transmit light of the second color among the light emitted from the second light-emitting area EA2.

[0218] The third color filter CF3 may overlap the third light-emitting area EA3. The third color filter CF3 may transmit a third color light, i.e., light in a blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. The third color filter CF3 may transmit the third color light among the light emitted from the third light-emitting area EA3.

[0219] Each of the lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the lenses LNS may be a structure for increasing the ratio of light directed toward the front of the display device 10. Each of the lenses LNS may have a cross-sectional shape that is convex toward the upper side.

[0220] The fill layer FIL may be disposed on the lenses LNS. The fill layer FIL may have a predetermined refractive index for light to travel in the third direction DR3 at an interface between the lenses LNS and the fill layer FIL. The fill layer FIL may also be a planarization layer. The fill layer FIL may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0221] The cover layer DCL may be disposed on the filling layer FIL. The cover layer DCL may be a glass substrate or a polymer resin such as resin. When the cover layer DCL is a glass substrate, it may be attached onto the filling layer FIL. In this case, the filling layer FIL may serve to adhere the cover layer DCL. When the cover layer DCL is a glass substrate, it may serve as a sealing substrate. When the cover layer DCL is a polymer resin such as resin, it may be directly applied onto the filling layer FIL.

[0222] Although not shown in the drawings, the display unit 200 may further include a polarizing plate disposed on the cover layer DCL. The polarizing plate may be disposed on one surface of the cover layer DCL. The polarizing plate may be a structure for preventing a decrease in visibility due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be, but is not limited to, a λ / 4 plate. However, if the visibility due to reflection of external light is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizing plate may be omitted.

[0223] Various embodiments of the display device 10 will now be described with reference to other drawings.

[0224] 14 and 15 are schematic cross-sectional views of display devices according to other embodiments.

[0225] 14, in the display device 10 according to an embodiment, the driving circuit unit 400 of the driving unit 100 may be disposed on the circuit board 300. The driving circuit unit 400 may be disposed on the circuit board 300 in the form of a separate chip without including the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driving unit 100. Thus, the gate drivers 610 and 620 may be electrically connected to the driving circuit unit 400 via a second pad PD2 disposed on the display unit 200, and the data driver 700 may be electrically connected to the driving circuit unit 400 via a second routing wire RM2. Although not shown in the drawing, the second routing wire RM2 may be electrically connected to the circuit board 300 and the driving circuit unit 400 via the second pad PD2.

[0226] 15, in the display device 10 according to an embodiment, a circuit board 300 may be disposed on a rear surface of the driver 100. The first single crystal semiconductor substrate 110 of the driver 100 may include a through hole penetrating therethrough, and a third routing wiring RM3 may be disposed in the through hole. The circuit board 300 may be attached to the rear surface of the driver 100 and the protective layer 900, and may be electrically connected to the driver circuit unit 400 and / or the data driver 700 of the driver 100 via the third routing wiring RM3 disposed in the through hole penetrating the first single crystal semiconductor substrate 110.

[0227] The third through hole TSV3 may be omitted and only the first through hole TSV1 and the second through hole TSV2 may be formed in the second single crystal semiconductor substrate 210 of the display unit 200. The display unit 200 and the driver 100 may be connected to each other via a first routing wire RM1 and a second routing wire RM2.

[0228] Fig. 16 is a schematic cross-sectional view of a display device according to another embodiment. Fig. 17 is a schematic view of the display device of Fig. 16 as seen from the rear.

[0229] 16 and 17, in the display device 10 according to the embodiment, the connecting wiring layer 500 is omitted, and the through holes TSV1, TSV2, TSV3 and the routing wirings RM1, RM2, RM3 may overlap the driver 100. In the display device 10, the area of ​​the driver 100 may be larger than that of the embodiment of FIGS. 7 and 8, and the driver 100 may overlap with the first to third through holes TSV1, TSV2, TSV3 formed in the display unit 200. As the area of ​​the driver 100 is larger, terminals connected to the routing wirings RM1, RM2, RM3 may be formed in the driver 100 at positions corresponding to the first to third through holes TSV1, TSV2, TSV3. The first to third routing wires RM1, RM2, and RM3 may include only conductive vias RVA1, RVA2, and RVA3 disposed in the through holes TSV1, TSV2, and TSV3, and the conductive vias RVA1, RVA2, and RVA3 may directly contact terminals formed on the driving circuit layer 120 of the driving unit 100. For example, the first routing wire RM1 may directly contact a terminal connected to the data driving unit 700, the second routing wire RM2 may directly contact a terminal connected to the driving circuit unit 400, and the third routing wire RM3 may directly contact the first pad PD1.

[0230] In the display device 10, the area of ​​the driving unit 100 is smaller than the area of ​​the display unit 200, but the driving unit 100 can be large enough to cover the area in which the multiple through holes TSV1, TSV2, and TSV3 are arranged. This makes it possible to omit the connection wiring of the routing wiring RM1, RM2, and RM3 that connects the through holes TSV1, TSV2, and TSV3 and the driving unit 100.

[0231] Fig. 18 is a perspective view showing a head mounted display device according to an embodiment, and Fig. 19 is an exploded perspective view showing an example of the head mounted display device of Fig. 18.

[0232] Referring to Figures 18 and 19, a head mounted display device 1000 according to one embodiment includes a first display device 11, a second display device 12, a display device storage section 1100, a storage section cover 1200, a first eyepiece lens 1210, a second eyepiece lens 1220, a head mounting band 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0233] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Since the first display device 11 and the second display device 12 are substantially the same as the display device 10 described with reference to FIG. 1, the description of the first display device 11 and the second display device 12 will be omitted.

[0234] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0235] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The middle frame 1400 serves to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0236] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving part 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 via a connector. The control circuit board 1600 may convert an externally input image source into digital video data DATA and transmit the digital video data DATA to the first display device 11 and the second display device 12 via the connector.

[0237] The control circuit board 1600 can transmit digital video data DATA corresponding to a left eye image optimized for the user's left eye to the first display device 11 and transmit digital video data DATA corresponding to a right eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 11 and the second display device 12.

[0238] The display device housing 1100 serves to house the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is disposed to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 on which the user's left eye is disposed and a second eyepiece 1220 on which the user's right eye is disposed. Although the drawings illustrate a case in which the first eyepiece 1210 and the second eyepiece 1220 are disposed separately, the present invention is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be integrated.

[0239] The first eyepiece 1210 is aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 is aligned with the second display device 12 and the second optical member 1520. Thus, the user can view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0240] The head mounting band 1300 serves to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be maintained in a state in which they are positioned over the left and right eyes of the user, respectively. When the display device housing 1100 is realized to be lightweight and compact, the head mounted display device 1000 may include a glasses frame instead of the head mounting band 1300 as shown in FIG.

[0241] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving a supply of an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0242] FIG. 20 is a perspective view showing a head mounted display device according to an embodiment.

[0243] 20, the head mounted display device 1000_1 according to an embodiment may be a display device in the form of glasses in which the display device housing 1200_1 is realized to be lightweight and small. The head mounted display device 1000_1 according to an embodiment may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and the display device housing 1200_1.

[0244] The display device housing 1200_1 may include a display device 13, an optical member 1060, and an optical path conversion member 1070. An image displayed on the display device 13 is enlarged by the optical member 1060, and the optical path is converted by the optical path conversion member 1070, and the image is provided to the right eye of the user via the right eye lens 1020. This allows the user to view an augmented reality image that combines a virtual image displayed on the display device 13 and a real image seen through the right eye lens 1020 via the right eye.

[0245] In the drawings, the display device housing 1200_1 is disposed at the right end of the support frame 1030, but is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, in which case an image of the display device 13 is provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 13 through both the left and right eyes.

[0246] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0247] 10 Display device 100 Drive unit 110 First single crystal semiconductor substrate 120 Drive circuit layer 200 Display section 210 Second single crystal semiconductor substrate 220 Sub-pixel circuit section 230 Display element layer 300 Circuit Boards 400 Drive circuit section 500 interconnect wiring layers 600 Gate driver 700 Data Drive Unit 800 Pixel circuit section 1000 Head-mounted display device MIL reflective layer EML Light emitting element layer TFE sealing layer OPL optical layer INS Interlayer insulation layer SINS Semiconductor insulating layer

Claims

1. a first single crystal semiconductor substrate having a plurality of first transistors formed thereon; and a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon; the second single crystal semiconductor substrate includes a display region in which a plurality of sub-pixels, each including a light emitting element, are arranged, a plurality of first through holes in which first conductive vias are arranged and electrically connected to a plurality of data lines connected to the plurality of sub-pixels, and a plurality of second through holes in which second conductive vias are arranged and electrically connected to a gate driver electrically connected to the sub-pixels, A display device, wherein a planar area of ​​the first single crystal semiconductor substrate is smaller than a planar area of ​​the second single crystal semiconductor substrate.

2. The display device according to claim 1 , wherein the number of the first through holes is greater than the number of the second through holes.

3. The display device according to claim 1 , wherein the number of the first through holes is equal to the number of pixel columns of the sub-pixels arranged in the display region.

4. a circuit board disposed on a plurality of pads disposed in a non-display area surrounding the display area of ​​the second single crystal semiconductor substrate; The display device according to claim 1 , wherein the second single crystal semiconductor substrate further includes a plurality of third through holes overlapping the pads.

5. The display device according to claim 4 , wherein the first through holes overlap the circuit board in a thickness direction.

6. The display device according to claim 4 , wherein the third through holes overlap the circuit board and the first single crystal semiconductor substrate.

7. The display device according to claim 4 , wherein the plurality of first through holes do not overlap the pads.

8. a circuit board disposed on a lower surface of the first single crystal semiconductor substrate; The display device of claim 1 , wherein the first single crystal semiconductor substrate further comprises a plurality of third through holes in which conductive vias connected to the circuit board are disposed.

9. The display device according to claim 8 , further comprising a drive circuit portion disposed on the circuit board.

10. The display device according to claim 1 , wherein a width measured in one direction of the first single crystal semiconductor substrate is greater than a width measured in the one direction of the display region.

11. The display device according to claim 1 , wherein the first through holes and the second through holes are disposed in a non-display area around the display area.

12. the data line is disposed on the second single crystal semiconductor substrate and extends in a first direction, and is electrically connected to at least a portion of the first transistor; The display device of claim 1 , further comprising a plurality of scan lines extending on the second single crystal semiconductor substrate in a second direction intersecting the first direction and electrically connected to the gate driver.

13. The display device according to claim 12 , wherein the first through holes are arranged adjacent to the data lines in the first direction.

14. The display device of claim 12 , wherein the number of the first through holes is the same as the number of the data lines.

15. disposed between the second single crystal semiconductor substrate and the first single crystal semiconductor substrate; The display device of claim 1 , further comprising an interconnect layer connected to the first conductive via and the second conductive via, respectively.

16. a frame that is worn on the user's body and corresponds to the left and right eyes; a plurality of display devices disposed in the frame; and a lens disposed on each of the plurality of display devices; The display device includes a first single crystal semiconductor substrate having a plurality of first transistors formed thereon; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of second transistors formed thereon; the second single crystal semiconductor substrate includes a display region in which a plurality of sub-pixels, each including a light emitting element, are arranged, a plurality of first through holes in which first conductive vias are arranged and electrically connected to a plurality of data lines connected to the plurality of sub-pixels, and a plurality of second through holes in which second conductive vias are arranged and electrically connected to a gate driver electrically connected to the sub-pixels, a planar area of ​​the first single crystal semiconductor substrate is smaller than a planar area of ​​the second single crystal semiconductor substrate.

17. The head mounted display device of claim 16 , wherein the number of the first through holes is the same as the number of pixel columns of the sub-pixels arranged in the display region.

18. The head mounted display device of claim 16 , wherein a width measured in one direction of the first single crystal semiconductor substrate is greater than a width measured in the one direction of the display region.

19. The head mounted display device according to claim 18 , wherein the plurality of first through holes and the plurality of second through holes are respectively arranged in a non-display area around the display area.

20. a circuit board disposed on a plurality of pads disposed in a non-display area surrounding the display area of ​​the second single crystal semiconductor substrate; the second single crystal semiconductor substrate further includes a plurality of third through holes overlapping the pads, The head mounted display device according to claim 16 , wherein the first through holes overlap the circuit board in a thickness direction.

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