Memory-in-pixel display

Abstract

To provide a display system that reduces reliance on a frame buffer for temporarily storing image data outside pixels.SOLUTION: A display system 52 may include an active area having a first pixel 70 formed in the active area, the first pixel 70 emitting light in response to image data 86. The display system 52 may also include a timing controller 54 to transmit the image data 86 to the first pixel 70. The first pixel 70 may include a memory 78 to digitally store the image data 86 received from the timing controller 54 and a driver (DRV) 80 to receive the image data 86 from the memory 78. The driver (DRV) 80 may cause light to be emitted in response to the image data 86.SELECTED DRAWING: Figure 6

Description

Summary of the Invention

[0001] A summary of certain embodiments disclosed herein is presented below. It should be understood that these aspects are presented only to provide the reader with an overview of these particular embodiments and are not intended to limit the scope of this disclosure. Indeed, the present disclosure may encompass various aspects not described below.

[0002] Methods and systems for reducing the bandwidth, or the amount transmitted simultaneously, of image data transmitted and processed to prepare an image for presentation on an electronic display by implementing in-memory pixels of the electronic display can provide immeasurable value. Such an implementation of in-memory pixels can enable the elimination of a frame buffer associated with the electronic display. By having memory in the pixels, not only can the complexity of the design of the electronic display be reduced, but since less image data is transmitted simultaneously to the pixel array of the electronic display, the electronic display can be designed more simply. For example, since the memory within the pixel stores values until the time of image presentation, the pixels can be programmed in smaller groups.

[0003] The present disclosure describes an electronic display having one or more pixels including memory and drivers that can help reduce the bandwidth associated with the transmission and processing of image data for presentation on the electronic display. By including memory within the pixels, it is possible to store the image data before outputting it to the light-emitting portion of the pixel. Thus, the memory within the pixel can function as an individual frame buffer for the pixel, reducing or, in some cases, eliminating the dependence on the frame buffer within the electronic display. The memory within the pixel may be used with a driver to cause the light-emitting portion of the pixel to emit light.

Brief Description of the Drawings

[0004] By reading the following "Mode for Carrying Out the Invention" and referring to the following drawings, various aspects of the present disclosure can be better understood.

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[0043] In the following, one or more specific embodiments will be described. In order to provide a concise description of these embodiments, not all features of the actual embodiments are shown in this specification. As in any engineering project or design project, it should be understood that in the development of any such actual implementation, numerous implementation-specific decisions must be made to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, although such development efforts may be complex and time-consuming, it should be understood that for those skilled in the art having the benefits of the present disclosure, they are routine work in design, fabrication, and manufacturing.

[0044] When introducing elements of various embodiments of the present disclosure, the articles "a", "an", and "the" mean that there are one or more elements. The terms "comprising", "including", and "having" are intended to be inclusive and mean that there may be additional elements other than the recited elements. Further, it should be understood that references to "an embodiment" or "embodiments" of the present disclosure are not intended to be construed as excluding the existence of additional embodiments that incorporate the recited features.

[0045] Electronic displays are installed in everything from mobile phones to computers, televisions, automotive dashboards, and many other electronic devices. Electronic displays have achieved higher resolutions by reducing the size of individual pixels. However, as the resolution increases, it can increase the difficulties associated with managing the increased image data, for example, by causing an increase in power consumption by processing the increased image data, which is associated with the increase in resolution processed by the processing circuit before the image is displayed. Further, as the resolution increases, more image data is used to communicate the same image at a higher electronic display resolution, which can increase the bandwidth used to communicate the image data to the pixel array for presenting the image from the processing circuit.

[0046] Embodiments of the present disclosure relate to systems and methods for implementing an in-pixel memory circuit that can be used as an individual frame buffer for each pixel, which can reduce the dependence on an external frame buffer of a pixel array and a driving circuit of an electronic display. The memory can be implemented within a pixel circuit including a light-emitting diode (LED). An organic light-emitting diode (OLED) represents one type of LED that can be found in a pixel, but other types of LEDs may also be used, and other types of LEDs may be used in pixel circuits such as components that support a liquid crystal display (LCD), a plasma display panel, and / or a dot matrix display.

[0047] The systems and methods of the present disclosure for implementing an in-pixel memory circuit can reduce the transmission bandwidth of image data to a pixel array for display because the pixel can store image data in the memory. In this way, since the pixel has its own memory for storing its own image data before displaying the image data, the dependence on a frame buffer for temporarily storing the image data outside the pixel is reduced.

[0048] A general description of a self-emitting display such as an LED (e.g., OLED) display and a suitable electronic device including the corresponding circuit of the present disclosure is provided. OLED represents one type of LED that can be found in self-emitting pixels, but other types of LEDs may also be used.

[0049] For illustrative purposes, an electronic device 10 including an electronic display 18 is shown in FIG. 1. As will be described in more detail below, the electronic device 10 can be any suitable electronic device such as a computer, a mobile phone, a portable media device, a tablet, a television, a virtual reality headset, a vehicle dashboard, etc. Thus, it should be noted that FIG. 1 is only an example of a specific implementation form and is intended to illustrate the types of components that may exist within the electronic device 10. The electronic device 10 can include, among other things, a processing core complex 12 such as a system-on-chip (SoC) and / or a system on a processing circuit(s), a memory device(s) 14, a communication interface(s) 16, an electronic display 18, an input structure 20, and a power supply 22. It should be noted that the various components described in FIG. 1 may include hardware elements (e.g., circuits), software elements (e.g., tangible non-transitory computer-readable media storing instructions), or a combination of both hardware elements and software elements. It should be noted that the various illustrated components may be combined into fewer components or divided into additional components.

[0050] As shown, the processing core complex 12 is operatively coupled to the memory device(s) 14. Thus, the processing core complex 12 executes instructions stored in the memory device(s) 14 to perform operations such as generating and / or transmitting image data. In this way, the processing core complex 12 can include one or more general-purpose microprocessors, one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof. Using pixels that include light-emitting components (e.g., LEDs, OLEDs), the electronic display 18 can display the image generated by the processing core complex 12.

[0051] In addition to instructions, the memory device(s) 14 can store data processed by the processing core complex 12. Thus, in some embodiments, the memory device 14 can include one or more tangible non-transitory computer-readable media. The memory device(s) 14 can be volatile and / or non-volatile. For example, the memory device(s) 14 can include random access memory (RAM) and / or read-only memory (ROM), flash memory, a hard drive, rewritable non-volatile memory such as an optical disk, or any combination thereof.

[0052] As shown, the processing core complex 12 is also operatively coupled to a communication interface(s) 16. In some embodiments, the communication interface(s) 16 can facilitate communicating data with another electronic device and / or network. For example, the communication interface(s) 16 (e.g., a radio frequency system) can communicatively couple the electronic device 10 to a personal area network (PAN) such as a Bluetooth® network, a local area network (LAN) such as an 802.11x Wi-Fi® network, and / or a wide area network (WAN) such as a 4G or Long Term Evolution (LTE) cellular network.

[0053] In addition, as shown, the processing core complex 12 is also operatively coupled to a power source 22. In some embodiments, the power source 22 can supply power to the processing core complex 12 and / or one or more components within the electronic device 10 such as the electronic display 18. Accordingly, the power source 22 may include any suitable energy source such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0054] As illustrated, the electronic device 10 is also operatively coupled to one or more input structures 20. In some embodiments, the input structure 20 can facilitate user interaction with the electronic device 10, for example, by receiving user input. Accordingly, the input structure 20 may include buttons, a keyboard, a mouse, a trackpad, etc. In addition, in some embodiments, the input structure 20 can include a touch sensing component within the electronic display 18. In such embodiments, the touch sensing component can receive user input by detecting the presence and / or position of an object touching the surface of the electronic display 18.

[0055] In addition to enabling user input, the electronic display 18 can include a display panel having one or more display pixels. As described above, the electronic display 18 controls the light emission from the display pixels to display a frame based at least in part on the corresponding image data, thereby presenting a visual representation of information such as a graphical user interface (GUI) of an operating system, an application interface, a still image, or video content. As shown, the electronic display 18 is operably coupled to the processing core complex 12. In this way, the electronic display 18 can display a frame based at least in part on the image data generated by the processing core complex 12. Additionally or alternatively, the electronic display 18 can display a frame based at least in part on the image data received via the communication interface(s) 16 and / or the input structure 20.

[0056] As can be appreciated, the electronic device 10 can take several different forms. As shown in FIG. 2, the electronic device 10 can take the form of a portable watch 30. For purposes of illustration, the portable watch 30 may be any Apple Watch® model available from Apple. As shown, the portable watch 30 includes an enclosure 32 (e.g., a housing). In some embodiments, the enclosure 32 can protect internal components from physical damage and / or shield from electromagnetic interference (e.g., components within a residence). The strap 34 can enable the portable watch 30 to be worn on the arm or wrist. The electronic display 18 can display information regarding the operation of the portable watch 30. The input structure 20 can enable the user to activate or deactivate the portable watch 30, navigate the user interface to the home screen, navigate the user interface to an application screen that the user can configure, activate the voice recognition function, provide volume adjustment, and / or toggle between vibration mode and ringing mode. As shown, the input structure 20 may be accessed through an opening in the enclosure 32. In some embodiments, the input structure 20 may include, for example, an audio jack for connecting to an external device.

[0057] As shown in FIG. 3, the electronic device 10 can also take the form of a tablet device 40. For the purpose of illustration, the tablet device 40 may be any iPad (registered trademark) model available from Apple. Depending on the size of the tablet device 40, the tablet device 40 can function as a handheld device such as a mobile phone. The tablet device 40 includes an enclosure 42 through which the input structure 20 can protrude. In a particular embodiment, the input structure 20 may include a hardware keypad (not shown). The enclosure 42 can also surround the electronic display 18. The input structure 20 can enable a user to interact with the GUI of the tablet device 40. For example, the input structure 20 can enable a user to type Rich Communication Services (RCS) text messages, Short Message Service (SMS) text messages, or make a phone call. The speaker 44 can output received audio signals, and the microphone 46 can capture the user's voice. The tablet device 40 may also include a communication interface 16 that enables the tablet device 40 to connect via a wired connection to another electronic device.

[0058] FIG. 4 shows a computer 48 representing another form that the electronic device 10 can take. For the purpose of illustration, the computer 48 may be any Macbook (registered trademark) or iMac (registered trademark) model available from Apple. It should be understood that the electronic device 10 can also take the form of any other computer including a desktop computer. The computer 48 shown in FIG. 4 includes an electronic display 18 and an input structure 20 including a keyboard and a trackpad. The communication interface 16 of the computer 48 can include, for example, a Universal Service Bus (USB) connection.

[0059] In any case, as described above, communicating information by operating the electronic device 10 to display an image on its electronic display 18 generally consumes power. Further, as described above, the electronic device 10 often stores a finite amount of electrical energy. Thus, in order to promote improved power consumption efficiency, in some embodiments, the electronic device 10 reduces or eliminates the use of an external frame buffer when displaying an image, and thus reduces the power consumed by using the frame buffer when displaying an image, and / or may include an electronic display 18 that implements in-pixel memory as a method of reducing the bandwidth of the image data received by the electronic display 18. In some cases, an internal frame buffer (e.g., located within the electronic display 18 such as the display driver integrated circuit of the electronic display 18) may be used instead of, or in addition to, in-pixel memory technology. By implementing in-pixel memory or related technology, the electronic display 18 may be programmed using lower-bandwidth image data, further enabling power consumption savings. Further, an electronic display 18 that uses memory within the in-pixel or on-vehicle frame buffer can have a less complex design than an electronic display 18 without in-pixel memory or without an on-vehicle frame buffer. These advantages can be realized to retain the data transmitted to the memory by the pixels until new image data is written to the memory.

[0060] Similarly, portions of the image data can be programmed one at a time to a subset of the pixels associated with the electronic display 18. The image to be displayed is typically converted to numerical data or image data so that the image is interpretable by the components of the electronic display 18. In this way, the image data itself can be divided into small "pixel" portions, each of which can correspond to a pixel portion of the electronic display 18 or a pixel portion of the display panel corresponding to the electronic display 18. In some embodiments, the image data is represented by a combination of red, green, and blue light, and one pixel that appears to have a single color is actually three sub-pixels that each emit a portion of red, green, and blue light to create a single color. In this way, the numerical or image data that quantifies the red-green-blue light combination can correspond to digital luminance levels or gray levels that associate the luminance intensity (e.g., brightness) of the color of the image data with those particular sub-pixels. As is understood, the number of gray levels in an image typically depends on the number of bits used to represent the gray levels within a particular electronic display 18, and 2 N is represented, where N corresponds to the number of bits used to represent the gray levels. As an example, in an embodiment where the electronic display 18 uses 8 bits to represent the gray levels, the gray levels range from 0 in the case of black or no light to 255 in the case of maximum light and / or full light, for a total of 256 potential gray levels. Similarly, an electronic display 18 that uses 6 bits can use 64 gray levels to represent the luminance intensity of each sub-pixel.

[0061] By having memory within the pixels of the electronic display 18, it becomes possible to transmit image data to the sub-pixels associated with one color without the need to simultaneously transmit the image data to additional sub-pixels associated with a second color. For purposes of the present disclosure, sub-pixels are discussed with respect to red-green-blue color channels, where a color channel is a layer of image data that includes gray levels of a single color, and when combined with additional color channels, an image of a true or desired color is created, and the image data of the color channel corresponds to the image data transmitted to the sub-pixels of the color channel. However, it should be understood that any combination of color channels and / or sub-pixels may be used, such as blue-green-red, cyan-magenta-yellow, and / or cyan-magenta-yellow-black.

[0062] For purposes of illustration, a display system 50 associated with an electronic display 18 that does not implement in-pixel memory, and a display system 52 associated with an electronic display 18 that implements in-pixel memory, each of which may be implemented as an electronic device 10, are shown in FIG. 5. The display system 50 includes a timing controller 54 for receiving image data 56, a frame buffer 58, a row driver 60, a column driver 62 communicatively coupled to the timing controller 54 via a communication link 64, and a pixel array 66 that receives control signals from the column driver 62 and the row driver 60 to create an image on the electronic display 18. Further, the display system 52 includes a timing controller 54 for receiving image data 56, a row driver 60, a column driver 62 communicatively coupled to the timing controller 54 via a communication link 68, and a pixel array 69 that implements in-pixel memory technology and receives control signals from the column driver 62 and the row driver 60 to create an image on the electronic display 18.

[0063] In preparation for displaying an image, the display system 50 may receive image data 56 in a timing controller 54. The timing controller 54 can receive and use the image data 56 to determine a clock signal and / or a control signal, and control the supply of the image data 56 to a pixel array 66 via a column driver 62 and a line driver 60. Additionally or alternatively, in some embodiments, the image data 56 is received by a frame buffer 58.

[0064] In either case, the frame buffer 58 can function as an external storage device of the timing controller 54 for storing the image data 56 before outputting it to the column driver 62 and / or the line driver 60. The timing controller 54 may transmit the image data 56 from the frame buffer 58 to the column driver 62 and / or the line driver 60 via a communication link 64.

[0065] The communication link 64 is large enough (e.g., determined by the transmission bandwidth of the image data) to simultaneously transmit the image data 56 associated with all channels, for example, the image data 56 associated with the red channel, the green channel, and the blue channel, to the line driver 60 and / or the column driver 62. In this way, the communication link 64 simultaneously communicates the image data 56 associated with each pixel of the pixel arrays 66 of the red, green, and blue channels. The column driver 62 and the line driver 60 can transmit a control signal based on the image data 56 to the pixel array 66. In response to the control signal, the pixel array 66 emits light at various light intensities or luminances indicated, for example, by gray levels in the range of 0 to 255, to communicate an image.

[0066] However, the display system 52 receives the image data 56 in the timing controller 54. The timing controller 54 may use the image data 56 to determine a clock signal used to supply the image data 56 to the in-pixel memory pixel array 69. The timing controller 54 transmits the image data 56 to the row driver 60 and / or the column driver 62 to program the memory of the pixel array 69 using the digital data signal associated with the image data 56, and the digital data signal indicates the emission luminance / gray level of the pixels of the pixel array 69.

[0067] By implementing the in-pixel memory system and method, the display system 52 can reduce the bandwidth of the signal communicated via the communication link 68 when compared to the bandwidth of the signal communicated via the communication link 64, for example. In some examples, a single channel of the image data 56 can be transmitted via the communication link 64 (e.g., the red channel), as opposed to all channels being transmitted to the pixel array 66 (e.g., red-green-blue channels) simultaneously. In this way, the communication link 68 communicates the image data 56 associated with each pixel of the pixel array 66 of the red channel, the green channel, and the blue channel at different times, causing a reduction in the overall bandwidth of the signal used to communicate the image data 56. Reducing the overall bandwidth of the communication link 68 may lead to a reduction in the power consumption of the electronic device 10 because processing fewer data (e.g., a single channel of image data) at a given time may consume fewer processing resources than processing more data (e.g., three channels of image data).

[0068] To describe in detail the operation of the pixel array 69 having an in-pixel memory for displaying an image, an example of a display system 52A implementing the in-pixel memory having a timing controller 54 linked to a row driver 60 and / or a column driver 62 via a communication link 68 is shown in FIG. 6. The display system 52A includes a pixel array 69 of L rows × M columns, and each of one or more pixels 70 includes sub-pixels 72 corresponding to the color channels of the electronic display 18, for example, a red sub-pixel 72R, a green sub-pixel 72G, and a blue sub-pixel 72B. Each of the sub-pixels 72 includes a memory 78 that stores up to N bits and a driver (DRV) 80 that operates the sub-pixel 72 to emit light, as shown in FIG. 6. It should be understood that the illustrated display system 52A is merely intended to be exemplary and is not limiting. For example, in some embodiments, the pixel array 69 may include sub-pixels 72 that emit various amounts of cyan, yellow, and magenta light corresponding to cyan-yellow-magenta color channels instead of, or in addition to, red-green-blue color channels.

[0069] To describe the operation of the display system 52A, the timing controller 54 receives image data 56 corresponding to the next image to be displayed on the electronic display having the pixel array 69. The timing controller 54 generates a control signal and / or a clock signal in response to the image data 56, transmits a signal related to the operation row of the pixel 70 to the row driver 60, and transmits a signal related to the operation column of the pixel 70 to the column driver 62. The row driver 60 generates an emission control signal 82 and a write control signal 84 for each of the red-green-blue (RGB) channels in response to the signal associated with the image data 56 transmitted from the timing controller 54. The column driver 62 also generates image data 86 to be transmitted to each memory 78 of the pixel 70 in response to the signal associated with the image data 56 transmitted from the timing controller 54. The column driver 62 can generate the image data 86 in response to the signal associated with the image data 56 and / or the image data 56 in some embodiments, but in some embodiments, the image data 56 is transmitted as the image data 86 to each of the pixels 70. The column driver 62 generates data of size N bits for each sub-pixel 72 that matches the size of the memory 78, which is also of size N bits.

[0070] Generally, via the transmission of the emission control signal 82, the write control signal 84, and the image data 86, the pixel 70 is operated to emit light to create an image on the electronic display 18. Each of the pixels 70 receives each emission control signal 88 of the emission control signal 82 transmitted from the row driver 60, each of the three write control signals 90 of the write control signal 84, and each image data 92 regarding the channel of the pixel 70, for example, N bits of the image data of the red channel (image data - R) 92R, N bits of the image data of the green channel (image data - G) 92G, and N bits of the image data of the blue channel (image data - B) 92B. The write control signal 84 can enable the memory 78 of the pixel 70 to be programmed by the image data 86 transmitted by the column driver 62. Further, each emission control signal 88 of the emission control signal 82 can control whether the pixel 70 can emit light. The emission control signal 88 is transmitted to each pixel 70 in the column. The activated emission control signal 88 activates the driver 80 to transmit the digital image data 92 from the memory 78 to a light-emitting diode (LED) associated with the light-emitting portion of the pixel 70, for example, the sub-pixel 72 that uses an analog data signal to emit light from the pixel 70. In the illustrated embodiment, the pixels 70R1C1, R2C1, R3C1 to RLC1 in a column of the pixel 70, for example, the first column, receive the same emission control signal 88. The image data 92 transmitted to the pixel 70 causes the pixel 70 to emit light of an overall color and / or brightness.

[0071] The perceived color emitted from pixel 70 varies based on the light emitted from each of the three channels of pixel 70, i.e., the light emitted from each sub-pixel. For example, when each sub-pixel is operated to output a luminance of 0, pixel 70 will appear off. When the red sub-pixel 72R outputs at 100% luminance, the green sub-pixel 72G outputs at 50% luminance, and the blue sub-pixel 72B outputs at 0% luminance, the overall color perceived as orange can be emitted from pixel 70. Thus, the data is rendered to correspond to the individual color channels of pixel 70 and sent to each sub-pixel 72.

[0072] By implementing memory 78 within pixel 70, it becomes possible to program image data 92 into pixel 70 prior to the desired presentation time of the image. In some embodiments, an activated write control signal 90 can cause memory 78 to clear (or overwrite) the stored image data 92, and without activating the write control signal 90, memory 78 can hold the programmed image data 92. For example, to write new image data, the write control signal -R 90R can clear the memory 78 of the red sub-pixel 72R and activate the writing of new image data, the loading of image data -R 92R into memory 78. In this example, since the write control signal -B 90B is not activated, the memory 78 of the blue sub-pixel 72B is not cleared and continues to hold its programmed image data, image data -B 92B. Having memory 78 within pixel 70 enables memory 78 to have a portion of image data 86, rather than an entire frame of data, written at one time, thus improving the use of the available bandwidth for communicating the image data to be displayed on the electronic display 18. This is an improvement in display technology and processing technology, as well as an improvement in the power consumption used to process the image data, as previously described with reference to FIG. 5.

[0073] In the pixel array 69, the image data 86 is communicated from the column driver 62 to the sub-pixels 72 via a directly communicable coupling, for example, a communicable coupling 94. In some embodiments, a multiplexing circuit can be used to control the transmission of the image data 86 to the sub-pixels 72, and as a result, a multiplexing control signal is used by the column driver 62 to mediate the transmission of the image data 98 to the sub-pixels 72. For example, in such mediation, the red sub-pixel 72R may not receive the image data 98 at the same time as the blue sub-pixel 72B or the green sub-pixel 72G.

[0074] For detailed description, an exemplary embodiment of a display system 52B associated with an electronic display 18 implementing an in-pixel memory, including a timing controller 54 linked to a row driver 60 and a column driver 62 via a communication link 68, is shown in FIG. 7. A display system 52B similar to the display system 52A shown in FIG. 6 includes an L-by-M pixel array 69, and each of the one or more pixels 70 includes sub-pixels 72, for example, a red sub-pixel 72R, a green sub-pixel 72G, and a blue sub-pixel 72B. Each of the sub-pixels 72 includes a memory 78 that stores up to N bits and a driver (DRV) 80 that operates the sub-pixel 72 to emit light, as shown in FIG. 6. It should be understood that the illustrated display system 52B is merely intended to be exemplary and not limiting. The functions and / or descriptions of the display system 52 common to both FIGS. 6 and 7 rely on this specification.

[0075] In an exemplary embodiment of the display system 52B of FIG. 7, the pixel array 69 includes a multiplexing circuit 96 that receives image data 98 of size N bits from the column driver 62. The multiplexing circuit 96 responds to each of the multiplex control signals (MUX control signals) 100 of the multiplex control signal 101. The MUX control signal 100 can cause the multiplexing circuit 96 to output data to the sub-pixel 72 of the pixel 70. In this way, through the emission of the MUX control signal 100, the column driver 62 can operate to program, for example, the sub-pixel 72 (e.g., one color channel) of the pixel 70 via the communicable coupling 94. For the pixel array 69, various embodiments of the sub-pixel 72 circuit can be used.

[0076] An example of one embodiment of the sub-pixel 72 implementing the in-pixel memory technology includes a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, and a counter 105. The sub-pixel 72 receives various signals including the image data 98, the bitplane clock 106, the reset signal 108, the common voltage 110, the first reference voltage 112, the second reference voltage 114, and the data clock 116, which is shown in FIG. 8. It should be understood that the illustrated sub-pixel 72 is merely intended to be exemplary and not limiting. For example, although the memory 78 is illustrated as a 12-bit register, it may be any suitable memory circuit that stores any suitable number of bits.

[0077] The illustrated sub-pixel 72 can emit light according to a binary pulse width modulation light-emitting scheme. To explain the operation of the sub-pixel 72, image data 98 is transmitted, for example, from the column driver 62 to the memory 78. Additionally or alternatively, image data 92, image data 56, or any suitable image data may be transmitted to the memory 78 for storage. Upon receiving the image data 98, the memory 78 stores the image data 98 clocked in by the data clock 116. The image data 98 can be represented by binary data such that any given bit can be equal to zero "0" or one "1", where 0 corresponds to the logical low voltage value of the system and 1 corresponds to the logical high voltage value of the system. The memory 78 can output the image data 98 to the switch 104 bit by bit, for example, in order from the least significant bit to the most significant bit, according to a clock signal generated by a combination of the counter 105 and the bit plane clock 106.

[0078] As shown, the bit plane clock 106 has a time period that increases with time so as to correspond to the influence level of a particular bit within the image data 98. In this way, the least significant bit of the image data 98 may be associated with a shorter clock time period than the most significant bit of the image data 98.

[0079] When the memory 78 outputs the image data 98 at, for example, the rising edge of the bit plane clock 106, the image data 98 operates the switch 104 to open and close it. The 0 bit opens the switch 104 and does not cause the LED 103 to emit light, while the 1 bit closes the switch 104 and causes the LED 103 to emit light. The operation of the switch 104 occurs at various emission periods as a method of modulating the emission of light from the LED 103, and as the modulation changes, the perceived luminance of the sub-pixel 72 changes. Therefore, due to the relationship between the image data 98 output from the memory 78 and the switch 104, the image data 98 equal to "000000000000" may not cause the LED 103 to emit light, and the image data 98 equal to "101011000111" makes the LED 103 be perceived as brighter. The image data 98 equal to "101011000111" causes the sub-pixel 72 to operate so as to emit light in response to each logical high value "1", which is a value that enables the switch 104 to emit light, and thus can be perceived as brighter. The more times the switch 104 operates during the emission period, the more light is emitted over time, so the pixel is perceived as brighter (for example, light is emitted in response to "1" and not in response to "0"). In this way, the image data 98 can be derived from the desired gray level of the sub-pixel 72 without being an exact binary representation of the gray level. However, it should be noted that there may be a scenario where the desired gray level of the sub-pixel 72 is actually equal to the binary representation transmitted via the image data 98.

[0080] When switch 104 closes, an electrical connection is created between the common voltage 110 and the first reference voltage 112. This enables current from current source 102 to be sent through LED 103 and allows light to be emitted from sub-pixel 72. Thus, the emission period of sub-pixel 72 can be varied to control the perceived light emitted from sub-pixel 72, and the emission period corresponds to the bit arrangement (e.g., most significant bit, least significant bit) of the image data 98 stored in memory 78. The closer the bit of the image data 98 is to the most significant bit position, the longer the emission period corresponding to that bit of the image data 98. When counter 105 counts up to 11, counter 105 restarts and causes its clock interval to restart on bit plane clock 106, for example, corresponding to the next least significant bit after the last most significant bit emission period. Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the overall current value used to control the light emitted from LED 103. For example, the second reference voltage 114 can use a lower current value to cause light to be emitted from LED 103 or can increase the sensitivity of LED 103 to current changes to enable LED 103.

[0081] This emission scheme is called a binary pulse width modulation emission scheme for sub-pixel 72, because the image data 98 is binary data selected to modulate the light emission from sub-pixel 72 so as to change the perceived luminance of sub-pixel 72. Graph 118 shows the emission period of sub-pixel 72 caused by the binary pulse width modulation emission scheme. In the binary pulse width modulation emission scheme, sub-pixel 72 is operated to change the perceived luminance of the emitted light by changing the light emission period. As shown in graph 118, the image data 98 received by sub-pixel 72 is represented by 5-bit binary data. Thus, when the image data 98 is equal to 01111, sub-pixel 72 emits light corresponding to a first range 120 having a first emission period 124A of the least significant bit and subsequent emission periods 124B, 124C, and 124D of the bits. In this embodiment, the least significant bit of the image data 98 from memory 78 first operates switch 104, so the least significant bit temporally corresponds to the first emission period 124A. Thus, as can be seen from the absence of an emission period between the first emission period 124A and the emission period 124B, light emission temporarily stops during the transmission of the bit for operating switch 104. Further, when the image data 98 is equal to 11111, the emission period of sub-pixel 72 corresponds to a second range 122 equal to the first range 120 plus a last emission period 124E corresponding to the most significant bit (for example, because the most significant bit becomes valid as 1 here).

[0082] When following the binary pulse width modulation emission scheme, image data 98 having data of 01111 is perceived as not brighter than image data 98 having data of 11111, depending on how the light is perceived by the viewer of the electronic display 18. This is because the more emission periods occur during the entire emission cycle (e.g., as represented by all 1s in image data 98 of 11111), the brighter the light emitted from the sub-pixel 72 is perceived. Therefore, when the sub-pixel 72 emits light for the last emission period 124E in addition to the first range 120 (e.g., when the most significant bit of the image data 98 is 1), the sub-pixel 72 can be perceived as brighter on the electronic display 18 than the sub-pixel 72 that emits light only in the first range 120.

[0083] Another example of an embodiment of the sub-pixel 72, which includes a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, a counter 130, and a comparator 132, and the sub-pixel 72 receives various signals including image data 98, a gray level clock 134, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116, is shown in FIG. 9. It should be understood that the illustrated sub-pixel 72 is merely intended to be exemplary and not limiting. For example, although the memory 78 is illustrated as an 8-bit register, it may be any suitable memory circuit that stores any suitable number of bits.

[0084] The illustrated sub-pixel 72 having an in-pixel memory can emit light according to a single pulse-width emission scheme. To explain the operation of sub-pixel 72, image data 98 is transmitted from column driver 62 to memory 78, for example, for storage. Additionally or alternatively, image data 92, image data 56, or any suitable image data may be transmitted to memory 78 for storage. In some embodiments, image data 98 may be clocked into memory 78 by data clock 116, for example, at the rising edge of data clock 116. The image data 98 communicated to sub-pixel 72 may correspond to the desired gray level at which sub-pixel 72 emits light. Using the image data 98 stored in memory 78, comparator 132 determines whether the current number represented by counter 130 is less than or equal to the image data 98 in memory 78. In other words, counter 130 counts up to the number indicated by image data 98, and in response to the condition that the number represented by counter 130 is, for example, less than or equal to the number indicated by image data 98 being satisfied, comparator 132 outputs a control signal that closes switch 104 when the condition is met. If the condition is not met, comparator 132 does not output a control signal and opens switch 104. Additionally or alternatively, comparator 132 activates a deactivation control signal to open switch 104. For example, if memory 78 stores a binary sequence of 10110101 corresponding to the number 181, comparator 132 checks whether counter 130 has counted up to the number 181, and if counter 130 exceeds the number 181, comparator 132 sends a signal to open switch 104 to stop light emission.

[0085] When switch 104 closes, an electrical connection is created between common voltage 110 and first reference voltage 112. Thereby, current from current source 102 is sent through LED 103, and light is emitted from sub-pixel 72. Thus, the emission period of sub-pixel 72 can be changed to control the perceived light emitted from sub-pixel 72 by changing the number indicated by image data 98. Additionally or alternatively, in some embodiments, second reference voltage 114 is included to change the overall current value used to control the light emitted from LED 103. For example, second reference voltage 114 can use a lower current value to emit light from LED 103 or increase the sensitivity of LED 103 to current changes so that LED 103 can be enabled.

[0086] Counter 130 counts from 0 to 255 and increments based on gray level clock 134, for example, the rising edge of gray level clock 134. The period of gray level clock 134 represents the time difference between increments of the gray levels of electronic display 18, for example, the difference in emission between the emission of gray level 100 and the emission of gray level 101. In this way, counter 130 counts up to the number represented by image data 98 stored in memory 78 and then emits light for a time period corresponding to the desired gray level. Counter 130 may continue to count up to a maximum value, for example, 255, beyond the number represented by image data 98 stored in memory 78, or may restart counting at a minimum value, for example, 0. Thus, in some embodiments, the count range of counter 130 may be defined through the design of counter 130, for example, through some registers and / or logic components included in counter 130. Additional image data 98 can be stored in memory 78 until counter 130 restarts counting at 0, and a comparison of the next emission period of the gray level associated with the additional image data 98 can be started.

[0087] By following this emission scheme, sub-pixel 72 can follow a single pulse width modulation emission scheme. The representation of the light emission from sub-pixel 72 following the single pulse width modulation emission scheme is shown in graph 136. Graph 136 includes the actual emission period 138 and the total emission period 140. The total emission period 140 corresponds to the total length of the emission represented by the maximum number transmitted as image data 98, for example 255, and may correspond to the maximum perceived luminance of the light emitted from sub-pixel 72. The actual emission period 138 corresponds to the period during which sub-pixel 72 emitted light, for example according to a number less than the maximum value transmitted as image data 98 from counter 130. Counter 130 increments from 0 to 255 upon receiving the time represented by the total emission period 140, but comparator 132 enables light emission during the time represented by the actual emission period 138. In this way, sub-pixel 72 can emit light of various perceived luminances.

[0088] Another example of an embodiment of sub-pixel 72, which includes memory 78, driver 80, current source 102, LED 103, switch 104, accumulator 150, and adder 152, is shown in FIG. 10. It should be understood that the illustrated sub-pixel 72 is merely intended to be exemplary and not limiting. For example, memory 78 is illustrated as being able to store 8-bit image data 98, but may be any suitable memory circuit that stores any suitable number of bits.

[0089] The illustrated sub-pixel 72 having an in-pixel memory can emit light according to a pulse density modulation emission scheme. In the pulse density modulation emission scheme, each pulse has a constant emission and a constant emission period, but has a variable separation interval between pulses, and brighter light emitted from the sub-pixel 72 corresponds to a larger number of pulses during the same period. To explain the operation of the sub-pixel 72 of the pulse density modulation emission scheme, image data 98 is transmitted from, for example, the column driver 62 to the memory 78 for storage. Additionally or alternatively, image data 92, image data 56, or any suitable image data may be transmitted to the memory 78 for storage. The image data 98 transmitted to the sub-pixel 72 is generated based at least on the desired gray level at which the sub-pixel 72 emits light.

[0090] Upon receiving the image data 98, the memory 78 stores the image data 98 according to the data clock 116, and for example, loads the bits of the image data 98 bit by bit at each rising edge of the data clock 116. The memory 78 outputs the image data 98 that is added to the binary data stored in the accumulator 150. Although the accumulator 150 is shown as an 8-bit accumulator, it should be understood that any suitable accumulator or register may be used to temporarily store data. The adder 152 can perform a binary addition of the image data 98 and the binary data of the accumulator 150 in response to the emission clock 154, for example, the rising edge of the emission clock 154. The sum from the adder 152 is transmitted to be stored in the accumulator 150 for use with the next image data 98, and the carry bit is used to open and close the switch 104.

[0091] When switch 104 closes, an electrical connection is created between common voltage 110 and first reference voltage 112. Thereby, current from current source 102 is sent through LED 103, generally enabling light to be emitted from subpixel 72. In this way, the variable separation interval between the pulse generated by emission clock 154 and adder 152 that transmits a carry bit from addition can contribute to varying the light emission from subpixel 72. Thus, the interval separating the light emission pulses of subpixel 72 can be varied to control the light emitted from subpixel 72, and brighter light can be emitted in response to a smaller interval separating the pulses (e.g., a higher density of pulses corresponds to brighter perceived light emitted from LED 103). Additionally or alternatively, in some embodiments, second reference voltage 114 is included to change the overall current value used to control the light emitted from LED 103. For example, second reference voltage 114 can increase the sensitivity of LED 103 to current changes so as to cause LED 103 to emit light using a lower current value or enable LED 103.

[0092] Graph 156 shows the light emission pulses and variable separation intervals between pulses caused by a pulse density modulation light emission scheme. In a pulse density modulation light emission scheme, subpixel 72 emits pulses separated by non-emission intervals of different lengths to vary the total light emitted from subpixel 72. As shown in graph 156, image data 98 can cause subpixel to emit light emission pulse 158 and not emit light over the time period of non-emission interval 160. For example, light emission pulse 162 has a non-emission interval that is shorter than non-emission interval 160 separating each light emission pulse, and thus, LED 103 of subpixel 72 can emit light of light emission pulse 162 that is perceived as brighter than the light emitted from LED 103 by light emission pulse 158.

[0093] Therefore, in summary, by using the in-pixel memory technology, the timing controller 54 can program the display system 52 with a smaller portion of the image data 98 rather than programming the image data 98 simultaneously to all the sub-pixels 72. For purposes of illustration, for preparation to send the image data for storage in one or more memories 78, a timing diagram of signals transmitted within the display system 52 illustrates a red image data transmission period 174R, a green image data transmission period 174G, a blue image data transmission period 174B, one or more copy periods 176, and one or more active periods 178, which is shown in FIG. 11.

[0094] As shown in the figure, the column driver 62 may receive a signal to start copying red data to one or more memories 78 of one or more red sub-pixels 72R. Upon receiving the signal, the column driver 62 can enter a copy period 176 in preparation for transmitting the red data to the red sub-pixels 72R. During the copy period 176, the column driver 62 can prepare to enable a multiplexing circuit 96 associated with the pixels 70 of the display system 52, for example, via an internal circuit such as a row decoder. The column driver 62 or other suitable circuit can operate the multiplexing circuit 96 to enable programming of the memories 78 of the red sub-pixels 72R, and can operate the multiplexing circuit 96, for example, by activating and / or deactivating a multiplexing control signal 101, to not permit programming of the memories 78 of the blue sub-pixels 72B and the green sub-pixels 72G. In this way, the red image data may be transmitted and stored in the memories 78 corresponding to the red sub-pixels 72R. At the end of the copy period 176, the column driver 62 may transmit the red image data to the red sub-pixels 72R during a red image data transmission period 174R. The transmitted red image data is transmitted to each memory 78 of the red sub-pixels 72R that is programmed with the new red image data. After transmitting the red image data to the red sub-pixels 72R, the column driver 62 and the row decoder can repeat the described process for the green and blue image data, enabling selective programming of the various color channels associated with each pixel 70.

[0095] Generally, the sub-pixel 72 is operated to emit light by receiving one or more control signals from, for example, the column driver 62 and / or the row driver 60. The row driver 60 and the column driver 62 can control the operation of the sub-pixel 72 by using control signals for controlling components of the sub-pixel 72, such as the current drive of the sub-pixel 72. As described above, the column driver 62 can be responsible for transmitting at least the image data to the sub-pixel 72, and the row driver 60 can be responsible for one or more control signals for controlling the light emission to be transmitted to the sub-pixel 72. The sub-pixel 72 may include any suitable controllable element, such as a transistor, that responds to these control signals and the image data, and an example thereof is a metal-oxide semiconductor field-effect transistor (MOSFET). However, any other suitable type of controllable element can also be used, including thin-film transistors (TFTs), p-type and / or n-type MOSFETs, and other transistor types.

[0096] In some embodiments, the row driver 60 and / or the column driver 62 can perform an initialization process, a charging process, a programming process, and a light emission process to the sub-pixel 72 to prepare to display an image on the electronic display 18. By performing these processes, the row driver 60 and / or the column driver 62 of the electronic display 18 can initialize the sub-pixel 72 to be programmed, can charge a capacitor for programming, can program the sub-pixel 72 with a signal corresponding to a drive current designed to cause the sub-pixel 72 to emit light, and can enable the image data to control the light emission from the sub-pixel 72. In some embodiments, the current drive can be responsible for generating a drive current within the sub-pixel 72.

[0097] To assist in a detailed description of a sub-pixel circuit having a current drive, an embodiment of a sub-pixel 72 including an initialization transistor (MINI) 220, a drive transistor (MDR) 222, a selection transistor (MSEL) 224, a switching transistor (MS) 226, a reset transistor (MRST) 228, a light-emitting portion such as an LED 230, a capacitor 232, and an auto-zero transistor (MAZ) 234 is shown in FIG. 12. It should be understood that the illustrated sub-pixel 72 is intended to be illustrative and not limiting. For example, the row driver 60 and the column driver 62 are described herein as outputting control signals related to image data and displaying the next image on the electronic display 18, but it should be understood that any suitable components can be used to emit the control signals for displaying the next image. Further, the circuit shown in FIG. 12 is merely an example of a circuit implemented within the sub-pixel 72 and / or the pixel 70 and should not be construed as limiting. For example, a voltage drive circuit (e.g., voltage drive) may be used with the sub-pixel 72 instead of a current drive circuit (e.g., current drive).

[0098] During the initialization process, the row driver 60 can enable the reset control (CSreset) signal 235 and disable the auto zero control (CSauto.zero) signal 237. The CSreset signal 235 can be sent to MRST228. In response to receiving the CSreset signal 235, MRST228 can be activated to allow the discharge of residual signals from the sub-pixels 72 from the display of the first image. These residual signals can be discharged to a node coupled to a voltage reset (Vreset) signal 239 designed to facilitate the discharge of the residual signals (e.g., 0 volts), such as system ground or a system reference voltage. Further, the row driver 60 can enable the select control (CSselect) signal 241. The CSselect signal 241 can be sent to MSEL224. In response to receiving the CSselect signal 241, MSEL224 can be activated to allow the voltage data (Vdata) signal 242 to be sent to the node of the capacitor 232. To complete the initialization process, the row driver 60 can also enable the initialization control (CSinitialization) signal 243. The CSinitialization signal 243 can be sent to MINI220. In response to receiving the CSinitialization signal 243, MINI220 can be activated to allow the initialization of the capacitor 232 to occur. In this state, the capacitor 232 can be charged to a voltage corresponding to the voltage difference between the Vdata signal 242 and the initialization voltage (Vinitialization) signal 244. Thus, the voltage difference can be programmed by selecting different values for the Vdata signal 242 and the Vinitialization signal 244 based on the desired voltage level for initializing the capacitor 232 while protecting the sub-pixels 72 from receiving additional signals that could interfere with the initialization or cause unintended light emission from the LED 230. The row driver 60 can continue the initialization process until the row driver 60 disables the CSinitialization signal 243 to deactivate MINI220.

[0099] After the initialization process, the row driver 60 may perform a charging process while MINI220 and MRST228 are inactive. During the charging process, MAZ234 and MINI220 remain inactive, and MSEL224 remains activated. While MSEL224 is activated, the capacitor 232 is charged based on the Vdata signal 242 and the reference voltage (Vreference) signal 246. By charging the capacitor 232, it may be possible for drive current to be transmitted through MDR222 even while MSEL224 is inactive. In some embodiments, the capacitor 232 stores the voltage value of the Vdata signal 242 such that MDR222 remains active throughout the emission process, enabling the sub-pixel 72 to generate a constant drive current through the LED230 for emission. Thus, the drive current enables light emission from the LED230 while MS226 is active, so the sub-pixel 72 has a current drive.

[0100] During the programming process, the row driver 60 may enable the CSauto.zero signal 237 to cause activation of MAZ234. When MAZ234 is activated, an electrical coupling is formed between the node of the capacitor 232 and the source node of MS226 such that the voltage value of the source node of MS226 becomes equal to the voltage value of the gate voltage (Vg) 245 of MDR222. After a period sufficient to increase the voltage of the source node of MS226 to be equal to the voltage value of Vg245, the row driver 60 can invalidate the CSauto.zero signal 237 to deactivate MAZ234. In this state, the sub-pixel 72 is programmed with an electrical signal ready to be transmitted to the LED230 when MS226 is activated. That is, in this state, the sub-pixel 72 is ready to transmit a drive current generated through the programmed signal in response to the CSimage.data signal 247 that activates MS226.

[0101] When the programming process is completed, the row driver 60 can operate the sub-pixel 72 to execute a light-emitting process. During the light-emitting process, the sub-pixel 72 emits light according to, for example, the image data control (CSimage.data) signal 247 transmitted from the column driver 62 to MS226. The sub-pixel 72 can receive the CSimage.data signal 247 from any suitable component of the electronic device 10 that can generate and / or generate image data for display via the sub-pixel 72. MS226 activates, for example, the logical high bit of a voltage having a value sufficient to switch MS226 (e.g., a programmed voltage at the source node of MS226 and large enough to overcome the threshold voltage of MS226) in response to the activated CSimage.data signal 247. When MS226 is activated, the voltage stored at the source node of MS226 is transmitted as a drive current through the LED 230. If the drive current exceeds the threshold voltage of the LED 230, the threshold voltage of the LED represents a voltage value above which light is emitted from the LED, and thus the LED 230 can emit light at least partially based on the value of the drive current.

[0102] As will be appreciated, the CSimage.data signal 247 can be binary and / or digital data representing image data used to operate the sub-pixel 72 to emit light at a particular gray level to convey an image (e.g., a second image). As described above, the sub-pixel 72 can operate according to various light-emitting schemes, and thus the CSimage.data signal 247 transmitted to MS226 can vary between embodiments. However, across embodiments, the CSimage.data signal 247 is derived from the image to be displayed on the display. Further, the activation and / or deactivation of the CSimage.data signal 247 causes the LED 230 to emit light or not emit light at least partially, thus enabling the CSimage.data signal 247 to modulate the emission of light from the sub-pixel 72.

[0103] When the emission process is completed, the row driver 60 can disable the CSselect signal 241 and enable the CSreset signal 235, causing the deactivation of MSEL224 and the activation of MRST228. When MSEL224 is deactivated, the capacitor 232 no longer receives charge, and the residual signal from the emission process is discharged by the activation of MRST228, so the sub-pixel 72 can no longer operate to emit light.

[0104] The described sub-pixel 72 is regarded as a current drive pixel because the sub-pixel 72 has a primary current that drives the LED230 to emit light or not emit light. In response to various control signals that control the timing of light emission from the sub-pixel 72, a primary or drive current is transmitted via MS226. The described sub-pixel 72 circuit may have certain advantages including a way to control the light emission from the LED230 without further converting the digital output to an analog output. Further, by including the capacitor 232, it is possible to compensate for the change in the threshold voltage associated with the sub-pixel 72 from the substrate bias effect and the side effects associated with applying a voltage to the gates of some transistors.

[0105] A further improvement to the sub-pixel 72 can occur when a voltage drive is included in addition to the current drive structure of the sub-pixel 72 in FIG. 12. At the start of the emission process, the voltage drive is enabled for a certain period to provide amplification to the anode of the LED230, facilitating the initial emission of light and enabling light emission using a weaker drive current without amplifying the anode of the LED230. Since the LED230 can operate within the forward bias region, it is possible to drive the LED230 to emit light using a smaller drive current value, or the operating region of the LED230 is more sensitive to small changes in current due to the amplification provided by the voltage drive.

[0106] For illustration purposes, a second embodiment of sub-pixel 72 having a hybrid drive including current drive 270 and voltage drive 272 and having memory 78 is shown in FIG. 13. It should be understood that the illustrated sub-pixel 72 is intended to be exemplary and not limiting. For example, although current drive 270 and voltage drive 272 are shown as separate elements within sub-pixel 72, one or both of the drives may be included in the aforementioned driver 80.

[0107] Row driver 60 and / or column driver 62 can operate sub-pixel 72 to emit light by activating and / or deactivating control signals. Row driver 60 and / or column driver 62 use the control signals to execute various processes for causing sub-pixel 72 to emit light, including an initialization process, a charging process, a programming process, and a light-emitting process of sub-pixel 72, to enable the display of image data corresponding to the image to be displayed.

[0108] To assist in illustrating the interaction of the control signals emitted by row driver 60 and / or column driver 62 with sub-pixel 72 of FIG. 13, timing diagram 279 corresponding to the signals used for display including Vdata signal 242, CSinitialization signal 243, CSselect signal 241, CSauto.zero signal 237, CSimage.data signal 247, CSselect signal 280, and CSreset signal 235 is shown in FIG. 14. It is intended that the timing diagram be exemplary and not limiting. For example, it should be understood that the control signals shown in FIG. 14 may represent more or fewer control signals implemented within sub-pixel 72.

[0109] The above initialization process corresponds to time period 282. During time period 282, the row driver 60 can provide a high voltage to the Vdata signal 242, can enable the CSinitialization signal 243 during the duration of the initialization process, can enable the CSselect signal 241 during time period 284, can disable the CSauto.zero signal 237, can disable the CSreset signal 235, and can disable the CSselect signal 280.

[0110] Referring back to FIG. 13, the control signals output by the row driver 60 to execute the initialization process cause the activation and / or deactivation of various switching elements as described above. By implementing the control signals of FIG. 14 in the sub-pixel 72, MINI220 is activated in response to the enabled CSinitialization signal 243, MSEL224 is activated in response to the enabled CSselect signal 241, MAZ234 is deactivated in response to the disabled CSauto.zero signal 237, MRST228 is deactivated in response to the disabled CSreset signal 235, and the voltage drive switching element (MVD) 285 is deactivated in response to the disabled CSselect signal 280. This configuration enables the voltage value difference between the Vdata signal 242 and the Vinitialization signal 244 to charge the capacitor 232. The row driver 60 can continue the initialization process until the row driver 60 disables the CSinitialization signal 243, deactivates MINI220, and thus the initialization is completed.

[0111] Referring back to FIG. 14, timing diagram 279 shows that after the initialization process, row driver 60 disables the CSinitialization signal 243 and executes a charging process for sub-pixel 72. During the charging process, the Vdata signal 242, CSauto.zero signal 237, CSimage.data signal 247, CSselect signal 280, and CSreset signal 235 remain in their previous states. Timing diagram 279 shows the Vdata signal 242 at a high voltage level of the sub-pixel 72 circuit (DVDD), corresponding to a logical high value, for example, in the binary data of sub-pixel 72 and / or electronic device 10. In some embodiments, DVDD is equal to the voltage value of the Vreference signal 246.

[0112] Referring back to FIG. 13, the control signals output by row driver 60 activate and / or deactivate various switching elements to execute a charging process. When the CSinitialization signal 243 is deactivated and MINI220 is deactivated, capacitor 232 charges based on the Vdata signal 242 and Vreference signal 246. By charging capacitor 232, it may be possible to continue using current drive 270 during the light emission process even while MSEL224 is deactivated. In some embodiments, capacitor 232 holds the voltage value of the Vdata signal 242 after the charging process so that MDR222 can remain active throughout the light emission process, enabling current drive 270 to generate a constant drive current through LED 230 for light emission.

[0113] After a suitable set period for charging the capacitor 232, the row driver 60 can execute a programming process. Briefly referring to FIG. 14, to execute the programming process, the row driver 60 enables the CSauto.zero signal 237 during the time period 286 and holds the Vinitialization signal 243, Vdata signal 242, CSimage.data signal 247, CSselect signal 280, and CSreset signal 235 in their previous states. As shown, the row driver 60 also transmits a ground voltage (GND) as the Vdata signal 242 during the time period 288 of the programming process. GND may be equal to zero volts or any suitable ground reference voltage associated with the electronic display 18, electronic device 0, and / or sub-pixel 72.

[0114] Returning to FIG. 13, in response to the enabled CSauto.zero signal 237, MAZ234 is activated. When MAZ234 is activated, an electrical coupling is formed between the node of the capacitor 232 and the source node of MS226 such that the voltage value of the source node of MS226 becomes equal to the voltage value of Vg245. After the time period 286, the row driver 60 disables the CSauto.zero signal 237 and MAZ234 is deactivated. In this state, the sub-pixel 72 is programmed with an electrical signal ready to be transmitted to the LED230 when MS226 is activated. That is, in this state, the sub-pixel 72 is ready to transmit a drive current generated via the programmed signal in response to the CSimage.data signal 247 that enables MS226. When the source node of MS226 is programmed with the Vg245 voltage, the row driver 60 transmits a Vdata signal 242 equal to GND and, at the end of the time period 284, disables the CSselect signal 241 to deactivate MSEL224. At the completion of the programming process, the row driver 60 can activate and / or deactivate control signals to execute a light-emitting process.

[0115] Referring to FIG. 14, during the emission process, the row driver 60 may return the Vdata signal 242 to DVDD, may continue to invalidate the CSinitialization signal 243, may continue to invalidate the CSselect signal 241, may enable the CSimage.data signal 247 during the time period 290, may enable the CSselect signal 280 during the time period 292, and may continue to invalidate the CSreset signal 235. As shown, the CSselect signal 280 is enabled simultaneously with the CSimage.data signal 247, but is invalidated earlier than the CSimage.data signal 247. This is because the CSselect signal 280 acts to activate the switching element and provide amplification to the anode of the LED 230 of the sub-pixel 72.

[0116] Returning to FIG. 13 for illustration, the voltage drive switching element (MVD) 285 of the sub-pixel 72 is activated in response to the activation of the CSselect signal 280 and operates the voltage drive 272. In response to the activation of the MVD 285, the reference voltage (Vreference) signal 300 is transmitted to the anode of the LED 230 when the CSimage.data signal 247 activates the switching transistors (MS) 302 and MS226 for the first transmitted CSimage.data signal 247. Thereby, the Vreference signal 300 is transmitted at the anode of the LED 230 and activates or "amplifies" a smaller program value from the source of the MS226, causing the emission of light from the LED 230. The amplification can continue during the time period 292, and at the end of the time period 292, the row driver 60 invalidates the CSselect signal 280, causing the deactivation of the MVD 285 and the MS302.

[0117] Generally, the emission process can continue for a time period 290, and the amplification can last for a shorter period, for example, for a time period 292. During the emission process, the sub-pixel 72 is programmed to send a drive current through the LED 230 in response to the activation of the MS226. As described above, the memory 78 of the sub-pixel 72 stores digital data and outputs digital data. Through the described hybrid drive, the stored digital data is transmitted from the memory 78 as digital data that turns into a control signal that controls the emission of light from the sub-pixel 72 with little overhead and without increasing power consumption. At the end of the amplification, in some embodiments, the sub-pixel 72 can be reset by activating the CSreset signal 235 over a duration such as the time period 294. Thus, the light emitted from the LED 230 can follow various emission schemes, as previously described in FIGS. 8 to 10, to communicate the gray levels associated with the image, because the binary data output from the memory 78 acts to modulate the light emitted through the LED 230.

[0118] To show the effect of "amplification" on the anode voltage of the sub-pixel 72, a graph 348 is shown in FIG. 15 showing an exemplary CSimage.data signal 350, a voltage signal 352 corresponding to the voltage at the anode of the LED 230, and a current signal 354 corresponding to the current through the LED 230 for a sub-pixel 72 that does not implement the hybrid drive. It should be understood that the illustrated timing diagram is intended to be exemplary and not limiting.

[0119] In this simulation, as the CSimage.data signal 350, a binary pulse width modulation light emission scheme was tested by providing a wider binary pulse. The simulation results shown in graph 348 generally have two parts. The first part 356 can correspond to a slower light emission response time, and the second part 358 can correspond to a normal light emission response time. The light emission response time generally refers to the relative responsiveness of the LED 230 to the applied voltage. It is also worth noting that an LED such as the LED 230 operates to conduct based on the voltage difference between the anode and cathode of the LED. When the voltage difference between the anode and cathode is greater than the threshold voltage, the LED operates to emit light according to the value of the current transmitted through the LED. In graph 348, the current signal 354 may generally correspond to the light emission of the LED 230, and the closer the value of the current signal 354 is to the state of the CSimage.data signal 350, the better the light emission response time of the LED 230. In graph 348, the influence of the slow charge effect on the anode voltage of the LED 230 is obvious. As shown by the general alignment between the amplitude of the current signal 354 and the CSimage.data signal 350 during the first part 356 and the second part 358 and the lack of its general coupling during the first part 356, the current signal 354 seems to respond less to the state change of the CSimage.data signal 350 than the second part 358. Amplifying the anode at the start of the light emission period can reduce or eliminate the slow charge effect of the anode voltage.

[0120] Proceeding to FIG. 16 for comparison, FIG. 16 shows a graph 370 depicting an exemplary CSimage.data signal 350, a voltage signal 374 corresponding to the voltage at the anode of LED 230, and a current signal 376 corresponding to the current through LED 230 for sub-pixel 72 having a hybrid drive. It should be understood that the illustrated timing diagram is intended to be exemplary and not limiting. For example, although the CSimage.data signal 350 is shown to follow a binary pulse width modulation emission scheme, any suitable emission scheme may cause the same improvement in responsiveness as described below.

[0121] In this simulation, similar to graph 348, a binary pulse width modulation emission scheme was tested by providing a wider binary pulse as the CSimage.data signal 350. However, unlike graph 348, graph 370 shows that the current signal 376 responds to changes in the CSimage.data signal 350. This improved responsiveness is due at least in part to the addition of a voltage drive 272 to sub-pixel 72. The voltage drive 272 of the hybrid drive "amplifies" the anode of LED 230, such that a smaller change in the voltage at the anode of LED 230 can elicit the same and / or similar responsiveness of the second portion 358 of graph 348. Thus, graph 370 shows the benefits and improvements to display technology provided by implementing at least a hybrid drive for sub-pixel 72.

[0122] As described above, a display implementing in-pixel memory technology can implement various pixel circuit embodiments and various memory circuit embodiments to achieve the advantages described above in this disclosure. An exemplary embodiment is a memory circuit that supports a binary pulse width emission scheme, and digital data stored in the memory circuit is output to a driving circuit to control the emission of light from the pixel. As an advice, the binary pulse width emission scheme functions in cooperation with a clock signal, such as a bitplane clock, and assigns contribution weights to various portions of the digital data transmitted from the memory circuit. In some embodiments, the clock signal is used to clock a register to output the stored digital data from the memory circuit. However, in some embodiments, the system clock and / or the row driver 60 can control the emission duration through the length of time during which the emission activation signal is activated.

[0123] To help illustrate a memory circuit that facilitates the control of emission via an emission activation signal, a sub-pixel 72 including a memory circuit 400A, an analog driving circuit 402, and an emission circuit 404 is shown in FIG. 17. It should be understood that the sub-pixel 72 is intended to be illustrative and not limiting. For example, the memory circuit 400A is shown as storing 12-bit digital data, but any suitable memory circuit, such as a circuit storing digital data greater than or less than 12 bits, may be used.

[0124] Memory circuit 400A may include writeable transistors (MWR) 406, one or more inverter pairs 408, and transmission selection transistors (MSEL) 410. Memory circuit 400A receives and stores digital data (DATA) 412 from, for example, column driver 62. Before memory circuit 400A stores DATA 412, row driver 60 enables writeable control signal (write_en) 414 to activate MWR 406, enabling image data to be written to the memory (e.g., inverter pair 408), so that the memory can store the image data. When DATA 412 is received, inverter pair 408 stores the DATA 412 value. By using memory circuit 400A, parallel transmission of DATA 412 is enabled, such that in addition to bit-by-bit transmission where each bit of DATA 412 is stored one bit at a time, all bits of DATA 412 are stored in their respective inverter pairs 408 simultaneously, or in the same write cycle (e.g., when write_en signal 414 is active). MSEL 410 is activated in response to valid selection control signal (Sel) 415 transmitted by row driver 60, which operates to activate MSEL 410 of the memory bit for transmission to, for example, analog drive circuit 402. In this way, MSEL 410A may be activated at the same time as MSEL 410B is deactivated. Thus, memory circuit 400A is loaded with one or more DATA 412 bits before the light emission process begins, and DATA 412 is easily read bit by bit by activation of each MSEL 410.

[0125] At the start of the emission process, for example, in the emission process as described in FIG. 14, the row driver 60 can enable the precharge control signal (Precharge) 416 to initially enable emission, at least partially based on the activation of the light-emitting transistor (MEM) 419. The MEM 419 can be activated in response to the row driver 60, thereby enabling the emission control signal (Emit_en) 420. In some embodiments, the row driver 60 can enable the precharge signal 416 simultaneously with the Emit_en signal 420, such that the Vreference signal 246 is transmitted to the MS 226 before the activation of the MSEL 410, enabling the anode of the LED 230 to be precharged or amplified. After the precharge is completed, during the emission process, the Emit_en signal 420 can continue to be enabled by the row driver 60. On the other hand, the row driver 60 disables the precharge signal 416 after precharge, allowing the stored DATA 412 to at least partially control the activation of the MEM 419. Thus, the stored DATA 412 transmitted from the inverter pair 408 can activate the MEM 419 in response to the logical value of the stored value (e.g., "1" or "0"). Note that in some embodiments, the logical high value is equal to the Vreference signal 246 and the logical low value is equal to the Vreference signal 248.

[0126] When the stored DATA 412 is transmitted from the memory circuit 400A, the light-emitting circuit 404 receives the stored DATA 412 at the gate of the MS 226. The MS 226 becomes active in response to the stored DATA 412 value, allowing the current generated by the analog drive circuit 402 to be transmitted to the LED 230 to cause emission. Emission can continue as long as the stored DATA 412 is applied as the CSimage.data signal 247. Thus, following the initialization process, the charging process, the programming process, and the emission process, the light emitted from the sub-pixel 72 is generally described using FIGS. 12 to 14.

[0127] A further embodiment of the sub-pixel 72 having the memory circuit 400B and the analog drive circuit 442 including the light-emitting circuit 404 is shown in FIG. 18. It should be understood that the sub-pixel 72 is intended to be illustrative and not limiting. For example, although the memory circuit 400B is shown as storing 16-bit digital data, any suitable memory such as a circuit that stores digital data greater than or less than 16 bits may be used. Further, although the sub-pixel 72 is shown as having the LED 230 included in the light-emitting circuit 404, any suitable light-emitting circuit 404 can be combined with the described in-pixel memory technology.

[0128] The memory circuit 400B is shown as including one or more writable transistors (MWR) 406, one or more inverter pairs 408, and one or more select transistors (MSEL) 410. DATA412 is received, for example, from the column driver 62 into the memory circuit 400B. To transmit DATA412 into the memory circuit 400B, the row driver 60 can enable the write_en signal 406 and the inverse of the write_en signal (inverse write_en) 444 to enable bit-by-bit memory storage of DATA412. For example, the row driver 60 can enable storage of the last bit of DATA412 in the inverter pair 408B by activating MWR406D and / or MWR406C. Thus, the row driver 60 and the column driver 62 can operate to enable bit-by-bit transmission and storage of DATA412 into the memory circuit 400B.

[0129] When the inverter pair 408 stores DATA412, the memory circuit 400B stores the DATA412 value until the row driver 60 selects each bit for transmission. Before selecting each bit for transmission, the row driver 60 precharges the sense amplifier 440 by enabling the Precharge signal 416. By precharging the sense amplifier 440 and then the analog drive circuit 442, the responsiveness of the sub-pixel 72 to the transmitted electrical signal can be improved compared to a non-precharged sub-pixel 72. As described above, precharging the sub-pixel 72 can make the state transition easier and reduce the requirements on the circuit (e.g., by enhancing the responsiveness of the circuit).

[0130] When the precharge is complete, the row driver 60 selects the bits for transmission to the analog drive circuit 442 and causes light emission according to the stored DATA412. To transmit the bits to the analog drive circuit 442, the row driver can enable the Sel signal 415 to activate the MSEL410 corresponding to the inverter pair 408. For example, the row driver 60 can enable the Sel signal 415A to activate the MSEL410A and MSEL410B to transmit the DATA412 stored in the inverter pair 408A to the analog drive circuit 442 for transmission.

[0131] In some embodiments, DATA412 is sent via sense amplifier 440 before being sent to analog drive circuit 442. Sense amplifier 440 acts to sense the logical state of DATA412 and can amplify the sensed logical state to a logical state that can be interpreted (e.g., by increasing the signal amplitude). The interpretable logical state may be at least partially based on the threshold voltage of MS226 of analog drive circuit 442. For example, the bit sent to node 446 is caused by transmission via sense amplifier 440 and is output as having a higher voltage value at node 448 based at least partially on the voltage difference between Vreference signal 248 and Vreference signal 246, which represents any suitable voltage value common to the display system (e.g., display system 52).

[0132] After DATA412 is amplified, the amplified DATA412 is sent to analog drive circuit 442 as CSimage.data signal 247 to activate or deactivate MS226. For example, in some embodiments, MS226 deactivates in response to the sent logical high DATA412 (e.g., sent as CSimage.data signal 247) and activates in response to the sent logical low DATA412. Thus, the voltage value of the digital data sent as CSimage.data signal 247 corresponds to the bias voltage of MS226, or the voltage value that operates MS226 to change state. When MS226 is activated, a drive current generated by analog drive circuit 442 based at least partially on the voltage difference between Vreference signal 450 and Vreference signal 451 is sent via LED230, enabling subpixel 72 to emit light. Therefore, in the described method, DATA412 stored in memory circuit 400B can drive the light emission from pixel circuits (e.g., subpixels, pixels).

[0133] To summarize the operation of the embodiment of sub - pixel 72 of FIGS. 18 and 17, an example of a process 461 for controlling the operation of sub - pixel 72 coupled to memory circuit 400 is described in FIG. 19. Generally, process 461 includes a step of loading the current bit into the memory (block 462), a step of determining whether the current bit is the last bit loaded into the memory (block 464), in response to the current bit not being the last bit, a step of loading the next current bit into the memory (block 462), in response to the current bit being the last bit, a step of enabling the reading of the bit from the memory to the selection signal (block 466), a step of waiting for the bit to cause light emission within the pixel circuit (block 468), a step of determining whether the bit is the last bit read from the memory (block 471). In response to the bit being the last bit, the display cycle is completed (block 472), and in response to the bit not being the last bit, the next selection signal is enabled to read the next bit from the memory (block 466). In some embodiments, process 461 can be at least partially implemented by executing instructions stored on a tangible non - transitory computer - readable medium, such as one or more storage devices 14, using a processing circuit, such as processing core complex 12. Additionally or alternatively, process 461 can be at least partially implemented based on circuit connections formed within a display control circuit, such as row driver 60, column driver 62, and / or timing controller 54.

[0134] Thus, in some embodiments, row driver 60 may load the current bit into memory circuit 400 (block 462). As described above, row driver 60 selectively enables each switching element, such as MWR406B or MWR406D, to enable bit-by-bit loading of the current bit of DATA412 into memory circuit 400. Enabling MWR406 causes the bit corresponding to the current bit of DATA412 to be sent for storage, e.g., in inverter pair 408, and the value of the current bit is continuously inverted until the bit is selected for transmission.

[0135] After loading the current bit into memory, row driver 60 can determine whether the current bit is the last bit (block 464). The last bit represents the last bit of DATA412 (e.g., the last bit to be stored in memory circuit 400). Thus, checking whether the current bit is the last bit checks whether all of DATA412 has been sent from column driver 62 for storage. For example, various techniques for determining whether the current bit is the last bit may be implemented, including maintaining a separate count to track the current bit position relative to the final bit position.

[0136] In response to the current bit not being the last bit, row driver 60 may load the next current bit into memory circuit 400 (block 462). As described above, row driver 60 enables each successive switching element to enable bit-by-bit transmission of the next bit of DATA412 as the next current bit into memory circuit 400. Thus, process 461 repeats until the last bit of DATA412 is stored in memory circuit 400.

[0137] However, in response to the current bit being the last bit, row driver 60 can enable the select signal to transmit bits from the memory (block 466). When the current bit is the last bit, row driver 60 determines that the target data stored in memory circuit 400 has completed loading into the memory, and thus, at this point, row driver 60 transmits the stored DATA412 to analog drive circuit 442 bit-by-bit or on a bit-by-bit basis to cause sub-pixel 72 to emit light at a level, or brightness, corresponding to DATA412, in gray. In some embodiments, row driver 60 transmits the stored bits in order from the least significant bit to the most significant bit, although any suitable order of memory circuit 400 and display system 52 may be used. To cause the transmission, row driver 60 enables Sel signal 415 corresponding to the target bit from memory circuit 400 for reading. Enabling Sel signal 415 causes the target bit to be transmitted to sense amplifier 440 and / or analog drive circuit 442 to cause light emission.

[0138] Next, the row driver 60 can wait for the programmed time period of the bits transmitted from the memory and cause the sub-pixel 72 to emit light (block 468). While the row driver 60 is waiting, the bits stored in the inverter pair 408 are transmitted to the MS226. When the MS226 is activated, the analog drive circuit 442 enables a drive current to be transmitted through the LED230, causing light emission from the sub-pixel 72. As previously described with reference to FIG. 8, the bit plane clock 106 can act to modulate the width of the light emission so as to correspond to the gray level that is generally perceived as the importance of the bits from the memory. The row driver 60 can use the bit plane clock 106 to modulate the light emission from the sub-pixel 72, for example, by modulating the overall light emission of the sub-pixel 72 (e.g., by enabling the Emit_en signal 420) and / or by modulating the time period during which the bits are selected for transmission from the memory circuit 400 (e.g., by enabling the Sel signal 415 to activate the MSEL410 during the time period corresponding to the importance of the bits). In some embodiments, note that the row driver 60 does not wait and continues to determine whether the bit read from the memory circuit 400 was the last bit of the DATA412 in which the bit was stored.

[0139] After reading the bit, the row driver 60 may determine whether the bit was the last bit of the DATA412 in which the bit was stored (block 471). The row driver 60 determines whether the last bit has been read and / or transmitted to the analog drive circuit 442. The row driver 60 can manage this determination in various ways, for example, by maintaining a counter that increments in parallel with the activation of the Sel signal 415 to indicate when the row driver 60 has read the expected number of bits from the memory circuit 400.

[0140] If the bit is the last bit, the row driver 60 can complete the display cycle (block 427). The display cycle may include the entire process 461 such that when reaching block 427, the row driver 60 emits light at the gray level corresponding to DATA412. When the display cycle is complete, the row driver 60 may be ready to receive new DATA412 corresponding to the same or different gray levels for emission.

[0141] However, in response to the bit not being the last bit, the row driver 60 can enable the next select signal to permit reading of the next current bit from the memory (block 466). The row driver 60 can manage the enabling of the next select signal in various ways, such as maintaining a separate count to track the current transmission bit position relative to the final transmission bit position. In any case, the row driver 60 determines the Sel signal 415 to enable (e.g., the Sel signal 415 corresponding to the bit to be transmitted next from the memory circuit 400). When the row driver 60 determines which Sel signal 415 to enable, the row driver 60 enables the Sel signal 415, causing activation of the MSEL410 corresponding to the target bit for transmission. The row driver 60 can repeat the transmission of the bits of the stored DATA412 until the last bit is reached. When the last bit is reached, the row driver 60 may complete the emission cycle and prepare for the next emission cycle (block 427).

[0142] Regarding FIGS. 18 and 19, the described embodiments of the sub-pixel 72 have an analog driving circuit 442 with a global anode. Further embodiments of the sub-pixel 72 may have an analog driving circuit 442 with a global cathode.

[0143] A sub-pixel having a global cathode including a memory circuit 400C and an analog drive circuit 442 having a light-emitting circuit 404 are shown in FIG. 20. It should be understood that the sub-pixel 72 is intended to be illustrative and not limiting. For example, the memory circuit 400C is shown as storing 16-bit digital data through bit-by-bit transmission of data, but any suitable memory circuit such as a circuit that stores digital data more than or less than 16 bits and / or a circuit that enables parallel transmission of data may be used.

[0144] In the illustrated embodiment, the cathode of the LED 230 is coupled to a reference voltage (Vreference) signal 470, and the anode of the LED 230 is coupled to a reference voltage (Vreference) signal 473 via MS226A, MS226B, MS276, and MS278. As described above, after the DATA412 is stored in the memory circuit 400C, in some embodiments, after precharging the circuit via the Precharge signal 416, the row driver 60 enables the Emit_en signal 420 to cause light emission. When MEM480 and MEM482 are activated, the stored DATA412 bits are transmitted through the sense amplifier 440, and the amplified bits are transmitted to MEM480, while the inverted version of the stored DATA412 bits is transmitted to MEM482 without amplification. From the previous discussion, the inverted bits and the amplified bits are used as control signals for activating MS226A and 226B that act effectively like the CSimage.data signal 247. When MS226A and MS226B are activated, the analog drive circuit 442 generates a drive current based at least in part on the voltage difference between the Vreference signal 473 and the Vreference signal 470 and transmits it through the LED 230, resulting in light emission.

[0145] Similar to the embodiments of the global anode, the global cathode sub-pixel 72 can generate different gray levels by following the binary pulse width modulation method. The binary pulse width modulation method can partially use the bitplane clock to control the control signal output from the row driver 60. In this way, the Emit_en signal 420 may be enabled for a shorter time period for bits with lower importance in the perceived gray level (e.g., the least significant bit of DATA412), and may be enabled for a longer time period for bits with higher importance in the perceived gray level (e.g., the most significant bit of DATA412). In some embodiments, the Sel signal 415 can be modulated to cause the sub-pixel 72 to emit light according to different gray levels.

[0146] As described in FIG. 9, by using the in-pixel memory technology and the comparator, the row driver can generate a single pulse width modulation emission scheme. Accordingly, an embodiment of the sub-pixel 72 including the comparator 490, the memory circuit 491, and the memory circuit 492 is shown in FIG. 21. It should be understood that the sub-pixel 72 is intended to be illustrative and not limiting. For example, although the memory circuit 492 is shown as being coupled to the LED drive circuit and coupled to the light emitting circuit of the sub-pixel 72, the memory circuit 492 can be coupled to any suitable light emitting circuit and / or drive circuit.

[0147] In the illustrated sub-pixel 72, the DATA412 of size n bits is received by the memory circuit 491 according to the same process as described above. That is, in some embodiments where the row driver 60 operates to enable the write_en signal 494 and cause the transmission of DATA412 to the inverter pair 496, the row driver 60 operates in cooperation with the column driver 62 and enables the write_en signal 494 simultaneously to cause all the bits associated with DATA412 to be transmitted to the inverter pair 496 in parallel. Additionally or alternatively, the row driver 60 causes bit-by-bit transmission of the bits associated with DATA412, for example, by selectively enabling the write_en signal 494, and causes the transmission of the first bit of DATA412, for example, by selectively enabling the write_en signal 494A, to load the bit into the inverter pair 496A.

[0148] When DATA412 is stored in the inverter pair 496, the comparator 490 uses the stored DATA412 bits and the bits transmitted from the count circuit (e.g., counter 130) to perform a comparison between the two sets of bits. As an aid, in a single pulse width modulation emission scheme, a count circuit such as counter 130 increments to the maximum gray level at the rising edge of a clock signal such as gray level clock 134 and emission occurs from sub-pixel 72 until the count circuit counts to a number equal to and / or exceeding the number represented by the stored DATA412. In this way, the comparator 490 compresses all the bits of DATA412 into a single bit indicating whether all the DATA412 bits are the same as the count transmitted from the count circuit. Thus, the comparator 490 performs bitwise XNOR compression on a single bit having embodiments of memory circuit 491 and memory circuit 492, where the output from the comparator 490 is a logical low (e.g., "0") value unless all the bits match. If all the bits match, the comparator 490 outputs a logical high value. The output from the comparator 490 is stored in memory circuit 492 and the value is held in the inverter pair 498 until the row driver 60 enables the emet_en signal 420 and the stored output of the comparator 490 is released to the LED driver and emission circuit to drive emission as described above. Note that CNT_b[n:0] corresponds to the inverse of CNT[n:0] and is used to compare the inverted output from the inverter pair 496 with the inverted bits of CNT[n:0].

[0149] In some embodiments, it should be understood that the count circuit may decrease, and the comparator 490 can output a logic low value when all bits match, or any combination thereof. In other words, various valid embodiments can apply the described in-pixel memory technology. Further, an optional transistor 500 may be included in the sub-pixel 72 to provide a power-saving effect by precharging the common output (e.g., MTCH) node of the comparator 490, thereby making the circuit more responsive to changes in the output from the comparator 490.

[0150] To explain in detail the operation of the sub-pixel 72 shown in FIG. 21, a process 520 for operating the sub-pixel 72 having a comparator 490 and a memory circuit 491 is described in FIG. 22. Generally, the process 520 includes a step of initializing the memory circuit (block 522), a step of precharging the common output from the comparator (block 524), a step of incrementing the count of the count circuit (block 526), a step of causing light emission based on an auto-comparator decision stored in the memory circuit (block 528), and a step of determining whether the count circuit has reached a maximum count (block 530). In response to the count circuit reaching the maximum count, the next image is prepared (block 532), and in response to the count circuit not reaching the maximum count, the common output from the comparator is precharged (block 524). In some embodiments, the process 520 can be at least partially implemented by executing instructions stored in a tangible non-transitory computer-readable medium, such as one or more storage devices 14, using a processing circuit such as the processing core complex 12. Additionally or alternatively, the process 461 can be implemented at least partially based on circuit connections formed within a display control circuit, such as the row driver 60, the column driver 62, and / or the timing controller 54.

[0151] Thus, in some embodiments, the row driver 60 may initialize the memory circuit 492 (block 522). To initialize the memory circuit 492, the row driver 60 enables a control signal to force the nodes of the memory circuit 492 to a low voltage value. Taking FIG. 21 as an example, to initialize the memory circuit 492, the row driver may enable an S reset (S_rst) signal to reset the voltage value of the nodes of the memory circuit 492 (e.g., the S node). By initializing the nodes of the memory circuit 492, the light-emitting circuit emits light until the comparator outputs a logic high, and the light emission from the sub-pixel 72 can be stopped (e.g., in response to the gray level stored in the memory being reached by the count circuit). In other words, in the case of one or more sub-pixels 72 implementing the comparator 490, the sub-pixels 72 start emitting light simultaneously but can stop emitting light at different times, and the respective light emission durations correspond to the target gray levels of the respective sub-pixels 72.

[0152] After initializing the memory circuit 492, the row driver 60 can precharge the comparator 490 (block 524). To precharge the comparator 490, the row driver 60 enables a "Precharge" signal that operates in conjunction with the inverse emit_en signal 420 to cause a voltage (e.g., DVDD) to be sent to the comparator 490 (e.g., the MTCH node of the comparator 490) to amplify the circuit, thus enabling the sub-pixel 72 to respond to changes in the output from the comparator 490. Although a specific circuit is shown that operates to precharge the comparator 490 in response to the Precharge signal, it should be understood that various effective circuit configurations may be used to facilitate the precharge of the comparator 490.

[0153] After pre-charging the comparator 490, the row driver 60 can increment the count of the count circuit (block 526). The row driver 60 can increment the count circuit, for example, in response to a clock signal that measures the increment timing. After incrementing the count circuit, the sub-pixel 72 automatically determines whether the count of the count circuit is equal to or exceeds the value represented by DATA412 in which the count of the count circuit is stored. This is because the individual bits of the count and the individual bits of DATA412 are each sent to the comparator 490, and the comparator 490 outputs a logic high value when all bits match and a logic low value when even one bit does not match. The comparator 490 transmits for storage in the inverter pair 498 of the memory circuit 492, and this value is stored until the row driver 60 enables light emission via the activation of the emit_en signal 420.

[0154] After incrementing the count of the count circuit, the row driver 60 causes light emission based on the output from the decision of the comparator 490 stored in the memory circuit 492 (block 528). The row driver 60 causes light emission by enabling the emit_en signal 420. As described above, when emit_en420 is activated, the value is sent from the inverter pair 498 to the LED driver and the light emission circuit of the sub-pixel to cause light emission from, for example, the LED 230 or any suitable light emission circuit. The value transmitted from the memory circuit 492 can activate or deactivate the switching circuit of the LED driver and the light emission circuit responsible for causing light emission.

[0155] When the row driver 60 causes light emission based on the output from the comparator 490, the row driver can determine whether the count of the count circuit is the maximum count (block 530). The count circuit can count from a minimum value to a maximum value, for example, from 0 to 255. Therefore, when the maximum value or the maximum count is reached by the count circuit, the row driver 60 may execute specific processing steps to resume the count.

[0156] In response to not reaching the maximum count, row driver 60 resumes process 520 (block 524) by precharging the common output from comparator 490. Thus, from there, process 520 continues as described, causing row driver 60 to transmit another output from comparator 490 indicating whether the stored DATA412 is greater than the count represented by the count circuit.

[0157] However, in response to reaching the maximum count, row driver 60 prepares for the next image (block 532). To do this, row driver 60 prepares to receive new DATA412 corresponding to the target gray level of subpixel 72 used to communicate the next image. Different embodiments of subpixel 72 can be prepared in various ways. For example, the subpixel 72 of FIG. 21 can enable one or more write_en signals 494 to facilitate loading new DATA412 into memory circuit 491. In some embodiments, preparing for the next image includes resuming the count of the count circuit, whereby at block 526, the count circuit can be incremented to zero and the count resumed. In embodiments where the count circuit is a series of flip - flops coupled together to form a counter such as counter 130, it should be understood that there is no need to resume the count circuit to zero as it automatically resumes to zero based on the digital logic characteristics of the circuit.

[0158] Several emission schemes, such as binary pulse width modulation and single pulse width modulation, have been described with respect to the general operating theory, specific exemplary memory circuits, and specific exemplary pixel circuits that enable the use of an emission scheme to generate the perceived gray level of light emitted from a subpixel. Additional emission schemes can be implemented by using in - pixel memory technology, which is the binary pulse width modulation rearrangement emission scheme.

[0159] To aid illustration, a memory circuit 560 having one or more MWR406, one or more MSEL410, inverter pairs 408, inverter pair 498, and a switch / reset (SR) latch 562 is shown in FIG. 23. The row driver 60 operates in cooperation with the column driver 62 to enable a control signal that, for example, enables the column driver 62 to store DATA412 in the memory circuit 560, so that DATA412 can be provided to the memory circuit 560 for storage before being transmitted as the CSimage.data signal 247 to the light-emitting portion of the pixel.

[0160] Generally, the row driver 60 can operate the memory circuit 560 to emit multiple bits of data simultaneously from the same node in the memory, e.g., node BP_pre. In this way, the row driver 60 can modulate the emission time to rearrange the bit order represented by DATA412. For example, if DATA412 is equal to 0010, the row driver 60 can operate the memory circuit 560 to cause the emission to follow 1-0-0-0 such that the emission time of "1" occurs first and is not emitted after the time period corresponding to "00". This rearrangement can improve the appearance of visual artifacts on the electronic display 18 while allowing the same gray level as "0010" to be emitted from the sub-pixels.

[0161] To elaborate further on the rearrangement associated with the binary pulse width modulation rearrangement emission scheme, FIG. 24A shows a bit plane graph 580, FIG. 24B shows an error graph 588, FIG. 24C shows a bit plane graph 582, FIG. 24D shows an error graph 590, FIG. 24E shows a bit plane graph 584, FIG. 24F shows an error graph 592, FIG. 24G shows a bit plane graph 586, FIG. 24H shows an error graph 594, and FIG. 24 as a whole shows the effect of the rearrangement on the overall error. FIGS. 24A - 24H represent the simulated performance of an electronic display 18 implementing a binary pulse width modulation emission scheme with and without rearrangement of a 6-bit binary number representing the target gray level of a sub-pixel and / or pixel.

[0162] The bitplane graph 580 shows the original sequence of a binary pulse width modulation emission scheme without rearrangement of the gray levels represented by 6 bits. All bitplane graphs 580, 582, 584, and 586 have bright portions 595 corresponding to emission and dark portions 596 corresponding to no emission. The bitplane graph 580 is caused by the row driver 60 that operates the subpixel 72 to emit light via binary pulse width modulation (e.g., the LED 230 is driven to emit light in response to the binary representation of at least the most significant bit such that 0101 emits light after 1-0-1-0 without rearrangement). Each rectangle of the bitplane graph indicates the relative importance of a particular bit at a particular position with respect to the bitplane used to cause a particular gray level in the range from the minimum gray level 598 (corresponding to all dark portions 596 of all bitplane values) to the maximum gray level 599 (corresponding to all bright portions 595 for all bitplane values). For example, the block 597 representing the most significant bit of the bitplane graph 580 is logically high for gray levels from 32 to 64 and logically low for gray levels from 0 to 32. This is consistent with the 6-bit binary representation of their decimal values. Further, all bitplanes are logically low and the gray level is 0, and all are logically high at a gray level of 64. These binary states correspond to the numerical representation of the gray level and are expected to have all bitplanes logically low or 000000 to make the gray level 0. Thus, the bitplane graph can visually represent the relative importance of the bits representing the gray level (e.g., in the bitplane graph 580, the state of the 6th bit changes the gray level value more dramatically than the 1st or least significant bit).

[0163] When sub-pixel 72 is operated to emit light according to a binary pulse width modulation emission scheme without rearrangement, as shown in bitplane graph 580 and error graph 588, the total error count is high (e.g., 322). The errors appear on the electronic screen of electronic display 18 as, for example, dynamic false contours, color breakdown, and / or flicker of light emitted from one or more pixels, so it may be desirable to reduce the total error count by rearrangement.

[0164] As seen in bitplane graph 582 and bitplane graph 584, when rearrangement occurs and the bitplane pattern tends to look like the ideal bitplane shown in bitplane graph 586 with the most significant bit emitted first so that the gray levels of the bitplane graph are generated, further, as shown in error graph 588, error graph 590, error graph 592, and error graph 594, the error decreases as the rearrangement occurs. The perceived image quality can be improved by reducing the error count by bitplane rearrangement. The ideal case (e.g., bitplane graph 586) shows how bitplane graph 586 gradually changes as the gray level increases and how the total error tends to reach some total states represented by the bitplane as the number of rearrangements increases (e.g., 6 bits correspond to a total of 64 states according to the following relationship: number of states = 2 n where n is the number of bits).

[0165] Returning to FIG. 23 to explain in detail how row driver 60 operates memory circuit 560 to execute a binary pulse width modulation rearrangement emission scheme, row driver 60 enables and / or disables control signals to adjust the transmission of rearranged DATA412 from memory circuit 560. For example, row driver 60 can selectively enable and / or disable Sel signal 415 to transmit each bit from inverter pair 408. In some embodiments, row driver 60 can selectively enable and / or disable Sel signal 415 in response to bit plane clock 106 that defines the emission period of the bit positions of DATA412.

[0166] In the case of high-level and ideal rearrangement, row driver 60 can operate memory circuit 560 to transmit DATA412 as CSimage.data signal 247 in order from the most significant bit to the least significant bit, except when the bit of DATA412 is logically low, to cause emission from subpixel 72. When the DATA412 bit is logically low, row driver 60 effectively operates memory circuit 560 to skip the logically low emission period and emit light according to the next logically high emission period. When all logically high bits represented by DATA412 are transmitted, row driver 60 is paused for a duration equal to the total duration of logically low emission periods, or in some embodiments, proceeds to process new DATA412 for emission. For example, referring to emission rearrangement example 600, when DATA412 is equal to 1111, the CSimage.data signal 247 is transmitted from memory circuit 560 as "1111" with the same total emission period as "1111", while when DATA412 is equal to "0011", the CSimage.data signal 247 transmitted from memory circuit 560 is equal to "1100", each bit having the same emission period as "0011", and when DATA412 is equal to "0100", the data is recorded as "1000" for transmission as CSimage.data signal 247. Finally, a single pulse width of emission is generated from data corresponding to the binary pulse width modulation emission scheme.

[0167] During the rearrangement, the row driver 60 can operate the memory circuit 560 either by discharging the bits or by ignoring the bits if the stored bits in the memory are zero. The row driver 60 can operate in several different operation modes based on the number of rearrangements performed by the row driver 60. For example, for one rearrangement, the row driver 60 may have two operation modes, and for three rearrangements, the row driver 60 may have eight operation modes.

[0168] The row driver 60 can determine which operation mode to operate in based at least in part on a comparison of the current emission time and the quadrant time. The row driver 60 can compare the current time with a predetermined time frame that defines the operation mode (for example, the first operation mode corresponds to the length of the first emission). These different operation modes can define how the row driver 60 prioritizes the image data to cause emission. For example, in one rearrangement example, the row driver 60 in the first operation mode can permit emission according to the bit plane if the first most significant bit is equal to the binary state "0" (for example, the bit plane means how the pixel operates to emit light in response to the binary state of the image data used to operate the switch 104), but if the first most significant bit is equal to the binary state "1", the row driver 60 can enable emission regardless of the emission defined by the bit plane and cause a rearrangement of the bit plane.

[0169] For each operation mode, regardless of the number of permutations, the row driver 60 may perform similar control operations. The row driver 60 for each operation mode operates to iterate through each bit of DATA 412 starting from the least significant bit (e.g., DATA[0] 412A) and proceeds to the bit before the most significant bit corresponding to the number of permutations (e.g., DATA[n-1] 412 for one permutation, DATA[n-2] 412 for two permutations). For each iteration, starting with DATA[0], the row driver 60 resets the S node, precharges the memory circuit 560, enables the Sel signal 415B to permit transmission to the SR latch 562 of the DATA[n] 412B bit, and enables the Sel signal 415 corresponding to the current iteration of the least significant bit such that either the most significant bit or the current iteration of the least significant bit is transmitted as the CSimage.data signal 247.

[0170] The row driver 60 can operate the memory circuit 560 in different ways based on the operation mode. For example, when the row driver 60 operates in the first operation mode, the row driver 60 further precharges the memory circuit 560 between enabling the Sel signal 415B to permit transmission to the SR latch 562 of the DATA[n] 412B bit and enabling the Sel signal 415 corresponding to the current iteration of the least significant bit. Additionally or alternatively, in operation modes other than the first operation mode, the row driver enables the Sel signal 415B and enables other Sel signals 415 corresponding to the number of most significant bits equal to the number of permutations (e.g., for two permutations, the Sel signals 415 for DATA[n] 412B and DATA[n-1] 412, for three permutations, the Sel signals 415 corresponding to DATA[n] 412B, DATA[n-1] 412, and DATA[n-2] 412), and terminates by enabling at least the Sel signal 415 corresponding to the current iteration of the least significant bit (e.g., data[0] 412A for the first iteration, DATA[1] 412 for the second iteration, data[2] 412 for the third iteration).

[0171] Therefore, in the example of two rearrangements, the row driver 60 can operate in four different operating modes for the memory DATA412 having 6 bits. In the first operating mode (corresponding to, for example, the first quarter of the gray level values between zero and the gray level threshold 16), the row driver 60 resets the S node, precharges it (for example, enables the Precharge signal 416), enables Sel[6]415, enables the SET signal 602, precharges it, enables Sel[5]415, enables the SET signal 602, precharges it, and in addition to the SET signal for each bit of DATA412, enables Sel[n]415 (for example, in the case of the first iteration, n = 0 and Sel[0]415A is enabled), and the value of n can be incremented from zero for each iteration until DATA[4]412 is reached. In the second operating mode (corresponding to, for example, the second quarter of the gray level values between the gray level threshold 16 and twice the gray level threshold 32), the row driver 60 resets the S node, precharges it, enables Sel[6]415B, enables the SET signal 602, precharges it, enables Sel[5]415, and in addition to the SET signal for each bit of DATA412, enables Sel[n]415, and the value of n is incremented from zero for each iteration until DATA[4]412 is reached. In the third operating mode (corresponding to, for example, the third quarter of the gray level values between twice the gray level threshold 32 and three times the gray level threshold 48), the row driver 60 resets the S node, precharges it, enables Sel[6]415B, enables Sel[5]415, enables the SET signal 602, precharges it, enables Sel[6]415B, and in addition to the SET signal for each bit of DATA412, enables Sel[n]415, and the value of n is incremented from zero for each iteration until DATA[4]412 is reached.In the fourth operation mode (e.g., corresponding to the fourth quarter of the gray level values between 48 which is three times the gray level threshold and 64 which is four times the gray level threshold), the row driver 60 resets the S node, pre-charges it, enables Sel[6]415B, enables Sel[5]415, and in addition to the SET signal for each bit of DATA412, enables Sel[n]415 and increments the value of n from zero for each iteration until it reaches DATA[4]412.

[0172] In other words, FIG. 25 includes a bit plane graph 604 representing a binary pulse width modulation light emission scheme with two permutations implemented in three color channels. As shown, the bit plane graph 582 corresponding to the two permutations is represented over time in the bit plane graph 604 in the three color channels of one pixel 70. The row driver 60 can take the timing of light emission with respect to the quadrants, and in the case of two permutations, one quadrant 606 can approximately correspond to one quarter of the light emission time (e.g., 1 / 2 n, where n is equal to the number of permutations. These quadrants 606 may be parallel to the aforementioned operating modes. As time increases, the electronic display 18 can change the emission priority. In other words, higher emission priority may be given to the two most significant bits of the image data of a specific pixel 70 during emission than to other bits. In some embodiments, the electronic display 18 may manage the emission based on a comparison between the most significant bits and the value represented by a counter, increasing from the binary state "00" to the binary state "11" on the edge of the clock signal (e.g., rising edge or falling edge) (for example, one period of the clock signal corresponds to the duration of one quadrant). Thus, in these embodiments, when the two most significant bits (MSB) are equal to the binary state "00", for the first quadrant 606A, with respect to the sub-pixel 72 of the pixel 70, the sub-pixel 72 may emit light according to the bit plane 608 (e.g., according to the binary data stored in the memory 78 represented thereby), provided that when the two most significant bits are equal to the binary states "11", "01", and / or "10", the sub-pixel emits light only for the duration of the emission period of the channel of the first quadrant 606, generally summarized by the output logic outline 610 (for example, the first color channel corresponds to the time duration 609).

[0173] To summarize the other three quadrants, while sub-pixel 72 is operating in the second quadrant 606B, if the two most significant bits are equal to the binary state "01", it emits light according to bitplane 608; if the two most significant bits are equal to the binary states "10" and / or "11", it emits light; if the two most significant bits are equal to the binary state "00", it does not emit light. While operating in the third quadrant 606C, sub-pixel 72 emits light according to bitplane 608 when the most significant bit is equal to the binary state "10", emits light when the two most significant bits are equal to "11", and does not emit light when the two most significant bits are equal to "00" and / or "01". While operating in the fourth quadrant 606D, sub-pixel 72 emits light according to bitplane 608 when the two most significant bits are equal to the binary state "11", and does not emit light when the two most significant bits are equal to "00", "01", and / or "10". Thus, in this way, sub-pixel 72 is operated to rearrange the light emissions corresponding to the two most significant bits, such that the light emissions of the two most significant bits occur before the light emissions by bitplane 608.

[0174] To help provide content, FIG. 26 shows a timing diagram of a binary pulse width modulation light emission scheme with two rearrangements implemented in three color channels. This timing diagram shows the relationship between the loading of digital data into memory 78, which occurs substantially simultaneously with other operations performed by row driver 60. For example, the loading of data for the most significant bit of the green channel occurs at the time 612 of light emission of the least significant bit of the red channel. As described for the fourth quadrant 606D, comparing FIG. 26 with FIG. 25, row driver 60 enables sub-pixel 72 to emit light according to a bitplane represented by data stored in memory 78 and transmitted from memory 78. As shown in the timing diagram, the total light emission period for all three color channels is approximately equal to three times the channel-specific light emission period.

[0175] An exemplary embodiment of a pixel operated by a row driver 60 according to a binary pulse width modulation rearrangement emission scheme, including a memory circuit 560, MWR 406, MSEL 410, inverter pair 408, inverter pair 498, and an SR latch 562 coupled to an analog drive circuit 561, is shown in FIG. 27. This figure is illustrative and not limiting, for example, various pixel circuits and analog drive circuits can be used in combination with the memory circuit 560 and in-pixel memory technology. FIG. 27 shows an example of a memory circuit 560 applied to a digital micromirror display (DMD).

[0176] Generally, the illustrated memory circuit 560 operates to receive DATA412 corresponding to the target gray level of the color channel of pixel 70 corresponding to the memory circuit 560. As shown, the memory circuit 560 includes memories of different color groups for each color channel. In this embodiment, pixel 70 has a memory circuit for each color channel instead of sub-pixels 72 specific to each color channel (e.g., R - G - B). The row driver 60 can operate the color channels by enabling the color group (CG) signal 564. When the CG transistor (MCG) 565 is activated, the stored DATA412 is transmitted towards the analog drive circuit 561. The row driver 60 can allow one color channel to be transmitted at a time. Thus, the illustrated memory circuit 560 facilitates the color sequential output from individual memory circuits to a shared output circuit coupled to the DMD electrodes.

[0177] The row driver 60 can operate the illustrated memory circuit 560 in the same manner as the memory circuit 560 of FIG. 23. Thus, in the two rearrangement examples, the row driver 60 can operate in four different operation modes, and the operation modes are selected based on the gray level value of DATA412. After writing DATA412 to the inverter pair 408, the row driver 60 operates the memory circuit 560 to transmit the stored DATA412 to the SR latch 562 one bit at a time and drive the DMD electrodes via the analog drive circuit 561. By driving the memory circuit 560 in different operation modes, the row driver 60 can selectively enable and / or disable the CG signal 564 (for example, 564B enables transmitting red data corresponding to bit plane 7), so as to rearrange DATA412 to generate a single pulse width modulation signal from the binary pulse width modulation emission data.

[0178] For example, as described above, for the first operation mode (corresponding to a gray level between zero and the gray level threshold), the row driver 60 can reset the S node, precharge it, enable Sel[n]415B, enable the SET signal 602, precharge it, enable Sel[n - 1]415, enable the SET signal 602, precharge it, and enable Sel[0]415A. The row driver can repeat the first operation mode for each bit of DATA412 and increment from the first bit DATA[0]412A until reaching DATA[n - 2] (for example, 2 corresponds to the number of rearrangements). The row driver 60 can operate as described for FIG. 23 while in the second, third, and fourth operation modes.

[0179] Similar to FIG. 27, an exemplary embodiment of a pixel 650 operated by a row driver 60 and following a single pulse width modulation emission scheme, including a memory circuit 654, a color channel selection transistor 656, an inverter pair 498, an analog drive circuit 561, and a comparator 490 electrically coupled to a light emitting circuit (not shown), is shown in FIG. 28. This figure is meant to be an example and not limiting, for example, any suitable pixel circuit can be used in combination with a memory circuit and in-pixel memory technologies, such as any combination of additional and / or alternative embodiments of suitable switching elements (e.g., the MOSFET shown). FIG. 28 is included to show an example of a pixel 650 applied to a liquid crystal display (LCD), and the operation of the memory circuit 654 and comparator 490 can generally follow the process shown and described in FIG. 22.

[0180] Generally, pixel 650 receives DATA412 during the data writing process managed by row driver 60, and when write_en signal 414 becomes active, it permits writing the DATA412 bits to a memory, for example, inverter pair 408. During the data writing process, pixel 650 receives gray level digital data of red channel (DATA) 412R, gray level digital data of green channel (DATA) 412G, and gray level digital data of blue channel (DATA) 412B, and pixel 650 receives DATA412 in serial data transmission and / or parallel data transmission to respective ones of memory circuit 654. When DATA412 is written to the memory of pixel 650, comparator 490 performs an automatic comparison between DATA412 from the memory and the count transmitted from a count circuit such as counter 130 and / or any suitable counting method. Using the same method as described for comparator 490 in FIG. 21, comparator 490 transmits a "1" if DATA412 and the count 658 from the count circuit are the same (e.g., all bits match), and transmits a "0" if they are not the same (e.g., one or more bits do not match). Row driver 60 transmits CG signal 564 to respective transistors of color channel selection transistors 656 to enable a color channel for color sequential emission, for example, any one of red, green, or blue color channels for emitting light through a shared output stage. When row driver 60 enables transmission from the color channel, the MTCH bit is transmitted to memory circuit 492 for storage. Row driver 60 can enable the EMIT signal to enable light emission according to the stored MTCH bit as described above. Additionally or alternatively, row driver 60 can enable the GHOST signal that at least partially does not generate light emission regardless of the MTCH bit stored in memory circuit 492. To emit light, row driver 60 enables the EMIT signal and causes the stored MTCH bit to be transmitted to analog drive circuit 561 coupled to a high reference voltage and a low reference voltage.The stored MTCH bits are sent to the analog drive circuit 561 to activate and / or deactivate the MS566 coupled to the LC electrode in response to a reference voltage (e.g., MS566A, MS566B). The reference voltage is shown as 5[V] and VSS, but may be any suitable voltage used to drive the LC electrode when activating the MS566.

[0181] According to the above structure, the pixel 650 can be operated to emit light according to a single pulse width modulation light emission scheme. Different embodiments can be operated by the row driver 60 to emit light according to different emission schemes. For example, the color channels of the pixel 650 may be operated according to a binary pulse width modulation light emission scheme when the digital data transmitted to the pixel 650 changes and the comparator 490 is removed.

[0182] As discussed throughout this disclosure, it should be understood that in-pixel memory technology is effective for various embodiments and display technologies. It should also be understood that for each reference voltage described or disclosed in the drawings, additional or alternative reference voltages may be used. Additionally or alternatively, although described as reducing or eliminating the dependence when using a frame buffer, it should be noted that in some embodiments, in-pixel memory technology may be used in parallel with the frame buffer. Furthermore, although the memory circuit is described as storing 6 bits, 12 bits, 8 bits, and / or 16 bits, it should be understood that any suitable memory structure can be used to store any suitable number of bits.

[0183] As briefly described with reference to FIG. 21, in contrast to, or in addition to, including the memory 78 within the sub-pixel 72 itself, minor adjustments to the in-pixel memory technology can generally be applied to enable the memory 78 to be moved to a smart buffer. FIG. 29 generally illustrates this in an in-pixel memory architecture electronic display 700 and a smart buffer architecture electronic display 702. The in-pixel memory architecture electronic display 700 includes a memory 78 within each sub-pixel 72 located within the active area 704 of the electronic display 18, as shown, where the active area 704 includes all of the light-emitting components of the electronic display and a communicatively coupled connection to support data transmission to the light-emitting components. In the in-pixel memory architecture electronic display 700, digital data is transmitted from the memory 708 to each respective sub-pixel 72 for localized buffering within the memory 78. In some embodiments, the digital data is transmitted from the memory 708 to the source area 710 before being transmitted to the memory 78 for localized buffering (e.g., buffering within the sub-pixel 72). However, a memory substantially similar to the memory 78 may be included in the smart buffer 712 of the smart buffer architecture electronic display 702, still eliminating or at least reducing the dependence on the frame buffer, while further enabling the removal of the memory 78 from the active area 704. By moving the memory 78 to the smart buffer 712, the row driver 60 can operate the input latch 714 and the output latch 716 to arbitrate the light emission from each sub-pixel 72 via an analog output circuit such as the driver 80. Here, the smart buffer 712 may represent any suitable buffer memory that is within the integrated circuit of the electronic display 18 but is disposed outside of the active area of the electronic display 18.

[0184] FIG. 30 shows an example of a smart buffer embodiment of a memory 78 circuit including a memory circuit 750, a comparator 752, a memory circuit 754, and an output inverter 756. This circuit functions in the same manner as the memory circuit shown in FIG. 21. The smart buffer of FIG. 30 receives digital data in response to a writable (write_en) control signal 757 that enables writing of the digital data to the memory circuit 750 (e.g., an inverter pair). Thus, the general operation of the memory circuit 754 and the comparator 752 can generally follow the process shown and described in FIG. 22. The smart buffer of FIG. 30 may have a memory 78 circuit for each sub-pixel 72 of the active area 704. The digital data value may be stored in the memory circuit 750 until a new value of the digital data is written to the smart buffer of a particular sub-pixel 72.

[0185] When digital data is sent to the memory circuit 750, the comparator 752 determines whether all bits of the digital data match the output (CNT / CNT_b) from the count circuit. Similar to the embodiments described above, the count circuit counts to enable emission according to the gray level represented by the digital data. The comparator may output a logical zero, “0” as the MTCH bit until the digital data matches the count, at which point the comparator outputs a logical one, “1” as the MTCH bit. The MTCH bit is generally sent to and stored in the memory circuit 754, while the value of the inverted MTCH bit is sent to the output inverter 756 and ultimately to the corresponding sub-pixel to cause and / or stop emission.

[0186] Continuing along the transmission path of the MTCH bit, FIG. 31 shows a pixel circuit 780 that can be used in conjunction with the smart buffer circuit of FIG. 30. The pixel circuit 780 includes an input latch 782 (e.g., an inverter pair) and an output latch 784 (e.g., an inverter pair), both of which are operated to latch digital data transmitted from a smart buffer, e.g., smart buffer 712, in response to a write_enable control signal 786. Once latched, the digital data can be automatically transmitted to the gate of drive transistor 788. As described above, drive transistor 788 is activated in response to the digital data and in response to the value of the digital data to transmit a drive current through a light emitting circuit, e.g., light emitting diode 790 of pixel circuit 780.

[0187] Accordingly, the technical effects of the present disclosure include techniques for implementing memory in one or more pixels of an electronic display to improve image data processing techniques for presentation. This technology includes systems and methods for receiving image data, storing the image data in memory within the pixel, and transmitting the image to a drive circuit to operate a light emitting element of the pixel to emit light. Further, any suitable pixel circuit implementing in-pixel memory technology can be used to implement different light emitting schemes including binary pulse width modulation light emitting schemes, binary pulse width modulation rearrangement schemes, single pulse width modulation light emitting schemes, and pulse density modulation light emitting schemes, and benefits from reducing the bandwidth used to communicate the same image without using in-pixel memory technology. These pixel circuits enabling the light emitting schemes can be coupled to pixel circuits having a hybrid drive to enhance the responsiveness to the electrical signal of the LED.

[0188] The technology described in this specification may be applied to and integrated with various display technologies and should not be limited to the specific embodiments illustrated and / or described in this specification. For example, although a pixel with memory is shown as having a light-emitting diode as a light modulation device, pixel-in-memory technology may generally be applied to different pixel circuits to support various display technologies using various light modulation devices. Thus, suitable pixel circuits that support light emission via a light-emitting diode, a digital micromirror display, an organic light-emitting diode, or a liquid crystal display, a plasma display, or a dot matrix display can each have memory in the pixel to achieve at least an improvement in data transmission bandwidth and ease of pixel programming.

[0189] It should be understood that the above-described specific embodiments are presented by way of example and that these embodiments may be subject to various modifications and alternative forms. Further, it is to be understood that the claims are not limited to the specific forms disclosed but rather include all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0190] The technology presented and claimed in this specification is applied with reference to tangible and specific examples of a practical nature that clearly improve the art and, as such, is not abstract, intangible, or merely theoretical. Further, it is intended that, in the event any of the appended claims at the end of this specification contain one or more elements presented as "means for [performing a function]" or "steps for [performing a function]", such elements shall be construed in accordance with 35 U.S.C. § 112(f). However, with respect to any of the claims containing elements presented in any other manner, it is intended that such elements shall not be construed in accordance with 35 U.S.C. § 112(f).

[0191] Exemplary embodiments may include the following.

[0192] Embodiment Example 1: An electronic display, comprising: An active area including a first pixel formed within the active area, the first pixel being configured to emit light in response to image data, the active area; A controller configured to transmit image data to the first pixel, The first pixel includes: An organic light emitting diode configured to emit light in response to image data; A memory configured to digitally store the image data received from the controller; A drive circuit configured to receive the image data from the memory, the drive circuit being configured to cause the organic light emitting diode to emit light in response to the image data. An electronic display.

[0193] Embodiment Example 2: The electronic display according to Embodiment Example 1, wherein the controller is configured to transmit the image data to the memory of the first pixel via a data line of the active area.

[0194] Embodiment Example 3: The controller is configured to transmit the image data to a multiplexing circuit via a data line of the active area, and the controller is configured to control the multiplexing circuit to mediate the transmission of the image data to the memory of the first pixel. The electronic display according to Embodiment Example 1.

[0195] Embodiment Example 4: The image data includes two or more color channels corresponding to the image to be displayed. The controller programs the memory associated with the first color channel of the image data at a first time by activating a first multiplexing control signal, and is configured to cause the memory of the first pixel to be programmed. The controller programs the memory associated with the second color channel of the image data at a second time by activating a second multiplexing control signal, and is configured to cause the memory of the second pixel to be programmed. The electronic display according to Embodiment Example 3.

[0196] Embodiment Example 5: The controller is configured to program the memory of the first pixel with image data, the image data is associated with a first color channel and is programmed at a first time, the controller is configured to program the memory of the first pixel with second image data, the second image data is associated with a second color channel and is programmed at a second time, the electronic display according to Embodiment Example 1.

[0197] Embodiment Example 6: The memory of the first pixel is configured to operate as an in-display frame buffer for the first pixel in the electronic display, the electronic display according to Embodiment Example 1.

[0198] Embodiment Example 7: The memory of the first pixel is configured to receive a counter signal and image data, and the memory is configured to operate a switch by transmitting the image data at least partially based on the counter signal, causing the organic light-emitting diode to emit light according to a binary pulse width modulation emission scheme, the electronic display according to Embodiment Example 1.

[0199] Embodiment Example 8: The driving circuit of the first pixel includes a comparator configured to receive a signal indicating a number and image data, and the comparator is configured to operate a switch at least partially based on the image data and the signal representing the number, causing the organic light-emitting diode to emit light according to a single pulse width modulation emission scheme, the electronic display according to Embodiment Example 1.

[0200] Embodiment Example 9: The driving circuit includes an adder configured to add image data to a specified value of an accumulator during an addition process, and the carry bit from the addition process is configured to operate a switch, causing the organic light-emitting diode to emit light according to a pulse density modulation emission scheme, the electronic display according to Embodiment Example 1.

[0201] Embodiment Example 10: A sub-pixel of a specific color in an electronic display, a memory configured to receive a signal indicating a value within a data range, a first terminal configured to receive a first voltage signal, a second terminal configured to receive a second voltage signal, a light-emitting diode configured to emit light at least partially based on a signal indicating a value within a data range, and the memory is configured to enable current to be transmitted through the light-emitting diode to cause light emission, and the current is at least partially based on the first voltage signal and the second voltage signal, the sub-pixel.

[0202] Embodiment Example 11: The memory includes a register configured to receive a counter signal and a signal indicating a value within a data range, and the memory is configured to operate a switch by transmitting a signal indicating a value within a data range at least partially based on the counter signal, so that the light-emitting diode emits light according to a binary pulse width modulation light emission scheme, the sub-pixel according to Embodiment Example 10.

[0203] Embodiment Example 12: The sub-pixel according to Embodiment Example 10 includes a comparator configured to receive a signal indicating a number and a signal indicating a value within a data range, and the comparator is configured to operate the light-emitting diode based on the signal indicating a value within a data range and the signal indicating a number, so that the light-emitting diode emits light according to a single pulse width modulation light emission scheme.

[0204] Embodiment Example 13: The sub-pixel according to Embodiment Example 10 includes an adder configured to add a signal indicating a value within a data range to a specified value of an accumulator configured to be coupled to the adder during an addition process, and a carry bit from the addition process is configured to operate the light-emitting diode so that the light-emitting diode emits light according to a pulse density modulation light emission scheme.

[0205] Embodiment Example 14: The memory is configured to function as a frame buffer for storing a signal indicating a value within a data range for a time period before permitting a signal indicating a value within the data range that is used to cause the light emitting diode to emit light, the sub-pixel described in Embodiment Example 10.

[0206] Embodiment Example 15: A pixel, A first sub-pixel of the pixel, the first sub-pixel corresponding to a first color channel, A first memory configured to store a first signal indicating a first value within a first data range used to communicate image data of the first color channel of the pixel, A first drive circuit configured to receive a first signal indicating a first value from the first memory, the first drive circuit being configured to cause a first light emitting diode to emit light based at least in part on the first signal indicating the first value, the first drive circuit, included in the first sub-pixel, A second sub-pixel of the pixel, the second sub-pixel corresponding to a second color channel, A second memory configured to store a second signal indicating a second value within a second data range used to communicate image data of the second color channel of the pixel, A second drive circuit configured to receive a second signal indicating a second value from the second memory, the second drive circuit being configured to cause a second light emitting diode to emit light based at least in part on the second signal indicating the second value, the second drive circuit, included in the second sub-pixel, the pixel including.

[0207] Embodiment Example 16: The first sub-pixel is configured to be programmed with a first signal indicating a first value at a first time, the second sub-pixel is configured to be programmed with a second signal indicating a second value at a second time, the first time occurring earlier than the second time, the pixel described in Embodiment Example 15.

[0208] Embodiment Example 17: The first signal is configured to be transmitted to the first sub-pixel via a multiplexing circuit configured to operate in response to a first control signal transmitted at a first time, and the first signal is configured to stop being transmitted to the first sub-pixel in response to the multiplexing circuit receiving a second control signal transmitted at a second time. The pixel according to Embodiment Example 16.

[0209] Embodiment Example 18: The first memory is configured to operate as a frame buffer for the first sub-pixel. The pixel according to Embodiment Example 15.

[0210] Embodiment Example 19: The first sub-pixel includes a first counter, the first memory is configured to receive an output from the first counter, the output from the first memory is configured to activate a switch in response to the output from the counter, and the output from the first memory is configured to operate a first light-emitting diode to emit light according to a binary pulse-width modulation light-emitting scheme. The pixel according to Embodiment Example 15.

[0211] Embodiment Example 20: The first driving circuit includes a comparator configured to receive an output from the first memory and an output from a counter configured to correspond to a time difference between the output from the first memory and an increment of a gray level associated with the first color channel, and the first driving circuit is configured to operate the first light-emitting diode based at least in part on the output from the comparator. The pixel according to Embodiment Example 15.

[0212] Embodiment Example 21: An electronic display, A memory formed within the active area of the electronic display or within an integrated circuit of the electronic display outside the active area, the memory being configured to store a digital data signal indicating a value within a data range, A driver disposed within the active area, the driver being configured to generate one or more analog electrical signals in response to the digital data signal, An electronic display including: a light modulation device disposed on an active area, the light modulation device being configured to emit light at least partially based on one or more analog electrical signals.

[0213] Embodiment Example 22: The electronic display according to Embodiment Example 21, wherein the light modulation device includes a light emitting diode, a digital micromirror display, an organic light emitting diode, or a liquid crystal display, a plasma display, or a device supporting a dot matrix display, or any combination thereof.

[0214] Embodiment Example 23: The electronic display according to Embodiment Example 21, wherein the light modulation device includes a light emitting diode, and the light emitting diode and the driver are configured to support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals.

[0215] Embodiment Example 24: The electronic display according to Embodiment Example 21, wherein the light modulation device includes a light emitting diode, and the light emitting diode and the driver are configured to support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals.

[0216] Embodiment Example 25: The electronic display according to Embodiment Example 24, wherein the memory includes a transistor configured to be activated in response to a selection control signal, and a first subset of the digital data signal is configured to be transmitted to the driver in response to the activation of the transistor.

[0217] Embodiment Example 26: The electronic display according to Embodiment Example 24, wherein the first inverter pair is configured to output a first subset of the digital data signal to a sense amplifier before outputting to the driver.

[0218] Embodiment Example 27: An electronic display according to Embodiment Example 24, comprising a switch / reset (SR) latch configured to be coupled to the output of a first inverter pair, and a second inverter pair configured to be coupled to the output of the switch / reset latch, wherein the switch / reset latch and the second inverter pair are configured to enable a binary pulse width modulation light emission scheme with rearrangement.

[0219] Embodiment Example 28: An electronic display according to Embodiment Example 24, wherein the memory includes a second inverter pair configured to store a second subset of digital data signals transmitted to the pixels.

[0220] Embodiment Example 29: An electronic display according to Embodiment Example 28, wherein a first subset of the digital data signals and a second subset of the digital data signals are transmitted to the first inverter pair in response to a controller that enables a writable control signal.

[0221] Embodiment Example 30: A pixel of an electronic display, a memory configured to store a first digital data signal transmitted from a column driver to the pixel, the first digital data signal being configured to correspond to an image to be displayed by having a value within a data range for communicating a portion of the image, a memory including one or more inverter pairs configured to receive the first digital data signal transmitted from the column driver to the memory within the pixel, a comparator configured to receive a first digital data signal and a second digital data signal from the one or more inverter pairs, and configured to output a control signal in response to determining when the first digital data signal matches the second digital data signal, a driver configured to receive the control signal from the memory and configured to cause the pixel to emit light based at least in part on the control signal.

[0222] Embodiment Example 31: The pixel according to Embodiment Example 30, including a counter configured to output to a comparator a display of the current number counted as the second digital data signal.

[0223] Embodiment Example 32: The pixel according to Embodiment Example 30, including a transistor configured to enable pre-charge of a memory.

[0224] Embodiment Example 33: The pixel according to Embodiment Example 30, including an additional inverter pair separate from one or more inverter pairs configured to store the output from a comparator before transmitting it as a control signal to a driver.

[0225] Embodiment Example 34: The pixel according to Embodiment Example 33, wherein the additional inverter pair is reset between a first memorization of a first output and a second memorization of a second output.

[0226] Embodiment Example 35: The pixel according to Embodiment Example 30, including a transistor configured to enable a control signal to be output from a comparator and transmitted to a driver, the transistor being configured to be activated in response to a dischargeable signal.

[0227] Embodiment Example 36: The pixel according to Embodiment Example 30, including additional memory corresponding to color channels associated with displaying an image, the additional memory being configured to be coupled to a driver.

[0228] Embodiment Example 37: An electronic display, a controller configured to generate one or more digital data signals to display an image, a buffer including a first memory configured to store a first digital data signal of one or more data signals, the first digital data signal being configured to display a portion of the image on the electronic display, A plurality of pixels configured to emit light in response to one or more digital data signals, wherein each pixel of the plurality of pixels A driver configured to receive a first digital data signal from a first memory and configured to generate an analog data signal in response to the first digital data signal transmitted from the first memory, the plurality of pixels including the driver An electronic display including a light-emitting circuit configured to be coupled to the driver and configured to emit light at least partially based on the analog data signal.

[0229] Embodiment Example 38: An electronic display according to Embodiment Example 37, including a selection circuit configured to be coupled to the output of a first memory and the output of a second memory, the buffer also including a second memory for storing a second digital data signal, the selection circuit being configured to select the first memory and output the first digital data signal to the driver regardless of selecting the second memory.

[0230] Embodiment Example 39: An electronic display according to Embodiment Example 38, wherein the selection circuit is configured to be coupled to the output of an inverter pair, the inverter pair being configured to store the output from the first memory when the selection circuit operates in a first state, and the inverter pair being configured to store the output from the second memory when the selection circuit operates in a second state.

[0231] Embodiment Example 40: An electronic display according to Example 37, wherein each pixel includes a count circuit configured to be coupled to a first sub-pixel, the first sub-pixel including a comparator, the comparator being configured to compare the output from the count circuit with the output from the first memory.

[0232] Embodiment Example 41: A pixel circuit for an electronic display, A memory configured to store a digital data signal indicating a value within a data range, A light-emitting diode configured to emit light based at least in part on a digital data signal, An initialization transistor configured to initialize a pixel circuit before the light-emitting diode emits light, A driving transistor configured to be activated based at least in part on a digital data signal, and a pixel circuit including the same.

[0233] Embodiment Example 42: The pixel circuit according to Embodiment Example 41, including a voltage driving circuit configured to be coupled to an anode of the light-emitting diode, the voltage driving circuit being configured to amplify the anode of the light-emitting diode at the start of a light-emitting period of the light-emitting diode.

[0234] Embodiment Example 43: The driving transistor is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET), and the pixel circuit includes a plurality of p-type or n-type MOSFETs configured to cause the light-emitting diode to emit light in response to a control signal, the pixel circuit according to Embodiment Example 41.

[0235] Embodiment Example 44: The pixel circuit according to Embodiment Example 41, including a reset circuit configured to be coupled in parallel with the light-emitting diode, the reset circuit being configured to reset the anode voltage of the light-emitting diode after a light-emitting period.

[0236] Embodiment Example 45: The pixel circuit according to Embodiment Example 41, including a hybrid drive including a voltage drive and a current drive circuit, the hybrid drive being configured to operate the light-emitting diode to emit light in response to a voltage data signal, a plurality of reference voltages, and an image data control signal based at least in part on the digital data signal.

[0237] Embodiment Example 46: A pixel circuit according to Embodiment Example 41, including an auto-zero transistor configured to be activated in response to an auto-zero control signal, wherein the voltage value of the source node of the auto-zero transistor is configured to increase until the voltage value of the source node of the auto-zero transistor becomes equal to the voltage value of the gate voltage of the driving transistor.

[0238] Embodiment Example 47: A pixel circuit according to Embodiment Example 41, wherein the memory includes a register configured to store a digital data signal and a comparator configured to compare a number generated by a counter with the digital data signal, and the memory is configured to transmit an output from the comparator to activate the driving transistor.

[0239] Embodiment Example 48: A pixel circuit according to Embodiment Example 41, including an additional circuit configured to operate with the memory to activate the driving transistor and cause light emission according to a binary pulse width modulation light emission scheme, a single pulse width modulation light emission scheme, a pulse density modulation light emission scheme, or any combination thereof.

[0240] Embodiment Example 49: An electronic display, a controller configured to generate one or more digital data signals to display an image, a plurality of pixels configured to emit light in response to one or more digital data signals, wherein a first pixel of the plurality of pixels includes a memory configured to receive a first digital data signal generated by the controller based at least in part on the image, a light emitting circuit configured to emit light based at least in part on the first digital data signal, an initialization transistor configured to initialize the first pixel before the light emitting circuit emits light, and a driving transistor configured to be activated based at least in part on the first digital data signal.

[0241] Embodiment Example 50: The electronic display according to Embodiment Example 49, including a second pixel of a plurality of pixels, wherein the memory of the second pixel is configured to receive a second digital data signal at a time different from the time when the memory of the first pixel is configured to receive the first digital data signal.

[0242] Embodiment Example 51: The electronic display according to Embodiment Example 50, wherein the controller is configured to mediate the transmission of one or more digital data signals to one or more pixels by controlling a multiplexing circuit.

[0243] Embodiment Example 52: The electronic display according to Embodiment Example 49, wherein the light-emitting circuit includes a light-emitting diode, and the first pixel includes a voltage drive circuit configured to amplify the anode of the light-emitting diode during the light-emitting period of the light-emitting diode.

[0244] Embodiment Example 53: The electronic display according to Embodiment Example 49, wherein the first pixel includes a hybrid drive circuit configured to operate a light-emitting circuit to emit light in response to a voltage data signal, a plurality of reference voltages, and an image data control signal based at least in part on the first digital data signal.

[0245] Embodiment Example 54: The electronic display according to Embodiment Example 49, wherein the light-emitting circuit includes a light-emitting diode, an organic light-emitting diode, or a circuit supporting a liquid crystal display, a plasma display panel, a dot matrix display, a digital micromirror drive display, or any combination thereof.

[0246] Embodiment Example 55: A method comprising: transmitting a first value to a first memory of a first pixel at a first time via a controller; executing an initialization process via a controller to prepare the first pixel to emit light according to the first value; Executing a programming process of programming a node of a first pixel with one or more voltage values via a controller; Executing an emission process via a controller, wherein execution of the emission process is configured to emit light from a light-emitting circuit of the first pixel.

[0247] Embodiment Example 56: The step of transmitting a first value to a first memory includes: The controller activating a first multiplexing control signal that permits transmission of the first value to the first memory at a first time via the controller; The controller deactivating a second multiplexing control signal that stops transmission of the first value to a second memory at the first time via the controller, thereby including a step of arbitrating programming of the first memory and the second memory of a second pixel, according to the method described in Embodiment Example 55.

[0248] Embodiment Example 57: The programming process includes: Activating an automatic zero control signal via a controller; Deactivating the automatic zero control signal via the controller after a predetermined time, according to the method described in Embodiment Example 45.

[0249] Embodiment Example 58: The light-emitting process includes: Activating a voltage drive control signal configured to cause amplification of a light-emitting circuit via a controller; Emitting, via the controller, an image data control signal configured to activate a drive transistor in response to a binary pulse width modulation light-emitting scheme, a single pulse width modulation light-emitting scheme, a pulse density modulation light-emitting scheme, or any combination thereof, according to the method described in Embodiment Example 45.

[0250] Embodiment Example 59: The method according to Embodiment Example 45 includes executing a reset process for resetting a light-emitting circuit to prepare for future light emission.

[0251] Embodiment Example 60: The initialization process includes the step of activating, via a controller, a selection control signal that causes charging of a capacitor, and through the charging of the capacitor, the capacitor is configured to transmit a drive current to a first pixel, the method according to Embodiment Example 45.

Claims

1. 1. An electronic display comprising: an active area including a first pixel formed within the active area, the first pixel configured to emit light in response to image data; a controller configured to transmit the image data to the first pixel; The first pixel includes: an organic light emitting diode configured to emit said light in response to said image data; a memory configured to digitally store the image data received from the controller; and a drive circuit configured to receive the image data from the memory, the drive circuit configured to cause the organic light emitting diode to emit the light in response to the image data.

2. 2. The electronic display of claim 1 , wherein the memory of the first pixel is configured to receive a counter signal and the image data, and the memory is configured to operate a switch by transmitting the image data based at least in part on the counter signal to cause the organic light emitting diode to emit the light according to a binary pulse width modulated light emission scheme.

3. 2. The electronic display of claim 1 , wherein the drive circuit of the first pixel includes a comparator configured to receive a signal indicative of a number and the image data, the comparator configured to operate a switch based at least in part on the image data and the signal representing the number to cause the organic light emitting diode to emit the light according to a single pulse width modulated light emission scheme.

4. 2. The electronic display of claim 1, wherein the drive circuitry includes an adder configured to add the image data to a defined value in an accumulator during a summing process, and a carry bit from the summing process is configured to operate a switch to cause the organic light emitting diode to emit the light according to a pulse density modulated light emission scheme.

5. 2. The electronic display of claim 1, wherein the controller is configured to program the memory of the first pixel with the image data, the image data associated with a first color channel and programmed at a first time, and the controller is configured to program the memory of the first pixel with second image data, the second image data associated with a second color channel and programmed at a second time.

6. 1. An electronic display comprising: a memory formed within an active area of ​​the electronic display or within an integrated circuit of the electronic display outside of the active area, the memory configured to store digital data signals indicative of values ​​within a data range; a driver disposed within the active area, the driver configured to generate one or more analog electrical signals in response to the digital data signal; a light modulation device disposed over the active area, the light modulation device configured to emit light based at least in part on the one or more analog electrical signals.

7. 7. The electronic display of claim 6, wherein the light modulating device comprises a light emitting diode, a digital mirror display, an organic light emitting diode, or a device supporting a liquid crystal display, a plasma display, or a dot matrix display, or any combination thereof.

8. The electronic display of claim 6 , wherein the memory includes a first pair of inverters configured to store a first subset of the digital data signals sent to the pixels.

9. 9. The electronic display of claim 8, wherein the first pair of inverters is configured to output the first subset of the digital data signals to a sense amplifier before outputting them to the driver.

10. 9. The electronic display of claim 8, comprising a switch / reset (SR) latch configured to couple to an output of the first inverter pair, and a second inverter pair configured to couple to an output of the switch / reset latch, the switch / reset latch and the second inverter pair configured to enable a binary pulse width modulation lighting scheme with reordering.

11. The electronic display of claim 6 , wherein the memory includes a second pair of inverters configured to store a second subset of the digital data signals sent to the pixels.

12. 12. The electronic display of claim 11, wherein said first subset of said digital data signals and said second subset of said digital data signals are sent to said first pair of inverters in response to a write enable control signal.

13. 7. The electronic display of claim 6, wherein the light modulation devices include light emitting diodes, the light emitting diodes and the drivers configured to support a global cathode or global anode configuration configured to emit light using the one or more analog electrical signals.

14. 1. A pixel circuit for an electronic display, comprising: a memory configured to store digital data signals indicative of values ​​within a data range; a light emitting diode configured to emit light based at least in part on the digital data signal; an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light; a drive transistor configured to be activated based at least in part on the digital data signal.

15. 15. The pixel circuit of claim 14, comprising a voltage drive circuit configured to couple to an anode of the light emitting diode, the voltage drive circuit configured to boost the anode of the light emitting diode at a start of a light emitting period of the light emitting diode.

16. 15. The pixel circuit of claim 14, wherein the drive transistor is configured as a metal oxide semiconductor field effect transistor (MOSFET), and the pixel circuit comprises a plurality of p-type or n-type MOSFETs configured to cause the light emitting diode to emit light in response to a control signal.

17. 15. The pixel circuit of claim 14, comprising a reset circuit configured to couple in parallel to the light emitting diode, the reset circuit configured to reset an anode voltage of the light emitting diode after a period of light emission.

18. 15. The pixel circuit of claim 14, comprising a hybrid drive including voltage drive and current drive circuitry, the hybrid drive configured to operate the light emitting diode to emit light in response to a voltage data signal, a plurality of reference voltages, and image data control signals based at least in part on the digital data signal.

19. 15. The pixel circuit of claim 14, comprising additional circuitry configured to operate with the memory to activate the drive transistor to cause emission according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, or a pulse density modulated emission scheme, or any combination thereof.

20. 15. The pixel circuit of claim 14, wherein the memory includes a register configured to store the digital data signal and a comparator configured to compare the digital data signal with a number configured to be generated by a counter, the memory being configured to transmit an output from the comparator to activate the drive transistor.

21. A pixel, a first sub-pixel of the pixel, the first sub-pixel corresponding to a first color channel; a first memory configured to store a first signal indicative of a first value within a first data range used to communicate image data for the first color channel of the pixel; a first sub-pixel including: a first drive circuit configured to receive the first signal indicative of the first value from the first memory, the first drive circuit configured to cause a first light emitting diode to emit light based at least in part on the first signal indicative of the first value; and a second sub-pixel of the pixel, the second sub-pixel corresponding to a second color channel; a second memory configured to store a second signal indicative of a second value within a second data range used to communicate image data for the second color channel of the pixel; and and a second drive circuit configured to receive the second signal indicative of the second value from the second memory, the second drive circuit configured to cause a second light emitting diode to emit light based at least in part on the second signal indicative of the second value.

22. 22. The pixel of claim 21 , wherein the first sub-pixel is configured to be programmed with the first signal indicating a first value at a first time and the second sub-pixel is configured to be programmed with the second signal indicating the second value at a second time, the first time occurring earlier than the second time.

23. 23. The pixel of claim 22, wherein the first signal is configured to be transmitted to the first sub-pixel via a multiplexing circuit configured to operate in response to a first control signal transmitted at the first time, and the first signal is configured to stop being transmitted to the first sub-pixel in response to the multiplexing circuit receiving a second control signal transmitted at the second time.

24. The pixel of claim 21 , wherein the first memory is configured to act as a frame buffer for the first sub-pixel.

25. 22. The pixel of claim 21 , wherein the first sub-pixel includes a first counter, the first memory configured to receive an output from the first counter, the output from the first memory configured to activate a switch in response to the output from the counter, and the output from the first memory configured to operate the first light emitting diode to emit the light according to a binary pulse width modulated emission scheme.

Images