Photoelectric conversion device and photoelectric conversion system

Abstract

To provide technique for improving characteristics in a photoelectric conversion device formed by laminating a first substrate and a second substrate to each other.SOLUTION: A photoelectric conversion device has a first substrate and a second substrate joined to the first substrate. The photoelectric conversion device has: a plurality of pixel circuits that is provided to form a plurality of columns on the first substrate, and each outputs a signal based on electric charges generated through photoelectric conversion; a plurality of column circuits that is provided on the second substrate, and each performs gain processing on an output signal from a corresponding pixel circuit; a reference signal output unit that is provided on the second substrate and outputs a reference signal according to the gain processing; a connection unit that electrically connects the first substrate and the second substrate to each other; and an output signal output unit that has an amplifier circuit provided on the first substrate. The signal output unit outputs signals based on the reference signal input from the reference signal output unit through the connection unit, to the plurality of column circuits through the amplifier circuit.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] In recent years, stacked image sensors configured by forming a pixel substrate on which pixels are arranged and a signal processing substrate on which peripheral circuit sections are arranged on separate semiconductor substrates and bonding these substrates together have become widespread. Patent Document 1 discloses an imaging device that is intended to suppress an increase in chip area without degrading pixel performance, and to suppress in-plane non-uniformity of dark current due to heat generation in peripheral circuits, by arranging a pixel array arranged on a pixel substrate and a column circuit arranged on a signal processing substrate at overlapping positions.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the imaging device described in Patent Document 1, characteristics may deteriorate due to differences in circuit non-linearity according to differences in characteristics between the circuits of the pixel substrate and the circuits of the signal processing substrate with different process technologies.

[0005] An object of the present invention is to provide a technique for improving characteristics in a photoelectric conversion device configured by bonding a first substrate provided with a pixel circuit and a second substrate.

Means for Solving the Problems

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device including a first substrate and a second substrate bonded to the first substrate, the photoelectric conversion device including: a plurality of pixel circuits provided in the first substrate so as to form a plurality of columns, each pixel circuit outputting a signal based on charges generated by photoelectric conversion; a plurality of column circuits provided in the second substrate, each column circuit performing gain processing on an output signal from a corresponding pixel circuit; a reference signal output unit provided in the second substrate and outputting a reference signal according to the gain processing; a connection unit electrically connecting the first substrate and the second substrate; and a signal output unit having an amplification circuit provided in the first substrate, wherein the signal output unit outputs a signal based on the reference signal input from the reference signal output unit via the connection unit to the plurality of column circuits via the amplification circuit.

Advantages of the Invention

[0007] According to the present invention, in a photoelectric conversion device configured by bonding a pixel substrate and a signal processing substrate, characteristics can be improved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment will be described. In this specification, even when the ratio of the output voltage to the input voltage is 1 or less, this ratio is expressed as "gain". Also, signal processing with a gain of 1 or less is included in "amplification". That is, what is generally called "buffering" (gain of about 1) or "attenuation" (gain less than 1) is also included in "amplification".

[0010] [First Embodiment] The photoelectric conversion device and its driving method according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment. FIG. 2 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to this embodiment. FIG. 3 is an equivalent circuit diagram showing a configuration example of a column circuit of the photoelectric conversion device according to this embodiment. FIGS. 4 and 5 are schematic diagrams showing configuration examples of the photoelectric conversion device according to this embodiment. FIGS. 6 and 7 are schematic cross-sectional views showing configuration examples of the photoelectric conversion device according to this embodiment. FIG. 8 is a schematic diagram showing a configuration example of the photoelectric conversion device according to a modified example of this embodiment.

[0011] First, the schematic configuration of the photoelectric conversion device according to this embodiment will be described with reference to FIG. 1. As shown in FIG. 1, the photoelectric conversion device 100 includes a pixel array unit 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 70, a signal processing circuit 80, and a timing generation unit 90. Further, the photoelectric conversion device 100 further includes a current source 18, a reference signal output circuit 34, a reference signal output circuit 48, and a counter circuit 56.

[0012] The pixel array unit 10 is provided with a plurality of pixels 12 arranged in a matrix over a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit including a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. FIG. 1 shows a total of 16 pixels 12 arranged in 4 rows and 4 columns, but typically tens of millions of pixels 12 are arranged in the pixel array unit 10. Note that the number of rows and columns of the pixel array arranged in the pixel array unit 10 is not particularly limited. In addition to the effective pixels that output pixel signals corresponding to the amount of incident light, the pixel array unit 10 may be provided with optical black pixels in which the photoelectric conversion unit is shielded from light, dummy pixels that do not output signals, and the like.

[0013] In each row of the pixel array unit 10, control lines 14 are arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 arranged in the first direction, and forms a common signal line for these pixels 12. The first direction in which the control lines 14 extend is sometimes referred to as the row direction or the horizontal direction. The control lines 14 are connected to the vertical scanning circuit 20. Note that the control lines 14 in each row may include a plurality of signal lines.

[0014] In each column of the pixel array unit 10, signal output lines 16 are arranged extending in a second direction (the vertical direction in FIG. 1) intersecting the first direction. The signal output lines 16 in each column are connected to the pixels 12 arranged in the second direction, and form a common signal line for these pixels 12. The second direction in which the signal output lines 16 extend is sometimes referred to as the column direction or the vertical direction. The signal output lines 16 are connected to the readout circuit 30. In addition, a current source 18 is connected to the signal output lines 16 in each column. Note that a plurality of signal output lines 16 may be arranged in each column of the pixel array unit 10.

[0015] The vertical scanning circuit 20 receives a control signal from the timing generation unit 90, generates a control signal for driving the pixel 12, and has a function of outputting it to the pixel 12 via the control line 14. As the vertical scanning circuit 20, logic circuits such as a shift register and an address decoder can be used. The vertical scanning circuit 20 sequentially outputs control signals to the control lines 14 of each row, and sequentially drives the pixels 12 of the pixel array unit 10 row by row. The signals read out from the pixels 12 row by row are input to the readout circuit 30 via the signal output lines 16 arranged in each column of the pixel array unit 10.

[0016] The readout circuit 30 has a plurality of column circuits 32 connected to each of the plurality of signal output lines 16 arranged in the pixel array unit 10. Each of the plurality of column circuits 32 has a function of performing predetermined gain processing on the output signal of the pixel 12 in the corresponding column. In the present embodiment, each of the plurality of column circuits 32 performs analog-to-digital conversion (AD conversion) on the pixel signal output from the pixel 12 connected to the corresponding signal output line 16, and has a role of holding the digital data that is the result of the AD conversion of the pixel signal. Each of the plurality of column circuits 32 is connected to a horizontal scanning circuit 70 and a horizontal output line 62. Further, a reference signal output circuit 34, a reference signal output circuit 48, and a counter circuit 56 are connected to the readout circuit 30.

[0017] The reference signal output circuit 34 has a role of outputting a reference signal VREF that serves as a basis for calculating a correction value for performing correction processing such as gain error correction performed in the signal processing circuit 80. The reference signal output circuit 34 controls the voltage value of the reference signal VREF according to the degree of change in the signal level of the reference signal rmp output from the reference signal output circuit 48. In this specification, a functional block including the reference signal output circuit 34 may be referred to as a reference signal output unit.

[0018] The reference signal output circuit 48 has a role of outputting a reference signal rmp used for AD conversion to the column circuits 32 of each column. The reference signal rmp used for AD conversion is a signal that has a predetermined amplitude corresponding to the range of the pixel signal and whose level changes over time. The reference signal rmp is not particularly limited, but for example, a ramp signal whose level monotonically increases or monotonically decreases over time can be applied. Note that the change in the signal level of the reference signal rmp does not necessarily have to be continuous and may be stepwise. Also, the change in the signal level of the reference signal rmp does not necessarily have to be linear with respect to time and may be curvilinear (e.g., sine wave or cosine wave) with respect to time. In this specification, the functional block including the reference signal output circuit 48 may be referred to as a reference signal output unit.

[0019] The counter circuit 56 has a role of counting a clock pulse signal CLK supplied from a clock pulse supply unit (not shown) and outputting a count signal indicating the count value to the column circuit 32. The counter circuit 56 starts the counting operation in synchronization with the timing at which the change in the signal level of the reference signal output from the reference signal output circuit 48 starts. Note that the function of the counter circuit 56 may be provided in each of the column circuits 32.

[0020] The horizontal scanning circuit 70 receives a control signal from the timing generation unit 90, generates a control signal for reading out pixel signals from the column circuits 32 of the readout circuit 30, and outputs it to the readout circuit 30. The horizontal scanning circuit 70 sequentially scans the column circuits 32 of each column of the readout circuit 30, and causes the pixel signals held in each memory to be sequentially output to the signal processing circuit 80 via the horizontal output line 62. As the horizontal scanning circuit 70, logic circuits such as a shift register and an address decoder can be used.

[0021] The signal processing circuit 80 is a processing circuit composed of a buffer amplifier, a differential amplifier, etc., which performs predetermined signal processing on the pixel signals of the columns selected by the horizontal scanning circuit 70 and outputs the processed pixel data. Examples of the signal processing performed in the signal processing circuit 80 include correction processing such as correction of gain errors in the column circuit. The external interface circuit included in the signal processing circuit 80 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied to the external interface circuit. The SerDes transmission circuit is, for example, an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit.

[0022] The timing generation unit 90 is a control circuit that outputs control signals for controlling the operations and their timings of the vertical scanning circuit 20, the reference signal output circuit 34, the reference signal output circuit 48, the counter circuit 56, the horizontal scanning circuit 70, the signal processing circuit 80, etc., and supplies them to each functional block. Note that at least a part of the control signals supplied to these functional blocks may be supplied from outside the photoelectric conversion device 100.

[0023] Each of the pixels 12 constituting the pixel array unit 10 has, for example, as shown in FIG. 2, a photoelectric conversion element PD, a transfer transistor M1, and a pixel circuit 17. The pixel circuit 17 can be composed of a reset transistor M2, an amplification transistor M3, and a selection transistor M4. In the present embodiment, the description will be based on a form in which the photoelectric conversion element PD, the transfer transistor M1, and the pixel circuit 17 are provided on the same substrate. However, as will be described later, the photoelectric conversion element PD and the pixel circuit 17 may be provided on different substrates.

[0024] The photoelectric conversion element PD can be, for example, a photodiode. In the photoelectric conversion element PD, the anode is connected to the ground voltage node, and the cathode is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion part (floating diffusion). The floating diffusion part includes a capacitance component (floating diffusion capacitance) and has a function as a charge holding part. The floating diffusion capacitance may include the gate capacitance of a transistor, a pn junction capacitance, a wiring capacitance, and the like. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal output line 16.

[0025] In the case of the pixel configuration of FIG. 2, the control line 14 for each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal TX is supplied from the vertical scanning circuit 20 to the gate of the transfer transistor M1. A control signal RES is supplied from the vertical scanning circuit 20 to the gate of the reset transistor M2. A control signal SEL is supplied from the vertical scanning circuit 20 to the gate of the selection transistor M4. When each transistor is composed of an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 20. Also, the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 20.

[0026] In addition, in this embodiment, an explanation will be given assuming a case where electrons among electron-hole pairs generated in the photoelectric conversion element PD by light incidence are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 can be constituted by an N-type MOS transistor. However, the signal charge is not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor becomes the opposite conductivity type to that described in this embodiment. In addition, the names of the source and drain of the MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by reverse names.

[0027] The photoelectric conversion element PD converts incident light into an amount of charge corresponding to the amount of the light (photoelectric conversion) and accumulates the generated charge. The transfer transistor M1 transfers the charge held by the photoelectric conversion element PD to the node FD when it is turned on. The charge transferred from the photoelectric conversion element PD is held in the capacitance component (floating diffusion capacitance) of the node FD. As a result, the node FD becomes a potential corresponding to the amount of the charge transferred from the photoelectric conversion element PD by charge-voltage conversion by the floating diffusion capacitance.

[0028] The reset transistor M2 has a role of controlling a reset operation for resetting the node FD as a charge holding unit. That is, the reset transistor M2 is a reset unit that resets the node FD to a voltage corresponding to the voltage VDD when it is turned on.

[0029] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the signal output line 16. The amplification transistor M3 is configured such that the voltage VDD is supplied to the drain and the bias current is supplied from the current source 18 to the source via the selection transistor M4, and it constitutes an amplification unit (source follower circuit) with the gate as the input node. As a result, the amplification transistor M3 outputs a signal based on the potential of the node FD to the signal output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are output units that output a pixel signal according to the amount of charge held in the node FD.

[0030] Each of the column circuits 32 that make up the readout circuit 30 may be configured to include, for example, as shown in FIG. 3, a reference signal output circuit 36, a comparator 52, and a memory 60. The reference signal output circuit 36 includes an amplification circuit. For example, the reference signal output circuit 36 may be configured to include an amplification transistor M5 and a selection transistor M6. The comparator 52 is configured by, for example, a differential amplification circuit and has two input nodes and one output node. The memory 60 has three input nodes and one output node. In this specification, the reference signal output circuits 36 of the plurality of column circuits 32 that make up the readout circuit 30 may sometimes be collectively referred to as the reference signal output unit 40.

[0031] The drain of the amplification transistor M5 is connected to the node to which the power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M5 is connected to the drain of the selection transistor M6. The source of the selection transistor M6 is connected to the signal output line 16. The reference signal VREF is supplied from the reference signal output circuit 34 to the gate of the amplification transistor M5. The control signal SEL_REF is supplied from the timing generation unit 90 to the gate of the selection transistor M6.

[0032] When the selection transistor M6 is turned on, it connects the amplification transistor M5 to the signal output line 16. The amplification transistor M5 is configured such that a voltage VDD is supplied to the drain and a bias current is supplied from the current source 18 to the source via the selection transistor M6, and it constitutes an amplification unit (source follower circuit) having the gate as the input node. As a result, the amplification transistor M5 outputs a signal based on the potential of the reference signal VREF to the signal output line 16 via the selection transistor M6.

[0033] The first input node of the comparator 52 (for example, the inverting input node (-) of the differential amplification circuit) is connected to the corresponding signal output line 16. The second input node of the comparator 52 (for example, the non-inverting input node (+) of the differential amplification circuit) is connected to the reference signal output circuit 48 via the reference signal line 50. The output node of the comparator 52 is connected to the first input node of the memory 60. The second input node of the memory 60 is connected to the counter circuit 56 via the count signal line 58. The third input node of the memory 60 is connected to the horizontal scanning circuit 70. The output node of the memory 60 is connected to the signal processing circuit 80 via the horizontal output line 62.

[0034] The comparator 52 compares the level of the voltage vl on the signal output line 16 with the level of the reference signal rmp output from the reference signal line 50, and outputs a signal according to the result of the comparison. For example, the comparator 52 outputs a high-level signal when the level of the reference signal rmp is lower than the level of the voltage vl. Also, the comparator 52 outputs a low-level signal when the level of the reference signal rmp is higher than the level of the voltage vl. Note that the relationship between the magnitude relationship of the input signal and the level of the output signal may be reversed.

[0035] The memory 60 holds, as digital data of the pixel signal, the count value indicated by the count signal COUNT output from the counter circuit 56 at the timing when the signal level of the output node of the comparator 52 is inverted. The digital data held in the memory 60 is sequentially transferred to the signal processing circuit 80 via the horizontal output line 62 for each column according to the control signal from the horizontal scanning circuit 70.

[0036] The photoelectric conversion device 100 of this embodiment is configured as a stacked photoelectric conversion device in which the above-described functional blocks are formed separately on a plurality of substrates, and these substrates are bonded together and electrically connected. FIG. 4 is a schematic diagram when the pixel substrate 110 and the signal processing substrate 140 are stacked to form the photoelectric conversion device 100. By arranging the pixel array unit 10 on a substrate different from other functional blocks, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of the pixel array unit 10.

[0037] On the pixel substrate 110, for example, the pixel array unit 10 and the reference signal output unit 40 can be arranged. On the signal processing substrate 140, for example, the current source 18, the vertical scanning circuit 20, the reference signal output circuit 34, the reference signal output circuit 48, the comparator 52, the counter circuit 56, the memory 60, the horizontal scanning circuit 70, the signal processing circuit 80, and the timing generation unit 90 can be arranged.

[0038] The pixels 12 and the reference signal output circuit 36 arranged on the pixel substrate 110 and the current source 18 and the comparator 52 arranged on the signal processing substrate 140 are electrically connected via the connection portion 112. The node including this connection portion 112 corresponds to the signal output line 16. Also, the reference signal output unit 40 arranged on the pixel substrate 110 and the reference signal output circuit 34 arranged on the signal processing substrate 140 are electrically connected via the connection portion 114.

[0039] Pad regions 82 are provided at the edges of each of the pixel substrate 110 and the signal processing substrate 140. A plurality of pad electrodes 84 are provided in the pad region 82 of the signal processing substrate 140. A plurality of pad openings 86 penetrating the pixel substrate 110 are provided in the pad region 82 of the pixel substrate 110. Each of the plurality of pad openings 86 is provided such that when the pixel substrate 110 is laminated on the signal processing substrate 140, the pad electrodes 84 of the signal processing substrate 140 are exposed inside thereof. Wiring for supplying power from an external device to the photoelectric conversion device 100 and for inputting and outputting signals between them is connected to the pad electrodes 84 through the pad openings 86 using, for example, wire bonding technology. Further, an output circuit for outputting a signal from the signal processing circuit 80 to the outside of the photoelectric conversion device 100, an ESD (Electro-Static Discharge) protection circuit (both not shown), etc. may be provided in the pad region 82.

[0040] In the configuration example of FIG. 4, the pad electrodes 84 are provided on the signal processing substrate 140. However, for example, as in the configuration example shown in FIG. 5, the pad electrodes 84 may be provided on the pixel substrate 110 side. In this case, for example, an output signal from the signal processing circuit 80 arranged on the signal processing substrate 140 can be transmitted to the pixel substrate 110 via the connection portion 116 and output from the pad electrodes 84 arranged on the pixel substrate 110. Regarding the connection with other pad electrodes 84, the electrical paths of the power supply and signals used on the signal processing substrate 140 can be provided in the same manner.

[0041] Two configuration examples of the connection portions 112, 114, 116 will be described below. FIG. 6 is a configuration example when the signal processing substrate 140 is bonded face-to-face to the pixel substrate 110, and FIG. 7 is a configuration example when the signal processing substrate 140 is bonded face-to-back to the pixel substrate 110. However, the configurations of the connection portions 112, 114, 116 are not limited to these.

[0042] In FIG. 6, the pixel substrate 110 includes a semiconductor substrate 120 having a first surface 122 and a second surface 124, and a wiring structure layer 130 disposed on the side of the first surface 122 of the semiconductor substrate 120. On the first surface 122 of the semiconductor substrate 120, a pixel array portion 10 including a plurality of pixels 12 and a reference signal output circuit 36 are provided. The wiring structure layer 130 includes a plurality of wiring layers disposed in an insulating layer 132. A predetermined circuit constituting the pixel array portion 10 and the reference signal output circuit 36 is configured by these plurality of wiring layers. Among the wiring layers constituting the wiring structure layer 130, the uppermost wiring layer farthest from the semiconductor substrate 120 is a Cu wiring layer 134.

[0043] The signal processing substrate 140 includes a semiconductor substrate 150 having a first surface 152 and a second surface 154, and a wiring structure layer 160 disposed on the side of the first surface 152 of the semiconductor substrate 150. On the first surface 152 of the semiconductor substrate 150, in addition to the reference signal output circuit 34, predetermined functional blocks excluding the pixel array portion 10 and the reference signal output circuit 36 are provided. The wiring structure layer 160 includes a plurality of wiring layers disposed in an insulating layer 162. A predetermined circuit and pad electrodes 84 constituting the predetermined functional blocks are configured by these plurality of wiring layers. Among the wiring layers constituting the wiring structure layer 160, the uppermost wiring layer farthest from the semiconductor substrate 150 is a Cu wiring layer 164.

[0044] The pixel substrate 110 and the signal processing substrate 140 are face-to-face joined such that the side of the first surface 122 of the semiconductor substrate 120 faces the side of the first surface 152 of the semiconductor substrate 150. The Cu wiring layer 134 and the Cu wiring layer 164 located at the joint between the pixel substrate 110 and the signal processing substrate 140 form a metal joint (Cu-Cu joint) between the metals constituting these metal wirings. This metal joint constitutes connection portions 112, 114 (and a connection portion 116 not shown) that electrically connect the pixel substrate 110 and the signal processing substrate 140. Note that the metal material constituting the connection portions 112, 114 is not limited to Cu (copper), and may be, for example, Au (gold).

[0045] On the side of the second surface 124 of the semiconductor substrate 120, an optical structure layer 170 including a color filter CF, a planarization layer 172, and a microlens ML is provided. That is, the configuration example in FIG. 6 is a backside illumination (BSI) type photoelectric conversion device that receives light incident from the side of the back surface (second surface 124) opposite to the front surface (first surface 122) of the semiconductor substrate 120 on which the photoelectric conversion element PD is disposed. The optical structure layer 170, the pixel substrate 110, and the insulating layer 162 are provided with pad openings 86 that penetrate these and reach the pad electrodes 84.

[0046] In FIG. 7, the pixel substrate 110 includes a semiconductor substrate 120 having a first surface 122 and a second surface 124, and a wiring structure layer 130 disposed on the side of the first surface 122 of the semiconductor substrate 120. On the first surface 122 of the semiconductor substrate 120, a pixel array portion 10 including a plurality of pixels 12 and a reference signal output circuit 36 are provided. The wiring structure layer 130 includes a plurality of wiring layers disposed in the insulating layer 132. A predetermined circuit constituting the pixel array portion 10 and the reference signal output circuit 36 is configured by these plurality of wiring layers. Further, the pixel substrate 110 is provided with a through electrode 136 that penetrates the semiconductor substrate 120 and the insulating layer from the side of the second surface 124 of the semiconductor substrate 120 and reaches a predetermined wiring layer of the wiring structure layer 130. Such an electrode provided through the semiconductor substrate is called a TSV (Through Silicon Via).

[0047] The signal processing substrate 140 includes a semiconductor substrate 150 having a first surface 152 and a second surface 154, and a wiring structure layer 160 disposed on the side of the first surface 152 of the semiconductor substrate 150. On the first surface 152 of the semiconductor substrate 150, in addition to the reference signal output circuit 34, predetermined functional blocks excluding the pixel array portion 10 and the reference signal output circuit 36 are provided. The wiring structure layer 160 includes a plurality of wiring layers disposed in the insulating layer 162. A predetermined circuit and pad electrodes 84 constituting the predetermined functional blocks are configured by these plurality of wiring layers. Among the wiring layers constituting the wiring structure layer 160, the uppermost wiring layer farthest from the semiconductor substrate 150 is the wiring layer 166.

[0048] The pixel substrate 110 and the signal processing substrate 140 are face-to-back bonded such that the side of the second surface 124 of the semiconductor substrate 120 faces the side of the first surface 152 of the semiconductor substrate 150. The joint portion between the through electrode 136 and the wiring layer 166 located at the joint of the pixel substrate 110 and the signal processing substrate 140 constitutes connection portions 112, 114 (and a connection portion 116 not shown) that electrically connect the pixel substrate 110 and the signal processing substrate 140.

[0049] On the side of the wiring structure layer 130 opposite to the semiconductor substrate 120, an optical structure layer 170 including a color filter CF, a planarization layer 172, and a microlens ML is provided. That is, the configuration example in FIG. 6 is a surface illumination (FSI (Frontside illumination)) type photoelectric conversion device that receives light incident from the front side (first surface 122) of the semiconductor substrate 120 on which the photoelectric conversion element PD is arranged. The optical structure layer 170, the pixel substrate 110, and the insulating layer 162 are provided with pad openings 86 that penetrate these and reach the pad electrode 84.

[0050] As described above, in a stacked image sensor, the image quality and the operation speed may deteriorate due to a difference in non-linearity of the circuit according to a difference in characteristics between the transistors of the pixel substrate and the transistors of the signal processing substrate with different process technologies.

[0051] First, considering the correlation with the signal processing circuit, it is preferable to generate the correction value for correcting the gain error within the signal processing substrate. However, if the gain correction value etc. are calculated only based on the column circuit and the reference signal on the signal processing substrate without considering the non-linearity according to the characteristics of the source follower or the selection transistor of the pixel, a deviation from the actual characteristics due to not considering the pixel components becomes a correction error, which is a factor in image quality degradation.

[0052] In addition, various characteristics of transistors represented by the threshold voltage vary independently of each other due to manufacturing variations in the pixel substrate and the signal processing substrate. As a result, the linkage between the voltage level of the clip circuit for limiting the signal amplitude of the pixel output and the reset level of the pixel decreases. This requires the allocation of margins considering the amount of variation in each operating point, squeezing the output voltage range of the pixel.

[0053] Furthermore, when a configuration is adopted in which a signal for calculating a correction value for gain error correction is generated only by a circuit on the signal processing substrate, the voltage shift when switching from the pixel output to the output of the signal processing substrate becomes a factor in reducing the responsiveness and also hinders high-speed operation.

[0054] On the other hand, in the photoelectric conversion device 100 of the present embodiment, the pixel array unit 10 and the reference signal output unit 40 are arranged on a common pixel substrate 110, and the reference signal output circuit 34 and the reference signal output circuit 48 are arranged on a common signal processing substrate 140. As a result, it is possible to improve the correction value accuracy and linearity by improving the correlation with the pixel characteristics, improve the gain error correction accuracy, and minimize the unnecessary operation margin and voltage shift associated with the operating point shift based on the device characteristic differences, enabling operation range optimization and high-speed operation. Hereinafter, these will be described in more detail while explaining the operation of the photoelectric conversion device 100. For the sake of simplicity of explanation, here, as the reference signal rmp, a ramp signal whose signal level monotonically increases or decreases with the passage of time is assumed.

[0055] The pixel signal output from the pixels 12 in the row selected by the control signal from the vertical scanning circuit 20 is input to the comparator 52 via the signal output line 16. At this time, the reference signal rmp compared with the pixel signal in the comparator 52 can have its slope (rate of change with time) controlled in the reference signal output circuit 48. The quantization unit, which is the voltage value per 1LSB, is determined by the relationship between the slope of this reference signal rmp and the count frequency in the counter circuit 56. Therefore, fixing the count frequency and reducing (smoothing) the slope of the reference signal rmp has the same effect as increasing the gain.

[0056] Here, the reference signal rmp is a common signal supplied to the comparator 52 of each column circuit 32 via the reference signal line 50. However, since the comparator 52 is provided for each column circuit 32 as a physically independent circuit, it is impossible to completely eliminate the influence on the characteristics due to manufacturing variations, and a certain relative variation may occur for each column circuit 32. This is the same for the gain characteristics described above. Therefore, the signal acquired by the photoelectric conversion device 100 is output after correcting the gain variation for each column circuit 32 in the signal processing circuit 80.

[0057] The correction value used in the correction process in the signal processing circuit 80 can be acquired, for example, in a correction value acquisition phase different from the imaging phase for acquiring an image. For example, this correction value can be calculated by acquiring the output of the column circuit 32 based on the reference signal VREF output by the reference signal output circuit 34 in the correction value acquisition phase. This reference signal VREF is preferably adjustable according to the reference signal rmp so that an appropriate amplitude can be set according to the slope of the reference signal rmp, and it is better to have a higher correlation with the reference signal rmp. Therefore, it is preferable to provide the reference signal output circuit 34 on the same signal processing substrate 140 as the reference signal output circuit 48 so that the same manufacturing variations are imposed.

[0058] On the other hand, it is preferable that the circuit elements of the reference signal output circuit 36, particularly the amplification transistor M5, have the same characteristics as the amplification transistor M3 of the pixel 12, and the transistor size (such as gate length L and gate width W) and layout shape are aligned with those of the amplification transistor M3. From such a perspective, it is preferable that the reference signal output circuit 36 (reference signal output unit 40) is provided on the same pixel substrate 110 as the pixel array unit 10. By configuring the reference signal output circuit 36 in this way, it becomes possible to transmit a signal based on the reference signal VREF to the subsequent comparator 52 through a circuit that mimics the input-output characteristics of the pixel source follower represented by gain and linearity. As a result, it is possible to obtain a correction value calculation signal highly correlated with the pixel signal in the imaging phase, taking into account the pixel characteristics, and improve the correction accuracy of the gain error superimposed on the output signal of the column circuit 32 to obtain a high-quality image signal. However, the present disclosure is not limited to this form, and the reference signal output circuit 36 may be provided with an operational amplifier or a voltage follower instead of the amplification transistor M5. Further, the reference signal output circuit 36 may be provided with an attenuator instead of the amplification transistor M5. Further, the reference signal output circuit 36 may be configured as a switch that switches whether to output the reference signal to the signal output line. In any of these forms, the reference signal output circuit 36 is a circuit that outputs a signal based on the input reference signal.

[0059] From such a perspective, in the photoelectric conversion device 100 of the present embodiment, the reference signal VREF output from the reference signal output circuit 34 arranged on the signal processing substrate 140 is supplied to the reference signal output circuit 36 arranged on the pixel substrate 110 via the connection portion 112.

[0060] In a CMOS image sensor, in order to reduce offset noise generated in pixel 12, reference signal output circuit 36, and comparator 52, it is common to perform noise reduction processing called CDS (Correlated Double Sampling). This CDS processing is a signal processing that reduces noise components commonly included in these two signals by subtracting the reference level from the signal level. Therefore, it is preferable that the reference signal output circuit 34 is configured to be transiently transitionable between two or more potentials including the reference level and the signal level for the CDS processing.

[0061] However, the reference signal VREF output by the reference signal output circuit 34 does not necessarily have to be a single signal capable of transient transition. For example, as the reference signal VREF, two or more DC signals corresponding to the reference level and the signal level for use in the CDS processing may be prepared, and the signal input to the amplification transistor M5 of the reference signal output circuit 36 may be switched according to the operation phase.

[0062] Also, in this embodiment, the description has centered on gain correction in the signal processing circuit 80, but the present invention is not limited to this. For example, data based on the obtained reference signal may be used for linearity correction or the like.

[0063] Also, in this embodiment, the description has been made on the premise that the reference signal VREF is a signal serving as a basis for calculating the gain correction value. However, the use of the reference signal VREF is not limited to this. For example, the reference signal VREF can also be used for the purpose of limiting the voltage operation amplitude of the signal output line 16 from which the pixel signal is output. In this case, during the correction value acquisition phase, the operation of the reference signal output unit 40 is not limited, and during the imaging phase, the control signal SEL_REF is controlled to a high level to turn on the selection transistor M6. By doing so, when the potential of the node FD becomes lower than the potential of the reference signal VREF, it becomes possible to use it as a clip circuit that clips the potential of the signal output line 16 to the potential based on the reference signal VREF. At this time, since the amplification transistor M5 for clipping has a high correlation with the amplification transistor M3 of the pixel 12 with respect to the influence due to manufacturing variations such as the threshold voltage, an efficient operation range design becomes possible.

[0064] As described above, according to this embodiment, in the photoelectric conversion device configured by bonding the pixel substrate and the signal processing substrate, the image quality and the operation speed can be improved.

[0065] In the configuration examples of FIGS. 4 and 5, the reference signal VREF is supplied from the reference signal output circuit 34 to the reference signal output unit 40 via one connection part 114. However, the reference signal VREF may be supplied from the reference signal output circuit 34 to the reference signal output unit 40 via a plurality of connection parts 114. Alternatively, for example, as shown in FIG. 8, a plurality of reference signal output circuits 34 may be provided on the signal processing substrate 140, and the reference signal VREF may be supplied from these plurality of reference signal output circuits 34 to the reference signal output unit 40 via a plurality of connection parts 114. By configuring in this way, the responsiveness of the reference signal VREF is improved, which is advantageous from the viewpoint of speeding up.

[0066] [Second Embodiment] The photoelectric conversion device and its driving method according to the second embodiment of the present invention will be described with reference to FIGS. 9 and 10. The same components as those of the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. FIG. 9 is a schematic diagram showing a configuration example of the photoelectric conversion device according to the present embodiment. FIG. 10 is a timing diagram showing the driving method of the photoelectric conversion device according to the present embodiment.

[0067] The photoelectric conversion device 100 according to the present embodiment is the same as the photoelectric conversion device according to the first embodiment, except that the configurations of the reference signal output circuit 48 and the column circuit 32 are different. In the present embodiment, the description will be centered on the points different from the photoelectric conversion device according to the first embodiment, and the description of the same points as those of the photoelectric conversion device according to the first embodiment will be omitted as appropriate.

[0068] The photoelectric conversion device 100 according to the first embodiment has one reference signal output circuit 48. In contrast, the photoelectric conversion device 100 according to the present embodiment has a reference signal output circuit 48L and a reference signal output circuit 48H, as shown in FIG. 9. The reference signal output circuit 48L and the reference signal output circuit 48H have different degrees of change in the signal level of the output reference signal rmp. Assuming a ramp signal as the reference signal rmp, the slope of the reference signal rmph output by the reference signal output circuit 48H is larger (steeper) than the slope of the reference signal rmpl output by the reference signal output circuit 48L. Here, the reference signal rmpl is a reference signal used for low-luminance pixel signals, and since the slope is small, high-gain AD conversion is possible. The reference signal rmph is a reference signal used for high-luminance pixel signals, and since the slope is large, low-gain AD conversion is possible.

[0069] Also, each column circuit 32 of the photoelectric conversion device 100 according to the present embodiment further includes switches SW1 and SW2, and a determination unit 54, in addition to a reference signal output circuit 36, a comparator 52, and a memory 60. The switches SW1 and SW2 serve as a reference signal selection circuit. The switch SW1 is connected between the reference signal output circuit 48L and the comparator 52. The switch SW2 is connected between the reference signal output circuit 48H and the comparator 52. The determination unit 54 is connected to the output node of the comparator 52, and has a role of controlling one of the switches SW1 and SW2 to be on and the other to be off according to the output signal of the comparator 52 and the control by the timing generation unit 90. Here, it is assumed that when the determination signal jdg output from the determination unit 54 is at a low level, the switch SW1 is on, the switch SW2 is off, and the reference signal rmpl is selected. Also, when the determination signal jdg output from the determination unit 54 is at a high level, the switch SW1 is off, the switch SW2 is on, and the reference signal rmph is selected. The determination signal jdg output from the determination unit 54 can also be forcibly set by the timing generation unit 90 or the like. By switching the slope of the reference signal rmp according to the amplitude of the optical signal output from the pixel 12, it is possible to achieve high-speed and high-dynamic-range AD conversion.

[0070] Next, a driving method of the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 10. FIG. 10 shows waveforms of control signals RES, TX, SEL, SEL_REF, the voltage vl of the signal output line 16, reference signals rmpl and rmph, the reference signal cmpi_rmp input to the comparator 52, the output signal cmpo of the comparator 52, and the determination signal jdg. Here, the signs attached to the control signals RES, TX, and SEL <m>represents the line number and is appended to the signs of the voltage vl, the reference signal cmpi_rmp, the output signal cmpo, and the determination signal jdg <n>represents the column number. FIG. 10 shows the operation of reading out signals from the pixel 12 arranged in the m-th row and the n-th column of the pixel array unit 10.

[0071] The operation shown in FIG. 10 is roughly divided into a correction value acquisition phase and an imaging phase. In the correction value acquisition phase, gain information based on the reference signal rmpl and gain information based on the reference signal rmph are respectively acquired based on the reference signal VREF. In the imaging phase, processing for the output signal from the pixel 12 is performed based on the acquired gain information.

[0072] The period from time t1 to time t9 is a correction value acquisition phase for acquiring gain information based on the reference signal rmpl for low-luminance signals. Immediately before time t1, the control signal RES <m>,TX <m>,SEL <m>, Assume that the SEL_REF and the determination signal jdg are at a low level.

[0073] At time t1, the timing generation unit 90 controls the control signal SEL_REF from a low level to a high level. As a result, the selection transistor M6 of the reference signal output circuit 36 in each column is turned on, and the signal (voltage vl) generated by the amplification transistor M5 based on the reference signal VREF is output to the signal output line 16 via the selection transistor M6.

[0074] In the correction value acquisition phase of the low-luminance signal, the reference signal VREF is controlled to a level corresponding to the reset level and a level corresponding to the optical amplitude. At time t1, the reference signal VREF is at a level corresponding to the reset level. The level corresponding to the optical amplitude is preferably set to the switching level between the reference signal rmpl and the reference signal rmph (hereinafter referred to as the "luminance switching level"). The comparator 52 receives the signal (reference signal cmpi_rmp) selected by the reference signal selection circuit (switches SW1 and SW2) according to the determination signal jdg from among the reference signal rmpl and the reference signal rmph.

[0075] After the voltage vl of the signal output line 16 settles to a potential corresponding to the reset level, the comparator 52 performs a comparison operation between the level of the voltage vl and the reference signal cmpi_rmp in a state where the reference signal rmpl is selected according to the low-level determination signal jdg. As a result, assume that at time t2, the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be NREF_L1.

[0076] At a subsequent time t3, the timing generation unit 90 forcibly controls the determination signal jdg output by the determination unit 54 to a high level. The comparator 52 performs a comparison operation between the level of the voltage vl and the reference signal cmpi_rmp in a state where the reference signal rmph is selected according to the high-level determination signal jdg. As a result, it is assumed that at time t4, the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be NREF_H1.

[0077] At a subsequent time t5, the timing generation unit 90 releases the forced control of the determination signal jdg output by the determination unit 54 to a high level and returns the determination signal jdg to a low level. Also, the reference signal output circuit 34 switches the reference signal VREF from a level corresponding to the reset level to a level corresponding to the optical amplitude.

[0078] During the period from time t6 to time t7 after the voltage vl on the signal output line 16 transitions to a level corresponding to the optical amplitude, the reference signal output circuit 48L outputs a signal of a constant level corresponding to the luminance switching level as the reference signal rmpl. The reference signal selection circuit (switches SW1, SW2) selects this constant-level reference signal rmpl according to the low-level determination signal jdg. The comparator 52 performs a comparison operation between the level of the voltage vl and the constant-level reference signal cmpi_rmp. Note that since the determination here is ignored in the correction value acquisition phase, it is not necessary to perform the above operation with the reference signal rmp, but from the viewpoint of the responsiveness of the reference signal rmp, it is preferable to align the imaging phase and the transient operation.

[0079] Thereafter, the reference signal output circuit 48L releases the level fixing of the reference signal rmpl and starts the temporal change of the signal level from the reference voltage of the reference signal rmpl. The comparator 52 performs a comparison operation between the voltage vl corresponding to the optical amplitude level and the reference signal cmpi_rmp in a state where the reference signal rmpl is selected according to the low-level determination signal jdg. At time t8, when the output signal cmpo of the comparator 52 is inverted (transitions to a high level), the memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be SREF_L.

[0080] The subsequent signal processing circuit 80 can obtain a signal value for calculating the gain correction value of the low-luminance signal by taking the difference between the count value SREF_L and the count value NREF_L1 (hereinafter, referred to as the count value REF_L).

[0081] The period from the subsequent time t9 to time t16 is a correction value acquisition phase for acquiring gain information based on the reference signal rmph for the high-luminance signal. At time t9, the control signal RES <m>,TX <m>,SEL <m>The determination signal jdg is at a low level, and the control signal SEL_REF is at a high level.

[0082] Even in the correction value acquisition phase of the high-brightness signal, the reference signal VREF is controlled to a level corresponding to the reset level and a level corresponding to the optical amplitude. At time t9, the reference signal VREF is at a level corresponding to the reset level. Also, the control signal SEL_REF is at a high level, and similar to the period from time t1 to time t8, on the signal output line 16, a voltage corresponding to the reset level and a voltage corresponding to the optical amplitude level are output based on the reference signal VREF. To the comparator 52, a signal (reference signal cmpi_rmp) selected by the reference signal selection circuit (switches SW1, SW2) according to the determination signal jdg among the reference signals rmpl and rmph is input.

[0083] After the voltage vl on the signal output line 16 stabilizes at a potential corresponding to the reset level, the comparator 52 performs a comparison operation between the level of the voltage vl and the reference signal cmpi_rmp in a state where the reference signal rmpl is selected according to the low-level determination signal jdg. As a result, at time t10, the output signal cmpo of the comparator 52 changes (transitions to a high level).

[0084] At the subsequent time t11, the timing generation unit 90 forcibly controls the determination signal jdg output by the determination unit 54 to a high level. Thereby, the reference signal rmph is selected as the reference signal cmpi_rmp.

[0085] Next, the comparator 52 performs a comparison operation between the level of the voltage vl and the reference signal cmpi_rmp in a state where the reference signal rmph is selected according to the high-level determination signal jdg. As a result, assume that at time t12, the output signal cmpo of the comparator 52 changes (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo changes. Let the count value at this time be NREF_H2.

[0086] At a subsequent time t13, the timing generation unit 90 releases the control of the determination signal jdg output by the determination unit 54 to a forced high level and returns the determination signal jdg to a low level. Further, the reference signal output circuit 34 switches the reference signal VREF from a level corresponding to the reset level to a level corresponding to the optical amplitude.

[0087] At a time t14 after the voltage vl on the signal output line 16 has transitioned to a level corresponding to the optical amplitude, the timing generation unit 90 forcibly controls the determination signal jdg output by the determination unit 54 to a high level. As a result, the reference signal rmph is selected as the reference signal cmpi_rmp.

[0088] Next, the comparator 52 performs a comparison operation between the voltage vl corresponding to the optical amplitude level and the reference signal cmpi_rmp in a state where the reference signal rmph is selected. When the output signal cmpo of the comparator 52 is inverted (transitions to a high level) at time t15, the memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be SREF_H.

[0089] The subsequent signal processing circuit 80 can obtain a signal value for calculating the gain correction value of the high-brightness signal by taking the difference between the count value SREF_H and the count value NREF_H2 (hereinafter referred to as the count value REF_H).

[0090] By calculating the ratio (REF_L / REF_H) of the count values REF_L and REF_H thus obtained, it is possible to accurately obtain the ratio of the slopes of the reference signals rmpl and rmph including the effects of manufacturing variations, temperature, power supply voltage, pixel characteristics, etc. In the imaging phase described later, when synthesizing a low-gain high-brightness signal to be aligned with a high-gain low-brightness signal in the same quantization unit, gain correction is performed using the above ratio (REF_L / REF_H). As a result, it is possible to obtain good signal characteristics with high linearity and small fluctuations at the luminance switching level.

[0091] The period from the subsequent time t16 to time t26 is the imaging phase. Immediately before time t16, the control signal RES <m>,TX <m>,SEL <m>The determination signal jdg is at a low level. Also, the control signal SEL_REF is controlled to a low level by the timing generation unit 90 after the end of the correction value acquisition phase.

[0092] At time t16, the vertical scanning circuit 20 controls the SEL of the m-th row to be read <m>Control it at a high level. As a result, the selection transistor M4 of the pixel 12 belonging to the row is turned on, and the signal output lines 16 of each column are in a state where a signal corresponding to the potential of the node FD of the corresponding pixel 12 can be output.

[0093] During the period from time t16 to subsequent time t17, the vertical scanning circuit 20 controls the signal RES of the row to be read <m>Control it at a high level. As a result, the reset transistor M2 of the pixel 12 belonging to the row is turned on, and the node FD becomes a reset potential according to the voltage VDD. The voltage vl of the signal output line 16 becomes a potential according to the reset potential of the node FD. At time t17, the control signal RES <m>After the transition to the low level, the voltage vl of the static signal output line 16 is the pixel reset level.

[0094] Next, the comparator 52 performs a comparison operation between the voltage vl (pixel reset level) and the reference signal cmpi_rmp with the reference signal rmpl selected. At time t18, when the output signal cmpo of the comparator 52 flips (transitions to the high level), the memory 60 holds the count value at the timing when the output signal cmpo flips. Let the count value at this time be N_L.

[0095] Next, the comparator 52 performs a comparison operation between the voltage vl (pixel reset level) and the reference signal cmpi_rmp with the reference signal rmph selected. At time t19, when the output signal cmpo of the comparator 52 flips (transitions to the high level), the memory 60 holds the count value at the timing when the output signal cmpo flips. Let the count value at this time be N_H.

[0096] During the subsequent period from time t20 to time t21, the vertical scanning circuit 20 controls the signal TX of the m-th row to be read. <m>Control it at a high level. As a result, the transfer transistor M1 of the pixel 12 belonging to the line is turned on, and the charge accumulated in the photoelectric conversion element PD is transferred to the node FD. The voltage vl of the signal output line 16 becomes a potential corresponding to the amount of charge transferred to the node FD. At time t21, the control signal TX <m>After transitioning to the low level, the voltage vl of the static signal output line 16 is the optical amplitude level.

[0097] After the voltage vl of the signal output line 16 has stabilized, during the period from time t22 to time t23, the reference signal output circuit 48L outputs, as the reference signal rmpl, a signal of a constant level corresponding to the luminance switching level. The reference signal selection circuit (switches SW1, SW2) selects this reference signal rmpl, and the comparator 52 performs a comparison operation between the voltage vl of the signal output line 16 and the reference signal rmpl.

[0098] If the output signal cmpo does not invert as a result of the comparison operation, that is, if it is determined to be high brightness, then as indicated by the dashed-dotted line, the determination signal jdg becomes high level and the reference signal rmph is selected. Thereafter, the reference signal output circuit 48H starts the time-dependent change of the signal level from the reference voltage of the reference signal rmph. The comparator 52 performs a comparison operation between the voltage vl corresponding to the optical amplitude level and the reference signal cmpi_rmp in a state where the reference signal rmph is selected in response to the high-level determination signal jdg. At time t24, when the output signal cmpo of the comparator 52 inverts (transitions to high level), the memory 60 holds the count value at the timing when the output signal cmpo inverts. Let the count value at this time be S_H.

[0099] If the output signal cmpo inverts as a result of the comparison operation, that is, if it is determined to be low brightness, then as indicated by the solid line, the determination signal jdg becomes low level and the reference signal rmpl is selected. Thereafter, the reference signal output circuit 48L releases the level fixation of the reference signal rmpl and starts the time-dependent change of the signal level from the reference voltage of the reference signal rmpl. The comparator 52 performs a comparison operation between the voltage vl corresponding to the optical amplitude level and the reference signal cmpi_rmp in a state where the reference signal rmpl is selected in response to the low-level determination signal jdg. At time t25, when the output signal cmpo of the comparator 52 inverts (transitions to high level), the memory 60 holds the count value at the timing when the output signal cmpo inverts. Let the count value at this time be S_L.

[0100] During the period from time t22 to time t23, the level of the output signal cmpo is held in the memory 60 as information indicating whether the optical amplitude count value obtained in the imaging phase is of low luminance or high luminance, and is transferred to the signal processing circuit 80 together with each obtained count value. When it is determined that the optical amplitude level is low luminance, the signal processing circuit 80 uses the difference value between the count value S_L and the count value N_L as pixel data. Further, when it is determined that the optical amplitude level is high luminance, the signal processing circuit 80 uses, as pixel data, a value obtained by integrating the difference value between the count value S_H and the count value N_H with the above ratio (REF_L / REF_H) as a coefficient. Thereby, high-precision gain correction processing including pixel characteristics becomes possible.

[0101] In the present embodiment, a method of obtaining count values based on the reset level with respect to the reference signals rmpl and rmph has been described, but the present invention is not limited thereto. For example, the count value based on the reset level may be signal-processed only with the value based on the reference signal rmpl, and the count value corresponding to the reset level based on the reference signal ramph may be obtained at a timing different from the signal processing of the pixels in the imaging phase and used.

[0102] As described above, according to the present embodiment, in the photoelectric conversion device configured by bonding the pixel substrate and the signal processing substrate, the image quality and the operation speed can be improved.

[0103] [Third Embodiment] The photoelectric conversion device and its driving method according to the third embodiment of the present invention will be described with reference to FIGS. 11 to 13. The same components as those of the photoelectric conversion device according to the first or second embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. FIG. 11 is a schematic diagram showing a configuration example of the photoelectric conversion device according to the present embodiment. FIG. 12 is a circuit diagram showing a configuration example of the column amplifier of the photoelectric conversion device according to the present embodiment. FIG. 13 is a timing diagram showing the driving method of the photoelectric conversion device according to the present embodiment.

[0104] The photoelectric conversion device 100 according to the present embodiment is the same as the photoelectric conversion device according to the first embodiment, except that the configuration of the column circuit 32 is different. In the present embodiment, the description will focus on the points different from the photoelectric conversion device according to the first embodiment, and the description of the same points as the photoelectric conversion device according to the first embodiment will be omitted as appropriate.

[0105] As shown in FIG. 11, each column circuit 32 of the photoelectric conversion device 100 according to the present embodiment further includes a column amplifier 42 and a determination unit 46 in addition to the reference signal output circuit 36, the comparator 52, and the memory 60. The column amplifier 42 can be composed of, for example, an operational amplifier 44, an input capacitor C0, feedback capacitors Cf1 and Cf2, and switches SW3 and SW4 as shown in FIG. 12.

[0106] The signal output line 16 is connected to one terminal of the input capacitor C0 which is also the input node of the column amplifier 42. The other terminal of the input capacitor C0 is connected to one terminal of the switch SW3, one terminal of the feedback capacitor Cf1, one terminal of the Cf2, and the inverting input node (-) of the operational amplifier 44. The non-inverting input node (+) of the operational amplifier 44 is connected to the ground voltage node. The other terminal of the feedback capacitor Cf2 is connected to one terminal of the switch SW4. The other terminals of the switch SW3, the switch SW4, and the other terminal of the feedback capacitor Cf1 are connected to the output node of the operational amplifier 44 which is also the output node of the column amplifier 42. The output node of the column amplifier 42 is connected to the first input node of the comparator 52 and the input node of the determination unit 46. The output node of the determination unit 46 is connected to the column amplifier 42 and the memory 60.

[0107] Switch SW3 is the reset switch of column amplifier 42 and is controlled by the control signal pc0r from the timing generation unit 90. That is, when switch SW3 is turned on, the inverting input node and the output node of operational amplifier 44 are connected to form a voltage follower, and the output voltage of operational amplifier 44 is reset to the reference voltage. Switch SW4 is controlled by the determination signal jdg output from the determination unit 46. The determination unit 46 is connected to the output node of the comparator 52 and is configured to output a determination signal jdg according to the output signal of the comparator 52 and the control by the timing generation unit 90. For example, when the output voltage vampo of the column amplifier 42 is equal to or higher than a predetermined voltage value (hereinafter referred to as the luminance switching level), the determination unit 46 determines it as high luminance and outputs a high-level determination signal jdg. Also, when the output voltage vampo of the column amplifier 42 is lower than the luminance switching level, the determination unit 46 determines it as low luminance and outputs a low-level determination signal jdg. The determination signal jdg output by the determination unit 46 can also be forcibly set by the timing generation unit 90 or the like.

[0108] The gain of column amplifier 42 is determined by the ratio of the input capacitance C0 and the feedback capacitances Cf1, Cf2. That is, when the capacitance values of the input capacitance C0 and the feedback capacitances Cf1, Cf2 are represented by the same sign, the gain of the column amplifier when switch SW4 is on is (C0 / (Cf1 + Cf2)). Also, the gain of the column amplifier when switch SW4 is off is (C0 / Cf1). Since the value of (C0 / Cf1) is larger than the value of (C0 / (Cf1 + Cf2)), the column amplifier 42 has a high-gain setting during low-luminance determination and a low-gain setting during high-luminance determination. The column amplifier 42 outputs the output voltage vampo obtained by amplifying the voltage vl of the signal output line 16 with the gain thus set to the comparator 52.

[0109] Next, a method for driving the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 13. FIG. 13 shows waveforms of control signals RES, TX, SEL, SEL_REF, pc0r, the voltage vl of the signal output line 16, the output voltage vampo of the column amplifier 42, the reference signal rmp, the output signal cmpo of the comparator 52, and the determination signal jdg. Here, the signs attached to the control signals RES, TX, SEL are <m>represents the line number and is appended to the signs of the voltage vl, output voltage vampo, output signal cmpo, and determination signal jdg <n>represents the column number. FIG. 13 shows the operation of reading the signal from the pixel 12 arranged in the m-th row and the n-th column of the pixel array section 10. Regarding the parts that overlap with the second embodiment, such as the reference signal VREF, the operation of the pixel 12, and the inversion operation of the comparator 52, the description will be omitted as appropriate.

[0110] The period from time t1 to time t5 is a correction value acquisition phase for acquiring the signal value for calculating the gain correction value of the low-luminance signal. Immediately before time t1, the control signal RES <m>,TX <m>,SEL <m>,SEL_REF,pc0r, it is assumed that the determination signal jdg is at a low level. Note that the times t1 to t17 in FIG. 13 and the times t1 to t26 in FIG. 10 are independent of each other, and even if they are the same time, they do not indicate related operations.

[0111] At time t1, the timing generation unit 90 controls the control signal pc0r from a low level to a high level. Thereby, the column amplifiers 42 of the column circuits 32 in each column are reset. Thereafter, the timing generation unit 90 returns the control signal pc0r from a high level to a low level to release the reset of the column amplifier 42. At this time, the control signal SEL_REF is at a high level, the reference signal VREF is at a level corresponding to the reset level, and a voltage vl corresponding to the reset level is output to the signal output line 16. At this time, the determination signal jdg is set to a low level, and the column amplifier 42 is set to a high gain (C0 / Cf1).

[0112] Next, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the reset level as an input and the reference signal rmp. As a result of the comparison operation, it is assumed that at time t2, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be NREF_L.

[0113] At the subsequent time t3, the reference signal output circuit 34 switches the reference signal VREF from a level corresponding to the reset level to a level corresponding to the optical amplitude. After the voltage vl on the signal output line 16 transitions to a level corresponding to the optical amplitude, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl at the optical amplitude level as the input and the reference signal rmp. As a result of the comparison operation, assuming that at time t4 the level of the reference signal rmp exceeds the level of the output voltage vampo and the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be SREF_L.

[0114] The subsequent signal processing circuit 80 can obtain a signal value for calculating the gain correction value of the low-luminance signal by taking the difference between the count value SREF_L and the count value NREF_L (hereinafter referred to as the count value REF_L).

[0115] The period from time t5 to time t8 is a correction value acquisition phase for obtaining a signal value for calculating the gain correction value of the high-luminance signal. At time t5, the control signal RES <m>,TX <m>,SEL <m>is at a low level, and the control signal SEL_REF is at a high level. The determination signal jdg is controlled from a low level to a high level at time t5.

[0116] At time t5, the timing generation unit 90 controls the control signal pc0r from a low level to a high level. Thereby, the column amplifiers 42 of the column circuits 32 in each column are reset. Thereafter, the timing generation unit 90 returns the control signal pc0r from a high level to a low level to release the reset of the column amplifier 42. At this time, the control signal SEL_REF is at a high level, the reference signal VREF is at a level corresponding to the reset level, and a voltage vl corresponding to the reset level is output to the signal output line 16. At this time, the determination signal jdg is set to a high level, and the column amplifier 42 is set to a low gain (C0 / (Cf1+Cf2)).

[0117] Next, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the reset level as an input and the reference signal rmp. As a result of the comparison operation, it is assumed that at time t6, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be NREF_H.

[0118] Next, the reference signal output circuit 34 switches the reference signal VREF from a level corresponding to the reset level to a level corresponding to the optical amplitude. After the voltage vl of the signal output line 16 transitions to a level corresponding to the optical amplitude, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the optical amplitude level as an input and the reference signal rmp. As a result of the comparison operation, it is assumed that at time t7, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to a high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be SREF_H.

[0119] The subsequent signal processing circuit 80 can obtain a signal value for calculating the gain correction value of the high-brightness signal by taking the difference between the count value SREF_H and the count value NREF_H (hereinafter referred to as the count value REF_H).

[0120] By calculating the ratio (REF_L / REF_H) of the count values REF_L and REF_H thus obtained, the gain ratio of the column amplifier 42 including the effects of manufacturing variations, temperature, power supply voltage, pixel characteristics, etc. can be obtained with high precision. In the imaging phase described later, when synthesizing a low-gain high-brightness signal to have the same charge conversion coefficient as a high-gain low-brightness signal, gain correction is performed using the above ratio (REF_L / REF_H). As a result, good signal characteristics with high linearity and small fluctuations at the brightness switching level can be obtained.

[0121] The period from the subsequent time t8 to time t17 is the imaging phase. Immediately before time t8, the control signal RES <m>,TX <m>,SEL <m>The determination signal jdg is at a low level. Also, the control signal SEL_REF is controlled to a low level by the timing generation unit 90 after the end of the correction value acquisition phase.

[0122] At time t8, the vertical scanning circuit 20 controls the RES signal of the m-th row to be read <m>Control it at a high level. As a result, the reset transistor M2 of the pixel 12 belonging to the line is turned on, and the node FD becomes a reset potential according to the voltage VDD. The voltage vl of the signal output line 16 becomes a potential according to the reset potential of the node FD. Control signal RES <m>After transitioning to the low level, the voltage vl of the static signal output line 16 is the pixel reset level.

[0123] Also at time t8, the timing generation unit 90 controls the control signal pc0r from the low level to the high level. Thereby, the column amplifiers 42 of the column circuits 32 in each column are reset. After that, the timing generation unit 90 returns the control signal pc0r from the high level to the low level to release the reset of the column amplifier 42. At this time, the determination signal jdg is set to the low level, and the column amplifier 42 is set to the high gain (C0 / Cf1).

[0124] Control signal RES <m>After pc0r transitions to the low level, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the pixel reset level as the input and the reference signal rmp. As a result of the comparison operation, assume that at time t10, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to the high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be N_L.

[0125] During the subsequent period from time t11 to time t12, the vertical scanning circuit 20 controls the signal TX of the m-th row to be read <m>Control it at a high level. As a result, the transfer transistor M1 of the pixel 12 belonging to the row is turned on, and the charge accumulated in the photoelectric conversion element PD is transferred to the node FD. The voltage vl of the signal output line 16 becomes a potential corresponding to the amount of charge transferred to the node FD. At time t12, the control signal TX <m>After transitioning to the low level, the voltage vl of the static signal output line 16 is the optical amplitude level.

[0126] During the period from time t13 to time t14 that follows, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the optical amplitude level input and the luminance switching level. As a result of the comparison operation, if it is determined (low luminance determination) that the level of the output voltage vampo is lower than the luminance switching level, the determination signal jdg is set to the low level (solid line in FIG. 13). As a result of the comparison operation, if it is determined (high luminance determination) that the level of the output voltage vampo is higher than the luminance switching level, the determination signal jdg is set to the high level (dashed line in FIG. 13). When the determination signal jdg transitions from the low level to the high level, the column amplifier 42 switches to the low gain setting (C0 / (Cf1 + Cf2)), and the level of the output voltage vampo decreases (dashed-dotted line in FIG. 13).

[0127] Next, the comparator 52 performs a comparison operation between the output voltage vampo of the column amplifier 42 with the voltage vl of the optical amplitude level input and the reference signal rmp.

[0128] Assume that during high luminance determination, as a result of the comparison operation, at time t15, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to the high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be S_H.

[0129] Assume that during low luminance determination, as a result of the comparison operation, at time t16, the level of the reference signal rmp exceeds the level of the output voltage vampo, and the output signal cmpo of the comparator 52 is inverted (transitions to the high level). The memory 60 holds the count value at the timing when the output signal cmpo is inverted. Let the count value at this time be S_L.

[0130] The determination result during the period from time t13 to time t14 is held in the memory 60 as information indicating whether the optical amplitude count value obtained in the imaging phase is of low luminance or high luminance, and is transferred to the signal processing circuit 80 together with each obtained count value. When the signal processing circuit 80 determines that the optical amplitude level is low luminance, it uses the difference value between the count value S_L and the count value N_L as pixel data. Further, when the signal processing circuit 80 determines that the optical amplitude level is high luminance, it uses the value obtained by integrating the difference value between the count value S_H and the count value N_L with the above-mentioned ratio (REF_L / REF_H) as a coefficient as pixel data. Thereby, high-precision gain correction processing including pixel characteristics becomes possible.

[0131] As described above, according to the present embodiment, in the photoelectric conversion device configured by bonding the pixel substrate and the signal processing substrate, the image quality and the operation speed can be improved.

[0132] [Fourth Embodiment] The photoelectric conversion device according to the fourth embodiment of the present invention will be described with reference to FIGS. 14 and 15. The same components as those of the photoelectric conversion device according to the first to third embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified. FIG. 14 is a block diagram showing a schematic configuration of the photoelectric conversion device according to the present embodiment. FIG. 15 is a circuit diagram showing a configuration example of a column circuit of the photoelectric conversion device according to the present embodiment.

[0133] In the first to third embodiments, a photoelectric conversion device in which the AD converter of the column circuit 32 is configured by a ramp type AD converter is shown. In the present embodiment, a photoelectric conversion device in which the AD converter of the column circuit 32 is configured by a ΔΣ type AD converter is shown. The ΔΣ type AD converter is an oversampling type AD converter that performs AD conversion based on the output signal of the pixel circuit. In the photoelectric conversion device using the ΔΣ type AD converter, as shown in FIG. 14, the reference signal output circuit 48 and the counter circuit 56 are unnecessary. Note that the output of the column circuit 32 of each column may be input directly to the signal processing circuit 80 without passing through the horizontal output line 62, for example, as shown in FIG. 14. The same may apply to the case of the first to third embodiments.

[0134] As shown in FIG. 15, the column circuit 32 of the photoelectric conversion device according to this embodiment includes a reference signal output circuit 36, sample-and-hold units 64N and 64S, a resistance element R, and an AD conversion unit 68. The sample-and-hold unit 64N has a function of sample-and-holding a signal corresponding to the pixel reset level based on the reset level signal output from the pixel 12 or the reference potential corresponding to the pixel reset level output from the reference signal output circuit 34. The sample-and-hold unit 64S has a function of sample-and-holding a signal corresponding to the optical amplitude level based on the optical amplitude level signal output from the pixel 12 or the reference potential corresponding to the optical amplitude level output from the reference signal output circuit 34. A resistance element R that generates a current according to the potential difference between the signals held in these is connected between the output unit of the sample-and-hold unit 64N and the output unit of the sample-and-hold unit 64S. The AD conversion unit 68 is a ΔΣ type AD conversion circuit. The reference signal output circuit 36, the sample-and-hold units 64N and 64S, the resistance element R, and the AD conversion unit 68 are respectively provided for each of the signal output lines 16.

[0135] As shown in FIG. 15, for example, the reference signal output circuit 36 can be composed of switches SW5 and SW6, an amplification transistor M5, and a selection transistor M6. A reference signal VREF1 is supplied from the reference signal output circuit 34 to one terminal of the switch SW5. A reference signal VREF2 is supplied from the reference signal output circuit 34 to one terminal of the switch SW6. The other terminal of the switch SW5 and the other terminal of the switch SW6 are connected to the gate of the amplification transistor M5. The drain of the amplification transistor M5 is connected to a node to which the power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M5 is connected to the drain of the selection transistor M6. The source of the selection transistor M6 is connected to the signal output line 16.

[0136] Switch SW5 is a switch driven by control signal REF_1. Switch SW6 is a switch driven by control signal REF_2. These switches SW5 and SW6 turn on when the corresponding control signal is at a high level and turn off when the corresponding control signal is at a low level, for example. In this case, reference signal VREF1 is supplied to the gate of amplification transistor M5 when control signal REF_1 is at a high level, and reference signal VREF2 is supplied when control signal REF_2 is at a high level. Note that reference signal VREF1 is a voltage corresponding to the reset level of pixel 12, and reference signal VREF2 is a voltage corresponding to the optical amplitude level of pixel 12.

[0137] Sample hold section 64N can be constituted by, for example, switches SW8n, SW9n, SW10n, SW11n, capacitor element Csmp_n, inverting amplifier Amp_n, P-type transistor M7n, and current source CSn as shown in FIG. 15. One terminal of switch SW8n is connected to signal output line 16. The other terminal of switch SW8n is connected to one terminal of capacitor element Csmp_n and one terminal of switch SW11n. The other terminal of capacitor element Csmp_n is connected to the input node of inverting amplifier Amp_n. A switch SW9n is connected between the input node and the output node of inverting amplifier Amp_n. The output node of inverting amplifier Amp_n is connected to one terminal of switch SW10n. The other terminal of switch SW10n is connected to the gate of P-type transistor M7n. The drain of P-type transistor M7n is connected to the ground voltage node. The source of P-type transistor M7n is connected to the other terminal of switch SW11n, one terminal of current source CSn, and one terminal of resistor element R. The other terminal of current source CSn is connected to the node to which the power supply voltage (voltage VDD) is supplied.

[0138] Switch SW8n is a switch driven by control signal Smp_n, and when it turns on, it connects signal output line 16 and capacitor element Csmp_n. When a reset signal (or a signal based on a reset level) is output on signal output line 16 and switch SW8n turns on, the reset signal (the signal based on the reset level) is stored in capacitor element Csmp_n. Switch SW9n is a switch driven by control signal Smpa_n, and when it turns on, it connects the input node and the output node of inverting amplifier Amp_n. Switches SW10n and SW11n are switches driven by control signal Hold_s, and when they turn on, they input a signal corresponding to the signal stored in capacitor element Csmp_n to a subsequent source follower circuit composed of P-type transistor M7n and current source CSn. These switches SW8n, SW9n, SW10n, and SW11n turn on, for example, when the corresponding control signal is at a high level and turn off when the corresponding control signal is at a low level.

[0139] Sample hold section 64S can be composed of, for example, switches SW8s, SW9s, SW10s, and SW11s, capacitor element Csmp_s, inverting amplifier Amp_s, P-type transistor M7s, and current source CSs as shown in FIG. 15. One terminal of switch SW8s is connected to signal output line 16. The other terminal of switch SW8s is connected to one terminal of capacitor element Csmp_s and one terminal of switch SW11s. The other terminal of capacitor element Csmp_s is connected to the input node of inverting amplifier Amp_s. A switch SW9s is connected between the input node and the output node of inverting amplifier Amp_s. The output node of inverting amplifier Amp_s is connected to one terminal of switch SW10s. The other terminal of switch SW10s is connected to the gate of P-type transistor M7s. The source of P-type transistor M7s is connected to the other terminal of switch SW11s, one terminal of current source CSs, and the other terminal of resistor element R. The other terminal of current source CSs is connected to a node to which a power supply voltage (voltage VDD) is supplied.

[0140] The switch SW8s is a switch driven by the control signal Smp_s, and when it is turned on, it connects the signal output line 16 and the capacitor element Csmp_s. When an optical signal (or a signal based on the optical amplitude level) is output on the signal output line 16 and the switch SW8s is turned on, the optical signal (the signal based on the optical amplitude level) is accumulated in the capacitor element Csmp_s. The switch SW9s is a switch driven by the control signal Smpa_s, and when it is turned on, it connects the input node and the output node of the inverting amplifier Amp_s. The switches SW10s and SW11s are switches driven by the control signal Hold_s, and when they are turned on, they input a signal corresponding to the signal accumulated in the capacitor element Csmp_s to the subsequent source follower circuit composed of the P-type transistor M7s and the current source CSs. These switches SW8s, SW9s, SW10s, and SW11s turn on, for example, when the corresponding control signal is at a high level and turn off when the corresponding control signal is at a low level.

[0141] The inverting amplifiers Amp_n and Amp_s can be composed of, for example, a source-grounded circuit. The input node of the inverting amplifier Amp_n is connected to the capacitor element Csmp_n, and the output node is connected to the subsequent source follower circuit. Similarly, the input node of the inverting amplifier Amp_s is connected to the capacitor element Csmp_s, and the output node is connected to the subsequent source follower circuit via the switch SW10s. And a resistance element R is connected between the output nodes of these source follower circuits. Thereby, the current I flowing through the resistance element R is expressed as in the following formula (1). Here, Vn is the potential of the output node of the sample hold section 64N (the potential based on the pixel reset level), Vs is the potential of the output node of the sample hold section 64S (the potential based on the optical amplitude level), and R is the resistance value of the resistance element R. I = (Vn - Vs) / R …(1)

[0142] Since the current I flowing through the resistor element R is proportional to the difference between the potential Vn based on the reset level of the pixel 12 and the potential Vs based on the light amplitude level, CDS processing is performed at the stage where the current I is input to the AD conversion unit 68. This current I is input to the AD conversion unit 68.

[0143] The AD conversion unit 68 is a ΣΔ type AD conversion circuit and can be composed of, for example, as shown in FIG. 15, a first DA conversion circuit 681, a first integration circuit 682, a second integration circuit 683, a second DA conversion circuit 684, a quantization circuit 685, and a decimation filter 686. The first integration circuit 682 has an integration capacitor C1. The second integration circuit 683 has a Gm cell GM that converts the voltage value integrated by the first integration circuit 682 into a voltage-current, and an integration capacitor C2. The quantization circuit 685 has a quantizer QC. A first DA conversion circuit 681 having a current source CS1 and a switch SW11 controlled by the output signal of the quantizer QC is connected to the input node of the first integration circuit 682. Thereby, the current to the first integration circuit 682 is controlled according to the digital signal output via the second integration circuit 683 and the quantization circuit 685. A second DA conversion circuit 684 having a current source CS2 and a switch SW12 controlled by the output signal of the quantizer QC is connected to the output node of the second integration circuit 683. Thereby, the current to the second integration circuit 683 is controlled according to the result of quantizing the output of the second integration circuit 683 by the quantizer QC.

[0144] In the AD conversion unit 68, an operation is performed in which the quantization circuit 685 feeds back the previous quantization value to the second integration circuit 683 and the first integration circuit 682 through the DA converter. By passing through the integration circuit twice while feeding back the previous quantization value to the DA conversion circuit in this way, it is possible to obtain second-order noise shaping characteristics. Further, by removing high-frequency noise by the decimation filter 686 arranged at the subsequent stage of the quantization circuit 685, an analog-digital conversion output with high accuracy can be obtained.

[0145] Next, a method for driving the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 16. FIG. 16 is a timing chart showing the method for driving the photoelectric conversion device according to the present embodiment. FIG. 16 shows the waveforms of the voltage vl of the signal output line 16 and the control signals Ref_1, Ref_2, SEL_REF, RES, TX, Smpa_n, Smp_n, Smpa_s, Smp_s, Hold_n, Hold_s. Here, the <m>represents the line number and is attached to the voltage vl <n>represents the column number. FIG. 16 shows the operation of reading the signal from the pixel 12 arranged in the m-th row and the n-th column of the pixel array unit 10. Each switch is assumed to be in the on state (conductive state) during the period when the corresponding control signal is at the high level, and in the off state (non-conductive state) during the period when the corresponding control signal is at the low level.

[0146] The operation shown in FIG. 16 can be roughly divided into a correction value acquisition phase for acquiring the offset correction data D0, a correction value acquisition phase for acquiring the gain correction data D1, and an imaging phase. The offset correction data D0 is correction data used to correct the offset component for each column. The gain correction data D1 is correction data used to correct the gain component for each column. In the imaging phase, processing for the output signal from the pixel 12 is performed based on the acquired offset information and gain information.

[0147] The period from time t1 to time t8 is the correction value acquisition phase for acquiring the offset correction data D0. Immediately before time t1, the control signals Ref_2, RES <m>,TX <m>, Assume that Smpa_n, Smp_n, Smpa_s, Smp_s, Hold_n, and Hold_s are at a low level, and control signals Ref_1 and SEL_REF are at a high level.

[0148] At time t1, the timing generation unit 90 controls the control signal Ref_1 to a high level, the control signal Ref_2 to a low level, and the control signal SEL_REF to a high level. As a result, the switch SW5 turns on, the switch SW6 turns off, and the reference signal VREF1 is supplied to the gate of the amplification transistor M5. Also, upon receiving the high-level control signal SEL_REF, the selection transistor M6 turns on, and the signal (voltage vl) generated by the amplification transistor M5 based on the reference signal VREF1 <n>) is output to the signal output line 16 via the selection transistor M6.

[0149] This reference signal VREF1 is generated by a reference signal output circuit 34 provided on the signal processing substrate 140 and input to a reference signal output unit 40 provided on the pixel substrate 110 via the connection unit 112, similar to the previous embodiments. The reference signal VREF2 is also generated by the reference signal output circuit 34 provided on the signal processing substrate 140 and input to the reference signal output unit 40 provided on the pixel substrate 110 via the connection unit 112.

[0150] Also at time t1, the timing generation unit 90 controls the control signals Smp_n and Smpa_n from the low level to the high level. As a result, the switches SW9n and SW10n are turned on, and the sample hold unit 64N for the reset signal is connected to the signal output line 16.

[0151] At the subsequent time t2, the timing generation unit 90 controls the control signal Smpa_n from the high level to the low level. As a result, the switch SW10n is turned off. Also, a potential Vn corresponding to the pixel reset level based on the reference signal VREF1 is sampled in the capacitor element Csmp_n.

[0152] At the subsequent time t3, the timing generation unit 90 controls the control signal Smp_n from the high level to the low level. As a result, the switch SW9n is turned off, and the sample hold unit 64N is disconnected from the signal output line 16.

[0153] At the subsequent time t4, the timing generation unit 90 controls the control signals Smp_s and Smpa_s from the low level to the high level. As a result, the switches SW9s and SW10s are turned on, and the sample hold unit 64S for the optical signal is connected to the signal output line 16.

[0154] At the subsequent time t5, the timing generation unit 90 controls the control signal Smpa_s from a high level to a low level. As a result, the switch SW10s turns off. Also, a potential Vn corresponding to the pixel reset level based on the reference signal VREF1 is sampled in the capacitive element Csmp_s.

[0155] At the subsequent time t6, the timing generation unit 90 controls the control signal Smp_s from a high level to a low level. As a result, the switch SW9s turns off, and the sample-and-hold unit 64S is disconnected from the signal output line 16.

[0156] Note that the voltage between the terminals of the switch SW9s when turning off the switch SW9s at time t6 is always substantially the same regardless of the potential of the signal output line 16. Therefore, an error in the gain component is not superimposed on the signal accumulated in the capacitive element Csmp_s due to charge injection caused by the turn-off operation of the switch SW9s. Also, when turning off the switch SW9s at time t6, both terminals of the capacitive element Csmp_s are in a high-impedance state, so no influence is caused by the turn-off operation of the switch SW9s. Due to these effects, it is possible to suppress the gain error with respect to the signal held in the capacitive element Csmp_s.

[0157] During the period from the subsequent time t7 to time t8, the timing generation unit 90 controls the control signal Hold_n from a low level to a high level. As a result, the switches SW10n and SW11n are turned on, and a signal based on the reference signal VREF1 is output from the capacitor element Csmp_n to the subsequent source follower circuit. Also, during the same period from time t7 to time t8, the timing generation unit 90 controls the control signal Hold_s from a low level to a high level. As a result, the switches SW10s and SW11s are turned on, and a signal based on the reference signal VREF1 is output from the capacitor element Csmp_s to the subsequent source follower circuit. As a result, a current I corresponding to the potential difference between the output node of the sample and hold unit 64N and the output node of the sample and hold unit 64S flows through the resistor element R, and this current I is input to the AD conversion unit 68. By AD-converting this current I in the AD conversion unit 68, the offset correction data D0(n) for each column can be obtained (n represents an integer of the column number).

[0158] The period from time t8 to time t13 is a correction value acquisition phase for acquiring the gain correction data D1. The operation in the correction value acquisition phase for acquiring the gain correction data D1 is the same as the operation in the correction value acquisition phase for acquiring the offset correction data D0, except that the reference signal supplied to the amplification transistor M5 is different. Regarding the parts common to the correction value acquisition phase for acquiring the gain correction data D1, the description will be omitted as appropriate.

[0159] The operation from time t8 to time t9, that is, until the signal based on the reference signal VREF1 is sampled by the sample and hold unit 64N, is the same as the operation from time t1 to time t4.

[0160] At the subsequent time t9, the timing generation unit 90 controls the control signal Ref_1 from a high level to a low level and controls the control signal Ref_2 from a low level to a high level. As a result, the switch SW5 turns off, the switch SW6 turns on, and the reference signal VREF2 is supplied to the gate of the amplification transistor M5. Then, the signal (voltage vl) generated by the amplification transistor M5 based on the reference signal VREF2 <n>) is output to the signal output line 16 via the selection transistor M6.

[0161] Also, at the same time t9, the timing generation unit 90 controls the control signals Smp_s and Smpa_s from the low level to the high level. As a result, the switches SW9s and SW10s are turned on, and the sample and hold unit 64S for the optical signal is connected to the signal output line 16.

[0162] At the subsequent time t10, the timing generation unit 90 controls the control signal Smpa_s from the high level to the low level. As a result, the switch SW10s is turned off. Also, the potential Vs corresponding to the optical amplitude level based on the reference signal VREF2 is sampled in the capacitance element Csmp_s.

[0163] At the subsequent time t11, the timing generation unit 90 controls the control signal Smp_s from the high level to the low level. As a result, the switch SW9s is turned off, and the sample and hold unit 64S is disconnected from the signal output line 16.

[0164] During the period from the subsequent time t12 to the time t13, the timing generation unit 90 controls the control signal Hold_n from the low level to the high level. As a result, the switches SW10n and SW11n are turned on, and a signal based on the reference signal VREF1 is output from the capacitance element Csmp_n to the subsequent source follower circuit. Also, during the period from the time t12 to the time t13, the timing generation unit 90 controls the control signal Hold_s from the low level to the high level. As a result, the switches SW10s and SW11s are turned on, and a signal based on the reference signal VREF2 is output from the capacitance element Csmp_s to the subsequent source follower circuit. As a result, a current I corresponding to the potential difference between the output node of the sample and hold unit 64N and the output node of the sample and hold unit 64S flows through the resistance element R, and this current I is input to the AD conversion unit 68. By AD-converting this current I in the AD conversion unit 68, the gain correction data D1(n) for each column can be obtained (n represents an integer of the column number).

[0165] The period from time t13 to time t20 is the imaging phase. First, at time t14 after the control signals Hold_n and Hold_s transition to the low level at time t13, the timing generation unit 90 controls the control signal SEL_REF from the high level to the low level. As a result, the selection transistor M6 turns off, and the signal output line 16 is disconnected from the reference signal output circuit 36.

[0166] During the subsequent period from time t15 to time t16, the timing generation unit 90 controls the control signal RES <m>Control it from a low level to a high level. As a result, the node FD of pixel 12 is reset, and a voltage vl corresponding to the reset potential of the node FD is output to the signal output line 16. The voltage vl of the signal output line 16 at this time is the pixel reset level.

[0167] Also at time t15, the timing generation unit 90 controls the control signals Smpa_n and Smp_n from a low level to a high level in the same manner as the period from time t1 to time t3. As a result, the switches SW8n and SW9n are turned on, and the signal at the pixel reset level is sampled by the sample hold unit 64N.

[0168] In the subsequent period from time t17 to time t18, the vertical scanning circuit 20 controls the control signal TX from a low level to a high level. As a result, the charge accumulated in the photoelectric conversion element PD is transferred to the node FD, and a voltage vl corresponding to the amount of charge transferred to the node FD is output to the signal output line 16. The voltage vl of the signal output line 16 at this time is the optical amplitude level.

[0169] Also at time t17, the timing generation unit 90 controls the control signals Smpa_s and Smp_s from a low level to a high level in the same manner as the period from time t9 to time t11. As a result, the switches SW8s and SW9s are turned on, and the signal at the optical amplitude level is sampled by the sample hold unit 64S.

[0170] In the period from the subsequent time t19 to time t20, the timing generation unit 90 controls the control signal Hold_n from the low level to the high level. As a result, the switches SW10n and SW11n are turned on, and a signal based on the pixel reset level is output from the capacitor element Csmp_n to the subsequent source follower circuit. Also, in the same period from time t19 to time t20, the timing generation unit 90 controls the control signal Hold_s from the low level to the high level. As a result, the switches SW10s and SW11s are turned on, and a signal based on the optical amplitude level is output from the capacitor element Csmp_s to the subsequent source follower circuit. As a result, a current I corresponding to the potential difference between the output node of the sample hold unit 64N and the output node of the sample hold unit 64S flows through the resistance element R, and this current I is input to the AD conversion unit 68. By AD-converting this current I in the AD conversion unit 68, pixel data for each column can be acquired.

[0171] FIG. 17 is a graph for explaining a correction value generation method using the offset correction data D0 and the gain correction data D1 acquired in the correction value acquisition phase. In FIG. 17, the horizontal axis indicates the level of the reference signal, and the vertical axis indicates the output value. The offset correction data D0 and the gain correction data D1 are acquired for each column as described above.

[0172] In FIG. 17, the offset correction data D0 in which both the reset level and the optical amplitude level used for the CDS process are based on the reference signal VREF1 is equivalent to a signal equivalent to darkness, and can be used as the offset correction value itself. By taking the difference between this offset correction value (offset correction data D0) and the pixel data of the same column acquired in the imaging phase, offset correction including process variation components on the pixel substrate 110 becomes possible.

[0173] Also, in FIG. 17, a gain correction value can be calculated from the gain correction data D1 obtained from the potential based on the reference signal VREF1 for the reset level and the potential based on the reference signal VREF2 for the optical amplitude level. For example, the difference value (D1 - D0) between the offset correction data D0 and the gain correction data D1 is calculated for each column, and the ratio of the difference value (D1 - D0) of each column to the average value of the difference values (D1 - D0) of all columns is calculated to obtain the gain correction value. By dividing the gain correction value of each column by the pixel data of the same column obtained in the imaging phase, gain correction with high correlation to the pixel signal, including the linearity of the pixel transistor, becomes possible.

[0174] Note that in this embodiment, the description has been based on a form having the sample - hold unit 64N for the reset signal and the sample - hold unit 64S for the optical signal, but the present invention is not limited to this. For example, even when three or more sample - hold units are provided for multi - sampling applications, the present invention can be similarly applied. In this case, the same effect can be obtained by acquiring correction values for each sample - hold unit.

[0175] As described above, according to this embodiment, in the photoelectric conversion device configured by bonding the pixel substrate and the signal processing substrate, the image quality and the operation speed can be improved.

[0176] [Fifth Embodiment] The photoelectric conversion device according to the fifth embodiment of the present invention will be described with reference to FIG. 18. The same components as those of the photoelectric conversion device according to the first to fourth embodiments are denoted by the same reference numerals, and the description is omitted or simplified. FIG. 18 is a circuit diagram showing a configuration example of the column circuit of the photoelectric conversion device according to this embodiment.

[0177] In the photoelectric conversion device according to the fourth embodiment, for example, a configuration for switching the gain of the readout circuit 30 according to the amount of light as described in the second embodiment can also be applied. In this embodiment, a configuration example when the gain switching function is applied to the photoelectric conversion device of the fourth embodiment will be described. In this embodiment, the description will focus on the differences from the photoelectric conversion device according to the fourth embodiment, and the description of the same points as the photoelectric conversion device according to the fourth embodiment will be omitted as appropriate.

[0178] The column circuit 32 of the photoelectric conversion device according to this embodiment, for example, as shown in FIG. 18, in addition to the reference signal output circuit 36 having switches SW5, SW6, amplification transistor M5, and selection transistor M6, further has a switch SW7. A reference signal VREF3 is supplied from the reference signal output circuit 34 to one terminal of the switch SW7. The other terminal of the switch SW7 is connected to the gate of the amplification transistor M5. That is, the reference signal output circuit 36 is configured to supply any one of the three types of reference signals VREF1, VREF2, and VREF3 to the gate of the amplification transistor M5 according to the connection states of the switches SW5, SW6, and SW7. Here, the reference signal VREF1 is a voltage corresponding to the reset level, the reference signal VREF2 is a voltage corresponding to the light amplitude level at low luminance, and the reference signal VREF3 is a voltage corresponding to the light signal level at high luminance.

[0179] Further, the column circuit 32 of this embodiment further has a determination unit 66. The determination unit 66 is connected to the signal output line 16 and the resistance element R, and is configured to change the resistance value of the variable resistance element VR according to the signal amount appearing on the signal output line 16. By changing the resistance value of the variable resistance element VR, the conversion gain when converting the differential voltage of the signals held in the sample hold units 64N and 64S into current can be controlled. Further, the determination unit 66 is configured to output a determination signal jdg corresponding to the signal amount appearing on the signal output line 16 to the subsequent signal processing circuit 80.

[0180] Next, a method for driving the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 19. FIG. 19 is a timing chart showing the method for driving the photoelectric conversion device according to the present embodiment. In FIG. 19, the voltage vl of the signal output line 16, control signals Ref_1, Ref_2, Ref_3, SEL_REF, RES <m>,TX <m>,It shows the waveforms of Smpa_n, Smp_n, Smpa_s, Smp_s, Hold_n, Hold_s, and the determination signal jdg. Here, it is noted in the signs of the control signals RES and TX <m>represents the line number and is attached to the voltage vl <n>represents the column number. FIG. 19 shows the operation of reading the signal from the pixel 12 arranged in the m-th row and n-th column of the pixel array unit 10. Each switch is assumed to be in an on state (conductive state) during the period when the corresponding control signal is at a high level and in an off state (non-conductive state) during the period when the corresponding control signal is at a low level.

[0181] The operation shown in FIG. 19 can be roughly divided into a correction value acquisition phase for acquiring the offset correction data D0, a correction value acquisition phase for acquiring the gain correction data D1, and an imaging phase. The correction value acquisition phase for acquiring the offset correction data D0 can be further divided into a correction value acquisition phase for acquiring the offset correction data D0 at low luminance and a correction value acquisition phase for acquiring the offset correction data D0 at high luminance. Also, the correction value acquisition phase for acquiring the gain correction data D1 can be divided into a correction value acquisition phase for acquiring the gain correction data D1 at low luminance and a correction value acquisition phase for acquiring the gain correction data D1 at high luminance.

[0182] In FIG. 19, the period from time t31 to time t32 is the correction value acquisition phase for acquiring the offset correction data D0 at low luminance. The period from time t32 to time t34 is the correction value acquisition phase for acquiring the gain correction data D1 at low luminance. The period from time t34 to time t36 is the correction value acquisition phase for acquiring the offset correction data D0 at high luminance. The period from time t36 to time t38 is the correction value acquisition phase for acquiring the gain correction data D1 at high luminance. The period from time t38 to time t40 is the imaging phase.

[0183] During the period from time t31 to time t32, the low-luminance offset correction data D0 is acquired based on the reference signal VREF1. The specific operation is the same as the operation during the period from time t1 to time t8 in FIG. 16, except that the control signal Ref_3 is controlled to be at a low level.

[0184] During the period from the subsequent time t32 to time t34, low luminance gain correction data D1 is acquired by switching from the reference signal VREF1 to the reference signal VREF2 at time t33. The specific operation is the same as the operation during the period from time t8 to time t13 in FIG. 16, except that the control signal Ref_3 is controlled to a low level.

[0185] During the period from the subsequent time t34 to time t36, after switching from the reference signal VREF2 to the reference signal VREF1 at time t35, high luminance offset correction data D0 is acquired based on the reference signal VREF1. The specific operation is the same as the operation during the period from time t1 to time t8 in FIG. 16, except that the control signal Ref_3 is controlled to a low level.

[0186] During the period from the subsequent time t36 to time t38, high luminance gain correction data D1 is acquired by switching from the reference signal VREF1 to the reference signal VREF3 at time t37. The specific operation is the same as the operation during the period from time t8 to time t13 in FIG. 16, except that the control signal Ref_2 is controlled to a low level and the control signal Ref_3 is controlled to a high level.

[0187] During the period from the subsequent time t38 to time t39, an imaging phase similar to the period from time t13 to time t20 in FIG. 16 is performed to acquire pixel data of each pixel 12. The offset correction data D0, gain correction data D1, and pixel data thus acquired are transferred to the subsequent signal processing circuit 80. Further, when the determination unit 66 determines that the subject is high luminance, for example, a high level determination signal jdg is output to the subsequent signal processing circuit 80, and when the determination unit 66 determines that the subject is low luminance, for example, a low level determination signal jdg is output. The determination signal jdg can be transferred to the signal processing circuit 80, for example, during the period from time t39 to time t40. Note that the determination as to whether the subject is low luminance or high luminance can be performed by, for example, the same method as in the second embodiment.

[0188] In the signal processing circuit 80, the pixel data acquired in the imaging phase is corrected using the offset correction data D0 and the gain correction data D1 for low brightness and high brightness, respectively. At this time, based on the determination signal jdg indicating the determination result of the determination unit 66, it is selected for each pixel 12 whether to use the correction value for low brightness or the correction value for high brightness.

[0189] Note that the method of inputting the reference signal used when acquiring the correction value is not necessarily limited to the method shown in FIG. 19. For example, the offset correction data D0 and the gain correction data D1 may be calculated not by directly acquiring their values, but by performing calculations using the input reference signals VREF1 and VREF2 and the output offset correction data D0 and gain correction data D1. For example, the reference signal corresponding to the optical amplitude level at the time of acquiring the high brightness offset correction data D0 is set to the reference signal VREF2. Then, the high brightness offset correction data D0 may be calculated by performing calculations using the reference signals VREF1 and VREF2 and the offset correction data D0 and gain correction data D1.

[0190] As described above, according to the present embodiment, in the photoelectric conversion device configured by bonding the pixel substrate and the signal processing substrate, the image quality and the operation speed can be improved.

[0191] [Sixth Embodiment] The photoelectric conversion system according to the sixth embodiment of the present invention will be described with reference to FIG. 20. FIG. 20 is a block diagram showing a schematic configuration of the photoelectric conversion system according to the present embodiment.

[0192] The photoelectric conversion device 100 described in the first to third embodiments above is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and the like. In addition, a camera module including an optical system such as a lens and an imaging device is also included in the photoelectric conversion system. FIG. 20 illustrates a block diagram of a digital still camera as an example of these.

[0193] The photoelectric conversion system 200 illustrated in FIG. 20 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, a diaphragm 204 for variably controlling the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the diaphragm 204 are an optical system that condenses light onto the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to third embodiments, and converts the optical image formed by the lens 202 into image data.

[0194] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. Further, the signal processing unit 208 performs operations of outputting image data by performing various corrections and compressions as necessary. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor layer (semiconductor substrate) different from the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed. Further, the signal processing unit 208 may be formed on the same semiconductor layer (semiconductor substrate) as the imaging device 201.

[0195] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Further, the photoelectric conversion system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading from the recording medium 214. Note that the recording medium 214 may be built into the photoelectric conversion system 200 or may be detachable.

[0196] Furthermore, the photoelectric conversion system 200 includes an overall control and arithmetic unit 218 that controls various operations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from the outside, and the photoelectric conversion system 200 may have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0197] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0198] As described above, according to this embodiment, a photoelectric conversion system to which the photoelectric conversion device 100 according to the first to third embodiments is applied can be realized.

[0199] [Seventh Embodiment] The photoelectric conversion system and the moving body according to the seventh embodiment of the present invention will be described with reference to FIG. 21. FIG. 21 is a diagram showing the configuration of the photoelectric conversion system and the moving body according to this embodiment.

[0200] FIG. 21(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to third embodiments. The photoelectric conversion system 300 includes an image processing unit 312 that performs image processing on a plurality of pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of a parallax image) from the plurality of pieces of image data acquired by the imaging device 310. Further, the photoelectric conversion system 300 includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information related to parallax, defocus amount, distance to an object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicatedly designed hardware, or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated circuit), or the like, or may be realized by a combination thereof.

[0201] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the photoelectric conversion system 300 is connected to a control ECU 330, which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of the collision determination unit 318. Further, the photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, when the collision determination unit 318 determines that there is a high possibility of collision, the control ECU 330 performs vehicle control to avoid the collision and reduce damage, such as applying the brakes, returning the accelerator, and suppressing the engine output. The alarm device 340 warns the user by sounding an alarm such as a sound, displaying alarm information on the screen of a car navigation system, or applying vibration to the seat belt or steering wheel.

[0202] In the present embodiment, the photoelectric conversion system 300 images the surroundings of the vehicle, for example, the front or the rear. Fig. 21(b) shows the photoelectric conversion system when imaging the front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends an instruction to the photoelectric conversion system 300 or the imaging device 310. With such a configuration, the ranging accuracy can be further improved.

[0203] In the above, an example of controlling so as not to collide with other vehicles has been described, but it is also applicable to control for automatically driving while following other vehicles and control for automatically driving so as not to deviate from the lane. Further, the photoelectric conversion system is not limited to vehicles such as the host vehicle, and can be applied to moving bodies (moving devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies but also to devices that widely utilize object recognition, such as an advanced road traffic system (ITS).

[0204] [Eighth Embodiment] The device according to the eighth embodiment of the present invention will be described with reference to Fig. 22. Fig. 22 is a block diagram showing a schematic configuration of the device according to the present embodiment.

[0205] FIG. 22 is a schematic diagram showing a device EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 according to any one of the first to third embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometric sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than the pixel circuits can be arranged in the peripheral area PR.

[0206] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip can be column circuits corresponding to the pixel columns of the first semiconductor chip, respectively. Also, the peripheral circuits in the second semiconductor chip can be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip, respectively. The connection between the first semiconductor chip and the second semiconductor chip can employ through electrodes (TSV), inter-chip wiring by direct bonding of a conductor such as copper, connection by micro bumps between chips, connection by wire bonding, and the like.

[0207] In addition to the semiconductor device IC, the photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC. The package PKG can include a base on which the semiconductor device IC is fixed, a lid such as glass facing the semiconductor device IC, and connection members such as bonding wires and bumps that connect the terminals provided on the base and the terminals provided on the semiconductor device IC.

[0208] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to a photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays the information (image) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores the information (image) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a movable part or a propulsion part such as a motor or an engine. In the equipment EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL or transmitted to the outside by a communication device (not shown) provided in the equipment EQP. For this purpose, it is preferable that the equipment EQP further includes a memory device MMRY and a processing device PRCS separately from the storage circuit part and the arithmetic circuit part of the photoelectric conversion device APR.

[0209] The equipment EQP shown in FIG. 22 can be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable terminal) or a camera (e.g., a single-lens reflex camera, a compact camera, a video camera, a surveillance camera). The mechanical device MCHN in the camera can drive the components of the optical device OPT for zooming, focusing, and shutter operation. Also, the equipment EQP can be a transportation device (a moving body) such as a vehicle, a ship, or an aircraft. Also, the equipment EQP can be a medical device such as an endoscope or a CT scanner.

[0210] The mechanical device MCHN in the transport device can be used as a moving device. The device EQP as a transport device is suitable for transporting the photoelectric conversion device APR or for assisting and / or automating driving (operation) by means of a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on the information obtained by the photoelectric conversion device APR.

[0211] The photoelectric conversion device APR according to the present embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is mounted on the device EQP, the value of the device EQP can also be increased. Thus, in manufacturing and selling the device EQP, determining to mount the photoelectric conversion device APR of the present embodiment on the device EQP is advantageous for increasing the value of the device EQP.

[0212] [Modified Embodiment] The present invention is not limited to the above embodiment and various modifications are possible.

[0213] For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment or an example in which a part of the configuration is replaced with that of another embodiment is also an embodiment of the present invention.

[0214] Also, among the transistors provided in pixel 12, a configuration in which one or both of transfer transistor M1 and selection transistor M4 are omitted may be adopted. When selection transistor M4 is omitted, the selection state and non-selection state of pixel 12 can be switched by providing a plurality of reset potentials for node FD. That is, by setting the potential of node FD such that the gate-source voltage Vgs of amplification transistor M3 is lower than the threshold voltage of amplification transistor M3, pixel 12 can be set to the non-selection state. On the other hand, by setting the potential of FD such that the gate-source voltage Vgs of amplification transistor M3 is higher than the threshold voltage of amplification transistor M3, pixel 12 can be set to the selection state. Additionally, more transistors may be provided in pixel 12. For example, in the case of pixel 12 performing a global shutter operation, a transistor connected to photoelectric conversion element PD and controlling the reset operation of photoelectric conversion element PD is provided. Further, between photoelectric conversion element PD and transfer transistor M1, a holding unit for holding charges and a transistor for switching the connection and disconnection between photoelectric conversion element PD and the holding unit are further provided. Such a structure of pixel 12 may be adopted.

[0215] In addition, in the first to third embodiments, a stacked-type photoelectric conversion device in which two substrates are bonded together has been described. However, the number of substrates constituting the photoelectric conversion device is not limited to two, and may be three or more. For example, a memory substrate provided with a memory may be provided separately from the substrates of the pixel substrate 110 and the signal processing substrate 140, and these substrates may be stacked in any order. Also in a stacked-type photoelectric conversion device in which three or more substrates are bonded together, similar to this embodiment, by separately forming the reference signal output circuit 34 and the reference signal output circuit 36 on appropriate substrates, the same effects as those of these embodiments can be obtained. Further, the pixel 12 may be provided separately on a plurality of substrates. For example, a structure may be adopted in which the photoelectric conversion element PD is arranged on one substrate (third substrate) and the pixel circuit 17 is arranged on another substrate (first substrate). The third substrate and the first substrate are electrically connected. This electrical connection can use, for example, the above-described TSV (Through Silicon Via) technology or metal bonding between metals (Cu-Cu bonding). Note that this division method is an example, and the pixel 12 may be divided and arranged on three or more substrates. That is, a three-layer or more photoelectric conversion device in which two or more pixel substrates and one or more signal processing substrates are stacked may be used. In any case, the reference signal output circuit 36 is arranged on the substrate on which the amplification transistor M3 of the pixel 12 is provided. That is, in each embodiment, it is sufficient that the reference signal output circuit 36 is arranged on the substrate on which the pixel circuit 17 is provided.

[0216] Also, FIG. 7 shows an FSI-type photoelectric conversion device bonded face-to-back such that the second face 124 of the pixel substrate 110 faces the first face 152 of the signal processing substrate 140. However, a BSI-type photoelectric conversion device bonded face-to-back such that the first face 122 of the pixel substrate 110 faces the second face 154 of the signal processing substrate 140 may be configured. In this case, the pixel substrate 110 and the signal processing substrate 140 are electrically connected via a through electrode provided so as to penetrate the semiconductor substrate 150.

[0217] In addition, in the first to fifth embodiments, examples in which the present invention is applied to a photoelectric conversion device having a ramp-type AD converter or a ΔΣ-type AD converter have been described. However, the AD converter included in the photoelectric conversion device does not necessarily have to be a ramp-type AD converter or a ΔΣ-type AD converter. The present invention is applicable not only to a photoelectric conversion device having a ramp-type AD converter or a ΔΣ-type AD converter, but also to a photoelectric conversion device having other AD converters such as a successive approximation type AD converter.

[0218] In addition, in each embodiment, a form in which the reference signal output circuit 48 provided inside the photoelectric conversion device generates the reference signal rmp has been described, but the present invention is not limited to this example. For example, a reference signal rmp generated outside the photoelectric conversion device may be input to the reference signal output circuit 48, and the reference signal output circuit 48 may buffer and output this reference signal rmp.

[0219] In addition, in each embodiment, a form in which the reference signal output circuit 34 provided inside the photoelectric conversion device generates the reference signal has been described, but the present invention is not limited to this example. For example, a reference signal generated outside the photoelectric conversion device may be input to the reference signal output circuit 34, and the reference signal output circuit 34 may buffer and output this reference signal.

[0220] In addition, the photoelectric conversion system shown in the sixth and seventh embodiments above shows an example of a photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied, and the photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied is not limited to the configurations shown in FIGS. 20 and 21(a).

[0221] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and causing one or more processors in a computer of the system or device to read and execute the program. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

[0222] Note that each of the above embodiments is merely an example of implementation when carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

[0223] The disclosure of the above embodiment includes the following configurations. (Configuration 1) A photoelectric conversion device having a first substrate and a second substrate bonded to the first substrate, a plurality of pixel circuits provided on the first substrate so as to form a plurality of columns, each outputting a signal based on charges generated by photoelectric conversion; a plurality of column circuits provided on the second substrate, each performing gain processing on the output signal from the corresponding pixel circuit; a reference signal output unit provided on the second substrate, outputting a reference signal according to the gain processing; a connection unit electrically connecting the first substrate and the second substrate; and a signal output unit having an amplification circuit provided on the first substrate, wherein the signal output unit outputs, via the amplification circuit, a signal based on the reference signal input from the reference signal output unit via the connection unit to the plurality of column circuits A photoelectric conversion device characterized by the above. (Configuration 2) further having a signal processing unit that processes the output signal of the column circuit, wherein the signal processing unit corrects the gain error of the column circuit that superimposes on the output signal of the column circuit when the output signal of the pixel circuit is used, using the output signal of the column circuit when the output signal of the signal output unit is input The photoelectric conversion device according to Configuration 1, characterized by the above. (Configuration 3) The signal processing unit corrects the gain error by using the ratio between the output signal of the signal output unit when the reference signal of the first level is input and the output signal of the signal output unit when the reference signal of the second level different from the first level is input. The photoelectric conversion device according to Configuration 2, characterized in that. (Configuration 4) The signal output unit restricts the voltage operation amplitude of the output signal of the pixel circuit input to the column circuit by the output signal when the reference signal is input. The photoelectric conversion device according to Configuration 1, characterized in that. (Configuration 5) The second substrate further includes a reference signal output unit that outputs a reference signal whose level changes with the passage of time. Each of the plurality of column circuits has a comparator that compares the output signal of the pixel circuit with the reference signal, and performs analog-to-digital conversion of the output signal of the pixel circuit with a gain according to the time change rate of the level of the reference signal. The photoelectric conversion device according to any one of Configurations 1 to 4, characterized in that. (Configuration 6) The reference signal output unit sets the level of the reference signal according to the time change rate. The photoelectric conversion device according to Configuration 5, characterized in that. (Configuration 7) The reference signal output unit includes a first reference signal output circuit that outputs a first reference signal and a second reference signal output circuit that outputs a second reference signal having a different time change rate from the first reference signal. Each of the plurality of column circuits selects either the first reference signal or the second reference signal as the reference signal to be compared with the output signal of the pixel circuit according to the level of the output signal of the pixel circuit. The photoelectric conversion device according to Configuration 5 or 6, characterized in that. (Configuration 8) Each of the plurality of column circuits has a column amplifier that amplifies the output signal of the pixel circuit. The reference signal output unit sets the level of the reference signal according to the gain of the column amplifier. The photoelectric conversion device according to any one of Configurations 1 to 7, characterized in that... (Configuration 9) Each of the plurality of column circuits sets the gain of the column amplifier according to the level of the output signal of the pixel circuit. The photoelectric conversion device according to Configuration 8, characterized in that... (Configuration 10) The plurality of column circuits have an oversampling type AD converter that performs analog-digital conversion based on the output signal of the pixel circuit. The photoelectric conversion device according to any one of Claims 1 to 4, characterized in that... (Configuration 11) Each of the plurality of pixel circuits further has a first amplification transistor that amplifies a signal corresponding to the amount of charge generated in the photoelectric conversion unit. The signal output unit is provided corresponding to the plurality of columns, and each has a plurality of second amplification transistors that amplify the reference signal and output it to the column circuit of the corresponding column. The size of the first amplification transistor is the same as the size of the second amplification transistor. The photoelectric conversion device according to any one of Configurations 1 to 10, characterized in that... (Configuration 12) The reference signal output unit and the signal output unit are electrically connected via a plurality of the connection parts. The photoelectric conversion device according to any one of Configurations 1 to 11, characterized in that... (Configuration 13) The reference signal output unit has a plurality of reference signal output circuits that each output the reference signal. The plurality of reference signals output by the plurality of reference signal output circuits are input to the signal output unit via different connection parts. The photoelectric conversion device according to any one of Configurations 1 to 12, characterized in that... (Configuration 14) It further has a pad electrode provided on the second substrate and connected to a wiring via an opening penetrating the first substrate. The photoelectric conversion device according to any one of Configurations 1 to 13, characterized in that... (Configuration 15) Further comprising a pad electrode provided on the first substrate, The pad electrode is electrically connected to the second substrate via a connection portion different from the connection portion that electrically connects the reference signal output portion and the signal output portion. The photoelectric conversion device according to any one of Configurations 1 to 13, characterized in that... (Configuration 16) Each of the first substrate and the second substrate has a metal wiring as the uppermost wiring layer, The connection portion is constituted by a metal junction between metals constituting the metal wiring. The photoelectric conversion device according to any one of Configurations 1 to 15, characterized in that... (Configuration 17) The connection portion includes a through electrode provided so as to penetrate a semiconductor substrate constituting the first substrate or the second substrate. The photoelectric conversion device according to any one of Configurations 1 to 15, characterized in that... (Configuration 18) Further comprising a plurality of photoelectric conversion portions each generating the charge, The plurality of photoelectric conversion portions are provided on the first substrate. The photoelectric conversion device according to any one of Configurations 1 to 17, characterized in that... (Configuration 19) Further comprising a plurality of photoelectric conversion portions each generating the charge, The plurality of photoelectric conversion portions are provided on a third substrate, and the third substrate is electrically connected to the first substrate. The photoelectric conversion device according to any one of Configurations 1 to 17, characterized in that... (Configuration 20) The photoelectric conversion device according to any one of Configurations 1 to 19, and A signal processing device that processes a signal output from the photoelectric conversion device A photoelectric conversion system characterized by comprising... (Configuration 21) A moving body, The photoelectric conversion device according to any one of Configurations 1 to 19, distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device, control means for controlling the moving body based on the distance information A moving body characterized by comprising: (Configuration 22) The photoelectric conversion device according to any one of Configurations 1 to 19, an optical device corresponding to the photoelectric conversion device, a control device for controlling the photoelectric conversion device, a processing device for processing a signal output from the photoelectric conversion device, a mechanical device controlled based on information obtained by the photoelectric conversion device, a display device for displaying information obtained by the photoelectric conversion device, and a storage device for storing information obtained by the photoelectric conversion device, at least one of A device characterized by comprising:

Explanation of Signs

[0224] 12... pixels 16... signal output lines 32... column circuits 34, 36... reference signal output circuits 42... column amplifiers 48... reference signal output circuits 100... photoelectric conversion device 110... pixel substrate 112, 114, 116... connection parts 140... signal processing substrate< / n> < / m> < / m> < / m> < / m> < / n> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m>

Claims

1. A photoelectric conversion device having a first substrate and a second substrate bonded to the first substrate, a plurality of pixel circuits provided in a plurality of columns on the first substrate, each pixel circuit outputting a signal based on an electric charge generated by photoelectric conversion; a plurality of column circuits provided on the second substrate, each of which performs gain processing on an output signal from a corresponding pixel circuit; a reference signal output unit provided on the second substrate and outputting a reference signal corresponding to the gain processing; a connection portion that electrically connects the first substrate and the second substrate; a signal output unit having an amplifier circuit provided on the first substrate, The signal output unit outputs a signal based on the reference signal input from the reference signal output unit via the connection unit to the plurality of column circuits via the amplifier circuit. A photoelectric conversion device comprising:

2. A signal processing unit that processes an output signal of the column circuit, The signal processing unit corrects a gain error of the column circuit superimposed on the output signal of the column circuit when the output signal of the pixel circuit is input, by using the output signal of the column circuit when the output signal of the signal output unit is input.

2. The photoelectric conversion device according to claim 1.

3. The signal processing unit corrects the gain error by using a ratio between the output signal of the signal output unit when the reference signal of a first level is inputted to the output signal of the signal output unit when the reference signal of a second level different from the first level is inputted.

3. The photoelectric conversion device according to claim 2.

4. The signal output unit limits a voltage operation amplitude of the output signal of the pixel circuit input to the column circuit by an output signal when the reference signal is input.

2. The photoelectric conversion device according to claim 1.

5. a reference signal output unit provided on the second substrate and configured to output a reference signal whose level changes over time; Each of the plurality of column circuits has a comparator that compares the output signal of the pixel circuit with the reference signal, and performs analog-to-digital conversion of the output signal of the pixel circuit with a gain corresponding to a time rate of change of the level of the reference signal.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. The reference signal output unit sets a level of the reference signal in accordance with the time rate of change.

6. The photoelectric conversion device according to claim 5.

7. the reference signal output unit includes a first reference signal output circuit that outputs a first reference signal, and a second reference signal output circuit that outputs a second reference signal having a time change rate different from that of the first reference signal; Each of the plurality of column circuits selects, in accordance with a level of the output signal of the pixel circuit, one of the first reference signal and the second reference signal as the reference signal to be compared with the output signal of the pixel circuit.

6. The photoelectric conversion device according to claim 5.

8. each of the plurality of column circuits includes a column amplifier that amplifies the output signal of the pixel circuit; The reference signal output unit sets a level of the reference signal in accordance with a gain of the column amplifier.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

9. Each of the plurality of column circuits sets a gain of the column amplifier in response to a level of the output signal of the pixel circuit.

9. The photoelectric conversion device according to claim 8.

10. The plurality of column circuits each include an oversampling AD converter that performs analog-to-digital conversion based on the output signal of the pixel circuit.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

11. Each of the plurality of pixel circuits further includes a first amplifying transistor that amplifies a signal corresponding to an amount of charge generated in the photoelectric conversion unit, the signal output unit includes a plurality of second amplifying transistors provided corresponding to the plurality of columns, each of which amplifies the reference signal and outputs the amplified reference signal to the column circuit of the corresponding column; The size of the first amplifying transistor is the same as the size of the second amplifying transistor.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

12. The reference signal output section and the signal output section are electrically connected via a plurality of the connection sections.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

13. the reference signal output unit includes a plurality of reference signal output circuits each of which outputs the reference signal; The plurality of reference signals outputted from the plurality of reference signal output circuits are inputted to the signal output section via the connection sections different from each other.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

14. The second substrate further includes a pad electrode to which a wiring is connected via an opening penetrating the first substrate.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

15. The semiconductor device further includes a pad electrode provided on the first substrate, The pad electrode is electrically connected to the second substrate via the connection portion different from the connection portion that electrically connects the reference signal output portion and the signal output portion.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

16. Each of the first substrate and the second substrate has a metal wiring as a top wiring layer, The connection portion is formed by metal bonding between the metals that constitute the metal wiring.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

17. The connection portion includes a through electrode provided so as to penetrate a semiconductor substrate constituting the first substrate or the second substrate.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

18. Further comprising a plurality of photoelectric conversion units each generating the electric charge; The plurality of photoelectric conversion units are provided on the first substrate.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

19. Further comprising a plurality of photoelectric conversion units each generating the electric charge; The plurality of photoelectric conversion units are provided on a third substrate, and the third substrate and the first substrate are electrically connected to each other.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

20. The photoelectric conversion device according to claim 1 , a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

21. A mobile object, The photoelectric conversion device according to claim 1 , a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

22. The photoelectric conversion device according to claim 1 , an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising:

Images