Amplifier circuit

Abstract

To provide an amplifier circuit that can be reduced in size.SOLUTION: An amplifier circuit comprises: a distributor 18 that distributes an input signal to a first signal and a second signal; a first amplifier that has a first node to which the first signal is input, amplifies the first signal input to the first node, and outputs the amplified first signal as a third signal; a second amplifier that has a second node to which the second signal is input, amplifies the second signal input to the second node, and outputs the amplified second signal as a fourth signal; a path 28 that galvanically connects the first node and the second node to each other through the distributor; and a combiner 20 that combines the third signal and the fourth signal with each other. A third node, which supplies bias voltage to the first amplifier and the second amplifier, is provided to only one point in the path.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] As an amplifier circuit for amplifying high-frequency signals such as microwaves, a balanced amplifier (balun) is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, a bias voltage is applied from a voltage source 8 to the input nodes of amplifiers 4 and 5, and a bias voltage is applied from a voltage source 9 to the output nodes of amplifiers 4 and 5. However, a specific method of applying the bias voltage from the voltage source 8 to the input nodes of amplifiers 4 and 5 is not described, and the amplifier circuit may be enlarged.

[0005] The present disclosure has been made in view of the above problems and aims to be miniaturized.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is an amplifier circuit including a distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a path that directly connects the first node and the second node via the distributor, a synthesizer that synthesizes the third signal and the fourth signal, and a third node that supplies a bias voltage to the first amplifier and the second amplifier in the path is provided at only one location.

[0007] One embodiment of the present disclosure is an amplifier circuit including a distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a synthesizer that synthesizes the third signal and the fourth signal, a single pad to which a bias voltage is supplied, a first bias circuit that directly connects the single pad and the first node and suppresses leakage of the first signal to the single pad, and a second bias circuit that directly connects the single pad and the second node and suppresses leakage of the second signal to the single pad.

[0008] One embodiment of the present disclosure includes a distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a synthesizer that synthesizes the third signal and the fourth signal, a single pad to which a bias voltage is supplied, a first bias circuit that is connected directly in DC between the single pad and the first node to suppress leakage of the first signal to the single pad, and a second bias circuit that is connected directly in DC between the first node and the second node to suppress leakage of the first signal to the second node and leakage of the second signal to the first node.

Advantages of the Invention

[0009] According to the present disclosure, miniaturization can be achieved.

Brief Description of the Drawings

[0010]

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DETAILED DESCRIPTION OF THE INVENTION

[0011] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is an amplifier circuit including a distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node into which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node into which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a path that directly connects the first node and the second node via the distributor, a synthesizer that synthesizes the third signal and the fourth signal, and a third node that supplies a bias voltage to the first amplifier and the second amplifier in the path is provided at only one location. Thereby, since the number of pads and the number of bias circuits can be reduced, the amplifier circuit can be miniaturized. (2) In the above (1), it may further include a pad to which the bias voltage is supplied, and a bias circuit that directly connects the pad and the third node and suppresses leakage of the first signal and the second signal to the pad. Thereby, since the pad and the bias circuit can be reduced, the amplifier circuit can be miniaturized. (3) In the above (1) or (2), the distributor may include a branch-line coupler including a first terminal to which the input signal is input, a second terminal from which the first signal is output, a third terminal located diagonally to the first terminal and from which the second signal is output, and a fourth terminal located diagonally to the second terminal and terminated at a reference potential. Thereby, the first node and the second node can be directly connected via the distributor. (4) In the above (3), it may further include a capacitor having a first terminal connected to the fourth terminal of the branch-line coupler, and a resistor having a first terminal connected to the second terminal of the capacitor and a second terminal connected to the reference potential. Thereby, it is possible to suppress a direct current from flowing from the path to the reference potential. (5) One embodiment of the present disclosure includes a distributor that distributes an input signal into a first signal and a second signal, a first node to which the first signal is input, a first amplifier that amplifies the first signal input to the first node and outputs the amplified first signal as a third signal, a second node to which the second signal is input, a second amplifier that amplifies the second signal input to the second node and outputs the amplified second signal as a fourth signal, a synthesizer that synthesizes the third signal and the fourth signal, a single pad to which a bias voltage is supplied, a first bias circuit that is connected directly in DC between the single pad and the first node to suppress leakage of the first signal to the single pad, and a second bias circuit that is connected directly in DC between the single pad and the second node to suppress leakage of the second signal to the single pad. As a result, the number of pads can be reduced, and thus the amplification circuit can be miniaturized. (6) One embodiment of the present disclosure includes a distributor that distributes an input signal into a first signal and a second signal, a first node to which the first signal is input, a first amplifier that amplifies the first signal input to the first node and outputs the amplified first signal as a third signal, a second node to which the second signal is input, a second amplifier that amplifies the second signal input to the second node and outputs the amplified second signal as a fourth signal, a synthesizer that synthesizes the third signal and the fourth signal, a single pad to which a bias voltage is supplied, a first bias circuit that is connected directly in DC between the single pad and the first node to suppress leakage of the first signal to the single pad, and a second bias circuit that is connected directly in DC between the first node and the second node to suppress leakage of the first signal to the second node and leakage of the second signal to the first node. As a result, the number of pads can be reduced, and thus the amplification circuit can be miniaturized. (7) In the above (5) or (6), the first terminal that outputs the first signal of the distributor and the second terminal that outputs the second signal of the distributor may not be connected directly in DC via the distributor. As a result, the number of pads can be reduced, and thus the amplification circuit can be miniaturized. (8) In (5) or (6) above, the first terminal that outputs the first signal of the distributor and the second terminal that outputs the second signal of the distributor are directly connected via the distributor in a DC manner, a first capacitor with the first terminal connected to the distributor and the second terminal connected to the first node, and a second capacitor with the first terminal connected to the distributor and the second terminal connected to the second node may be provided. Thereby, the number of pads can be reduced, and thus the amplifier circuit can be miniaturized. (9) In any of (1) to (8) above, another distributor that distributes a high-frequency signal into the input signal and a fifth signal, and a control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal are provided, and the synthesizer modulates the loads of the first amplifier and the second amplifier using the sixth signal, and may synthesize the third signal, the fourth signal, and the sixth signal and output the synthesized signal as an output signal. Thereby, the bandwidth of the operating band can be broadened. (10) In (9) above, a DC path that directly connects the output node of the first amplifier and the output node of the control amplifier via the synthesizer may be provided, and a fourth node that supplies a bias voltage to the first amplifier and the control amplifier in the DC path may be provided at only one location. Thereby, the number of pads and the number of bias circuits can be reduced, and thus the amplifier circuit can be miniaturized. [Details of Embodiments of the Present Disclosure] A specific example of the amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] [Example 1] Example 1 is an example of a balun. FIG. 1 is a circuit diagram of the amplifier circuit according to Example 1. As shown in FIG. 1, in the amplifier circuit 100 of Example 1, amplifiers 10 and 11 are connected in parallel between the input terminal Tin and the output terminal Tout. A high-frequency signal is input as the input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station for mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A capacitor C01 for DC (Direct Current) cut is connected between the input terminal Tin and the distributor 18. The distributor 18 distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0013] The signal S1 passes through the matching circuit (MN: Matching Network) 16 and is input to the amplifier 10. The matching circuit 16 matches the impedance seen from the distributor 18 to the matching circuit 16 and the impedance seen from the matching circuit 16 to the amplifier 10. The amplifier 10 (first amplifier) has nodes N1 (first node) and N3. The amplifier 10 amplifies the signal S1 input to the node N1, and outputs the amplified signal S1 as a signal S3 (third signal) to the node N3. The signal S3 amplified by the amplifier 10 is input to the synthesizer 20.

[0014] The signal S2 passes through the matching circuit 17 and is input to the amplifier 11. The matching circuit 17 matches the impedance seen from the distributor 18 to the matching circuit 17 and the impedance seen from the matching circuit 17 to the amplifier 11. The amplifier 11 (second amplifier) has nodes N2 (second node) and N4. The amplifier 11 amplifies the signal S2 input to the node N2, and outputs the amplified signal S2 as a signal S4 (fourth signal) to the node N4. The signal S4 amplified by the amplifier 11 is input to the synthesizer 20.

[0015] The synthesizer 20 synthesizes the signals S3 and S4, and outputs the synthesized signal as the output signal So to the output terminal Tout. A capacitor C02 for DC cut is connected between the synthesizer 20 and the output terminal Tout.

[0016] Path 28 directly connects nodes N1 and N2 in a DC manner via matching circuits 16, 17, and distributor 18. As a result, nodes N1 and N2 are short-circuited in a DC manner and have substantially the same potential in DC. Path 27 directly connects nodes N3 and N4 in a DC manner via synthesizer 20. As a result, nodes N3 and N4 are short-circuited in a DC manner and have substantially the same potential in DC.

[0017] A bias circuit (BC: Bias Circuit) 12 is connected between node N5 in path 28 and pad 13. Pad 13 is a pad that supplies an input bias voltage to nodes N1 and N2, which are the input nodes of amplifiers 10 and 11. Bias circuit 12 directly connects pad 13 and node N5 and suppresses the leakage of signal S1 flowing through node N5 to pad 13. Nodes N1 and N2 are directly connected in a DC manner by path 28. Therefore, substantially the same input bias voltage is applied to nodes N1 and N2. Bias circuit 12 may be connected at any location in path 28.

[0018] A bias circuit 14 is connected between node N6 in path 27 and pad 15. Pad 15 is a pad that supplies an output bias voltage to nodes N3 and N4, which are the output nodes of amplifiers 10 and 11. Bias circuit 14 directly connects pad 15 and node N6 and suppresses the leakage of signal S3 flowing through node N6 to pad 15. Nodes N3 and N4 are directly connected in a DC manner by path 27. Therefore, substantially the same output bias voltage is applied to nodes N3 and N4.

[0019] A matching circuit or a harmonic processing circuit may be connected between node N3 and synthesizer 20. A matching circuit or a harmonic processing circuit may be connected between node N4 and synthesizer 20. The matching circuit is a circuit that matches the impedance seen from the matching circuit to node N3 or N4 and the impedance seen from the matching circuit to synthesizer 20. The harmonic processing circuit is a circuit that reflects the harmonic signals in signal S3 or S4 to node N3 or N4. The harmonic signals are, for example, the second harmonic or the third harmonic when the operating band of amplifier circuit 100 is taken as the fundamental wave.

[0020] Amplifiers 10 and 11 are, for example, FETs (Field Effect Transistors), where the source is grounded, a high-frequency signal is input to the gate, and a high-frequency signal is output from the drain. The FET is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). Each of amplifiers 10 and 11 may be provided with multiple stages of FETs. When amplifiers 10 and 11 are FETs, the bias voltages supplied to pads 13 and 15 are the gate bias voltage and the drain bias voltage, respectively.

[0021] When amplifier circuit 100 is a balanced amplifier, divider 18 distributes input signal Si into signals S1 and S2 such that the amplitudes of signals S1 and S2 are substantially the same and the phase of signal S2 at the center frequency fo of the operating band lags the phase of signal S1 by approximately 90°. Synthesizer 20 delays the phase of signal S3 by 90° and synthesizes it with signal S4. Amplifier circuit 100 may be an amplifier circuit other than a balanced amplifier.

[0022] [Example of Bias Circuit] Figures 2 to 4 are circuit diagrams showing Examples 1 to 3 of the bias circuit in Embodiment 1. As shown in FIG. 2, in Example 1, the bias circuit 12 includes a transmission line TL1 and a capacitor C1. The first end of the transmission line TL1 is electrically connected to the node N5, and the second end of the transmission line TL1 is electrically connected to the pad 13. The transmission line TL1 is a λ / 4 transmission line. The electrical length of the λ / 4 transmission line is, for example, λ / 4. Here, λ is the wavelength of the center frequency fo of the operating band of the amplifier circuit 100. The electrical length of the λ / 4 transmission line does not have to be exactly λ / 4, and may be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to the following examples. A capacitor C1 is shunt-connected to the node between the transmission line TL1 and the pad 13. Thereby, the bias voltage supplied to the pad 13 is supplied to the node N5, and the signals S1 or S2 passing through the node N5 are less likely to leak to the pad 13.

[0023] As shown in FIG. 3, in Example 2, an inductor L1 is used instead of the transmission line TL1 in FIG. 2. Also in Example 2 of FIG. 3, by appropriately setting the inductance of the inductor L1 and the capacitance of the capacitor C1, the signals S1 or S2 passing through the node N5 are less likely to leak to the pad 13.

[0024] As shown in FIG. 4, Example 3 is an example using a CRLH (Composite Right / Left Handed) line. A transmission line TL2 and an inductor L2 are serially connected between the node N5 and the pad 13. A capacitor C2 is shunt-connected to the node between the inductor L2 and the pad 13. Capacitors C3 and C4 are serially connected between the node between the transmission line TL2 and the inductor L2 and the ground. An inductor L3 is shunt-connected to the node between the capacitors C3 and C4. Also in Example 3 of FIG. 4, by appropriately setting the inductances of the inductors L2 and L3 and the capacitances of the capacitors C2 to C4, the signals S1 or S2 passing through the node N5 are less likely to leak to the pad 13. A CRLH line other than the circuit of FIG. 4 may be used.

[0025] [Examples of the distributor] Figs. 5 to 7 are circuit diagrams showing Examples 1 to 3 of the distributor in Example 1. As shown in Fig. 5, in Example 1, the distributor 18 uses a Wilkinson-type distributor. The Wilkinson-type distributor 18a includes transmission lines TL11, TL12, and a resistor R11. The transmission line TL11 is connected between the ends T1 and T2, and the transmission line TL12 is connected between the ends T1 and T3. The transmission lines TL11 and TL12 are λ / 4 transmission lines. The resistance value of the resistor R11 is, for example, twice the reference impedance. A transmission line TL13 is connected between the transmission line TL12 and the end T3. The transmission line TL13 is a λ / 4 transmission line. The Wilkinson-type distributor distributes the input signal Si input to the end T1 into signals S1 and S2 of the same amplitude, and the transmission line TL13 delays the phase of the signal S2 at the center frequency fo by approximately 90° from the phase of the signal S1. The ends T2 and T3 are connected directly in terms of DC through the transmission lines TL11 to TL13. Note that 90° does not have to be exactly 90°, and for example, when converted to the wavelength λ, it may be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to the following examples.

[0026] As shown in Fig. 6, in Example 2, the distributor 18 uses a distributed constant type branch line coupler as a 90° coupler. A transmission line TL21 is connected between the ends T1 and T2. A transmission line TL22 is connected between the ends T2 and T3. A transmission line TL23 is connected between the ends T3 and T4. A transmission line TL24 is connected between the ends T4 and T1. The transmission lines TL21 to TL24 are λ / 4 transmission lines. The input signal Si input to the end T1 is distributed into the signals S1 and S2 and output from the ends T2 and T3, respectively. The phase of the signal S2 at the center frequency fo is delayed by approximately 90° from the phase of the signal S1. The end T4 is connected to the reference potential through, for example, the reference impedance (for example, 50 Ω). The ends T2 and T3 are connected directly in terms of DC through the transmission lines TL21 to TL24.

[0027] As shown in Fig. 7, in Example 3, the distributor 18 uses a concentrated multiplier type branch line coupler. An inductor L11 is connected between terminals T1 and T2. An inductor L12 is connected between terminals T2 and T3. An inductor L13 is connected between terminals T3 and T4. An inductor L14 is connected between terminals T4 and T1. The node between inductors L14 and L11 is grounded via a capacitor C11. The node between inductors L11 and L12 is grounded via a capacitor C12. The node between inductors L12 and L13 is grounded via a capacitor C13. The node between inductors L13 and L14 is grounded via a capacitor C14. By appropriately setting the inductances of inductors L11 to L14 and the capacitances of capacitors C11 to C14, the input signal Si input to terminal T1 is approximately equally distributed to signals S1 and S2 and output from terminals T2 and T3 respectively, and the phase of signal S2 at the center frequency fo lags the phase of signal S1 by approximately 90°. Terminal T4 is connected to the reference potential via, for example, a reference impedance. Terminals T2 and T3 are connected directly in terms of DC via inductors L11 to L14.

[0028] The matching circuits 16 and 17 are passive circuits including inductors and capacitors. Capacitors are not connected in series in the paths through which signals S1 and S2 flow respectively. As a result, terminal T2 and node N1 are connected directly in terms of DC, and terminal T3 and node N2 are connected directly in terms of DC. The matching circuits 16 and 17 are, for example, circuits in which inductors are connected in series, a π-type circuit of CLC configuration, a T-type circuit of LCL configuration, an L-type circuit of LC configuration, or a circuit combining these circuits.

[0029] [Example of an amplification circuit using a 90° coupler] FIG. 8 is a circuit diagram of the amplifier circuit according to Embodiment 1, and is an example in which the 90° couplers of FIG. 6 are used for the distributor 18 and the synthesizer 20. As shown in FIG. 8, the terminal T1 of the distributor 18 is connected to the input terminal Tin via a capacitor C01 for DC cut. The terminal T2 is connected to the node N1 via the matching circuit 16. The terminal T3 is connected to the node N2 via the matching circuit 17. The terminal T4 is terminated via a capacitor C03 for DC cut and a resistor R01. The terminal T1 of the synthesizer 20 is electrically connected to the node N3. The terminal T2 is terminated via a capacitor C04 for DC cut and a resistor R02. The terminal T3 is connected to the output terminal Tout via a capacitor C02 for DC cut. The terminal T4 is connected to the node N4. The resistance values of the resistors R01 and R02 are the reference impedance (for example, 50 Ω). In the synthesizer 20, the signals S3 and S4 input to the terminals T1 and T4 are combined into the output signal So, where the phase of the signal S3 at the center frequency fo lags behind the phase of the signal S4 by approximately 90°.

[0030] The path 28 is connected directly between the nodes N1 and N2 via the distributor 18. Therefore, by connecting the bias circuit 12 to the node N5 at any position on the path 28, an almost identical input bias voltage can be applied to the amplifiers 10 and 11. The path 27 is connected directly between the nodes N3 and N4 via the synthesizer 20. Therefore, by connecting the bias circuit 14 to the node N6 at any position on the path 27, an almost identical output bias voltage can be applied to the amplifiers 10 and 11. The capacitor C01 can suppress the flow of a DC current to the input terminal Tin due to the input bias voltage. The capacitor C02 can suppress the flow of a DC current to the output terminal Tout due to the output bias voltage. The capacitors C03 and C04 can suppress the flow of a DC current through the resistors R01 and R02.

[0031] [Comparative Example 1] FIG. 9 is a circuit diagram of the amplifier circuit according to Comparative Example 1. As shown in FIG. 9, in the amplifier circuit 110 of Comparative Example 1, DC cut capacitors C01a and C01b are respectively connected between the distributor 18 and nodes N1 and N2. DC cut capacitors C02a and C02b are respectively connected between the synthesizer 20 and nodes N3 and N4. A pad 13a is connected to a node N5a between the node N1 and the capacitor C01a via a bias circuit 12a, and a pad 13b is connected to a node N5b between the node N2 and the capacitor C01b via a bias circuit 12b. A pad 15a is connected to a node N6a between the node N3 and the capacitor C02a via a bias circuit 14a, and a pad 15b is connected to a node N6b between the node N4 and the capacitor C02b via a bias circuit 14b.

[0032] In Comparative Example 1, the nodes N1 and N2 are not directly connected in DC, and the nodes N3 and N4 are not directly connected in DC. Therefore, pads 13a and 13b are respectively connected to the nodes N5a and N5b via bias circuits 12a and 12b separately. Pads 15a and 15b are respectively connected to the nodes N6a and N6b via bias circuits 14a and 14b separately. In this way, since two pads 13a and 13b, two bias circuits 12a and 12b, two pads 15a and 15b, and two bias circuits 14a and 14b are provided, the amplifier circuit 110 becomes large-sized.

[0033] As an amplifier circuit in which an amplifier is connected in parallel between an input terminal Tin and an output terminal Tout, a Doherty amplifier circuit is known. In the Doherty amplifier circuit, the main amplifier operates in class A or class AB, and the peak amplifier operates in class C. For this reason, the input bias voltages of the main amplifier and the peak amplifier are made different. Therefore, a bias circuit for applying an input bias voltage to the main amplifier and a bias circuit for applying an input bias voltage to the peak amplifier are provided separately. However, when the input bias voltages of the amplifiers 10 and 11 can be made the same as in the first embodiment and the first comparative example, if two pads 13a and 13b and two bias circuits 12a and 12b are provided as in the first comparative example, the amplifier circuit becomes large.

[0034] The pad 13 is a metal layer such as a copper layer, a gold layer, or an aluminum layer provided on a dielectric substrate. A bonding wire or a bump or the like is joined to the pad 13. For this reason, the size of the pad 13 is 50 μm × 50 μm or more, and as an example, it becomes very large at 100 μm × 100 μm. Therefore, if two pads 13a and 13b are provided as in the first comparative example, the amplifier circuit becomes large.

[0035] [Description of the First Embodiment] According to the first embodiment, a node N5 (third node) for supplying an input bias voltage to the amplifiers 10 and 11 is provided only at one location in a path 28 that directly connects the nodes N1 and N2. Thereby, an input bias voltage can be supplied to the amplifiers 10 and 11 using one bias circuit 12 and one pad 13. Therefore, the amplifier circuit 100 can be miniaturized. In FIGS. 1 and 8, the node N5 is provided between the distributor 18 and the node N1, but it may be provided between the distributor 18 and the node N2.

[0036] The bias circuit 12 directly connects the pad 13 and the node N5 to suppress the leakage of the signals S1 and S2 to the pad 13. In this way, the number of the pads 13 and the bias circuit 12 can be reduced, and the amplifier circuit 100 can be miniaturized. For example, the absolute value of the impedance (e.g., resistance value) in DC between the pad 13 and the node N5 is smaller than the absolute value of the impedance at the center frequency fo of the operating band between the pad 13 and the node N5, and is, for example, 1 / 10 times or less, 1 / 100 times or less, and 1 / 1000 times or less. Also, the leakage from the node N5 to the pad 13 at the center frequency fo is -20 dB or less, -40 dB or less, and -60 dB or less. The same applies to the bias circuit in the following embodiments.

[0037] As shown in FIG. 8, a branch-line coupler is used as the divider 18. An input signal Si is input to the end T1 (the first end) of the branch-line coupler. The signal S1 is output from the end T2 (the second end). The end T3 (the third end) is located diagonally to the end T1, and the signal S2 is output from the end T3. The end T4 (the fourth end) is located diagonally to the end T2 and is terminated at the reference potential. Thereby, the nodes N1 and N2 are connected by a DC path 28 via the divider 18.

[0038] The first end of the capacitor C03 is connected to the end T4. The first end of the resistor R01 is connected to the second end of the capacitor C03, and the second end of the resistor R01 is connected to the reference potential. Thereby, the flow of the DC current from the path 28 to the reference potential via the resistor R01 can be suppressed. The resistance value of the resistor R01 is the reference impedance (e.g., 50 Ω). The resistance value of the resistor R01 does not have to be exactly the reference impedance, and may be, for example, 0.8 times or more and 1.2 times or less of the reference impedance.

[0039] [Embodiment 2] FIG. 10 is a circuit diagram of the amplifier circuit according to Embodiment 2. As shown in FIG. 10, in the amplifier circuit 102 of Embodiment 2, a node N5a is provided between the node N1 and the terminal T2, and a node N5b is provided between the node N2 and the terminal T3. A capacitor C01a for DC cut is provided between the node N5a and the terminal T2, and a capacitor C01b for DC cut is provided between the node N5b and the terminal T3.

[0040] A bias circuit 12a is provided between the node N5a and N7, and a bias circuit 12b is provided between the node N5b and N7. A pad 13 is electrically connected to the node N7. The bias circuit 12a connects the pad 13 and the node N5a in DC, and suppresses the leakage of the signal S1 flowing through the node N5a to the pad 13 and the node N5b. The bias circuit 12b connects the pad 13 and the node N5b in DC, and suppresses the leakage of the signal S2 flowing through the node N5b to the pad 13 and the node N5a. Other circuit configurations are the same as those in FIG. 1 of Embodiment 1, and the description is omitted.

[0041] [Examples of Bias Circuits] FIGS. 11 to 13 are circuit diagrams showing Examples 1 to 3 of the bias circuit in Embodiment 2. As shown in FIG. 11, in Example 1, the bias circuits 12a and 12b have the same circuit configuration as the bias circuit 12 in FIG. 2. In the bias circuits 12a and 12b, the first ends of the transmission lines TL1 are connected to the nodes N5a and N5b respectively, and the second ends of the transmission lines TL1 are connected to the node N7. The capacitor C1 is shunt-connected to the node between the node N7 and the transmission line TL1. Thereby, the bias voltage supplied to the pad 13 is supplied to the nodes N5a and N5b, and the signal S1 passing through the node N5a and the signal S2 passing through the node N5b are less likely to leak to the pad 13.

[0042] As shown in FIG. 12, in Example 2, the bias circuits 12a and 12b have the same circuit configuration as the bias circuit 12 in FIG. 3. In the bias circuits 12a and 12b, an inductor L1 is used instead of the transmission line TL1 in FIG. 11. Also in Example 2 of FIG. 12, by appropriately setting the inductance of the inductor L1 and the capacitance of the capacitor C1, the signals S1 passing through the node N5a and the signals S2 passing through the node N5b are less likely to leak to the pad 13.

[0043] As shown in FIG. 13, in Example 3, the bias circuits 12a and 12b have the same circuit configuration as the bias circuit 12 in FIG. 4. Also in Example 3 of FIG. 13, by appropriately setting the inductances of the inductors L2 and L3 and the capacitances of the capacitors C2 to C4, the signals S1 passing through the node N5a and the signals S2 passing through the node N5b are less likely to leak to the pad 13. CRLH lines other than the circuit in FIG. 13 may be used.

[0044] [Examples of Dividers] FIGS. 14 and 15 are circuit diagrams showing Example 4 and Example 5 of the divider in Embodiment 2. As shown in FIG. 14, in Example 4, the divider 18 is a distributed coupling type coupler in which the transmission lines TL41 and TL42 are electromagnetically coupled. The input signal Si input to the terminal T1 is distributed into the signals S1 and S2 and output to the terminals T2 and T3, respectively. The terminal T4 is connected to the reference potential via, for example, a reference impedance. The phase of the signal S2 at the center frequency fo lags behind the phase of the signal S1 by approximately 90°. By appropriately setting the coupling coefficient between the transmission lines TL41 and TL42, the ratio of the amplitudes of the signals S1 and S2 can be appropriately set.

[0045] As shown in Fig. 15, in Example 5, the distributor 18 is a closely wound coil coupler that electromagnetically couples inductors L21 and L22. The input signal Si input to terminal T1 is distributed into signals S1 and S2, and the phase of signal S2 at the center frequency fo lags behind the phase of signal S1 by approximately 90°. By appropriately setting the inductances of inductors L21 and L22 and the coupling coefficient between inductors L21 and L22, the ratio of the amplitudes of signals S1 and S2 can be appropriately set. Terminal T4 is connected to the reference potential via, for example, a reference impedance.

[0046] According to Example 2, the pad 13 to which the bias voltage is supplied is a single pad 13. The bias circuit 12a (first bias circuit) directly connects the single pad 13 and the node N1 to suppress the leakage of signal S1 to the single pad 13. The bias circuit 12b (second bias circuit) directly connects the single pad 13 and the node N2 to suppress the leakage of signal S2 to the single pad 13. Thereby, compared with Comparative Example 1 in Fig. 9, the number of pads 13 can be made one. Thereby, the amplifier circuit 102 can be miniaturized.

[0047] When using the distributors of Example 4 in Fig. 14 and Example 5 in Fig. 15 as the distributor 18 in Fig. 10, terminals T2 and T3 are not directly connected via the distributor 18. For this reason, it is difficult to use a single bias circuit 12 as in Example 1. Therefore, a single pad 13, bias circuits 12a and 12b as described in Figs. 11 to 13 are used. Thereby, compared with Comparative Example 1, the number of pads 13 can be made one, and the amplifier circuit 102 can be miniaturized. When using Example 4 in Fig. 14 and Example 5 in Fig. 15 as the distributor 18, the capacitor for DC cut may be provided between the input terminal Tin and the distributor 18 instead of being provided between the distributor 18 and the nodes N1 and N2.

[0048] As the distributor 18 in FIG. 10, the distributors of Examples 1 to 3 having the circuit configurations described in FIGS. 5 to 7 may be used. As shown in FIG. 10, the first terminal of the capacitor C01a (first capacitor) is connected to the distributor 18, and the second terminal of the capacitor C01a is connected to the node N1. The first terminal of the capacitor C01b (second capacitor) is connected to the distributor 18, and the second terminal of the capacitor C01b is connected to the node N2. In this case, the nodes N1 and N2 are DC-isolated. Therefore, the single pad 13, bias circuits 12a and 12b as described in FIGS. 11 to 13 are used. Thereby, the number of pads 13 can be made one as compared with Comparative Example 1, and the amplifier circuit 102 can be miniaturized.

[0049] [Simulation] In Example 2, the passing characteristics of the nodes N5a and N5b and the isolation characteristics between the nodes N5a and N5b were simulated.

[0050] FIG. 16 is a circuit diagram of the circuit used in the simulation. As shown in FIG. 16, a node N5a is provided in the path between the ports P1 and P2. A node N5b is provided in the path between the ports P3 and P4. A bias circuit 12a and a transmission line TL4 are connected in series between the node N5a and the node N7. A bias circuit 12b and a transmission line TL5 are connected in series between the node N5b and the node N7. The circuit configurations of the bias circuits 12a and 12b are the same as those of Example 1 in FIG. 11. A transmission line TL3 is provided between the node N7 and the power supply B. The transmission lines TL3 to TL5 correspond to the lines that electrically connect the node N7 to the power supply B, the bias circuits 12a and 12b, respectively.

[0051] The characteristic impedances at 3.5 GHz of transmission lines TL1 and TL3 to TL5 were each set to 80 Ω. The electrical length of transmission line TL1 at 3.5 GHz was converted to a phase of 90°, and the electrical lengths of transmission lines TL3 to TL5 at 3.5 GHz were each converted to a phase of 5°. The capacitance of capacitor C1 was set to 100 pF, and the DC bias voltage supplied by power supply B was set to -2.6 V. Ports P1 to P4 are terminated with 50 Ω.

[0052] FIG. 17 is a diagram showing S21 and S41 in the simulation. FIG. 18 is a diagram showing S43 and S23 in the simulation. S21, S41, S43, and S23 correspond to the S parameters between the respective ports. In FIGS. 17 and 18, the absolute values of S21, S41, S43, and S23 are shown in dB. S21 represents the passing characteristic from port P1 to P2, S41 represents the isolation characteristic from port P1 to P4, S43 represents the passing characteristic from port P1 to P2, and S23 represents the isolation characteristic from port P3 to P2. The frequency fo corresponding to the center frequency of the operating band of the amplifier circuit is 3.5 GHz.

[0053] As shown in FIGS. 17 and 18, S21 and S43 at the frequency fo are approximately 0 dB, and there is almost no loss of signals S1 and S2 at nodes N5a and N5b. At 7 GHz, S21 and S43 become minimal because at 7 GHz, the electrical length of transmission line TL1 corresponds to 1 / 2 of the wavelength. S41 and S23 at the frequency fo are approximately -80 dB or less, and the isolation characteristics are good.

[0054] As in the above simulation, in the second embodiment, while suppressing the loss of signals S1 and S2 at nodes N5a and N5b, it is possible to suppress the leakage of signal S1 to node N5a and the leakage of signal S2 to node N5b.

[0055] [Embodiment 3] FIG. 19 is a circuit diagram of the amplifier circuit according to Embodiment 3. As shown in FIG. 19, in the amplifier circuit 104 of Embodiment 3, a bias circuit 12 is provided between the pad 13 and the node N5a, and a bias circuit 12c is provided between the nodes N5a and N5b. The bias circuit 12 is connected to the pad 13 and the node N5a in a DC manner to suppress the leakage of the signal S1 flowing through the node N5a to the pad 13. The bias circuit 12c is connected to the nodes N5a and N5b in a DC manner to suppress the leakage of the signal S1 flowing through the node N5a to the node N5b and to suppress the leakage of the signal S2 flowing through the node N5b to the node N5a. The other circuit configurations are the same as those in FIG. 10 of Embodiment 2, and the description thereof is omitted.

[0056] [Examples of Bias Circuits] FIGS. 20 to 21 are circuit diagrams showing Example 1 and Example 2 of the bias circuit in Embodiment 3. As shown in FIG. 20, in Example 1, the bias circuit 12 has the same circuit configuration as the bias circuit 12 in FIG. 2. The bias circuit 12 supplies the bias voltage supplied to the pad 13 to the node N5a and suppresses the leakage of the signal S1 passing through the node N5a to the pad 13.

[0057] In the bias circuit 12c, the first end of the transmission line TL1a is electrically connected to the node N5a, and the second end of the transmission line TL1a is connected to the node N8. The first end of the transmission line TL1b is electrically connected to the node N5b, and the second end of the transmission line TL1b is connected to the node N8. The capacitor C1 is shunt-connected to the node N8. The transmission lines TL1a and TL1b are λ / 4 transmission lines. The bias circuit 12c supplies the bias voltage supplied to the node N5a to the node N5b, suppresses the leakage of the signal S1 passing through the node N5a to the node N5b, and suppresses the leakage of the signal S2 passing through the node N5b to the node N5a.

[0058] As shown in FIG. 21, in Example 2, inductors L1, L1a, and L1b are respectively used instead of the transmission lines TL1, TL1a, and TL1b in FIG. 20. By appropriately setting the inductances of inductors L1, L1a, and L1b and the capacitance of capacitor C1, the signal S1 passing through node N5a is less likely to leak to pad 13 and node N5b, and the signal S2 passing through node N5b is less likely to leak to node N5a. Bias circuits 12 and 12c may include CRLH lines.

[0059] According to Example 3, the pad 13 to which the bias voltage is supplied is a single pad 13. The bias circuit 12 (first bias circuit) directly connects the single pad 13 and node N1 to suppress the leakage of the signal S1 to the single pad 13. The bias circuit 12c (second bias circuit) directly connects nodes N1 and N2 to suppress the leakage of the signal S1 to node N2 and the leakage of the signal S2 to node N1. Thereby, compared with Comparative Example 1 in FIG. 9, the number of pads 13 can be made one. Thereby, the amplifier circuit 104 can be miniaturized.

[0060] As the divider 18 in FIG. 10 of Example 2 and FIG. 19 of Example 3, the dividers in Example 4 of FIG. 14 and Example 5 of FIG. 15 may be used. In this case, terminals T2 and T3 are not directly connected via the divider 18. For this reason, it is difficult to use a single bias circuit 12 as in Example 1. Therefore, a single pad 13, bias circuits 12 and 12c as described in FIGS. 20 and 21 are used. Thereby, compared with Comparative Example 1, the number of pads can be made one, and the amplifier circuit 104 can be miniaturized.

[0061] As the distributor 18 in FIG. 10 of Example 2 and FIG. 19 of Example 3, the distributors of Examples 1 to 3 having the circuit configurations described in FIGS. 5 to 7 may be used. In this case, as shown in FIG. 19, when the capacitors C01a and C01b are provided, the nodes N1 and N2 are DC-isolated. Therefore, the single pad 13, bias circuits 12 and 12c as described in FIGS. 20 and 21 are used. As a result, the number of pads can be made one as compared with Comparative Example 1, and the amplifier circuit 104 can be miniaturized.

[0062] [Example 4] Example 4 is an example of an LMBA (Load Modulated Balanced Amplifier). FIG. 22 is a circuit diagram of the amplifier circuit according to Example 4. As shown in FIG. 22, in the amplifier circuit 106 of Example 4, a control amplifier 21, amplifiers 10 and 11 are connected in parallel between the input terminal Tin and the output terminal Tout. A high-frequency signal is input as the input signal Sin to the input terminal Tin. A distributor 24 (another distributor) distributes the input signal Sin input to the input terminal Tin into a signal S5 (the fifth signal) and an input signal Si.

[0063] The signal S5 is input to the control amplifier 21 via the matching circuit 26 and the capacitor C05. The matching circuit 26 matches the impedance seen from the distributor 24 to the matching circuit 26 and the impedance seen from the matching circuit 26 to the control amplifier 21. The capacitor C05 is a DC-cut capacitor. The control amplifier 21 amplifies the signal S5 and outputs the amplified signal as a signal S6 (the sixth signal). The signal S6 amplified by the control amplifier 21 is output to the terminal T2 of the synthesizer 20.

[0064] A bias circuit 22 is provided between the node N9 between the control amplifier 21 and the capacitor C05 and the pad 23. The pad 23 is a pad that supplies an input bias voltage to the input node of the control amplifier 21. The bias circuit 22 connects the pad 23 and the node N9 in DC and suppresses the leakage of the signal S5 flowing through the node N9 to the pad 23.

[0065] A bias circuit 14 is provided between a node N6 between the control amplifier 21 and an end T2 of the synthesizer 20 and the pad 15. The pad 15 is a pad that supplies an output bias voltage to input nodes of the control amplifier 21, the amplifiers 10 and 11. The bias circuit 14 directly connects the pad 15 and the node N6 and suppresses leakage of a signal S6 flowing through the node N5 to the pad 15.

[0066] The input signal Si distributed by the distributor 24 is input to the amplifier circuit 100. The amplifier circuit 100 is the same as the amplifier circuit 100 of the first embodiment except that the bias circuit 14 and the pad 15 are not provided, the synthesizer 20 is a 90° coupler in FIG. 5, and the signal S6 is input to the end T2 of the synthesizer 20, and the description thereof is omitted.

[0067] The control amplifier 21 corresponds to the main amplifier of the Doherty amplifier circuit, and the amplifiers 10 and 11 correspond to the peak amplifiers of the Doherty amplifier circuit. The control amplifier 21 operates in class AB or class B, and the amplifiers 10 and 11 operate in class C. When the input power of the input signal Sin is small, the control amplifier 21 mainly amplifies the input signal Sin. When the input power increases, in addition to the control amplifier 21, the amplifiers 10 and 11 amplify the peak of the input signal Sin. Thereby, the control amplifier 21 and the amplifiers 10 and 11 amplify the input signal Sin.

[0068] When the power of the input signal Si is low and amplifiers 10 and 11 are not operating, the signal S6 input to the terminal T2 of the synthesizer 20 is divided into two equal parts of signal S6 / 2 at terminals T1 and T4 respectively. The phase of the signal S6 / 2 at terminal T4 lags behind the phase of the signal S6 / 2 at terminal T1 by 90°. The signal S6 / 2 is reflected at terminals T1 and T4. The signal S6 / 2 is combined at terminal T3. The phase of the signal S6 / 2 reflected at terminal T1 is 90° later than the phase of the signal S6 / 2 reflected at terminal T4. As a result, at terminal T3, the phases of the two signals S6 / 2 are aligned and the signal S6 is combined. The combined signal S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient seen from the synthesizer 20 to the amplifiers 10 and 11 is close to 1, and the load impedance of the amplifiers 10 and 11 is substantially high.

[0069] When the power of the input signal Sin is high and amplifiers 10 and 11 are operating, the phase of the signal S4 lags behind the phase of the signal S3 by 90°. The phase of the signal S6 / 2 at terminal T4 lags behind the phase of the signal S6 / 2 at terminal T1 by 90°. The signal S3 + S6 / 2 combined at terminal T1 and the signal S4 + S6 / 2 combined at terminal T4 are combined at terminal T3. The combined signal S3 + S4 + S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient seen from the synthesizer 20 to the amplifiers 10 and 11 is less than 1, and the larger the amplitudes of the signals S3 and S4, the smaller the reflection coefficient. Therefore, the load impedance of the amplifiers 10 and 11 is substantially reduced. In this way, the synthesizer 20 modulates the load impedance seen from the amplifiers 10 and 11 to the synthesizer 20 depending on the amplitudes of the signals S3 and S4.

[0070] In a Doherty amplifier circuit, the synthesizer that combines the signal amplified by the main amplifier and the signal amplified by the peak amplifier is provided with a λ / 4 line as an impedance converter. The load impedance of the main amplifier is modulated using the λ / 4 line. In this case, when the frequency changes, it is difficult to broaden the operating bandwidth because the electrical length of the λ / 4 line deviates from λ / 4. In one example, the specific bandwidth of the synthesizer using the λ / 4 line is about 8%.

[0071] In the LMBA as in Example 4, the synthesizer 20 modulates the loads of the amplifiers 10 and 11 using the signal S6, synthesizes the signals S3, S4, and S6, and outputs the synthesized signal as the output signal So. Thereby, it becomes possible to widen the operating bandwidth. For example, the ratio bandwidth of a 90° coupler is at most 120% in a commercially available 90° hybrid coupler, for example.

[0072] In the LMBA, the input bias voltage of the amplifier 10 and the input bias voltage of the amplifier 11 can be made substantially the same. Therefore, by using the amplifier circuits of Examples 1 to 3 for the amplifier circuit including the amplifiers 10 and 11, the amplifier circuit 106 can be miniaturized.

[0073] The DC path 29 directly connects the node N3 of the amplifier 10 and the output node of the control amplifier 21 via the synthesizer 20. A node N6 (fourth node) that supplies a bias voltage to the amplifier 10 and the control amplifier 21 is provided at only one location in the DC path 29. Thereby, the pads 15 and the bias circuit 14 that apply the output bias voltage to the amplifier 10 and the control amplifier 21 can be made one each. Therefore, the amplifier circuit 106 can be miniaturized.

[0074] The DC path 29 may directly connect the nodes N3 and N4 and the output node of the control amplifier 21 via the synthesizer 20. A node N6 that supplies a bias voltage to the amplifiers 10 and 11 and the control amplifier 21 may be provided at only one location in the DC path 29. Thereby, the pads 15 and the bias circuit 14 that apply the output bias voltage to the amplifiers 10 and 11 and the control amplifier 21 can be made one each. Therefore, the amplifier circuit 106 can be miniaturized.

[0075] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Description of Symbols

[0076] 10 (First Amplifier), 11 (Second Amplifier) Amplifiers 12 (First Bias Circuit), 12a (First Bias Circuit), 12b (Second Bias Circuit), 12c (Second Bias Circuit), 14, 14a, 14b, 22 Bias Circuits 13, 13a, 13b, 15, 15a, 15b, 23 Pads 16, 17, 26 Integrated Circuits 18, 24 (Another Distributor) Distributors 20 Synthesizer 21 Control Amplifier 27, 28 Paths 29 DC Path 100, 102, 104, 106, 110 Amplification Circuits S1 (First Signal), S2 (Second Signal), S3 (Third Signal), S4 (Fourth Signal), S5 (Fifth Signal), S6 (Sixth Signal) Si Input Signal So Output Signal N1 (First Node), N2 (Second Node), N5 (Third Node), N6 (Fourth Node) Nodes C01a (First Capacitor), C01b (Second Capacitor) Capacitors

Claims

1. A distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a path that directly connects the first node and the second node via the distributor, a synthesizer that synthesizes the third signal and the fourth signal, an amplifier circuit in which only one third node for supplying a bias voltage to the first amplifier and the second amplifier in the path is provided.

2. a pad to which the bias voltage is supplied, a bias circuit that directly connects the pad and the third node and suppresses leakage of the first signal and the second signal to the pad, according to the amplifier circuit of Claim 1.

3. The amplifier circuit according to Claim 1 or Claim 2, wherein the distributor includes a branch-line coupler having a first end to which the input signal is input, a second end from which the first signal is output, a third end located diagonally to the first end from which the second signal is output, and a fourth end located diagonally to the second end and terminated at a reference potential.

4. a capacitor having a first end connected to the fourth end of the branch-line coupler, a resistor having a first end connected to the second end of the capacitor and a second end connected to the reference potential, according to the amplifier circuit of Claim 3.

5. A distributor that distributes an input signal into a first signal and a second signal, a first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, a second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, a synthesizer that synthesizes the third signal and the fourth signal, a single pad to which a bias voltage is supplied, a first bias circuit that directly connects the single pad and the first node and suppresses leakage of the first signal to the single pad, a second bias circuit that directly connects the single pad and the second node and suppresses leakage of the second signal to the single pad, an amplifier circuit comprising.

6. A distributor that distributes an input signal into a first signal and a second signal, A first amplifier having a first node to which the first signal is input, amplifying the first signal input to the first node, and outputting the amplified first signal as a third signal, A second amplifier having a second node to which the second signal is input, amplifying the second signal input to the second node, and outputting the amplified second signal as a fourth signal, A synthesizer that synthesizes the third signal and the fourth signal, A single pad to which a bias voltage is supplied, A first bias circuit that connects the single pad and the first node in a direct current manner to suppress leakage of the first signal to the single pad, A second bias circuit that connects the first node and the second node in a direct current manner to suppress leakage of the first signal to the second node and leakage of the second signal to the first node, An amplifier circuit comprising: **Claim 7** The amplifier circuit according to claim 5 or claim 6, wherein a first end that outputs the first signal of the distributor and a second end that outputs the second signal of the distributor are not connected in a direct current manner via the distributor. **Claim 8** A first end that outputs the first signal of the distributor and a second end that outputs the second signal of the distributor are connected in a direct current manner via the distributor, A first capacitor having a first end connected to the distributor and a second end connected to the first node, The amplifier circuit according to claim 5 or claim 6, further comprising a second capacitor having a first end connected to the distributor and a second end connected to the second node. **Claim 9** Another distributor that distributes a high-frequency signal into the input signal and a fifth signal, A control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal, Comprising: The synthesizer modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal. The amplifier circuit according to any one of claims 1, 5, and 6. **Claim 10** A direct current path that connects the output node of the first amplifier and the output node of the control amplifier in a direct current manner via the synthesizer, The amplifier circuit according to claim 9, wherein a fourth node that supplies a bias voltage to the first amplifier and the control amplifier in the direct current path is provided at only one location.

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