Amplifier circuit

Abstract

To provide an amplifier circuit that can prevent deterioration in characteristics.SOLUTION: An amplifier circuit comprises: a distributor 16 that distributes an input signal to a first signal and a second signal the phase of which is delayed by 90° compared to that of the first signal; first amplifier that amplifies the first signal and outputs the amplified first signal to a first node as a third signal; a second amplifier that amplifies the second signal and outputs the amplified second signal to a second node as a fourth signal; a first inductor that connects the first node and the second node to each other; a second inductor that connects the first node and a third node to each other; a third inductor that connects the third node and a fourth node, which outputs an output signal obtained by combining the fourth signal and the third signal the phase of which is delayed by 90° compared to that of the fourth signal, to each other; a fourth inductor that connects the second node and the fourth node to each other; a first capacitor that is shunt-connected to the third node; and a second capacitor that is shunt-connected to the fourth node. The inductance of the first inductor and the third inductor is larger than the inductance of the second inductor and the fourth inductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] As an amplifier circuit for amplifying high-frequency signals such as microwaves, a balanced amplifier is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, losses occur due to the lines connecting the amplifiers and the couplers. Also, due to the ground capacitances at the output terminals of amplifiers 4 and 5, the bandwidth becomes narrow.

[0005] This disclosure has been made in view of the above problems, and an object thereof is to suppress deterioration of characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a distributor that distributes an input signal into a first signal and a second signal whose phase is 90° later than that of the first signal, a first amplifier that amplifies the first signal and outputs the amplified first signal as a third signal to a first node, a second amplifier that amplifies the second signal and outputs the amplified second signal as a fourth signal to a second node, a first inductor that connects the first node and the second node, a second inductor that connects the first node and a third node, a third inductor that connects the third node and a fourth node that outputs an output signal in which the fourth signal and a third signal whose phase is 90° later than that of the fourth signal are combined, a fourth inductor that connects the second node and the fourth node, a first capacitor shunt-connected to the third node, a second capacitor shunt-connected to the fourth node, and an amplifier circuit in which the inductances of the first inductor and the third inductor are larger than the inductances of the second inductor and the fourth inductor.

Advantages of the Invention

[0007] According to the present disclosure, deterioration of characteristics can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Mode for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distributor that distributes an input signal into a first signal and a second signal whose phase is 90° later than that of the first signal, a first amplifier that amplifies the first signal and outputs the amplified first signal as a third signal to a first node, a second amplifier that amplifies the second signal and outputs the amplified second signal as a fourth signal to a second node, a first inductor that connects the first node and the second node, a second inductor that connects the first node and a third node, a third inductor that connects the third node and a fourth node that outputs an output signal in which the third signal and a third signal whose phase is 90° later than that of the fourth signal are synthesized, a fourth inductor that connects the second node and the fourth node, a first capacitor shunt-connected to the third node, a second capacitor shunt-connected to the fourth node, and an amplifier circuit in which the inductances of the first inductor and the third inductor are larger than the inductances of the second inductor and the fourth inductor. Thereby, deterioration of characteristics can be suppressed. (2) In the above (1), the inductances of the first inductor and the third inductor may be 0.8×√2 or more and 1.2×√2 or less of the inductances of the second inductor and the fourth inductor. Thereby, the first to fourth inductors, the first and second capacitors can function as a branch line coupler. (3) In the above (1) or (2), the reactance element may not be shunt-connected to the first node and the second node. Thereby, the first to fourth inductors and the first and second capacitors can function as a branch-line coupler. (4) In the above (3), when the center frequency of the operating band is fo and the reference impedance is Zo, the first grounding capacitance of the output node of the first amplifier, the second grounding capacitance of the output node of the second amplifier, and the capacitance C0 of the first capacitor and the second capacitor are 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), the inductance of the first inductor and the third inductor is 0.8 times or more and 1.2 times or less of Zo / (2πfo), and the inductance of the second inductor and the fourth inductor may be 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)). Thereby, the amplifier circuit can function as a balanced amplifier. (5) In the above (1) or (2), it may include a first reactance element shunt-connected to the first node and a second reactance element shunt-connected to the second node. Thereby, the first to fourth inductors, the first and second capacitors, and the first and second reactance elements can function as a branch-line coupler. (6) In (5) above, when the center frequency of the operating band is fo and the reference impedance is Zo, the capacitance component obtained by combining the first ground capacitance of the output node of the first amplifier and the first reactance element, the capacitance component obtained by combining the second ground capacitance of the output node of the second amplifier and the second reactance element, and the capacitances C0 of the first capacitor and the second capacitor are 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), the inductances of the first inductor and the third inductor are 0.8 times or more and 1.2 times or less of Zo / (2πfo), and the inductances of the second inductor and the fourth inductor may be 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)). Thereby, the amplifier circuit can be made to function as a balanced amplifier. (7) In any one of (1) to (6) above, a first semiconductor chip including the first amplifier and a first pad corresponding to the first node, and a second semiconductor chip including the second amplifier and a second pad corresponding to the second node, and the first inductor may include a first bonding wire having a first end connected to the first pad. Thereby, deterioration of characteristics can be suppressed. (8) In (7) above, the second end of the first bonding wire may be connected to the second pad. Thereby, deterioration of characteristics can be suppressed. (9) In (7) above, the first inductor may include a second bonding wire having a first end connected to the second pad. Thereby, deterioration of characteristics can be suppressed. (10) In any one of (7) to (9) above, the first pad and the first capacitor may be connected, a third bonding wire corresponding to the second inductor, the second pad and the second capacitor may be connected, and a fourth bonding wire corresponding to the fourth inductor may be provided. Thereby, the second inductor and the fourth inductor can be formed. (11) In any of (7) to (10) above, the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, the first ground capacitance of the first pad, and the second ground capacitance of the second pad may form a branch line coupler. Thereby, deterioration of the characteristics of the branch line coupler can be suppressed. (12) In any of (1) to (11) above, another distributor that distributes a high-frequency signal into the input signal and a fifth signal, and a control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal are provided. The synthesizer including the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, and the second capacitor may modulate the loads of the first amplifier and the second amplifier using the sixth signal, synthesize the third signal, the fourth signal, and the sixth signal, and output the synthesized signal as an output signal. Thereby, deterioration of the characteristics can be suppressed. [Details of Embodiments of the Present Disclosure] A specific example of the amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is intended to be indicated by the claims and to include all modifications within the meaning and scope equivalent to the claims.

[0010] [Example 1] Example 1 is an example of a balanced amplifier. FIG. 1 is a circuit diagram of the amplifier circuit according to Example 1. In FIG. 1, illustration of a bias circuit that supplies a bias voltage to amplifiers 10 and 12 is omitted.

[0011] As shown in FIG. 1, in the amplifier circuit 100 of the first embodiment, amplifiers 10 and 12 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station for mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A distributor 16 distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal). The phase of the signal S2 lags 90° with respect to the signal S1.

[0012] The signal S1 passes through a matching network 13 and is input to the amplifier 10. The matching network 13 matches the impedance seen from the distributor 16 to the matching network 13 and the impedance seen from the matching network 13 to the amplifier 10. The amplifier 10 (first amplifier) amplifies the signal S1 and outputs the amplified signal S1 as a signal S3 (third signal). The signal S3 amplified by the amplifier 10 is input to a node N1.

[0013] The signal S2 passes through a matching network 14 and is input to the amplifier 12. The matching network 14 matches the impedance seen from the distributor 16 to the matching network 14 and the impedance seen from the matching network 14 to the amplifier 12. The amplifier 12 (second amplifier) amplifies the signal S2 and outputs the amplified signal S2 as a signal S4 (fourth signal). The signal S4 amplified by the amplifier 12 is input to a node N2.

[0014] Amplifiers 10 and 12 each include transistors Q1 and Q2 such as FETs (Field Effect Transistors). In transistors Q1 and Q2, the source S is grounded, a high-frequency signal is input to the gate G, and a high-frequency signal is output from the drain D. Transistors Q1 and Q2 are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOS (Laterally Diffused Metal Oxide Semiconductor). Parasitic capacitances Cds1 and Cds2 exist between the drain D and the source S of transistors Q1 and Q2.

[0015] The synthesizer 18 is a lumped-constant type branch-line coupler and includes parasitic capacitances Cds1, Cds2, capacitors C1, C2, and inductors L1 to L4. Inductor L1 (the first inductor) electrically connects node N1 (the first node) and N2 (the second node). Inductor L2 (the second inductor) electrically connects node N1 and node N3 (the third node). Inductor L3 (the third inductor) electrically connects node N3 and N4 (the fourth node). Inductor L4 (the fourth inductor) electrically connects node N2 and N4. Capacitor C1 (the first capacitor) is shunt-connected to node N3. Capacitor C2 (the second capacitor) is shunt-connected to node N4. Node N3 is grounded via a reference resistor Ro (for example, 50 Ω). Node N4 is electrically connected to the output terminal Tout. Signals S3 and S4 are synthesized at node N4, and the synthesized signal is output from the output terminal Tout as the output signal So.

[0016] When the amplifier circuit 100 is a balanced amplifier, the distributor 16 distributes the input signal Si into signals S1 and S2 such that the amplitudes of signals S1 and S2 are substantially the same, and the phase of signal S2 at the center frequency fo of the operating band lags behind the phase of signal S1 by approximately 90°. The synthesizer 18 delays the phase of signal S3 by 90° and synthesizes it with signal S4. Note that 90° does not have to be exactly 90°, for example, it may be converted to the wavelength λ at the center frequency fo of the operating band, and may be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to the following embodiments. The amplifier circuit 100 may be an amplifier circuit other than a balanced amplifier.

[0017] [Synthesizer 18] First, the lumped - constant type branch - line coupler will be described. FIG. 2 is a circuit diagram of the lumped - constant type branch - line coupler. As shown in FIG. 2, capacitors C3 and C4 are provided instead of the parasitic capacitances Cds1 and Cds2 of the synthesizer 18 in FIG. 1, respectively. Nodes N1 to N4 are electrically connected to terminals T1 to T4, respectively. A method for determining the values of the capacitors C1 to C4 and inductors L1 to L4 of the lumped - constant type branch - line coupler will be described.

[0018] To explain how to determine the values of the capacitors C1 to C4 and inductors L1 to L4 of the lumped - constant type branch - line coupler, the distributed - constant type branch - line coupler will be described. FIG. 3 is a circuit diagram of the distributed - constant type branch - line coupler. As shown in FIG. 3, transmission lines TL1, TL2, TL3, and TL4 are connected between nodes N1 and N2, between nodes N1 and N3, between nodes N3 and N4, and between nodes N2 and N4, respectively. The lengths of the transmission lines TL1 to TL4 are λ / 4. The characteristic impedances of the transmission lines TL1 and TL3 are Zc1, and the characteristic impedances of the transmission lines TL2 and TL4 are Zc2. Assume that a signal S01 is input to terminal T1, and signals S03 and S04 are output from terminals T3 and T4. At this time, the ratio of the amplitudes of signals S03 and S04 is represented in dB as S03 - S04.

[0019] Table 1 shows the characteristic impedances Zc1 and Zc2 for realizing the ratio S03 - S04.

Table 1

[0020] In Table 1, the reference impedance Zo is set to 50 Ω. The reference impedance Zo corresponds to the impedance seen from the outside of terminals T1, T2, T3, and T4. Particularly in Fig. 1, it is the impedance seen from node N4 looking out from the output terminal Tout to which the load is connected, and it corresponds to the characteristic impedance of the transmission line connecting node N2 and the output terminal Tout.

[0021] In Table 1, the values of capacitors C1 to C4 and inductors L1 to L4 in the lumped - constant type branch - line coupler that achieves the desired S03 - S04 will be described. Let the capacitance of capacitors C1 to C4 be C0, the inductance of inductors L1 and L3 be L01, and the inductance of inductors L2 and L4 be L02. Let the center frequency of the operating band be fo. At this time, the capacitance C0, inductances L01, and L02 are determined by the following equations. C0 = 1 / (2πfo×Zc1)+1 / (2πfo×Zc2) (Equation 1) L01 = Zc1 / (2πfo) (Equation 2) L02 = Zc2 / (2πfo) (Equation 3)

[0022] In FIG. 1, when the parasitic capacitances Cds1 and Cds2 satisfy Equation 1, by setting the inductances of inductors L1 to L4 and the capacitances of capacitors C1 and C2 in FIG. 1 so as to satisfy Equations 1 to 3, the synthesizer 18 including the parasitic capacitances Cds1 and Cds2 in FIG. 1 functions as a lumped-constant type branch-line coupler. The inductances of inductors L1 to L4 and the capacitances of capacitors C1 and C2 do not have to be exactly the values calculated by Equations 1 to 3. For example, the parasitic capacitances Cds1 and Cds2, and the capacitance C0 of capacitors C1 and C2 may be 0.8 times or more and 1.2 times or less of the values obtained from Equation 1, and may be 0.9 times or more and 1.1 times or less. The inductance L01 of inductors L1 and L3 may be 0.8 times or more and 1.2 times or less of the value obtained from Equation 2, and may be 0.9 times or more and 1.1 times or less. The inductance L02 of inductors L2 and L4 may be 0.8 times or more and 1.2 times or less of the value obtained from Equation 3, and may be 0.9 times or more and 1.1 times or less.

[0023] [Comparative Example 1] FIG. 4 is a circuit diagram of the amplifier circuit according to Comparative Example 1. As shown in FIG. 4, in the amplifier circuit 110 of Comparative Example 1, a synthesizer 18 is provided separately from the parasitic capacitances Cds1 and Cds2 of the amplifiers 10 and 12. The synthesizer 18 is a distributed-constant type or lumped-constant type branch-line coupler. Other configurations are the same as those in the first embodiment.

[0024] In Comparative Example 1, a line 20 such as a bonding wire or a transmission line is provided between the amplifiers 10 and 12 and the synthesizer 18. The insertion loss increases due to the line 20. In addition, the ground parasitic capacitances Cds1 and Cds2 are added to the outputs of the amplifiers 10 and 12. For this reason, it is difficult to broaden the bandwidth of the amplifier circuit 110.

[0025] According to Example 1, in FIG. 1, the inductances L01 of inductors L1 and L3 are larger than the inductance L02 of inductors L2 and L4. Thus, as shown in Table 1, the synthesizer 18 functions as a lumped-constant type branch-line coupler. The line 20 in Comparative Example 1 forms at least part of the inductors L2 and L4 in the synthesizer 18. Therefore, the loss caused by the line 20 can be suppressed. Also, the parasitic capacitances Cds1 and Cds2 function as the capacitors C3 and C4 of the lumped-constant type branch-line coupler in FIG. 2. Thereby, broadband operation becomes possible. As described above, the degradation of characteristics can be suppressed.

[0026] As shown in Table 1, when S03 - S04 = 0 dB, Zc2 is approximately Zc1 / √2. Therefore, the inductance L01 can be set to be 0.8×√2 or more and 1.2×√2 or less of the inductance L02. Thereby, the synthesizer 18 functions as a branch-line coupler.

[0027] No reactive elements such as capacitors or inductors are shunt-connected to nodes N1 and N2. Thereby, the parasitic capacitances Cds1 and Cds2 function as the capacitors C3 and C4 in FIG. 3. Therefore, the synthesizer 18 functions as a branch-line coupler.

[0028] When the amplifier circuit 100 is a balanced amplifier, S03 - S04 = 0 dB in Table 1. In this case, Zc1 = Zo and Zc2 = Zc / √2. Therefore, from Equation 1 to Equation 3, when the capacitances of the parasitic capacitance Cds1 (the first ground capacitance of the output node of amplifier 10), the parasitic capacitance Cds2 (the second ground capacitance of the output node of amplifier 12), and the capacitors C1 and C2 are set to C0, C0 can be set to be not less than 0.8 times and not more than 1.2 times of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductance L01 of the inductors L1 and L3 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (2πfo), and can be set to be not less than 0.9 times and not more than 1.1 times. The inductance L02 of the inductors L2 and L4 can be set to be not less than 0.8 times and not more than 1.2 times of Zo / (√2×(2πfo)), and can be set to be not less than 0.9 times and not more than 1.1 times.

[0029] Note that when the amplifier circuit 100 is a balanced amplifier, the saturation powers of the amplifiers 10 and 12 are substantially the same. For example, the difference in the saturation powers of the amplifiers 10 and 12 is 1 dB or less or 2 dB or less.

[0030] [Implementation Example 1 of Example 1] FIG. 5 is a plan view showing a first implementation example of a synthesizer and an amplifier in Example 1. As shown in FIG. 5, semiconductor chips 31a, 31b and MIM (Metal Insulator Metal) capacitors 36a, 36b, lines 37a and 37b are mounted on a substrate 30. The upper surface of the substrate 30 is, for example, a conductor layer to which a reference potential such as a ground potential is supplied. The semiconductor chip 31a includes a transistor Q1 corresponding to the amplifier 10, a substrate 32a, and pads 33a and 34a provided on the substrate 32a. The semiconductor chip 31b includes a transistor Q2 corresponding to the amplifier 12, a substrate 32b, and pads 33b and 34b provided on the substrate 32b. The pads 33a and 33b are input pads to which a high-frequency signal is input, for example, gate pads. The pads 34a and 34b are output pads from which a high-frequency signal is output, for example, drain pads. When the transistors Q1 and Q2 are GaN HEMTs, the substrates 32a and 32b are, for example, silicon carbide substrates, sapphire substrates or gallium nitride substrates. The pads 33a, 33b, 34a and 34b are, for example, gold layers, copper layers or aluminum layers.

[0031] The MIM capacitors 36a and 36b include a lower electrode, an upper electrode, and a dielectric layer sandwiched between the lower electrode and the upper electrode. The lower electrode is electrically connected to a conductor layer to which the reference potential of the upper surface of the substrate 30 is supplied. The lines 37a and 37b are electrically connected to the upper electrodes of the MIM capacitors 36a and 36b, respectively. A dielectric layer is provided between the lines 37a and 37b and the conductor layer to which the reference potential is supplied. The lines 37a and 37b are transmission lines such as microstrip lines, for example. The characteristic impedance at the center frequency fo of the transmission line formed by the lines 37a and 37b is substantially the reference impedance.

[0032] Pads 34a and 34b are electrically connected by bonding wire 40a. Pad 34a and the upper electrode of MIM capacitor 36a are electrically connected by bonding wire 40b. The upper electrode of MIM capacitor 36a and the upper electrode of MIM capacitor 36b are electrically connected by bonding wire 40c. Pad 34b and the upper electrode of MIM capacitor 36b are electrically connected by bonding wire 40d.

[0033] Semiconductor chips 31a and 31b respectively correspond to amplifiers 10 and 12 in FIG. 1. MIM capacitors 36a and 36b respectively correspond to capacitors C1 and C2 in FIG. 1. Bonding wires 40a, 40b, 40c, and 40d respectively correspond to inductors L1, L2, L3, and L4 in FIG. 1.

[0034] [Mounting Example 2 of Embodiment 1] FIG. 6 is a plan view showing mounting example 2 of the synthesizer and the amplifier in Embodiment 1. As shown in FIG. 6, conductor patterns 38a and 38b are provided on substrate 30. Bonding wire 41a electrically connects pad 34a and pattern 38a. Bonding wire 41b electrically connects pad 34b and pattern 38b. Bonding wire 41c electrically connects patterns 38a and 38b. Bonding wires 41a to 41c, patterns 38a and 38b form inductor L1. Other configurations are the same as those in mounting example 1 of FIG. 5 and the description thereof is omitted.

[0035] In Implementation Examples 1 and 2 of Example 1, the semiconductor chip 31a (first semiconductor chip) includes an amplifier 10 and a pad 34a (first pad) corresponding to node N1. The semiconductor chip 31b (second semiconductor chip) includes an amplifier 12 and a pad 34b (second pad) corresponding to node N2. The inductor L1 includes a bonding wire 40a or 41a (first bonding wire) having a first end connected to the pad 34a. Thereby, the pad 34a can function as the node N1. Thus, it is possible to suppress the provision of the line 20 as in Comparative Example 1, and it is possible to suppress deterioration of characteristics.

[0036] As in Implementation Example 1 of Example 1, the second end of the bonding wire 40a is connected to the pad 34b. Thereby, the pad 34b can function as the node N2. Thus, it is possible to suppress the provision of the line 20 as in Comparative Example 1, and it is possible to suppress deterioration of characteristics.

[0037] As in Implementation Example 2 of Example 1, the inductor L1 includes a bonding wire 41b (second bonding wire) having a first end connected to the pad 34b. Thereby, the pad 34b can function as the node N2. Thus, it is possible to suppress the provision of the line 20 as in Comparative Example 1, and it is possible to suppress deterioration of characteristics.

[0038] The bonding wire 40b (third bonding wire) connects the pad 34a and the capacitor C1 and corresponds to the inductor L2. The bonding wire 40d (fourth bonding wire) connects the pad 34b and the capacitor C2 and corresponds to the inductor L4. Thereby, the inductors L2 and L4 can be formed by the bonding wires 40b and 40d, respectively.

[0039] [Example 2] FIG. 7 is a circuit diagram of the amplifier circuit according to Example 2. As shown in FIG. 7, in the amplifier circuit 102 of Example 2, a capacitor C5 is shunt-connected to the node N1, and a capacitor C6 is shunt-connected to the node N2. Other configurations are the same as those in Example 1 and the description thereof is omitted.

[0040] When the parasitic capacitances Cds1 and Cds2 are smaller than C0 calculated from Table 1, by providing the capacitors C5 and C6, the capacitances of the capacitors C3 and C4 in FIG. 3 can be set to desired values. In this case, the capacitances of the capacitors C5 and C6 are smaller than the capacitances of the capacitors C1 and C2.

[0041] [Implementation Example of Example 2] FIG. 8 is a plan view showing an implementation example of a synthesizer and an amplifier in Example 2. As shown in FIG. 8, MIM capacitors 43a and 43b are provided on the substrate 30. The structures of the MIM capacitors 43a and 43b are the same as those of the MIM capacitors 36a and 36b. The bonding wire 42a electrically connects the pad 34a and the upper electrode of the MIM capacitor 43a. The bonding wire 42b electrically connects the pad 34b and the upper electrode of the MIM capacitor 43b. The lower electrodes of the MIM capacitors 43a and 43b are electrically connected to a conductor layer to which a reference potential is supplied. Other configurations are the same as those in the implementation example 1 of FIG. 5 and the description thereof is omitted.

[0042] The MIM capacitors 43a and 43b respectively correspond to the capacitors C5 and C6 in FIG. 7. The bonding wire 42a and the MIM capacitor 43a form a conductive reactance element 46a. The bonding wire 42b and the MIM capacitor 43b form a conductive reactance element 46b.

[0043] [Example 3] FIG. 9 is a circuit diagram of the amplifier circuit according to Embodiment 3. As shown in FIG. 9, in the amplifier circuit 104 of Embodiment 3, an inductor L5 is shunt-connected to node N1, and an inductor L6 is shunt-connected to node N2. A capacitor C01 is electrically connected between the inductor L5 and the ground, and a capacitor C02 is electrically connected between the inductor L6 and the ground. The capacitors C01 and C02 are capacitors for bias voltage cut that suppress the flow of the bias current to the ground. Other configurations are the same as those in Embodiment 2 and will not be described.

[0044] When the parasitic capacitances Cds1 and Cds2 are larger than C0 calculated from Table 1, by providing the inductors L5 and L6, the capacitances of the capacitors C3 and C4 in FIG. 3 can be set to desired values.

[0045] [Mounting Example of Embodiment 3] FIG. 10 is a plan view showing a mounting example of the synthesizer and the amplifier in Embodiment 3. As shown in FIG. 10, MIM capacitors 45a and 45b are provided on the substrate 30. The structures of the MIM capacitors 45a and 45b are the same as those of the MIM capacitors 36a and 36b. The MIM capacitors 45a and 45b are the capacitors C01 and C02, respectively. The bonding wire 44a electrically connects the pad 34a and the upper electrode of the MIM capacitor 45a. The bonding wire 44b electrically connects the pad 34b and the upper electrode of the MIM capacitor 45b. The lower electrodes of the MIM capacitors 45a and 45b are electrically connected to a conductor layer to which a reference potential is supplied. Other configurations are the same as those of the mounting example of Embodiment 2 in FIG. 8 and will not be described.

[0046] The bonding wires 44a and 44b respectively correspond to the inductors L5 and L6 in FIG. 9. The bonding wire 44a and the MIM capacitor 45a form an inductive reactance element 48a. The bonding wire 44b and the MIM capacitor 45b form an inductive reactance element 48b.

[0047] According to Embodiments 2 and 3, the reactance element 46a or 48a (first reactance element) is shunt-connected to the node N1. The reactance element 46b or 48b (second reactance element) is shunt-connected to the node N2. Thereby, even when the parasitic capacitances Cds1 and Cds2 are different from the capacitance C0 calculated from Table 1, the capacitances of the capacitors C3 and C4 in FIG. 3 can be made closer to C0. Thereby, the synthesizer 18 functions as a branch-line coupler.

[0048] The capacitance component obtained by synthesizing the parasitic capacitance Cds1 and the reactance element 46a or 48a, the capacitance component obtained by synthesizing the parasitic capacitance Cds2 and the reactance element 46b or 48b, and the capacitances C0 of the capacitors C1 and C2 can be set to be 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo)+1 / (2πfo×Zo / √2), and can be set to be 0.9 times or more and 1.1 times or less. The inductance L01 of the inductors L1 and L3 can be set to be 0.8 times or more and 1.2 times or less of Zo / (2πfo), and can be set to be 0.9 times or more and 1.1 times or less. The inductance L02 of the inductors L2 and L4 can be set to be 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)), and can be set to be 0.9 times or more and 1.1 times or less. Thereby, the amplifier circuits 102 and 104 can be made into balanced amplifiers.

[0049] [Embodiment 4] Embodiment 4 is an example of an LMBA (Load Modulated Balanced Amplifier). FIG. 11 is a circuit diagram of the amplifier circuit according to Embodiment 4. As shown in FIG. 11, in the amplifier circuit 106 of Embodiment 4, a control amplifier 22, amplifiers 10 and 12 are connected in parallel between the input terminal Tin and the output terminal Tout. A high-frequency signal is input as an input signal Sin to the input terminal Tin. A distributor 24 (another distributor) distributes the input signal Sin input to the input terminal Tin into a signal S5 (fifth signal) and an input signal Si.

[0050] The signal S5 is input to the control amplifier 22 via the matching circuit 26. The matching circuit 26 matches the impedance seen from the distributor 24 to the matching circuit 26 and the impedance seen from the matching circuit 26 to the control amplifier 22. The control amplifier 22 amplifies the signal S5 and outputs the amplified signal as a signal S6 (the sixth signal). The signal S6 amplified by the control amplifier 22 is output to the node N3 of the synthesizer 18.

[0051] The input signal Si distributed by the distributor 24 is input to the amplifier circuit 100. The amplifier circuit 100 is the same as the amplifier circuit 100 of the first embodiment except for the point where the signal S6 is input to the node N3 of the synthesizer 18, and the description thereof is omitted.

[0052] The control amplifier 22 corresponds to the main amplifier of the Doherty amplifier circuit, and the amplifiers 10 and 12 correspond to the peak amplifiers of the Doherty amplifier circuit. The control amplifier 22 operates in class AB or class B, and the amplifiers 10 and 12 operate in class C. When the input power of the input signal Sin is small, the control amplifier 22 mainly amplifies the input signal Sin. When the input power increases, in addition to the control amplifier 22, the amplifiers 10 and 12 amplify the peak of the input signal Sin. Thereby, the control amplifier 22 and the amplifiers 10 and 12 amplify the input signal Sin.

[0053] The synthesizer 18 modulates the loads of the amplifiers 10 and 12 using the signal S6, synthesizes the signals S3, S4, and S6, and outputs the synthesized signal as the output signal So. The following will specifically describe it.

[0054] When the power of the input signal Si is low and amplifiers 10 and 12 are not operating, the signal S6 input to node N3 of synthesizer 18 is divided into two signals S6 / 2 at nodes N1 and N2 respectively. The phase of the signal S6 / 2 at node N2 lags behind the phase of the signal S6 / 2 at node N1 by 90°. The signal S6 / 2 is reflected at nodes N1 and N2. The signal S6 / 2 is combined at node N4. The phase of the signal S6 / 2 reflected at node N1 lags behind the phase of the signal S6 / 2 reflected at node N2 by 90°. As a result, at node N4, the phases of the two signals S6 / 2 are aligned and the signal S6 is combined. The combined signal S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient seen by synthesizer 18 from amplifiers 10 and 12 is approximately 1, and the load impedance of amplifiers 10 and 12 is substantially high.

[0055] When the power of the input signal Sin is high and amplifiers 10 and 12 are operating, the phase of signal S4 lags behind the phase of signal S3 by 90°. The phase of the signal S6 / 2 at node N2 lags behind the phase of the signal S6 / 2 at node N1 by 90°. The signal S3 + S6 / 2 combined at node N1 and the signal S4 + S6 / 2 combined at node N2 are combined at node N4. The combined signal S3 + S4 + S6 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficient seen by synthesizer 18 from amplifiers 10 and 12 is less than 1, and the larger the amplitudes of signals S3 and S4, the smaller the reflection coefficient. For this reason, the load impedance of amplifiers 10 and 12 is substantially low. In this way, synthesizer 18 modulates the load impedance seen by synthesizer 18 from amplifiers 10 and 12 depending on the amplitudes of signals S3 and S4.

[0056] In the Doherty amplifier circuit, a λ / 4 line is provided as an impedance converter in a synthesizer that synthesizes a signal amplified by a main amplifier and a signal amplified by a peak amplifier. The load impedance of the main amplifier is modulated using the λ / 4 line. In this case, when the frequency changes, the electrical length of the λ / 4 line deviates from λ / 4, making it difficult to broaden the operating bandwidth. In one example, the specific bandwidth of the synthesizer using the λ / 4 line is about 8%.

[0057] In the LMBA as in Embodiment 4, the synthesizer 18 modulates the loads of the amplifiers 10 and 12 using the signal S6, synthesizes the signals S3, S4, and S6, and outputs the synthesized signal as the output signal So. Thereby, it becomes possible to broaden the operating bandwidth. For example, the specific bandwidth of a 90° coupler is at most 120% in a commercially available 90° hybrid coupler.

[0058] By using the amplifier circuits of Embodiments 1 to 3 in the LMBA, deterioration of the characteristics of the amplifier circuit 106 can be suppressed. The high-frequency characteristics can be improved. In particular, when the loss of the line 20 is large as in Comparative Example 1, the reflection coefficient of the signal S6 / 2 at the nodes N1 and N2 becomes less than 1. As a result, the loss in the synthesizer 18 increases. In Embodiment 4, the loss of the line 20 can be suppressed. Thereby, the loss in the synthesizer 18 can be suppressed. Note that in the LMBA or the like, S03 - S04 in Table 1 may be negative or positive other than 0 dB.

[0059] It should be considered that all aspects of the embodiments disclosed this time are illustrative and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Description of Reference Numerals

[0060] 10 (First Amplifier), 12 (Second Amplifier) Amplifier 13, 14, 26 Matching Circuit 16, 24 (Another Divider) Divider 18 Synthesizer Lines 20, 37a, 37b 22 Control amplifier Substrates 30, 32a, 32b Semiconductor chips 31a, 31b Pads 33a, 33b, 34a (first pad), 34b (second pad) MIM capacitors 36a, 36b, 43a, 43b, 45a, 45b Patterns 38a, 38b Bonding wires 40a, 40b, 40c, 40d, 41a, 41b, 41c, 42a, 42b, 44a, 44b Reactance elements 46a, 46b, 48a (first reactance element), 48b (second reactance element) Amplification circuits 100, 102, 104, 106, 110 Capacitors C1 (first capacitor), C2 (second capacitor) Parasitic capacitances Cds1 (first ground capacitance), Cds2 (second ground capacitance) Inductors L1 (first inductor), L2 (second inductor), L3 (third inductor), L4 (fourth inductor) Nodes N1 (first node), N2 (second node), N3 (third node), N4 (fourth node) Signals S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal) Input signals Si, Sin Output signal So

Claims

1. A distributor that distributes an input signal into a first signal and a second signal whose phase is 90° later than that of the first signal; A first amplifier that amplifies the first signal and outputs the amplified first signal as a third signal to a first node; A second amplifier that amplifies the second signal and outputs the amplified second signal as a fourth signal to a second node; A first inductor connecting the first node and the second node; A second inductor connecting the first node and a third node; A third inductor connecting the third node and a fourth node that outputs an output signal in which the third signal whose phase is 90° later than the fourth signal and the fourth signal are combined; A fourth inductor connecting the second node and the fourth node; A first capacitor shunt-connected to the third node; A second capacitor shunt-connected to the fourth node; An amplifier circuit in which the inductances of the first inductor and the third inductor are larger than the inductances of the second inductor and the fourth inductor.

2. The amplifier circuit according to Claim 1, wherein the inductances of the first inductor and the third inductor are 0.8×√2 or more and 1.2×√2 or less of the inductances of the second inductor and the fourth inductor.

3. The amplifier circuit according to Claim 1 or Claim 2, wherein no reactive element is shunt-connected to the first node and the second node.

4. When the center frequency of the operating band is fo and the reference impedance is Zo, The capacitance C0 of the first ground capacitance of the output node of the first amplifier, the second ground capacitance of the output node of the second amplifier, the first capacitor and the second capacitor is 0.8 times or more and 1.2 times or less of 1 / (2πfo×Zo) + 1 / (2πfo×Zo / √2); The inductances of the first inductor and the third inductor are 0.8 times or more and 1.2 times or less of Zo / (2πfo); The amplifier circuit according to Claim 3, wherein the inductances of the second inductor and the fourth inductor are 0.8 times or more and 1.2 times or less of Zo / (√2×(2πfo)).

5. A first reactive element shunt-connected to the first node; A second reactive element shunt-connected to the second node; The amplifier circuit according to Claim 1 or Claim 2, comprising the above.

6. When the center frequency of the operating band is \(f_o\) and the reference impedance is \(Z_o\), the capacitance component obtained by combining the first ground capacitance of the output node of the first amplifier and the first reactance element, the capacitance component obtained by combining the second ground capacitance of the output node of the second amplifier and the second reactance element, and the capacitances \(C_0\) of the first capacitor and the second capacitor are 0.8 times or more and 1.2 times or less of \(1 / (2\pi f_o\times Z_o)+1 / (2\pi f_o\times Z_o / \sqrt{2})\), the inductances of the first inductor and the third inductor are 0.8 times or more and 1.2 times or less of \(Z_o / (2\pi f_o)\), the inductances of the second inductor and the fourth inductor are 0.8 times or more and 1.2 times or less of \(Z_o / (\sqrt{2}\times(2\pi f_o))\). The amplifier circuit according to claim 5. **Claim 7** a first semiconductor chip including the first amplifier and a first pad corresponding to the first node; a second semiconductor chip including the second amplifier and a second pad corresponding to the second node; comprising The amplifier circuit according to claim 1 or claim 2, wherein the first inductor includes a first bonding wire having a first end connected to the first pad. **Claim 8** The amplifier circuit according to claim 7, wherein a second end of the first bonding wire is connected to the second pad. **Claim 9** The amplifier circuit according to claim 7, wherein the first inductor includes a second bonding wire having a first end connected to the second pad. **Claim 10** connecting the first pad and the first capacitor, a third bonding wire corresponding to the second inductor, connecting the second pad and the second capacitor, a fourth bonding wire corresponding to the fourth inductor, The amplifier circuit according to claim 7, comprising **Claim 11** The amplifier circuit according to claim 7, wherein the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, the first ground capacitance of the first pad, and the second ground capacitance of the second pad form a branch-line coupler. **Claim 12** another distributor that distributes a high-frequency signal into the input signal and a fifth signal; a control amplifier that amplifies the fifth signal and outputs the amplified fifth signal as a sixth signal; comprising The synthesizer including the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, and the second capacitor modulates the loads of the first amplifier and the second amplifier using the sixth signal, synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as an output signal. The amplifier circuit according to claim 1 or claim 2.

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