Display device and method for driving display device

Abstract

To provide a display device and a method for driving the display device, which can reduce the number of signal wires.SOLUTION: A display device comprises a display panel, a scanning line driving portion 46, and a touch detection portion. The display panel has scanning lines GL. The scanning line driving portion 46 has a circuit group 100A. The circuit group 100A includes shift registers 110 V1 to 110 V8, each of which has unit circuits 120 connected in multiple stages and sequentially outputs scanning signals to the scanning lines GL of display areas V1 to V8 of the display panel. The touch detection portion detects a touch during a stop period of the circuit group 100A. The shift registers 110 V1 to 110 V8 sequentially output the scanning signals when selection signals SEL and start signals ST are input to the unit circuits 120 of a first stage. The selection signals SEL have different phases from each other, and the start signals ST are commonly input to the unit circuits 120 of the first stage.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a display device and a method for driving the display device.

Background Art

[0002] An in-cell type display device in which the function of a touch sensor (touch panel) is incorporated into a display panel is known. In the in-cell type display device, pixel electrodes for driving pixels of the display device are used for touch detection. Therefore, at the time of touch detection, the scanning of the scanning lines of the display panel is temporarily stopped, and touch detection is performed during a stop period in which the scanning of the scanning lines is stopped. Thereby, it is possible to suppress noise caused by potential changes in the scanning lines from being mixed in touch detection.

[0003] For example, Patent Document 1 discloses a display device including a display panel, a gate driving circuit, and a touch driving circuit. The display panel has a display area including gate lines, data lines, and a touch sensor, and the gate driving circuit divides the display area into a plurality of horizontal blocks and drives the gate lines of the horizontal blocks for each unit of the horizontal blocks in each display period within one frame. The touch driving circuit detects a touch via the touch sensor of the horizontal block for each unit of the horizontal block in each touch detection period within one frame.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In Patent Document 1, the gate driving circuit includes a plurality of driving stage groups and a plurality of holding stage groups. The driving stage group supplies a scanning pulse to the gate line included in the corresponding horizontal block in each display period, and the holding stage group supplies a carry signal to the subsequent driving stage group according to the output signal supplied from the previous driving stage group between the driving stage groups. Thereby, a display device including a gate driving circuit that stably holds the output signal during the touch detection period, that is, while the scanning of the gate line is stopped, is realized.

[0006] In the gate driving circuit of Patent Document 1, many signals are required to operate the driving stage group and the holding stage group. For example, when the display area is divided into eight horizontal blocks, 20 signals (4 gate start signals, 8 gate shift clocks, 4 scan hold clocks, and 4 stage reset clocks) are required (paragraph 0067 of the specification of Patent Document 1). Therefore, the number of signal wirings of the gate driving circuit increases, and when the gate driving circuit is formed at the frame edge of the display panel, the outer size of the display panel increases. Also, when the gate driving circuit is incorporated into the driver IC, the size of the driver IC increases.

[0007] Furthermore, in the driving stage group of the gate driving circuit of Patent Document 1, a high voltage is always applied to the input terminal of the transistor to which the start signal is input to the gate terminal. Therefore, there is a possibility that a threshold voltage shift occurs in the transistor to which the start signal is input to the gate terminal.

[0008] The present disclosure has been made in view of the above circumstances, and an object thereof is to provide a display device and a driving method for the display device that can reduce the number of signal wirings. Another object is to provide a display device and a driving method for the display device that suppress the threshold voltage shift of the transistor in the scanning line driving unit.

Means for Solving the Problems

[0009] According to a first aspect of the present disclosure, a display device includes: a display panel having a plurality of scanning lines and divided into a plurality of display areas; a scanning line driver that sequentially outputs scanning signals to each of the scanning lines; a touch detection unit that detects a touch on the display panel, wherein the scanning line driver has at least one circuit group, the circuit group is connected in multiple stages and includes a plurality of unit circuits that output the scanning signals to each of the scanning lines, and each of the unit circuits includes a plurality of shift registers that sequentially output the scanning signals to each of the scanning lines within each of the display areas; the touch detection unit detects a touch on the display panel during a stop period in which the at least one circuit group stops outputting the scanning signals; in one of the circuit groups, each of the shift registers outputs the scanning signals sequentially when a selection signal for selecting the shift register that outputs the scanning signals and a start signal for starting the output of the scanning signals are input to each of the first-stage unit circuits; each of the selection signals input to each of the first-stage unit circuits has a different phase from each other according to a scanning period and a stop period in which the circuit group outputs the scanning signals; the start signal is commonly input to each of the first-stage unit circuits.

[0010] According to a second aspect of the present disclosure, a driving method of a display device includes: a driving method of a display device having a plurality of scanning lines and a display panel divided into a plurality of display areas, and performing a display operation for displaying display elements and touch detection alternately, It has a plurality of unit circuits that are connected in multiple stages and output a scanning signal to each of the scanning lines, and sequentially outputs the scanning signal to each of the scanning lines within each of the plurality of display areas from one of a plurality of shift registers, and sequentially outputs the scanning signal to each of the scanning lines to display the display element or a part of the display element in one of the display areas, a display step; A touch detection step of detecting a touch on the display panel during a stop period in which the plurality of shift registers stop outputting the scanning signal, and includes; In the display step, By inputting a selection signal for selecting the shift register that outputs the scanning signal and a start signal for starting the output of the scanning signal to the unit circuit of the first stage of each of the shift registers, the scanning signal is sequentially output from one of the plurality of shift registers, Each of the selection signals input to each of the unit circuits of the first stage has a different phase from each other according to the scanning period and the stop period in which the plurality of shift registers output the scanning signal, The start signal is commonly input to each of the unit circuits of the first stage.

Advantages of the Invention

[0011] According to the present disclosure, since a selection signal having a different phase and selecting a shift register that outputs a scanning signal is input to each of the unit circuits of the first stage of the shift register, and a start signal for starting the output of the scanning signal is commonly input, the number of signal wirings in the scanning line driving unit can be reduced. Further, since selection signals having different phases are input to the unit circuits of the first stage, a voltage is not always applied to the transistors forming the unit circuits, and the threshold voltage shift of the transistors can be suppressed.

Brief Description of the Drawings

[0012]

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Best Mode for Carrying Out the Invention

[0013] Hereinafter, a display device and a driving method of the display device according to an embodiment will be described with reference to the drawings.

[0014] <Embodiment 1> With reference to FIGS. 1 to 10, a display device 10 and a driving method of the display device 10 according to the present embodiment will be described. The display device 10 is mounted on a vehicle, an aircraft, home appliances, furniture, etc.

[0015] As shown in FIG. 1, the display device 10 includes a display panel 20, a touch detection unit 30, a display control unit 40, and a control unit 50. The display panel 20 is, for example, a color liquid crystal display panel and displays display elements (characters, images, etc.). The touch detection unit 30 detects a touch on the display panel 20. The display control unit 40 causes the display panel 20 to display display elements. The display control unit 40 includes a timing controller 42, a data line driver 44, and a scan line driver 46. The control unit 50 controls the touch detection unit 30 and outputs the detected touch position to the outside. Further, the control unit 50 receives input data (input image data) from the outside and controls the display control unit 40. In the present embodiment and the following embodiments, for ease of understanding, the right direction (right direction on the paper surface) of the display panel 20 in FIG. 1 is defined as the +X direction, the upward direction (upward direction on the paper surface) is defined as the +Y direction, and the direction perpendicular to the +X direction and the +Y direction (front direction on the paper surface) is defined as the +Z direction for explanation.

[0016] The display panel 20 of the display device 10 is an in-cell type color liquid crystal display panel having a function of displaying display elements and a function of detecting touches. Here, the in-cell type color liquid crystal display panel refers to a configuration in which one of two substrates sandwiching liquid crystal has an electrode used for touch detection on the main surface on the liquid crystal side. Further, a touch means that an object comes into contact with the display panel 20 or the object approaches the display panel 20 to such an extent that a parasitic capacitance is formed between the object and a sensor electrode SE of the display panel 20 described later. The object is a user's finger, a pen, etc.

[0017] The display panel 20 is a known transmissive horizontal electric field type color liquid crystal display panel, which is actively matrix-driven by a TFT (Thin Film Transistor) to display display elements. As shown in FIG. 1, the display panel 20 has a display portion 22, a detection region 23, and a frame portion 24. The display portion 22 has main pixels PX formed from three sub-pixels SP arranged in a matrix to display display elements. The detection region 23 is a region capable of detecting a touch on the display panel 20. In the frame portion 24, a scanning line driving portion 46, wirings, etc. are arranged. In the present embodiment, the display portion 22 and the detection region 23 coincide with each other.

[0018] In the present embodiment, as shown in FIG. 2, the display portion 22 is divided into eight display regions V1 to V8 extending in the X direction. Also, as shown in FIG. 3, the detection region 23 is divided into eight detection regions H1 to H8 extending in the Y direction.

[0019] In the display device 10, during one frame in which display elements are displayed on the display panel 20, a display operation for displaying display elements and touch detection are alternately performed in a time-division manner. Specifically, as shown in FIG. 4, the display operations in each of the display regions V1 to V8 are sequentially performed during respective display periods P1 to P8. Touch detection in one of the detection regions H1 to H8 is performed during respective detection periods S1 to S8. In FIG. 4, for example, during the display period P1, the display operation in the display region V1 is performed, and after the display scanning stops, during the detection period S1, touch detection in the detection region H4 is performed. Then, after the touch detection during the detection period S1 stops, the display operation in the display region V2 is performed during the display period P2. That is, touch detection is performed during a stop period in which the display operation has stopped.

[0020] As shown in FIG. 2, the display panel 20 includes a plurality of scanning lines G1 to Gn and a plurality of data lines D1 to Dm. The scanning lines G1 to Gn extend in the X direction and are arranged along the Y direction. The scanning lines G1 to Gn are connected to the scanning line driver unit 46. The data lines D1 to Dm extend in the Y direction and are arranged along the X direction. The data lines D1 to Dm are connected to the data line driver unit 44. Hereinafter, the scanning lines G1 to Gn may be collectively referred to as the scanning line GL, and the data lines D1 to Dm may be collectively referred to as the data line DL.

[0021] Sub-pixels SP are arranged at positions where the scanning line GL and the data line DL intersect. In this embodiment, three sub-pixels SP (for example, a sub-pixel SP that emits red light, a sub-pixel SP that emits green light, and a sub-pixel SP that emits blue light) form one main pixel PX.

[0022] The sub-pixel SP has a TFT, a pixel electrode, and a common electrode (none of which are shown). The gate electrode of the TFT is connected to the scanning line GL, and the source terminal of the TFT is connected to the data line DL. Also, the drain terminal of the TFT is connected to the pixel electrode. The TFT supplies a data voltage corresponding to the video signal supplied from the data line DL to the pixel electrode in response to the scanning signal supplied from the scanning line GL. The pixel electrode has, for example, a comb shape and is connected to the drain electrode of the TFT. The common electrode is connected to a common wiring (not shown). In this embodiment, the common electrode is divided into a plurality of parts, and the divided common electrodes constitute the sensor electrode SE. The liquid crystal of the display panel 20 controls the amount of light emitted from the sub-pixel SP according to the potential difference between the data voltage of the pixel electrode and the common voltage applied to the common electrode via the common wiring.

[0023] As described above, the sensor electrode SE is composed of divided common electrodes. As shown in FIG. 3, the sensor electrodes SE are arranged in a matrix in the detection region 23. The sensor electrodes SE are connected to the touch detection unit 30 via the sensor wiring SL. The sensor electrodes SE receive an input of a drive signal from the touch detection unit 30 via the sensor wiring SL, and output a response signal (output signal) to the touch detection unit 30 with respect to the drive signal. Note that the sensor wiring SL is provided in a layer above the scanning line GL and the data line DL (+Z side layer).

[0024] The touch detection unit 30 of the display device 10 is a circuit that detects the presence or absence of a touch on the display panel 20 and the position of the touch. The touch detection unit 30 detects the presence or absence of a touch and the position of the touch in each of the detection regions H1 to H8 during each of the detection periods S1 to S8. The touch detection unit 30 is connected to the sensor electrodes SE via the sensor wiring SL. The touch detection unit 30 outputs various signals to the sensor electrodes SE in accordance with a control signal (including a synchronization signal) supplied from the control unit 50. Further, the touch detection unit 30 receives the response signal output from the sensor electrodes SE. Furthermore, the touch detection unit 30 obtains the position of the touch from the response signal, and outputs a signal representing the position of the touch to the control unit 50. The touch detection unit 30 may be incorporated, for example, in TDDI (Touch Display Driver Integration).

[0025] Returning to FIG. 1, the display control unit 40 of the display device 10 includes a timing controller 42, a data line driver 44, and a scanning line driver 46.

[0026] The timing controller 42 converts input data (input image data) representing a display element, which is input from the control unit 50, into a video signal PSI. The timing controller 42 outputs the converted video signal PSI to the data line driver unit 44. Further, the timing controller 42 generates a control signal DSI for controlling the data line driver unit 44 and a control signal GSI for controlling the scan line driver unit 46 based on the input data representing the display element, a control signal including a synchronization signal, etc. input from the control unit 50, and outputs the control signal DSI to the data line driver unit 44 and the control signal GSI to the scan line driver unit 46.

[0027] Based on the control signal DSI, the data line driver unit 44 converts the video signal PSI supplied from the timing controller 42 into a data voltage. The data line driver unit 44 outputs the converted data voltage to each of the data lines DL. The data line driver unit 44 and the timing controller 42 may be incorporated in, for example, TDDI.

[0028] Based on the control signal GSI supplied from the timing controller 42, the scan line driver unit 46 sequentially outputs scan signals to each of the scan lines GL. The scan line driver unit 46 is, for example, a circuit formed in the frame portion 24 of the display panel 20.

[0029] As shown in FIG. 5, the scan line driver unit 46 includes eight shift registers 110V1 to 110V8 corresponding to the respective display areas V1 to V8 of the display panel 20. Each of the shift registers 110V1 to 110V8 has a plurality of unit circuits 120 corresponding to the number of scan lines GL in each of the display areas V1 to V8. The unit circuits 120 are connected in multiple stages. The unit circuit 120 outputs a scan signal to one scan line GL.

[0030] Shift registers 110V1 to 110V8 may form at least one circuit group. In this embodiment, an example where shift registers 110V1 to 110V8 form one circuit group 100A will be described. That is, in this embodiment, the scanning line driving unit 46 has one circuit group 100A, and the circuit group 100A has eight shift registers 110V1 to 110V8.

[0031] In this embodiment, as described above, each of the shift registers 110V1 to 110V8 corresponds to each of the display areas V1 to V8. Therefore, each of the display areas V1 to V8 corresponds to the scanning area of each of the shift registers 110V1 to 110V8. Also, the scanning period during which each of the shift registers 110V1 to 110V8 outputs a scanning signal corresponds to each of the display periods P1 to P8. Hereinafter, the scanning period of each of the shift registers 110V1 to 110V8 will be described as the scanning periods P1 to P8, and the scanning periods (scanning periods P1 to P8) will also be collectively referred to as the scanning period P.

[0032] Also, the display operation and the touch detection are alternately performed (FIG. 4), and the touch detection is performed during the stop period when the display operation stops. Therefore, it can also be said that the touch detection is performed during the stop period when the shift registers 110V1 to 110V8 stop outputting the scanning signal, and the stop period corresponds to the detection periods S1 to S8. Hereinafter, the stop period of each of the shift registers 110V1 to 110V8 will be described as the stop periods S1 to S8, and the stop periods (stop periods S1 to S8) will also be collectively referred to as the stop period S.

[0033] In this embodiment, each of the shift registers 110V1 to 110V8 sequentially outputs a scanning signal from each of the unit circuits 120 when the start signal ST and the selection signal SEL are input to the first-stage unit circuit 120 of each. Hereinafter, the selection signal SEL input to each of the shift registers 110V1 to 110V8 will be denoted as selection signals SEL1 to SEL8. Also, the shift registers (shift registers 110V1 to 110V8) may be collectively referred to as the shift register 110.

[0034] The start signal ST is a signal for starting the output of the scanning signal. The start signal ST is commonly input to each of the first-stage unit circuits 120 of the shift registers 110V1 to 110V8. The selection signals SEL1 to SEL8 are signals for selecting the shift register 110 that outputs the scanning signal. As shown in FIG. 6, the selection signals SEL1 to SEL8 have different phases from each other according to the scanning period P during which the shift registers 110V1 to 110V8 (that is, the circuit group 100A) output the scanning signal and the stop period S during which the shift registers 110V1 to 110V8 stop outputting the scanning signal. Since the phases of the selection signals SEL1 to SEL8 are different from each other according to the scanning period P and the stop period S, even if the start signal ST is commonly input to each of the first-stage unit circuits 120, the scanning signal is sequentially output from one shift register 110 to which the selection signal SEL is input.

[0035] In the present embodiment, since the start signal ST for starting the output of the scanning signal is commonly input to each of the first-stage unit circuits 120 of the shift registers 110V1 to 110V8, has different phases, and the selection signal SEL for selecting the shift register 110 that outputs the scanning signal is input to each of the first-stage unit circuits 120, the number of signal wirings can be reduced. Hereinafter, the configuration of the shift register 110 will be specifically described.

[0036] FIG. 7 is a block diagram for explaining the configuration of the shift register 110. Input to the shift register 110 are the start signal ST, one of the selection signals SEL1 to SEL8, the reset signal RST, the clock signal CLK_A and the clock signal CLK_B which are two clock signals with inverted phases, the frame reset signal FRM, and the low-level voltage VGL. In FIG. 7, the frame reset signal FRM is omitted for easy understanding. The frame reset signal FRM is a signal for resetting the shift register 110 at the start of each frame.

[0037] The start signal ST, the selection signals SEL1 to SEL8, the reset signal RST, the clock signal CLK_A, the clock signal CLK_B, and the frame reset signal FRM correspond to the control signal GSI supplied from the timing controller 42. The low-level voltage VGL is supplied from, for example, the control unit 50. Hereinafter, the output signal corresponds to the scan signal.

[0038] During the scanning period P1, when the start signal ST, which is commonly input to all the first-stage unit circuits 120, and the selection signal SEL1, whose phase is different from the other selection signals SEL2 to SEL8, are input to the first-stage unit circuit 120 of the first shift register 110V1, the first-stage unit circuit 120 of the shift register 110V1 outputs the output signal (i.e., the scan signal) G1_OUT from the output terminal OUT to the scan line G1 based on the clock signals CLK_A and CLK_B. The output signal G1_OUT output from the first-stage unit circuit 120 of the shift register 110V1 is input to the second-stage (next-stage) unit circuit 120, and the second-stage unit circuit 120 outputs the output signal G2_OUT to the next scan line G2 (GL) based on the input output signal and the clock signals CLK_A and CLK_B. On the other hand, the output signal G2_OUT output from the second-stage (next-stage) unit circuit 120 is also supplied to the first-stage (previous-stage) unit circuit 120.

[0039] The unit circuits 120 after the third stage of the shift register 110V1 sequentially output the output signals G3_OUT to Gx_OUT to the scan lines GL in the display area V1 in the same manner as the first-stage unit circuit 120 and the second-stage unit circuit 120 described above. When the final-stage unit circuit 120 outputs the output signal Gx_OUT, the output of the output signal from the shift register 110V1 to the scan lines GL in the display area V1 during the scanning period P1 stops. Note that the reset signal RST, which is commonly input to all the final-stage unit circuits 120, is input to the final-stage unit circuit 120 instead of the output signal of the next stage.

[0040] When the output of the output signal (scanning signal) from the shift register 110V1 stops, during the detection period S1 (stop period S1), touch detection is performed by the touch detection unit 30 in one of the detection regions H1 to H8 (detection region H4 in this embodiment).

[0041] When the touch detection ends during the detection period S1 (stop period S1), during the scanning period P2, similar to the scanning period P1, the output signals (scanning signals) Gk_OUT to Gy_OUT are sequentially output from the second shift register 110V2 to the scanning lines GL in the display region V2. In this case, to the first-stage unit circuit 120 of the shift register 110V2, a start signal ST that is commonly input to all the first-stage unit circuits 120, selection signals SEL1, SEL3 to SEL8, and a selection signal SEL2 having a different phase are input.

[0042] For the third and subsequent shift registers 110 (shift registers 110V3 to 110V8), similar to the first shift register 110V1 and the second shift register 110V2, the output of the output signal and the touch detection are alternately performed.

[0043] FIG. 8 is a diagram showing the circuit configuration of the unit circuit 120. The unit circuit 120 includes nine transistors T0 to T8 and two capacitors C0 and C1.

[0044] In the first-stage unit circuit 120, the gate terminal of the transistor T0 is input with the start signal ST, and the first terminal of the transistor T0 is input with the selection signal SEL. Also, the second terminal of the transistor T0 in the first-stage unit circuit 120 is connected to the node N1. In the unit circuits 120 from the second stage onward, the gate terminal and the first terminal of the transistor T0 are diode-connected and input with the output signal (scanning signal) output from the previous-stage unit circuit 120. The second terminal of the transistor T0 in the unit circuits 120 from the second stage onward is connected to the node N1, similar to the first-stage unit circuit 120. The transistor T0 corresponds to the second transistor and boosts the node N1.

[0045] In the embodiments of the present disclosure, the first terminal of the transistor T0 refers to one of the source terminal and the drain terminal, and the second terminal of the transistor T0 refers to the other of the source terminal and the drain terminal. The same applies to other transistors.

[0046] The gate terminal of the transistor T1 receives the output signal output from the unit circuit 120 in the next stage (the second stage). The first terminal of the transistor T1 is connected to the node N1, and the second terminal of the transistor T1 is connected to the signal wiring that supplies the low-level voltage VGL. Note that in the unit circuit 120 of the last stage, the reset signal RST is input to the gate terminal of the transistor T1 instead of the output signal output from the unit circuit 120 in the next stage.

[0047] The gate terminal of the transistor T2 is connected to the node N2. The first terminal of the transistor T2 is connected to the node N1, and the second terminal of the transistor T2 is connected to the signal wiring that supplies the low-level voltage VGL.

[0048] The gate terminal of the transistor T3 is connected to the node N1. The first terminal of the transistor T3 is connected to the node N2, and the second terminal of the transistor T3 is connected to the signal wiring that supplies the low-level voltage VGL.

[0049] One terminal of the capacitor C1 is connected to the node N2. The other terminal of the capacitor C0 receives the clock signal CLK_A or the clock signal CLK_B.

[0050] The gate terminal of the transistor T4 is connected to the node N1. The first terminal of the transistor T4 receives the clock signal CLK_A or the clock signal CLK_B, and the second terminal of the transistor T4 is connected to the output terminal OUT. The transistor T4 corresponds to the first transistor.

[0051] One terminal of the capacitor C0 is connected to the gate terminal of the transistor T4, and the other terminal of the capacitor C0 is connected to the second terminal (output terminal OUT) of the transistor T4. That is, the capacitor C0 is connected between the gate terminal and the second terminal of the transistor T4.

[0052] The gate terminal of the transistor T5 is connected to the node N2. The first terminal of the transistor T5 is connected to the output terminal OUT, and the second terminal of the transistor T5 is connected to the signal wiring that supplies the low-level voltage VGL.

[0053] The gate terminal of the transistor T6 receives the clock signal CLK_A or the clock signal CLK_B. The first terminal of the transistor T6 is connected to the output terminal OUT, and the second terminal of the transistor T6 is connected to the signal wiring that supplies the low-level voltage VGL.

[0054] The gate terminal of the transistor T7 receives the frame reset signal FRM. The first terminal of the transistor T7 is connected to the node N1, and the second terminal of the transistor T7 is connected to the signal wiring that supplies the low-level voltage VGL.

[0055] The gate terminal of the transistor T8 receives the frame reset signal FRM. The first terminal of the transistor T8 is connected to the output terminal OUT, and the second terminal of the transistor T8 is connected to the signal wiring that supplies the low-level voltage VGL.

[0056] In this embodiment, since the selection signal SEL is input to the first terminal of the transistor T0 of the first-stage unit circuit 120, the voltage is not always input to the first terminal of the transistor T0 of the first-stage unit circuit 120. Therefore, the bias voltage between the gate terminal and the first terminal of the transistor T0 in the first-stage unit circuit 120 can be suppressed, and the threshold voltage shift of the transistor T0 in the first-stage unit circuit 120 can be suppressed. Further, in the unit circuits 120 from the second stage onward, since the gate terminal and the first terminal of the transistor T0 are diode-connected, the bias voltage can also be suppressed and the threshold voltage shift can be suppressed in the transistor T0 of the unit circuits 120 from the second stage onward.

[0057] Next, the operation of the shift register 110 will be described with reference to FIG. 9. FIG. 9 is a timing chart of the shift register 110. In FIG. 9, for ease of understanding, the potentials of the nodes N1 and N2 are shown only for the first-stage unit circuit 120 of the scanning period P1 (shift register 110V1), and the timing chart is simplified.

[0058] In the first period t0 of one frame, in all the unit circuits 120, when the frame reset signal becomes high level, the transistors T7 and T8 are turned on. When the transistor T7 is turned on, the node N1 is connected to the signal wiring that supplies the low-level voltage VGL and becomes a low potential. Also, when the transistor T8 is turned on, the output terminal OUT is also connected to the signal wiring that supplies the low-level voltage VGL and becomes a low level (low output).

[0059] In the next period t1, in the first-stage unit circuit 120 of the shift register 110V1, the start signal ST, which is commonly input to all the first-stage unit circuits 120, becomes high level. As a result, the transistor T0 is turned on. When the transistor T0 is turned on, the high potential of the selection signal SEL1 among the selection signals SEL1 to SEL8 having different phases is applied to the node N1, and the node N1 becomes high potential. When the node N1 becomes high potential, the transistors T3 and T4 are turned on.

[0060] When the transistor T3 is turned on, the potential of node N2 is connected to the signal wiring that supplies the low-level voltage VGL and drops to a low potential. Although the transistor T4 is in the ON state, the clock signal CLK_A is at the low level, and the transistor T6 is in the ON state due to the clock signal CLK_B. Since the output terminal OUT is connected to the signal wiring that supplies the low-level voltage VGL, the output terminal OUT maintains the low level. On the other hand, the node potential of node N1 is held in the capacitor C0 connected between the gate terminal and the second terminal of the transistor T4. This node potential is the potential obtained by subtracting the threshold voltage of the transistor T0 from the high-level potential of the selection signal SEL1.

[0061] In the next period t2, in the unit circuit 120 at the first stage of the shift register 110V1, since the start signal ST and the selection signal SEL1 are at the low level, node N1 becomes a floating state. Since the capacitor C0 has the potential held in the period t1, the transistor T4 maintains the ON state. At this time, the clock signal CLK_A becomes high level, and due to the capacitive coupling between the parasitic capacitance of the transistor T4 and the capacitor C0, the gate potential (the potential of node N1) of the transistor T4 rises rapidly (bootstrap effect). Due to the rapid rise of the gate potential of the transistor T4, the high level of the clock signal CLK_A is output from the output terminal OUT as the output signal (scan signal) G1_OUT. Node N2 is connected to the signal wiring that supplies the low-level voltage VGL because the transistor T3 is turned on by the potential of node N1, and becomes a low potential.

[0062] In the next period t3, in the first-stage unit circuit 120 of the shift register 110V1, the clock signal CLK_A changes to the low level and the clock signal CLK_B changes to the high level. As a result, the transistor T6 is turned on, and the potential (voltage) held in the capacitor C0 is discharged. Also, since the output signal G2_OUT of the second-stage (subsequent stage) unit circuit 120 is applied to the transistor T1, the node N1 is connected to the signal wiring that supplies the low-level voltage VGL and becomes a low potential. The node N2 is in a floating state and maintains the low potential in the period t2.

[0063] In the next period t4, in the first-stage unit circuit 120 of the shift register 110V1, the clock signal CLK_A changes to the high level. Also, the node N2 becomes a high potential because the high-level potential of the clock signal CLK_A is held in the capacitor C1. Due to these, the transistor T2 is turned on, and the node N1 is connected to the signal wiring that supplies the low-level voltage VGL. Also, the transistor T5 is turned on, and the output terminal OUT is connected to the signal wiring that supplies the low-level voltage VGL.

[0064] In the next period t5, in the first-stage unit circuit 120 of the shift register 110V1, the clock signal CLK_A changes to the low level. As a result, the node N2 discharges the potential of the capacitor C1 and becomes a low potential.

[0065] Here, returning to the period t3, in the second-stage unit circuit 120 of the shift register 110V1, the output signal of the first-stage (preceding stage) unit circuit 120 is input to the gate terminal and the first terminal of the diode-connected transistor T0. As a result, similar to the first-stage unit circuit 120, the output signal G2_OUT is output from the output terminal OUT from the second-stage unit circuit 120.

[0066] The unit circuits after the third stage of the shift register 110V1 also sequentially output the output signals from the output terminal OUT in the same manner as the second-stage unit circuit 120.

[0067] When the unit circuit 120 at the final stage of the shift register 110V1 outputs the output signal Gx_OUT, the scanning period P1 ends, and the stop period S1 (detection period S1) during which the output of the scanning signal (output signal) from the shift register 110 stops begins. In the period t6 which is the first period of the stop period S1, the reset signal RST that is commonly input to all the unit circuits 120 at the final stage is input to the transistor T1 of the unit circuit 120 at the final stage of the shift register 110V1. As a result, the transistor T1 becomes in the ON state, and the node N1 of the unit circuit 120 at the final stage becomes at a low potential. During the stop period S1, touch detection is performed by the touch detection unit 30.

[0068] When the touch detection during the stop period S1 ends, the scanning period P2 begins. In the unit circuit 120 at the first stage of the shift register 110V2, the start signal ST becomes at a high level, and the high potential of the selection signal SEL2 among the selection signals SEL1 to SEL8 having different phases is applied to the node N1. Then, the shift register 110V2 sequentially outputs the output signals Gk_OUT to Gy_OUT in the same manner as the shift register 110V1. Hereinafter, the shift registers 110V3 to 110V8 also sequentially output the output signals in the same manner as the shift register 110V2.

[0069] The control unit 50 of the display device 10 controls the entire display device 10 according to an instruction from the outside. The control unit 50 outputs input data (input image data) representing the display elements to the display control unit 40 (timing controller 42). Further, the control unit 50 outputs a control signal including a synchronization signal to the touch detection unit 30 and the display control unit 40 (timing controller 42). Furthermore, the control unit 50 supplies the low-level voltage VGL to the scanning line driving unit 46 (shift register 110) of the display control unit 40.

[0070] The control unit 50 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and a power supply circuit. The functions of the control unit 50 are realized, for example, by the CPU executing a program stored in the ROM.

[0071] As described above, in this embodiment, the start signal ST for starting the output of the scan signal (output signal) is commonly input to each of the first-stage unit circuits 120 of the shift registers 110V1 to 110V8. Also, selection signals SEL1 to SEL8 for selecting the shift registers 110 that output scan signals with different phases are input to each of the first-stage unit circuits 120. By these means, the signal wiring for supplying the start signal ST to each of the first-stage unit circuits 120 of the shift registers 110V1 to 110V8 can be shared, and the number of signal wirings can be reduced. For example, when the display unit 22 is divided into eight display areas V1 to V8 as in this embodiment, 13 signals (start signal ST, selection signals SEL1 to SEL8, reset signal RST, clock signals CLK_A, CLK_B, frame reset signal FRM) are supplied to the shift register 110 as the control signal GSI. The number of signal wirings for supplying these signals is only 13.

[0072] Referring to FIG. 10, the driving process of the display device 10 (that is, the driving method of the display device 10) will be described. As shown in FIG. 10, the driving process includes a display process (step S110) and a touch detection process (step S120). In the driving process, the display process (step S110) and the touch detection process (step S120) are alternately performed.

[0073] In the display process (step S110), scanning signals (output signals) are sequentially output from one of the eight shift registers 110V1 to 110V8 to the scanning lines GL in each of the eight display areas V1 to V8 of the display panel 20, and the scanning signals are sequentially output to each of the scanning lines GL, so that display elements or parts of the display elements are displayed in the corresponding display areas V1 to V8. When the output of the scanning signal from one shift register 110 ends, the output of the scanning signals from the eight shift registers 110V1 to 110V8 stops. Each of the eight shift registers 110V1 to 110V8 has a plurality of unit circuits 120 connected in multiple stages. The unit circuit 120 outputs a scanning signal to one scanning line GL.

[0074] First, the timing controller 42 of the display control unit 40 sequentially outputs scanning signals from one of the shift registers 110V1 to 110V8 of the scanning line driving unit 46 of the display control unit 40 to the scanning lines GL in the corresponding display areas V1 to V8 based on the control signal from the control unit 50. In this case, the timing controller 42 inputs a selection signal SEL and a start signal ST to the first-stage unit circuits 120 of each of the shift registers 110V1 to 110V8. The start signal ST is a signal for starting the output of the scanning signal and is commonly input to each of the first-stage unit circuits 120. The selection signal SEL is a signal for selecting the shift register 110 that outputs the scanning signal, and has different phases according to the scanning period P during which the shift register 110 outputs the scanning signal and the stop period S during which the shift register 110 stops outputting the scanning signal. Thereby, even if the start signal ST is commonly input to each of the first-stage unit circuits 120, the scanning signal is sequentially output from one shift register 110 to which the selection signal SEL is input.

[0075] Specifically, the timing controller 42 inputs a selection signal SEL1 and a start signal ST to the first-stage unit circuit 120 of the shift register 110V1. The start signal ST is commonly input to all the first-stage unit circuits 120. The selection signal SEL1 has a different phase from the other selection signals SEL2 to SEL8 according to the scanning period P and the stop period S. As a result, the scanning signal is sequentially output to the scanning lines GL within the corresponding display area V1 only from the shift register 110V1.

[0076] On the other hand, based on the control signal from the control unit 50, the timing controller 42 outputs a data voltage corresponding to the scanning line GL from which the scanning signal is output from the shift register 110 to each of the data lines DL from the data line driver 44. Specifically, the timing controller 42 outputs a data voltage from the data line driver 44 according to the display element or a part of the display element displayed in the display area V1.

[0077] As described above, the display element or a part of the display element is displayed in one display area (display area V1).

[0078] In the touch detection process (step S120), a touch on the display panel 20 is detected during the stop periods S1 to S8 in which the shift registers 110V1 to 110V8 stop outputting the scanning signal. The touch detection unit 30 applies a drive signal to the sensor electrodes within one detection area (for example, detection area H4) among the detection areas H1 to H8 based on the control signal of the control unit 50 and receives a response signal. Thereby, a touch on the display panel 20 is detected. When the touch detection process (step S120) ends, the drive process returns to the display process (step S110).

[0079] In the drive process of the display device 10, the display process (step S110) and the touch detection process (step S120) are repeated. In the display process (step S110), the display element or a part of the display element is sequentially displayed in the display areas V1 to V8. When an end instruction is input from the control unit 50 (step S130; YES), the drive process of the display device 10 ends.

[0080] As described above, the start signal ST for starting the output of the scanning signal is commonly input to each of the unit circuits 120 at the first stage of the shift register 110, and the selection signals SEL1 to SEL8 for selecting the shift register 110 that outputs the scanning signal and having different phases from each other are input to each of the unit circuits 120 at the first stage. Therefore, the signal wiring for supplying the start signal ST can be shared, and the number of signal wirings for supplying signals to the scanning line driving unit 46 of the display device 10 can be reduced. That is, the number of signal wirings of the display device 10 can be reduced.

[0081] Since the reset signal RST is commonly input to the unit circuit 120 at the last stage of the shift register 110, the number of signal wirings for supplying the reset signal can also be reduced, and the signal wirings of the display device 10 can be further reduced.

[0082] Also, since the selection signal SEL is input to the first terminal of the transistor T0 of the unit circuit 120 at the first stage, the threshold voltage shift of the transistor T0 of the unit circuit 120 at the first stage can be suppressed. Further, in the unit circuits 120 after the second stage, since the gate terminal and the first terminal of the transistor T0 are diode-connected, the threshold voltage shift can also be suppressed in the transistor T0 of the unit circuits 120 after the second stage.

[0083] <Embodiment 2> In Embodiment 1, eight shift registers 110V1 to 110V8 form one circuit group 100A. The eight shift registers 110V1 to 110V8 may form two circuit groups 100A and 100B. Hereinafter, the circuit groups (circuit groups 100A and 100B) may be collectively referred to as the circuit group 100.

[0084] The display device 10 of the present embodiment includes a display panel 20, a touch detection unit 30, a display control unit 40, and a control unit 50, similar to the display device 10 of Embodiment 1. Since the configuration of the display device 10 of the present embodiment is the same as that of the display device 10 of Embodiment 1 except for the scanning line driving unit 46 of the display control unit 40, the scanning line driving unit 46 of the present embodiment will be described.

[0085] Similar to the scanning line driving unit 46 of the first embodiment, the scanning line driving unit 46 of this embodiment includes eight shift registers 110V1 to 110V8 corresponding to the display regions V1 to V8 of the display panel 20 respectively. The configurations of the shift register 110 and the unit circuit 120 of this embodiment are the same as those of the first embodiment. Also, in this embodiment, for each of the shift registers 110V1 to 110V8, when the start signal ST and the selection signal SEL are input to the respective first-stage unit circuits 120, scanning signals are sequentially output from the respective unit circuits 120.

[0086] In this embodiment, as shown in FIG. 11, the shift registers 110V1 to 110V8 form two circuit groups 100A and 100B. Specifically, the shift registers 110V1 to 110V4 form the circuit group 100A, and the shift registers 110V5 to 110V8 form the circuit group 100B.

[0087] Similar to the circuit group 100A of the first embodiment, the circuit group 100A and the circuit group 100B sequentially output scanning signals respectively. Also, the circuit group 100A and the circuit group 100B sequentially output scanning signals according to the stop period S.

[0088] In this embodiment, as the start signal ST, the start signal ST1 is input to the circuit group 100A, and the start signal ST2 is input to the circuit group 100B. Also, as the selection signals SEL, the selection signals SEL1 to SEL4 are input to the circuit group 100A and the circuit group 100B. Note that the reset signal RST, the clock signal CLK_A, the clock signal CLK_B, the frame reset signal FRM, and the low-level voltage VGL are the same as those of the first embodiment.

[0089] Similar to the circuit group 100A of Embodiment 1, in one circuit group 100A, as shown in FIGS. 11 and 12, the start signal ST1 is commonly input to each of the first-stage unit circuits 120 of the shift registers 110V1 to 110V4. Also, in one circuit group 100B, the start signal ST2 is commonly input to each of the first-stage unit circuits 120 of the shift registers 110V5 to 110V8. Therefore, in one circuit group 100A or circuit group 100B, the signal wiring for supplying the start signal ST1 or the start signal ST2 can be shared.

[0090] After the output of the scan signal of the circuit group 100A (the output of the last-stage unit circuit 120 of the shift register 110V4) ends, the start signal ST2 starts to be commonly input to the first-stage unit circuits of the shift register 110 of the circuit group 100B at intervals of the stop period S (S4 minutes). Thereby, the circuit group 100A and the circuit group 100B sequentially output scan signals.

[0091] As shown in FIGS. 11 and 12, each of the selection signals SEL1 to SEL4 has a different phase from each other according to the scan period P and the stop period S, and is commonly input to each of the first-stage unit circuits of the shift registers 110 of the two circuit groups 100A and 100B. For example, the selection signal SEL1 is commonly input to the first-stage unit circuit 120 of the shift register 110V1 of the circuit group 100A and the first-stage unit circuit 120 of the shift register 110V5 of the circuit group 100B. Thereby, the signal wiring for supplying the selection signals SEL1 to SEL4 to the first-stage unit circuit 120 of the shift register 110 of the circuit group 100A and the signal wiring for supplying the selection signals SEL1 to SEL4 to the first-stage unit circuit 120 of the shift register 110 of the circuit group 100B can be shared. In the present embodiment, the number of signal wirings for supplying the selection signal SEL can be reduced to half of the number of signal wirings for supplying the selection signal SEL in Embodiment 1.

[0092] As described above, the signal wiring for supplying the start signal ST1 or the start signal ST2 can be shared, and further, the signal wiring for supplying the selection signals SEL1 to SEL4 can also be shared. Therefore, in the present embodiment, the number of signal wirings for supplying signals to the scanning line driving unit 46 can be further reduced. Also in the present embodiment, the number of signal wirings of the display device 10 can be reduced.

[0093] Also, similar to the first embodiment, the threshold voltage shift of the transistor T0 of the first-stage unit circuit 120 can be suppressed.

[0094] <Embodiment 3> In the first and second embodiments, the selection signal SEL is input directly from the timing controller 42 to the first-stage unit circuit 120 of the shift register 110. The selection signal SEL may be input to the first-stage unit circuit 120 via a switching circuit 200 that is connected to each of the first-stage unit circuits 120 of the shift register 110 and outputs the selection signal SEL to the first-stage unit circuit 120 by a switching signal SW. Also, the plurality of shift registers 110 forming one circuit group 100 may form a plurality of shift register groups 111.

[0095] The display device 10 of the present embodiment includes a display panel 20, a touch detection unit 30, a display control unit 40, and a control unit 50, similar to the display devices 10 of the first and second embodiments. The configuration of the display device 10 of the present embodiment is the same as that of the display devices 10 of the first and second embodiments, except for the display unit 22 and the detection region 23 of the display panel 20 and the scanning line driving unit 46 of the display control unit 40. Here, the display unit 22 and the detection region 23 of the display panel 20 and the scanning line driving unit 46 of the present embodiment will be described.

[0096] In the present embodiment, the display unit 22 of the display panel 20 is divided into 32 display regions V1 to V32 extending in the X direction, as shown in FIG. 13. Also, the detection region 23 is divided into 32 detection regions H1 to H32 extending in the Y direction, as shown in FIG. 14.

[0097] Also in this embodiment, within one frame in which display elements are displayed on the display panel 20, the display operation for displaying the display elements and touch detection are alternately performed in a time-division manner. Specifically, as shown in FIG. 15, the display operations in each of the display regions V1 to V32 are sequentially performed during each of the display periods P1 to P32. Touch detection in one of the detection regions H1 to H32 is performed during each of the detection periods S1 to S32.

[0098] The scanning line driving unit 46 of this embodiment includes 32 shift registers 110V1 to 110V32 corresponding to each of the display regions V1 to V32 of the display panel 20. The configurations of the shift register 110 and the unit circuit 120 in this embodiment are the same as those in Embodiments 1 and 2. Also in this embodiment, for each of the shift registers 110V1 to 110V32, when the start signal ST and the selection signal SEL are input to the respective first-stage unit circuits 120, scanning signals are sequentially output from each of the unit circuits 120.

[0099] Similar to the shift register 110 of Embodiment 2, the shift register 110 of this embodiment forms a plurality of circuit groups 100. In this embodiment, the shift registers 110V1 to 110V32 form four circuit groups 100A to 100D. Each of the circuit groups 100A to 100D is formed by eight shift registers 110. For example, as shown in FIG. 16, the circuit group 100A is formed by the shift registers 110V1 to 110V8.

[0100] The circuit groups 100A to 100D sequentially output scanning signals, similar to the circuit group 100A of Embodiment 1. Also, the circuit groups 100A to 100D sequentially output scanning signals according to the stop period S, similar to the circuit groups 100A and 100B of Embodiment 2.

[0101] Furthermore, in one circuit group 100, the shift register 110 forms a plurality of shift register groups 111. The plurality of shift register groups 111 sequentially output scanning signals.

[0102] In this embodiment, eight shift registers 110 within one circuit group 100 form two shift register groups 111 each having four shift registers 110. For example, the shift registers 110V1 to 110V4 of the circuit group 100A form the shift register group 111A of the circuit group 100A, and the shift registers 110V5 to 110V8 of the circuit group 100A form the shift register group 111B of the circuit group 100A.

[0103] In this embodiment, as shown in FIG. 16, the circuit group 100 includes a plurality of switching circuits 200. The switching circuits 200 are each connected to the first-stage unit circuit 120 of the shift register 110. One circuit group 100 includes eight switching circuits 200, and one shift register group 111 includes four switching circuits 200.

[0104] A selection signal SEL and a switching signal SW supplied from the timing controller 42 are input to the switching circuit 200. The switching circuit 200 outputs the selection signal SEL to the first-stage unit circuit 120 according to the switching signal SW. That is, the switching circuit 200 controls whether to input the selection signal SEL to the first-stage unit circuit 120.

[0105] As shown in FIG. 17, the switching circuit 200 is, for example, a switch circuit formed of TFTs. Also, the switching signal SW is one of the control signals GSI supplied from the timing controller 42. Note that in FIG. 17, the clock signal CLK_A, the low-level voltage VGL, etc. are omitted.

[0106] Next, signals input to and output from the circuit group 100 of this embodiment will be described. Since the clock signal CLK_A, the low-level voltage VGL, etc. of this embodiment are the same as those of the first embodiment, here, as signals input to the circuit group 100, the start signal ST, the selection signal SEL, and the switching signal SW will be described.

[0107] In this embodiment, as the start signal ST, each of the start signals ST1 to ST4 is input to each of the circuit groups 100A to 100D. Similar to the start signals ST1 and ST2 in Embodiment 2, each of the start signals ST1 to ST4 starts to be input to the corresponding circuit group 100 after the output of the scan signal of the previous circuit group 100 (the output of the unit circuit 120 at the final stage) ends, with an interval of the stop period S. Thereby, the circuit groups 100A to 100D sequentially output scan signals. For example, in the configuration shown in FIG. 16, after the output of the scan signal of the circuit group 100A (the output of the unit circuit 120 at the final stage of the shift register 110V8) ends, the start signal ST2 starts to be input to the circuit group 100B with an interval of the stop period S.

[0108] Similar to the start signals ST1 and ST2 in Embodiment 2, each of the start signals ST1 to ST4 is commonly input to each of the unit circuits 120 at the first stage of the shift register 110 in the circuit group 100 to which each of the start signals ST1 to ST4 is input. Thereby, similar to Embodiment 2, the signal wiring for supplying the start signal ST can be shared, and the number of signal wirings can be reduced. Except for the start signal ST, the signals input to the circuit group 100A are the same as those input to the circuit groups 100B to 100D. Therefore, hereinafter, mainly taking the circuit group 100A as an example, the selection signal SEL, the switching signal SW, and the output signal will be described.

[0109] In this embodiment, each of the selection signals SEL1 to SEL4 is input to each of the switching circuits 200 of one shift register group 111 of the circuit group 100. As shown in FIG. 18, each of the selection signals SEL1 to SEL4 has a different phase from each other according to the scan period P and the stop period S. Also, each of the selection signals SEL1 to SEL4 is commonly input to each of the switching circuits 200 of the shift register group 111. Thereby, similar to Embodiment 2, the signal wiring for supplying the selection signals SEL1 to SEL4 can be shared, and the number of signal wirings can be reduced.

[0110] For example, each of the selection signals SEL1 to SEL4 is input to each of the switching circuits 200 of the shift register group 111A of the circuit group 100A. Each of the selection signals SEL1 to SEL4, together with each of the switching circuits 200 of the shift register group 111A of the circuit group 100A, is also commonly input to each of the switching circuits 200 of the other shift register group 111B of the circuit group 100A, and each of the switching circuits 200 of the shift register groups 111A and 111B of the circuit groups 100B to 100D.

[0111] In this embodiment, as the switching signal SW, switching signals SW1 and SW2 are input to the switching circuit 200. Each of the switching signals SW1 and SW2 is input to the switching circuit 200 at different timings for each shift register group 111 with its phase adjusted to the phase of each of the selection signals SEL1 to SEL4. Further, the switching signal SW1 is commonly input to each of the switching circuits 200 of the shift register group 111A of the circuit groups 100A to 100D, and the switching signal SW2 is commonly input to each of the switching circuits 200 of the shift register group 111B of the circuit groups 100A to 100D. Thereby, the signal wirings for supplying the switching signals SW1 and SW2 can be shared, and the number of signal wirings can be reduced.

[0112] For example, as shown in FIGS. 17 and 18, the switching signal SW1 is input to a switching circuit 200 (hereinafter referred to as switching circuit 200V1) connected to the first-stage unit circuit 120 of the shift register 110V1 in the shift register group 111A of the circuit group 100A at the same timing as the selection signal SEL1. The switching circuit 200 outputs the selection signal SEL to the first-stage unit circuit 120 according to the switching signal SW. Therefore, the switching circuit 200V1 outputs the selection signal SEL1a as the selection signal SEL to the first-stage unit circuit 120 of the shift register 110V1. The selection signal SEL1a is input to the first-stage unit circuit 120 of the shift register 110V1. When the start signal ST1 is input to the first-stage unit circuit 120 of the shift register 110V1 at the same timing as the input of the selection signal SEL1a, the shift register 110V1 sequentially outputs output signals from the unit circuit 120 (display period P1).

[0113] Next, at the same timing as the selection signal SEL2, it is input to a switching circuit 200 (hereinafter referred to as switching circuit 200V2) connected to the first-stage unit circuit 120 of the shift register 110V2 in the shift register group 111A of the circuit group 100A. In this case, similar to the switching circuit 200V1, the switching circuit 200V2 outputs the selection signal SEL2a as the selection signal SEL to the first-stage unit circuit 120 of the shift register 110V2. Then, when the selection signal SEL2a and the start signal ST1 are input to the first-stage unit circuit 120 of the shift register 110V2, the shift register 110V2 sequentially outputs output signals from the unit circuit 120 (display period P2).

[0114] Regarding the shift registers 110V3 and 110V4 in the shift register group 111A of the circuit group 100A as well, output signals are sequentially output from the unit circuit 120 (display periods P3 and P4) by the selection signals SEL3a and SEL4a input from the switching circuits 200 (switching circuits 200V3 and 200V4) connected to the first-stage unit circuit 120 and the start signal ST1.

[0115] The switching signal SW2 is input to the switching circuit 200 of the shift register group 111B of the circuit group 100A at a timing different from that of the switching signal SW1. Specifically, the switching signal SW2 is input to the switching circuit 200 of the shift register group 111B after the input of the switching signal SW1 to the switching circuit 200 (switching circuits 200V1 to 200V4) of the shift register group 111A is completed.

[0116] First, the switching signal SW2 is input to the switching circuit 200 (hereinafter referred to as the switching circuit 200V5) connected to the first-stage unit circuit 120 of the shift register 110V5 of the shift register group 111B of the circuit group 100A at the same timing as the selection signal SEL1. In this case, similar to the switching circuits 200V1 to 200V4, the switching circuit 200V5 outputs the selection signal SEL1b as the selection signal SEL to the first-stage unit circuit 120 of the shift register 110V5. Then, when the selection signal SEL1b and the start signal ST1 are input to the first-stage unit circuit 120 of the shift register 110V5, the shift register 110V5 sequentially outputs output signals from the unit circuit 120 (display period P5).

[0117] Regarding the shift registers 110V6 to 110V8 of the shift register group 111B of the circuit group 100A, output signals are sequentially output from the unit circuit 120 by the selection signals SEL2b to SEL4b and the start signal ST1 input from the switching circuits 200 (switching circuits 200V6 to 200V8) connected to the first-stage unit circuit 120 (display periods P6 to P8).

[0118] Also in the circuit groups 100B to 100D, similar to the circuit group 100A, the start signal ST, the selection signal SEL, the switching signal SW, etc. are input, and output signals are sequentially output.

[0119] In this embodiment, four selection signals SEL are input to a circuit group 100 formed by eight shift registers 110. The four selection signals SEL (SEL1 to SEL4) are controlled by a switching circuit 200 for input to the shift registers 110, and are input to each of the eight shift registers 110 as eight selection signals SEL (SEL1a to SEL4a, SEL1b to SEL4b). Therefore, even including the signal wiring for supplying the switching signal SW to the switching circuit 200, the scanning line driving unit 46 of this embodiment can reduce the number of signal wirings for supplying signals compared to the scanning line driving unit 46 not provided with the switching circuit 200.

[0120] For example, in Embodiment 2, when the display unit 22 is divided into 32 display areas V1 to V32 and the detection area 23 is divided into 32 detection areas H1 to H32, and four circuit groups 100 are formed from 32 shift registers 110, 16 signals (start signals ST1 to ST4, selection signals SEL1 to SEL8, reset signal RST, clock signals CLK_A, CLK_B, frame reset signal FRM) are required. On the other hand, in this embodiment, the number of necessary signals is only 14 (start signals ST1 to ST4, selection signals SEL1 to SEL4, switching signals SW1, SW2, reset signal RST, clock signals CLK_A, CLK_B, frame reset signal FRM).

[0121] As described above, also in this embodiment, the signal wiring for supplying the start signal ST can be shared, and the signal wiring for supplying the selection signal SEL can also be shared. Furthermore, since the switching circuit 200 controls the input of the selection signal SEL to the shift register 110, the number of signal wirings for supplying the selection signal SEL can be reduced, and the signal wiring for supplying the switching signal SW to the switching circuit 200 can also be shared. Thereby, the number of signal wirings for supplying signals to the scanning line driving unit 46 can be further reduced.

[0122] <Modification Example> Although the embodiments have been described above, the present disclosure can be variously modified without departing from the gist.

[0123] In the embodiment, an in-cell type color liquid crystal display panel is used as the display panel 20, but the display panel 20 may be other display panels. For example, the display panel 20 may be an OLED (Organic Light Emitting Diode) display panel.

[0124] For example, in the embodiment, the display portion 22 of the display panel 20 is divided into eight display regions V1 to V8. The number of divisions for dividing the display portion 22 is arbitrary.

[0125] The number of divisions for dividing the detection region 23 is also arbitrary. Further, the detection regions H1 to H8 may extend in the X direction.

[0126] In the embodiment, the common electrode of the display panel 20 is divided, and the divided common electrodes constitute the sensor electrodes SE. The sensor electrodes SE may be provided on the display panel 20 separately from the common electrode.

[0127] The touch detection unit 30 may be a touch control IC (Integrated circuit).

[0128] The unit circuit 120 and the shift register 110 may be formed from TFTs on the substrate constituting the display panel 20. When the unit circuit 120 and the shift register 110 are formed from TFTs, the semiconductor portion of the TFTs is formed from amorphous silicon, low-temperature polysilicon, oxide semiconductors, or the like.

[0129] In the embodiment, the transistors T0 to T8 of the unit circuit 120 are n-type, but the transistors T0 to T8 may be p-type.

[0130] In Embodiment 2, the scanning line driving unit 46 has two circuit groups 100A and 100B. The scanning line driving unit 46 may have three or more circuit groups. Also, the number of shift registers 110 forming one circuit group is arbitrary. The total number of shift registers 110 in the scanning line driving unit 46 only needs to correspond to the number of divisions for dividing the display unit 22.

[0131] In the embodiment, the scanning line driving unit 46 is a circuit formed in the frame portion 24. The scanning line driving unit 46 may be provided in the frame portion 24 as a scanning line driver IC. Also, the scanning line driving unit 46 may be incorporated in the TDDI.

[0132] In Embodiment 3, the shift registers 110 form a plurality of circuit groups 100. The switching circuit 200 may be applied to the scanning line driving unit 46 in which one shift register 110 forms one circuit group 100 as in Embodiment 1.

[0133] As described above, the preferred embodiments have been explained, but the present disclosure is not limited to such specific embodiments, and the present disclosure includes the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0134] 10 represents a display device, 20 represents a panel, 22 represents a display section, 23 represents a detection area, 24 represents a frame portion, 30 represents a touch detection section, 40 represents a display control section, 42 represents a timing controller, 44 represents a data line driver section, 46 represents a scanning line driver section, 50 represents a control section, 100, 100A to 100D represent circuit groups, 110V1 to 110V32 represent shift registers, 111, 111A to 111D represent shift register groups, 120 represents a unit circuit, 200, 200V1 to 200V8 represent switching circuits, V1 to V32 represent display areas, H1 to H32 represent detection areas, PSI represents a video signal, DSI, GSI represent control signals, SE represents a sensor electrode, SL represents a sensor wiring, PX represents a main pixel, SP represents a sub-pixel, DL, D1, Dm represent data lines, GL, G1, Gn represent scanning lines, P1 to P32 represent display periods and scanning periods, S1 to S32 represent detection periods and stop periods, ST, ST1 to ST4 represent start signals, SEL, SEL1 to SEL8, SEL1a to SEL4a, SEL1b to SEL4b represent selection signals, SW, SW1, SW2 represent switching signals, RST represents a reset signal, VGL represents a low-level voltage, FRM represents a frame reset signal, CLK_A, CLK_B represent clock signals, G1_OUT to Gn_OUT represent output signals and scanning signals, T0 to T8 represent transistors, N1, N2 represent nodes, C0, C1 represent capacitances, t0 to t6 represent periods

Claims

1. A display panel having a plurality of scanning lines and a display section divided into a plurality of display regions; a scanning line driver for sequentially outputting scanning signals to the scanning lines; a touch detection unit that detects a touch on the display panel, The scanning line driver has at least one circuit group, the circuit group includes a plurality of unit circuits connected in multiple stages and outputting the scanning signal to each of the scanning lines, and a plurality of shift registers sequentially outputting the scanning signal from each of the unit circuits to each of the scanning lines in each of the display areas; the touch detection unit detects a touch on the display panel during a stop period in which the at least one circuit group stops outputting the scanning signal; In one of the circuit groups, Each of the shift registers sequentially outputs the scanning signals by inputting a selection signal for selecting the shift register that outputs the scanning signal and a start signal for starting output of the scanning signal to the unit circuit of the first stage of the shift register; the selection signals input to the first-stage unit circuits have phases different from each other depending on a scanning period during which the circuit group outputs the scanning signal and the stop period; the start signal is input in common to each of the unit circuits in the first stage; Display device.

2. the scanning line driving unit has a plurality of the circuit groups, The plurality of circuit groups sequentially output the scanning signals; the selection signals input to the respective first-stage unit circuits are input in common to the respective first-stage unit circuits of different circuit groups; The display device according to claim 1 .

3. a reset signal for resetting the unit circuit in a final stage is commonly input to each of the unit circuits in the final stage of each of the plurality of shift registers; The display device according to claim 1 .

4. The unit circuit includes: a first transistor that controls an output of the scanning signal and outputs the scanning signal from a terminal; a second transistor connected to a node connected to the gate terminal of the first transistor and configured to boost the node; In the first stage unit circuit, the selection signal is input to a first terminal of the second transistor; the start signal is input to a gate terminal of the second transistor; The display device according to claim 1 .

5. In the unit circuits in the second stage or later, the first terminal and the gate terminal of the second transistor are diode-connected; the scanning signal output from the unit circuit at a previous stage or earlier is input to the first terminal of the second transistor; The display device according to claim 4.

6. the circuit group includes a plurality of switching circuits each connected to one of the first-stage unit circuits and configured to output the input selection signal to the first-stage unit circuit in response to a switching signal; In the one circuit group, the plurality of shift registers form a plurality of shift register groups; each of the selection signals input to the switching circuits is input in common to each of the switching circuits of different shift register groups; the selection signals input to the switching circuits connected to the first-stage unit circuits of the shift registers forming one of the shift register groups have different phases; The switching signal is input to the switching circuit at a timing different from each other for each shift register group. The display device according to claim 1 .

7. The switching circuit is a switch circuit that switches whether or not to output the selection signal in response to the switching signal. The display device according to claim 6.

8. A method for driving a display device including a display panel having a plurality of scanning lines and a display unit divided into a plurality of display regions, the method comprising: a display process in which a plurality of unit circuits are connected in multiple stages and output a scanning signal to each of the scanning lines, the unit circuits sequentially outputting the scanning signals to each of the scanning lines in each of the plurality of display areas from one of the plurality of shift registers, the shift registers sequentially outputting the scanning signals to each of the scanning lines in each of the plurality of display areas, thereby displaying the display element or a part of the display element in one of the display areas; a touch detection step of detecting a touch on the display panel during a stop period in which the plurality of shift registers stop outputting the scanning signals; In the display step, a selection signal for selecting the shift register that outputs the scanning signal and a start signal for starting output of the scanning signal are input to the unit circuit in the first stage of each of the shift registers, thereby sequentially outputting the scanning signal from one of the shift registers among the plurality of shift registers; the selection signals input to the first-stage unit circuits each have a phase different from each other depending on a scanning period during which the shift registers output the scanning signals and the stop period; The start signal is commonly input to each of the unit circuits in the first stage. A method for driving a display device.

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