Semiconductor device

Abstract

To provide a semiconductor device having a thin-film transistor with excellent electrical characteristics and reliability, and a method for mass-producing the semiconductor device.SOLUTION: A semiconductor device includes thin film transistors 107a and 170b of an inverted staggered type (bottom gate structure) in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer 103, and buffer layers 104a and 104b are provided between the semiconductor layer and source and drain electrode layers 105a and 105b. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the semiconductor layer between the source and drain electrode layers and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] A thin-film transistor (hereafter referred to as TFT) that uses an oxide semiconductor film in the channel formation region. The present invention relates to a semiconductor device having a circuit and a manufacturing method thereof. The components are electro-optical devices such as LEDs and light-emitting display devices with organic light-emitting elements. Regarding electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, a switching element made of a TFT has been installed for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices) Active matrix display devices are made up of pixels (or one dot). ) has a switching element, which increases pixel density compared to the simple matrix method. This is advantageous because it can be driven at a low voltage when the

[0004] In addition, thin film transistors (TFTs) and the like are fabricated using oxide semiconductor films in the channel formation region. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. TFTs that use zinc oxide (ZnO) as the thin film, and InGaO3 (ZnO) m Using T TFTs using these oxide semiconductor films are formed on a light-transmitting substrate. The technology for forming the semiconductor device and using it as a switching element for an image display device is described in Patent Documents 1 and 2. This is disclosed in.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] For thin-film transistors using an oxide semiconductor film in the channel formation region, high operating speed, relatively simple manufacturing processes, and sufficient reliability are required. When forming a thin-film transistor, source electrodes and drain electrodes are made of a low-resistance metal material. In particular, when manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. When a thin-film transistor structure is formed in which source electrodes and drain electrodes made of a metal material with a low electrical resistance value are in direct contact with an oxide semiconductor film, there is a risk that the contact resistance will increase. One of the factors causing the increase in contact resistance is considered to be the formation of a Schottky junction at the contact surface between the source electrodes and drain electrodes and the oxide semiconductor film.

[0007]

[0008]

[0009] In addition, a capacitance is formed at the portion where the source electrodes and drain electrodes are in direct contact with the oxide semiconductor film, resulting in a decrease in the frequency characteristics (referred to as f characteristics), which may prevent the high-speed operation of the thin-film transistor.

[0008]

[0009] ​​​Using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) In a thin film transistor, one of the problems is to reduce the contact resistance of the source electrode or the drain electrode and to provide a thin film transistor and a method for manufacturing the same.

[0010] Another problem is to improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn.

[0011] Another problem is to reduce the variation in the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn. In particular, in a liquid crystal display device, when the variation between individual elements is large, display unevenness may occur due to the variation in the TFT characteristics

[0012] Also, in a display device having a light emitting element, the on-current (I on ) of a TFT (a TFT that supplies current to a light emitting element disposed in a driving circuit or a pixel) disposed so that a constant current flows through a pixel electrode has a large variation, there is a risk of luminance variation occurring in the display screen

[0013] As described above, an object of the present invention is to solve at least one of the above problems.

Means for Solving the Problems

[0014] One embodiment of the present invention uses an oxide semiconductor film containing In, Ga, and Zn as a semiconductor layer, and is characterized by including a reverse staggered type (bottom gate structure) thin film transistor in which a buffer layer is provided between the semiconductor layer and the source electrode layer and the drain electrode layer.

[0015] ​​​​In this specification, a semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an "IGZO semiconductor layer".

[0016] An ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible.

[0017] Therefore, an ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer.

[0018] As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element that imparts an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. Incorporating magnesium, aluminum, titanium, etc. into the buffer layer has an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation, etc.

[0019] The buffer layer functions as an n+ layer and can also be referred to as a drain region or a source region.

[0020] In order to reduce the variation in the electrical characteristics of the thin film transistor, the IGZO semiconductor layer is amorphous. It is preferably in a fast state.

[0021] One form of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, a buffer layer having an n-type conductivity type on the semiconductor layer, and a source electrode layer and a drain electrode layer on the buffer layer, and has a thin film transistor. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. One form of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, a buffer layer having an n-type conductivity type on the semiconductor layer, and a source electrode layer and a drain electrode layer on the buffer layer, and has a thin film transistor. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The semiconductor layer includes a region with a thin film thickness between the source electrode layer and the drain electrode layer. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a higher carrier concentration as it... In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a higher carrier concentration as it...

[0022] One form of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, a buffer layer having an n-type conductivity type on the semiconductor layer, and a source electrode layer and a drain electrode layer on the buffer layer, and has a thin film transistor. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. One form of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a semiconductor layer on the gate insulating layer, a buffer layer having an n-type conductivity type on the semiconductor layer, and a source electrode layer and a drain electrode layer on the buffer layer, and has a thin film transistor. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The semiconductor layer includes a region with a thin film thickness between the source electrode layer and the drain electrode layer. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a higher carrier concentration as it... In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a higher carrier concentration as it... In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer.

[0023] In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. - In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer.

[0024] The oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a higher carrier concentration as it... Therefore, it has the characteristic that the hole mobility also increases. Thus, including In, Ga, and Zn The relationship between the carrier concentration and the hole mobility of the oxide semiconductor film is as shown in FIG. 27. The semiconductor The carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the layer is 1 ×10 17 atoms / cm 3 less than (more preferably 1×10 11 atoms / cm 3 or less), and the carrier concentration range (buffer layer concentration range 2) of the IGZO film suitable as the buffer layer is preferably 1×10 or more (1×10 18 atoms / cm 3 or less). The carrier concentration of the above IGZO film, when used as the semiconductor layer, is the value at room temperature without applying the source 22 atoms / cm 3 drain, and gate voltages. When the carrier concentration range of the IGZO film for the channel exceeds the above range, there is a risk of becoming normally on as a thin film transistor. Therefore, by using the IGZO film within the carrier concentration range disclosed in this specification as the channel of the semiconductor layer, a highly reliable thin film transistor can be obtained.

[0025]

[0026] Also, it is preferable to use a titanium film for the source electrode layer and the drain electrode layer. For example, using a stack of a titanium film, an aluminum film, and a titanium film results in low resistance and less occurrence of hillocks in the aluminum film.

[0027] One form of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a semiconductor layer on the gate insulating layer, and form an n-type on the semiconductor layer ​​​​​​​A buffer layer having a conductivity type is formed, and a source electrode layer and a drain electrode layer are formed on the buffer layer. The semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer. The gate insulating layer, the semiconductor layer, the buffer layer having an n-type conductivity type, the source electrode layer, and the drain electrode layer can be continuously formed without being exposed to the atmosphere. When continuously forming a film, defects caused by impurities in the atmosphere becoming dust and mixing into the interface can be reduced.

[0028] The gate insulating layer, the semiconductor layer, the buffer layer having an n-type conductivity type, the source electrode layer, and the drain electrode layer can be formed by a sputtering method. The gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere (or an atmosphere of 90% or more oxygen and 10% or less rare gas (argon)), and the buffer layer having an n-type conductivity type is preferably formed in a rare gas (argon) atmosphere. When continuously forming a film using the sputtering method in this way, the productivity is high and the reliability of the thin film interface is stabilized. Also, when the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen, a decrease in reliability due to deterioration and a shift of the thin film transistor characteristics to the normal-on side can be reduced. One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a semiconductor layer on the gate insulating layer, and form an n-type buffer layer on the semiconductor layer.

[0029] The gate insulating layer, the semiconductor layer, the buffer layer having an n-type conductivity type, the source electrode layer, and the drain electrode layer The gate insulating layer and the semiconductor layer may be formed by a sputtering method. The gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere (or an atmosphere of 90% or more oxygen and 10% or less rare gas (argon)), and the buffer layer having an n-type conductivity type is preferably formed in a rare gas (argon) atmosphere. The gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere (or an atmosphere of 90% or more oxygen and 10% or less rare gas (argon)), and the buffer layer having an n-type conductivity type is preferably formed in a rare gas (argon) atmosphere. When continuously forming a film using the sputtering method in this way, the productivity is high and the reliability of the thin film interface is stabilized. Also, when the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen, a decrease in reliability due to deterioration and a shift of the thin film transistor characteristics to the normal-on side can be reduced.

[0030] When continuously forming a film using the sputtering method in this way, the productivity is high and the reliability of the thin film interface is stabilized. Also, when the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen, a decrease in reliability due to deterioration and a shift of the thin film transistor characteristics to the normal-on side can be reduced. One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a semiconductor layer on the gate insulating layer, and form an n-type buffer layer on the semiconductor layer. When the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen, a decrease in reliability due to deterioration and a shift of the thin film transistor characteristics to the normal-on side can be reduced. One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a semiconductor layer on the gate insulating layer, and form an n-type buffer layer on the semiconductor layer.

[0031] One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a semiconductor layer on the gate insulating layer, and form an n-type buffer layer on the semiconductor layer. On the gate insulating layer, a semiconductor layer is formed, and on the semiconductor layer, an n-type buffer layer is formed. A buffer layer having a conductivity type is formed, and a source electrode layer and a drain electrode layer are formed on the buffer layer. The semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer. The gate insulating layer, the semiconductor layer, the buffer layer, the source electrode layer, and the drain electrode layer are continuously formed without being exposed to the atmosphere.

Advantages of the Invention

[0032] According to one embodiment of the present invention, a thin-film transistor with low photocurrent, small parasitic capacitance, and high on-off ratio can be obtained, and a thin-film transistor with good dynamic characteristics can be fabricated. Therefore, a semiconductor device having a thin-film transistor with high electrical characteristics and high reliability can be provided.

Brief Description of the Drawings

[0033]

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Embodiments for Carrying Out the Invention

[0034] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. Without departing from the spirit and scope of the present invention, those skilled in the art can easily understand that the form and details can be variously changed. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. Among those skilled in the art, it is easily understood that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. Among those skilled in the art, it is easily understood that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted.

[0035] (Embodiment 1) In this embodiment, the thin film transistor and its manufacturing process will be described with reference to FIGS. 1 to 4. The thin film transistors 170a, 170b, and 170c having a bottom gate structure according to this embodiment are shown in FIGS. 1 and 2. FIG. 1(A1) is a plan view, and FIG. 1(A2) is a cross-sectional view taken along line A1 - A2 in FIG. 1(A1). FIG. 1(B1) is a plan view, and FIG. 1(B2) is a cross-sectional view taken along line B1 - B2 in FIG. 1(B1). FIG. 2(A1) is a plan view, and FIG. 2(A2) is a cross-sectional view taken along line C1 - C2 in FIG. 2(A1).

[0036] In FIG. 1, on a substrate 100, a thin film transistor 170a including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided. As the semiconductor layer 103, an oxide semiconductor film containing In, Ga, and Zn is used, and between the source electrode layer or the drain electrode layers 105a and 105b and the semiconductor layer 103 which is an IGZO semiconductor layer In FIG. 1, a thin film transistor 170a including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided. In FIG. 1, a thin film transistor 170a including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided. In FIG. 2, a thin film transistor 170b including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided.

[0037] In FIG. 1, on a substrate 100, a thin film transistor 170a including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided. As the semiconductor layer 103, an oxide semiconductor film containing In, Ga, and Zn is used, and between the source electrode layer or the drain electrode layers 105a and 105b and the semiconductor layer 103 which is an IGZO semiconductor layer In FIG. 1, on a substrate 100, a thin film transistor 170a including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, buffer layers 104a and 104b having an n-type conductivity type, and a source electrode layer or a drain electrode layer 105a and 105b is provided.

[0038] As the semiconductor layer 103, an oxide semiconductor film containing In, Ga, and Zn is used, and between the source electrode layer or the drain electrode layers 105a and 105b and the semiconductor layer 103 which is an IGZO semiconductor layer and the semiconductor layer 103 which is an IGZO semiconductor layer, A buffer layer 104a and 104b having a carrier concentration higher than that of the semiconductor layer 103 is intentionally provided to form an ohmic contact.

[0039] As the buffer layers 104a and 104b, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layers 104a and 104b may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are contained in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment, etc. after film formation.

[0040] In the present embodiment, the carrier concentration range of the semiconductor layer is less than 1×10 17 atoms / cm 3 (more preferably, 1×10 11 atoms / cm 3 or more), and the carrier concentration range of the buffer layer is preferably 1×10 atoms / cm 18 or more (1×10 3 atoms / cm 22 or less 3 ). ) is preferred.

[0041] If the carrier concentration range of the IGZO film for the channel exceeds the above range, there is a risk of becoming normally on as a thin film transistor. Therefore, by using the IGZO film within the carrier concentration range of the present embodiment as the channel of the semiconductor layer, a highly reliable thin film transistor can be obtained. ​​​​​​​​

[0042] Also, when a second buffer layer that functions as an n-layer and has a carrier concentration lower than that of the buffer layer and higher than that of the semiconductor layer is provided between the semiconductor layer and the buffer layer, the carrier concentration of the second buffer layer may be set within the concentration range between the carrier concentrations of the semiconductor layer and the buffer layer. The buffer layers 104a and 104b function as n+-layers and can also be referred to as the drain region or the source region. Note that the buffer layers 104a and 104b have a taper at the ends, and in the plan views of FIGS. 1(A1) and 1(B1), the buffer layers 104a and 104b indicate the upper ends of the taper. Therefore, in the plan views of FIGS. 1(A1) and 1(B1), the ends of the gate electrode layer 101 coincide with the ends of the buffer layers 104a and 104b as described, but as shown in FIGS. 1(A2) and 1(B2), the gate electrode layer 101 partially overlaps with the buffer layers 104a and 104b. This is the same in other drawings of this specification. The thin film transistor 170a in FIGS. 1(A1) and 1(A2) is an example in which the buffer layers 104a and 104b and the source electrode layer or drain electrode layers 105a and 105b are etched using different masks, and the buffer layers 104a and 104b and the source electrode layer or drain electrode layers 105a and 105b have different shapes.

[0043]

[0044]

[0045] The thin film transistor 170b in FIGS. 1(B1) and 1(B2) is an example in which the buffer layers 104a and 104b and the source electrode layer or drain electrode layers 105a and 105b are etched using the same mask. This is an example of processing, reflecting the same shape as the buffer layers 104a and 104b and the source electrode layer or drain electrode layer 1 05a and 105b.

[0046] Also, the thin film transistors 170a and 170b in FIGS. 1(A1), (A2), (B1), and (B2) are such that, on the semiconductor layer 103, the ends of the source electrode layer or drain electrode layers 105a and 105b do not coincide with the ends of the buffer layers 104a and 104b, and an example where the buffer layers 104a and 104b are partially exposed.

[0047] On the other hand, the thin film transistor 170c in FIGS. 2(A1) and (A2) is an example of etching the semiconductor layer 103 and the buffer layers 104a and 104b using the same mask, and the ends of the semiconductor layer 10 3 and the buffer layers 104a and 104b coincide. Note that the thin film transistor 170c in FIGS. 2(A1) and (A2) is also an example where, on the semiconductor layer 103, the ends of the source electrode layer or drain electrode layers 105a and 105b coincide with the ends of the buffer layers 104a and 104b. There is.

[0048] Furthermore, a thin film transistor 170d having a stacked structure of a source electrode layer or a drain electrode layer is shown in FIG. 11. The thin film transistor 170d has a stack of source electrode layers or drain electrode layers 105a1 , 105a2, and 105a3, and a stack of source electrode layers or drain electrode layers 105b1, 105 b2, and 105b3. For example, titanium films can be used for the source electrode layer or drain electrode layers 105 a1 and 105b1, aluminum films for 105a2 and 105b2, and titanium films for 10 5a3 and 105b3. It is possible.

[0049] In the thin film transistor 170d, the source electrode layer or the drain electrode layer 105a1, 105b uses 1 as an etching stopper, and etches and forms the source electrode layer or the drain electrode layer 105a2, 105a3, 105b2, 105b3 by wet etching. Using the same mask as the above wet etching, the source electrode layer or the drain electrode layer 105a1, 105b1, the buffer layer 104a, 104b, and the semiconductor layer 103 are etched and formed by dry etching.

[0050] Therefore, the source electrode layer or the drain electrode layer 105a1 coincides with the end of the buffer layer 104a, and the source electrode layer or the drain electrode layer 105b1 coincides with the end of the buffer layer 104b, respectively, and the source electrode layer or the drain electrode layer 105a2, 105a3, the source electrode layer or the drain electrode layer 105b2, 105b3 have ends that recede from the source electrode layer or the drain electrode layer 105a1, 105b1.

[0051] Thus, when the selectivity in the etching process is low between the conductive film used for the source electrode layer and the drain electrode layer, and the buffer layer and the semiconductor layer, a conductive film that functions as an etching stopper may be laminated and the etching process may be performed multiple times under different etching conditions.

[0052] The manufacturing method of the thin film transistor 170a in FIGS. 1(A1)(A2) will be described with reference to FIGS. 3(A) to (G).

[0053] The gate electrode layer 101, the gate insulating layer 102, and the semiconductor film 111 are formed on the substrate 100 ( see FIG. 3(A)). The substrate 100 is barium borosilicate glass, aluminoborosilicate ​​​Glass or aluminosilicate glass, made by the fusion or float process. In addition to alkali-free glass and ceramic substrates, we also offer heat-resistant substrates that can withstand the processing temperatures of this manufacturing process. A plastic substrate having a metal substrate such as a stainless steel alloy may be used. A substrate having an insulating film on the surface of the plate may be used. The size of the substrate 100 is 320 mm× 400mm, 370mm×470mm, 550mm×650mm, 600mm×720m m, 680mm x 880mm, 730mm x 920mm, 1000mm x 1200mm, 1100mm×1250mm, 1150mm×1300mm, 1500mm×1800m m, 1900mm x 2200mm, 2160mm x 2460mm, 2400mm x 280 0mm, or 2850mm x 3050mm, etc. can be used.

[0054] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed by using a sputtering method or the like. The insulating film may be formed as a single layer or a multilayer.

[0055] The gate electrode layer 101 may be made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode layer 101 is formed using a metal material such as sulphur dioxide or an alloy material thereof. A conductive film is formed on the substrate 100 by a sputtering method or a vacuum deposition method, and then photolithography is performed on the conductive film. A mask is formed by a printing technique or an inkjet method, and a conductive film is etched using the mask. It can be formed by etching. It can also be formed by etching conductive nanoparticles such as silver, gold, and copper. The gate electrode layer 101 is formed by discharging the conductive paste by an ink-jet method and baking the same. This can be achieved. Note that as a barrier metal for improving the adhesion of the gate electrode layer 101 and preventing the diffusion of the forming material of the gate electrode layer 101 into the substrate or the underlying film, a nitride film of the above metal material may be provided between the substrate 100 and the gate electrode layer 101. Also, the gate electrode layer 101 may have a single-layer structure or a laminated structure. For example, a laminate of a molybdenum film and an aluminum film, a laminate of a molybdenum film and an alloy film of aluminum and neodymium, a laminate of a titanium film and an aluminum film, a laminate of a titanium film, an aluminum film, and a titanium film, etc. can be used. Since a semiconductor film or wiring is formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent steps. The gate insulating layer 102 and the semiconductor film 111 can be continuously formed without being exposed to the atmosphere. When forming the films continuously, each laminated interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. If the threshold voltage value is high even though the field effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as a thin film transistor cannot be achieved in a state where the driving voltage is low, and there is a risk of becoming a load. Also, if the threshold voltage value is negative,

[0056]

[0057]

[0058] ​​​​​​​​​​​​​​​ Even when the gate voltage is 0 V, a current flows between the source electrode and the drain electrode, which is likely to be a so-called normally-on type. It tends to become on.

[0059] In the case of an n-channel thin-film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied as the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state and a drain current flows is not suitable as a thin-film transistor used in a circuit. Therefore, it is desirable that a channel is formed at a positive threshold voltage as close to 0 V as possible for the gate voltage of a thin-film transistor using an oxide semiconductor film containing In, Ga, and Zn. The threshold voltage of a thin-film transistor is considered to be greatly affected by the interface of the oxide semiconductor layer, that is, the interface between the oxide semiconductor layer and the gate insulating layer. Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin-film transistor can be improved, and the complication of the manufacturing process can be prevented, realizing a thin-film transistor having both mass productivity and high performance. In particular, when moisture in the air exists at the interface between the oxide semiconductor layer and the gate insulating layer, problems such as deterioration of the electrical characteristics of the thin-film transistor, variation in the threshold voltage, and tendency to become normally on occur. By continuously forming the oxide semiconductor layer and the gate insulating layer, such hydrogen compounds can be eliminated.

[0060]

[0061]

[0062]

[0063]

[0064] ​​​​​​​​​​​Therefore, without exposing to the atmosphere, the gate insulating layer 102 and the semiconductor film 111 are formed by sputtering under reduced pressure in a continuous film formation process to obtain a good interface, low leakage current, and high current driving capability, thus realizing a thin film transistor.

[0065] Also, the gate insulating layer 102 and the semiconductor film 111, which is an oxide semiconductor film containing In, Ga, and Zn, are preferably formed in an oxygen atmosphere (or an atmosphere with 90% or more oxygen and 10% or less noble gas (such as argon or helium)).

[0066] When continuously forming films using the sputtering method in this way, the productivity is high and the reliability of the thin film interface is stable. Also, when forming the gate insulating layer and the semiconductor layer in an oxygen atmosphere to contain a large amount of oxygen, it is possible to reduce the reliability degradation due to deterioration and the phenomenon that the thin film transistor becomes normally on.

[0067] The gate insulating layer 102 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film using a CVD method, a sputtering method, or the like. The thin film transistor 170c shown in FIGS. 2(A1) and (A2) is an example of laminating the gate insulating layer 102.

[0068] As the gate insulating layer 102, it can be formed by laminating a silicon nitride film or a silicon nitride oxide film, and a silicon oxide film or a silicon oxynitride film in this order. Note that the gate insulating layer 102 does not need to be two layers, and can be formed by laminating three layers in the order of a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a silicon nitride film or a silicon nitride oxide film from the substrate side. Also the gate insulating layer 102 can be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, It can be formed of a single layer of a plain film.

[0069] Also, as the gate insulating layer 102, a silicon nitride film may be formed on the gate electrode layer 101 by plasma CVD method, and a silicon oxide film may be laminated on the silicon nitride film by sputtering method. By plasma CVD method, a silicon nitride film and a silicon oxide film may be laminated in order on the gate electrode layer 101, and a silicon oxide film may be further laminated on the silicon oxide film by sputtering method. Here, the silicon oxynitride film means that, as its composition, the oxygen content is higher than that of nitrogen, and in the concentration range, oxygen is 55 to 65 atomic %, nitrogen is 1 to 20 atomic %, Si is 25 to 35 atomic %, and hydrogen is contained in the range of 0.1 to 10 atomic %. Also, the silicon nitride oxide film means that, as its composition, the nitrogen content is higher than that of oxygen, and as the concentration range

[0070] it means that oxygen is 15 to 30 atomic %, nitrogen is 20 to 35 atomic %, Si is 25 to 35 atomic %, and hydrogen is contained in the range of 15 to 25 atomic %.

[0071] Also, as the gate insulating layer 102, a compound containing at least two kinds of oxides, nitrides, oxynitrides, or nitroxides of aluminum, yttrium, or hafnium or their compounds can also be used.

[0071] Also, the gate insulating layer 102 may contain a halogen element such as chlorine or fluorine. The concentration of the halogen element in the gate insulating layer 102 may be 1×10 atoms

[0072] / cm or more and 1×10 15 atoms / cm 3 or less at the concentration peak. 20 3

[0073] ​As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, the semiconductor film 111 may be formed by sputtering an oxide semiconductor containing In, Ga, and Zn. The conductive film may be formed to a thickness of 50 nm. Using an oxide semiconductor target containing Ga and Zn, the distance between the substrate and the target was Distance 170 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon or oxygen atmosphere In addition, the use of a pulsed direct current (DC) power supply reduces dust. This is preferable because the film thickness distribution becomes uniform.

[0074] Next, the semiconductor film 111 is processed by etching using a mask 113, and the semiconductor layer 112 is The semiconductor layer 112 is formed by photolithography or droplet deposition. A mask 113 is formed by a discharge method, and the semiconductor film 111 is etched using the mask 113. It can be formed by applying

[0075] The end of the semiconductor layer 112 is etched into a tapered shape, so that the step shape This can prevent the wiring from being cut off.

[0076] Next, In, Ga, and A semiconductor film 114 having n-type conductivity, which is an oxide semiconductor film containing Zn, is formed (FIG. 3). A mask 116 is formed on a semiconductor film 114 having an n-type conductivity. The mask 116 is formed by photolithography or inkjet printing. The conductive semiconductor film 114 is processed by etching using a mask 116 to form an n-type Form a semiconductor film 115 having a conductivity type (see Fig. 3(D)). The semiconductor film 115 having an n-type conductivity type may have a film thickness of 2 to 100 nm (preferably 20 to 50 nm). The semiconductor film 114 having an n-type conductivity type is preferably formed in an atmosphere of a noble gas (preferably argon).

[0077] As other film formation methods other than the sputtering method for oxide semiconductor films such as the semiconductor film 111 and the semiconductor film 115 having an n-type conductivity type, a vapor phase method such as a pulsed laser deposition method (PLD method) and an electron beam evaporation method can be used. Among the vapor phase methods, in terms of easy control of the composition of the material system, the PLD method is suitable from the viewpoint of mass productivity as described above, and the sputtering method is suitable.

[0078] In addition, for etching of IGZO semiconductor films such as the semiconductor film 111 and the semiconductor film 115 having an n-type conductivity type, organic acids such as citric acid and oxalic acid can be used as an etchant. For example, a 50-nm semiconductor film 111 can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Inc.).

[0079] Form a conductive film 117 on the semiconductor film 115 having an n-type conductivity type (see Fig. 3(E)).

[0080] The conductive film 117 is preferably formed of a single layer or a laminate of aluminum or an aluminum alloy added with a heat resistance improving element or a hillock preventing element such as copper, silicon, titanium, neodymium, scandium, molybdenum. Also, the film on the side in contact with the semiconductor film having an n-type conductivity type is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and a laminated structure in which aluminum or an aluminum alloy is formed thereon. ​​​​​ may also be used. Furthermore, the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched with titanium , tantalum, molybdenum, tungsten, or nitrides of these elements to form a laminated structure may also be used. Here, as the conductive film 117, a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used.

[0081] Using a laminate of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur on the aluminum film.

[0082] The conductive film 117 is formed by sputtering or vacuum deposition. Also, the conductive film 117 may be ejected and fired using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as silver, gold, copper. formed.

[0083] Next, a mask 118 is formed on the conductive film 117. Using the mask 118, the conductive film 117 is etched and separated to form the source electrode layer or drain electrode layers 105a, 105b (see Fig. 3(F)). When the conductive film 117 is wet-etched as shown in Fig. 3 of the present embodiment , since the conductive film 117 is etched isotropically, the ends of the mask 118 and the ends of the source electrode layer or drain electrode layers 105a, 105b do not match as well and are more recessed. Next, using the mask 118, an n-type semiconductor film 115 is etched to form the buffer layers 104a, 104b (see Fig. 3(G)). Note that depending on the etching conditions , in the etching process of the n-type semiconductor film 115, the exposed region of the semiconductor layer 11 2 is also partially etched to become the semiconductor layer 103. Thus, the buffer layers 104a , the channel region of the semiconductor layer 103 between 104b becomes a region with a thin film thickness as shown in FIG. 3(G). In the semiconductor layer 103 which is an IGZO semiconductor layer, the region with a thin film thickness is 2 nm or more and 200 nm or less, preferably 20 nm or more and 150 nm or less.

[0084] Furthermore, the semiconductor layer 103 may be subjected to plasma treatment. By performing plasma treatment , damage due to etching of the semiconductor layer 103 can be recovered. The plasma treatment is preferably performed in an atmosphere of O2, N2O, preferably N2, He, Ar containing oxygen. Also, it may be performed in an atmosphere in which Cl2 and CF4 are added to the above atmosphere. Note that the plasma treatment is preferably performed without bias.

[0085] The ends of the source electrode layer or drain electrode layer 105a, 105b and the ends of the buffer layers 104a, 1 04b do not coincide and are offset, and the ends of the buffer layers 104a, 104b are formed outside the ends of the source electrode layer or drain electrode layer 105a, 105 b.

[0086] After that, the mask 118 is removed. By the above steps, the thin film transistor 170a can be formed .

[0087] Next, the manufacturing process of the thin film transistor 170b shown in FIGS. 1(B1)(B2) is shown in FIG. 4.

[0088] FIG. 4(A) shows a state in which the mask 113 is removed in the process of FIG. 3(B). An n-type semiconductor film 114 and a conductive film 121 are sequentially laminated on the semiconductor layer 1 12 (see FIG. 4( B)). In this case, the semiconductor film 114 having a conductivity type and the conductive film 121 can be continuously formed by sputtering without being exposed to the atmosphere.

[0089] A mask 122 is formed on the semiconductor film 114 having an n-type conductivity type and the conductive film 121, and the conductive film 121 is wet-etched using the mask to form the source electrode layer or the drain electrode layer 105a, 105b (see Fig. 4(C)).

[0090] Next, the semiconductor film 114 having an n-type conductivity type is dry-etched to form the buffer layers 10 4a, 104b (see Fig. 4(D)). In the same process, a part of the semiconductor layer 112 is also etched to become the semiconductor layer 103. As shown in Fig. 4, when the same mask is used for etching to form the buffer layers 104a, 104b and the source electrode layer or the drain electrode layer 105a, 105b, the number of masks can be reduced, so that the process can be simplified and the cost can be reduced.

[0091] An insulating film may be formed as a protective film on the thin film transistors 170a, 170b, 170c. The protective film can be formed in the same manner as the gate insulating layer. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. For example, a laminate of a silicon oxide film and a silicon nitride film may be formed as the protective film on the thin film transistors 170a, 170b, 170c.

[0092] In addition, oxide semiconductor films such as the semiconductor layer 103 and the buffer layers 104a, 104b are preferably subjected to a heat treatment after film formation. The heat treatment may be performed in any process as long as it is after film formation but can be performed immediately after film formation, after the formation of the conductive film 117, after the formation of the protective film, etc. Also, it may be performed in combination with other heat treatments. The heat treatment temperature is 300°C or higher and 400°C or lower, preferably It may be set to 350 °C or lower. When the semiconductor layer 103, buffer layers 104a and 104b are continuously formed as shown in FIG. 2, heat treatment may be performed after lamination. The heat treatment may be performed multiple times in a separate process from the semiconductor layer 103 and the buffer layers 104a and 104b. When forming the source electrode layer or drain electrode layers 105a and 105b, the ends of the buffer layers 104a and 104b do not coincide and are offset, so that the distance between the ends of the source electrode layer or drain electrode layers 105a and 105b is increased. This can prevent leakage current and short circuits between the source electrode layer or drain electrode layers 105a and 105b. Therefore, a thin film transistor with high reliability and high breakdown voltage can be manufactured.

[0093] Moreover, the ends of the buffer layers 104a and 104b may be shaped to coincide with the ends of the source electrode and drain electrode, like the thin film transistor 170c in FIGS. 2(A1) and (A2). If etching for forming the source electrode layer or drain electrode layers 105a and 105b and etching for forming the buffer layers 104a and 104b are performed by dry etching, the shape can be made like the thin film transistor 170c in FIGS. 2(A1) and (A2). Also, if a semiconductor film 115 having an n-type conductivity type is etched using the source electrode and drain electrodes 105a and 105b as masks and the buffer layers 104a and 104b are formed, the shape can be made like the thin film transistor 170c in FIGS. 2(A1) and (A2). A buffer layer (an oxide semiconductor layer containing In, Ga, and Zn and having an n-type conductivity type) is not provided, a gate electrode layer, a gate insulating layer, a semiconductor layer (an oxide semiconductor containing In, Ga, and Zn)

[0094]

[0095] If it has a stacked structure including a gate electrode layer, a source electrode layer, and a drain electrode layer, the distance between the gate electrode layer and the source electrode layer or the drain electrode layer becomes short, and the parasitic capacitance generated therebetween increases. Furthermore, this increase in parasitic capacitance becomes more prominent due to the thinning of the semiconductor layer. In the form of the present embodiment, a buffer layer having a high carrier concentration such as an oxide semiconductor layer having an n-type conductivity type containing In, Ga, and Zn is provided, and a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer, a buffer layer, a source electrode layer, and a drain electrode layer is used. Therefore, even if the film thickness of the semiconductor layer is thin, the parasitic capacitance can be suppressed.

[0096] According to the present embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good operating characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided.

[0097] (Embodiment 2) The present embodiment is an example of a thin film transistor having a multi-gate structure. Therefore, other operations can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having the same functions as in Embodiment 1 and the repetition of the processes will be omitted.

[0098] In the present embodiment, the thin film transistor used in the semiconductor device will be described with reference to FIGS. 5(A)(B ) to FIGS. 7(A)(B).

[0099] FIG. 5(A) is a plan view showing the thin film transistor, and FIG. 5(B) corresponds to a cross-sectional view showing the thin film transistor 171a taken along line E1-E2 in FIG. 5(A).

[0100] As shown in FIGS. 5(A) and 5(B), on a substrate 150, there is provided a thin film transistor 171a of a multi-gate structure including gate electrode layers 151a and 151b, semiconductor layers 153a and 153b, buffer layers 154a, 154b, and 154c, and a source electrode layer or a drain electrode layer 155a and 155b. is provided.

[0101] The semiconductor layers 153a and 153b are oxide semiconductor layers containing In, Ga, and Zn, and the buffer layers 154a, 154b, and 154c are oxide semiconductor layers containing In, Ga, and Zn having an n-type conductivity type. The buffer layers 154a, 154b, and 154c functioning as a source region or a drain region (n+ layer) have a carrier concentration higher than that of the semiconductor layers 153a and 153b. is higher.

[0102] One of the semiconductor layers 153a and 153b is electrically connected to the other via the buffer layer 154c. On the other hand, the semiconductor layer 153a is electrically connected to the source electrode layer or the drain electrode layer 155a via the buffer layer 154a, and the semiconductor layer 153b is electrically connected to the source electrode layer or the drain electrode layer 155b via the buffer layer 154b. is electrically connected.

[0103] FIG. 6 shows a thin film transistor 171b of a multi-gate structure with another configuration. FIG. 6(A) is a plan view showing the thin film transistor 171b, and FIG. 6(B) corresponds to a cross-sectional view showing the thin film transistor 171b along line F 1-F2 in FIG. 6(A). In the thin film transistor 171b of FIG. 6, a wiring layer 156 formed in the same process as the source electrode layer or the drain electrode layers 155a and 155b is provided on the buffer layer 154c, and the semiconductor layer 153a and the semiconductor layer 1 53b 53b is electrically connected by the buffer layer 154c and the wiring layer 156.

[0104] FIG. 7 shows a thin film transistor 171c with a multi-gate structure of another configuration. FIG. 7(A) is a plan view showing the thin film transistor 171c, and FIG. 7(B) corresponds to a cross-sectional view showing the thin film transistor 171c along the line G 1-G2 in FIG. 7(A). In the thin film transistor of FIG. 7 171c, an example is shown in which the semiconductor layer 153a and the semiconductor layer 153b are formed as a single continuous semiconductor layer 153. The semiconductor layer 153 is provided so as to straddle the gate insulating layer 152 and the gate electrode layers 151a, 151b.

[0105] Thus, in the thin film transistor with a multi-gate structure, the semiconductor layers formed on each gate electrode layer may be provided continuously, or a plurality of semiconductor layers may be provided in electrical connection via a buffer layer and a wiring layer or the like.

[0106] The thin film transistor with a multi-gate structure of the present embodiment has a small off-current, and a semiconductor device including such a thin film transistor can be provided with high electrical characteristics and high reliability.

[0107] In the present embodiment, an example of a double gate structure with two gate electrode layers is shown as the multi-gate structure, but it can also be applied to a triple gate structure or the like having more gate electrode layers.

[0108] The present embodiment can be implemented in appropriate combination with other embodiments.

[0109] (Embodiment 3) This embodiment is an example of laminating a buffer layer in a thin-film transistor. Therefore, others can be performed in the same manner as in Embodiment 1 or Embodiment 2, and descriptions of the same parts or parts having similar functions as in Embodiment 1 or Embodiment 2, and repetitions of processes are omitted.

[0110] In this embodiment, the thin-film transistor 173 used in the semiconductor device will be described with reference to FIG. 8. Hereinafter, it will be described.

[0111] As shown in FIG. 8, a thin-film transistor 173 including a gate electrode layer 101, a semiconductor layer 103, buffer layers 106a and 106b, buffer layers 104a and 104b, and a source electrode layer or a drain electrode layer 105a and 105b is provided on a substrate 100.

[0112] In the thin-film transistor 173 of this embodiment, buffer layers 106a and 106b are provided as second buffer layers between the semiconductor layer 103 and the buffer layers 104a and 104b, respectively. Hereinafter, it will be described.

[0113] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn, and the buffer layers 10 4a, 104b, and the buffer layers 106a and 106b are oxide semiconductor layers containing In, Ga, and Zn having an n-type conductivity type.

[0114] The second buffer layer ( buffer layers 106a and 106b) provided between the semiconductor layer 103 and the buffer layers 104a and 104b has a carrier concentration higher than that of the semiconductor layer 103 and lower than that of the buffer layers 104a and 104b. While the buffer layers 104a and 104b function as n+ layers, the second buffer layer (buffer layers 106a and 106b) functions as an n- layer. Hereinafter, it will be described. Hereinafter, it will be described.

[0115] In this embodiment, the suitable carrier concentration range for the semiconductor layer 103 is 1×10 17 a toms / cm 3 less (more preferably 1×10 11 atoms / cm 3 or more), and the suitable carrier concentration range for the buffer layer is 1×10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 or less) is preferable.

[0116] If the carrier concentration range of the semiconductor layer 103 for the channel exceeds the above range, the thin film transistor may become normally-on. Therefore, by using the IGZO film within the carrier concentration range of this embodiment as the channel of the semiconductor layer 103, a highly reliable thin film transistor can be formed.

[0117] The suitable concentration range for the buffer layers 106a and 106b that function as the n-layer is a concentration range where the carrier concentration is lower than that of the buffer layers 104a and 104b that function as the n+ layer and higher than that of the semiconductor layer 103.

[0118] Thus, the buffer layer provided between the semiconductor layer and the source electrode layer or the drain electrode layer may have a stacked structure, and its carrier concentration is controlled to increase from the semiconductor layer toward the source electrode layer or the drain electrode layer.

[0119] The thin film transistor having the stacked buffer layer of this embodiment has a low off-current, and a semiconductor device including such a thin film transistor can impart high electrical characteristics and high reliability. ​​​​​​

[0120] This embodiment can be implemented in appropriate combination with other embodiments.

[0121] (Embodiment 4) This embodiment is an example in which the shape and manufacturing method of the thin-film transistor are partially different in Embodiment 1. Therefore, other operations can be performed in the same manner as in Embodiment 1, and descriptions of the same parts or parts having similar functions, and repetitions of the processes are omitted.

[0122] In this embodiment, the thin-film transistor 174 used in the display device and its manufacturing process will be described with reference to FIGS. 9 and 10. FIG. 9(A1) is a plan view of the thin-film transistor 174, and FIGS. 9(A2) and 10 correspond to cross-sectional views showing the thin-film transistor along line D1-D2 in FIG. 9(A1) and its manufacturing process.

[0123] As shown in FIGS. 9(A) and 9(B), a thin-film transistor 174 including a gate electrode layer 101, a semiconductor layer 103, buffer layers 104a and 104b, and source electrode layers or drain electrode layers 105a and 105b is provided on a substrate 100.

[0124] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn, and the buffer layers 104a and 104b are oxide semiconductor layers containing In, Ga, and Zn having an n-type conductivity type. The buffer layers 104a and 104b that function as a source region or a drain region (n+ layer) have a higher carrier concentration than the semiconductor layer 103.

[0125] The semiconductor layer 103 is electrically connected to the source electrode layer or drain electrode layer 105a via the buffer layer 104a and to the source electrode layer or drain electrode layer 105b via the buffer layer 104b. ​​​​​​​​​​​ It continues.

[0126] A manufacturing process of the thin film transistor 174 will be described with reference to FIG. Next, a gate insulating layer 102, In, G a, and a semiconductor film 131 which is a semiconductor film that is an oxide semiconductor film containing Zn; The semiconductor film has an n-type conductivity and is an oxide semiconductor film containing In, Ga, and Zn. A film 132 and a conductive film 133 are formed in this order (see FIG. 10A).

[0127] A gate insulating layer 102, a semiconductor film 131 which is an oxide semiconductor film containing In, Ga, and Zn, an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity; The semiconductor film 132 and the conductive film 133 are successively formed without being exposed to the air. By continuously forming the film without exposing it to the air, atmospheric components and airborne substances can be prevented. Since each layer interface can be formed without being contaminated by impurity elements, The variation in transistor characteristics can be reduced.

[0128] In this embodiment, an example is given in which exposure is performed using a high-resolution mask to form the mask 135. A resist is formed to form a mask 135. The resist may be a positive resist or A positive resist is used here.

[0129] Next, a multi-tone mask is used as a photomask to irradiate the resist with light. Expose.

[0130] A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. A mask that enables forming a resist mask having regions of a plurality of (typically two types) thicknesses in a single exposure and development process. Therefore, by using a multi-tone mask, it is possible to reduce the number of photomasks.

[0131] Typical examples of multi-tone masks include a grayscale mask and a halftone mask.

[0132] A grayscale mask is composed of a light-transmissive substrate, a light-shielding portion formed thereon, and a diffraction grating. In the light-shielding portion, the light transmittance is 0%. On the other hand, for the diffraction grating, by setting the intervals between light-transmitting portions such as slits, dots, and meshes to be less than or equal to the resolution limit of the light used for exposure, the light transmittance can be controlled. Note that the diffraction grating can use either periodic slits, dots, meshes, or aperiodic slits, dots, meshes.

[0133] As the light-transmissive substrate, a light-transmissive substrate such as quartz can be used. The light-shielding portion and the diffraction grating can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide.

[0134] When the grayscale mask is irradiated with exposure light, in the light-shielding portion, the light transmittance is 0%, and in the regions where the light-shielding portion and the diffraction grating are not provided, the light transmittance is 100%. Also, in the diffraction grating, it can be adjusted in the range of 10 - 70%. The adjustment of the light transmittance in the diffraction grating can be achieved by adjusting the intervals and pitches of the slits, dots, or meshes of the diffraction grating.

[0135] The halftone mask is composed of a substrate having translucency, a semi-transmissive portion formed thereon, and a light-shielding portion. The semi-transmissive portion can use MoSiN, MoSi, MoSiO, MoSiON, Cr Si, etc. The light-shielding portion can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide.

[0136] When the halftone mask is irradiated with exposure light, the light transmittance in the light-shielding portion is 0%, and the light transmittance in the region where the light-shielding portion and the semi-transmissive portion are not provided is 100%. Also, in the semi-transmissive portion, it can be adjusted in the range of 10 to 70%. The adjustment of the light transmittance in the semi-transmissive portion can be achieved by adjusting the material of the semi-transmissive portion.

[0137] After exposure using a multi-tone mask and then development, as shown in Fig. 10(B), a mask 135 having regions with different film thicknesses can be formed.

[0138] Next, using the mask 135, the semiconductor film 131, the semiconductor film 132 having an n-type conductivity type, and the conductive film 133 are etched and separated. As a result, a semiconductor film 136, a semiconductor film 137 having an n-type conductivity type, and a conductive film 138 can be formed (see Fig. 10(B)).

[0139] Next, the mask 135 is ashed. As a result, the area of the mask is reduced and the thickness becomes thinner. At this time, the resist of the mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 101) is removed, and a separated mask 139 can be formed (see Fig. 10(C)).

[0140] Using the mask 139, the conductive film 138 is etched to form a source electrode layer or a drain electrode layer 1 Form 05a and 105b. When wet-etching the conductive film 138 as in this embodiment since the conductive film 138 is etched isotropically, the ends of the mask 139 and the source electrode layer or the drain electrode layers 105a, 105b do not coincide and recede further, and a semiconductor film 137 having an n-type conductivity type and the semiconductor film 136 protrude outside the source electrode layer or the drain electrode layers 105a, 105b. Next, using the mask 139, etch the semiconductor film 137 having an n-type conductivity type and the semiconductor film 136 to form the buffer layers 104a, 10 4b and the semiconductor layer 103 (see Fig. 10(D)). Note that only a part of the semiconductor layer 103 is etched to form a semiconductor layer having a groove portion.

[0141]

[0142] The formation process of the buffer layers 104a, 104b and the groove portion of the semiconductor layer 103 can be formed in the same process. Similarly, the ends of the semiconductor layer 103 are partially etched and exposed. After that, remove the mask 139.

[0142] Through the above steps, the thin film transistor 174 shown in Figs. 9(A) and 9(B) can be manufactured. .

[0143] As in this embodiment, when using a resist mask having a plurality (typically two types) of thickness regions formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost can be reduced.

[0144] This embodiment can be implemented in appropriate combination with other embodiments.

[0145] (Embodiment 5) In this embodiment, in a display device which is an example of the semiconductor device of the invention disclosed in this specification At least a part of the driver circuit and a thin film transistor to be arranged in the pixel portion are fabricated on the same substrate. An example of this is described below.

[0146] The thin film transistor disposed in the pixel portion is according to any one of the first to fourth embodiments. In addition, the thin film transistor shown in any one of the first to fourth embodiments is formed as follows. Since the photodiode is an n-channel TFT, the driver circuit is composed of n-channel TFTs. A part of the driver circuit capable of performing this is formed on the same substrate as the thin film transistor of the pixel portion.

[0147] An active matrix liquid crystal display device which is an example of the semiconductor device of the invention disclosed in this specification. An example of a block diagram of the display device shown in FIG. A pixel portion 5301 having a plurality of pixels each having a display element on a substrate 5300 and a scanning line driver for selecting each pixel. A signal line driver circuit 5302 controls the input of a video signal to a selected pixel. 03.

[0148] In addition, the thin film transistor shown in any one of the first to fourth embodiments is an n-channel The signal line driver circuit is configured with n-channel TFTs. He explains.

[0149] The signal line driver circuit shown in FIG. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0150] The pixel section 5301 is connected to the signal line driving circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction, and is connected to the scanning line driving circuit 5302 by a plurality of scanning lines G1 to Gn (not shown) extending in the row direction. The pixel section 5301 has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. Each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

[0151] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613 and the wirings 5621_1 to 5621_M. The switch groups 5602_1 to 5602_M are respectively connected to the first wiring 5611, the second wiring 5612, the third wiring 56 13 and the wirings 5621_1 to 5621_M corresponding to the switch groups 5602_1 to 5602_M. The wirings 5621_1 to 5621_M are respectively connected to three signal lines via the first thin film transistor 5603a, the second thin film transistor 5603b and the third thin film transistor 5603c. For example, the wiring 562 1_J (any one of the wirings 5621_1 to 5621_M) in the Jth column is connected to the signal lines Sj-1, Sj, and signal line via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in the switch group 560 2_J. Sj+1.

[0152] ​​​​​​​​Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0153] Note that the driver IC 5601 is preferably formed on a single crystal substrate. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M may be connected via an FPC or the like.

[0154] Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 performs the same operation as in FIG. 14 even when the scanning lines of other rows are selected.

[0155] Note that the timing chart of FIG. 14 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 560 3c.

[0156] Note that the timing chart of FIG. 14 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, and the on / off timing of the third thin film transistor 56 ​​​​​​​The on / off timing of 03c, the signal 5721_J input to the wiring 5621_J in column J is shown.

[0157] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621 _J during the third sub-selection period T3 is input to the signal line Sj+1. Further, during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621 _J are respectively denoted as Data_j-1, Data_j, and Data_j+ 1.

[0158] As shown in FIG. 14, during the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2 , the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J ​The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 03c and input to the signal line Sj+1.

[0159] From the above, the signal line driver circuit in FIG. 13 divides one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0160] As shown in FIG. 13, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0161] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or It is preferably divided into three sub-selection periods.

[0162] As another example, as shown in the timing chart of FIG. 15, one selection period is precharged. to the second period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 may be divided. Further, the timing chart of FIG. 15 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5803 a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 562 1_J in the J-th column. As shown in FIG. 15, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603 b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is applied to the signal lines Sj- 1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603 b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data _j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a . In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time , Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b . In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c. 603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c. At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0163] From the above, the signal line driver circuit of FIG. 13 to which the timing chart of FIG. 15 is applied By providing a precharge selection period before the sub selection period, the signal lines can be precharged. This allows high-speed writing of video signals to the pixels. In this embodiment, the same reference numerals are used for the same parts as those in FIG. 14, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0164] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP ) is input, the selection signal is generated. The generated selection signal is buffered The signal is buffered and amplified in the 10-bit signal line and then fed to the corresponding scan line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be capable of passing a large current. Used.

[0165] One form of a shift register used as a part of a scanning line driving circuit is shown in FIG. 16 and FIG. 17. He explains.

[0166] The circuit configuration of the shift register is shown in Figure 16. The shift register shown in Figure 16 has multiple free It is composed of flip-flops 5701_i (flip-flops 5701_1 to 5701_n). Also, it operates when a first clock signal, a second clock signal, a start pulse signal, and a reset signal are input.

[0167] The connection relationship of the shift register in FIG. 16 will be described. In the shift register of FIG. 16, the flip-flop 5701_i at the i-th stage (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 17 connected to the seventh wiring 5717_i-1, the second wiring 5502 shown in FIG. 17 connected to the seventh wiring 5717_i+1, the third wiring 5503 shown in FIG. 17 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 connected to the fifth wiring 5715.

[0168] Also, the fourth wiring 5504 shown in FIG. 17 is connected to the second wiring 5712 in the flip-flops at odd-numbered stages and to the third wiring 5713 in the flip-flops at even-numbered stages, and the fifth wiring 5505 shown in FIG. 17 is connected to the fourth wiring 5714.

[0169] However, the first wiring 5501 shown in FIG. 17 of the flip-flop 5701_1 at the first stage is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 17 of the flip-flop 5701_n at the n-th stage is connected to the sixth wiring 5716.

[0170] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Further, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the first ​​​​​​​​​​​​It may be called the power line of 2.

[0171] Next, the details of the flip-flop shown in FIG. 16 are shown in FIG. 17. The flip -flop shown in FIG. 17 includes a first thin-film transistor 5571, a second thin-film transistor 5572, a third thin-film transistor 5573, a fourth thin-film transistor 5574, a fifth thin-film tran sistor 5575, a sixth thin-film transistor 5576, a seventh thin-film transistor 5577 and an eighth thin-film transistor 5578. Note that the first thin-film transistor 5571, the second thin-film transistor 5572, the third thin-film transistor 5573, the fourth thin-film tran sistor 5574, the fifth thin-film transistor 5575, the sixth thin-film transistor 5576, the seventh thin-film transistor 5577 and the eighth thin-film transistor 5578 are n-channel type transistors, and are assumed to be in an on state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

[0172] Next, the connection configuration of the flip-flop shown in FIG. 16 is shown below.

[0173] The first electrode (either the source electrode or the drain electrode) of the first thin-film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin-film transistor 5571 is connected to the third wiring 5503.

[0174] The first electrode of the second thin-film transistor 5572 is connected to the sixth wiring 5506, and the second thin-film transistor 5572 second electrode is connected to the third wiring 5503.

[0175] The first electrode of the third thin-film transistor 5573 is connected to the fifth wiring 5505, and the third The second electrode of the thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505 .

[0176] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth thin film transistor 5574's second electrode is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571

[0177] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the fifth thin film transistor 5575's second electrode is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 .

[0178] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth thin film transistor 5576's second electrode is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572

[0179] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh thin film transistor 5577's second electrode is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 . The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 , the second electrode of the eighth thin-film transistor 5578 is connected to the gate electrode of the second thin-film transistor 5572, and the gate electrode of the eighth thin-film transistor 5578 is connected to the first wiring 550 1.

[0180] Note that the connection points of the gate electrode of the first thin-film transistor 5571, the gate electrode of the fourth thin-film transistor 5574 , the second electrode of the fifth thin-film transistor 5575, the second electrode of the sixth thin-film transistor 5576, and the second electrode of the seventh thin-film transistor 5577 are taken as the node 5543. Further, the connection points of the gate electrode of the second thin-film transistor 5572, the second electrode of the third thin-film transistor 5573, the second electrode of the fourth thin-film transistor 5574, the gate electrode of the sixth thin-film transistor 5576, and the second electrode of the eighth thin-film transistor 5578 are taken as the node 5544.

[0181] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5 504 may be respectively referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line. Further, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0182] Also, the signal line driving circuit and the scanning line driving circuit can also be fabricated only with the n-channel type TFTs shown in any one of Embodiments 1 to 4. Since the n-channel type TFTs shown in any one of Embodiments 1 to 4 have a large mobility of the transistors, it is possible to increase the driving frequency of the driving circuit. Further, the n-channel type TFTs shown in any one of Embodiments 1 to 4 contain indium, gallium, and zinc having an n-type Since the parasitic capacitance is reduced by the buffer layer which is an oxide semiconductor layer containing, the frequency characteristics (f characteristics called) are high. For example, the scanning line driving circuit using the n channel type TFT shown in any one of Embodiments 1 to 4 can be operated at high speed, so that it is also possible to increase the frame frequency or to realize black screen insertion.

[0183] Furthermore, by increasing the channel width of the transistors of the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, a scanning line driving circuit for driving the scanning lines of even rows is arranged on one side, and a scanning line driving circuit for driving the scanning lines of odd rows is arranged on the opposite side thereby making it possible to increase the frame frequency.

[0184] Also, when manufacturing an active matrix light emitting display device which is an example of the semiconductor device of the invention disclosed in this specification, in order to arrange a plurality of thin film transistors in at least one pixel it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix light emitting display device is shown in Fig. 12(B).

[0185] The light emitting display device shown in Fig. 12(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5 403 for controlling the input of the video signal to the selected pixel.

[0186] ​​​​In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 12(B) is in a digital format, When a pixel is turned on, the transistor is switched on and off to make it either emitting light or not. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradations by controlling the period during which the liquid crystal display is turned on.

[0187] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0188] In the light-emitting display device shown in FIG. 12B, a switching TFT and a When two TFTs are arranged, the first TFT, which is the gate wiring of the switching TFT, The signal input to the scanning line is generated by the first scanning line driver circuit 5402, and the current control TFT A signal input to the second scanning line, which is a gate wiring, is generated by a second scanning line driver circuit 5404. In this example, the signal input to the first scanning line and the signal input to the second scanning line are The signals for the scanning lines may be generated by a single scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. A plurality of first scan lines may be provided for each pixel. All the signals input to the multiple first scanning lines may be generated by one scanning line driver circuit. , may be generated by a plurality of scanning line driving circuits.

[0189] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those in any one of the first to fourth embodiments. It is also possible to fabricate the device using only the n-channel TFT shown in FIG.

[0190] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in devices with switching elements and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0191] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, It does not move. Also, the color of the first particle and the color of the second particle are different (including colorless). Including).

[0192] In this way, the electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The electrophoresis display does not require a polarizing plate or a counter substrate that are necessary for a liquid crystal display device, and the thickness and weight are halved. Reduced.

[0193] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also Color display is also possible by using particles having a color filter or a dye.

[0194] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by any one of the thin film transistors of Embodiment 1 to Embodiment 4 can be used. 4.

[0195] Note that the first particle and the second particle in the microcapsule may be made of a conductor material, an insulator material, A semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof May be used.

[0196] By the above steps, a highly reliable display device can be manufactured as a semiconductor device. ​​​​​

[0197] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0198] (Embodiment 6) Here, an example of manufacturing an inverted staggered thin film transistor in which at least the stack of the gate insulating layer and the oxide semiconductor layer is continuously formed without being exposed to the atmosphere is shown below. Here, the processes up to the process of continuously forming a film are shown, and for the subsequent processes, a thin film transistor may be manufactured according to any one of Embodiments 1 to 4. In the present specification, continuous film formation means that during a series of processes from the first film formation process performed by sputtering to the second film formation process performed by sputtering, the atmosphere in which the substrate to be processed is placed is always in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without being exposed to a contaminated atmosphere such as the atmosphere. By performing continuous film formation, film formation can be performed while avoiding reattachment of moisture or the like to the cleaned substrate to be processed. Up to the process of performing continuous film formation is shown, and for the subsequent processes, a thin film transistor may be manufactured according to any one of Embodiments 1 to 4. It is sufficient to manufacture a thin film transistor according to any one of Embodiments 1 to 4.

[0199] In the present specification, continuous film formation means that during a series of processes from the first film formation process performed by sputtering to the second film formation process performed by sputtering, the atmosphere in which the substrate to be processed is placed is always in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without being exposed to a contaminated atmosphere such as the atmosphere. By performing continuous film formation, film formation can be performed while avoiding reattachment of moisture or the like to the cleaned substrate to be processed. During a series of processes from the first film formation process to the second film formation process, the atmosphere where the substrate to be processed is placed is not exposed to a contaminated atmosphere such as the atmosphere, and is always controlled in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). Atmosphere) without being exposed to a contaminated atmosphere such as the atmosphere. By performing continuous film formation, film formation can be performed while avoiding reattachment of moisture or the like to the cleaned substrate to be processed. Performing continuous film formation can avoid reattachment of moisture or the like to the cleaned substrate to be processed and perform film formation. It is possible to perform film formation while avoiding reattachment of moisture or the like to the cleaned substrate to be processed.

[0200] Performing a series of processes from the first film formation process to the second film formation process within the same chamber is within the scope of continuous film formation in this specification. It is considered to be within the scope of continuous film formation in this specification.

[0201] Also, when performing a series of processes from the first film formation process to the second film formation process in different chambers, after finishing the first film formation process, the substrate is transported between the chambers without being exposed to the atmosphere and the second film formation is performed. This is also considered to be within the scope of continuous film formation in this specification. When performing a series of processes from the first film formation process to the second film formation process in different chambers, after finishing the first film formation process, the substrate is transported between the chambers without being exposed to the atmosphere and the second film formation is performed. This is also considered to be within the scope of continuous film formation in this specification.

[0202] Note that between the first film formation process and the second film formation process, there are a substrate transfer process, an alignment process, and a slow cooling process. a step of heating or cooling the substrate to a temperature required for the first process or the second process, etc. However, it is assumed that it is within the range of continuous film formation in this specification.

[0203] However, when a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation process and the second film formation process, it is not applicable to the range of continuous film formation described in this specification. shall not apply.

[0204] When performing continuous film formation without exposing to the atmosphere, it is preferable to use a multi-chamber type manufacturing apparatus as shown in FIG. 18. shall be used.

[0205] A transfer chamber 80 equipped with a transfer mechanism (typically a transfer robot 81) for transferring the substrate is provided at the center of the manufacturing apparatus. In the transfer chamber 80, a cassette chamber 82 for setting a cassette case for storing a plurality of substrates to be carried into and out of the transfer chamber is connected. shall be stored.

[0206] In addition, a plurality of processing chambers are connected to the transfer chamber 80 via gate valves 84 to 88, respectively. Here, an example of connecting five processing chambers to a transfer chamber 80 having a hexagonal upper surface shape is shown. Note that by changing the upper surface shape of the transfer chamber, the number of processing chambers that can be connected can be changed. For example, if it is square, three processing chambers can be connected, and if it is octagonal, seven processing chambers can be connected. shall be connected. For example, if it is square, three processing chambers can be connected, and if it is octagonal, seven processing chambers can be connected. shall be connected.

[0207] Among the five processing chambers, at least one processing chamber is a sputtering chamber for performing sputtering. The sputtering chamber has at least inside the chamber, a sputtering target, a power application mechanism for sputtering the target, a gas introduction means, and a means for holding the substrate at a predetermined position. A substrate holder or the like is provided. Further, in order to reduce the pressure inside the sputtering chamber , pressure control means for controlling the pressure inside the chamber is provided in the sputtering chamber.

[0208] In the sputtering method, there are an RF sputtering method using a high-frequency power source for the sputtering power source and a DC sputtering method , and there is also a pulsed DC sputtering method in which a bias is applied pulsatively. RF sputtering method is mainly used when forming an insulating film, and DC sputtering method is mainly used when forming a metal film .

[0209] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. Multi-source sputtering apparatus can also deposit different material films in the same chamber, or discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0210] There is also a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber , and a sputtering apparatus using an ECR sputtering method that uses plasma generated using microwaves without using glow discharge.

[0211] As the sputtering chamber, various sputtering methods described above are appropriately used.

[0212] Also, as a film-forming method, there is a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a thin film of their compound, and a bias sputtering method in which a voltage is also applied to the substrate during film formation .

[0213] Among the five processing chambers, one of the other processing chambers is a heating chamber that performs preheating of the substrate before sputtering , a cooling chamber that cools the substrate after sputtering, or a Let it be a chamber for performing Rasma processing.

[0214] Next, an example of the operation of the manufacturing apparatus will be described.

[0215] Set the substrate cassette containing the substrate 94 with the film-forming surface facing downward in the cassette chamber 82 , and use the vacuum evacuation means provided in the cassette chamber 82 to reduce the pressure in the cassette chamber. Incidentally, In advance, evacuate the inside of each processing chamber and the transfer chamber 80 by the vacuum evacuation means provided respectively to do so. By doing so, while the substrate is being transferred between the processing chambers, it is possible to maintain a clean state without being exposed to the atmosphere.

[0216] Incidentally, the substrate 94 with the film-forming surface facing downward has at least a gate electrode provided in advance . For example, an underlying insulating film such as a silicon nitride film or a silicon oxynitride film obtained by plasma CVD may be provided between the substrate and the gate electrode. When using a glass substrate containing an alkali metal as the substrate 94 , the underlying insulating film has the effect of suppressing the intrusion of mobile ions such as sodium from the substrate into the semiconductor region above and changing the electrical characteristics of the TFT.

[0217] Here, a silicon nitride film covering the gate electrode is formed by plasma CVD, and a substrate on which the first layer of gate insulating film is formed is used. The silicon nitride film formed by plasma CVD is dense , and by using it as the first layer of gate insulating film, the occurrence of pinholes and the like can be suppressed. Incidentally, here, an example of a laminated gate insulating film is shown, but it is not particularly limited, and a single layer or a laminate of three or more layers may be used.

[0218] Next, open the gate valve 83 and use the transfer robot 81 to move the first substrate 94 from the cassette Extract from it, open the gate valve 84 and convey it into the first processing chamber 89, and close the gate valve 8 4. In the first processing chamber 89, the substrate is heated by a heating heater or lamp heating to remove moisture and the like adhering to the substrate 94 from the gate insulating film. In particular, since the electrical characteristics of the TFT may change if moisture is contained in the gate insulating film, heating before sputter deposition is effective. If sufficient moisture has been removed at the stage when the substrate is set in the cassette chamber 82, this heat treatment is unnecessary.

[0219] Also, plasma processing means may be provided in the first processing chamber 89 to perform plasma processing on the surface of the first-layer gate insulating film. Further, heating means may be provided in the cassette chamber 82 to perform heating to remove moisture in the cassette chamber 82

[0220] Next, open the gate valve 84 and convey the substrate to the transfer chamber 80 by the transfer robot 81, open the gate valve 85 and convey it into the second processing chamber 90, and close the gate valve 85.

[0221] Here, the second processing chamber 90 is a sputter chamber using the RF magnetron sputtering method -. In the second processing chamber 90, a silicon oxide film (SiO x film) is formed as the second-layer gate insulating film. As the second-layer gate insulating film, in addition to the silicon oxide film, an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgOx film), an aluminum nitride film ( AlNx film), a yttrium oxide film (YOx film), etc. can be used.

[0222] Also, a small amount of a halogen element, for example, fluorine, chlorine, etc. may be added to the second-layer gate insulating film in the film to fix mobile ions such as sodium. As the method, the chamber ​​​​​A gas containing a halogen element is introduced therein for sputtering. However, when introducing a gas containing a halogen element, it is necessary to provide a decontamination facility in the exhaust means of the chamber. The gas concentration of the halogen element contained in the gate insulating film is preferably within the range where the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer) is 1×10 cm 15 or more and 1×10 -3 cm 20 or less. -3 Preferably, it is within the range.

[0223] When obtaining a SiOx film, artificial quartz can be used as a target, and a sputtering method using a rare gas, typically argon can be used, or a reactive sputtering method can be used in which single crystal silicon is used as a target and reacted with oxygen gas to obtain a SiOx film. Here, in order to incorporate as much oxygen as possible into the SiOx film, artificial quartz is used as a target, and sputtering is performed in an atmosphere of only oxygen or an atmosphere where oxygen is 90% or more and Ar is 10% or less to form a SiOx film with excess oxygen.

[0224] After forming the SiOx film, without exposing it to the atmosphere, the gate valve 85 is opened and the transfer robot 8 transfers the substrate to the transfer chamber 80, the gate valve 86 is opened, and it is transferred into the third processing chamber 91, and the gate valve 86 is closed.

[0225] Here, the third processing chamber 91 is a sputtering chamber using the DC magnetron sputtering method. In the third processing chamber 91, a metal oxide layer (IGZO film) is formed as a semiconductor layer. It can be formed using an oxide semiconductor target containing In, Ga, and Zn in a rare gas atmosphere or an oxygen atmosphere. Here, as much oxygen as possible is incorporated into the IGZO film. ​​​​​​ For inclusion, an oxide semiconductor containing In, Ga, and Zn is used as a target, and in an atmosphere of only oxygen or in an atmosphere where oxygen is 90% or more and Ar is 10% or less, pulsed DC sputtering is performed to form an oxygen-excess IGZO film.

[0226] In this way, without exposure to the atmosphere, by continuously depositing an oxygen-excess SiOx film and an oxygen-excess IGZO film, the interface state between the oxygen-excess films is stabilized, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before the deposition of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, causing variations in the threshold value, deterioration of electrical characteristics, and symptoms such as the TFT becoming a normally on TFT. Moisture is a hydrogen compound, and by continuously depositing without exposure to the atmosphere, the presence of hydrogen compounds at the interface can be excluded. Therefore, by continuously depositing, variations in the threshold value can be reduced, deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally on side can be reduced or preferably eliminated.

[0227] Also, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed in the sputtering chamber of the second processing chamber 90, and by sequentially laminating using a shutter to perform continuous film deposition, lamination can also be performed within the same chamber. The shutter is provided between the target and the substrate. The target for film deposition has the shutter opened, and the target for which film deposition is not performed is closed by the shutter. The advantages of laminating within the same chamber are that the number of chambers used can be reduced, and the part where the substrate is transported between different chambers This is a point where tickling or the like can be prevented from adhering to the substrate.

[0228] Next, without exposing to the atmosphere, the gate valve 86 is opened and the substrate is transported into the transfer chamber 80 by the transfer robot 81. is transported to the transfer chamber 80.

[0229] If it is not the process using a grayscale mask, at this stage, the substrate is carried out from the manufacturing apparatus through the cassette chamber, and patterning of the oxygen-excess IGZO film is performed using photolithography technology. However, if it is the process using a grayscale mask, continuous film formation shown below is continued. is carried out.

[0230] Next, without exposing to the atmosphere, the gate valve 87 is opened and the substrate is transported into the fourth processing chamber 92, and the gate valve 87 is closed.

[0231] Here, the fourth processing chamber 92 is a sputtering chamber using the DC magnetron sputtering method. In the fourth processing chamber 92, sputtering is performed by the pulsed DC sputtering method in an atmosphere of only a rare gas, and a second IGZO film serving as a buffer layer is formed in contact with the oxygen-excess IGZO film. The oxygen concentration in the film of this second IGZO film is lower than that of the oxygen-excess IGZO film. Also, as the second IGZO film, it is preferable to have a higher carrier concentration than the oxygen-excess IGZO film, and a target containing Mg, Al, or Ti may be further used for the oxide semiconductor containing In, Ga, and Zn as the target. Mg, Al, and Ti are oxidation-resistant materials, and when these materials are included in the second IGZO film, there is an oxygen blocking effect, etc., and even if heat treatment or the like is performed after film formation, the oxygen concentration of the semiconductor layer can be kept within an optimal range. This second IGZO film functions as a source region or a drain region. ​​​​​​

[0232] Next, the gate valve 87 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. The wafer is transferred to the transfer chamber 80, the gate valve 88 is opened, the wafer is transferred to the fifth processing chamber 93, and the gate Close valve 88.

[0233] Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. In the fifth treatment chamber 93, a metal multilayer film that will become a source electrode layer or a drain electrode layer is formed. A titanium target is placed in the sputtering chamber of the fifth processing chamber 93. Both the aluminum target and the aluminum target are installed, and the shutter is used to stack them one after another. In this example, aluminum is deposited on a titanium film. A titanium film is then laminated on the aluminum film.

[0234] In this way, when using a gray-tone mask, oxygen-rich Si It is possible to continuously deposit an Ox film, an oxygen-rich IGZO film, a second IGZO film, and a metal multilayer film. In particular, the interface state of the oxygen-rich IGZO film becomes more stable, improving the reliability of the TFT. If the substrate is exposed to the air before or after the IGZO film is formed, moisture may adhere to it. This adversely affects the interface state, resulting in variations in threshold voltage, deterioration of electrical characteristics, and normally-on. This may cause symptoms such as TFT. Moisture is a hydrogen compound, and By continuously depositing the film without touching the substrate, hydrogen compounds are prevented from existing at the interface of the IGZO film. Therefore, by successively depositing four layers, the threshold voltage is reduced. Reduction of ragging, prevention of deterioration of electrical characteristics, and shift of TFT to the normally-on side. can be reduced, desirably without any shift.

[0235] Also, without exposing to the atmosphere, by continuously depositing a second IGZO film serving as a buffer layer and a metal multilayer film serving as a source electrode layer and a drain electrode layer, a good interface state can be realized between the second IGZO film and the metal multilayer film, and the contact resistance can be reduced.

[0236] Also, in the sputtering chamber of the second processing chamber 90, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed, and by switching the gases introduced sequentially using a shutter and depositing three layers continuously, lamination can be performed within the same chamber. Advantages of laminating within the same chamber include reducing the number of chambers used and preventing particles and the like from adhering to the substrate while transporting the substrate between different chambers.

[0237] After repeating the above steps to perform film formation processing on the substrates in the cassette case and finishing the processing of a plurality of substrates, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and the cassette are taken out.

[0238] Also, in the first processing chamber 89, heat treatment after forming an oxygen-excessive IGZO film can be performed, specifically, heat treatment at 30 0°C to 400°C, preferably heat treatment at 350°C or higher. By performing this heat treatment, the electrical characteristics of the reverse staggered thin film transistor can be improved. This heat treatment is not particularly limited as long as it is after forming the oxygen-excessive IGZO film. For example, it can be performed immediately after forming the oxygen-excessive IGZO film or immediately after forming the metal multilayer film.

[0239] ​Next, each laminated film is patterned using a grayscale mask. It may be formed using dry etching or wet etching, or it may be selectively etched separately in multiple etching steps.

[0240] In the subsequent steps, according to any one of the above-described Embodiments 1 to 4, an inverted staggered type thin film transistor can be fabricated.

[0241] Here, a manufacturing apparatus of a multi-chamber type has been described as an example, but continuous film formation may be performed without exposing to the atmosphere using a manufacturing apparatus of an inline type in which sputtering chambers are connected in series.

[0242] Also, the apparatus shown in FIG. 18 is a so-called face-down type processing chamber in which the substrate is set with the film formation surface facing downward, but the substrate may be set vertically to form a vertically placed type processing chamber. The vertically placed type processing chamber has an advantage that its footprint is smaller than that of the face-down type processing chamber, and is effective when using a large-area substrate that may be bent due to its own weight.

[0243] (Embodiment 7) A thin film transistor of the invention disclosed in this specification can be fabricated, and a semiconductor device (also referred to as a display device) having a display function can be fabricated by using the thin film transistor in a pixel portion and further in a driving circuit. Also, a thin film transistor of the invention disclosed in this specification can be integrally formed on the same substrate as the pixel portion for part or the whole of the driving circuit to form a system-on-panel.

[0244] The display device includes a display element. Examples of the display element include a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0245] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above-mentioned is mounted. Regarding the element substrate, which corresponds to one form before the display element is completed in the process of manufacturing a display device The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only pixel electrodes of the display element are formed, or the substrate may be in a state where only pixel electrodes of the display element are formed. After the conductive film that will become the electrode is formed, but before etching is performed to form the pixel electrode. It's fine to have one, and any form is acceptable.

[0246] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit) inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0247] In this embodiment, an example of a liquid crystal display device is shown as the semiconductor device of the invention disclosed in this specification. 。

[0248] FIGS. 19(A) and (B) show an active matrix type liquid crystal display device to which the invention disclosed in this specification is applied. FIG. 19(A) is a plan view of the liquid crystal display device, and FIG. 19(B) is a cross-sectional view taken along line V-X in FIG. 19(A). The thin film transistor 201 used in the semiconductor device can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. FIGS. 19(A) and (B) show an active matrix type liquid crystal display device to which the invention disclosed in this specification is applied. FIG. 19(A) is a plan view of the liquid crystal display device, and FIG. 19(B) is a cross-sectional view taken along line V-X in FIG. 19(A). The thin film transistor 201 used in the semiconductor device can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. (A) is a cross-sectional view taken along line V-X in FIG. 19(A). The thin film transistor 201 used in the semiconductor device can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. 1 can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. In addition, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment. In addition, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 201 of this embodiment.

[0249] The liquid crystal display device of this embodiment in FIG. 19(A) includes a source wiring layer 202, a reverse staggered type thin film transistor 201 having a multi-gate structure, a gate wiring layer 203, and a capacitor wiring layer 204. The liquid crystal display device of this embodiment in FIG. 19(A) includes a source wiring layer 202, a reverse staggered type thin film transistor 201 having a multi-gate structure, a gate wiring layer 203, and a capacitor wiring layer 204. 。

[0250] Further, in FIG. 19(B), the liquid crystal display device of this embodiment includes a thin film transistor 201 having a multi-gate structure, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 used for the display element, an insulating layer 261 functioning as an alignment film, a substrate 200 provided with a polarizing plate 268, an insulating layer 263 functioning as an alignment film, an electrode layer 265 used for the display element, a coloring layer 264 functioning as a color filter, and a substrate 266 provided with a polarizing plate 267, which are opposed to each other with a liquid crystal layer 262 interposed therebetween, and have a liquid crystal display element 260. Further, in FIG. 19(B), the liquid crystal display device of this embodiment includes a thin film transistor 201 having a multi-gate structure, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 used for the display element, an insulating layer 261 functioning as an alignment film, a substrate 200 provided with a polarizing plate 268, an insulating layer 263 functioning as an alignment film, an electrode layer 265 used for the display element, a coloring layer 264 functioning as a color filter, and a substrate 266 provided with a polarizing plate 267, which are opposed to each other with a liquid crystal layer 262 interposed therebetween, and have a liquid crystal display element 260. Further, in FIG. 19(B), the liquid crystal display device of this embodiment includes a thin film transistor 201 having a multi-gate structure, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 used for the display element, an insulating layer 261 functioning as an alignment film, a substrate 200 provided with a polarizing plate 268, an insulating layer 263 functioning as an alignment film, an electrode layer 265 used for the display element, a coloring layer 264 functioning as a color filter, and a substrate 266 provided with a polarizing plate 267, which are opposed to each other with a liquid crystal layer 262 interposed therebetween, and have a liquid crystal display element 260. 00, and an insulating layer 263 functioning as an alignment film, an electrode layer 265 used for the display element, a coloring layer 264 functioning as a color filter, and a substrate 266 provided with a polarizing plate 267, which are opposed to each other with a liquid crystal layer 262 interposed therebetween, and have a liquid crystal display element 260. Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases.

[0251] Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. exists. When the cholesteric liquid crystal is heated, just before the transition from the cholesteric phase to the isotropic phase it is the phase that appears. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 262. used. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 10 μs to 1 00 μs, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency.

[0252] Although FIG. 19 is an example of a transmissive liquid crystal display device, it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0253] Also, in the liquid crystal display device of FIG. 19, a polarizing plate 267 is provided outside (the viewing side) of the substrate 266, and an example is shown in which a coloring layer 264 and an electrode layer 265 used for the display element are provided in this order on the inside. However, the polarizing plate 267 may be provided inside the substrate 266. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to FIG. 19, and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. Also, a light-shielding film that functions as a black matrix may be provided.

[0254] Also, in this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in Embodiment 1 is covered with an insulating layer (insulating layer 211, insulating layer 212, insulating layer 213) that functions as a protective film or a planarizing insulating film. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film is formed by a CVD method or the like. ​​​​​​​​A single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed by using the above method. The protective film can be formed by laminating organic silane gas and oxygen in the process gas. A silicon oxide film may be formed by plasma CVD using the same.

[0255] Organosilanes are ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethyl Silane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (T MCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilane (HMDS), triethoxysilane (SiH(OC2H5)3), or tris(dimethylamino)silane (TDS). Compounds such as ethylaminosilane (SiH(N(CH3)2)3).

[0256] An insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is a hiroma of an aluminum film. Here, the insulating layer 211 is made of an oxide film using a plasma CVD method. A silicon film is formed. TEOS and O2 are used as process gases for forming the silicon oxide film. The flow rate ratio is TEOS\O2=15\750 (sccm). The temperature is 300℃.

[0257] In addition, an insulating layer 212 is formed as the second layer of the protective film. Silicon nitride film is formed using plasma CVD. The process gas for forming silicon nitride film is , SiH4, N2, NH3 and H2 are used. A silicon nitride film is used as one layer of the protective film. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the above from happening.

[0258] Further, after forming the protective film, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed. This may be done.

[0259] Also, an insulating layer 213 is formed as a planarization insulating film. As the insulating layer 213, organic materials having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. The siloxane-based resin may have at least one of fluorine, an alkyl group, or an aromatic group in addition to hydrogen in the substituent. Note that the insulating layer 213 may be formed by laminating a plurality of insulating films formed of these materials.

[0260]

[0261] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may have at least one of fluorine, an alkyl group, or an aromatic hydrocarbon in addition to hydrogen in the substituent. For the formation of the insulating layer 213, depending on the material, a CVD method, a sputtering method, a SOG method, a spin coat, a dip, a spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When forming the insulating layer 213 using a material liquid, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed simultaneously during the baking process. By combining the baking process of the insulating layer 213 and the annealing of the IGZO semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.​​​​​​​​​​​​

[0262] The electrode layers 255 and 265 that function as pixel electrode layers are indium containing tungsten oxide oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide ide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO .), indium zinc oxide, indium tin oxide added with silicon oxide, etc., and a light-transmitting conductive material can be used.

[0263] Further, as the electrode layers 255 and 265, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used for formation. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

[0264] As the conductive polymer, so-called π-electron conjugated system conductive polymers can be used. For example polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0265] By the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device .

[0266] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0267] (Embodiment 8) In this embodiment, an example of an electronic paper is shown as the semiconductor device of the invention disclosed in this specification​​​ 。

[0268] FIG. 26 shows an active matrix type electronic paper as an example of a semiconductor device to which the invention disclosed in this specification is applied. As the thin film transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Further, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 581 of the present embodiment.

[0269] The electronic paper in FIG. 26 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by disposing spherical particles painted white and black between a first electrode layer and a second electrode layer that are electrode layers used in a display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0270] The thin film transistor 581 on the substrate 580 is an inverted staggered type thin film transistor of a multi-gate structure, and is in contact with and electrically connected to the first electrode layer 587 through a source electrode layer or a drain electrode layer, and openings formed in the insulating layers 583, 584, and 585. Between the first electrode layer 587 and the second electrode layer 588 provided on the substrate 596, there are a black region 590a and a white region 590b, and spherical particles 589 including a cavity 594 filled with a liquid around are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 26).

[0271] ​​​​​​​​​​​​Also, it is possible to use an electrophoresis element instead of the twist ball. A transparent liquid is filled with positively charged white fine particles and negatively charged black fine particles, and microcapsules with a diameter of about 10 μm to 20 0 μm are used. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required and the power consumption is small, and it is possible to recognize the display portion even in a dim place. Also even when power is not supplied to the display portion, it is possible to hold the image once displayed. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device having a display device) is separated from the radio wave transmission source it is possible to save the displayed image. By the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device .

[0272] .

[0273] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0274] (Embodiment 9) In this embodiment, an example of a light-emitting display device is shown as the semiconductor device of the invention disclosed in this specification . As the display element of the display device, here, a light-emitting element using electroluminescence is shown . The light-emitting element using electroluminescence has an organic light-emitting material It is distinguished depending on whether it is a compound or an inorganic compound. Generally, the former is an organic EL element and the latter is called an inorganic EL element.

[0275] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine to form an excited state of the light-emitting organic compound and emit light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0276] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element structure . The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder and its light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation .

[0277] Figs. 22(A) and (B) show an active matrix type light-emitting display device as an example of a semiconductor device to which the invention disclosed in this specification is applied. Fig. 22(A) is a plan view of the light-emitting display device and Fig. 22(B) is a cross-sectional view taken along line Y-Z in Fig. 22(A). In addition, Fig. 23 shows an equivalent circuit of the light-emitting display device shown in Fig. 22 .

[0278] As the thin-film transistors 301 and 302 used in the semiconductor device, in Embodiment 1 and Embodiment It can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Further, the thin film transistors shown in Embodiment 3 or Embodiment 4 can also be applied as the thin film transistors 301 and 302 of the present embodiment.

[0279] The light-emitting display device of the present embodiment shown in FIGS. 22(A) and 23 includes a thin film transistor 301 with a multi-gate structure, a thin film transistor 302, a light-emitting element 303, a capacitive element 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin film transistors 301 and 302 are n-channel type thin film transistors.

[0280] Also, in FIG. 22(B), the light-emitting display device of the present embodiment includes, on a substrate 300, a thin film tr ansistor 302, an insulating layer 311, an insulating layer 312, an insulating layer 313, a partition wall 321, and a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323 used for the light-emitting element 303.

[0281] The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, polyamide, or siloxane .

[0282] In the present embodiment, since the thin film transistor 302 of the pixel is of the n-type, it is desirable to use a cathode as the first electrode layer 320 which is the pixel electrode layer. Specifically, as the cathode, a material with a small work function, for example, Ca, Al, CaF, MgAg, AlLi, etc. can be used.

[0283] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Espe​​ Using a photosensitive material, an opening is formed on the first electrode layer 320, and it is preferable that the side wall of the opening is formed as an inclined surface having a continuous curvature.

[0284] The electroluminescent layer 322 may be composed of a single layer or may be configured such that a plurality of layers are stacked.

[0285] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The second electrode layer 323 can be formed of a transparent conductive film using a conductive material having transparency as listed as the pixel electrode layer in Embodiment 7. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323 overlap each other to form the light-emitting element 303. After that, a protective film may be formed on the second electrode layer 323 and the partition wall 321 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0286] Furthermore, in practice, when it is completed up to FIG. 22(B), it is preferable to package (encapsulate) it with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing so as not to be further exposed to the outside air.

[0287] Next, the configuration of the light-emitting element will be described with reference to FIG. 24. Here, taking the case where the driving TFT is an n-type as an example, the cross-sectional structure of the pixel will be described. The TFTs 7001, 7011, and 7021, which are driving TFTs used in the semiconductor devices of FIGS. 24(A), (B), and (C), are It can be manufactured in the same manner as the thin film transistor shown in Embodiment 1, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistors shown in Embodiment 2, Embodiment 3, or Embodiment 4 can be applied as TFT7001, 7011, 7021. For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure. The light emitting element with a top emission structure will be described with reference to FIG. 24(A). FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003.

[0288] For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure. For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure. For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure. For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure. For the light emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are top emission in which a thin film transistor and a light emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, bottom emission in which light is extracted from the surface on the substrate side, and double-sided emission structures in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration of the present embodiment can be applied to light emitting elements having any emission structure.

[0289] The light emitting element with a top emission structure will be described with reference to FIG. 24(A).

[0290] FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. FIG. 24(A) shows a cross-sectional view of a pixel when the TFT7001, which is a driving TFT, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light emitting element 7002 and the TFT7001, which is a driving TFT, are electrically connected, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer is formed on the cathode 7003. , stack them in the order of the electron transport layer, the light-emitting layer, the hole transport layer, and the hole injection layer. Note that it is not necessary to provide all of these layers. The anode 7005 is made of a conductive material having light-transmitting properties that transmit light and is formed, for example, using indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide with added selenium, or other light-transmitting conductive films. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 24(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow .

[0291]

[0292] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 24(B). When the driving TFT7 011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side, a cross-sectional view of the pixel is shown. In Fig. 24(B), the cathode 7013 of the light-emitting element 7012 is formed on the light-transmitting conductive film 7017 electrically connected to the driving TFT7011, and the light-emitting layer 7014 and the anode 7015 are sequentially stacked on the cathode 7013. When the anode 7 015 has light-transmitting properties, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as it is a conductive material with a low work function, similar to the case of Fig. 24(A). However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, a film with a thickness of 20 nm An aluminum film having a thickness can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or may be configured such that a plurality of layers are laminated, as in FIG. 24(A). The anode 7015 does not need to transmit light, but can be formed using a conductive material having translucency, as in FIG. 24(A). And the shielding film 7016 can use, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin added with a black pigment can also be used.

[0293]

[0294] The region sandwiching the light-emitting layer 7014 between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel shown in FIG. 24(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow. Next, a light-emitting element having a double-sided emission structure will be described with reference to FIG. 24(C). In FIG. 24(C), on a translucent conductive film 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and the light-emitting layer 7024 and the anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023 can use various materials as long as they are conductive materials having a small work function, as in the case of FIG. 24(A). However, the film thickness should be such that light can pass through. For example, Al having a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 may be composed of a single layer or may be configured such that a plurality of layers are laminated, as in FIG. 24(A). The anode 7025 can be formed using a translucent conductive material that transmits light, as in FIG. 24(A). ​​​​​​​​​​​​​

[0295] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in FIG. 24(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0296] Here, although the organic EL element has been described as the light-emitting element, an inorganic EL element can also be provided as the light-emitting element.

[0297] In this embodiment, an example in which a thin-film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected has been shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0298] Note that the semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 24, and various modifications based on the technical idea of the invention disclosed in this specification are possible.

[0299] By the above steps, a highly reliable light-emitting display device can be manufactured as a semiconductor device .

[0300] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0301] (Embodiment 10) Next, the configuration of a display panel, which is one form of the semiconductor device, is shown below. In this embodiment a liquid crystal display panel (also referred to as a liquid crystal panel), which is one form of a liquid crystal display device having a liquid crystal element as a display element, and a light-emitting display panel (also referred to as a light-emitting panel), which is one form of a semiconductor device having a light-emitting element as a display element, will be described.

[0302] Next, the appearance and cross-section of a light-emitting display panel corresponding to one form of the semiconductor device of the invention disclosed in this specification will be described with reference to FIG. 25. FIG. 25 is a top view of a panel in which an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type formed on a first substrate are sealed with a sealing material between the second substrate, and FIG. 25(B) corresponds to a cross-sectional view taken along H-I in FIG. 25(A). A pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on the first substrate 4501 are surrounded by a sealing material 4505. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. Also, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of thin film transistors. In FIG. 25(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated. The thin film transistors 4509 and 4510 have an IGZO semiconductor layer and an I having an n-type conductivity type.

[0303] A pixel portion 4502, signal line driver circuits 4503a, 450 3b, and scanning line driver circuits 4504a, 4504b are provided so as to surround them with a sealing material 4505. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 4504a, 4504b. Thus, the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 45 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506.

[0304] Also, the pixel portion 4502, signal line driver circuits 4503a, 4 503b, and scanning line driver circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin film transistors, and in FIG. 25(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated. The thin film transistors 4509 and 4510 have an IGZO semiconductor layer and an I having an n-type conductivity type. The thin film transistors 4509 and 4510 have an IGZO semiconductor layer and an I having an n-type conductivity type.

[0305] The thin film transistors 4509 and 4510 have an IGZO semiconductor layer and an I having an n-type conductivity type. It corresponds to a thin-film transistor including a GZO semiconductor layer, and the thin-film transistors shown in Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4 can be applied. In this embodiment, the thin-film transistors 4509 and 4510 are n-channel type thin-film transistors and.

[0306] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin-film transistor 4510. Note that the configuration of the light-emitting element 4511 is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0307] Also, various signals and potentials applied to the signal line drive circuits 4503a and 4503b, the scan line drive circuits 4504a and 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a and 4518 b.

[0308] In this embodiment, the connection terminal 4515 is formed of the same conductive film as the second electrode layer 4512, and the wiring 4516 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511.

[0309] The connection terminal 4515 is electrically connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519.

[0310] The substrate located in the light extraction direction of the light-emitting element 4511 must be light-transmissive. In that case, a glass plate, a plastic plate, a polyester film, or an acrylic film ​​​​​​​​Use a material with translucency like Irm.

[0311] In addition, as the filler 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler .

[0312] Also, if necessary, a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, due to the unevenness of the surface Diffuse the reflected light and perform an antiglare treatment that can reduce reflection.

[0313] The signal line drive circuits 4503a, 4503b, and the scan line drive circuits 4504a, 4504b are mounted on a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or only a part thereof may be separately formed and mounted, and this embodiment is not limited to the configuration of FIG. 25.

[0314] Next, the appearance and cross section of a liquid crystal display panel corresponding to one form of the semiconductor device of the invention disclosed in this specification will be described with reference to FIG. 20. FIG. 20 shows a highly reliable thin film formed on the first substrate 4001 including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. The transistors 4010, 4011, and the liquid crystal element 4013 are sealed with a sealing material 4005 between them and the second substrate 4006. This is a top view of the panel, where the sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. FIG. 20(B) corresponds to a cross-sectional view taken along M-N of FIGS. 20(A1)(A2). (A1)(A2) of M-N in the cross-sectional view corresponding.

[0315] The second substrate 4006 is provided above the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Thus, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated.

[0316] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0317] The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 each have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated.

[0318] The thin film transistors 4010 and 4011 correspond to thin film transistors including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type, and the thin film transistors shown in Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0319] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that each function as an alignment film are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0320] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, a polyester film or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0321] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is provided. Note that spherical spacers may be used.

[0322] In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel section 4 002 are supplied from the FPC 4018.

[0323] In the present embodiment, the connection terminal 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013 and the wiring 4016 is formed of the same conductive film as the gate electrode layers of the thin film transistors 4010 and 4011.

[0324] The connection terminal 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0325] In FIG. 20, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0326] FIG. 21 shows an example of a liquid crystal display module configured as a semiconductor device using the TFT substrate 2600 manufactured by applying the invention disclosed in this specification.

[0327] FIG. 21 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by the sealing material 2602, and a pixel section 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided therebetween to form a display area. ​ 。The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to each of the colors red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed . The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, a retardation plate may be laminated in a state of being between the polarizing plate and the liquid crystal layer. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment), an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal), etc.

[0328]

[0329] Through the above steps, a highly reliable display panel can be fabricated as a semiconductor device.

[0330] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is as follows.

[0331] (Embodiment 11) The semiconductor device of the invention disclosed in this specification can be applied as electronic paper. The electronic paper can be used in electronic devices in all fields as long as it can display information. For example, the electronic paper can be used for electronic books (e-books), posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 28 and 29. FIG. 28(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper

[0332] printout, the advertisement is replaced manually. However, if the electronic paper to which the invention disclosed in this specification is applied is used, the advertisement can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information.

[0333] Also, FIG. 28(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper printout, the advertisement is replaced manually. However, if the electronic paper to which the invention disclosed in this specification is applied is used, the advertisement can be changed in a short time without much manpower. Also, a stable image can be obtained without the display being distorted. Note that the advertisement may be configured to be able to wirelessly transmit and receive information.

[0334] Also, FIG. 29 shows an example of an e-book 2700. For example, the e-book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing ​​​​​The housing 2703 is integrated by the shaft portion 2711, and can perform opening and closing operations around the shaft portion 2711 as the axis. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0335] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display consecutive screens, or may be configured to display different screens. With the configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 29), and an image can be displayed on the left display unit (display unit 2707 in FIG. 29).

[0336] Also, FIG. 29 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be advanced by the operation keys 2723. Note that the housing may be configured to be provided with a key board, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, etc. may be provided. Further, the e - book 2700 may be configured to have a function as an electronic dictionary.

[0337] Also, the e - book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is also possible to purchase and download desired book data, etc. from an e - book server.

[0338] (Embodiment 12) The semiconductor device according to the invention disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of the electronic devices include a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, and a large gaming machine such as a pachinko machine. ) and so on.

[0339] FIG. 30(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. An image can be displayed by the display unit 9703. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0340] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control unit 9610, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control unit 9610.

[0341] Note that the television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and further, by connecting to a communication network by wire or wirelessly via the modem, one-way (from the sender to the receiver) or two-way communication can be performed. ​​​​It is also possible to perform information communication (between a sender and a receiver, or between receivers, etc.).

[0342] FIG. 30(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and by displaying image data taken with, for example, a digital camera, it can function in the same way as a normal photo stand.

[0343] Note that the digital photo frame 9700 has a configuration including an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals and USB cables), a recording medium insertion part, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because the design will be improved. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion part of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0344] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0345] FIG. 31(A) shows a portable game machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected so as to be openable and closable by a connecting part 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, the portable game machine shown in FIG. 31(A) has, among other things, a speaker unit 9884, a recording medium insertion part 988 ​​​​​​​​​​6. The LED lamp 9890 is provided with input means (operation keys 9885, connection terminals 9887, sensors 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), microphones 9889), etc.). Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration having at least one form of the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. The portable gaming machine shown in Fig. 31(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration having at least one form of the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. The portable gaming machine shown in Fig. 31(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions. It only needs to be a configuration having at least one form of the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. The portable gaming machine shown in Fig. 31(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions. The portable gaming machine shown in Fig. 31(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions. It has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions. Note that the functions of the portable gaming machine shown in Fig. 31(A) are not limited to this, and it can have various functions.

[0346] Fig. 31(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Also, the slot machine 9900 is provided with other operation means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it only needs to be a configuration having at least one form of the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. It only needs to be a configuration having at least one form of the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. It can be a configuration with other accessory equipment appropriately provided.

[0347] Fig. 32 shows an example of a mobile phone 1000. The mobile phone 1000 has, in addition to a display unit 1002 incorporated in a housing 100 1, operation buttons 1003, an external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0348] The mobile phone 1000 shown in FIG. 32 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or typing an e-mail can be performed by the display unit 100. This can be done by touching 2 with a finger or other object.

[0349] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0350] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0351] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0352] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0353] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and when there is no input by the touch operation of the display unit 1002 for a certain period, the screen mode may be controlled to switch from the input mode to the display mode. The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 1002 and imaging the palm print, fingerprint, etc., identity authentication can be performed. Also, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, finger veins, palm veins, etc. can also be imaged.

[0354] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 1002 and imaging the palm print, fingerprint, etc., identity authentication can be performed. Also, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, finger veins, palm veins, etc. can also be imaged. The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 1002 and imaging the palm print, fingerprint, etc., identity authentication can be performed. Also, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, finger veins, palm veins, etc. can also be imaged.

Claims

[Claim 1] a gate electrode layer; a gate insulating layer on the gate electrode layer; a semiconductor layer on the gate insulating layer; a buffer layer having an n-type conductivity on the semiconductor layer; a thin film transistor including a source electrode layer and a drain electrode layer on the buffer layer, the semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc; the buffer layer has a higher carrier concentration than the semiconductor layer; the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer.

Images