Semiconductor component and ink jet recording element substrate

Abstract

To prevent error writing to an anti-fuse element due to noise intrusion in a semiconductor component having the anti-fuse element.SOLUTION: A semiconductor component has: a semiconductor substrate; a transistor which is arranged on the semiconductor substrate and is connected to a first terminal with a first potential; an anti-fuse element connected between a second terminal with a second potential different from the first potential and the transistor; and a noise detection circuit which is electrically connected to the second terminal, detects noise and outputs a detection signal. The transistor uses the semiconductor component that is switched off on the basis of the detection signal outputted from the noise detection circuit.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a semiconductor component and an inkjet recording element substrate.

Background Art

[0002] A liquid ejection device that ejects liquid to perform recording on a recording medium such as paper generally has a liquid ejection head provided with a substrate. Such a substrate of the liquid ejection head may have a semiconductor component equipped with an anti-fuse element mounted thereon. This semiconductor component is used to record product-specific information such as chip ID and setting parameters after the completion of the product. Since the anti-fuse element basically can only be written once, it is also called an OTP (One Time Programmable) memory. For example, Patent Document 1 shows a configuration using an anti-fuse element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Document 1 discloses a semiconductor component including a voltage application circuit that supplies a voltage for writing to an anti-fuse element. In this voltage application circuit, it is possible to switch whether to apply the power supply voltage applied to the electrode pad to the anti-fuse element by a switching circuit. However, there is a possibility that a high-frequency voltage that has invaded the surge electrode due to so-called noise such as electrostatic discharge or lightning surge outside the semiconductor component may pass through the voltage application circuit, resulting in incorrect writing to the anti-fuse element.

[0005] The present invention has been made in view of the above problems. An object of the present invention is to prevent an anti-fuse element in a semiconductor component having an anti-fuse element from being erroneously written due to the intrusion of noise.

Means for Solving the Problems

[0006] The present invention employs the following configuration. That is, a semiconductor substrate, a transistor disposed on the semiconductor substrate and connected to a first terminal at a first potential, an anti-fuse element connected between a second terminal at a second potential different from the first potential and the transistor, a noise detection circuit electrically connected to the second terminal and outputting a detection signal by detecting noise and the transistor is turned off based on the detection signal output by the noise detection circuit This is a semiconductor component characterized by the above.

Effects of the Invention

[0007] According to the present invention, in a semiconductor component having an anti-fuse element, it is possible to prevent an anti-fuse element from being erroneously written due to the intrusion of noise.

Brief Description of the Drawings

[0008]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 5

Mode for Carrying Out the Invention

[0009] Hereinafter, with reference to the drawings, preferred embodiments of the present invention will be described in detail by way of example. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described in this embodiment are not intended to limit the scope of the present invention only to those, unless otherwise specified. Also, the materials, shapes, etc. of the members once described in the following description are the same as the initial description in the subsequent description unless otherwise described again. In particular, well-known techniques or publicly known techniques in the relevant technical field can be applied to configurations and processes not specifically illustrated or described. Also, duplicate explanations may be omitted.

[0010] [Example 1] (Circuit Configuration) Figure 1A is an example of the circuit configuration of a semiconductor component, showing the state before information is written to the anti-fuse element Ca.

[0011] The semiconductor component of this embodiment has a memory section 10 having a transistor MP1, a transistor MN1, a transistor MND1, and an anti-fuse element Ca. The anti-fuse element Ca is an element that has a first resistance value before information is written, and has a second resistance value smaller than the first resistance value after the information is written. That is, the resistance value of the anti-fuse element Ca changes by the information writing operation. It is preferable that the magnitude of the first resistance value is larger. Ideally, the first resistance value may be infinite. Also, it is preferable that the difference between the first resistance value and the second resistance value is larger.

[0012] The anti-fuse element Ca functions as a capacitive element before information is written, and functions as a resistive element after information is written. Since FIG. 1A shows the state before information is written to the anti-fuse element Ca, the anti-fuse element Ca is represented by the circuit symbol of a capacitive element. With such a configuration, the anti-fuse element Ca can hold the written information based on the change in the resistance value.

[0013] In FIG. 1A, the transistor MP1 is a P-type transistor, and the transistor MN1 is an N-type transistor. Also, the output signal of a noise detection signal input circuit NAND1 (described later) is input to the gates of the transistor MP1 and the transistor MN1.

[0014] Also, a power supply voltage VDD (for example, 3.3 V) is supplied to the source and back gate of the transistor MP1, and the drain is connected to the drain of the MN1 and the gate of the transistor MD1. The source and back gate of the transistor MN1 are connected to the ground GND. The transistor MP1 and the transistor MN1 form a logic circuit (an inverter in FIG. 1A).

[0015] Transistor MND1 is an N-type high-voltage transistor that controls the application of voltage to the anti-fuse element Ca. Transistor MND1 can be configured, for example, by an NMOS transistor. Here, the high-voltage transistor is a transistor having a higher breakdown voltage than transistors (such as MP1 and MN1) used in logic circuits. The high-voltage transistor is preferably formed so as not to fail even when a large voltage (for example, 32V) that cannot be withstood by transistors in general logic circuits such as a control unit is applied. Also, by making transistors MP1 and MN1 that constitute the logic circuit transistors with a lower breakdown voltage than transistor MND1, the logic circuit can be operated at high speed.

[0016] The anti-fuse element Ca is connected to wiring B via transistor MND1. As the anti-fuse element Ca, for example, an anti-fuse element having a MOS structure (Metal Oxide Semiconductor structure) can be used. The anti-fuse element Ca is connected to wiring A.

[0017] Wiring A and wiring B are connection parts for electrically connecting the memory unit 10 and an external circuit, and are terminals for applying a voltage to the anti-fuse element Ca or measuring a voltage. For example, the potential of wiring A can be set to a high voltage (for example, 32V) during information writing. The drain of transistor MND1 is connected to one terminal of the anti-fuse element Ca, and the source of transistor MND1 is connected to GND. The other terminal of the anti-fuse element Ca is connected to wiring A. Wiring B (the first terminal) is set to, for example, the ground potential GND (the first potential).

[0018] The voltage application circuit 11 is a circuit that switches whether or not to supply the high voltage (the second potential) applied to the VH terminal to wiring A based on the control signal Sig2. The VH terminal is, for example, an external connection terminal of 32V and corresponds to the second terminal. The voltage application circuit 11 can be configured to include, for example, a P-type high-voltage MOS transistor MPD1 as shown in FIG. 1B. as shown.

[0019] As shown in FIG. 1C, the transistor MPD1 may be configured to perform a switching operation based on a control signal Sig4 output from a separately provided write / read control circuit 15. The write / read control circuit 15 may include a booster circuit that boosts the logic power supply voltage VDD to the voltage of the control signal Sig4. Further, when the high voltage applied to the VH terminal is lower than the write voltage of the anti-fuse element, the voltage application circuit 11 may be configured to include a step-down circuit that steps down the VH voltage (e.g., 32V) to the write voltage (e.g., 24V).

[0020] When reading whether the anti-fuse element Ca is in the written state, as shown in FIG. 1B, the voltage of the VID terminal electrically connected to the wiring C can be detected from outside the semiconductor component to make a determination. Also, as shown in the same figure, the read circuit 16 may detect the written state. When the read circuit 16 is mounted on the same semiconductor component, it is preferable to connect a high-voltage-resistant transistor MND3 between the read circuit 16 and the wiring C so that the read circuit 16 and the wiring C can be electrically separated except during reading.

[0021] As shown in FIG. 1C, the control signal Sig3 of the transistor MND3 may output a control signal Sig5 from the write / read control circuit 15 in combination with the control signal Sig4 of the voltage application circuit 11. Note that if the high-voltage-resistant MOS transistors MPD1 and MND3 are turned on simultaneously, the voltage output from the voltage application circuit 11 and the voltage output from the read circuit 16 may interfere with each other and cause malfunction. Furthermore, if the read circuit 16 is composed of low-voltage-resistant transistors used in a logic circuit, the high voltage applied from the VH terminal may be applied to the low-voltage-resistant transistors, potentially damaging the read circuit 16. Therefore, the write / read control circuit 15 needs to control so that the high-voltage-resistant MOS transistors MPD1 and MND3 are not turned on simultaneously. There is a need to perform control so that they are not turned on simultaneously.

[0022] Next, the operation when writing information to the anti-fuse element Ca in FIG. 1B will be described. When writing information to the anti-fuse element Ca, the transistor MPD1 of the voltage application circuit 11 is turned on. As a result, the high voltage (e.g., 32V) applied to the VH terminal is applied to the wiring C to which the anti-fuse element Ca is connected. At this time, the transistor MND3 needs to be turned off so that the readout circuit 16 and the wiring C are in an electrically separated state (Hi impedance).

[0023] Next, Hi (e.g., 3.3V) is input to the control signal Sig1 corresponding to the anti-fuse element Ca to be written, and the transistor MND1 is turned on. Here, the control signal Sig1 and the detection signal Vgn1 output from the noise detection circuit 12 described later are input to the noise detection signal input circuit NAND1. Also, Hi is output as the detection signal Vgn1 during normal times other than when noise is detected. Therefore, the wiring E, which is the output of the noise detection signal input circuit NAND1, becomes the Lo level (e.g., ground potential), and a Hi-level signal is output from Vga to turn on the transistor MND1. As a result, the high voltage applied to the wiring C is applied to the gate insulating film of the anti-fuse element Ca. As a result, the gate insulating film of the anti-fuse element Ca is broken down, and the resistance value of the anti-fuse element Ca decreases significantly. Therefore, before writing, the anti-fuse element Ca was a capacitive element, whereas after writing, the anti-fuse element Ca becomes a resistive element.

[0024] Next, the information readout operation will be described when the readout circuit 16 is mounted on the same semiconductor component as the anti-fuse element Ca in FIG. 1B. Before performing information readout, the transistor MPD1 needs to be in the off state, and the VH terminal voltage needs to be in a state (Hi impedance) electrically separated from the wiring C connected to the anti-fuse element Ca. Also, the transistor MND3 is turned on to electrically connect the readout circuit 16 and the wiring C.

[0025] In this state, by setting the control signal Sig1 corresponding to the anti-fuse element Ca for which information reading is desired to a high-level signal, the transistor MND1 is turned on. As a result, a read current Iread is supplied from the read circuit 16 to the anti-fuse element Ca. Here, if the resistance of the anti-fuse element Ca is Ra, the read voltage Vread of Iread×Ra is input to a voltage comparator provided in the read circuit 16 via the wiring C. The read voltage Vread is compared with a comparison reference voltage Vref. When Vread is larger, "High" is output to the output terminal OUT, and when Vread is smaller, "Low" is output.

[0026] Since the anti-fuse element Ca generally consists of an insulating film, its resistance value becomes large in the unwritten state. When writing is performed, the insulating film is destroyed and becomes conductive, and the resistance value becomes small. In the case of the circuit given as an example, "High" is output in the unwritten state, and "Low" is output in the written state. However, an inverter INV may be added to the OUT output stage to provide inverse logic. Note that the configuration of the read circuit 16 may be other than the method of detecting the resistance value using the current source given in this embodiment.

[0027] On the other hand, in the product manufacturing process or the environment in which the user uses the product, a very large surge voltage may invade the semiconductor component from the VH terminal due to electrostatic discharge (ESD: Electro-Static Dischage) or a lightning surge that invades the building's AC100V power supply. In particular, during information reading, even though the transistor MPD1 shown in FIG. 1B is in the off state, if a surge voltage is applied to the VH terminal, it is conceivable that the surge voltage will invade the wiring C through the parasitic capacitance Cp formed on the semiconductor substrate.

[0028] At this time, since the transistor MND3 is in the on state, there is a possibility that a high-voltage surge voltage is applied to the read circuit 16 and it may be damaged. Also, at this time, the transistor MND1 is on, that is, the lower electrode of the anti-fuse element Ca is connected to GND. Therefore, even if a relatively small surge voltage of about 10 V, which is the breakdown voltage of the insulating film of the anti-fuse element Ca, is applied to the upper electrode, writing may be performed. As a result, the anti-fuse element Ca that was not intended to be written may be written, and the information recorded in the semiconductor component may change. Also, during electrical measurement in the product shipment inspection process, for example, during confirmation of the integrity of the anti-fuse element Ca or during confirmation of the operation of the read circuit, the same problems may occur.

[0029] (Conventional configuration) Fig. 5 shows a specific circuit diagram of the conventional configuration. The voltage application circuit 211 is generally composed of transistors. In Fig. 5, an example in which the voltage application circuit 211 is composed of MOS transistors is shown. Except during writing, by turning off the MOS transistor MP202, the anti-fuse element Ca is electrically disconnected from the power supply pad VH. Therefore, operations different from writing, such as read determination by a separately provided read circuit 212, can be performed. Here, the MOS transistor MP202 can normally maintain the off state in an environment where the power supply and ground voltages are stable. However, when a high-frequency voltage or a surge voltage enters the power supply pad VH due to electrostatic discharge or lightning surge received from outside the semiconductor component, the surge voltage may pass through the parasitic capacitance Cp201 formed in the MOS transistor MP202 or the like. Particularly when a surge voltage enters up to the wiring Z during the read operation, there is a possibility of damage to the read circuit 212 or incorrect writing to the anti-fuse element Ca.

[0030] (Effects of this configuration)

[0031] (Effects of this configuration) Therefore, in the present invention, as shown in FIG. 1A, a noise detection circuit 12 is connected near the VH terminal where the noise voltage intrudes. The noise detection circuit 12 is configured to output a detection signal Vgn1 that turns off the transistor MND1 when it detects noise. The noise detection circuit 12 is arranged at least in a position closer to the VH terminal, which is an external connection terminal, than the positions where the voltage application circuit 11 and the anti-fuse element Ca are arranged in the semiconductor substrate.

[0032] In this embodiment, the detection signal Vgn1 and the control signal Sig1 are input to the noise detection signal input circuit NAND1. The noise detection circuit 12 outputs Hi normally and Lo when noise is detected as the detection signal Vgn1. Thereby, normally, the inverted data of the control signal Sig1 is input to the memory module (memory unit 10), and the transistor MND1 is controlled according to the control signal Sig1.

[0033] On the other hand, when the noise detection circuit 12 detects the noise voltage intruded from the VH terminal, it outputs Lo as the detection signal Vgn1. When Lo is input to one terminal of the noise detection signal input circuit NAND1, Hi is output to the wiring E from the NAND1 circuit regardless of the voltage of the control signal Sig1. Therefore, Hi is input to the memory unit 10 and the transistor MND1 is always in the off state.

[0034] Thereby, even when noise or a surge voltage intrudes when Hi is input to the control signal Sig1 that turns on the transistor MND1 in the read operation of the anti-fuse element Ca or the shipping inspection process, etc., the transistor MND1 is turned off. That is, since the lower electrode of the anti-fuse element Ca is in a Hi impedance state, a high voltage is not applied across the anti-fuse element Ca. Therefore, the write operation to the anti-fuse element Ca is expected The execution of the write operation at an unexpected timing is suppressed. Therefore, it is possible to suppress the change of the information recorded in the semiconductor component at an unexpected timing. Here, although NAND1 is used as the combinational circuit, the present invention is not limited to this, and any combinational circuit that can realize the same function may be used.

[0035] While referring to the circuit diagram of FIG. 1B, a more detailed voltage waveform will be described with reference to FIG. 2A. The noise voltage applied to the VH terminal is shown as the VH waveform, and the voltage across both ends of the anti-fuse element Ca is shown as the Vca waveform. A voltage as a write voltage is supplied to the VH terminal. A high voltage (for example, 32V) is applied to the VH terminal as a steady state. However, since the transistor MPD1 of the voltage application circuit 11 is in the off state during information reading, the voltage value of the wiring C becomes 0V or a value equal to the read voltage value of the anti-fuse element Ca.

[0036] Here, assume that a noise voltage of several tens of MHz and 60V peak is applied to the VH terminal. In this case, the high-frequency component is transmitted to the wiring C through the parasitic capacitance Cp. Here, when no noise countermeasure is taken (in the case of the prior art), as shown by the dotted line in the Vca waveform, it may reach a voltage of 15V. If the dielectric breakdown voltage of the anti-fuse element Ca is, for example, 10V (shown by the broken line in Vca), writing will be performed on the anti-fuse element Ca.

[0037] On the other hand, when noise countermeasures are taken as in this embodiment, for the noise detection capacitor Cn1 (capacitive element) in the noise detection circuit 14, the high-frequency component of the noise voltage passes through, and the voltage rises like the noise detection signal Vgn2 shown in the Vgn2 waveform of FIG. 2A. Here, during the period when Vgn2 exceeds the threshold voltage Vth (indicated by the broken line in Vgn2) of the noise detection signal input circuit NAND1 operation (NAND1 operation time), Lo is input to one end of NAND1. As a result, the transistor MND1 is turned off, and the potential difference across the anti-fuse element Ca is suppressed. Therefore, as shown by the solid line in the Vca waveform of FIG. 2A, the voltage rise across the anti-fuse element Ca is suppressed. As a result, the voltage can be kept below the dielectric breakdown voltage of 10 V of the anti-fuse element Ca. Thus, it is possible to prevent miswriting of the anti-fuse element Ca due to the noise voltage invading from the VH terminal.

[0038] Note that a pull-down resistor Rn1 (first resistive element) is provided in the noise detection circuit 14 so that the noise detection signal input circuit NAND1 does not operate in a state where no noise invades, that is, in a steady state where the voltage is stable. Also, it is preferable to connect a protection diode, which is generally used as a protection element, between the VH terminal and GND so as not to be destroyed by the noise voltage.

[0039] As shown in FIG. 1C, a configuration that prevents information from being accidentally written to the anti-fuse element Ca by connecting a parallel resistor Rp (third resistive element) to the anti-fuse element Ca is more preferable. Specifically, when a write voltage (for example, 32 V) is applied to the wiring D, it is possible to prevent a high voltage from being applied across the anti-fuse element Ca and the write state from occurring even though the memory driving transistor MND1 is in a non-conductive state.

[0040] (Cross-sectional structure) FIG. 3 shows a specific example of the cross-sectional structure of the semiconductor substrate 110 including the anti-fuse element Ca, the resistive element Rp, and the transistor MND1 shown in FIG. 1C.

[0041] In the semiconductor substrate 110, a P-well region 101, and N-well regions 102a, 102b, and 102c are formed on a P-type silicon substrate 100. The P-well region 101 can be formed in the same process as the P-well of the NMOS transistor constituting the logic circuit. Also, the N-well regions 102a, 102b, and 102c can be formed in the same process as the N-well of the PMOS transistor constituting the logic circuit.

[0042] Note that the impurity concentration of the N-well region with respect to the P-type silicon substrate 100 is such that the breakdown voltage between the N-well regions 102a, 102b, and 102c and the P-type silicon substrate 100 is higher than the high voltage VID. Also, the impurity concentration of the P-well region 101 and the N-well regions 102a, 102b, and 102c is such that the breakdown voltage between the P-well region 101 and the N-well regions 102a, 102b is higher than the high voltage VID.

[0043] A field oxide film 103, high-concentration N-type diffusion regions 106a to 106e, and a high-concentration P-type diffusion region 107 are formed in the P-well region 101 and the N-well regions 102a, 102b, and 102c. The field oxide film 103 can be formed, for example, by the LOCOS (Local Oxidation of Silicon) method.

[0044] The configuration of the transistor MND1, which is a high-voltage-resistant NMOS transistor, will be described. The gate electrode 105a is disposed on the adjacent P-well region 101 and N-well region 102a via a gate insulating film 104. The region where the P-well region 101 and the gate electrode 105a overlap becomes the channel formation region.

[0045] The high-concentration N-type diffusion region 106a serves as the source of the transistor MND1, and the high-concentration P-type diffusion region 107 serves as the back gate electrode. The N-well region 102a has a portion that extends to below the gate electrode 105a as an electric field relaxation region for the drain. The high-concentration N-type diffusion region 106b formed within the N-well region 102a serves as the drain electrode of the transistor MND1.

[0046] Furthermore, the drain side of the gate electrode 105a has a structure that rides on the field oxide film 103 formed within the N-well region 102, namely, a so-called LOCOS offset structure. Thereby, even when the transistor MND1 is in the OFF state, that is, when the voltage of the gate electrode is GND and the voltage of the drain electrode has risen to the high voltage VID, the gate-drain breakdown voltage can be ensured.

[0047] Next, the structure of the anti-fuse element Ca will be described. The anti-fuse element Ca has an upper electrode, a lower electrode, and an insulating layer therebetween. For example, the electrode 105b provided via the gate insulating film 104 on the N-well region 102b functions as the upper electrode of the anti-fuse element Ca. Also, in the N-well region 102b, the portion that overlaps with the upper electrode in a plan view with respect to the surface on which elements such as the transistor MND1 of the semiconductor substrate 110 are arranged and is connected to the high-concentration N-type diffusion region 106c functions as the lower electrode. Note that the plan view with respect to the surface on which elements such as the transistor MND1, the anti-fuse element Ca, and the resistance element Rp are arranged is, for example, a plan view with respect to the surface of the channel formation region of the transistor MD1.

[0048] In the figure, a high-concentration N-type diffusion region 106c is formed only in a region of the N-well region 102b that does not overlap with the upper electrode in plan view, but the arrangement of the high-concentration N-type diffusion region 106c is not limited to this. For example, a high-concentration N-type diffusion region 106b may be formed in part of the overlapping portion with the upper electrode or over the entire overlapping portion. When a high-concentration N-type diffusion region 106c is also formed in a region overlapping with the upper electrode in plan view, the overlapping portion of the high-concentration N-type diffusion region 106c also functions as the lower electrode of the anti-fuse element Ca.

[0049] Furthermore, in the figure, the lower electrode of the anti-fuse element Ca is connected to the drain of the transistor MND1, but the upper electrode may be connected to the drain of the third transistor MND1 and the lower electrode may be connected to a high voltage (wiring A shown in FIG. 1A).

[0050] The gate insulating film 104 can be formed in the process of forming the gate insulating films of the transistors MP1 and MN1 constituting the logic circuit. For example, an oxide film can be used as the material of the gate insulating film 104. Also, the electrodes 105a and 105b can be, for example, polysilicon layers. The polysilicon layer, the high-concentration N-type diffusion regions 106a to 106c, and the high-concentration P-type diffusion region 107 can be formed in the same process as the process of forming each element of the transistors MP1 and MN1 constituting the low-voltage logic circuit.

[0051] Thus, the anti-fuse element Ca is a capacitive element having a MOS structure, and the transistor that controls writing to the anti-fuse element Ca is a MOS transistor. Therefore, since the anti-fuse element Ca and the transistor can be formed in the same process, semiconductor components can be formed at low cost with a small number of processes.

[0052] On the high-concentration P-type diffusion region 107, N-type diffusion regions 106a to 106e, and field oxide film 103, an insulating film provided with a plurality of contact portions 108 is provided, and conductive layers 109a to 109e are provided on the insulating film. The conductive layers 109a to 109e can be formed of a metal such as aluminum, for example. Note that the manufacturing method, material, and structure of the conductive layers 109a to 109e and each electrode and wiring are not limited as long as they are electrically connected.

[0053] In the figure, as the anti-fuse element Ca, a capacitive element in which the lower electrode and the upper electrode are formed of an N-well region and polysilicon is shown as an example. However, the anti-fuse element Ca is not limited to this structure, and for example, a capacitive element using a PMOS transistor may be used. As long as one of the lower electrode and the upper electrode of the anti-fuse element Ca functions as one terminal and the other functions as the other terminal.

[0054] The resistance element Rp has an N-well region 102c, which is a semiconductor region in the semiconductor substrate 110, and is connected to the conductive layers of 109d and 109e via high-concentration N-type diffusion regions 106d and 106e, respectively. However, the resistance element Rp is not limited to such a structure of a common diffusion resistance. For example, a resistor made of a conductive layer or a resistor made of polysilicon may be used as the resistance element Rp.

[0055] The insulating film is an insulator layer formed on the semiconductor substrate 110 so as to cover the transistor MND1, the resistance element Rp, etc., and is made of, for example, silicon oxide. Also, the insulator layer is not limited to this, and may be made of silicon nitride, silicon carbide, or a laminate or mixture layer of these.

[0056] The conductive layer 109a is connected to the source and the back gate of the transistor MND1 via the contact portion 108, and a ground potential is applied. The conductive layer 109b is connected to the drain electrode of the transistor MND1 and the lower electrode of the anti-fuse element Ca via the contact portion 108. The conductive layer 109c is connected to the upper electrode of the anti-fuse element Ca via the contact portion 108 and is connected to the wiring A shown in FIG. 1A at a portion not shown. A high voltage (for example, 32V) is applied to the conductive layer 109c via the wiring A during writing. The conductive layer 109d is connected to the conductive layer 109c (not shown), and the conductive layer 109e is connected to the conductive layer 109b (not shown).

[0057] [Example 2] Subsequently, Example 2 will be described. The same reference numerals are used for the same configurations as in Example 1, and the description will be simplified. The noise detection circuit 17 of this embodiment suppresses the increase in the voltage across the anti-fuse element Ca efficiently by driving the noise detection signal input circuit more stably.

[0058] In the noise detection circuit 17 shown in FIG. 1C, the signal of the noise detection capacitor Cn2 is input to the transistor MN2. The voltage Vgn4 obtained by dividing the logic power supply voltage VDD by the pull-up resistor Rn3 (the fourth resistor element) and the transistor MN2 (the third transistor) is output as the voltage Vgn5 after passing through the buffer circuit BUF1. In this embodiment, the noise detection signal input circuit NAND1 is configured to be driven in response to the output of this voltage Vgn5.

[0059] A detailed voltage waveform will be described with reference to FIG. 2B. The noise voltage applied to the VH terminal is shown as the VH waveform. A voltage as a writing voltage is supplied to the VH terminal. A high voltage (for example, 32V) is applied to the VH terminal as a steady state. However, since the transistor MPD1 of the voltage application circuit 11 is in the off state during information reading, the voltage value of the wiring D is 0V or equal to the reading voltage value of the anti-fuse element Ca.

[0060] Here, assume that a noise voltage of several tens of MHz and 60 V peak is applied to the VH terminal. In this case, the high-frequency component is transmitted to the wiring D through the parasitic capacitance Cp. Here, when no noise countermeasure is taken (in the case of the prior art), it may reach a voltage of 15 V as shown by the dotted line in the Vca waveform. If the breakdown voltage of the insulating film of the anti-fuse element Ca is, for example, 10 V (shown by the broken line in Vca), writing will be performed on the anti-fuse element Ca.

[0061] On the other hand, when a noise countermeasure as in this embodiment is taken, the high-frequency component of the noise voltage passes through the noise detection capacitance Cn2 in the noise detection circuit 17, and the voltage rises as shown by the noise detection signal Vgn3 waveform in FIG. 2B. Here, during the period when Vgn3 exceeds the on threshold voltage Vth of the transistor MN2 (MN2 on time), MN2 turns on.

[0062] When MN2 turns on, the voltage Vgn4 at the input terminal of BUF1 becomes 0 V, that is, the voltage Vgn4 at the input terminal of the noise detection signal input circuit NAND1 becomes 0 V. Therefore, the output of the noise detection signal input circuit NAND1 becomes hi, the transistor MND1 turns off, and the voltage rise across the anti-fuse element Ca is suppressed. Since the noise voltage immediately falls, Vgn3 also falls, and subsequently the transistor MN2 turns off. However, until the input voltage Vgn4 of BUF1 transitions from the 0 V state to the VDD voltage, it takes a time proportional to the time constant τ = Rn3 × Cinv determined by the pull-up resistor Rn3 and the capacitance Cinv (not shown) added to the gate of BUF1. The logic inversion of BUF1 needs to exceed the threshold voltage (about 1 / 2 of the VDD voltage). Therefore, while Vng4 does not exceed this value, Lo is continuously input to the noise detection signal input circuit NAND1, so the off state of the transistor MND1 is maintained, and the voltage rise across the anti-fuse element Ca can be continuously suppressed.

[0063] For example, when the pull-up resistor Rn3 = 100 kΩ and the additional capacitance Cinv = 1 pF, the time constant τ = 1 μsec. Therefore, the time until BUF1 is inverted is about 0.7 μsec, and during that time, Lo can be continuously input to the noise detection signal input circuit NAND1. During that time, regarding the voltage Vca across the anti-fuse element Ca, as shown by the solid line, the voltage rise can be suppressed, so the breakdown voltage of the insulating film of the anti-fuse element Ca can be kept below 10 V. Therefore, it is possible to prevent miswriting of the anti-fuse element Ca due to the noise voltage invading from the VH terminal.

[0064] Furthermore, there is a possibility that the noise voltage passes through the voltage application circuit 11 and reaches the wiring D before the noise detection circuit 17 detects the noise and the noise detection signal input circuit NAND1 becomes Lo and the transistor MND1 turns off. Therefore, as shown in FIG. 1C, by inserting a noise delay resistor Rd (second resistance element) at the output terminal of the voltage application circuit 11, the noise to the wiring D is delayed as shown in the Vca waveform of FIG. 2B, and before the voltage rise of Vca becomes high a configuration in which the transistor MND1 is turned off is preferable. Since the noise delay resistor Rd may affect the voltage drop during writing of the anti-fuse element Ca or the writing current limitation, a value of about several tens of Ω with less of these effects is preferable. Since the noise delay resistor Rd has a relatively small resistance value, it can be formed by a polysilicon layer or high-concentration N-type diffusion.

[0065] FIG. 4A shows a connection diagram of the recording element Rh, the anti-fuse element Ca, and the selection circuit 86 when the circuit of the present embodiment is mounted on an inkjet recording element substrate. It operates to exclusively select the recording element Rh or the anti-fuse element Ca according to the logical state of the function selection signal 88 which is an output signal from the selection circuit 86. During specific bit selection, the selection is carried out according to the bit selection signal 87 which is an output signal from the selection circuit 86. A common signal line is used for the transmission of the bit selection signal 87 by the recording element Rh and the anti-fuse element Ca.

[0066] One terminal of the input of NAND1 of circuit 85 composed of memory unit 20 (memory module) and input NAND1 circuit is connected to the output of noise detection circuit 12, and voltage application circuit 11 is installed between memory unit 20 and VH terminal.

[0067] Fig. 4B shows an example in which the circuit of this embodiment is arranged on an inkjet recording element substrate 81. The recording element substrate 81 has an ink supply port 82 for supplying a liquid such as ink, an external connection terminal 83, and a recording element 84. The recording element substrate 81 can be suitably used for an inkjet recording device (liquid ejection device). By using such a recording element substrate 81, the anti-fuse element can be used as an OTP memory for recording product information such as chip ID and setting parameters after the product is completed. The recording element 84 has a functional part such as a heating element or a piezoelectric element, and performs recording by applying energy to a liquid such as ink to eject it.

[0068] In the recording element substrate 81, the memory unit 20 and the noise detection signal input circuit NAND1 are arranged in parallel in the direction in which the recording elements 84 are arranged. The noise detection circuit 12 and the voltage application circuit 11 are arranged in the region between the array group of the external connection terminals 83 and the array group of the recording elements 84. The effects as described above can be obtained in the forms shown in Figs. 4A and 4B. However, the arrangement on the substrate is not limited to this.

[0069] The noise detection circuit 17 is preferably arranged in the vicinity of the VH terminal which is an external connection terminal so that it can detect the noise voltage with high sensitivity and good responsiveness, and more preferably arranged adjacent to the VH terminal. The selection circuit 86 is arranged in the region between the array group of the external connection terminals 83 and the array group of the recording elements Rh. By arranging according to the figure, the symmetry of the outer shape of the inkjet recording element substrate can be maintained as much as possible, and the wiring connection region in the substrate can be made smaller.

[0070] [Example 3] In this example, an example in the case where a plurality of voltage application circuits shown in the above embodiment are arranged is shown. The same reference numerals are used for the same configurations as those in the above examples, and the description is simplified.

[0071] Figure 1D shows the circuit configuration of the semiconductor component according to this embodiment. The semiconductor component includes a plurality of memory units 20 each including a capacitive element which is an anti-fuse element Ca, a parallel resistor Rp, and a transistor MND1. Wiring E and wiring F are electrically separated from each other. For each wiring, there are respective connection switches MND31 and MND32 between each voltage application circuit 11, 111, each noise detection signal input circuit NAND1, NAND2, and a readout circuit 160.

[0072] The noise detection signal Vgn5 which is the output signal of the noise detection circuit 17 outputs Lo, and when Lo is input to the noise detection signal input circuits NAND1 and NAND2 respectively, the outputs of the NAND1 and NAND2 circuits become Hi regardless of the voltages of the control signals Sig10 and Sig20. Therefore, Hi is input to the memory unit 20 and the transistor MND1 is always in the off state. In this embodiment, since two voltage application circuits are provided, stable writing to two anti-fuse elements Ca can be performed, and the writing time can be shortened. Note that, for the sake of explanation, an example in which the semiconductor component has two voltage application circuits is shown in this embodiment. However, if it is desired to further shorten the writing time of the anti-fuse element Ca within a single time period, more voltage application circuits may be provided. Similarly, if it is desired to further shorten the readout time of the anti-fuse element Ca within a single time period, a plurality of readout circuits may be provided. With the configuration of this embodiment, it is possible to prevent miswriting of the anti-fuse element Ca from the noise voltage invading from the VH terminal.

[0073] In this embodiment, since two voltage application circuits are provided, stable writing to two anti-fuse elements Ca can be performed, and the writing time can be shortened. Note that, for the sake of explanation, an example in which the semiconductor component has two voltage application circuits is shown in this embodiment. However, if it is desired to further shorten the writing time of the anti-fuse element Ca within a single time period, more voltage application circuits may be provided. Similarly, if it is desired to further shorten the readout time of the anti-fuse element Ca within a single time period, a plurality of readout circuits may be provided. With the configuration of this embodiment, it is possible to prevent miswriting of the anti-fuse element Ca from the noise voltage invading from the VH terminal.

[0074] [Embodiment 4] Subsequently, Embodiment 4 will be described. The same reference numerals are used for the configurations similar to those in the above embodiments, and the description will be simplified.

[0075] In this embodiment, as shown in FIG. 1E, a high-voltage transistor MND4 controlled only by a control signal Sig1 and a high-voltage transistor MND5 controlled only by a detection signal Vgn1 are connected in series on one side of a terminal of an anti-fuse element Ca. The transistor MND4 corresponds to the second transistor, and the transistor MND5 corresponds to the first transistor. The transistors MND4 and MND5 are respectively connected to transistors MP2 / MN2 and MP3 / MN3 with lower breakdown voltages to form an inverter of a logic circuit. The control signal Sig1 is input to the gates of the transistor MP2 and the transistor MN2, and the detection signal Vgn1 is input to the gates of the transistor MP3 and the transistor MN3.

[0076] Normally, the detection signal Vgn1 outputs Lo (Hi in Embodiment 1), and the transistor MND5 is turned on. On the other hand, at the time of noise detection, the detection signal Vgn1 outputs Hi (Lo in Embodiment 1), and the transistor MND5 is turned off. Also, the transistor MND4 turns on and off according to the control signal Sig1. That is, normally, the anti-fuse element Ca is read and written according to the control signal Sig1, and at the time of noise detection, since the transistor MND5 is turned off, the anti-fuse element Ca is not read and written regardless of the value of the control signal Sig1.

[0077] [Modification Example] Also, in the form in which a plurality of anti-fuse elements Ca are arranged as shown in FIGS. 1C and 1D, the GNDs connected to the source sides of the respective memory driving transistors MND1 can be bundled into one. Then, the bundled line can be commonly connected to the drain side of one high-voltage transistor MND controlled only by the noise detection signal Vgn1. In the form using the NAND circuits shown in Embodiments 1 to 3, it is necessary to provide a NAND circuit for each anti-fuse element Ca, but in this form, the reading and writing of all the anti-fuse elements Ca can be controlled by one high-voltage transistor MND.

[0078] In Examples 1 to 3 described above, although the noise detection circuit 12 was connected and provided near the VH terminal on the assumption that noise voltage would invade from the VH terminal, the present invention is not limited to this, and a logic power supply terminal or an external connection terminal dedicated for noise detection may be provided. Further, the number of noise detection terminals and noise detection circuits is not limited to one, and a plurality of them may be provided.

[0079] As described above, according to each embodiment of the present invention, a noise detection circuit is arranged near an external connection terminal that becomes a noise invasion end, and when the noise detection circuit detects noise, a control signal for turning off the anti-fuse driving transistor is output, thereby preventing miswriting. Therefore, it is possible to suppress miswriting caused by external noise or the like invading through the anti-fuse writing circuit.

[0080] [Configuration 1] A semiconductor substrate, A transistor arranged on the semiconductor substrate and connected to a first terminal at a first potential, An anti-fuse element connected between a second terminal at a second potential different from the first potential and the transistor, A noise detection circuit electrically connected to the second terminal, detecting noise, and outputting a detection signal and having The transistor is turned off based on the detection signal output by the noise detection circuit A semiconductor component characterized by this. [Configuration 2] Further having a combination circuit that inputs the detection signal output by the noise detection circuit and the control signal of the anti-fuse element, and outputs a control signal for turning off the transistor when the noise detection circuit detects noise The semiconductor component according to Configuration 1, characterized by this. [Configuration 3] The combination circuit turns off the transistor when the detection signal output by the noise detection circuit exceeds a threshold voltage The semiconductor component according to Configuration 2, characterized by this. [Configuration 4] The transistor includes a first transistor and a second transistor connected in series, the first transistor is a transistor that is turned off when the noise detection circuit detects noise, and the second transistor is a transistor controlled by a control signal of the anti-fuse element. The semiconductor component according to Configuration 1, characterized in that. [Configuration 5] The noise detection circuit includes a capacitor element and a first resistor element connected in series between the second terminal and the first terminal, and outputs a voltage between the capacitor element and the first resistor element as the detection signal. The semiconductor component according to any one of Configurations 1 to 4, characterized in that. [Configuration 6] The semiconductor component further includes a voltage application circuit that supplies a voltage from the second terminal to the anti-fuse element. The semiconductor component according to any one of Configurations 1 to 5, characterized in that. [Configuration 7] The voltage application circuit supplies a write voltage of the anti-fuse element. The semiconductor component according to Configuration 6, characterized in that. [Configuration 8] A second resistor element for delaying noise is connected in series to the output end of the voltage application circuit. The semiconductor component according to Configuration 6 or 7, characterized in that. [Configuration 9] The voltage application circuit includes a P-type high breakdown voltage MOS transistor. The semiconductor component according to any one of Configurations 6 to 8, characterized in that. [Configuration 10] The noise detection circuit is arranged on the semiconductor substrate at a position closer to the second terminal than the positions where the voltage application circuit and the anti-fuse element are arranged. The semiconductor component according to any one of Configurations 6 to 9, characterized in that. [Configuration 11] having a plurality of said voltage application circuits The semiconductor component according to any one of Configurations 6 to 10, characterized in that. [Configuration 12] further having a third resistance element connected in parallel with the anti-fuse element between the second terminal and the transistor The semiconductor component according to any one of Configurations 1 to 11, characterized in that. [Configuration 13] The third resistance element is a common diffusion resistance The semiconductor component according to Configuration 12, characterized in that. [Configuration 14] The noise detection circuit further has a fourth resistance element and a third transistor connected to the first terminal, The third transistor is turned on based on the voltage between the capacitor element and the first resistance element The semiconductor component according to Configuration 5, characterized in that. [Configuration 15] further having a reading circuit for reading the writing state of the anti-fuse element The semiconductor component according to any one of Configurations 1 to 14, characterized in that. [Configuration 16] a semiconductor substrate, a semiconductor component disposed on the semiconductor substrate, the semiconductor component having a transistor disposed on the semiconductor substrate and connected to a first terminal at a first potential, an anti-fuse element connected between a second terminal at a second potential different from the first potential and the transistor, and a noise detection circuit electrically connected to the second terminal and detecting noise and outputting a detection signal, wherein the transistor is turned off based on the detection signal output by the noise detection circuit, a recording element disposed on the semiconductor substrate and applying energy to a liquid to eject the liquid, An inkjet recording element substrate having, wherein product information of the inkjet recording element substrate is recorded in the anti-fuse element An inkjet recording element substrate characterized by the following.

Explanation of symbols

[0081] 12: Noise detection circuit, 83: External connection terminal, Ca: Anti-fuse element, MND1: Transistor

Claims

1. A semiconductor substrate, a transistor disposed on the semiconductor substrate and connected to a first terminal at a first potential, an anti-fuse element connected between a second terminal at a second potential different from the first potential and the transistor, a noise detection circuit electrically connected to the second terminal and configured to detect noise and output a detection signal wherein the transistor is turned off based on the detection signal output by the noise detection circuit characterizing the semiconductor component.

2. further comprising a combination circuit configured to receive the detection signal output by the noise detection circuit and a control signal for the anti-fuse element, and output a control signal for turning off the transistor when the noise detection circuit detects noise characterizing the semiconductor component according to claim 1.

3. the combination circuit turns off the transistor when the detection signal output by the noise detection circuit exceeds a threshold voltage characterizing the semiconductor component according to claim 2.

4. the transistor includes a first transistor and a second transistor connected in series, the first transistor is turned off when the noise detection circuit detects noise, the second transistor is controlled by the control signal for the anti-fuse element characterizing the semiconductor component according to claim 1.

5. the noise detection circuit includes a capacitive element and a first resistive element connected in series between the second terminal and the first terminal, and outputs the voltage between the capacitive element and the first resistive element as the detection signal characterizing the semiconductor component according to claim 1.

6. further comprising a voltage application circuit configured to supply a voltage from the second terminal to the anti-fuse element characterizing the semiconductor component according to any one of claims 1 to 5.

7. the voltage application circuit supplies a write voltage for the anti-fuse element characterizing the semiconductor component according to claim 6.

8. a second resistive element for delaying noise is connected in series to the output terminal of the voltage application circuit characterizing the semiconductor component according to claim 6.

9. the voltage application circuit includes a P-type high-voltage MOS transistor characterizing the semiconductor component according to claim 6.

10. The noise detection circuit is disposed on the semiconductor substrate at a position closer to the second terminal than the positions where the voltage application circuit and the anti-fuse element are disposed. This semiconductor component according to claim 6, characterized in that.

11. Having a plurality of the voltage application circuits This semiconductor component according to claim 6, characterized in that.

12. Further comprising a third resistor element connected in parallel with the anti-fuse element between the second terminal and the transistor This semiconductor component according to claim 1, characterized in that.

13. The third resistor element is a common diffusion resistor This semiconductor component according to claim 12, characterized in that.

14. The noise detection circuit further includes a fourth resistor element and a third transistor connected to the first terminal, The third transistor is turned on based on the voltage between the capacitor element and the first resistor element This semiconductor component according to claim 5, characterized in that.

15. Further comprising a readout circuit for reading the write state of the anti-fuse element This semiconductor component according to claim 1, characterized in that.

16. A semiconductor substrate, A semiconductor component disposed on the semiconductor substrate, comprising a transistor disposed on the semiconductor substrate and connected to a first terminal having a first potential, and an anti-fuse element connected between a second terminal having a second potential different from the first potential and the transistor, and a noise detection circuit electrically connected to the second terminal for detecting noise and outputting a detection signal, wherein the transistor is turned off based on the detection signal output by the noise detection circuit, the semiconductor component, A recording element disposed on the semiconductor substrate for applying energy to a liquid to eject it, An inkjet recording element substrate having, wherein product information of the inkjet recording element substrate is recorded in the anti-fuse element This inkjet recording element substrate, characterized in that. ​

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