Semiconductor package and method of manufacturing the same

Abstract

To provide a semiconductor package improved in reliability.SOLUTION: A semiconductor package includes an interconnection chip INC between a first chip stack CS1 and a second chip stack CS2, the interconnection chip including interconnection vias INV electrically connecting first through-vias TSV1 and second through-vias TSV2 to each other. The interconnection chip has a lower surface 210LS in contact with the first chip stack, an upper surface 210US in contact with the second chip stack, and a side surface between the lower surface and the upper surface. The side surface of the interconnection chip includes a first portion extending from the lower surface of the interconnection chip at a first inclination, and a second portion extending from the first portion to the upper surface of the interconnection chip at a second inclination lower than the first inclination.SELECTED DRAWING: Figure 1b

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] Semiconductor devices mounted on electronic devices are required to be miniaturized, with high performance and large capacity. To achieve this, the development of semiconductor packages that interconnect semiconductor chips stacked vertically using through electrodes (e.g., Through Silicon Via) has been carried out.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the problems to be solved by the present invention is to provide a semiconductor package with improved reliability.

Means for Solving the Problems

[0004] As a solution to the above problems, an exemplary embodiment of the present invention includes a base chip including lower connection terminals and upper connection terminals on opposite sides of each other, and a through electrode that electrically connects the lower connection terminals and the upper connection terminals; a first chip stack including a plurality of first semiconductor chips stacked in a first direction on the base chip, the first semiconductor chips including first lower pads and first upper pads on opposite sides of each other, and first through vias that electrically connect the first lower pads and the first upper pads; a second chip stack including a plurality of second semiconductor chips stacked in the first direction on the first chip stack, the second semiconductor chips including second lower pads and second upper pads on opposite sides of each other, and second through vias that electrically connect the second lower pads and the second upper pads; an interconnect chip disposed between the first chip stack and the second chip stack, the interconnect chip including interconnect vias that electrically connect the first through vias and the second through vias; a mold layer covering at least a part of each of the first chip stack, the second chip stack, and the interconnect chip on the base chip; a plurality of connection bumps disposed under the base chip and electrically connected to the lower connection terminals, wherein each of the first lower pads of the plurality of first semiconductor chips contacts the upper connection terminal of the base chip adjacent in the first direction and the first upper pads of the plurality of first semiconductor chips adjacent in the first direction, each of the second upper pads of the plurality of second semiconductor chips contacts the second lower pads of the plurality of second semiconductor chips adjacent in the first direction, the interconnect chip has a lower surface in contact with the first chip stack, an upper surface in contact with the second chip stack, and a side surface between the lower surface and the upper surface, and the side surface of the interconnect chip includes a first portion extending at a first inclination from the lower surface of the interconnect chip and a second portion extending at a second inclination smaller than the first inclination from the first portion to the upper surface of the interconnect chip, thereby providing a semiconductor package.

[0005] Exemplary embodiments of the present invention include a base chip including a through electrode, a plurality of first semiconductor chips stacked in a first direction on the base chip and including first through vias that are electrically connected to the through electrode in the first direction, a second chip stack stacked in the first direction on the first chip stack and including a plurality of second semiconductor chips including second through vias that are electrically connected to the first through vias in the first direction, an interconnect chip disposed between the first chip stack and the second chip stack and including interconnect vias that electrically connect the first through vias and the second through vias, and a mold layer covering side surfaces of the first chip stack, side surfaces of the second chip stack, and side surfaces of the interconnect chip. The interconnect chip provides a semiconductor package including a first region overlapping the second chip stack in the first direction and a second region extending from the first region and overlapping the mold layer and the first chip stack in the first direction.

[0006] Exemplary embodiments of the present invention include a base chip including a through electrode, a plurality of first semiconductor chips stacked in a first direction on the base chip and including first through vias that are electrically connected to the through electrode and to each other in the first direction, a plurality of second semiconductor chips stacked in the first direction on the plurality of first semiconductor chips and including second through vias that are electrically connected to each other in the first direction, and an interconnect chip disposed between the uppermost first semiconductor chip among the plurality of first semiconductor chips and the lowermost second semiconductor chip among the plurality of second semiconductor chips and including interconnect vias that electrically connect the first through vias and the second through vias. The thickness of the interconnect chip in the first direction is smaller than the thickness of each of the plurality of first semiconductor chips and the thickness of each of the plurality of second semiconductor chips. The interconnect chip has a lower surface in contact with the uppermost first semiconductor chip and an upper surface in contact with the lowermost second semiconductor chip. The lower surface of the interconnect chip is a wave surface having height irregularities, and the upper surface of the interconnect chip is a flat surface, providing a semiconductor package.

[0007] An exemplary embodiment of the present invention provides a method of manufacturing a semiconductor package, including forming a first chip stack including a plurality of first semiconductor chips on a semiconductor wafer, attaching interconnect chips to the first chip stack respectively, applying a planarization process to the interconnect chips, and forming a second chip stack including a plurality of second semiconductor chips on the planarized interconnect chips, wherein each width of the second chip stack is smaller than each width of the corresponding interconnect chips.

Advantages of the Invention

[0008] According to an embodiment of the present invention, by inserting planarized interconnect chips between a plurality of semiconductor chips stacked in multiple stages, a semiconductor package with improved quality and reliability of the bonding surface can be provided.

[0009] The various and significant advantages and effects of the present invention are not limited to the above-described content and can be more easily understood during the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0010]

Figure 1a

Figure 1b

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Figure 2d

Figure 3a

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Figure 3c

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Figure 7a

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Figure 8a

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Figure 9a

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Figure 10a

Figure 10b

Figure 11a

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Figure 12a

Figure 12b

Mode for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the accompanying drawings. Unless otherwise specified, terms such as "upper part", "upper surface", "lower part", "lower surface", "side surface", etc. in this specification are based on the drawings and can actually be different depending on the direction in which the components are arranged.

[0012] Also, ordinal numbers such as "first", "second", "third", etc. can be used as labels for specific elements, steps, directions, etc. to distinguish various elements, steps, directions, etc. from each other. Terms not described using "first", "second", etc. in the specification can still be referred to as "first" or "second" in the claims. Also, a term referred to by a specific ordinal number (e.g., "the first" in a specific claim) can be described as another ordinal number (e.g., "the second" in the specification or another claim) elsewhere.

[0013] FIG. 1a is a plan view of a semiconductor package 10 according to an exemplary embodiment of the present invention, and FIG. 1b is a cross-sectional view taken along line I-I' of FIG. 1a.

[0014] Referring to FIGS. 1a and 1b, a semiconductor package 10 of an exemplary embodiment can include a base chip BC, a plurality of chip stacks CS1, CS2, and at least one interconnect chip INC. Depending on the embodiment, the semiconductor package 10 can further include an uppermost semiconductor chip TC, a mold layer ML, and / or a plurality of connection bumps BP.

[0015] A plurality of chip stacks CS1, CS2 may be sequentially arranged on the base chip BC. For example, the plurality of chip stacks CS1, CS2 may include a first chip stack CS1 and a second chip stack CS2 that are stacked in the vertical direction (Z direction). Each of the plurality of chip stacks CS1, CS2 may include a plurality of semiconductor chips C1, C2 stacked in the vertical direction (Z direction). The first chip stack CS1 may include a plurality of first semiconductor chips C1 stacked in the first direction (Z direction) on the base chip BC. The second chip stack CS2 may include a plurality of second semiconductor chips C2 stacked in the first direction (Z direction) on the interconnect chip INC. According to an embodiment, the plurality of first semiconductor chips C1 and the plurality of second semiconductor chips C2 may be provided in a number less than or more than that shown in the drawings. For example, the first chip stack CS1 may include 3 or fewer or 5 or more (e.g., 8, 12, etc.) first semiconductor chips C1, and the second chip stack CS2 may include 2 or fewer or 4 or more second semiconductor chips C2. Note that in the drawings, the number of the plurality of first semiconductor chips C1 (4) is shown to be the same as the number of the plurality of second semiconductor chips C2 and the uppermost semiconductor chip TC (4), but it is not limited thereto (see the embodiment of FIG. 5).

[0016] The plurality of first semiconductor chips C1 may include a first lower pad LP1 and a first upper pad UP1 on opposite sides of each other, and a first through via TSV1 that electrically connects the first lower pad LP1 and the first upper pad UP1. The first through via TSV1 may be electrically connected to the through electrode TV in the first direction (Z direction).

[0017] The plurality of second semiconductor chips C2 may include a second lower pad LP2 and a second upper pad UP2 on opposite sides of each other, and a second through via TSV2 that electrically connects the second lower pad LP2 and the second upper pad UP2. The second through via TSV2 may be electrically connected to the first through via TSV1 in the first direction (Z direction).

[0018] The uppermost semiconductor chip TC can include connection pads CP that are electrically connected to the second through vias TSV2 of the uppermost second semiconductor chip C2. The connection pads CP can be understood as components having the same and similar features as the lower pads LP described below. Depending on the embodiment, the thickness of the uppermost semiconductor chip TC may be greater than the thickness t1 of the first semiconductor chip C1 and the thickness t2 of the second semiconductor chip C2, but is not limited thereto.

[0019] Since the plurality of first semiconductor chips C1, the plurality of second semiconductor chips C2, and the uppermost semiconductor chip TC can include substantially the same or similar components, hereinafter, the same or similar components will be described with the same or similar terms and / or reference numerals. The plurality of first semiconductor chips C1, the plurality of second semiconductor chips C2, and the uppermost semiconductor chip TC can be referred to as "semiconductor chips C1, C2, TC".

[0020] The semiconductor chips C1, C2, TC can include a substrate 110, a circuit layer 120, a lower insulating layer LI, lower pads LP, an upper insulating layer UI, upper pads UP, and / or through vias TSV. The uppermost semiconductor chip TC can include only the substrate 110, the circuit layer 120, the third lower insulating layer LI, and the connection pads CP. The substrate 110, the circuit layer 120, etc. will be described in more detail with reference to FIG. 2a. In this specification, the lower insulating layer LI, the lower pads LP, the upper insulating layer UI, the upper pads UP, and / or the through vias TSV can be understood as referring to the corresponding first and second components, respectively. For example, the lower insulating layer LI can be understood to refer to all of the first lower insulating layer LI1 and the second lower insulating layer LI2, and the through via TSV can be understood to refer to all of the first through via TSV1 and the second through via TSV2.

[0021] At least one interconnect chip INC may be disposed between a plurality of chip stacks CS1, CS2. For example, the interconnect chip INC may be disposed between a first chip stack CS1 and a second chip stack CS2. The interconnect chip INC can include interconnect vias INV that electrically connect the first chip stack CS1 and the second chip stack CS2. The interconnect vias INV can electrically connect a first through via TSV1 and a second through via TSV2.

[0022] In an exemplary embodiment, the plurality of first semiconductor chips C1, the plurality of second semiconductor chips C2, and the interconnect chip INC can be joined and bonded to each other by intermetallic bonding and dielectric bonding.

[0023] For example, each of the plurality of first semiconductor chips C1 can include a first lower insulating layer LI1 surrounding a first lower pad LP1 and a first upper insulating layer UI1 surrounding a first upper pad UP1. Each of the plurality of second semiconductor chips C2 can include a second lower insulating layer LI2 surrounding a second lower pad LP2 and a second upper insulating layer UI2 surrounding a second upper pad UP2. The interconnect chip INC can include a chip body 210 that surrounds the interconnect vias INV and defines a lower surface 210LS and an upper surface 210US.

[0024] The first lower insulating layer LI1 of each of the plurality of first semiconductor chips C1 can contact the dielectric layer DL of the base chip BC adjacent in the first direction (Z direction) and the first upper insulating layer UI1 of each of the plurality of first semiconductor chips C1 adjacent in the first direction (Z direction). The second upper insulating layer U12 of each of the plurality of second semiconductor chips C2 can contact the second lower insulating layer LI2 of each of the plurality of second semiconductor chips C2 adjacent in the first direction (Z direction).

[0025] Each first lower pad LP1 of the plurality of first semiconductor chips C1 can contact the upper connection terminal UT of the base chip BC adjacent in the first direction (Z direction) and the first upper pad UP1 of each of the plurality of first semiconductor chips C1 adjacent in the first direction (Z direction). Each second upper pad UP2 of the plurality of second semiconductor chips C2 can contact each second lower pad LP2 of the plurality of second semiconductor chips C2 adjacent in the first direction (Z direction).

[0026] The first lower insulating layer LI1, the first upper insulating layer UI1, the second lower insulating layer LI2, and the second upper insulating layer UI2 may include at least one of silicon oxide (SiO) and silicon carbonitride (SiCN). The chip body 210 of the interconnect chip INC can include a material to which the first upper insulating layer UI1 and the second lower insulating layer LI2 can be joined and bonded. For example, the chip body 210 of the interconnect chip INC can include a semiconductor material such as silicon (Si), germanium (Ge), etc., but is not limited thereto.

[0027] The interconnect chip INC can improve the bonding quality and reliability of the further stacked semiconductor chips by removing the surface topology accumulated by the plurality of first semiconductor chips C1 between the plurality of first semiconductor chips C1 and the plurality of second semiconductor chips C2. The interconnect chip INC can have a lower surface 210LS in contact with the uppermost first semiconductor chip C1a among the plurality of first semiconductor chips C1 and an upper surface 210US in contact with the lowermost second semiconductor chip C2a among the plurality of second semiconductor chips C2. The lower surface 210LS of the interconnect chip INC is a wave surface in contact with the upper surface of the uppermost first semiconductor chip C1a on which the surface topologies of the plurality of first semiconductor chips C1 are accumulated, while the upper surface 210US of the interconnect chip INC can be a flat surface to which a planarization process is applied. This will be described in more detail with reference to FIGS. 8a to 12b.

[0028] In an exemplary embodiment, the upper surface 210US of the interconnect chip INC may have its edges polished, which may not provide a flat surface necessary for dielectric bonding in some areas. Thus, the plurality of second semiconductor chips C2 can have a horizontal width smaller than the horizontal width of the interconnect chip INC. For example, the first width w1 in the second direction (X direction) of the first chip stack CS1 may be larger than the second width w2 in the second direction (X direction) of the second chip stack CS2. The width W of the interconnect chip INC in the second direction (X direction) may be the same as or smaller than the first width w1 and larger than the second width w2. The third width w3 of the base chip BC in the second direction (X direction) may be larger than the first width w1, but is not limited thereto.

[0029] In an exemplary embodiment, the thickness of the interconnect chip INC may be smaller than the respective thicknesses of the plurality of first semiconductor chips C1 and the plurality of second semiconductor chips C2. For example, the thickness T from the lower surface 210LS to the upper surface 210US of the interconnect chip may be smaller than the respective thicknesses t1 of the plurality of first semiconductor chips C1 and the respective thicknesses t2 of the plurality of second semiconductor chips C2. The thickness T of the interconnect chip INC may be in the range of about 30 μm or less, for example, about 30 μm to about 20 μm, about 25 μm to about 15 μm, about 20 μm to about 10 μm, etc., but is not limited thereto.

[0030] The base chip BC can be a buffer chip or a control chip including a number of logic elements and / or memory elements. For example, the base chip BC can transmit signals from the first semiconductor chip C1, the second semiconductor chip C2, and the uppermost semiconductor chip TC stacked on it to the outside, and further transmit signals and power from the outside to the semiconductor chips C1, C2. The semiconductor chips C1, C2, TC can be memory chips including volatile memory elements such as DRAM and SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, or RRAM.

[0031] Since the components of the base chip BC have substantially the same or similar features as those of the semiconductor chips C1, C2, and TC, the same or similar components are denoted by the same or similar terms and / or reference numerals, and the overlapping parts are replaced by the descriptions of the corresponding components. For example, the lower connection terminal LT and the upper connection terminal UT of the base chip BC correspond to the lower pad LP and the upper pad UP of the semiconductor chips C1, C2, and TC, the dielectric layer DL of the base chip BC corresponds to the lower insulating layer LI and the upper insulating layer UI of the semiconductor chips C1, C2, and TC, and the through electrode TV of the base chip BC can be understood to correspond to the through via TSV of the semiconductor chips C1 and C2.

[0032] The base chip BC can include a lower connection terminal LT and an upper connection terminal UT on opposite sides of each other, and a through electrode TV that electrically connects the lower connection terminal LT and the upper connection terminal UT.

[0033] The base chip BC can further include a dielectric layer DL surrounding the upper connection terminal UT. The upper connection terminal UT can be in direct contact with the first lower pad LP1 of the lowermost first semiconductor chip C1 adjacent in the vertical direction (Z direction). The dielectric layer DL can be in direct contact with the first lower insulating layer LI1 of the lowermost first semiconductor chip C1 adjacent in the vertical direction (Z direction).

[0034] The base chip BC can be electrically connected to an external device (e.g., a main board) via a plurality of connection bumps BP. The plurality of connection bumps BP are disposed under the base chip BC and can be electrically connected to the lower connection terminal LT. The plurality of connection bumps BP can include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof. According to an embodiment, the plurality of connection bumps BP can have a form combining conductive pillars and solder balls.

[0035] The mold layer ML can cover at least a part of each of the plurality of chip stacks CS1, CS2, at least one interconnect chip INC, and the uppermost semiconductor chip TC on the base chip BC. For example, the mold layer ML can cover the side surfaces of the first chip stack CS1, the side surfaces of the second chip stack CS2, the interconnect chip INC, and the side surfaces of the uppermost semiconductor chip TC. According to an embodiment, the upper surface of the uppermost semiconductor chip TC can be exposed from the mold layer ML.

[0036] Hereinafter, with reference to FIGS. 2a to 2d together with FIG. 1b, some components of the semiconductor package 10 will be described in more detail.

[0037] FIG. 2a is a partial enlarged view of the “A” region in FIG. 1b, and FIGS. 2b to 2d are drawings for explaining exemplary modifications of FIG. 2a. FIG. 2a shows in more detail some components of the semiconductor package 10, such as the substrate 110, the circuit layer 120, the through-silicon via TSV, and the interconnect via INV.

[0038] Referring to FIG. 2a, the substrate 110 can be a semiconductor wafer. The substrate 110 can include, for example, semiconductor elements such as silicon or germanium, or compound semiconductors such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The substrate 110 can include a conductive region 112 and a separation region 111 formed on the front surface 110S1. The conductive region 112 can be, for example, a well doped with impurities or a structure doped with impurities. The separation region 111 is an element isolation structure having a STI (shallow trench isolation) structure and can include silicon oxide.

[0039] The circuit layer 120 can be disposed on the front surface 110S1 of the substrate 110 on which the conductive region 112 is formed. The circuit layer 120 can include individual element IDs, an interlayer insulating layer 121, and a wiring structure 125.

[0040] The individual element IDs can be disposed on the front surface 110S1 of the substrate 110. The individual element IDs can include, for example, FETs such as planar FETs and FinFETs, memory elements such as flash memories, DRAMs, SRAMs, EEPROMs, PRAMs, MRAMs, FeRAMs, and RRAMs, logic elements such as AND, OR, and NOT, and various active and / or passive elements such as system LSIs, CISs, and MEMS.

[0041] The interlayer insulating layer 121 is formed to cover the individual element IDs and the wiring structure 125, and can electrically isolate the individual element IDs disposed on the substrate 110. The interlayer insulating layer 121 can include FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilaca Glass), BPSG (BoroPhosphoSilica Glass), PTEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. At least a partial region of the interlayer insulating layer 121 surrounding the wiring structure 125 can be composed of a low dielectric layer. The interlayer insulating layer 121 can be formed using chemical vapor deposition (CVD), flowable-CVD process, or spin coating process. Depending on the process, the boundary between the interlayer insulating layer 121 and the lower insulating layer LI may not be clearly distinguishable.

[0042] The wiring structure 125 can be formed in a multilayer structure including a plurality of wiring patterns and a plurality of vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) can be disposed between the wiring pattern or / and via and the interlayer insulating layer 121. The wiring structure 125 can be electrically connected to the conductive region 112 and / or the individual element ID by the interconnecting portion 123 (e.g., contact plug).

[0043] The lower pad LP can be electrically connected to the wiring structure 125. The lower pad LP can include, for example, at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0044] The lower insulating layer LI can surround the side surface of the lower pad LP. The lower insulating layer LI can include, for example, silicon oxide (SiO) or silicon carbonitride (SiCN). The lower insulating layer LI can form a bonding surface provided for dielectric bonding between the lower pads LP.

[0045] The upper pad UP can be electrically connected to the through-via TSV. The upper pad UP can be electrically connected to the conductive region 112 and / or the wiring structure 125 via the through-via TSV.

[0046] The upper insulating layer UI can surround the side surface of the upper pad UP. The upper insulating layer UI can include, for example, silicon oxide (SiO) or silicon carbonitride (SiCN). The upper insulating layer UI can form a bonding surface provided for dielectric bonding between the upper pads UP.

[0047] The through-via TSV can electrically connect the lower pad LP and the upper pad UP through the substrate 110. The through-via TSV can include a via plug 145 and a side barrier layer 141 surrounding its side surface. The via plug 145 can include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and can be formed by an electroplating process, a PVD process, or a CVD process. The side barrier layer 141 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and can be formed by an electroplating process, a PVD process, or a CVD process. A side insulating film 143 including an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (e.g., HARP oxide) can be formed between the side barrier layer 141 and the substrate 110.

[0048] The through-via TSV can penetrate an insulating protective layer 113 formed on the back surface 110S2 of the substrate 110. The insulating protective layer 113 can include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 114 such as a polishing stop layer or a barrier can be disposed on the insulating protective layer 113. For example, the buffer film can include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0049] The interconnect via INV can electrically connect the first through-via TSV1 of the uppermost first semiconductor chip C1a and the second through-via TSV2 of the lowermost second semiconductor chip C2a through the chip body 210. The interconnect via INV can include a via plug 145 and a side barrier layer 141. A side insulating film 143 can be formed between the side barrier layer 141 and the chip body 210.

[0050] In one embodiment, the lower end of the interconnect via INV of the interconnect chip INC may be in direct contact with the first upper pad UP1 of the uppermost first semiconductor chip C1a, and the upper end of the interconnect via INV of the interconnect chip INC may be in direct contact with the second lower pad LP2 of the lowermost second semiconductor chip C2a. The first upper insulating layer UI1 of the uppermost first semiconductor chip C1a and the second lower insulating layer LI2 of the lowermost second semiconductor chip C2a may be in contact with the chip body 210 of the interconnect chip INC. The lateral width D of the interconnect via INV may be at substantially the same level as the lateral width d1 of the first through-via TSV1 and the lateral width d2 of the second through-via TSV2. Here, "the same level" is a concept including process errors and can be understood as not being designed to be intentionally different.

[0051] Referring to FIG. 2b, in the semiconductor package 10a of the modified example, the interconnect via INV can be formed larger than the first through-via TSV1 and the second through-via TSV2. The lateral width D of the interconnect via INV may be larger than the lateral width d1 of the first through-via TSV1 and the lateral width d2 of the second through-via TSV2. The area of the interconnect via INV provided for metal bonding with the first upper pad UP1 and the second lower pad LP2 increases, and the connection reliability and bonding quality can be improved.

[0052] Referring to FIGS. 2c and 2d, in the semiconductor packages 10b and 10c of the modified example, the interconnect chip INC may further include a bonding pad BDP disposed at at least one of the lower end and the upper end of the interconnect via INV. The chip body 210 of the interconnect chip INC may include a semiconductor layer 210a surrounding the interconnect via INV and a passivation layer 210b surrounding the bonding pad BDP on at least one surface of the semiconductor layer 210a.

[0053] The bonding pad BDP can contact at least one of the first upper pad UP1 of the uppermost first semiconductor chip C1a and the second lower pad LP2 of the lowermost second semiconductor chip C2a. The passivation layer 210b can contact at least one of the first upper insulating layer UI1 of the uppermost first semiconductor chip C1a and the second lower insulating layer LI2 of the lowermost second semiconductor chip C2a. The first upper insulating layer UI1, the second lower insulating layer LI2, and the passivation layer 210b include at least one of silicon oxide (SiO) and silicon carbonitride (SiCN), and the semiconductor layer 210a can include, but is not limited to, semiconductor materials such as silicon (Si) and germanium (Ge). Thus, the interconnect chip INC can further include components provided for metal-to-metal bonding and dielectric-to-dielectric bonding.

[0054] Hereinafter, with reference to FIGS. 3a to 3c together with FIG. 1b, the side shape of the interconnect chip INC will be described in more detail.

[0055] FIG. 3a is a partial enlarged view of the “B” region of FIG. 1b, and FIGS. 3b to 3c are drawings for explaining exemplary modifications of FIG. 3a.

[0056] Referring to FIG. 3a, the interconnect chip INC can have a lower surface 210LS in contact with the first chip stack CS1, an upper surface 210US in contact with the second chip stack CS2, and a side surface 210SS between the lower surface 210LS and the upper surface 201US. The side surface 210SS of the interconnect chip INC can include a first portion 210S1 extending from the lower surface 210LS of the interconnect chip INC and a second portion 210S2 extending from the first portion 210S1 to the upper surface 210US of the interconnect chip INC.

[0057] The first portion 210S1 can extend at a certain inclination with respect to the lower surface 210LS of the interconnect chip INC. Since the second portion 210S2 is formed by a planarization process, it can extend at a constant or continuously changing inclination.

[0058] For example, the first portion 210S1 has a first lower end be1 connected to the lower surface 210LS of the interconnect chip INC and a first upper end te1 connected to the second portion 210S2, and can extend from the first lower end be1 to the first upper end te1 with a constant first inclination. The second portion 210S2 has a second lower end be2 connected to the first upper end te1 and a second upper end te2 connected to the upper surface 210US of the interconnect chip INC, and can extend from the second lower end be2 to the second upper end te2 with a decreasing second inclination. That is, the second inclination of the second portion 210S2 may be smaller than the first inclination of the first portion 210S1. As an example, the height h of the second portion 210S2 can be 1 / 2 or less of the thickness T of the interconnect chip INC, but is not limited thereto.

[0059] In one embodiment, the plurality of second semiconductor chips C2 can have a size (width and / or length) smaller than that of the interconnect chip INC in order to ensure the quality of the bonding surface and the alignment margin. Accordingly, the side surface SS2 of the second chip stack CS2 can be horizontally separated (e.g., in the X direction) from the second upper end te2 of the second portion 210S2. Considering the alignment margin between the plurality of second semiconductor chips C2, the side surfaces of the plurality of second semiconductor chips C2 constituting the side surface SS2 of the second chip stack CS2 may not form a flat vertical surface. That is, although the side surface SS2 of the second chip stack CS2 is shown as the side surface of the lowermost second semiconductor chip CS2a, depending on the embodiment, the side surfaces of the upper second semiconductor chips C2 that are not located in the same vertical plane as the side surface of the lowermost second semiconductor chip CS2a can also be horizontally separated (e.g., in the X direction) from the second upper end te2 of the second portion 210S2.

[0060] In addition, the interconnect chip INC can include a first region R1 that overlaps with the second chip stack CS2 in a first direction (Z direction), and a second region R2 that extends from the first region R1 and overlaps with the mold layer ML and the first chip stack CS1 in the first direction (Z direction). The total length of the boundary line between the second region R2 of the interconnect chip INC and the mold layer ML in the first direction (Z direction) may be greater than the thickness T of the interconnect chip INC in the first direction (Z direction). In FIG. 3a, the total length of the boundary line between the second region R2 and the mold layer ML can be defined as the sum of the length of the first portion 210S1, the length of the second portion 210S2, and the length of a portion of the upper surface 210US in contact with the mold layer ML.

[0061] In one embodiment, the interconnect chip INC can have a size (width and / or length) smaller than that of the plurality of first semiconductor chips C1 in consideration of the alignment margin and the stability of the planarization process. For example, the side surface 210SS (or the first portion 210S1) of the interconnect chip INC can be horizontally separated (e.g., in the X direction) from the side surface SS1 of the first chip stack CS1, but is not limited thereto (see the embodiment in FIG. 4). Considering the alignment margin between the plurality of first semiconductor chips C1, the side surfaces of the plurality of first semiconductor chips C1 constituting the side surface SS1 of the first chip stack CS1 may not form a flat vertical surface.

[0062] Referring to FIG. 3b, in the semiconductor package 10d of the modified example, the height h of the second portion 210S2 of the side surface 210SS of the interconnect chip INC can be equal to or greater than 1 / 2 of the thickness T of the interconnect chip INC. In this way, the thickness T of the interconnect chip INC can be minimized, the gap between the first chip stack CS1 and the second chip stack CS2 can be reduced, and the semiconductor package 10d can be miniaturized and thinned. According to the modified example, the side surface 210SS of the interconnect chip INC may not include the first portion 210S1 having a certain inclination.

[0063] Referring to FIG. 3c, in the semiconductor package 10e of the modification, the second upper end te2 of the second portion 210S2 of the side surface 210SS of the interconnect chip INC can be aligned in the vertical direction (Z direction). The plurality of second semiconductor chips C2 or the lowermost second semiconductor chip C2a can have substantially the same area as the flat upper surface 210US of the interconnect chip INC. Also in this case, considering that the edge portion of the interconnect chip INC is a curved surface and the alignment margin, the separation distance sd between the side surface 210SS (or the first portion 210S1) of the interconnect chip INC and the side surface SS2 of the second chip stack CS2 may be in the range of about 1 μm or more, for example, about 1 μm to about 10 μm, about 1 μm to about 8 μm, about 3 μm to about 8 μm, etc., but is not limited thereto.

[0064] FIG. 4 is a cross-sectional view of a semiconductor package 10A according to an exemplary embodiment.

[0065] Referring to FIG. 4, the semiconductor package 10A of the exemplary embodiment can have the same or similar features as those described with reference to FIGS. 1a to 3c, except that the width W of the interconnect chip INC is substantially the same as the width w1 of the first chip stack CS. In the exemplary embodiment, a planarization process can be applied to the interconnect chip INC to remove the surface topology accumulated by the plurality of first semiconductor chips C1. In order to ensure the bonding stability between the interconnect chip INC and the uppermost first semiconductor chip C1a during the planarization process, the interconnect chip INC can have an area substantially the same as at least the area of the uppermost first semiconductor chip C1a. However, considering the alignment margin between the interconnect chip INC and the uppermost first semiconductor chip C1a, the side surfaces of the interconnect chip INC and the uppermost first semiconductor chip C1a may not form the same vertical plane.

[0066] FIG. 5 is a cross-sectional view of a semiconductor package 10B according to an exemplary embodiment.

[0067] Referring to FIG. 5, the semiconductor package 10B of the exemplary embodiment can have the same or similar features as those described with reference to FIGS. 1a to 4, except that it includes a larger number (e.g., eight) of first semiconductor chips C1 than the second chip stack CS2 with the top semiconductor chip TC added to the first chip stack CS1 (e.g., four). In the exemplary embodiment, the interconnect chip INC can be disposed on the topmost first semiconductor chip C1a on which the surface topology has been accumulated to such an extent that it degrades the bonding quality of the bonding surface after the maximum number of first semiconductor chips C1 are stacked. That is, the number of the plurality of first semiconductor chips C1 constituting the first chip stack CS1 is not particularly limited. The surface topology characteristics of the topmost first semiconductor chip C1a on which the interconnect chip INC is disposed will be described later with reference to FIGS. 12a and 12b.

[0068] FIG. 6 is a cross-sectional view of a semiconductor package 10C according to an exemplary embodiment.

[0069] Referring to FIG. 6, the semiconductor package 10C of the exemplary embodiment can have the same or similar features as those described with reference to FIGS. 1a to 5, except that it includes a plurality of interconnect chips INC1, INC2. Depending on the embodiment, the plurality of interconnect chips INC1, INC2 and the plurality of chip stacks CS1, CS2, CS3 may be stacked in a larger number than those shown in the drawing.

[0070] The semiconductor package 10C can include a base chip BC, a first chip stack CS1, a second chip stack CS2, a third chip stack CS3, a top semiconductor chip TC, a first interconnect chip INC1, and a second interconnect chip INC2. Since the base chip BC, the first chip stack CS1, the second chip stack CS2, and the first interconnect chip INC1 have substantially the same features as the base chip BC, the first chip stack CS1, the second chip stack CS2, and the interconnect chip INC described above, the overlapping description will be omitted below.

[0071] The second interconnect chip INC2 may be disposed on the uppermost second semiconductor chip C2b among the plurality of second semiconductor chips C2. The second interconnect chip INC2 can remove the surface topology accumulated by the plurality of second semiconductor chips C2, and improve the bonding quality and reliability of the third chip stack CS3. The second interconnect chip INC2 can have a lower surface 210LS in contact with the uppermost second semiconductor chip C2b and an upper surface 210US in contact with the lowermost third semiconductor chip C3a. The lower surface 210LS of the second interconnect chip INC2 is a wave surface on which the surface topologies of the plurality of second semiconductor chips C2 are accumulated, whereas the upper surface 210US of the second interconnect chip INC2 can be a flat surface to which a planarization process has been applied. Since the second interconnect chip INC2 has substantially the same features as the above-described interconnect chip INC, the description thereof is replaced with the description with reference to FIGS. 1a to 3c.

[0072] The third chip stack CS3 can include a plurality of third semiconductor chips C3 stacked in a first direction (Z direction) on the second interconnect chip INC2. Depending on the embodiment, the plurality of third semiconductor chips C3 may be provided fewer or more than those shown in the drawings. The third chip stack CS3 can have a width smaller than the horizontal width of the second interconnect chip INC2.

[0073] The plurality of third semiconductor chips C3 can include third lower pads LP3 and third upper pads UP3 on opposite sides of each other, and third through vias TSV3. The third through vias TSV3 may be electrically connected to the second through vias TSV2 in the first direction (Z direction). The uppermost semiconductor chip TC can include connection pads CP electrically connected to the third through vias TSV3 of the uppermost third semiconductor chip C3.

[0074] Each of the plurality of third semiconductor chips C3 can include a third lower insulating layer LI3 surrounding a third lower pad LP3 and a third upper insulating layer UI3 surrounding a third upper pad UP3. The third upper insulating layer UI3 of each of the plurality of third semiconductor chips C3 can contact the third lower insulating layer LI3 of each of the plurality of third semiconductor chips C3 adjacent in the first direction (Z direction). The third upper pad UP3 of each of the plurality of third semiconductor chips C3 can contact the third lower pad LP3 of each of the plurality of third semiconductor chips C3 adjacent in the first direction (Z direction).

[0075] FIG. 7a is a plan view of a semiconductor package 1 according to an exemplary embodiment of the present invention, and FIG. 7b is a cross-sectional view taken along line II-II' of FIG. 7a.

[0076] Referring to FIGS. 7a and 7b, the semiconductor package 1 of the exemplary embodiment can include a package substrate 600, an interposer substrate 700, a first chip structure 800, and a second chip structure 900.

[0077] The first chip structure 800 can include a logic chip such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-digital converter, an ASIC, etc.

[0078] The second chip structure 900 can be understood as a semiconductor package structure having the same or similar features as the semiconductor packages 10, 10a, 10b, 10c, 10d, 10e, 10A, 10B, 10C described with reference to FIGS. 1a to 6. For example, the second chip structure 900 can include a high-capacity memory device such as a high bandwidth memory (HBM).

[0079] The package substrate 600 is a support substrate on which the interposer substrate 700 is mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, or the like. The package substrate 600 can include a lower pad 612, an upper pad 611, and a wiring circuit 613. External connection bumps 615 connected to the lower pad 612 may be disposed on the lower surface of the package substrate 600. The external connection bumps 615 can include, for example, solder balls.

[0080] The interposer substrate 700 can include a semiconductor substrate 701, a lower protective layer 703, lower pads 705, an interconnect structure 710, conductive bumps 720, and silicon through vias 730. The first chip structure 800 and the second chip structure 900 can be electrically connected to each other through the interposer substrate 700.

[0081] The semiconductor substrate 701 can be formed of, for example, any one of silicon, an organic material, plastic, and a glass substrate. When the semiconductor substrate 701 is a silicon substrate, the interposer substrate 700 can be referred to as a silicon interposer. Different from what is shown in the drawings, when the semiconductor substrate 701 is an organic substrate, the interposer substrate 700 can be referred to as a panel interposer.

[0082] The lower protective layer 703 is disposed on the lower surface of the semiconductor substrate 701, and the lower pads 705 can be disposed under the lower protective layer 703. The lower pads 705 can be connected to the silicon through vias 730. The interposer substrate 700 can be electrically connected to the package substrate 600 through the conductive bumps 720 disposed under the lower pads 705.

[0083] The interconnect structure 710 is disposed on the upper surface of the semiconductor substrate 701 and can include an interlayer insulating layer 711 and a single-layer or multilayer wiring structure 712. When the interconnect structure 710 consists of a multilayer wiring structure, the wiring patterns of different layers may be connected to each other via contact vias. The first semiconductor chip structure 800 and the second semiconductor chip structure 900 can be electrically connected to the upper pad 704 via the connection bumps BP.

[0084] The silicon through-via 730 can extend from the upper surface to the lower surface of the semiconductor substrate 701. Also, the silicon through-via 730 may extend into the interior of the interconnect structure 710 and be electrically connected to the multilayer wiring structure 712. Depending on the embodiment, the interposer substrate 700 may only include an interconnect structure inside and may not include the silicon through-via 730.

[0085] The interposer substrate 700 can be used for the purpose of converting or transmitting an input electrical signal between the package substrate 600 and the first chip structure 800 or the second chip structure 900. Therefore, the interposer substrate 700 may not include elements such as active elements and passive elements. Further, depending on the embodiment, the interconnect structure 710 may be disposed below the silicon through-via 730. For example, the positional relationship between the interconnect structure 710 and the silicon through-via 730 can be relative.

[0086] FIGS. 8A to 11B are drawings for explaining the manufacturing process of an exemplary semiconductor package.

[0087] Referring to FIGS. 8a and 8b, a first chip stack CS1 including a plurality of first semiconductor chips C1 can be formed on a semiconductor wafer WF. The semiconductor wafer WF can include a preliminary base chip BC' divided by a scribe lane SL. The plurality of first semiconductor chips C1 can be stacked in the vertical direction (Z direction). The plurality of first semiconductor chips C1 can be joined by a thermal compression process. The plurality of first semiconductor chips C1 can be directly joined by an intermetallic bonding and an interdielectric bonding (hereinafter referred to as "direct bonding") without conductive members (such as solder bumps, copper pillars, etc.) for electrical connection. The plurality of base chips BC and the plurality of first semiconductor chips C1 can be understood to include the components described with reference to FIGS. 1a to 2a. Since the upper and lower surfaces of the plurality of first semiconductor chips C1 are directly joined, the upper surface US of the uppermost first semiconductor chip C1a with the surface topology accumulated may have a reduced surface topology characteristic.

[0088] Referring to FIGS. 9a and 9b, interconnect chips INC can be respectively attached on the first chip stack CS1. The interconnect chips INC can be joined to the uppermost first semiconductor chip C1a by a thermal compression process. Since the interconnect chips INC are directly joined to the uppermost first semiconductor chip C1a, the temporary upper surface 210US' of the interconnect chips INC can have a surface topology corresponding to the uppermost first semiconductor chip C1a. The interconnect chips INC can have a size (width and / or length) smaller than that of the plurality of first semiconductor chips C1, but not limited thereto, considering the stability of the alignment margin and the planarization process. The surface topologies of the uppermost first semiconductor chip C1a and the interconnect chips INC are shown simplified in a one-directional waveform form for the convenience of explanation.

[0089] Referring to FIGS. 10a and 10b, a planarization process can be applied to the interconnected chip INC. The planarization process can include a grinding process and a polishing process. For example, by removing a portion of the upper part of each of the interconnected chips INC using planarization equipment PT such as a grinding wheel or a polishing pad, a flat surface provided for "direct bonding" can be formed. Therefore, the lower surface 210LS of the interconnected chip INC is a wave surface having height irregularities (or a number of protrusions), and the upper surface 210US of the interconnected chip INC can be a flat surface. The upper surface 210US of the interconnected chip INC can be polished to have a surface roughness (Ra) in the range of about 0.05 nm or less, for example, about 0.01 nm to about 0.05 nm. The lower surface 210LS of the interconnected chip INC directly bonded to the uppermost first semiconductor chip C1a can also have a surface roughness (Ra) of about 0.05 nm or less. A portion of each side surface of the planarized interconnected chip INC can be a curved surface with a constantly changing inclination (see, for example, FIG. 3a).

[0090] Referring to FIGS. 11a and 11b, a second chip stack CS2 including a plurality of second semiconductor chips C2 can be formed on the planarized interconnected chip INC, and the uppermost semiconductor chip TC can be attached. The plurality of second semiconductor chips C2 can be stacked vertically (in the Z direction) on the interconnected chip INC. The plurality of second semiconductor chips C2 can be directly bonded without a conductive member (e.g., a solder bump, a copper pillar, etc.) by a thermo-compression bonding process. The plurality of second semiconductor chips C2 can be understood to include the components described with reference to FIGS. 1a to 2a.

[0091] Since the plurality of second semiconductor chips C2 are stacked on the upper surface 210US of the planarized interconnect chip INC, a second chip stack CS2 with excellent bonding quality between the plurality of second semiconductor chips C2 can be formed. The plurality of second semiconductor chips C2 can have a size (width and / or length) smaller than that of the interconnect chip INC in order to ensure the quality of the bonding surface and the alignment margin. The respective horizontal widths (in the X and Y directions) of the second chip stack CS2 may be smaller than the respective horizontal widths of the corresponding interconnect chip INC. Considering that the edge portion of the interconnect chip INC is a curved surface and the alignment margin, the separation distance sd between one side surface of the interconnect chip INC and one side surface of the second chip stack CS2 may be in the range of about 1 μm or more, for example, about 1 μm to about 10 μm, about 1 μm to about 8 μm, about 3 μm to about 8 μm, etc., but is not limited thereto.

[0092] After that, a mold layer for exposing the uppermost semiconductor chip TC on the semiconductor wafer WF can be formed, and a cutting process can be performed along the scribe lane SL to separate individual semiconductor packages.

[0093] FIGS. 12a and 12b are graphs for explaining the surface topology of the interconnect chip INC before and after the planarization process. FIGS. 12a and 12b show the results of scanning the surface topology of the interconnect chip INC before and after the planarization process using an AFM (Atomic Force Microscope). FIG. 12a shows the surface topology in the a-a' range of FIG. 9b, and FIG. 12b shows the surface topology in the b-b' range of FIG. 10b.

[0094] Referring to FIGS. 12a and 12b, the temporary upper surface 210US' of the interconnected chip INC before the planarization process has topological characteristics with a large difference in the height of surface bending. For example, the difference between the highest point and the lowest point on the temporary upper surface 210US' can be about 4,000 Å or more. The inclination of the surface bending on the temporary upper surface 210US' can be about 3 Å / μm or more. However, this is a numerical value exemplarily defining the surface topological characteristics that may reduce the bonding quality of direct bonding, and the embodiments of the present invention are not applicable only within the above-described numerical range.

[0095] The upper surface 210US of the interconnected chip INC after the planarization process can be a flat surface from which surface bending has been removed. Therefore, the difference between the highest point and the lowest point on the upper surface 210US of the interconnected chip INC is about 10 Å or less, and the inclination of the surface bending can be about 0.1 Å / μm or less. However, this is an exemplary numerical value, and the difference between the highest point and the lowest point on the upper surface 210US of the interconnected chip INC and the inclination of the surface bending can be substantially close to 0.

[0096] The present invention is not limited by the above-described embodiments and the attached drawings, but is limited by the attached claims. Therefore, various forms of substitution, modification, and change are possible by those having ordinary knowledge in the art without departing from the technical idea of the present invention described in the claims, and it can also be said that this belongs to the scope of the present invention.

Claims

1. a base chip including a lower connection terminal and an upper connection terminal on opposite sides of each other, and a through electrode electrically connecting the lower connection terminal and the upper connection terminal; a first chip stack including a plurality of first semiconductor chips stacked in a first direction on the base chip, the first semiconductor chips including first lower pads and first upper pads opposite each other, and first through vias electrically connecting the first lower pads and the first upper pads; a second chip stack including a plurality of second semiconductor chips stacked in the first direction on the first chip stack, the second semiconductor chips including second lower pads and second upper pads opposite each other and second through vias electrically connecting the second lower pads and the second upper pads; an interconnect chip disposed between the first chip stack and the second chip stack, the interconnect chip including an interconnect via electrically connecting the first through via and the second through via; a molding layer covering at least a portion of each of the first chip stack, the second chip stack, and the interconnect chip on the base chip; a plurality of connection bumps disposed under the base chip and electrically connected to the lower connection terminals; the first lower pads of each of the first semiconductor chips contact the upper connection terminals of the base chip adjacent in the first direction and the first upper pads of each of the first semiconductor chips adjacent in the first direction; the second upper pads of each of the plurality of second semiconductor chips contact the second lower pads of each of the plurality of second semiconductor chips adjacent to each other in the first direction; the interconnect chip has a bottom surface in contact with the first chip stack, a top surface in contact with the second chip stack, and a side surface between the bottom surface and the top surface; a semiconductor package, the side of the interconnect chip including a first portion extending at a first incline from the bottom surface of the interconnect chip, and a second portion extending from the first portion to the top surface of the interconnect chip at a second incline less than the first incline.

2. the first portion has a first lower end coupled to the lower surface of the interconnect chip and a first upper end coupled to the second portion; The semiconductor package of claim 1 , wherein the first slope is constant from the first bottom end to the first top end.

3. the second portion has a second lower end coupled to the first upper end of the first portion and a second upper end coupled to the top surface of the interconnect chip; The semiconductor package of claim 2 , wherein the second slope decreases from the second bottom end to the second top end.

4. The semiconductor package of claim 3 , wherein a side surface of the second chip stack is spaced apart from the second top end of the second portion.

5. 2. The semiconductor package of claim 1, wherein a thickness from the bottom surface to the top surface of the interconnect chip is smaller than a thickness of a first semiconductor chip adjacent in the first direction among the plurality of first semiconductor chips and a thickness of a second semiconductor chip adjacent in the first direction among the plurality of second semiconductor chips.

6. 6. The semiconductor package of claim 5, wherein the thickness of the interconnect chip is about 30 [mu]m or less.

7. The semiconductor package of claim 1 , wherein a first width of the first chip stack in a second direction perpendicular to the first direction is greater than a second width of the second chip stack in the second direction.

8. 8. The semiconductor package of claim 7, wherein the width of the interconnect chip in the second direction is equal to or smaller than the first width and is greater than the second width.

9. The semiconductor package according to claim 8 , wherein a third width of the base chip in the second direction is greater than the first width.

10. The semiconductor package of claim 1 , further comprising a top semiconductor chip disposed on the second chip stack and including connection pads electrically coupled to the second through vias.

11. Each of the plurality of first semiconductor chips further includes a first lower insulating layer surrounding the first lower pad and a first upper insulating layer surrounding the first upper pad; Each of the plurality of second semiconductor chips further includes a second lower insulating layer surrounding the second lower pad and a second upper insulating layer surrounding the second upper pad; the interconnect chip further includes a chip body surrounding the interconnect via and defining the lower surface and the upper surface; 2. The semiconductor package of claim 1, wherein the first upper insulating layer of a first semiconductor chip among the plurality of first semiconductor chips adjacent to the interconnect chip in the first direction, and the second lower insulating layer of a second semiconductor chip among the plurality of second semiconductor chips adjacent to the interconnect chip in the first direction, contact the chip body of the interconnect chip.

12. the first lower insulating layer, the first upper insulating layer, the second lower insulating layer, and the second upper insulating layer include at least one of silicon oxide (SiO) and silicon carbonitride (SiCN); The semiconductor package of claim 11 , wherein the chip body comprises silicon (Si).

13. a lower end of the interconnect via of the interconnect chip contacts the first upper pad of the first semiconductor chip; The semiconductor package of claim 11 , wherein a top end of the interconnect via of the interconnect chip contacts the second bottom pad of the second semiconductor chip.

14. the interconnect chip further includes a bonding pad disposed on at least one of a lower end and an upper end of the interconnect via; the chip body of the interconnect chip further includes a semiconductor layer surrounding the interconnect vias and a passivation layer surrounding the bonding pads on at least one side of the semiconductor layer; the bonding pad contacts at least one of the first upper pad of the first semiconductor chip and the second lower pad of the second semiconductor chip; The semiconductor package of claim 11 , wherein the passivation layer contacts at least one of the first upper insulating layer of the first semiconductor chip and the second lower insulating layer of the second semiconductor chip.

15. the first lower insulating layer, the first upper insulating layer, the second lower insulating layer, the second upper insulating layer, and the passivation layer include at least one of silicon oxide (SiO) and silicon carbonitride (SiCN); The semiconductor package of claim 14 , wherein the semiconductor layer of the chip body comprises silicon (Si).

16. the base chip further includes a dielectric layer surrounding the upper connection terminal; the first lower insulating layer of each of the plurality of first semiconductor chips contacts the dielectric layer of the base chip adjacent in the first direction and the first upper insulating layer of each of the plurality of first semiconductor chips adjacent in the first direction; The semiconductor package of claim 11 , wherein the second upper insulating layer of each of the second semiconductor chips contacts the second lower insulating layer of each of the second semiconductor chips adjacent in the first direction.

17. a base chip including a through electrode; a first chip stack including a plurality of first semiconductor chips stacked in a first direction on the base chip and including first through vias electrically connected to the through electrodes in the first direction; a second chip stack including a plurality of second semiconductor chips stacked on the first chip stack in the first direction and including second through vias electrically connected to the first through vias in the first direction; an interconnect chip disposed between the first chip stack and the second chip stack, the interconnect chip including an interconnect via electrically connecting the first through via and the second through via; a mold layer covering a side surface of the first chip stack, a side surface of the second chip stack, and a side surface of the interconnect chip; the interconnect chip includes a first region overlapping the second chip stack in the first direction, and a second region extending from the first region and overlapping the molding layer and the first chip stack in the first direction.

18. 20. The semiconductor package of claim 17, wherein a total length of a boundary between the second region of the interconnect chip and the molding layer in the first direction is greater than a thickness of the interconnect chip in the first direction.

19. a base chip including a through electrode; a plurality of first semiconductor chips stacked in a first direction on the base chip and including first through vias electrically connected to the through electrodes in the first direction; a plurality of second semiconductor chips stacked in the first direction on the plurality of first semiconductor chips and including second through vias electrically connected to each other in the first direction; an interconnection chip disposed between an uppermost first semiconductor chip of the plurality of first semiconductor chips and a lowermost second semiconductor chip of the plurality of second semiconductor chips, the interconnection chip including an interconnection via electrically connecting the first through via and the second through via; a thickness of the interconnect chip in the first direction is smaller than a thickness of each of the plurality of first semiconductor chips and a thickness of each of the plurality of second semiconductor chips; the interconnect chip has a bottom surface in contact with the top first semiconductor chip and a top surface in contact with the bottom second semiconductor chip; the lower surface of the interconnect chip is a wave surface having height variations; The top surface of the interconnect chip is a flat surface.

20. 20. The semiconductor package of claim 19, wherein the bottom surface and the top surface of the interconnect chip each have a surface roughness of about 0.05 nm or less.

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