Display panel, method for manufacturing the same, and display device

Abstract

To provide a display panel, a method for manufacturing the same, and a display device.SOLUTION: The display panel includes a base, a functional film layer including a power supply signal line layer, a data line layer, and a compensation function layer, and a plurality of first light-emitting elements. The power supply signal line layer of the functional film layer includes power source signal line patterns (VDD1 and VDD2) arranged at each sub-pixel area, the data line layer includes data line patterns (DATA1 and DATA2) arranged at each sub-pixel area, and the compensation function layer includes a compensation function pattern (401) arranged at at least one sub-pixel area. The first light-emitting element includes a first anode (501), a first light-emitting pattern (601), and a first cathode. The first anode (501) has a first overlapping region, a second overlapping region, and a third overlapping region with the power source signal line patterns (VDD1 and VDD2), the data line patterns (DATA1 and DATA2), and the compensation function pattern (401) respectively.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present disclosure relates to the technical field of displays, and particularly to a display panel, a manufacturing method thereof, and a display device. It is related to.

Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) displays products are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high definition, excellent flexibility, and high luminous efficiency. Among them, they are widely used in various fields.

[0003] On the other hand, as the application range of AMOLED display products expands, the requirements for the display quality of AMOLED display products are also increasing. Among them, the color shift phenomenon that is likely to occur during display by display products has attracted wide attention from people. Among them, the color shift phenomenon that is likely to occur during display by display products has attracted wide attention from people.

Summary of the Invention

[0004] The object of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.

[0005] The first aspect of the present disclosure is a display panel, comprising a base, a functional film layer provided on the base, and a plurality of first light-emitting elements provided on the side of the functional film layer opposite to the base, and further comprising a plurality of sub-pixel areas arranged in an array, wherein the functional film layer includes a power signal line layer, a data line layer, and a compensation functional layer, the power signal line layer includes a power signal line pattern provided in each of the sub-pixel areas, the data line layer includes a data line pattern provided in each of the sub-pixel areas, and the power signal line pattern is included, and further includes a plurality of sub-pixel areas arranged in an array. The functional film layer includes a power signal line layer, a data line layer, and a compensation functional layer. The power signal line layer includes a power signal line pattern provided in each sub-pixel area. The data line layer includes a data line pattern provided in each sub-pixel area. The power signal line pattern includes a power signal line pattern provided in each sub-pixel area, and the data line pattern , including a first portion extending along a first direction, the data line pattern extends along the first direction and the compensation function layer includes a compensation function pattern provided in at least one of the sub-pixel areas . Each of the first light-emitting elements includes a first anode, a first light-emitting pattern, and a first cathode sequentially stacked along a direction away from the base, and a positive projection of the first anode on the base has a first overlap region with a positive projection of the corresponding power signal line pattern on the base, and a positive projection of the first anode on the base has a second overlap region with a positive projection of the corresponding data line pattern on the base, and a positive projection of the first anode on the base has a third overlap region with a positive projection of the corresponding compensation function pattern on the base, and the second overlap region is located between the first overlap region and the third overlap region, providing a display panel . Optionally, the first anode includes a first edge portion and a second edge portion provided opposite to each other along a second direction, and a first intermediate portion located between the first edge portion and the second edge portion, and the second direction intersects the first direction .

[0006] Optionally, a positive projection of the first edge portion on the base includes the first overlap region, a positive projection of the second edge portion on the base includes the third overlap region, and a positive projection of the first intermediate portion on the base includes the second overlap region . Optionally, a positive projection of the first edge portion on the base does not overlap with a positive projection of the first light-emitting pattern on the base, and a positive projection of the second edge portion on the base does not overlap with a positive projection of the first light-emitting pattern on the base and a positive projection of the second edge portion on the base does not overlap with a positive projection of the first light-emitting pattern on the base.

[0007] Optionally, a positive projection of the first edge portion on the base does not overlap with a positive projection of the first light-emitting pattern on the base, and a positive projection of the second edge portion on the base does not overlap with a positive projection of the first light-emitting pattern on the base, and a positive projection of the second edge portion on the base The orthographic projection does not overlap with the orthographic projection of the first light-emitting pattern on the base, and the The orthographic projection of the first intermediate portion on the base overlaps with the orthographic projection of the first light-emitting pattern on the base.

[0008] Optionally, the functional film layer further includes a gate scanning line layer, an initialization signal line layer, a reset signal line layer, and a light emission control signal line layer, The gate scanning line layer includes a gate scanning line pattern provided in each of the sub-pixel areas, The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas, The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas, The light emission control signal line layer includes a light emission control signal line pattern provided in each of the sub-pixel areas, The gate scanning line pattern, the initialization signal line pattern, the reset signal line pattern, and the light emission control signal line pattern all extend along a second direction, and the second direction intersects with the first direction.

[0009] Optionally, the first anode further includes a third edge portion and a fourth edge portion provided opposite to each other along the first direction, the first intermediate portion is located between the third edge portion and the fourth edge portion, the third edge portion is respectively coupled to the first edge portion and the second edge portion, and the fourth edge portion is respectively coupled to the first edge portion and the second edge portion described above. The orthographic projection of the first intermediate portion on the base, the orthographic projection of the corresponding gate scanning line pattern on the base, and the orthographic projection of the corresponding reset signal line pattern on the base include a sixth overlapping region. ​​

[0010] Optionally, the first anode includes a body portion and a via hole connection portion, and the body portion includes the first edge portion, the second edge portion, the third edge portion, the fourth edge portion and the first intermediate portion, and the body portion has a centrosymmetric pattern.

[0011] Optionally, the first intermediate portion has a centrosymmetric pattern, and the orthographic projection of the first intermediate portion on the base overlaps the orthographic projection of the first light-emitting pattern on the base.

[0012] Optionally, the display panel includes a first metal layer, a second metal layer, and a third metal layer, and the gate scanning line layer, the reset signal line layer, and the light-emitting control signal line layer are located in the first metal layer, the initialization signal line layer is located in the second metal layer, the data line layer, the power supply signal line layer, and the compensation function layer are located in the third metal layer, the functional film layer further includes a first insulating layer and a second insulating layer. The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer. The functional film layer further includes a first insulating layer and a second insulating layer. The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer. The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer. is located between the second metal layer and the third metal layer.

[0013] Optionally, the compensation function pattern is made of a conductive material and is coupled to the initialization signal line pattern. is coupled to the initialization signal line pattern.

[0014] Optionally, the compensation function pattern is provided in the same layer as the data line pattern.

[0015] Optionally, the display panel further includes a plurality of sub-pixel driving circuits. Among the plurality of sub-pixel driving circuits, the first part of the sub-pixel driving circuits corresponds one-to-one with the first light-emitting elements. Among the plurality of sub-pixel driving circuits, the first part of the sub-pixel driving circuits corresponds one-to-one with the first light-emitting elements. , the sub-pixel driving circuit of the first part is for driving the light emission of the corresponding first light-emitting element and the sub-pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor. The gate of the first transistor is coupled to the corresponding gate scanning line pattern, and the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor. The gate of the second transistor is coupled to the corresponding reset signal line pattern, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor. The gate of the fourth transistor is coupled to the corresponding gate scanning line pattern, and the first electrode of the fourth transistor is coupled to the corresponding data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor. The first electrode of the driving transistor is coupled to the corresponding power supply signal line pattern, and the second electrode of the driving transistor is coupled to the corresponding first light-emitting element. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power supply signal line pattern.

[0016] Optionally, the sub-pixel driving circuit further includes a first conductive connection part, and the second electrode of the first transistor is coupled to the gate of the driving transistor through the first conductive connection part. The display panel further includes a third metal layer, and the first conductive connection part is located in the third metal layer. Place it, and the positive on the base of the first conductive connection part included in the sub-pixel driving circuit of the first part The projection does not overlap with the positive projection on the base of the corresponding first anode. .

[0017] Optionally, the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements , and each of the second light-emitting elements includes a second anode, a second light-emitting pattern, and a second cathode that are sequentially stacked along the direction away from the base. Each of the third light-emitting elements includes two sub-light-emitting elements provided opposite to each other along the first direction, and each of the sub-light-emitting elements includes a third anode, a third light-emitting pattern, and a third cathode that are sequentially stacked along the direction away from the base. The plurality of sub-pixel driving circuits further include a sub-pixel driving circuit of a second part and a sub-pixel driving circuit of a third part. The sub-pixel driving circuit of the second part corresponds to the second light-emitting element one-to-one, and the sub-pixel driving circuit of the second part is for driving the light emission of the corresponding second light-emitting element. The sub-pixel driving circuit of the third part corresponds to the sub-light-emitting element one-to-one, and the sub-pixel driving circuit of the third part is for driving the light emission of the corresponding sub-light-emitting element. The positive projection on the base of the first conductive connection part included in the sub-pixel driving circuit of the second part overlaps with the positive projection on the electrode of the corresponding second anode. The positive projection on the base of the first conductive connection part included in the sub-pixel driving circuit of the third part overlaps with the positive projection on the base of the corresponding third anode. The sub-pixel driving circuit of the second part corresponds to the second light-emitting element one-to-one, and the sub-pixel driving circuit of the second part is for driving the light emission of the corresponding second light-emitting element. The sub-pixel driving circuit of the third part corresponds to the sub-light-emitting element one-to-one, and the sub-pixel driving circuit of the third part is for driving the light emission of the corresponding sub-light-emitting element. The sub-pixel driving circuit of the third part corresponds to the sub-light-emitting element one-to-one, and the sub-pixel driving circuit of the third part is for driving the light emission of the corresponding sub-light-emitting element. is for that. The positive projection on the base of the first conductive connection part included in the sub-pixel driving circuit of the second part overlaps with the positive projection on the electrode of the corresponding second anode. The positive projection on the base of the first conductive connection part included in the sub-pixel driving circuit of the third part overlaps with the positive projection on the base of the corresponding third anode. The positive projection on the base of the first conductive connection part included in the sub-pixel driving circuit of the third part overlaps with the positive projection on the base of the corresponding third anode.

[0018] Optionally, the gate of the first transistor is in direct contact with the corresponding gate scanning line pattern.

[0019] Optionally, the orthographic projection of the first electrode of the first transistor on the base does not overlap with the orthographic projection of the corresponding compensation function pattern on the base.

[0020] Optionally, the orthographic projection of the second electrode of the first transistor on the base does not overlap with the orthographic projection of the corresponding compensation function pattern on the base.

[0021] Optionally, the sub-pixel driving circuit further includes a seventh transistor. The gate of the seventh transistor is coupled to the reset signal line pattern. The second electrode of the seventh transistor in the first part of the sub-pixel driving circuit is coupled to the first anode. There is a seventh overlap region between the orthographic projection of the first electrode of the seventh transistor on the base and the orthographic projection of the corresponding compensation function pattern on the base. The first electrode of the seventh transistor is coupled to the corresponding compensation function pattern through a via hole provided in the seventh overlap region, and thus is indirectly coupled to the corresponding initialization signal line pattern through the compensation function pattern.

[0022] Optionally, the orthographic projection of the gate of the driving transistor on the base at least partially overlaps with the orthographic projection of the corresponding compensation function pattern on the base.

[0023] Optionally, there is a first overlap region that overlaps between the orthographic projection of the gate of the driving transistor on the base and the orthographic projection of the corresponding compensation function pattern on the base. ​​​​​​​​​​​​ includes an overlapping portion, The orthographic projection of the first overlapping portion on the base overlaps at least partially with the orthographic projection of the corresponding first anode on the base.

[0024] Optionally, the first electrode plate of the storage capacitor is provided with the same material as the gate scanning line pattern and the reset signal line pattern, and the second electrode plate of the storage capacitor is provided with the same material as the initialization signal line pattern, The orthographic projection of the first electrode plate of the storage capacitor on the base and the orthographic projection of the second electrode plate of the storage capacitor on the base are both located between the orthographic projection of the corresponding gate scanning line pattern on the base and the orthographic projection of the corresponding light emission control signal line pattern on the base.

[0025] Optionally, the functional film layer further includes a gate insulating layer and a first insulating layer located on the side opposite to the base in the gate insulating layer, and the first electrode plate of the storage capacitor, the gate scanning line pattern and the reset signal line pattern are all located on the surface of the gate insulating layer opposite to the base, and the second electrode plate of the storage capacitor and the initialization signal line pattern are both located on the surface of the first insulating layer opposite to the base.

[0026] Optionally, the orthographic projection of the first electrode plate of the storage capacitor on the base and the orthographic projection of the second electrode plate of the storage capacitor on the base both overlap partially with the orthographic projection of the corresponding first anode on the base.

[0027] Optionally, the orthographic projection of the first electrode plate of the storage capacitor on the base and the orthographic projection of the second electrode plate of the storage capacitor on the base ​​​​​​​​​​​The orthographic projections of the second electrode plate on the base all partially overlap with the orthographic projections of the corresponding compensation function patterns on the base. Overlap with the orthographic projections of the corresponding compensation function patterns on the base.

[0028] Optionally, the central region of the second electrode plate of the storage capacitor includes an opening, and the orthographic projection of the opening on the base Does not overlap with the orthographic projection of the corresponding compensation function pattern on the base. Overlap with the orthographic projections of the corresponding compensation function patterns on the base.

[0029] Optionally, in the direction perpendicular to the base, the thickness difference between the compensation function layer and the power signal line layer is within a threshold range, or the thickness difference between the compensation function layer and the data line layer is within a threshold range. Overlap with the orthographic projections of the corresponding compensation function patterns on the base. Overlap with the orthographic projections of the corresponding compensation function patterns on the base.

[0030] Optionally, the display panel further includes a plurality of second light-emitting elements, Each of the second light-emitting elements includes a second anode, a second light-emitting pattern, and a second cathode that are sequentially stacked along the direction away from the base, and the second anode includes A fifth edge portion and a sixth edge portion provided opposite to each other along the second direction, and a second intermediate portion located between the fifth edge portion and the sixth edge portion. The orthographic projection of the second intermediate portion on the base Overlaps with the orthographic projection of the second light-emitting pattern on the base, The orthographic projection of the second intermediate portion on the base at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the base, and the orthographic projection of the second intermediate portion on the base Overlaps with the orthographic projection of the corresponding data line pattern on the base at least partially. Overlaps with the orthographic projection of the second light-emitting pattern on the base. The orthographic projection of the second intermediate portion on the base at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the base, and the orthographic projection of the second intermediate portion on the base Overlaps with the orthographic projection of the corresponding data line pattern on the base at least partially. Overlaps with the orthographic projection of the corresponding data line pattern on the base at least partially. Overlaps with the orthographic projection of the corresponding data line pattern on the base at least partially.

[0031] Optionally, the second light-emitting pattern is symmetric with respect to a second axis of symmetry, and the second axis of symmetry extends along the first direction, and the orthogonal projection of the base of the second symmetry axis on the base of the corresponding power signal line pattern is located inside the orthogonal projection on the base of the corresponding power signal line pattern. is located inside the orthogonal projection on the base of the corresponding power signal line pattern.

[0032] Optionally, the display panel further includes a plurality of third light-emitting elements, each of the third light-emitting elements includes two sub-light-emitting elements provided opposite to each other along the first direction, each of the sub-light-emitting elements includes a third anode, a third light-emitting pattern, and a third cathode sequentially stacked along a direction away from the base, the third anode includes a seventh edge portion and an eighth edge portion provided opposite to each other along the second direction, and a third intermediate portion located between the seventh edge portion and the eighth edge portion, the orthogonal projection of the third intermediate portion on the base overlaps with the orthogonal projection of the third light-emitting pattern on the base, the orthogonal projection of the third intermediate portion on the base at least partially overlaps with the orthogonal projection of the corresponding data line pattern on the base, the orthogonal projection of the seventh edge portion on the base at least partially overlaps with the orthogonal projection of the corresponding power signal line pattern on the base. the orthogonal projection of the third intermediate portion on the base at least partially overlaps with the orthogonal projection of the corresponding data line pattern on the base, the orthogonal projection of the seventh edge portion on the base at least partially overlaps with the orthogonal projection of the corresponding power signal line pattern on the base.

[0033] Optionally, the first light-emitting element includes a red sub-pixel, the second light-emitting element includes a blue sub-pixel, and the third light-emitting element includes a green sub-pixel.

[0034] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel.

[0035] Based on the technical solution of the above display panel, a third aspect of the present invention is a method for manufacturing a display panel. ​​​​​That is, the display panel includes a plurality of sub-pixel areas arranged in an array, and the manufacturing method includes: fabricating a functional film layer including a power signal line layer, a data line layer, and a compensation function layer on a base, where the power signal line layer includes a power signal line pattern provided in each of the sub-pixel areas, the data line layer includes a data line pattern provided in each of the sub-pixel areas, the power signal line pattern includes a first portion extending along a first direction, the data line pattern extends along the first direction and the compensation function layer includes a compensation function pattern provided in at least one of the sub-pixel areas; fabricating, on a side of the functional film layer opposite to the base, a plurality of first light-emitting elements, each of the first light-emitting elements including a first anode, a first light-emitting pattern, and a first cathode sequentially stacked along a direction away from the base, where a positive projection of the first anode on the base has a first overlap region with a positive projection of the corresponding power signal line pattern on the base, a second overlap region with a positive projection of the corresponding data line pattern on the base, and a third overlap region with a positive projection of the corresponding compensation function pattern on the base, and the second overlap region is located between the first overlap region and the third overlap region; and providing a method for manufacturing a display panel including the above. The drawings described herein are for providing a further understanding of the present disclosure, constitute a part of the present disclosure, and the exemplary embodiments and descriptions thereof are for interpreting the present disclosure and do not constitute an improper limitation to the present disclosure.

[0036] ​

Brief Description of the Drawings

[0037]

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Embodiments for Carrying Out the Invention

[0038] To further explain the display panel, its manufacturing method, and the display device according to embodiments of the present disclosure, the following will be described in detail with reference to the specification drawings.

[0039] The structure of the AMOLED display panel includes a base, a plurality of sub-pixel driving circuits provided on the base, and a plurality of light-emitting elements provided on the side opposite to the base in the sub-pixel driving circuit. including an element, wherein the light-emitting element corresponds one-to-one with the sub-pixel driving circuit, and the sub-pixel driving circuit realizes the display function of the display panel by driving the light emission of the corresponding light-emitting element for this purpose.

[0040] In related technologies, as shown in FIG. 1, the sub-pixel driving circuit generally includes a plurality of thin-film transistors. FIG. 1 shows the specific layout of the seven thin-film transistors when the sub-pixel driving circuit includes seven thin-film transistors M1~ M7, and when laying out according to this method, the sub-pixel driving circuit includes an active layer as shown in FIG. 2, a first metal layer as shown in FIG. 3, a second metal layer as shown in FIG. 4, and a third metal layer as shown in FIG. 5. The active layer includes an active pattern (for example, the part within the dashed frame in FIG. 2) for forming the channel area of each thin-film transistor, and a doped active pattern (for example, the part outside the dashed frame in FIG. 2) that is coupled to the active pattern and has conductive performance. The first metal layer includes the gates of each thin-film transistor, a scanning signal line pattern GATE coupled to the gates, one electrode plate CE1 of the storage capacitor in the sub-pixel driving circuit, a reset signal line pattern RST, and a light emission control signal line pattern EM. The second metal layer includes an initialization signal line pattern VINT and the other electrode plate CE2 of the storage capacitor in the sub-pixel driving circuit. The third metal layer includes a data line pattern DATA, a power supply signal line pattern VDD, and several conductive connection parts (for example , symbols 341~343). It should be noted that, as shown in FIG. 1, when laying out the sub-pixel driving circuit, separate layers are involved. are involved. are involved. are involved. are involved. are involved. are involved. are involved. are involved.

[0041] It should be noted that, as shown in FIG. 1, when laying out the sub-pixel driving circuit, separate layers To realize the connection between the functional patterns provided in, several via holes (for example, reference numerals 381 to 388) may be provided.

[0042] As shown in FIGS. 6 and 7, the present disclosure provides a display panel, and the display panel includes a plurality of sub-pixel driving circuits. Exemplarily, each sub-pixel driving circuit includes seven thin film transistors and one capacitor. The display panel further includes an initialization signal line pattern VINT, a gate scanning line pattern GATE, a light emission control signal line pattern EM, a reset control signal line pattern R ST, a data line pattern DATA, and a power supply signal line pattern VDD. Each pattern corresponds one-to-one to the sub-pixel area of the display panel and is located therein.

[0043] The plurality of sub-pixel driving circuits are distributed to form an array and correspond one-to-one to the sub-pixel area of the display panel. The plurality of sub-pixel driving circuits can be partitioned into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The initialization signal line pattern VINT corresponding to the sub-pixel driving circuits located in the same row is sequentially electrically connected and formed as an integral structure. The gate scanning line pattern GATE corresponding to the sub-pixel driving circuits located in the same row is sequentially electrically connected and formed as an integral structure. The light emission control signal line pattern EM corresponding to the sub-pixel driving circuits located in the same row is sequentially electrically connected and formed as an integral structure. The reset control signal line pattern RST corresponding to the sub-pixel driving circuits located in the same row is sequentially electrically connected and formed as an integral structure. The data line pattern DATA corresponding to the sub-pixel driving circuits located in the same column is Sub-pixel driving circuits that are electrically connected in sequence, formed as an integrated structure, and located in the same column The power supply signal line pattern VDD corresponding thereto is electrically connected in sequence and formed as an integrated structure is formed

[0044] Exemplarily, each of the sub-pixel driving circuits in each row includes a plurality of sub-pixel driving circuits arranged in sequence along the X direction, and the initialization signal line pattern VINT, the gate scanning line pattern G ATE, the light emission control signal line pattern EM, and the reset control signal line pattern RST all extend along the X direction, and any of the plurality of sub-pixel driving circuits included in each row of sub-pixel driving circuits can be coupled to the corresponding initialization signal line pattern VINT, gate scanning line pattern G ATE, light emission control signal line pattern EM, and reset control signal line pattern RST respectively Each of the sub-pixel driving circuits in each column includes a plurality of sub-pixels driving circuits arranged in sequence along the Y direction, and the data line pattern DATA and the power supply signal line pattern VDD all extend along the Y direction, and any of the plurality of sub-pixel driving circuits included in each column of sub-pixel driving circuits can be coupled to the corresponding data line pattern DATA and power supply signal line pattern V DD respectively

[0045] As shown in FIG. 6, each sub-pixel driving circuit included in the display panel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 All of the transistors T7 can adopt P-type transistors.

[0046] The first transistor T1 has a double-gate structure, and the gate of the first transistor T1 The gate 201g is coupled to the corresponding gate scan line pattern GATE, and the source S1 of the first transistor T 1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0047] The second transistor T2 has a double-gate structure, and the gate 2 02g of the second transistor T2 is coupled to the corresponding first reset signal line pattern RST1, and the source S2 of the second transistor T2 is coupled to the corresponding first initialization signal line pattern VINT1, and the drain D2 of the second transistor T 2 is coupled to the gate 203g of the third transistor T3 .

[0048] The gate 204g of the fourth transistor T4 is coupled to the corresponding gate scan line pattern GAT E, the source S4 of the fourth transistor T4 is coupled to the corresponding data line pattern DAT A, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0049] The gate 205g of the fifth transistor T5 is coupled to the corresponding first emission control signal line pattern EM 1, the source S5 of the fifth transistor T5 is coupled to the corresponding power supply signal line pattern VD D, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0050] The gate 206g of the sixth transistor T6 is coupled to the corresponding second emission control signal line pattern EM is coupled to 2, and the source S6 of the sixth transistor T6 is the drain of the third transistor T3 is coupled to D3, and the drain D6 of the sixth transistor T6 is the first anode of the light-emitting element OLED is coupled to 501.

[0051] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2 is coupled to, the drain D7 of the seventh transistor T7 is the first anode of the light-emitting element OLED is coupled to 501, and the source S7 of the seventh transistor T7 is coupled to the corresponding second initialization signal line pattern VINT2.

[0052] Since the first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, the gate 203g of the third transistor T3 can be directly used as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power supply signal line pattern VDD pattern. is coupled to.

[0053] As shown in FIG. 7, since the first light emission control signal line pattern EM1 and the second light emission control signal line pattern EM2 can be used interchangeably as the same light emission control signal line pattern EM, through the light emission control signal line pattern the on / off states of the fifth transistor T5 and the sixth transistor T6 can be simultaneously controlled. is enabled.

[0054] As shown in FIG. 8, during the operation of the sub-pixel driving circuit with the structure of FIG. 7, in each operation cycle both include a first reset period P1, a write compensation period P2, a second reset period P3, and a light emission period P4. is included.

[0055] In the first reset period P1, the input from the first reset signal line pattern RST1 The first reset signal is at an active level, the second transistor T2 is turned on, and the first The initialization signal transmitted by the initialization signal line pattern VINT1 is input to the gate 203g of the third transistor T3. As a result, the gate-source voltage Vgs held by the third transistor T3 in the previous frame is cleared, and a reset for the gate 203g of the third transistor T3 is realized. The gate-source voltage Vgs held by the third transistor T3 in the previous frame is cleared, and a reset for the gate 203g of the third transistor T3 is realized. g is realized.

[0056] During the write compensation period P2, the first reset signal is at an inactive level, the second transistor T2 is turned off, the gate scan signal input from the gate scan line pattern GATE is at an active level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, a data signal is written to the data line pattern DATA, and is transmitted to the source S3 of the third transistor T3 via the fourth transistor T4. Thereby, due to the fact that the first transistor T1 and the fourth transistor T4 are turned on, the third transistor T3 is formed as a diode structure. The cooperation operation of the first transistor T1, the third transistor T3, and the fourth transistor T4 realizes threshold voltage compensation for the third transistor T3. When the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vdata + Vth, where Vdata represents the data signal and Vth represents the threshold voltage of the third transistor T3. 3 is formed as a diode structure, so that the cooperation operation of the first transistor T1, the third transistor T 3 and the fourth transistor T4 realizes threshold voltage compensation for the third transistor T3. When the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vdata + Vth, where Vdata represents the data signal and Vth represents the threshold voltage of the third transistor T3. When the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vdata + Vth, where Vdata represents the data signal and Vth represents the threshold voltage of the third transistor T3. can be controlled to finally reach Vdata + Vth, where Vdata represents the data signal and Vth represents the threshold voltage of the third transistor T3. signal, and Vth represents the threshold voltage of the third transistor T3.

[0057] During the second reset period P3, the gate scan signal is at an inactive level, and both the first transistor T1 and the fourth transistor T4 are turned off. The second reset signal line pattern Both the first transistor T1 and the fourth transistor T4 are turned off, and the second reset signal line pattern The second reset signal input from RST2 is at an active level, and the seventh transistor T7 is controlled to turn on, and the first initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the anode of the light-emitting element OLED, and the light-emitting element OLED is controlled not to emit light.

[0058] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line pattern EM is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to turn on, so that the power supply signal transmitted by the power supply signal line pattern VDD is input to the source S3 of the third transistor T3, and the gate 203g of the third transistor T3 is held at Vdata + Vth. As a result, the third transistor T3 turns on, and the gate-source voltage corresponding to the third transistor T3 becomes Vdata + Vth - Vdd, where Vd d is the potential corresponding to the power supply signal. The leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element OLED, driving the light emission of the corresponding light-emitting element OLED.

[0059] As shown in FIGS. 9 and 10, FIG. 9 shows a schematic diagram of the layout of three adjacent sub-pixel driving circuits. When manufacturing the above sub-pixel driving circuit, the layout of each film layer corresponding to the sub-pixel driving circuit is sequentially stacked and provided along the direction away from the base 70 as follows: an active layer (usually a low-temperature polysilicon layer), a gate insulating layer GI1, a first gate metal layer, a first interlayer insulating layer GI2, a second gate metal layer, a second interlayer insulating layer ILD, a first source-drain metal layer, and a planarization layer PLN in this order.

[0060] As shown in FIG. 11, the active layer forms the channel areas (e.g., 101pg to 107pg), source formation areas (e.g., 101 ps to 107ps), and drain formation areas (e.g., 101pd to 107pd) of each transistor in the sub-pixel driving circuit, and the active layers corresponding to the source formation area and the drain formation area have better conductive performance than the active layer corresponding to the channel area due to the doping effect. The active layer corresponding to the source formation area can be used as the source (e.g., S1 to S7) of each transistor, and the active layer corresponding to the drain formation area can be used as the drain (e.g., D1 to D7) of each transistor.

[0061] As shown in FIG. 12, the first gate metal layer forms the gates (e.g., 201g to 207g) of each transistor in the sub-pixel driving circuit, as well as the gate scanning signal line pattern GATE, emission control signal line pattern EM, first reset signal line pattern RST1 and second reset signal line pattern RST2 included in the display panel. Among them, the gate 203g of the third transistor T3 in each sub-pixel driving circuit is also used as the first electrode plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.

[0062] As shown in FIG. 13, the second gate metal layer includes the second electrode plate Cst2 of the storage capacitor Cst, the shield pattern 301 (for shielding the active layer between the two channel areas corresponding to the first transistor T1), and the first initialization signal line pattern VI included in the display panel. It is for forming NT1 and the second initialization signal line pattern VINT2.

[0063] As shown in FIGS. 9 and 14, the first source-drain metal layer is for forming data line patterns (e.g., DATA1, DATA2, DATA3) and power supply signal lines (e.g., VDD1, VDD2, VDD3) included in the display panel.

[0064] More specifically, continuing to refer to FIGS. 9, 11, and 12, the gate 201g of the first transistor T1 covers the first channel area 101pg, the source S1 of the first transistor T1 is located in the first source formation area 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation area 101pd.

[0065] The gate 202g of the second transistor T2 covers the second channel area 102pg, the source S2 of the second transistor T2 is located in the second source formation area 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation area 102pd.

[0066] The gate 203g of the third transistor T3 covers the third channel area 103pg, the source S3 of the third transistor T3 is located in the third source formation area 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation area 103pd.

[0067] The gate 204g of the fourth transistor T4 covers the fourth channel area 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation area 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation area 104pd. ​

[0068] The gate 205g of the fifth transistor T5 covers the fifth channel area 105pg, and the source S5 of the fifth transistor T5 is located in the fifth source formation area 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation area 105pd.

[0069] The gate 206g of the sixth transistor T6 covers the sixth channel area 106pg, and the source S6 of the sixth transistor T6 is located in the sixth source formation area 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation area 106pd.

[0070] The gate 207g of the seventh transistor T7 covers the seventh channel area 107pg, and the source S7 of the seventh transistor T7 is located in the seventh source formation area 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation area 107pd.

[0071] The gate 203g of the third transistor T3 is also used as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power supply signal line VDD.

[0072] Continuing to refer to FIG. 9, FIG. 9 shows a red light emitting element and a blue light emitting element, and anodes included in at least one of the red light emitting element and the blue light emitting element can simultaneously cover a power supply signal line pattern and a data line pattern. Exemplarily, the anode pattern 901 included in the blue light emitting element simultaneously covers the power supply signal line pattern VDD1 and the data line pattern DATA1, and the anode pattern 902 included in the red light emitting element is a power supply signal line and a data line pattern. It simultaneously covers the gate line pattern VDD2 and the data line pattern DATA2, and the power signal line pattern and the data line pattern are both complete strip-shaped patterns extending along the vertical direction (for example, the Y direction). Therefore, according to the above layout method, the anode pattern has a smaller step generated in the vertical extension direction, which is beneficial to improving the color shift phenomenon occurring in the light-emitting element. It is beneficial.

[0073] According to the above display panel, the color shift phenomenon occurring in the light-emitting element is improved to a certain extent. However, as can be seen from FIG. 10, since a step may occur in the horizontal extension direction (for example, the X direction) between the power signal line pattern VDD and the data line pattern DATA, the anode pattern 902 formed later will be inclined in the horizontal extension direction. As a result, the organic light-emitting material layer 802 formed on the anode pattern 902 will also be inclined. Consequently, there is still a color shift phenomenon during the display by the display panel.

[0074] Based on the existence of the above problems, as shown in FIGS. 15 and 17, an embodiment of the present disclosure is a display panel including a base 50, a functional film layer provided on the base 50, and a plurality of first light-emitting elements provided on the side of the functional film layer opposite to the base 50, and further including a plurality of sub-pixel areas arranged in an array The functional film layer includes a power signal line layer, a data line layer, and a compensation functional layer. The power signal line layer includes power signal line patterns (for example, VDD1 and VDD2 in FIG. 15) provided in each of the sub-pixel areas. The data line layer includes data line patterns (for example, DATA1 and DATA2 in FIG. 15) provided in each of the sub-pixel areas. The power The signal line pattern includes a first portion extending along a first direction, and the data line pattern extends along the first direction, and the compensation function layer includes a compensation function pattern 401 provided in at least one of the sub-pixel areas . Each of the first light-emitting elements includes a first anode 501, a first light-emitting pattern 601, and a first cathode, which are sequentially stacked along a direction away from the base 50 . The orthographic projection of the first anode 501 on the base 50 has a first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50, and the orthographic projection of the first anode 501 on the base 50 has a second overlap region F2 with the orthographic projection of the corresponding data line pattern on the base 50, and the orthographic projection of the first anode 501 on the base 50 has a third overlap region F3 with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3, providing a display panel . . .

[0075] Specifically, the plurality of sub-pixel areas arranged in an array can be partitioned into a sub-pixel area column extending along a first direction and a sub-pixel area row extending along a second direction. The sub-pixel area column includes a plurality of sub-pixel areas arranged along the first direction , and the sub-pixel area row includes a plurality of sub-pixel areas arranged along the second direction . The first direction and the second direction intersect. Exemplarily, the first direction includes the Y direction , and the second direction includes the X direction.

[0076] The power signal line layer includes a power signal line pattern provided in each sub-pixel area. The power signal line pattern may be selectively formed in a grid shape, and the grid-shaped power signal line pattern includes a first portion extending along the first direction. The power signal line pattern corresponds one-to-one with the sub-pixel area, and the power signal line pattern is located in the corresponding sub-pixel area, and each of the power signal line patterns VDD corresponding to the sub-pixel areas located in the same column is electrically connected in sequence and formed as an integral structure.

[0077] The data line layer includes data line patterns provided in each of the sub-pixel areas, and the data line patterns extend along the first direction. The data line patterns correspond one-to-one with the sub-pixel area, and the data line patterns are located in the corresponding sub-pixel areas, and each of the data line patterns DATA corresponding to the sub-pixel areas located in the same column is electrically connected in sequence and formed as an integral structure.

[0078] The display panel further includes a plurality of first light-emitting elements located on the side of the functional film layer opposite to the base 50, and the first light-emitting elements are sequentially stacked along the direction away from the base 50 and include a first anode 501, a first light-emitting pattern 601, and a first cathode. When the display panel operates, a driving signal is supplied to the first anode 501, and a common signal is supplied to the first cathode, so that an electric field is generated between the first anode 501 and the first cathode. As a result, the first light-emitting pattern 601 is controlled to emit light of a corresponding color. Exemplarily, the first light-emitting element includes a red light-emitting element and can emit red light .

[0079] The compensation function layer includes a compensation function pattern 401 provided in at least one of the sub-pixel areas. Exemplarily, the compensation function pattern 401 corresponds to the first light-emitting element on a one-to-one basis. When laying out the display panel, first form a functional film layer on the base 50, and then fabricate a first light-emitting element on the side of the functional film layer opposite to the base 50. When laying out the functional film layer, the power signal line pattern and the data line pattern may be alternately arranged along the second direction. The compensation function pattern 401 may be provided near the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the base 50 has a first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50, and has a second overlap region F2 with the orthographic projection of the corresponding data line pattern on the base 50, and has a third overlap region F3 with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3. When laying out the display panel, first form a functional film layer on the base 50, and then fabricate a first light-emitting element on the side of the functional film layer opposite to the base 50. When laying out the functional film layer, the power signal line pattern and the data line pattern may be alternately arranged along the second direction. The compensation function pattern 401 may be provided near the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the base 50 has a first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50, and has a second overlap region F2 with the orthographic projection of the corresponding data line pattern on the base 50, and has a third overlap region F3 with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3. When laying out the display panel, first form a functional film layer on the base 50, and then fabricate a first light-emitting element on the side of the functional film layer opposite to the base 50. When laying out the functional film layer, the power signal line pattern and the data line pattern may be alternately arranged along the second direction. The compensation function pattern 401 may be provided near the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the base 50 has a first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50, and has a second overlap region F2 with the orthographic projection of the corresponding data line pattern on the base 50, and has a third overlap region F3 with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3. When laying out the functional film layer, the power signal line pattern and the data line pattern may be alternately arranged along the second direction. The compensation function pattern 401 may be provided near the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the base 50 has a first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50, and has a second overlap region F2 with the orthographic projection of the corresponding data line pattern on the base 50, and has a third overlap region F3 with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3. The second overlap region F2 is located between the first overlap region F1 and the third overlap region F3.

[0080] As can be seen from the specific structure of the above display panel, in the display panel according to the embodiments of the present disclosure, since the compensation function pattern 401 can compensate for the step generated when the power signal line pattern and the data line pattern are below the first anode 501, in the display panel, the first anode 501 included in the first light-emitting element partially corresponds to the corresponding power signal line pattern, partially corresponds to the corresponding data line pattern, and at least partially corresponds to the corresponding compensation function pattern 401. ​​When the compensation function pattern 401 is simultaneously covered, the first anode 501 can have a high flatness, and as a result, the color shift phenomenon that occurs during display by the display panel is effectively reduced. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2.

[0081] As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2. As shown in FIG. 25, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The second direction intersects the first direction. The orthographic projection of the first edge portion 501a1 on the base 50 includes the first overlap region F1, the orthographic projection of the second edge portion 501a2 on the base 50 includes the third overlap region F3, and the orthographic projection of the first intermediate portion 501a5 on the base 50 includes the second overlap region F2.

[0082] Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction. Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction. Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction. Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction. Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction. Specifically, the specific structure of the first anode 501 is diverse. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are provided to face each other along a second direction, and a first intermediate portion 501a5 that is located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2, and the intermediate portion may all extend along the first direction.

[0083] The orthographic projection of the first edge portion 501a1 on the base 50 forms the first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50. The orthographic projection of the first edge portion 501a1 on the base 50 forms the first overlap region F1 with the orthographic projection of the corresponding power signal line pattern on the base 50. ​It is possible that the orthographic projection of the first intermediate portion 501a5 on the base 50 does not overlap with the orthographic projection of the corresponding data line pattern on the base 50, and the second overlap region F2 can be formed. The orthographic projection of the second edge portion 501a2 on the base 50 does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the base 50, and the third overlap region F3 can be formed. In the display panel according to the above embodiment, the first edge portion 501a1 and the second edge portion 501a2 provided opposite to each other along the second direction in the first anode 501 can respectively cover the corresponding power signal line pattern and the corresponding compensation function pattern 401.

[0084] Moreover, the intermediate portion between the first edge portion 501a1 and the second edge portion 501a2 in the first anode 501 can cover the corresponding data line pattern. Therefore, the power signal line pattern, the data signal line pattern, and the compensation function pattern 401 covered by the first anode 501 can be uniformly distributed in the region covered by the first anode 501, and as a result, the flatness of the first anode 501 is more preferably guaranteed. As shown in FIGS. 15 and 25, in some embodiments, the orthographic projection of the first edge portion 501a1 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50, the orthographic projection of the second edge portion 501a2 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50, and the orthographic projection of the first intermediate portion 501a5 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50. In the region covered by the first anode 501, the power signal line pattern, the data signal line pattern, and the compensation function pattern 401 can be

[0085] uniformly distributed, and as a result, the flatness of the first anode 501 is more preferably guaranteed. As shown in FIGS. 15 and 25, in some embodiments, the orthographic projection of the first edge portion 501a1 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50, the orthographic projection of the second edge portion 501a2 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50, and the orthographic projection of the first intermediate portion 501a5 on the base 50 does not overlap with the orthographic projection of the first light emission pattern 601 on the base 50. Overlaps with the orthographic projection of the pattern 601 on the base 50.

[0086] Specifically, on the surface of the first anode 501 opposite to the base 50, when forming the first light-emitting pattern 601, the specific layout method of the first light-emitting pattern 601 is diverse. Exemplarily, the orthographic projection of the first light-emitting pattern 601 on the base 50 is located between the orthographic projection of the first edge pattern on the base 50 and the orthographic projection of the second edge pattern on the base 50, and overlaps with the orthographic projection of the first intermediate portion 501a5 on the base 50. According to this method, when laying out the first light-emitting pattern 601, the first light-emitting pattern 601 can be located on the surface of the intermediate portion of the first anode 501. The surface of the intermediate portion of the first anode 501 has a higher flatness, so it is more advantageous for improving the flatness of the first light-emitting pattern 601. As shown in FIG. 25, in some embodiments, the first intermediate portion 501a5 is a centrally symmetric pattern, and the orthographic projection of the first intermediate portion 501a5 on the base 50 overlaps with the orthographic projection of the first light-emitting pattern 601 on the base 50.

[0087] Specifically, the first intermediate portion 501a5 of the first anode 501 may optionally be a centrally symmetric pattern. Exemplarily, the orthographic projection of the first intermediate portion 501a5 on the base 50 is a hexagon. In this case, the orthographic projection of the first light-emitting pattern 601 on the base 50 overlaps with the orthographic projection of the first intermediate portion 501a5 on the base 50.

[0088] ​​​​​​​When configured in this way, the first light-emitting pattern 601 also becomes a centrosymmetric pattern, and according to the first intermediate portion 501a5 and the first light-emitting pattern 601, it is advantageous in terms of the flatness and light emission uniformity of the first light-emitting pattern 601.

[0089] In some embodiments, the ratio of the sum of the area of the first overlap region F1 and the area of the second overlap region F2 to the area of the third overlap region F3 is close to 2:1. Specifically, when laying out the first anode 501, the power signal line pattern, the data line pattern

[0090] and the compensation function pattern 401, in the direction perpendicular to the base 50, by controlling the degree of overlap of the first anode 501 with each of the power signal line pattern, the data line pattern and the compensation function pattern 401, the flatness of the first anode 501 may be adjusted. Exemplarily, the ratio of the sum of the area of the first overlap region F1 and the area of the second overlap region F2 to the area of the third overlap region F3 may be configured to be close to 2:1. According to this configuration method, the first overlap area, the second overlap area and the third overlap area become close, that is, the areas of the power signal line pattern, the data line pattern and the compensation function pattern 401 covered by the first anode 501 become close, so it is advantageous for improving the flatness of the first anode 501. As shown in FIG. 15, in some embodiments, the functional film layer is a gate scanning line layer, and the first overlap area, the second overlap area and the third overlap area become close, that is, the areas of the power signal line pattern, the data line pattern and the compensation function pattern 401 covered by the first anode 501 become close, so it is advantageous for improving the flatness of the first anode 501. the areas of the power signal line pattern, the data line pattern and the compensation function pattern 401 covered by the first anode 501 become close, so it is advantageous for improving the flatness of the first anode 501.

[0091] As shown in FIG. 15, in some embodiments, the functional film layer is a gate scanning line layer, Further including an initialization signal line layer, a reset signal line layer, and a light emission control signal line layer, The gate scanning line layer includes a gate scanning line pattern GA provided in each of the sub-pixel areas TE, the initialization signal line layer includes an initialization signal line pattern VINT provided in each of the sub-pixel areas The reset signal line layer includes a reset signal line pattern RST provided in each of the sub-pixel areas The light emission control signal line layer includes a light emission control signal line pattern EM provided in each of the sub-pixel areas The gate scanning line pattern GATE, the above-mentioned initialization signal line pattern VINT, the reset signal line pattern RST, and the light emission control Signal line pattern EM all extend along a second direction, and the second direction intersects with the first direction Specifically, the gate scanning line layer includes a gate scanning line pattern GATE provided in each of the sub-pixel areas The gate scanning line pattern GATE extends along the second direction, and the gate scanning line patterns GATE corresponding to each sub-pixel area located in the same row

[0092] Are sequentially electrically connected and formed as an integral structure. The initialization signal line layer includes an initialization signal line pattern VINT provided in each of the sub-pixel areas The initialization signal line layer extends along the second direction, and the initialization signal line patterns VINT corresponding to each sub-pixel area located in the same row Are sequentially electrically connected and formed as an integral structure.

[0093] The reset signal line layer includes a reset signal line pattern RST provided in each of the sub-pixel areas The reset signal line pattern RST extends along the second direction, and the same The reset signal line patterns RST corresponding to each sub-pixel area located in the same row are sequentially electrically connected And formed as an integral structure.

[0094] The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas RST, the reset signal line pattern RST extends along the second direction, and the same The reset signal line pattern RST corresponding to each sub-pixel area located in the j row is sequentially electrically connected and formed as an integral structure.

[0095] The light emission control signal line layer includes a light emission control signal line pattern EM provided in each of the sub-pixel areas. The light emission control signal line pattern EM extends along the second direction, and the light emission control signal line patterns EM corresponding to the sub-pixel areas located in the same row are sequentially electrically connected and formed as an integral structure.

[0096] As shown in FIGS. 15 and 25, in some embodiments, the first anode 501 further includes a third edge portion 501a3 and a fourth edge portion 501a4 provided opposite to each other along the first direction. The first intermediate portion 501a5 is located between the third edge portion 501 a3 and the fourth edge portion 501a4. The third edge portion 501a3 is respectively coupled to the first edge portion 501a1 and the second edge portion 501a2, and the fourth edge portion 501a4 is respectively coupled to the first edge portion 501a1 and the second edge portion 501a2. The positive projection of the first intermediate portion 501a5 on the base 50, the positive projection of the corresponding gate scan line pattern on the base 50, and the positive projection of the corresponding reset signal line pattern on the base 50 include a sixth overlap region. Specifically, the first anode 501 further includes a third

[0097] edge portion 501a3 and a fourth edge portion 501a4 provided opposite to each other along the first direction. The first intermediate portion 50 1a5 is located between the third edge portion 501a3 and the fourth edge portion 501a4. ​ The first edge portion 501a1, the second edge portion 501a2, and the third edge portion 5 01a3 and the fourth edge portion 501a4 together surround the intermediate portion.

[0098] When the first anode 501 is laid out, the base of the third edge portion 501a3 is 15. The orthogonal projection on the substrate 50 and the corresponding initialization signal line pattern VINT (for example, The orthogonal projection of the first initialization signal line pattern VINT1 on the base 50 includes the following: Four overlapping regions are formed, on the base 50 of the fourth edge portion 501a4. and a corresponding orthogonal projection of the light emission control signal line pattern EM on the base 50. A fifth overlap region is formed in the first intermediate portion 501a5. 0 and the corresponding gate scanning line pattern GATE on the base 50. Orthogonal projection, and the corresponding reset signal line pattern RST (for example, the first The reset signal line pattern RST1) is projected onto the base 50 in a sixth overlay. According to this layout method, a wrap region may be formed. The fourth overlap region and the fifth overlap region face each other along the direction. The sixth overlapping region is provided by overlapping the fourth overlapping region and the fifth overlapping region. The first anode 501 is covered by the first anode 501 because it is located between the first anode 501 and the burlap region. The initialization signal line pattern VINT, the light emission control signal line pattern EM, the gate scanning line pattern The turn GATE and the reset signal line pattern RST are connected to the first anode 501. This allows the surface area to be uniformly distributed, thereby reducing the flatness of the first anode 501. is more suitably guaranteed.

[0099] As shown in FIG. 25, in some embodiments, the first anode 501 has a main body portion 501a and a via connection portion 501b. The main body portion 501a has the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3 , the fourth edge portion 501a4 and the first intermediate portion 501a5. The main body portion 501a has a centrosymmetric pattern.

[0100] Specifically, the first anode 501 includes a main body portion 501a and a via hole connection portion 501b that are coupled to each other. The surface of the main body portion 501a on the side opposite to the base 50 is for forming the first light emission pattern 601. The via connection portion 501 b is coupled to the sub-pixel driving circuit in the display panel through vias and is for receiving the driving signal supplied from the sub-pixel driving circuit.

[0101] As described above, by configuring the first anode 501 to include the main body portion 501a and the via hole connection portion 501b, it is possible to avoid the formation of vias in the portion for forming the first light emission pattern 601 in the first anode 501. Therefore, the light emission effect of the first light emitting element is guaranteed. Also, by configuring the main body portion 501a to include the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3 , the fourth edge portion 501a4 and the first intermediate portion 501a5, and by configuring the main body portion 501a to have a centrosymmetric pattern, the power supply signal line pattern VDD (for example, VDD1 in FIG. 15), the data line pattern D is configured as follows. At the same time, by configuring the main body portion 501a to be a centrosymmetric pattern, the above-mentioned power supply signal line pattern VDD (for example, VDD1 in FIG. 15), the data line pattern D ATA (e.g., DATA1 in FIG. 15), the gate scanning line pattern GATE, and the reset signal line pattern RST (e.g., the first reset signal line pattern RST1 in FIG. 15 ), the emission control signal line pattern EM, and the initialization signal line pattern VINT (e.g., the first initialization signal line pattern VINT1 in FIG. 15 ), the portion covered by the first anode 501 in these patterns can be uniformly distributed below the first anode 501, which is advantageous for improving the flatness of the first anode 501.

[0102] As shown in FIGS. 12, 13, 16, 17, and 18, in some embodiments , the display panel includes a first metal layer, a second metal layer, and a third metal layer. The gate scanning line layer, the reset signal line layer, and the emission control signal line layer are located in the first metal layer. The initialization signal line layer is located in the second metal layer. The data line layer, the power supply signal line layer, and the compensation function layer are located in the third metal layer. The functional film layer further includes a first insulating layer (e.g., GI2 in FIG. 1 7) and a second insulating layer (e.g., ILD in FIG. 17). The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer.

[0103] Specifically, when laying out the display panel, functional layer patterns extending along the same direction may be laid out in the same layer. Exemplarily, the gate scanning line layer, the reset signal line layer, and the emission control signal line layer are provided in the same layer and jointly formed as the first metal layer, and the data line layer, the power supply signal line layer, and the compensation function layer are provided in the same layer and jointly formed as the third metal layer. ​

[0104] Since the dimensions of the display panel are fixed, the layout space in the same layer is limited. If the functional layer patterns extending along the same direction cannot be laid out in the same layer, a part of the functional layer patterns may be laid out in other film layers. Exemplarily, the initialization signal line layer is formed as the second metal layer, and the second metal layer and the first metal layer are provided in separate layers. Do it like this.

[0105] It should be noted that when manufacturing each metal layer, an insulating layer may be formed between adjacent metal layers to avoid the occurrence of a short circuit between adjacent metal layers. Exemplarily, the functional film layer further includes a first insulating layer and a second insulating layer. The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is configured to be located between the second metal layer and the third metal layer. layer. Configure it like this.

[0106] In the display panel according to the above embodiment, by laying out the functional layer patterns extending along the same direction in the same layer and laying out an insulating layer between adjacent conductive film layers, the occurrence of a short circuit between each functional pattern included in the display panel is avoided, while the layout space in the display panel is maximally utilized, which is advantageous for the development of the thinning of the display panel. panel. While avoiding the occurrence of a short circuit between each functional pattern included in the display panel, the layout space in the display panel is maximally utilized, which is advantageous for the development of the thinning of the display panel. layout space in the display panel is maximally utilized, which is advantageous for the development of the thinning of the display panel.

[0107] As shown in FIG. 15, in some embodiments, the compensation functional pattern 401 is made of a conductive material and is coupled to the initialization signal line pattern VINT (for example, the first initialization signal line pattern VINT1 in FIG. 15). Specifically, the material of the compensation functional pattern 401 can be set according to actual needs.

[0108] Specifically, the material of the compensation functional pattern 401 can be set according to actual needs. Exemplarily, it may be a conductive material or an insulating material. When manufacturing the compensation function pattern 4 01, the compensation function pattern 401 may be coupled to a fixed signal output terminal so that the compensation function pattern 401 has a fixed potential. In this way, it is possible to avoid the stability of the display panel operation being affected due to the compensation function pattern 401 being in a floating state.

[0109] Furthermore, the initialization signal line pattern VINT may also be used as a fixed potential output terminal. Since the initialization signal line pattern VINT is for transmitting an initialization signal having a fixed potential, by coupling the compensation function pattern 401 to the initialization signal line pattern VINT, the compensation function pattern 401 can be made to have the same fixed potential as the initialization signal.

[0110] As described above, by using the initialization signal line pattern VINT as the fixed potential output terminal, it is possible to avoid separately manufacturing a fixed potential output terminal that is exclusively used for supplying a fixed potential to the compensation function pattern 401 on the display substrate. The layout space of the functional film layer is effectively improved, and moreover, the voltage of the initialization signal line is enhanced. As a result, the voltage of the initialization signal transmitted through the initialization signal line becomes more stable, which is advantageous for realizing the stable operating performance of the sub-pixel driving circuit. It should be noted that, referring to FIG. 5 continuously, when the initialization signal line pattern VINT is used as the fixed potential output terminal, the orthographic projection of the compensation function pattern 401 on the base 50 and the orthographic projection of the initialization signal line pattern VINT on the base 50

[0111] It should be noted that, referring to FIG. 5 continuously, when the initialization signal line pattern VINT is used as the above-mentioned fixed potential output terminal, the orthographic projection of the compensation function pattern 401 on the base 50 and the orthographic projection of the initialization signal line pattern VINT on the base 50 , it may be configured to have an overlap region. Thus, if a via hole is provided in the overlap region , the connection between the compensation function pattern 401 and the initialization signal line pattern VI NT can be realized.

[0112] In some embodiments, the compensation function pattern 401 is provided in the same layer as the data line pattern D ATA.

[0113] Specifically, when laying out the compensation function pattern 401, the compensation function pattern 40 1 may be provided in the same layer as the data line pattern DATA. According to this layout method , it is possible to avoid one layer being monopolized by the compensation function pattern 401, which is advantageous for thinning the display panel.

[0114] Further, the compensation function pattern 401 may be provided with the same material as the data line pattern DATA. According to this configuration method , the compensation function pattern 401 can be formed in the same patterning process as the data line pattern DATA. Therefore, the manufacturing flow of the display panel is effectively simplified, and the manufacturing cost of the display panel is saved.

[0115] In some embodiments, the display panel further includes a plurality of sub-pixel driving circuits. Among the plurality of sub-pixel driving circuits, the first part of the sub-pixel driving circuits corresponds one-to-one with the first light-emitting element . The first sub-pixel driving circuit of the first part is for driving the light emission of the corresponding first light-emitting element . The sub-pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, and a storage capacitor.

[0116] The gate of the first transistor is coupled to the corresponding gate scan line pattern GATE and the first electrode of the first transistor is coupled to the second electrode of the drive transistor The second electrode of the first transistor is coupled to the gate of the drive transistor, and the gate of the second transistor is coupled to the corresponding reset signal line pattern RST, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern VINT and the second electrode of the second transistor is coupled to the gate of the drive transistor, the gate of the fourth transistor is coupled to the corresponding gate scan line pattern GATE and the first electrode of the fourth transistor is coupled to the corresponding data line pattern DATA The second electrode of the fourth transistor is coupled to the first electrode of the drive transistor and the first electrode of the drive transistor is coupled to the corresponding power supply signal line pattern VDD The second electrode of the drive transistor is coupled to the corresponding first light emitting element, and the storage The first plate of the capacitor is coupled to the gate of the drive transistor, and the second plate of the storage capacitor is coupled to the corresponding power supply signal line pattern VDD.

[0117] Exemplarily, the functional film layer includes n + 1 power supply signal line patterns VDD, n + 1 data line patterns DATA, n + 1 gate scan line patterns GATE, n + 1 initialization signal line patterns VINT, n + 1 reset signal line patterns RST, and n + 1 emission control signal line patterns EM. The display panel includes a plurality of sub-pixel drive circuits corresponding one-to-one to the sub-pixel areas and the plurality of sub-pixel drive circuits include n + 1 rows of sub-pixels It can be partitioned into a pixel driving circuit and can also be partitioned into sub-pixel driving circuits of n + 1 columns. The n + 1 power signal line patterns VDD correspond one-to-one with the n + 1 columns of sub-pixel driving circuits. The n + 1 data line patterns DATA correspond one-to-one with the n + 1 columns of sub-pixel driving circuits. The n + 1 gate scanning line patterns GATE correspond one-to-one with the n + 1 rows of sub-pixel driving circuits. The n + 1 initialization signal line patterns VINT correspond one-to-one with the n + 1 rows of sub-pixel driving circuits. The n + 1 reset signal line patterns RST correspond one-to-one with the n + 1 rows of sub-pixel driving circuits. The n + 1 emission control signal line patterns EM correspond one-to-one with the n + 1 rows of sub-pixel driving circuits. Based on the above exemplary structure, the specific structure of the sub-pixel driving circuit located in the nth row and nth column and its connection method with various signal line patterns will be described in detail below.

[0118] As shown in FIGS. 7 and 15, the sub-pixel driving circuit includes a driving transistor (i.e., the third transistor T3, hereinafter referred to as the third transistor T3), a first transistor T1, a second transistor T2, a fourth transistor T4, and a storage capacitor Cst. The first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors. Taking it as an example, its specific structure and connection method with various signal line patterns will be described in detail.

[0119] As shown in FIGS. 7 and 15, the sub-pixel driving circuit includes a driving transistor (i.e., the third transistor T3, hereinafter referred to as the third transistor T3), a first transistor T1, a second transistor T2, a fourth transistor T4, and a storage capacitor Cst. The first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors. The gate 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE. The first electrode (i.e., the source S1) of the first transistor T1 is coupled to the second electrode (i.e., the drain D3) of the third transistor T3. The As shown in FIGS. 7 and 15, the sub-pixel driving circuit includes a driving transistor (i.e., the third transistor T3, hereinafter referred to as the third transistor T3), a first transistor T1, a second transistor T2, a fourth transistor T4, and a storage capacitor Cst. The first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors. The gate 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE. The first electrode (i.e., the source S1) of the first transistor T1 is coupled to the second electrode (i.e., the drain D3) of the third transistor T3. The first The first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors.

[0120] The gate 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE. The first electrode (i.e., the source S1) of the first transistor T1 is coupled to the second electrode (i.e., the drain D3) of the third transistor T3. The The gate 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE. The first electrode (i.e., the source S1) of the first transistor T1 is coupled to the second electrode (i.e., the drain D3) of the third transistor T3. The The gate 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE. The first electrode (i.e., the source S1) of the first transistor T1 is coupled to the second electrode (i.e., the drain D3) of the third transistor T3. The first The two electrodes (i.e., drain D1) are coupled to the gate 203g of the third transistor T3 .

[0121] The gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RS T1, the first electrode (i.e., source S2) of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and the second electrode (i.e ., drain D2) of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0122] The gate 204g of the fourth transistor T4 is coupled to the gate scan line pattern GATE , the first electrode (i.e., source S4) of the fourth transistor T4 is coupled to the data line pa ttern DATA, and the second electrode (i.e., drain D4) of the fourth transistor T4 is coupled to the first electrode (i.e., source S3) of the third transistor T3.

[0123] The first electrode (i.e., source S3) of the third transistor T3 is coupled to the power supply signal line pattern VDD, and the second electrode (i.e., drain D3) of the third transistor T3 is coupled to the corresponding light emitting element OLED.

[0124] The first plate Cst1 of the storage capacitor Cst is coupled to the gate 203 g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power supply signal line pattern VD D.

[0125] In some embodiments, the functional film layer further includes a light emission control signal line pattern and a second reset signal line pattern RST2, and the sub-pixel driving circuit includes a fifth transistor, a first Further includes a sixth transistor and a seventh transistor, and the gate of the fifth transistor is the front Coupled to the light emission control signal line pattern, the first electrode of the fifth transistor is the power supply letter Coupled to the number line pattern VDD, the second electrode of the fifth transistor is the drive transistor Coupled to the first electrode of the transistor, the gate of the sixth transistor is the light emission control signal line pattern Coupled to the first electrode of the sixth transistor, the second electrode of the sixth transistor is coupled to the corresponding light emitting element, and the first electrode of the sixth transistor is the second electrode of the drive transistor Coupled to the second electrode of the drive transistor, the second electrode of the sixth transistor is coupled to the corresponding light emitting element, and the gate of the seventh transistor is coupled to the second reset signal line pattern Coupled to the second reset signal line pattern, the first electrode of the seventh transistor is coupled to the initialization signal line, and the second electrode of the seventh transistor Is coupled to the second electrode of the sixth transistor. Is coupled to the second electrode of the sixth transistor.

[0126] Specifically, continuing with the sub-pixel driving circuit located in the nth row and nth column as an example, as shown in FIGS. 7 and As shown in FIG. 15, the gate 205g of the fifth transistor T5 is the light emission control signal Coupled to the line pattern EM, the first electrode (i.e., source S5) of the fifth transistor T5 is Coupled to the power supply signal line pattern VDD, the second electrode (i.e., Drain D5) of the fifth transistor T5 is the first electrode of the drive transistor (i.e., the third transistor T3) That is, it is coupled to the source S3.

[0127] The gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM Coupled to the first electrode (i.e., source S6) of the sixth transistor T6, the first electrode of the sixth transistor T6 is the drive transistor Is coupled to the second electrode (i.e., drain D3) of the third transistor T3, and the first electrode of the sixth transistor T6 is the second electrode of the drive transistor The second electrode (i.e., drain D6) of the six-transistor T6 is connected to the corresponding light-emitting element OLED. combined, The gate 207g of the seventh transistor T7 is connected to the second reset signal line pattern RST2 (exemplarily, as the second reset signal line pattern RST2, it may be the reset signal line pattern RST corresponding to the sub-pixel driving circuit of the n + 1th row). sub-pixel driving circuit of the n + 1th row). The first electrode (i.e., source S7) of the seventh transistor T7 is connected to the second initialization signal line pattern VINT2 (exemplarily, as the second initialization signal line pattern VINT2, it may be the initialization signal line pattern VINT corresponding to the sub-pixel driving circuit of the n + 1th row). The second electrode (i.e., drain D7) of the seventh transistor T7 is connected to the second electrode (i.e., drain D6) of the sixth transistor T6. sub-pixel driving circuit of the n + 1th row). connected, In the display panel according to the above embodiment, the sub-pixel driving circuit is configured to include the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, so that the sub-pixel driving circuit can drive the light emission of the corresponding light-emitting element OLED only in the light-emitting stage. The occurrence of abnormal light emission in the light-emitting element OLED is avoided, so that the display quality of the display panel is more preferably improved.

[0128] In the display panel according to the above embodiment, the sub-pixel driving circuit is configured to include the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, so that the sub-pixel driving circuit can drive the light emission of the corresponding light-emitting element OLED only in the light-emitting stage. The occurrence of abnormal light emission in the light-emitting element OLED is avoided, so that the display quality of the display panel is more preferably improved. The occurrence of abnormal light emission in the light-emitting element OLED is avoided, so that the display quality of the display panel is more preferably improved. The occurrence of abnormal light emission in the light-emitting element OLED is avoided, so that the display quality of the display panel is more preferably improved. The display quality of the display panel is more preferably improved.

[0129] As shown in FIGS. 21 and 22, in some embodiments, the sub-pixel driving circuit further includes a first conductive connection portion 701. The second electrode (i.e., drain D1) of the first transistor T1 is connected to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) through the first conductive connection portion 701. The display panel further includes a third metal layer. The second electrode (i.e., drain D1) of the first transistor T1 is connected to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) through the first conductive connection portion 701. The display panel further includes a third metal layer. The second electrode (i.e., drain D1) of the first transistor T1 is connected to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) through the first conductive connection portion 701. The display panel further includes a third metal layer. The second electrode (i.e., drain D1) of the first transistor T1 is connected to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) through the first conductive connection portion 701. The display panel further includes a third metal layer. is included, and the first conductive connection portion 701 is located in the third metal layer, and the orthographic projection of the first conductive connection portion included in the sub-pixel driving circuit of the first part on the base does not overlap with the orthographic projection of the corresponding first anode 501 on the base. Specifically, the compensation function pattern 401 is provided between the data line pattern (for example, DATA1) and the first conductive connection portion included in the sub-pixel driving circuit of the first part, and the data line pattern can be located directly below the first anode in the sub-pixel driving circuit of the first part. In the display panel with the above structure, the compensation function pattern 401 can separate the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) from the data line pattern (for example, DATA1), so that crosstalk is more preferably avoided from occurring in the gate potential of the driving transistor due to signal changes on the data line pattern. Moreover, according to the display panel with the above structure, the occurrence of a short circuit between the first conductive connection portion 701 and the compensation function pattern 401 is also avoided.

[0130] Furthermore, as shown in FIGS. 21 and 23, the compensation function pattern 401 is coupled to the initialization signal line pattern (for example, VINT1) so that a fixed potential can be provided to the compensation function pattern 401, thereby further avoiding crosstalk from occurring in the gate potential of the driving transistor due to signal changes on the data line pattern. Also, as described above, by positioning the first conductive connection portion 701 in the third metal layer, the first conductive connection portion 701 forms a single pattern with other patterns included in the third metal layer. can be located, and in the display panel of the above structure, due to the compensation function pattern 401, the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) and the data line pattern (for example, DATA1) can be separated, so that crosstalk occurring in the gate potential of the driving transistor due to signal changes on the data line pattern is more preferably avoided. Moreover, according to the display panel of the above structure, the occurrence of a short circuit between the first conductive connection portion 701 and the compensation function pattern 401 is also avoided. Specifically, the compensation function pattern 401 is provided between the data line pattern (for example, DATA1) and the first conductive connection portion included in the sub-pixel driving circuit of the first part, and the data line pattern That is, the gate of the third transistor T3) and the data line pattern (for example, DAT A1) can be separated, so that crosstalk occurring in the gate potential of the driving transistor due to signal changes on the data line pattern is more preferably avoided. Moreover, according to the display panel of the above structure, the occurrence of a short circuit between the first conductive connection portion 701 and the compensation function pattern 401 is also avoided. In addition, as shown in FIGS. 21 and 23, the compensation function pattern 401 is coupled to the initialization signal line pattern (for example, VINT1) to give a fixed potential to the compensation function pattern 401, so that crosstalk occurring in the gate potential of the driving transistor due to signal changes on the data line pattern is further avoided.

[0131] Furthermore, as shown in FIGS. 21 and 23, the compensation function pattern 401 is coupled to the initialization signal line pattern (for example, VINT1) so that the compensation function pattern 401 can have a fixed potential, thereby further avoiding crosstalk from occurring in the gate potential of the driving transistor due to signal changes on the data line pattern. Also, as described above, by positioning the first conductive connection portion 701 in the third metal layer, the first conductive connection portion 701 is formed with other patterns included in the third metal layer in a single pattern. Moreover, according to the display panel of the above structure, the occurrence of a short circuit between the first conductive connection portion 701 and the compensation function pattern 401 is also avoided.

[0132] Also, as described above, by positioning the first conductive connection portion 701 in the third metal layer, the first conductive connection portion 701 forms a single pattern with other patterns included in the third metal layer. Since it can be formed in the ning process, the flow of the manufacturing process of the display substrate is preferably simplified. It is simplified.

[0133] As shown in FIG. 24, in some embodiments, the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements. Each of the second light-emitting elements includes a second anode 502, a second light-emitting pattern 602, and a second cathode, which are sequentially stacked along a direction away from the base. Each of the third light-emitting elements includes two sub-light-emitting elements provided opposite to each other along the first direction. Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode, which are sequentially stacked along a direction away from the base. The plurality of sub-pixel driving circuits further include a second part of sub-pixel driving circuits and a third part of sub-pixel driving circuits. The second part of sub-pixel driving circuits corresponds one-to-one with the second light-emitting elements and is for driving the light emission of the corresponding second light-emitting elements. The third part of sub-pixel driving circuits corresponds one-to-one with the sub-light-emitting elements and is for driving the light emission of the corresponding sub-light-emitting elements. The second anode 502, the second light-emitting pattern 602, and the second cathode are provided by being sequentially stacked along a direction away from the base. Each of the third light-emitting elements includes two sub-light-emitting elements provided opposite to each other along the first direction. Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode, which are sequentially stacked along a direction away from the base. The third anode 503, the third light-emitting pattern 603, and the third cathode are provided by being sequentially stacked along a direction away from the base. Including. The plurality of sub-pixel driving circuits further include a second part of sub-pixel driving circuits and a third part of sub-pixel driving circuits. The second part of sub-pixel driving circuits corresponds one-to-one with the second light-emitting elements. The second part of sub-pixel driving circuits is for driving the light emission of the corresponding second light-emitting elements. The third part of sub-pixel driving circuits corresponds one-to-one with the sub-light-emitting elements. The third part of sub-pixel driving circuits is for driving the light emission of the corresponding sub-light-emitting elements. For that purpose. The orthographic projection of the first conductive connection portion included in the second part of sub-pixel driving circuits on the base overlaps with the orthographic projection of the corresponding second anode 502 on the electrode. The orthographic projection of the first conductive connection portion included in the third part of sub-pixel driving circuits on the base overlaps with the orthographic projection of the corresponding third anode 503 on the base. The orthographic projection of the first conductive connection portion included in the third part of sub-pixel driving circuits on the base. Overlaps with the orthographic projection of the corresponding third anode 503 on the base.

[0134] As described above, the base of the first conductive connection included in the subpixel driving circuit of the second portion The orthogonal projection on the first anode 502 corresponds to the orthogonal projection on the second anode 502. and burlap the base of a first conductive connection included in a subpixel driving circuit of the third portion. The orthogonal projection on the base of the third anode 503 is overlaid with the corresponding orthogonal projection on the base of the third anode 503. The second anode 502 and the third anode 50 3 will have a higher flatness.

[0135] As shown in FIG. 15, in some embodiments, the gate of the first transistor T1 201g is in direct contact with the corresponding gate scanning line pattern GATE.

[0136] Specifically, the gate 201g of the first transistor T1 and the corresponding gate scanning line The first transistor is formed in the same layer as the pattern GATE and integrally formed. The gate 201g of the transistor T1 and the corresponding gate scanning line pattern GATE are Not only can the first transistor be formed in the same patterning process, but the first transistor formed The gate of the gate electrode of the corresponding gate scanning line pattern GATE can be directly contacted with the corresponding gate scanning line pattern GATE. The gate of the first transistor is connected to the corresponding gate scanning line pattern GATE. This eliminates the need for a separate conductive connection for connecting the two.

[0137] In some embodiments, the gate of the second transistor, the gate of the seventh transistor Each gate may be integral with the corresponding gate scanning line pattern GATE. Alternatively, the gate of the second transistor and the gate of the seventh transistor are opposite to each other. It may be in direct contact with the corresponding gate scanning line pattern GATE, or the second transistor The gates of the transistor and the seventh transistor may both be part of the corresponding gate scanning line pattern GATE.

[0138] In some embodiments, the orthographic projection of the first electrode of the first transistor on the base 50 at least partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the base 50, and / or the orthographic projection of the second electrode of the first transistor on the base 50 at least partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. Specifically, as shown in FIG. 15, in the sub-pixel driving circuit having the above structure, the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured as such.

[0139] Specifically, as shown in FIG. 15, in the sub-pixel driving circuit having the above structure, the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured such that the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured such that the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured such that the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured such that the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured such that the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the second electrode (i.e., the N1 node in FIG. 15) of the first transistor T1 on the base 50, and / or the orthographic projection of the compensation function pattern 401 on the base 50 at least partially overlaps with the orthographic projection of the first electrode (formed at 101ps in FIG. 15) of the first transistor T1 on the base 50. It may be configured as such.

[0140] According to the above configuration method, in the direction perpendicular to the base 50, the compensation function pattern 401 can cover the second electrode of the first transistor T1 and / or the first electrode of the first transistor T 1. Therefore, the second electrode of the first transistor T1 and / or serves as a shield for the first electrode of the first transistor T1, and the first crosstalk to the first transistor T1 when the data signal transmitted on the data line pattern DATA adjacent to the transistor T1 changes is avoided. Moreover, the second electrode of the first transistor T1 is coupled to the gate 203g of the third transistor T3, and the first electrode of the transistor T1 is coupled to the second electrode of the third transistor T3. Therefore, when the data signal transmitted on the data line pattern DATA adjacent to the first transistor T1 changes, crosstalk to the third transistor T3 is further avoided. As shown in FIG. 21, in some embodiments, the orthographic projection of the first electrode of the first transistor T1 on the base does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the base, and / or the orthographic projection of the second electrode of the first transistor T1 on the above-mentioned base does not overlap with the orthographic projection of the corresponding compensation function pattern on the base.

[0141] According to the above configuration method, a wide distance is provided between the compensation function pattern 401 and the first conductive connection portion 701, the occurrence of a short-circuit defect between the compensation function pattern 401 and the first conductive connection portion 701 is avoided, and while the flatness of the first anode 501 is guaranteed, the formation of a parasitic capacitance between the compensation function pattern 401 and the shield pattern 301 is avoided. the above-mentioned base does not overlap with the orthographic projection of the corresponding compensation function pattern on the base. the orthographic projection of the second electrode of the first transistor T1 on the above-mentioned base does not overlap with the orthographic projection of the corresponding compensation function pattern on the base.

[0142] According to the above configuration, a wide distance is provided between the compensation function pattern 401 and the first conductive connection portion 701, the occurrence of a short-circuit defect between the compensation function pattern 401 and the first conductive connection portion 701 is avoided, and while the flatness of the first anode 501 is guaranteed, the formation of a parasitic capacitance between the compensation function pattern 401 and the shield pattern 301 is avoided. In some embodiments, the sub-pixel driving circuit further includes a seventh transistor T7 while the flatness of the first anode 501 is guaranteed, the formation of a parasitic capacitance between the compensation function pattern 401 and the shield pattern 301 is avoided.

[0143] In some embodiments, the sub-pixel driving circuit further includes a seventh transistor T7 The gate 207g of the seventh transistor T7 is connected to a reset signal line pattern (for example, 15) in the subpixel driving circuit of the first part. A second electrode of the transistor T7 is coupled to the first anode 501 and a orthogonal projection of a first electrode of the seventh transistor in the pixel driving circuit onto the base 50; , the seventh between the corresponding compensation function pattern 401 and the orthogonal projection on the base 50. There is an overlap region, and the first electrode of the seventh transistor is connected to the seventh overlap region. The compensation function pattern 401 is connected to the corresponding compensation function pattern 401 through a via hole provided in the substrate region. As a result, the corresponding initialization signal line pattern is Indirectly connected to VINT.

[0144] Specifically, the orthogonal projection of the first electrode of the seventh transistor onto the base 50 and the corresponding A seventh overhang is formed between the orthogonal projection of the compensation function pattern 401 on the base 50. If there is an overlap region, a via hole can be formed in the seventh overlap region. The first electrode of the seventh transistor is connected to the compensation function pattern 40 through the via hole. 1, and the compensation function pattern 401 is coupled to the initialization signal line. Therefore, the first electrode of the seventh transistor and the An indirect connection with the initialization signal line can be realized.

[0145] In the above embodiment, the first electrode of the seventh transistor is connected to the compensation function pattern 40. 1, the first electrode of the seventh transistor is indirectly coupled to the initialization signal line via and the initialization signal line, the fabrication of a conductive connection part used exclusively for coupling the initialization signal line to the It indicates that the manufacturing process of the display panel is simplified and the production cost is saved.

[0146] It should be noted that, as shown in FIG. 15, the orthographic projection of the base 5 of the compensation function pattern 401 on the base 50 0 may overlap with the orthographic projection of the second pole of the seventh transistor on the base 50, or, as shown in FIG. 19, the orthographic projection of the base 50 of the compensation function pattern 401 on the base 50 may not overlap with the orthographic projection of the second pole of the seventh transistor on the base 50. orthographic projection may not overlap with the orthographic projection of the second pole of the seventh transistor on the base 50. As shown in FIG. 15, in some embodiments, the orthographic projection of the gate of the driving transistor on the base 50

[0147] at least partially overlaps with the orthographic projection of the corresponding base 50 of the compensation function pattern 401 on the base 50. Specifically, continuing to refer to FIG. 15, the orthographic projection of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) on the base 50 at least partially overlaps with the orthographic projection of the corresponding base 50 of the compensation function pattern 401 on the base 50.

[0148] By configuring the compensation function pattern 401 such that the orthographic projection of the gate of the driving transistor on the base 50 (i.e., the gate 203g of the third transistor T3) at least partially overlaps with the orthographic projection of the corresponding base 50 of the compensation function pattern 401 on the base 50, the compensation function pattern 401 can cover at least a part of the gates of the driving transistors, so that the gates of the driving transistors are shielded, and crosstalk to the driving transistors when the data signals transmitted on the data line pattern DATA adjacent to the driving transistors change is avoided. As a result, the stable operating performance of the driving transistors is preferably guaranteed. at least partially overlaps with the orthographic projection of the corresponding base 50 of the compensation function pattern 401 on the base 50. By configuring the compensation function pattern 401 such that the orthographic projection of the gate of the driving transistor on the base 50 (i.e., the gate 203g of the third transistor T3) at least partially overlaps with the orthographic projection of the corresponding base 50 of the compensation function pattern 401 on the base 50, the compensation function pattern 401 can cover at least a part of the gates of the driving transistors, so that the gates of the driving transistors are shielded, and crosstalk to the driving transistors when the data signals transmitted on the data line pattern DATA adjacent to the driving transistors change is avoided. As a result, the stable operating performance of the driving transistors is preferably guaranteed. As a result, the stable operating performance of the driving transistors is preferably guaranteed. Continuing to refer to FIG. 15, in some embodiments, the gate of the driving transistor As a result, the stable operating performance of the driving transistors is preferably guaranteed.

[0149] Continuing to refer to FIG. 15, in some embodiments, the gate of the driving transistor The orthographic projection of the drive transistor on the base 50 and the orthographic projection of the corresponding compensation function pattern 401 on the base 50 include a first overlapping portion that overlaps. The orthographic projection of the first overlapping portion on the base 50 overlaps at least partially with the orthographic projection of the corresponding first anode 50 1 on the base 50.

[0150] Specifically, according to the above configuration method, in the direction perpendicular to the base 50, the gate of the drive transistor, the compensation function pattern 401, and the first anode 501 have a common overlapping region. Thus, according to the compensation function pattern 401, not only can crosstalk to the drive transistor when the data signal transmitted on the data line pattern DATA adjacent to the drive transistor changes be avoided, but also crosstalk to the drive transistor when the drive signal transmitted on the first anode 501 changes can be avoided. Furthermore, the compensation function pattern 401 may be provided between the gate of the drive transistor and the first anode 501. Thus, according to the compensation function pattern 401, crosstalk to the drive transistor when the drive signal transmitted on the first anode 501 changes can be more preferably avoided.

[0151] As shown in FIG. 15, in some embodiments, the first electrode plate Cst1 of the storage capacitor Cst is provided with the same material as the gate scan line pattern GATE and the reset signal line pattern RST, and the second electrode plate Cst2 of the storage capacitor Cst is the initialization signal line pattern pattern.

[0152] As shown in FIG. 15, in some embodiments, the first electrode plate Cst1 of the storage capacitor Cst is provided with the same material as the gate scan line pattern GATE and the reset signal line pattern RST, and the second electrode plate Cst2 of the storage capacitor Cst is the initialization signal line pattern pattern. It is provided with the same material as that of VINT, and the base of the first electrode plate Cst1 of the storage capacitance Cst The orthographic projection on 50, and the base 50 of the second electrode plate Cst2 of the storage capacitance Cst The orthographic projections are all between the orthographic projection on the base 50 of the corresponding gate scanning line pattern GATE and the orthographic projection on the base 50 of the corresponding emission control signal line pattern EM And are located therebetween

[0153] Specifically, when manufacturing each functional pattern in the display panel, some functional patterns in the display panel May be manufactured with the same material. Exemplarily, some of the functional patterns with conductive performance in the display panel are manufactured with materials having the same type of conductive performance, and some of the functional patterns with insulating performance in the display panel are manufactured with materials having the same type of insulating performance

[0154] More specifically, the first electrode plate Cst1 of the storage capacitance Cst is provided with the same material as that of the gate scanning line pattern GATE and the reset signal line pattern RST, and the second electrode plate Cst2 of the storage capacitance C st may be provided with the same material as that of the initialization signal line pattern VINT. According to this configuration method, when manufacturing the first electrode plate Cst1 of the storage capacitance Cst, the aforementioned gate scanning line pattern GATE and the reset signal line pattern RST, they can be formed in the same manufacturing environment using the same process equipment. Similarly, when manufacturing the second electrode plate Cst2 of the storage capacitance Cst and the initialization signal line pattern VINT, they can also be formed in the same manufacturing environment using the same Process equipment. Therefore, in this configuration method, the flow of the manufacturing process of the display panel can be effectively simplified, and the manufacturing cost of the display panel can be saved ​​​​​​​​​

[0155] Also, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitance Cst , the orthographic projection of the first electrode plate Cst1 of the storage capacitance Cst on the base 50, and the storage Both the orthographic projection of the second electrode plate Cst2 of the capacitance Cst on the base 50 are respectively the orthographic projection of the corresponding gate scan line pattern GATE on the base 50 and the orthographic projection of the corresponding emission control signal It may be configured to be located between the orthographic projection of the line pattern on the base 50. According to this configuration method, it is only guaranteed that the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitance Cst can have a certain facing area in the direction perpendicular to the base 50 Without, in the direction perpendicular to the base 50, the first electrode plate Cst1 and The second electrode plate Cst2 of the storage capacitance Cst, and the gate scan line pattern GATE and the emission control signal line pattern The occurrence of overlap between the patterns is avoided. Therefore, the storage capacitance Cst does not form other parasitic capacitances between the gate scan line pattern GATE and the emission control signal line pattern EM, and the stable operating performance of the sub-pixel driving circuit is guaranteed.

[0156] In some embodiments, the functional film layer further includes a gate insulating layer (for example, GI1 in FIG. 17) and a first insulating layer Located on the side opposite to the base 50 in the gate insulating layer (for example, GI2 in FIG. 17). The first electrode plate Cst 1 of the storage capacitance Cst, the gate scan line pattern GATE, and the reset signal line pattern RST are all located on the surface of the gate insulating layer opposite to the base 50. The second electrode plate Cst2 of the storage capacitance C st and the initialization signal line pattern VINT are both located on the first insulating insulation It is located on the surface of the layer opposite to the base 50.

[0157] Specifically, the functional film layer further includes the gate insulating layer and the first insulating layer. The gate insulating layer is for insulating between the gate and the active layer in the thin film transistor. The first insulating layer is for insulating between the conductive functional patterns provided in separate layers on the display substrate.

[0158] When laying out the functional film layer of the display substrate, exemplarily, the first electrode Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE, and the reset signal line pattern RST may all be provided on the surface of the gate insulating layer opposite to the base 50. In this way, when the first electrode Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE, and the reset signal line pattern RST are made of the same type of material, the first electrode Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE, and the reset signal line pattern RST can be formed simultaneously in the same patterning process.

[0159] Similarly, the second electrode Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT may both be provided on the surface of the first insulating layer opposite to the base 50. In this way, when the second electrode Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT are made of the same type of material, the second electrode Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT can be formed simultaneously in the same patterning process.

[0160] If the functional film layer in the display panel is laid out according to the above method, the layout space can be effectively saved, which is not only beneficial to the thinning of the display panel, but also effectively simplifies the process flow of the production process of the display panel and can save the production cost of the display panel. As shown in FIG. 15, in some embodiments, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 both partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. As shown in FIG. 15, in some embodiments, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 both partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50.

[0161] As shown in FIG. 15, in some embodiments, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 both partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized.

[0162] Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized.

[0163] As shown in FIG. 15, in some embodiments, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 both partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Specifically, when laying out the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, for example, the orthographic projection of the first electrode plate Cst1 of the storage capacitor Cst on the base 50 and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding first anode 501 on the base 50. Since the first anode 501, the first electrode plate Cst1, and the second electrode plate Cst2 of the storage capacitor Cst are all provided in separate layers, according to this layout method, while avoiding the occurrence of a short circuit between the first anode 501 and the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst, more layout space of the display panel is utilized. The orthographic projection on the base 50 partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. It partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the base 50.

[0164] Specifically, referring to FIG. 15, the orthographic projection of the compensation function pattern 401 on the base 50 is configured to at least partially overlap with the orthographic projection of the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitance Cst on the base 50. In this way, the compensation function pattern 401 can cover at least a part of the first electrode plate Cst1 and at least a part of the second electrode plate Cst2 of the storage capacitance Cst. According to the compensation function pattern 401, when the data signal transmitted on the data line pattern DAT A adjacent to the storage capacitance Cst changes, it can not only avoid crosstalk to the storage capacitance Cst, but also avoid crosstalk to the storage capacitance Cst when the drive signal transmitted on the first anode 501 changes. As a result, the stability of the sub-pixel driving circuit operation in the display panel is more preferably guaranteed. When the data signal transmitted on the data line pattern DAT A adjacent to the storage capacitance Cst changes, crosstalk to the storage capacitance Cst can be avoided. When the drive signal transmitted on the first anode 501 changes, crosstalk to the storage capacitance Cst can be avoided. As a result, the stability of the sub-pixel driving circuit operation in the display panel is more preferably guaranteed. The stability of the sub-pixel driving circuit operation in the display panel is more preferably guaranteed.

[0165] As shown in FIGS. 13 and 15, in some embodiments, the central region of the second electrode plate Cst2 of the storage capacitance Cst includes an opening 302. The orthographic projection of the opening 302 on the base 50 does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. The orthographic projection of the opening 302 on the base 50 does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the base 50. It does not overlap.

[0166] Specifically, the region where the opening 302 is located on the second electrode plate Cst2 of the storage capacitance Cst is generally used for the formation of a via hole and a conductive part passing through the via hole. The via hole and the conductive part are used to connect the functional patterns located on both the upper and lower sides of the second electrode plate. is as follows.

[0167] In the display panel according to the above embodiment, the orthographic projection of the opening 302 on the base 50 overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the base 50 is configured not to overlap, so that the occurrence of a short circuit between the compensation function pattern 401 and the conductive part in the opening 302 can be more preferably avoided, and thus the stability of the sub-pixel driving circuit operation in the display panel is more preferably guaranteed.

[0168] It should be noted that when the layout space is limited, the orthographic projection of the opening 302 on the base 50 may be configured to partially overlap with the orthographic projection of the corresponding compensation function pattern 401 on the base 50, and the key point is that it is ensured that no short circuit occurs between the compensation function pattern 401 and the conductive part in the opening 302.

[0169] As shown in FIGS. 15 and 18, in some embodiments, the orthographic projection of the compensation function pattern 4 01 on the base 50 may be configured to partially overlap with the orthographic projection of the shield pattern 301 on the base, or, as shown in FIG. 20, in some embodiments, the orthographic projection of the compensation function pattern 401 on the base 50 may be configured not to overlap with the orthographic projection of the shield pattern 301 on the base.

[0170] In some embodiments, in the direction perpendicular to the base 50, the thickness difference between the compensation function layer and the power supply signal line layer is within a threshold range, or the compensation function layer and The thickness difference from the data line layer is within a threshold range.

[0171] Specifically, when manufacturing the compensation function pattern 401, in the direction perpendicular to the base 50 the thickness of the compensation function pattern 401 can be set according to actual needs, and illustratively in the direction perpendicular to the base 50, whether the thickness difference between the compensation function layer and the power signal line layer is within the threshold range, or whether the thickness difference between the compensation function layer and the data line layer is within the threshold range, and according to this configuration method, the compensation function layer can preferably compensate for the step generated between the power signal line layer and the data line layer.

[0172] It should be noted that the threshold range may be configured to be 0.1 μm or less. In this way, in the direction perpendicular to the base 50, the thicknesses of the compensation function layer, the power signal line layer, and the data line layer are close to each other, so that the compensation effect for the step is preferably guaranteed.

[0173] As shown in FIGS. 24 and 26, in some embodiments, the display panel further includes a plurality of second light-emitting elements, and each of the second light-emitting elements includes a second anode 502, a second light-emitting pattern 602, and a second cathode sequentially stacked along the direction away from the base 50. The second anode 502 includes a fifth edge portion 502a1 and a sixth edge portion 502a2 provided opposite to each other along the second direction, and a second intermediate portion 502a3 located between the fifth edge portion 5 02a1 and the sixth edge portion 502a2. The orthographic projection of the second intermediate portion 502a3 on the base 50 overlaps with the orthographic projection of the second light-emitting pattern 602 on the base 50. ​​​The orthographic projection of the second intermediate portion 502a3 on the base 50 overlaps at least partially with the orthographic projection of the corresponding power supply signal line pattern VDD on the base 50, and the orthographic projection of the second intermediate portion 502a3 on the base 50 overlaps at least partially with the orthographic projection of the corresponding data line pattern D ATA on the base 50.

[0174] Specifically, the display panel may further include a second light-emitting element, and the second light-emitting element has a light-emitting color different from that of the first light-emitting element. The second light-emitting element includes a second anode 502, a second light-emitting pattern 602, and a second cathode that are sequentially stacked along a direction away from the base 50. The second anode 502 is coupled to a corresponding second sub-pixel driving circuit in the display panel to receive a driving signal supplied from the second sub-pixel driving circuit. The second cathode receives a common signal, and the second light-emitting pattern 602 emits light of a corresponding color under the combined action of the second anode 502 and the second cathode. The second cathode receives a common signal, and the second light-emitting pattern 602 emits light of a corresponding color under the combined action of the second anode 502 and the second cathode. Color light.

[0175] The structure of the second anode 502 is diverse. Exemplarily, the second anode 502 includes a fifth edge portion 502a1 and a sixth edge portion 502a2 that are oppositely provided along the second direction, and a second intermediate portion 502a3 located between the fifth edge portion 502a1 and the sixth edge portion 502a2. And a second intermediate portion 502a3 located between the fifth edge portion 502a1 and the sixth edge portion 502a2. Including.

[0176] When the second light-emitting element is laid out, the orthographic projection of the second intermediate portion 502a3 on the base 50 overlaps with the orthographic projection of the second light-emitting pattern 602 on the base 50. , the orthographic projection of the second intermediate portion 502a3 on the base 50 overlaps at least partially with the orthographic projection of the corresponding power supply signal line pattern VDD on the base 50, and the orthographic projection of the second intermediate portion 502a3 on the base 50 may be configured to overlap at least partially with the orthographic projection of the corresponding data line pattern D ATA on the base 50. According to this layout method, the intermediate portion of the second anode 502 can uniformly cover the power supply signal line pattern VDD and the data line pattern DATA, so the intermediate portion of the second anode 502 will have high flatness. In this way, when forming the second light emitting pattern 602 on the second intermediate portion 502a3 of the second anode 502, since it can be ensured that the second light emitting pattern 602 has high flatness, the light emitting effect of the second light emitting element is guaranteed, and the color shift phenomenon occurring during display by the display panel is reduced . As shown in FIG. 26, in some embodiments, the second light emitting pattern 602 is symmetric with respect to the second

[0177] symmetry axis, the second symmetry axis extends along the first direction, and the orthographic projection of the second symmetry axis on the base 50 is located inside the orthographic projection of the corresponding power supply signal line pattern VDD on the said base 50. Specifically, the structure of the second light emitting pattern 602 can be set according to actual needs.

[0178] Exemplarily, it can be configured such that the second light emitting pattern 602 is an axisymmetric pattern, and in this way, it is more advantageous for improving the light emission uniformity of the second light emitting element.

[0179] Furthermore, the second light-emitting pattern 602 is symmetric with respect to the second axis of symmetry, and the second axis of symmetry extends along the first direction, and the orthogonal projection of the second axis of symmetry on the base 50 is located inside the orthogonal projection of the corresponding power signal line pattern VDD on the base 50. According to this layout method, the central portion of the second light-emitting pattern 602 can cover the power signal line pattern VDD, and since the power signal line pattern VDD extends along the first direction and has a wide width in the direction perpendicular to the first direction, most of the second light-emitting pattern 602 is formed on the power signal line pattern VDD. As a result, the flatness of the second light-emitting pattern 602 is more preferably ensured, and the color shift phenomenon generated during the display by the display panel is reduced. The orthogonal projection of the second axis of symmetry on the base 50 is located inside the orthogonal projection of the corresponding power signal line pattern VDD on the base 50. The orthogonal projection of the second axis of symmetry on the base 50 is located inside the orthogonal projection of the corresponding power signal line pattern VDD on the base 50. According to this layout method, the central portion of the second light-emitting pattern 602 can cover the power signal line pattern VDD. According to this layout method, the central portion of the second light-emitting pattern 602 can cover the power signal line pattern VDD. The power signal line pattern VDD extends along the first direction and has a wide width in the direction perpendicular to the first direction. Since the power signal line pattern VDD extends along the first direction and has a wide width in the direction perpendicular to the first direction, most of the second light-emitting pattern 602 is formed on the power signal line pattern VDD. Since the power signal line pattern VDD extends along the first direction and has a wide width in the direction perpendicular to the first direction, most of the second light-emitting pattern 602 is formed on the power signal line pattern VDD. As a result, the flatness of the second light-emitting pattern 602 is more preferably ensured, and the color shift phenomenon generated during the display by the display panel is reduced.

[0180] As shown in FIGS. 24 and 27, in some embodiments, the display panel further includes a plurality of third light-emitting elements, and each of the third light-emitting elements includes two sub-light-emitting elements provided facing each other along the first direction. Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode sequentially stacked along the direction away from the base 50. The third anode 503 includes a seventh edge portion 503a1 and an eighth edge portion 503a2 provided facing each other along the second direction, and a third intermediate portion located between the seventh edge portion 503a1 and the eighth edge portion 503a2. The orthogonal projection of the third intermediate portion on the base 50 overlaps with the orthogonal projection of the third light-emitting pattern 603 on the base 50. As shown in FIGS. 24 and 27, in some embodiments, the display panel further includes a plurality of third light-emitting elements, and each of the third light-emitting elements includes two sub-light-emitting elements provided facing each other along the first direction. As shown in FIGS. 24 and 27, in some embodiments, the display panel further includes a plurality of third light-emitting elements, and each of the third light-emitting elements includes two sub-light-emitting elements provided facing each other along the first direction. Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode sequentially stacked along the direction away from the base 50. Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode sequentially stacked along the direction away from the base 50. The third anode 503 includes a seventh edge portion 503a1 and an eighth edge portion 503a2 provided facing each other along the second direction, and a third intermediate portion located between the seventh edge portion 503a1 and the eighth edge portion 503a2. The third anode 503 includes a seventh edge portion 503a1 and an eighth edge portion 503a2 provided facing each other along the second direction, and a third intermediate portion located between the seventh edge portion 503a1 and the eighth edge portion 503a2. The orthogonal projection of the third intermediate portion on the base 50 overlaps with the orthogonal projection of the third light-emitting pattern 603 on the base 50. The orthogonal projection of the third intermediate portion on the base 50 overlaps with the orthogonal projection of the third light-emitting pattern 603 on the base 50. The orthogonal projection of the third intermediate portion on the base 50 is located inside the orthogonal projection of the corresponding data line pattern DA on the base 50. The orthographic projection of the TA on the base 50 at least partially overlaps with the seventh edge portion 5 The orthographic projection of 03a1 on the base 50 overlaps at least partially with the orthographic projection of the corresponding power signal line pattern VDD on the base 50 of the base 50.

[0181] Specifically, the display panel may further include a plurality of third light emitting elements, and each of the third light emitting elements includes two sub-light emitting elements provided opposite to each other along the first direction. Each of the sub-light emitting elements has a different emission color from any of the emission colors of the first light emitting element and the second light emitting element, and the sub-light emitting elements are sequentially stacked along the direction away from the base 50 and may include a third anode 503, a third light emitting pattern 603, and a third cathode. The third anode 503 is coupled to a corresponding third sub-pixel driving circuit in the display panel and receives a driving signal supplied from the third sub-pixel driving circuit. The third cathode receives a common signal, and the third light emitting pattern 603 emits light of a corresponding color under the combined action of the third anode 503 and the third cathode. The structure of the third anode 503 is diverse. Exemplarily, the third anode 503 includes a seventh edge portion and an eighth edge portion provided opposite to each other along the second direction, and a third intermediate portion located between the seventh edge portion and the eighth edge portion. When the third light emitting element is laid out, the orthographic projection of the third intermediate portion on the base 50 overlaps with the orthographic projection of the third light emitting pattern 603 on the base 50, and the orthographic projection of the third intermediate portion on the base 50 overlaps with the corresponding data line pattern DATA on the base 50. The third anode 503 is coupled to a corresponding third sub-pixel driving circuit in the display panel and receives a driving signal supplied from the third sub-pixel driving circuit. The third cathode receives a common signal, and the third light emitting pattern 603 emits light of a corresponding color under the combined action of the third anode 503 and the third cathode. The third anode 503 is coupled to a corresponding third sub-pixel driving circuit in the display panel and receives a driving signal supplied from the third sub-pixel driving circuit. The third cathode receives a common signal, and the third light emitting pattern 603 emits light of a corresponding color under the combined action of the third anode 503 and the third cathode. The third cathode receives a common signal, and the third light emitting pattern 603 emits light of a corresponding color under the combined action of the third anode 503 and the third cathode. The third cathode receives a common signal, and the third light emitting pattern 603 emits light of a corresponding color under the combined action of the third anode 503 and the third cathode.

[0182] The structure of the third anode 503 is diverse. Exemplarily, the third anode 503 includes a seventh edge portion and an eighth edge portion provided opposite to each other along the second direction, and a third intermediate portion located between the seventh edge portion and the eighth edge portion. The third anode 503 includes a seventh edge portion and an eighth edge portion provided opposite to each other along the second direction, and a third intermediate portion located between the seventh edge portion and the eighth edge portion. The third anode 503 includes a seventh edge portion and an eighth edge portion provided opposite to each other along the second direction, and a third intermediate portion located between the seventh edge portion and the eighth edge portion.

[0183] When the third light emitting element is laid out, the orthographic projection of the third intermediate portion on the base 50 overlaps with the orthographic projection of the third light emitting pattern 603 on the base 50, and the orthographic projection of the third intermediate portion on the base 50 overlaps with the corresponding data line pattern DATA on the base 50. base 50. overlaps at least partially with the orthographic projection on the base 50, and the orthographic projection of the seventh edge portion on the base 50 overlaps at least partially with the orthographic projection of the corresponding power signal line pattern VDD on the base 50. It may be configured in this way. According to this layout method, the overlap area between the third anode 503, the corresponding power signal line pattern VDD, and the data line pattern DATA TA becomes small, and the third light emitting pattern 603 can be guaranteed to have a high flatness. Therefore, the light emitting effect of the third light emitting element is guaranteed, and the color shift phenomenon occurring during the display by the display panel is reduced. In some embodiments, the first light emitting element includes a red sub-pixel, the second light emitting element includes a blue sub-pixel, and the third light emitting element includes a green sub-pixel.

[0184] Specifically, the emission colors of the first light emitting element, the second light emitting element, and the third light emitting element can be set according to actual needs. Exemplarily, the first light emitting element includes a red sub-pixel, the second light emitting element includes a blue sub-pixel, and the third light emitting element includes a green sub-pixel.

[0185] Embodiments of the present disclosure further provide a display device including the display panel according to the above embodiments. In the display panel according to the above embodiments, the compensation function pattern 401 can compensate for the step generated below the first anode 501 by the power signal line pattern VDD and the data line pattern DATA. Therefore, in the display panel, the first anode 501 included in the first light emitting element causes a part of the corresponding power signal line pattern VDD and a part of the corresponding

[0186] the data line pattern DATA.

[0187] line pattern VDD and a part of the corresponding data line pattern DATA are caused by the first anode 501 included in the first light emitting element. Since the compensation function pattern 401 can compensate for the step generated below the first anode 501 by the power signal line pattern VDD and the data line pattern DATA, in the display panel, the first anode 501 included in the first light emitting element causes a part of the corresponding power signal line pattern VDD and a part of the corresponding data line pattern DATA. data line pattern DATA. The data line pattern DATA and at least a part of the corresponding compensation function pattern 401 are When covered at the same time, the first anode 501 can have a high degree of flatness. As a result, the color shift phenomenon that occurs when displaying on a display panel is effectively reduced, When the display device according to the embodiment includes the display panel according to the embodiment, the display device similarly has the above-mentioned advantageous effects. It has a beneficial effect.

[0188] It should be noted that the display device may be a television, a display, a digital photo frame, etc. Any product or part with a display function, such as a mobile phone or tablet PC .

[0189] An embodiment of the present disclosure is a method for manufacturing a display panel, the display panel being arranged in an array. a plurality of sub-pixel areas formed on the substrate, the method comprising: A functional film layer including a power supply signal line layer, a data line layer, and a compensation functional layer, includes a power supply signal line pattern VDD provided in each of the sub-pixel areas, and the data line The layer includes a data line pattern DATA provided in each of the sub-pixel areas, and the power signal The signal line pattern VDD includes a first portion extending along a first direction, and the data line pattern The compensation function layer includes at least one of the first and second layers. A functional film layer including a compensation functional pattern 401 provided in a sub-pixel area is formed on a base 50. To produce and A plurality of first light emitting elements, each of the first light emitting elements being separated from the base 50 A first anode 501 and a first light-emitting pattern are stacked in sequence along the direction away from each other. 601 and a first cathode, However, the orthogonal projection of the corresponding power supply signal line pattern VDD on the base 50 is different from the first orthogonal projection. There is a burlap area F1 on the base 50 of the corresponding data line pattern DATA. There is a second overlap area F2 with the orthogonal projection at There is a third overlap area F3 with respect to the orthogonal projection of the first plane on the base 50, and the second plane The burlap region F2 is a region between the first overlap region F1 and the third overlap region F2. F3, the base 50 in the functional film layer is disposed between the first light emitting element 10 and the second light emitting element 11. and fabricating the opposite side of the display panel.

[0190] Specifically, the sub-pixel areas arranged in an array extend along a first direction. the pixel array may be partitioned into columns of sub-pixel areas and rows of sub-pixel areas extending along a second direction; The sub-pixel area column includes a plurality of sub-pixel areas arranged along the first direction. The sub-pixel area row includes a plurality of sub-pixel areas arranged along the second direction. The first direction and the second direction intersect, and the first direction includes a Y direction, for example. In rare cases, the second direction includes the X direction.

[0191] The power supply signal line layer includes a power supply signal line pattern VDD provided in each of the sub-pixel areas. The power supply signal line pattern VDD may be selectively formed in a lattice shape, and the lattice shape The power supply signal line pattern VDD includes a first portion extending along the first direction. The power supply signal line pattern VDD corresponds to the sub-pixel area column in one-to-one correspondence. The turn VDD is located in each sub-pixel area included in the corresponding sub-pixel area column. .

[0192] The data line layer includes a data line pattern DATA provided in each of the sub-pixel areas. The data line pattern DATA extends along the first direction. The data line pattern DAT A is located in each sub-pixel area included in the corresponding column of sub-pixel areas.

[0193] The display panel includes a plurality of functional film layers located on the opposite side of the base 50. The first light emitting element further includes a first light emitting element, the first light emitting element being arranged along a direction away from the base 50. The first anode 501, the first light-emitting pattern 601 and the first cathode 502 are laminated in this order. During the operation of the display panel, a driving signal is supplied to the first anode 501, and the front A common signal is supplied to the first cathode, so that the first anode 501 and the first cathode An electric field is generated between the first light-emitting pattern 601 and the corresponding color light. For example, the first light-emitting element includes a red light-emitting element, and the first light-emitting element is controlled to emit red light. It can be issued.

[0194] The compensation function layer has a compensation function pattern provided in at least one of the sub-pixel areas. For example, the compensation function pattern 401 corresponds to the first light emitting device in a one-to-one correspondence. We will respond with In manufacturing the display panel, a functional film layer is first formed on the base 50, and then the functional film layer is A first light emitting element is manufactured on the opposite side of the base 50 in the above-mentioned, and when manufacturing the functional film layer, The power supply signal line pattern VDD and the data line pattern DATA are arranged along the second direction. The compensation function patterns 401 may be arranged alternately with the first light emitting element. For example, in front of the first anode 501 in the first light emitting element. The orthogonal projection on the base 50 is a projection of the corresponding power supply signal line pattern VDD on the base 50. The orthogonal projection above has a first overlap region F1, and the corresponding data line pattern D There is a second overlap area F2 with the orthogonal projection of the ATA on the base 50, The orthogonal projection of the compensation function pattern 401 on the base 50 is a third overlap region. F3, and the second overlap region F2 is adjacent to the first overlap region F1. It is located between the third overlap region F3.

[0195] In the display panel manufactured using the manufacturing method according to the embodiment of the present disclosure, The pattern 401 is a pattern including the power supply signal line pattern VDD and the data line pattern DATA. Since the step occurring under the first anode 501 can be compensated for, the display panel A first anode 501 included in one light emitting device is connected to a part of the corresponding power signal line pattern. a line VDD, a part of the corresponding data line pattern DATA, and at least a part of the corresponding When the corresponding compensation function pattern 401 is simultaneously covered, the first anode 501 has a high flatness. As a result, the color shift phenomenon that occurs when displaying on a display panel can be effectively prevented. is substantially reduced.

[0196] It should be noted that each embodiment in this specification is described in a progressive manner. The same or similar parts of each embodiment may be referred to each other, and each embodiment may be used in combination with other embodiments. The explanation focuses on the differences from the examples. In particular, the method embodiment is basically the same as the Since it is similar to the product embodiment, it is briefly described. For related parts, refer to the description part of the product embodiment. It suffices to refer to the description part.

[0197] Unless otherwise defined, technical terms or scientific terms used in this disclosure have the ordinary meanings that can be understood by those skilled in the art. The "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. It is only for distinguishing different components. Similar terms such as "comprising" or "including" mean that the elements or members listed before "comprising" or "including" include the elements or members listed after "comprising" or "including" and their equivalents, but do not exclude other elements or members. The elements or members listed before "comprising" or "including" include the elements or members listed after "comprising" or "including" and their equivalents, but do not exclude other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections whether directly connected or indirectly connected. Whether directly connected or indirectly connected, electrical connections may be included. Terms such as "upper", "lower", "left", "right", etc. only indicate relative positional relationships. When the absolute position of the object to be described changes, the corresponding relative positional relationships may also change accordingly. When it is mentioned that an element such as a layer, film, region or substrate is located "above" or "below" another element, the element may be located "directly" "above" or "below" another element, or intermediate elements may be interposed. It should be understood that when it is mentioned that an element such as a layer, film, region or substrate is located "above" or "below" another element, the element may be located "directly" "above" or "below" another element, or intermediate elements may be interposed.

[0198] It should be understood that when it is mentioned that an element such as a layer, film, region or substrate is located "above" or "below" another element, the element may be located "directly" "above" or "below" another element, or intermediate elements may be interposed. When it is mentioned that an element such as a layer, film, region or substrate is located "above" or "below" another element, the element may be located "directly" "above" or "below" another element, or intermediate elements may be interposed. Or intermediate elements may be interposed.

[0199] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or specific examples. They may be combined in an appropriate manner in any one or more embodiments or specific examples.

[0200] What has been described above is only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. It will not be. A person skilled in the art can easily conceive of modifications and substitutions within the technical scope described in the present disclosure, and all of these modifications and substitutions should be within the protection scope of the present disclosure. Therefore it is so. The protection scope of the present disclosure should comply with the scope of the appended claims. ​

Claims

1. A display panel, comprising: a base; a functional film layer provided on the base; and a display layer provided on the functional film layer. a plurality of first light emitting elements provided on the opposite side of the base, the first light emitting elements being arranged in an array; a plurality of sub-pixel areas, The functional film layer includes a power signal line layer, a data line layer and a compensation functional layer, and the power signal line layer , a power supply signal line pattern provided in each of the sub-pixel areas, and the data line layer The power supply signal line pattern includes a data line pattern provided in the sub-pixel area. The data line pattern includes a first portion extending along a first direction, the data line pattern extending along the first direction. The compensation function layer extends through at least one of the sub-pixel areas. Includes functional patterns, Each of the first light emitting elements is stacked in sequence in a direction away from the base. A first anode is provided, a first light-emitting pattern is provided, and a first cathode is provided, The orthogonal projection of the power supply signal line pattern on the base is The shadow is a first overlap region on the base of the corresponding data line pattern. There is a second overlapping area between the orthogonal projection of the compensation function pattern and the base of the compensation function pattern. There is a third overlapping area with the orthogonal projection on the surface of the image, and the second overlapping area is the a display panel located between the first overlapping area and the third overlapping area; 。

2. The first anode has a first edge portion and a second edge portion provided opposite to each other along a second direction. a first intermediate portion located between the first edge portion and the second edge portion; the second direction and the first direction intersect, an orthogonal projection of the first edge portion onto the base includes the first overlap region; an orthogonal projection of the second edge portion onto the base includes the third overlap region; an orthogonal projection of the first intermediate portion onto the base includes the second overlap region; The display panel according to claim 1.

3. The orthogonal projection of the first edge portion on the base is and the orthogonal projection of the second edge portion on the base does not overlap with the orthogonal projection on the base. The first intermediate portion does not overlap with the orthogonal projection of the first light-emitting pattern on the base. The orthogonal projection of the first light-emitting pattern on the base overlaps with the orthogonal projection of the first light-emitting pattern on the base. The display panel according to claim 2 ,

4. The functional film layer includes a gate scanning line layer, an initialization signal line layer, a reset signal line layer, and a light emission control signal layer. Further comprising a line layer; The gate scanning line layer includes a gate scanning line pattern provided in each of the sub-pixel areas. The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. The reset signal line layer is a reset signal line pattern provided in each of the sub-pixel areas. The light emission control signal line layer includes a light emission control signal line provided in each of the sub-pixel areas. the gate scanning line pattern, the initialization signal line pattern, the reset The signal line pattern and the light emission control signal line pattern both extend along a second direction. The display panel according to claim 2 , wherein the second direction intersects with the first direction.

5. The first anode has a third edge portion and a fourth edge portion provided opposite to each other along the first direction. the first intermediate portion further includes an edge portion, the first intermediate portion being a portion between the third edge portion and the fourth edge portion. the third edge portion is located between the first edge portion and the second edge portion, the fourth edge portion is connected to the first edge portion and the second edge portion, Attached to the part, a front view of the orthogonal projection of the first intermediate portion on the base and the corresponding gate scan line pattern; Orthogonal projection on the base, and corresponding orthogonal projection of the reset signal line pattern on the base. The display panel of claim 4 , wherein the projection includes a sixth overlap region.

6. The first anode includes a body portion and a via hole connecting portion, and the body portion is the first edge portion, the second edge portion, the third edge portion, the fourth edge portion, and the 6. The display of claim 5, including a first intermediate portion, said body portion being in a centrosymmetric pattern. panel.

7. The first intermediate portion has a centrally symmetric pattern, and the first intermediate portion has a right-angled cross section on the base.

3. The method of claim 2, wherein the projection overlaps with an orthogonal projection of the first light emitting pattern onto the base. Display panel.

8. the display panel includes a first metal layer, a second metal layer and a third metal layer; The gate scanning line layer, the reset signal line layer, and the light emission control signal line layer are made of the first metal Located in the layer the initialization signal line layer is located on the second metal layer; the data line layer, the power signal line layer and the compensation function layer are located on the third metal layer; The functional film layer further includes a first insulating layer and a second insulating layer, and the first insulating layer is the second insulating layer is disposed between the second metal layer and the third metal layer; The display panel according to claim 4 , wherein the metal layer is disposed between the metal layer and the display panel.

9. The compensation function pattern is made of a conductive material and is coupled to the initialization signal line pattern. The display panel according to claim 4 .

10. 10. The method of claim 9, wherein the compensation function pattern is provided in the same layer as the data line pattern. Display panel.

11. The display panel further includes a plurality of sub-pixel driving circuits, The first sub-pixel driving circuit corresponds to the first light emitting element in a one-to-one manner. Each subpixel driving circuit is for driving the corresponding first light emitting element to emit light. the sub-pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor; The gate of the first transistor is coupled to the corresponding gate scan line pattern, A first electrode of a first transistor is coupled to a second electrode of the drive transistor, and the first a second electrode of the transistor is coupled to the gate of the drive transistor; The gate of the second transistor is coupled to the corresponding reset signal line pattern. A first electrode of the second transistor is coupled to a corresponding initialization signal line pattern, a second electrode of a second transistor coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the corresponding gate scan line pattern, A first electrode of a fourth transistor is coupled to the corresponding data line pattern, and the fourth transistor a second electrode of the transistor coupled to the first electrode of the drive transistor; A first electrode of the driving transistor is coupled to a corresponding power signal line pattern; a second electrode of the driving transistor is coupled to the corresponding first light emitting element; A first plate of the storage capacitor is coupled to the gate of the drive transistor.

5. The display panel according to claim 4, wherein the second plate is coupled to the corresponding power supply signal line pattern. Ru.

12. The sub-pixel driving circuit further includes a first conductive connection, and a second electrode of the first transistor. is coupled to the gate of the drive transistor via the first conductive connection; The display panel further includes a third metal layer, and the first conductive connection is located on the third metal layer. a first conductive connection included in a subpixel driving circuit of the portion, the first conductive connection being connected to the base of the first pixel; The projection does not overlap with the corresponding orthogonal projection of the first anode on the base. The display panel according to claim 11 .

13. The display panel further includes a plurality of second light emitting elements and a plurality of third light emitting elements, The second light emitting element is a second array of second light emitting elements stacked in sequence in a direction away from the base. Each of the third light emitting elements includes a node, a second light emitting pattern, and a second cathode. The light emitting element includes two sub-light emitting elements disposed opposite each other along the first direction, Each of the optical elements is a third array of layers stacked in sequence in a direction away from the base. a node, a third light-emitting pattern, and a third cathode; The plurality of sub-pixel driving circuits include a second portion of sub-pixel driving circuits and a third portion of sub-pixel driving circuits. The second portion of the sub-pixel driving circuit is connected to the second light emitting element in a one-to-one correspondence. In response, the sub-pixel driving circuit of the second portion drives the corresponding second light emitting element to emit light. The third portion of the sub-pixel driving circuit is arranged to correspond to the sub-light emitting element in a one-to-one correspondence. In response, the sub-pixel driving circuit of the third portion drives the corresponding sub-light-emitting element to emit light. The The orthogonal projection of the first conductive connection included in the subpixel driving circuit of the second portion on the base is , which overlaps with the orthogonal projection of the corresponding second anode on the electrode, and the third portion The orthogonal projection of the first conductive connection included in the subpixel driving circuit on the base is 13. The method of claim 12, wherein the first anode overlaps an orthogonal projection of the corresponding third anode on the base. Display panel.

14. The gate of the first transistor is in direct contact with the corresponding gate scanning line pattern. The display panel according to claim 11 .

15. The orthogonal projection of the first electrode of the first transistor onto the base corresponds to the compensation function pas 12. The display panel of claim 11, which does not overlap with the orthogonal projection of the turn on the base. Ru.

16. The orthogonal projection of the second electrode of the first transistor onto the base corresponds to the compensation function pas- sage.

12. The display panel of claim 11, which does not overlap with the orthogonal projection of the turn on the base. Ru.

17. The sub-pixel driving circuit further includes a seventh transistor, is coupled to the reset signal line pattern, and the seventh transistor in the first portion of the subpixel driving circuit a second electrode of the seventh transistor coupled to the first anode; and a corresponding orthogonal projection of the compensation function pattern onto the base. and a seventh overlap region between the first electrode of the seventh transistor and the second electrode of the seventh transistor. The corresponding compensation function pattern is connected to the seventh overlap region through a via hole. By being coupled to the compensation function pattern, the corresponding initialization signal line pattern is The display panel of claim 11 , wherein the display panel is indirectly coupled to the first through-hole.

18. The orthogonal projection of the gate of the drive transistor onto the base corresponds to the compensation function pattern.

12. The method according to claim 11, wherein the projection of the first line at least partially overlaps the orthogonal projection of the first line on the base. The display panel described.

19. The orthogonal projection of the gate of the driving transistor on the base and the corresponding compensation function pattern The orthogonal projection of the first overlapping portion on the base includes a first overlapping portion. Rarely, The orthogonal projection of the first overlapping portion on the base corresponds to the first anode.

20. The method of claim 18, wherein the projection at least partially overlaps with an orthogonal projection on the base. Display panel.

20. The first electrode of the storage capacitor is connected to the gate scanning line pattern and the reset signal line pattern. The second electrode plate of the storage capacitor is made of the same material as the initialization signal line pattern. The fee is set at an orthogonal projection of a first plate of the storage capacitor on the base, and an orthogonal projection of a second plate of the storage capacitor on the base; Any orthogonal projection on the base corresponds to a corresponding orthogonal projection on the base of the gate scan line pattern. and a corresponding orthogonal projection of the light emission control signal line pattern on the base. The display panel according to claim 11 .

21. The functional film layer is located on a side of the gate insulating layer opposite to the base. and a first insulating layer for placing the first electrode of the storage capacitor, the gate scanning line pattern, and and the reset signal line pattern are both opposite to the base in the gate insulating layer. The second electrode plate of the storage capacitor and the initialization signal line pattern are both located on the front surface of the substrate. The indicia according to claim 11, which is located on a surface of the first insulating layer opposite the base. panel.

22. an orthogonal projection of a first plate of the storage capacitor on the base, and an orthogonal projection of a second plate of the storage capacitor on the base; Any orthogonal projection on the base is in the same plane as the orthogonal projection of the corresponding first anode on the base.

12. The display panel of claim 11, wherein the display panels are partially overlapping.

23. an orthogonal projection of a first plate of the storage capacitor on the base, and an orthogonal projection of a second plate of the storage capacitor on the base; Any orthogonal projection on the base corresponds to an orthogonal projection of the corresponding compensation function pattern on the base. The display panel of claim 11 , wherein the display panel partially overlaps with the first and second display panels.

24. The central region of the second plate of the storage capacitor includes an aperture, and an orthogonal projection of the aperture onto the base does not overlap with the orthogonal projection of the corresponding compensation feature pattern on the base. The display panel according to claim 11.

25. a difference in thickness between the compensation function layer and the power supply signal line layer in a direction perpendicular to the base; is within a threshold range, or the thickness difference between the compensation function layer and the data line layer is , within a threshold range.

26. The display panel further includes a plurality of second light-emitting elements, The second light emitting elements are stacked in sequence in a direction away from the base. a second anode, a second light-emitting pattern and a second cathode, the second anode being a fifth edge portion and a sixth edge portion provided opposite to each other along the second direction; a second intermediate portion located between the edge portion and the sixth edge portion, The orthogonal projection of the portion on the base overlaps with the orthogonal projection of the second light-emitting pattern on the base. Coming together, The orthogonal projection of the second intermediate portion on the base corresponds to the and at least partially overlapping the orthogonal projection on the base, the second intermediate portion on the base. The orthogonal projection is at least partially aligned with the orthogonal projection of the corresponding data line pattern on the base. The display panel of claim 1 .

27. The second light emission pattern is symmetrical about a second axis of symmetry, the second axis of symmetry being substantially parallel to the first axis of symmetry. a second axis of symmetry extending along a direction, and an orthogonal projection of the second axis of symmetry on the base corresponds to the power signal 27. The display panel of claim 26, located within an orthogonal projection of a line pattern on the base. Ru.

28. The display panel further includes a plurality of third light-emitting elements, Each of the third light emitting elements includes two sub-light emitting elements arranged opposite to each other along the first direction. Each of the sub-light-emitting elements includes a light-emitting element, and each of the sub-light-emitting elements is arranged along a direction away from the base. a third anode, a third light-emitting pattern and a third cathode, which are stacked in this order; The third anode has seventh and eighth edge portions provided opposite to each other along the second direction. an edge portion and a third intermediate portion located between the seventh edge portion and the eighth edge portion; and an orthogonal projection of the third intermediate portion on the base is a projection of the third light-emitting pattern. It overlaps with the orthographic projection on the base, The orthogonal projection of the third intermediate portion onto the base corresponds to the base of the corresponding data line pattern. at least partially overlaps with the orthogonal projection on the The seventh edge portion is orthogonally projected onto the base so as to project onto the base of the corresponding power supply signal line pattern.

27. The display panel of claim 26, at least partially overlapping an orthogonal projection on the base.

29. The first light-emitting element includes a red sub-pixel, the second light-emitting element includes a blue sub-pixel, 30. The display panel of claim 28, wherein the third light-emitting element comprises a green subpixel.

30. A display device comprising the display panel according to any one of claims 1 to 29.

31. A method for manufacturing a display panel, the display panel comprising: the manufacturing method further comprising: A functional film layer including a power supply signal line layer, a data line layer, and a compensation functional layer, , a power supply signal line pattern provided in each of the sub-pixel areas, and the data line layer a data line pattern provided in the sub-pixel area, the power supply signal line pattern being a first portion extending along a first direction, the data line pattern extending along the first direction; The compensation function layer extends through at least one of the sub-pixel areas. Producing a functional film layer including a functional pattern on a base; A plurality of first light emitting elements, each of the first light emitting elements being spaced apart from the base. The first anode, the first light-emitting pattern and the first cathode are laminated in order along the direction in which the first anode is disposed. a first anode having a first anode and a second anode having a first anode and a second anode, There is a first overlap area with the orthogonal projection of the turn on the base, and the corresponding data There is a second overlap region with the orthogonal projection of the data line pattern on the base, and the corresponding front a third overlap region between the compensation function pattern and the orthogonal projection on the base; The second overlap region is a region including the first overlap region and the third overlap region. A plurality of first light emitting elements are disposed between the functional film layer and the base. and (b) fabricating the display panel.

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