Power reduction in physical layer processing of wireless system

Abstract

To provide a system and a method for reducing power consumption in a base station.SOLUTION: A method receives data for a slot, processes the data in a first power mode, and assigns jobs associated with the data to one or more accelerators or one or more signal processing (DSP) cores. A scheduler receives jobs assigned by the controller and schedules a plurality of jobs for execution by at least one or more hardware accelerators and one or more DSP cores. After a controller completes processing of the data associated with the slot, the first power mode is transitioned to a second power mode that is a lower power mode than the first power mode, and an event manager transitions the controller from the second power mode to the first power mode in response to a trigger event.SELECTED DRAWING: Figure 9

Description

Background Art

[0001] [Cross - Reference to Related Applications] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 610,988, filed on December 15, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The power consumption of smartphones is crucial for the success of wireless networks due to the limited power of batteries. However, the power consumption by base stations in wireless networks such as 4G is usually not considered, and little effort has been made to reduce it. However, since the emergence of 5G wireless communication systems, due to several different reasons including the use of higher frequencies for 5G wireless communication systems compared to 4G wireless communication systems, the power consumption by base stations has substantially increased. Furthermore, since the emergence of 5G wireless communication, due to the higher frequencies of 5G wireless networks, the need to significantly increase the number of base stations to provide sufficient coverage due to the medium - to - high - frequency band characteristics of signals has led to an increase in power consumption. For example, in 5G wireless communication, approximately three times as many base stations are used compared to 4G wireless communication to achieve the same coverage. The increase in power consumption leads to inefficiencies in the system and also results in an increase in operating costs.

[0003] The above examples and related limitations regarding the related technical fields are intended to be illustrative rather than exclusive. Other limitations regarding the related technical fields will become apparent upon reading this specification and examining the figures.

Brief Description of the Drawings

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.

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DETAILED DESCRIPTION OF THE INVENTION

[0014] In the following disclosure, many different embodiments or examples are provided so as to implement different features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations being discussed.

[0015] Before various embodiments are described in more detail, it should be understood that the elements in such embodiments can be different, so the embodiments are not limiting. It should be similarly understood that the specific embodiments described and / or illustrated herein can be readily separated from the specific embodiments and, optionally, combined with any of several other embodiments, or replaced with elements in any of several other embodiments described herein. It should also be understood that the terms used herein are for the purpose of describing a particular concept and are not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the technical field to which the embodiments belong.

[0016] In wireless networks such as 5G, considering the significant increase in the number of base stations and their power consumption associated with the increase in signal frequency, it is necessary to reduce the power consumption by the base stations. By reducing the power consumed by base stations in a 5G wireless network (deployed for macrocells, microcells, and / or small cells), a reduction in the costs associated with the operation of such wireless networks is brought about.

[0017] According to some embodiments, a 5G wireless network can be adapted to a virtual radio access network (RAN) and / or an open radio access network (ORAN) in which the upper layer stack is processed on a cloud server and the physical (PHY) layer processing is offloaded to a hardware component such as a Peripheral Component Interconnect (PCI) card or a PCI Express (PCIe). It is understood that the PHY layer processing can be performed simultaneously for a plurality of cells in a wireless network that interfaces with one or more radio units.

[0018] Typically, PHY layer processing and radio frequency (RF) in a wireless network consume most of the power consumed within the system, for example, about 70% of the power. Therefore, efforts to reduce the power consumption associated with PHY layer processing and / or RF within the system can significantly reduce the overall power consumption of the system.

[0019] Resources, such as physical resource blocks (PRBs), memory, buffer space, and processing resources for signal processing and computing controller workloads (e.g., accelerators and / or digital signal processors (DSPs)), etc., are generally allocated by a base station, for example, in a 5G network, to a cell when the specific cell is configured. It is understood that 5G wireless networks are dynamic load systems that support a variety of use cases, each of which may have their own unique data workflows, such as broadband, Internet of Things (IoT), ultra-low latency, etc. Conventionally, resources have been allocated (statically) based on cell configuration, regardless of the load (traffic cell), resulting in inefficient power consumption. Therefore, managing the power consumption associated with PHY layer processing based on the (possibly dynamic) load is an effective way to reduce the power consumption in PHY layer processing. For example, placing components, such as memory components, processors, etc., in a lower power mode (e.g., sleep mode, clock gating to turn off) when not in use can be an effective tool in reducing power consumption.

[0020] Wireless frames in a wireless network can be divided into a plurality of sub-frames, where each sub-frame can be divided into a plurality of slots, where each slot can be used to transmit a plurality of orthogonal frequency-division multiplexing (OFDM) symbols (i.e., a plurality of symbols can be transmitted by one user, or a plurality of symbols can be transmitted by a plurality of users). As a non-limiting example, in 5G wireless communication, 100 MHz can be used with a sub-carrier spacing (SCS) of 30 KHz, the slot duration can be 500 μs, and can be used to communicate 14 OFDM symbols.

[0021] According to some embodiments, a base station may allocate a certain number of uplink slots in a shared memory for uplink data (by one or more processors, one or more accelerators, and / or one or more DSPs), may allocate a certain number of downlink slots in the shared memory for downlink data (by one or more processors, one or more accelerators, and / or one or more DSPs), and may allocate a certain number of slots in a flexible shared memory (which may be allocated to the uplink or downlink) (by one or more processors, one or more accelerators, and / or one or more DSPs). Generally, the allocation of the shared memory for uplink, downlink, or flexible slots is based on the cell configuration. For example, most users are involved in content downloading as opposed to content uploading, and thus, the base station may allocate 7 slots of the shared memory for downlink, 2 slots of the shared memory for uplink, and 1 slot of the shared memory as a flexible slot. It is understood that a 5G wireless network may be deployed in a time division duplex (TDD) mode, i.e., either for transmission or reception on the cell. Slots allocated for the uplink during the downlink consume power even when they are not being utilized, thereby resulting in inefficient power consumption. Similarly, slots allocated for the downlink during the uplink consume power even when they are not being utilized, thereby resulting in inefficient power consumption. In other words, regardless of the load, the slots allocated by the base station based on the cell configuration (e.g., 7 downlink slots, 2 uplink slots, and 1 flexible slot) result in power waste.

[0022] To manage power consumption and reduce waste, the shared memory used in PHY layer processing (for one or more processors, one or more accelerators, and / or one or more DSPs) can be partitioned into multiple memory banks. The multiple memory banks can form groups (e.g., rows of memory banks, columns of memory banks, etc.) that can be allocated as uplink slots, downlink slots, or flexible slots. By forming memory banks, it becomes possible to clock off the memory banks as needed, thereby reducing power consumption.

[0023] In a non-limiting example, during the uplink, the base station can clock off (gate) unused memory bank groups, such as memory banks allocated to the downlink, memory banks allocated to the downlink, and a specific group of memory banks allocated to the uplink based on the load. In a non-limiting example, during the downlink, the base station can clock off (gate) unused memory bank groups, such as memory banks allocated to the uplink, memory banks allocated to the uplink, and a specific group of memory banks allocated to the downlink based on the load. As a result, the unused memory banks no longer consume power, thereby reducing the power usage by the base station and more specifically by the shared memory used in PHY layer processing.

[0024] In some embodiments, one or more processors in a base station, e.g., central processing units (CPUs), are used for PHY layer processing. The one or more CPUs can process data and allocate one or more jobs to one or more hardware accelerators, or allocate one or more jobs to one or more DSPs. In a conventional system, the one or more CPUs remain in their full-power-on mode during times when the one or more CPUs are not processing any data, e.g., during times when one or more hardware accelerators are processing one or more jobs, during times when one or more DSPs are processing one or more jobs, etc. This results in power waste. Therefore, according to some embodiments, the one or more CPUs transition to a lower power mode (e.g., sleep mode) after completion of processing (e.g., after allocation of jobs to one or more accelerators, after allocation of jobs to one or more DSPs, etc.) to reduce power consumption. For example, the one or more CPUs can process data for a duration of two symbols to allocate jobs to one or more accelerators and / or one or more DSPs, and then transition to a lower power mode (e.g., sleep mode) for the remaining symbols within a given slot that includes 14 symbols, e.g., 12 symbols, etc. As a result, the power usage by the one or more CPUs is significantly reduced.

[0025] FIG. 1 shows an example of a wireless network 100 according to one aspect of the present embodiment. The figure shows the components as functionally separated, but such a representation is for illustrative purposes only. It will be apparent that the components depicted in this figure can be arbitrarily combined or divided into separate software, firmware, and / or hardware components. Furthermore, it will be apparent that such components can be executed on the same host or multiple hosts regardless of how they are combined or divided, and that multiple hosts can be connected by one or more networks.

[0026] The wireless network 100 may include a plurality of cells, for example, cells 102, 104, 106, 112, 114, 116, 122, 124, and 126. Each cell may include a plurality of cells. For example, cell 102 may include two cells, three cells, etc. Each of cells 102 to 126 is wirelessly coupled to a base station 130. The base station 130 may include one or more servers, one or more PCI cards, etc. for processing the PHY layer of data. The wireless network 100 conforms to a virtual RAN and / or ORAN architecture.

[0027] It is understood that the base station 130 includes one or more processors for processing data and allocating jobs to one or more DSPs and / or one or more hardware accelerators. The base station 130 can allocate resources such as slots for uplink, downlink, etc. based on cell configuration data, for example, the configuration data associated with cell 102, etc. For example, the base station 130 can allocate 7 slots for downlink, 2 slots for uplink, and 1 slot as a flexible slot to cells 102 to 126 based on the configuration data associated with (e.g., received from) the cell. The allocated flexible slot can be dynamically allocated between uplink / downlink as needed. It is understood that the upper layer processing associated with the communication between the base station 130 and the cells, such as cells 102 to 126, can be offloaded to a cloud server, while the PHY layer processing can be offloaded to a PCI card.

[0028] Figure 2 shows an example of base station processed data according to an aspect of the present embodiment. The base station includes a controller 210, a scheduler 220, a DSP 230, an accelerator 240, and a shared memory 250. In a non-limiting example, the controller 210 can include one or more processors, such as a CPU. Configuration data 202 associated with a given cell, such as cell 102, cell 104, cell 116, etc., can be received by the controller 210. The controller 210 can configure and allocate resources within the base station for the cell based on the configuration data 202.

[0029] Each of the components in FIG. 2 is a dedicated hardware block / component that includes one or more processors (e.g., microprocessors) and an on-chip memory unit that stores software instructions. As detailed below, when the software instructions are executed by the processors, each of the hardware components becomes a special-purpose hardware component for managing power and executing job commands. In some embodiments, a system as shown in FIG. 2 exists on a single chip, e.g., a system-on-chip (SOC).

[0030] The shared memory 250, e.g., 96 MB, can be decomposed into smaller memory banks, e.g., 24 memory banks of 4 MB each. In this non-limiting example, the shared memory 250 can be decomposed into a plurality of memory banks, e.g., memory banks 222A - 222X, where the group of memory banks or each individual memory bank can be clock-gated to turn off when not in use to reduce the power consumption of the system. According to a non-limiting example, the plurality of memory banks within the shared memory 250 can be grouped together and distributed to the uplink slot, downlink slot, or distributed as flexible slots that can be dynamically assigned to the uplink or downlink as needed. The controller 210 can distribute a certain number of memory banks of the shared memory 250 to the downlink slot, distribute a certain number of memory banks of the shared memory 250 to the uplink slot, and distribute a certain number of memory banks of the shared memory 250 to the flexible slot based on the configuration data 202. The shared memory 250 can be used by one or more of the controller 210, DSP 230, and accelerator 240.

[0031] In this example, and for purposes of illustration not to be construed as limiting the scope of the present embodiment, the controller 210 may group together the memory banks 222A-222F based on the configuration data 202 and allocate them as a downlink memory bank 252 to a downlink slot. In a non-limiting example, the controller 210 may group together the memory banks 222G-222L based on the configuration data 202, allocate them to an uplink slot, group together the memory banks 222M-222R, allocate them to another uplink slot, group together the memory banks 222S-222X, allocate them to yet another uplink slot, and form an uplink memory bank 254. In other words, while one row of memory banks from the shared memory 250 is allocated to one downlink slot, three rows of memory banks from the shared memory 250 are allocated to three uplink slots. In this example, the memory banks are not allocated to flexible slots, but in other examples, multiple memory banks may be grouped and allocated to flexible slots. In some examples, seven memory bank groups may be formed, each of which may be allocated to a downlink slot, two memory bank groups may be formed, each of which may be allocated to an uplink slot, and one memory bank group may be formed, which is allocated as a flexible slot.

[0032] It is understood that the number of memory banks within each group can be different. For example, the number of memory banks allocated (grouped) for a certain uplink slot can be different from that of another uplink slot. In other words, as shown, a certain group of memory banks allocated to an uplink slot can include 5 memory banks, and another group of memory banks can have a different number of memory banks, such as 3 memory banks, 4 memory banks, etc. It is understood that the number of memory banks allocated (grouped) for a certain downlink slot can be different from the number of memory banks within different downlink slots. In other words, as shown, a certain group of memory banks allocated to a downlink slot can include 5 memory banks, and another group of memory banks allocated to a different downlink slot (not shown here) can have a different number of memory banks, such as 3 memory banks, 4 memory banks, etc. Furthermore, it is understood that the number of memory banks allocated (grouped) for a downlink slot can be different from the number of memory banks within an uplink slot. In other words, showing 5 memory banks per group is for illustrative purposes only and should not be construed as limiting the scope of this embodiment. Furthermore, each memory bank can have the same capacity, such as 4 MB, or they can have different capacities from each other. For example, one memory bank can be 4 MB, while another memory bank can be 16 MB.

[0033] In a non-limiting example, it is understood that each group of memory banks may have its own clock signal. For example, memory banks 222A to 222F may have their own clock signal 262, while memory banks 222G to 222L may have their own clock signal 264, while memory banks 222M to 222R may have their own clock signal 266, while memory banks 222S to 222X may have their own clock signal 268. Each group can be clocked off when not in use to manage their power consumption, as will be described in more detail with respect to FIGS. 3A to 4D below. For example, the downlink memory bank 252 can be clocked off by turning off the clock signal 262 when the base station is involved in the uplink, and the uplink memory bank 254 can be clocked off by turning off the clock signals 264 to 268 when the base station is involved in the downlink. In some non-limiting examples, it is understood that each memory bank can be individually clocked as desired so that the power consumption by the memory banks can be controlled at a finer granularity level. Variations regarding power management are described in more detail in FIGS. 3A to 4D below.

[0034] According to some embodiments, when resources, such as memory banks, are allocated based on the configuration data 202 (as described above), the base station may start processing data communication from cells, such as cells 102 to 126. Data (PHY layer data) associated with a given slot may be received by the controller 210 from one or more of the cells 102 to 126. The controller 210 may process the received data (slot) and determine whether the data is for uplink or downlink. Therefore, unused memory banks may be clocked off to reduce power consumption. For example, if the controller 210 determines that the received data is for uplink, the power of the memory banks allocated for downlink slots may be turned off (e.g., by clocking them off), and if the controller 210 determines that the received data is for downlink, the power of the memory banks allocated for uplink slots may be turned off (e.g., by clocking them off), thereby reducing the power consumption of the base station.

[0035] In some embodiments, the controller 210 may process the received data and generate and allocate jobs for other processing components. In other words, signal processing may be offloaded from the controller 210 to other components, such as the accelerator 240, the DSP 230, etc. For example, the controller 210 may allocate a specific job associated with the received slot to the DSP 230 and allocate a specific job associated with the received slot to the accelerator 240. It is understood that the accelerator 240 may be one or more hardware accelerators (e.g., field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.) configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equivalence, demapping, etc. It is understood that the DSP 230 may include one or more DSP cores configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, timing estimation, etc.

[0036] It is understood that a subset of the accelerators from the accelerator 240 may be placed in a lower power mode when they are not in use (idle) to reduce power consumption. Similarly, a subset of the DSPs from the DSP 230 may be placed in a lower power mode when they are not in use (idle) to reduce power consumption. The jobs allocated by the controller 210 are scheduled for the DSP 230 and / or the accelerator 240 using the scheduler 220.

[0037] In some embodiments, it is understood that certain event data 204 may be received by the scheduler 220 and / or the controller 210. The event data 204 may be used to further manage the power consumption by the controller 210, which will be described in great detail in FIGS. 6-7B below.

[0038] It is understood that the base station may include other components not shown for the sake of simplicity. For example, the base station may also include other memory components, such as DDR memory, one or more databases, etc.

[0039] Referring now to FIG. 3A, a non-limiting example of the distribution of memory banks to slots is shown for illustrative purposes. In FIG. 3A, the controller 310 may be similar to that of the controller 210, and the on-chip shared memory 350 may be similar to the shared memory 250. The memory banks 322A-322X are similar to the memory banks 222A-222X in FIG. 2, and the clock signals 362-368 are similar to the clock signals 262-268. The memory banks 322A-322F may be grouped together and allocated to the downlink slot as the downlink memory bank 352, while the memory banks 322G-322L, the memory banks 322M-322R, and the memory banks 322S-322X are allocated to the uplink slot as the uplink memory banks 354, respectively.

[0040] Referring now to FIG. 3B, data is received by a controller 310 from a cell, such as cell 102. The controller 310 may determine that the received data is for the downlink. Since the system is deployed in a TTD system, data is either transmitted or received, but not both. Thus, since the received data indicates the downlink, it is determined that the memory banks 322A - 322F allocated to the downlink slots are utilized, while the uplink memory bank 354 is not utilized. Therefore, since the slot is for the downlink and not the uplink, during the current slot, the memory banks 322G - 322X are clocked off, for example, using clock signals 364 - 368. By clocking off the memory banks 322G - 322X, the power consumption that would otherwise result in a waste of power as the memory banks 322G - 322X are not being used for the current slot being processed is reduced. Further, generally, uplink processing is inherently more complex and thus consumes more power. Therefore, when the memory banks 322G - 322X are not in use, turning off the memory banks 322G - 322X allocated to the uplink results in significant power savings.

[0041] Referring now to FIG. 3C, data is received by a controller 310 from a cell, such as cell 126. The controller 310 may determine that the received data is for an uplink. Since the system is deployed in a TTD system, the data is either transmitted or received, but not both. Thus, since the received data indicates an uplink, it is determined that the memory banks 322G - 322X allocated to the uplink slots are utilized, while the downlink memory bank 352 is not utilized. Therefore, since the slot is for uplink rather than downlink, during the current slot, the memory banks 322A - 322F are clocked off, for example using a clock signal 362. By clocking off the memory banks 322A - 322F, power consumption that would otherwise result in power waste as the memory banks 322A - 322F are not being used for the current slot being processed is reduced.

[0042] Referring now to FIG. 3D, data is received by controller 310 from a cell, e.g., cell 126. Controller 310 may determine that the received data is for uplink. Since the system is deployed in a TTD system, data is either transmitted or received, and not both. Thus, since the received data indicates an uplink, memory banks 322G - 322X allocated to the uplink slot are utilized, while downlink memory bank 352 is determined not to be utilized. Further, the system may determine that not all memory banks within uplink memory bank 354 are used based on the load associated with the wireless network. For example, controller 310 may determine that memory banks 322M - 322X are used for two uplink slots. In other words, even if the data being processed is associated with the uplink, memory banks 322G - 322L within uplink memory bank 354 may be determined to be unnecessary. Thus, since the slot is for uplink and not downlink, memory banks 322A - 322F from downlink memory bank 352 are clocked off during the current slot, e.g., using clock signal 362, and memory banks 322G - 322L allocated to the uplink slot are not used, so memory banks 322G - 322L are clocked off. By clocking off memory banks 322A - 322F and memory banks 322G - 322L, power consumption that would otherwise result in power waste as memory banks 322A - 322L are not used for the current slot being processed is reduced. In other words, power consumption is limited to the memory banks in use, thereby reducing power consumption.

[0043] Figures 4A to 4D show an example of managing power associated with shared memory in a dynamic configuration of a wireless network according to an aspect of the present embodiment. Figures 4A to 4D show the power consumption for each memory bank that can be controlled in a more granular manner. In Figure 4A, the controller 410 can be similar to that of the controller 310, and the on-chip shared memory 450 can be similar to the on-chip shared memory 350. The memory banks 422A to 422X are similar to the memory banks 322A to 322X in Figures 3A to 3D, except that the power consumption by each memory bank is individually controlled by its respective clock signals 462 to 468. The memory banks 422A to 422F are grouped together and can be allocated to the downlink slot as the downlink memory bank 452, while the memory banks 422G to 422L, the memory banks 422M to 422R, and the memory banks 422S to 422X are allocated to the uplink slot as the uplink memory bank 454, respectively.

[0044] In this non-limiting example, data is received by controller 410 from a cell, e.g., cell 102. Controller 410 may determine that the received data is for uplink. Since the system is deployed in a TTD system, data is either transmitted or received, but not both. Accordingly, it is determined that memory banks 422A - 422F allocated to downlink slots are not utilized. Therefore, memory banks 422A - 422F may be clocked off using clock signal 462. Further, controller 410 may determine that a subset of the memory banks allocated to uplink slots may be required based on the load on the wireless network. Accordingly, the number of memory banks that may be required is adjusted, and unused memory banks are clocked off to reduce power consumption. For example, memory banks 422G - 422Q may be determined to be unnecessary based on the load even if they are allocated to uplink slots, and thus are clocked off to reduce power consumption. Clock signals 464 and 466 may be used to clock off memory banks 422G - 422Q during the processing of the current slot, thereby reducing power consumption. By clocking off memory banks 422G - 422Q, power consumption that would otherwise result in a waste of power is reduced because memory banks 422G - 422Q are not being used for the current slot being processed.

[0045] Figure 4B is substantially the same as that of Figure 4A, except that controller 410 determines that the load on the wireless network is higher compared to Figure 4A. Therefore, more memory banks are required to process the current slot associated with the uplink. In this non-limiting example, memory banks 422G - 422O are clocked off to reduce power consumption in addition to downlink memory bank 452 being clocked off because they are not required to process the current slot.

[0046] FIG. 4C is substantially the same as that of FIG. 4A, except that the controller 410 determines that the load on the wireless network is lighter compared to FIG. 4A. Therefore, fewer memory banks are required to process the current slot associated with the uplink. In this non-limiting example, in addition to the downlink memory bank 452 being clocked off because the memory banks 422G-422R and 422W-422X are unnecessary for processing the current slot, they are also clocked off to reduce power consumption.

[0047] FIG. 4D is substantially the same as FIG. 4A. In this non-limiting example, data is received by the controller 410 from a cell, such as cell 102. The controller 410 may determine that the received data is for the downlink. Since the system is deployed in a TTD system, the data is either transmitted or received, but not both. Therefore, it is determined that the memory banks 422G-422X allocated to the uplink slot are not utilized. Thus, the memory banks 422G-422X can be clocked off using the clock signals 464-468. Further, the controller 410 may determine that a subset of the memory banks allocated to the downlink slot may be required based on the load on the wireless network. Accordingly, the number of memory banks that may be required is adjusted, and the unused memory banks are clocked off to reduce power consumption. For example, the memory banks 422A-422D may be determined to be unnecessary based on the load even if they are allocated to the downlink slot, and thus are clocked off to reduce power consumption. The clock signal 462 may be used to clock off the memory banks 422A-422D during the processing of the current slot, thereby reducing power consumption. By clocking off the memory banks 422A-422D and 422G-422X, the power consumption that would otherwise result in a waste of power is reduced because the memory banks 422A-422D and 422G-422X are not used for the current slot being processed.

[0048] It should be understood that FIGS. 3A to 4D are for illustrative purposes and should not be construed as limiting the scope of the present embodiment, and illustrate controlling the power consumption of a memory bank using a clock signal. For example, the clock signal can be used together with gate logic for controlling power-on or power-off of the memory bank.

[0049] FIG. 5 shows an example of a base station 500 having a shared memory for data processing according to an aspect of the present embodiment. The base station 500 may include one or more controllers 510A to 510N, one or more DSPs 550A to 550N, one or more accelerators 540A to 540N, and a shared memory that can be decomposed into a plurality of memory banks 522A to 522K, for example, 96 MB. It is understood that one or more controllers 510A to 510N, one or more DSPs 550A to 550N, one or more accelerators 540A to 540N, and a plurality of memory banks 522A to 522K can be coupled to each other via an interconnect 540, for example, InterconnectX. It is understood that the controller 510A may include a plurality of controllers, for example, CPUs. Similarly, each of the controllers 510B to 510N may include a plurality of controllers. It is further understood that the DSP 550A may include a plurality of DSPs. Similarly, each of the DSPs 550B to 550N may include a plurality of DSPs. Further, it is understood that the accelerator 540A may include a plurality of accelerators, for example, FPGAs, ASICs, etc. Similarly, each of the accelerators 540B to 540N may include a plurality of accelerators. It is understood that the DSPs, accelerators, controllers, and memory banks in FIG. 5 may be the same as those described in FIGS. 2 to 4D. Further, as described above, each controller, each DSP, each accelerator, and each memory bank can be clocked off (placed in a lower power mode) when not needed, thereby reducing power consumption. It is understood that the memory banks 522A to 522K may each be 4 MB of memory. In some non-limiting examples, it is further understood that the sizes of at least two of the memory banks may be different from each other, for example, one may be 4 MB and another may be 8 MB.

[0050] As described above, the utilization rate of the shared memory varies based on the number of supported cells and bandwidth (i.e., based on the load on the wireless network). In a non-limiting example of TDD, in 18 cells having a 20 MHz bandwidth, and 7 downlink slots and 3 uplink slots, the embodiments described above enable 14 uplink banks to be clock-gated for approximately 70% of the time, thereby providing significant power savings associated with PHY layer processing. The reduction in power consumption using the embodiments described above can range from approximately 26% savings in the uplink to approximately 62% savings for the downlink, with an average savings rate of approximately 52%.

[0051] It is understood that in a 5G wireless network, it is time-critical, and the time budget that a system (e.g., a base station) has for analyzing the received data of the configured cells and appropriately creating jobs may be very limited. Therefore, as described above, a combination of an accelerator and / or a DSP may be used. In a non-limiting example, a PHY configured with a 15 kHz subcarrier spacing has a 1 ms time slot for processing and the next 1 ms slot for transmitting or receiving 14 OFDM symbols over the air. The allocated time slot can be further reduced by increasing the subcarrier spacing. For example, the time slot for a subcarrier spacing increased to 30 kHz is halved. To manage the limited time budget, the PHY layer processing may utilize two subsystems. The first subsystem may include a DSP, an accelerator, a shared memory, etc., as described above. The second subsystem may include a CPU subsystem, as described in FIG. 6 below.

[0052] FIG. 6 shows an example of a processing unit of a base station in a wireless network according to an aspect of the present embodiment. The processing unit may include a controller 610 (CPU thread), a scheduler 620, and an event manager 630. The controller 610 can be one or more of the controllers as described in FIGS. 2 to 5. The controller 610 receives data in the wireless network. The controller 610 is configured to process data in a first power mode (e.g., full power-on mode), and based on the processing, may allocate a first set of jobs to at least one or more accelerators and / or a second set of jobs to at least one or more DSPs. It is understood that the accelerators and DSPs are the same as those described in FIGS. 2 to 5. When the allocation of jobs for processing is completed (i.e., when the processing of data by the controller 610 is completed), the allocation of the jobs is sent to the scheduler 620 for scheduling the execution by the accelerators and / or DSPs.

[0053] Since the controller 610 has completed its processing of the current data (e.g., the allocation of jobs to the DSP and / or accelerators), it is understood that it transitions to a second power mode, which is a lower power mode than the first power mode (e.g., sleep mode). According to a non-limiting example, the event manager 630 manages the power mode associated with the controller 610. In a non-limiting example, the event manager 630 causes the controller 610 to transition to the second power mode, and in another non-limiting example, the controller 610 automatically transitions to the second power mode. In a non-limiting example, it is understood that the event manager 630 is further configured to cause the controller 610 to transition from the second power mode to the first power mode (to wake up the controller 610) in response to a trigger event, such as an interrupt, the elapse of a configurable amount of time, etc.

[0054] The management of the power consumption of the controller 610 regarding downlink processing will be described with respect to a non-limiting example in FIG. 7A. In FIG. 7A, data associated with the downlink slot 702 is received, followed by the next set of data associated with the downlink slot 705. The controller 610 processes the data associated with the downlink slot 702. In a non-limiting example, (when the controller 610 is in the sleep mode) the controller 610 is activated by the event manager 630 when data is received, as a result of which the data can be processed. In this non-limiting example, the controller 610 processes the data within the time amount for 2 symbols (e.g., analyzes the received data) (i.e., the controller 610 is in the active state during the controller activation 703), and can create / assign the job associated with the data within the downlink slot 702 for the DSP and / or the accelerator.

[0055] The assignment of the job is sent to the scheduler 620 and scheduled for execution by the DSP and / or accelerator. For example, the created / assigned job can be queued in a queue within the scheduler 620. Since the controller 610 has completed its processing (i.e., the analysis and assignment / creation of jobs for the accelerator and / or DSP), it is transitioned from the first power mode to the second power mode by the event manager 630. Therefore, the controller 610 remains in the second power mode (i.e., controller sleep 704) until a trigger event occurs. In this non-limiting example, the trigger event is receiving data associated with the downlink slot 705 and can be a generated interrupt. Therefore, the event manager 630 activates the controller 610 to process the data associated with the downlink slot 705. In this non-limiting example, the controller 610 is in an active state during the controller activation 706 required for it to process the data associated with the downlink slot 705 (i.e., the amount of time required for it to assign jobs associated with the data within the downlink slot 705 to the DSP and / or accelerator). When the assignment of the jobs associated with the data within the downlink slot 705 is determined by the controller 610, the event manager 630 causes the controller 610 to transition to the second power mode as described above. As shown, the controller 610 spends a significant amount of time (e.g., the amount of time associated with 12 symbols) in the second power mode and is only in an active state for a time sufficient to complete its processing (e.g., which may require about 2 symbols, the analysis and assignment / creation of jobs for the DSP and / or accelerator). Therefore, the power consumed by the controller 610 is significantly reduced. Since there are typically multiple controllers, e.g., 6 controllers, etc., in the system, this results in an even more significant reduction in power.The downlink slot is processed 70% of the time, so it is understood that significant power reduction is achieved by the power management of the controller 610 described above.

[0056] It is understood that the above example describes that the trigger event is an interrupt generated as a result of receiving new data. However, it is understood that the trigger event can be the elapse of a configured amount of time. For example, the controller 610 can transition to the second power mode over a configured amount of time (e.g., an amount of time that can be configured), and when the configured amount of time has elapsed, it transitions from the second power mode to the first power mode. In a non-limiting example, the trigger event can be the one that occurs first out of the elapse of a configured amount of time or a generated interrupt. In other words, the controller 610 can remain in the second power mode in the absence of a trigger event, e.g., an interrupt, and transition to the first power mode after the elapse of a configured amount of time, or it can transition to the first power mode before the elapse of a configured amount of time if an interrupt is received before the elapse of a configured amount of time. In a non-limiting example, the interrupt can be associated with the time report described with respect to FIG. 7B for uplink data.

[0057] Referring now to FIG. 7B, the management of the power consumption of the controller 610 regarding uplink processing is described. In this example, data associated with the uplink slot 709 is received, followed by data associated with the uplink slots 712 and 715 respectively. Each uplink slot includes 14 symbols for illustrative purposes. According to a non-limiting example, it is understood that the controller 610 may process uplink data that may require about 3 symbols (3-symbol length). For example, the controller 610 may analyze the received data and allocate / create a job (i.e., assignment 721) associated with the data within the uplink slot 709 for one or more DSPs and / or one or more accelerators, which may require up to 3 symbols. The allocated / created job is sent to the scheduler 620 (e.g., queued in a queue within the scheduler 620) and may be scheduled for execution by one or more DSPs and / or one or more accelerators. Therefore, after the first 3 symbols of the data within the uplink slot 709, the controller 610 is transitioned from the first power mode to the second power mode by the event manager 630. In one example, the controller 610 is transitioned from the first power mode to the second power mode until a trigger event, such as the elapse of a configured amount of time, an interrupt, event data, etc., occurs. In this example, the controller 610 remains in the second power mode for a controller sleep 711 time period corresponding to an amount of time equivalent to 9 symbol lengths in this example. The event data 722 may be generated by one or more of the DSPs and / or one or more of the accelerators, etc., associated with processing each of their respective data scheduled for execution prior to the data associated with the uplink slot 709, for example. The event data 722 may include, in a non-limiting example, a time report, which may require an equivalent of 2 symbol lengths.

[0058] Event data 722 causes an interrupt to wake up the controller 610, for example, to transition the controller 610 from a second power mode to a first power mode. After the event data 722, the next set of data associated with the uplink slot 712 may follow. Therefore, the controller 610 spends another three-symbol length to analyze the data associated with the uplink slot 712 and assign / create jobs for one or more accelerators and / or one or more DSPs. As described above, the assigned / created jobs are sent to the scheduler 620 (e.g., queued in its queue) and scheduled for execution by the DSP and / or accelerator. In a non-limiting example, the controller 610 stays in the first power mode for the amount of time of the controller wake-up 713 (equivalent to five symbols) to process the event data 722 and the data associated with the uplink slot 712. Since the controller 610 has completed processing the data associated with the uplink slot 712, it is understood that it is transitioned from the first power mode to the second power mode by the event manager 620.

[0059] The controller 610 remains in the second power mode for a controller sleep 714 time (9 symbol lengths in this example) until the following trigger events occur, such as an interruption, event data, new data for the next uplink slot, the elapse of a configured amount of time, etc. In this non-limiting example, event data 724 generated by one or more of the DSPs associated with data processing for the uplink slot 709 and / or one or more of the accelerators can be received. Thus, an interruption can be generated to shift the controller 610 from the second power mode to the first power mode. Similar to the previous case, the next set of data associated with the uplink slot 715 is received and analyzed, and a job is created / assigned by the controller 610 for one or more of the accelerators and / or DSPs. In other words, the controller 610 remains in the first power mode for a controller startup 716 time (5 symbol lengths in this example) before it is shifted by the event manager 620 to the second power mode for a controller sleep 717 time.

[0060] As shown in FIGS. 7A and 7B, the controller spends a significant amount of time in a lower power mode compared to a conventional system that was always on regardless of whether it was processing data or not. As a result, the power consumed by the controller is significantly reduced.

[0061] As described with reference to FIGS. 6-7B, it is understood that the power management associated with the controller can operate in a polling mode or an interrupt mode. In the polling mode, the controller 610 can call the event manager 630 to poll for events, such as the elapse of a configured amount of time, a time report generated by the DSP and / or the accelerator, etc. After calling the event manager 630, the controller 610 can transition to a second power mode (e.g., sleep mode) for a configured amount of time. During the configured amount of time, the controller 610 remains in the second power mode if no trigger event other than the elapse of the configured amount of time at which the controller 610 transitions back to the first power mode occurs. At that point, the controller 610 can process any pending tasks and, when the processing is complete, can transition to the second power mode. If there are no pending tasks when the controller 610 transitions from the second power mode to the first power mode, it is understood that it will transition back to the second power mode. The process can be repeated many times. However, if a trigger event other than the elapse of the configured time occurs, the controller 610 is transitioned to the first power mode by the event manager 630 before the configured amount of time has elapsed. When in the first power mode, the controller 610 processes any pending requests and, upon completion, transitions back to the second power mode. The process can be repeated many times.

[0062] In contrast, in interrupt mode, the controller 610 transitions itself from the first power mode to the second power mode when it has completed its processing (e.g., data analysis and assignment / creation of jobs for one or more of the DSP and / or accelerator). The controller 610 may remain in the second power mode until an interrupt is received by the event manager 630. The event manager 630 wakes up the controller 610 (i.e., transitions the controller 610 from the second power mode to the first power mode). The controller 610 may complete the processing of any pending tasks and, when it has completed its processing, may transition itself back to the second power mode. This process may be repeated multiple times.

[0063] The embodiments described in FIGS. 6-7B result in a power consumption reduction of about 85% for the downlink and about 60% for the uplink, with an average reduction rate of about 78%.

[0064] FIG. 8 shows an exemplary flowchart for managing power associated with shared memory in a processor of a base station according to one aspect of the present embodiment. As described above with respect to FIGS. 1-5, at step 810, cellular configuration data and network traffic data are received. As described with respect to FIGS. 1-5, the cellular configuration data is associated with a plurality of cells within a wireless network. As described with respect to FIGS. 1-5, at step 820, a first subset of memory banks of a plurality of memory banks of the on-chip shared memory is allocated to uplink slots based on the cellular configuration. As described above, at step 830, a plurality of uplink groups (e.g., rows) are formed from the first subset of memory banks. In a non-limiting example, one uplink group may include one memory bank. As described above with respect to FIGS. 1-5, at step 840, a second subset of memory banks of a plurality of memory banks of the on-chip shared memory is allocated to downlink slots based on the cellular configuration. As described above, at step 850, a plurality of downlink groups are formed from the second subset of memory banks. In a non-limiting example, one downlink group may include one memory bank. As described above, at step 860, a first subset of memory banks of a plurality of memory banks is clocked off in response to network traffic data being associated with downlink slots. As described above, at step 870, a second subset of memory banks of a plurality of memory banks is clocked off in response to network traffic data being associated with uplink slots.

[0065] In some embodiments, a subset of the uplink groups among the plurality of uplink groups is clocked off based on the load associated with the network traffic data, in response to the network traffic data being associated with a downlink slot. In some embodiments, a subset of the downlink groups among the plurality of downlink groups is clocked off based on the load associated with the network traffic data, in response to the network traffic data being associated with an uplink slot.

[0066] In some embodiments, a third subset of the memory banks among the plurality of memory banks is allocated as a flexible slot configured as an uplink slot or a downlink slot in response to the load associated with the network traffic. As described above, the wireless network can be deployed in TDD. It is understood that the number of memory banks within each uplink group can be the same as or different from each other. It is further understood that the number of memory banks within each downlink group can be the same as or different from each other. Furthermore, the number of memory banks within one uplink group can be the same as or different from one downlink group.

[0067] It is understood that the method may include a stage of processing the physical layer of network traffic data. In a non-limiting example, the method may further include a stage of determining whether the traffic data is associated with either the uplink or the downlink. In some embodiments, the method may also include scheduling a first plurality of jobs for one or more hardware accelerators and scheduling a second plurality of jobs for one or more DSP cores, where the one or more DSP cores are configured to execute at least one or more operations associated with channel estimation. The hardware accelerator may be configured to execute at least one or more operations associated with FEC calculation, equivalence, and demapping. The DSP core may be configured to execute one or more of DMR signal generation, frequency error calculation, and timing estimation.

[0068] FIG. 9 shows an exemplary flowchart for managing power associated with a processor of a base station according to one aspect of the present embodiment. As described in FIGS. 1 and 6 to 7B, in step 910, in a wireless network, a controller receives data associated with a slot. The wireless network can be deployed in TDD. As described in FIGS. 1 and 6 to 7B, in step 920, the data is processed in a first power mode. As described in FIGS. 1 and 6 to 7B, in step 930, a plurality of jobs associated with the data are assigned to at least one or a plurality of hardware accelerators or to one or a plurality of DSP cores. As described in FIGS. 1 and 6 to 7B, in step 940, after the controller completes processing the data associated with the slot, the controller transitions from the first power mode to the second power mode. It is understood that the second power mode is a lower power mode compared to the first power mode when the controller is processing the data associated with the slot. As described in FIGS. 1 and 6 to 7B, in step 950, a plurality of jobs are scheduled for at least one or a plurality of hardware accelerators or for one or a plurality of DSP cores. As described in FIGS. 1 and 6 to 7B, in step 960, the controller transitions from the second power mode to the first power mode in response to a trigger event.

[0069] It is understood that the data can be downlink data and the slot can be a downlink slot. As described in FIGS. 1 and 6 to 7B, it is understood that the trigger event can be associated with receiving another data associated with another slot in the wireless network.

[0070] It is understood that the data can be uplink data and the slot can be an uplink slot. As described in FIGS. 1 and 6 to 7B, according to some non-limiting examples, the trigger event is associated with a subset of jobs associated with a plurality of jobs for at least one or more hardware accelerators, or another subset of jobs associated with a plurality of jobs for one or more DSP cores, and is to receive data.

[0071] In some embodiments, the controller transitions from the first power mode to the second power mode over a configured amount of time. It is understood that the step of transitioning the controller from the second power mode to the first power mode may be in response to the elapse of a configured amount of time and further in response to the absence of a trigger event. In a non-limiting example, the method further comprises the step of the controller requesting polling after the controller has transitioned to the first power mode, and in the absence of a trigger event, the controller transitions from the first power mode to the second power mode. It is understood that the controller may transition from the second power mode to the first power mode during a configured amount of time and in response to the reception of a trigger event.

[0072] In some embodiments, the controller remains in the second power mode until an interrupt is generated and sent to the controller to cause the controller to transition from the second power mode to the first power mode. In a non-limiting example, the method includes a stage in which at least one or a plurality of hardware accelerators process a subset of jobs among the plurality of jobs, and a stage in which one or a plurality of DSP cores process another subset of jobs among the plurality of jobs. As described above, the one or more hardware accelerators are configured to execute at least one or a plurality of operations associated with FEC calculation, equalization, and demapping, and the one or more DSP cores are configured to execute at least one or a plurality of operations associated with channel estimation, DMR signal generation, frequency error calculation, and timing estimation.

[0073] The foregoing description of various embodiments of the subject matter of the claims has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter of the claims to the exact forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others of ordinary skill in the relevant art to understand the invention for various embodiments and the various modifications suitable for the particular uses contemplated.

Claims

1. A controller configured to receive data associated with a slot in a wireless network, wherein the controller is further configured to process the data in a first power mode and assign a number of jobs associated with the data to at least one or more hardware accelerators or to one or more digital signal processing (DSP) cores; a scheduler configured to receive the jobs assigned by the controller, the scheduler further configured to schedule the jobs for execution by the at least one or more hardware accelerators and the one or more DSP cores; and an event manager configured to manage a power mode associated with the controller, where the event manager is configured to transition the controller from the first power mode to a second power mode after the controller completes the processing of the data associated with the slot, where the second power mode is a lower power mode compared to the first power mode when the controller is processing the data associated with the slot, and the event manager is further configured to transition the controller from the second power mode to the first power mode in response to a trigger event. A system comprising:

2. 2. The system of claim 1, wherein the data is downlink data and the slots are downlink slots.

3. The system of claim 1 or 2, wherein the trigger event is associated with receiving different data associated with a different slot in the wireless network.

4. 2. The system of claim 1, wherein the data is uplink data and the slots are uplink slots.

5. 5. The system of claim 4, wherein the trigger event is receiving data associated with a subset of jobs associated with the plurality of jobs for the at least one or more hardware accelerators or associated with another subset of jobs associated with the plurality of jobs for the one or more DSP cores.

6. The system of claim 1 or 2, wherein the event manager is configured to transition the controller from the first power mode to the second power mode for a configured amount of time.

7. 7. The system of claim 6, wherein the controller is configured to transition from the second power mode to the first power mode in response to the lapse of the configured amount of time and further in response to an absence of the trigger event.

8. 8. The system of claim 7, wherein the controller requests polling from the event manager after the controller is transitioned to the first power mode, and the controller is transitioned from the first power mode to the second power mode in the absence of the trigger event.

9. 7. The system of claim 6, wherein the controller is configured to transition from the second power mode to the first power mode for the configured amount of time and in response to receiving the trigger event.

10. 3. The system of claim 1 or 2, wherein the controller remains in the second power mode until an interrupt is generated by the event manager and sent to the controller to transition the controller from the second power mode to the first power mode.

11. the at least one or more hardware accelerators configured to process a subset of the jobs of the plurality of jobs assigned by the controller; and the one or more DSP cores configured to process a different subset of the plurality of jobs assigned by the controller; The system of claim 1 or 2, further comprising:

12. The system of claim 1 or 2, wherein the controller, the scheduler, and the event manager are in a base station deployed in time division duplex (TDD).

13. 3. The system of claim 1 or 2, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping, and the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

14. receiving, in a wireless network, data associated with a slot, by a controller; processing the data in a first power mode; assigning a plurality of jobs associated with the data to at least one or more hardware accelerators or to one or more digital signal processing (DSP) cores; transitioning the controller from the first power mode to a second power mode after the controller completes the processing of the data associated with the slot, where the second power mode is a lower power mode compared to the first power mode when the controller is processing the data associated with the slot; Scheduling the jobs to at least one or more hardware accelerators or to one or more DSP cores; and transitioning the controller from the second power mode to the first power mode in response to a trigger event. A method for providing the above.

15. The method of claim 14 , wherein the data is downlink data and the slots are downlink slots.

16. The method of claim 14 or 15, wherein the trigger event is associated with receiving another data associated with another slot in the wireless network.

17. The method of claim 14 , wherein the data is uplink data and the slots are uplink slots.

18. 20. The method of claim 17, wherein the trigger event is receiving data associated with a subset of jobs associated with the plurality of jobs for the at least one or more hardware accelerators, or associated with another subset of jobs associated with the plurality of jobs for the one or more DSP cores.

19. 16. The method of claim 14 or 15, wherein the controller is transitioned from the first power mode to the second power mode for a configured amount of time.

20. 20. The method of claim 19, wherein transitioning the controller from the second power mode to the first power mode is responsive to the expiration of the configured amount of time and further responsive to no receipt of the trigger event.

21. 21. The method of claim 20, further comprising the controller requesting polling after the controller is transitioned to the first power mode, wherein in the absence of the triggering event, the controller is transitioned from the first power mode to the second power mode.

22. 20. The method of claim 19, further comprising transitioning the controller from the second power mode to the first power mode for the configured amount of time and in response to receiving the trigger event.

23. 16. The method of claim 14 or 15, wherein the controller remains in the second power mode until an interrupt is generated and sent to the controller to transition the controller from the second power mode to the first power mode.

24. the at least one or more hardware accelerators processing a subset of the jobs; and said one or more DSP cores processing a different subset of jobs of said plurality of jobs. The method of claim 14 or 15, further comprising:

25. 25. The method of claim 24, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping, and the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

26. 16. The method according to claim 14 or 15, wherein the wireless network is deployed in Time Division Duplex (TDD).

27. Means for receiving, in a wireless network, data associated with a slot, by a controller; means for processing the data in a first power mode; means for allocating a plurality of jobs associated with said data to at least one or more hardware accelerators or to one or more digital signal processing (DSP) cores; means for transitioning the controller from the first power mode to a second power mode after the controller completes the processing of the data associated with the slot, where the second power mode is a lower power mode compared to the first power mode when the controller is processing the data associated with the slot; means for scheduling the jobs for at least one or more hardware accelerators or for one or more DSP cores; and means for transitioning the controller from the second power mode to the first power mode in response to a trigger event; A system comprising:

28. 30. The system of claim 27, wherein the data is downlink data and the slots are downlink slots.

29. 29. The system of claim 27 or 28, wherein the trigger event is associated with receiving different data associated with a different slot in the wireless network.

30. 30. The system of claim 27, wherein the data is uplink data and the slots are uplink slots.

31. 31. The system of claim 30, wherein the trigger event is receiving data associated with a subset of jobs associated with the plurality of jobs for the at least one or more hardware accelerators or associated with another subset of jobs associated with the plurality of jobs for the one or more DSP cores.

32. 29. The system of claim 27 or 28, wherein the controller is transitioned from the first power mode to the second power mode for a configured amount of time.

33. 33. The system of claim 32, wherein transitioning the controller from the second power mode to the first power mode is responsive to the expiration of the configured amount of time and further responsive to no receipt of the trigger event.

34. 34. The system of claim 33, further comprising the controller requesting polling after the controller is transitioned to the first power mode, wherein in the absence of the triggering event, the controller is transitioned from the first power mode to the second power mode.

35. 33. The system of claim 32, further comprising means for transitioning the controller from the second power mode to the first power mode for the configured amount of time and in response to receiving the trigger event.

36. 29. The system of claim 27 or 28, wherein the controller remains in the second power mode until an interrupt is generated and sent to the controller to transition the controller from the second power mode to the first power mode.

37. means for the at least one or more hardware accelerators to process a subset of the jobs of the plurality of jobs; and means for the one or more DSP cores to process a different subset of jobs of the plurality of jobs; 29. The system of claim 27 or 28, further comprising:

38. 38. The system of claim 37, wherein the one or more hardware accelerators are configured to perform at least one or more operations associated with forward error correction (FEC) calculation, equalization, and demapping, and the one or more DSP cores are configured to perform at least one or more operations associated with channel estimation, demodulation reference (DMR) signal generation, frequency error calculation, and timing estimation.

39. 29. The system of claim 27 or 28, wherein the wireless network is deployed in Time Division Duplex (TDD).

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