Error rate measuring device and automatic phase adjustment method using the same

Abstract

To precisely match the phase of a clock input to a device under test with the center of a phase margin.SOLUTION: A phase amount calculation unit 6b calculates, as a phase amount for coarse adjustment for each component of a device 2 to be adjusted, a phase amount corresponding to a center position between an upper limit position and a lower limit position where an error is detected using an error detection unit 6a by varying the phase of a clock under the control of increase and decrease of the phase amount of a coarse adjustment phase variable device 5a, and calculates, as a phase amount for fine adjustment for each component of the device 2 to be adjusted, a phase amount corresponding to the presence or absence of an error detected by the error detection unit 6a when the phase of the clock is varied by controlling the increase and decrease of the phase amount of a fine adjustment phase variable device 5b. A phase amount control unit 6c controls the phase amount of the coarse adjustment phase variable device 5a for each component of the adjusted device 2 such that the clock phase becomes the phase amount for coarse adjustment, and then controls the phase amount of the fine adjustment phase variable device 5b such that the clock phase becomes the phase amount for fine adjustment.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an error rate measurement device capable of automatically adjusting the phase of an adjustment target device (for example, a waveform shaping IC, etc.) that requires phase adjustment of a clock for synchronizing data input from a control unit built in the device, such as an FPGA (field-programmable gate array), and an automatic phase adjustment method using the device.

Background Art

[0002] In recent years, the traffic of data centers and networks has been increasing steadily, and the transmission speed and communication standards of devices used in the physical layer are also advancing towards higher speed and larger capacity. Along with this, error rate measurement devices are also required to have higher bit rates and higher modulation rates. For example, PCI Express 5.0 using an NRZ signal of 32 Gbit / s per lane and 400G Ethernet (registered trademark) standard using a PAM4 signal with a modulation rate of 53.125 Gbaud per lane have been established.

[0003] By the way, in ICs with clock inputs for data input and timing synchronization, such as MUX (multiplexer), DEMUX (demultiplexer), and D-FF (delay flip-flop) used in error rate measurement devices, it is necessary to keep the phase relationship between the clock input and the data input within the allowable range, that is, within the phase margin. If the phase relationship between the data and the clock deviates from the phase margin, bit errors will occur in the error rate measurement device, and the user will not be able to accurately measure the error rate. Therefore, error rate measurement devices are equipped with a phase shifter to adjust the phase of the clock.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in order to increase the speed of the error rate measuring device, when the data input to these ICs is increased to a high bit rate, the phase margin becomes narrower accordingly, and there is a problem that high-precision clock phase adjustment is required.

[0006] In addition, the data and clock input to these ICs come through different paths depending on the components mounted in the error rate measuring device, so the amount of phase change due to temperature is different for each path. Therefore, there is a problem that the phase relationship between the data and the clock shifts as the temperature changes from the time of adjustment. When the phase relationship deviates from the optimum value, bit errors are likely to occur in the error rate measuring device, and there is no margin for applying jitter.

[0007] Furthermore, a digitally controlled phase shifter (delay variable IC) has a maximum phase variable amount and a setting resolution, and generally these are in a trade-off relationship. When selecting a phase shifter to satisfy the phase variable amount required for adjusting the phase relationship in the error rate measuring device, the resolution may be too rough for a high bit rate and the phase adjustment accuracy may be insufficient. For example, in the case of a phase shifter with a resolution of 12 ps and 8-bit digital control, 21-point phase settings can be obtained for an ideal phase margin of 250 ps at 4 Gbit / s without jitter, but only 6 points can be obtained for an ideal phase margin of 62.5 ps at 16 Gbit / s, so it is insufficient as a setting resolution. In an actual waveform, the phase margin becomes even narrower due to the influence of jitter, so only 3 or 4 points can be obtained, and it becomes difficult to accurately align the phase of the clock with the center of the phase margin.

[0008] Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide an error rate measuring device capable of accurately aligning the phase of a clock input to a device under measurement with the center of a phase margin, and an automatic phase adjustment method using the device.

Means for Solving the Problem

[0009] In order to achieve the above object, the error rate measuring device according to claim 1 of the present invention processes data from the control unit 6 at the timing of a clock input via a phase shifter 5 whose phase amount is controllable, in order to automatically perform phase adjustment for each of a plurality of components of the device under adjustment 2 inside the error rate measuring device, and outputs a test signal for measuring the error rate with respect to the object to be measured. The error rate measuring device 1 includes the device under adjustment 2, The phase shifter includes a coarse adjustment phase shifter 5a and a fine adjustment phase shifter 5b having a finer resolution than the coarse adjustment phase shifter, and is provided in a number corresponding to the components of the device under adjustment for a few minutes, The control unit is, After variably controlling the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter for each component of the device under adjustment, based on the coarse adjustment result when the phase amount of the coarse adjustment phase shifter is increased or decreased, the phase amount of the fine adjustment phase shifter is increased or decreased for each component of the device under adjustment to vary the phase of the clock. A phase amount control unit 6c; When the phase amount of the coarse adjustment phase shifter is increased or decreased for each component of the device under adjustment by the phase amount control unit to vary the phase of the clock, an upper limit position and a lower limit position where an error occurs for each component of the device under adjustment are detected. When the phase amount of the fine adjustment phase shifter is increased or decreased for each component of the device under adjustment by the phase amount control unit to vary the phase of the clock, an error detection unit 6a that detects a position where an error occurs for each component of the device under adjustment; The phase amount corresponding to the center position between the upper limit position and the lower limit position where an error is detected by the error detection unit by varying the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter is calculated as the phase amount for coarse adjustment for each component of the device under adjustment, and the phase amount corresponding to the presence or absence of error detection by the error detection unit when the phase of the clock is varied by increasing or decreasing the phase amount of the fine adjustment phase shifter is calculated as the phase amount for fine adjustment for each component of the device under adjustment. The error rate measuring device is provided with a phase amount calculation unit 6b. After controlling the phase amount of the coarse adjustment phase shifter for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, the phase amount of the fine adjustment phase shifter is controlled so that the phase of the clock becomes the phase amount for fine adjustment, and the phase of the clock for each component of the device to be adjusted is automatically adjusted.

[0010] The error rate measuring device according to claim 2 is the error rate measuring device according to claim 1, When the phase amount calculation unit 6b varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit detects the upper limit position and the lower limit position where an error occurs, the phase amount corresponding to the center position between the detected upper limit position and the lower limit position of the error is calculated for each component of the device to be adjusted as the phase amount for fine adjustment.

[0011] The error rate measuring device according to claim 3 is the error rate measuring device according to claim 1, When the phase amount calculation unit 6b varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, if the error detection unit does not detect an error, the phase amount for coarse adjustment is calculated for each component of the device to be adjusted as the phase amount for fine adjustment.

[0012] The error rate measuring device according to claim 4 is the error rate measuring device according to claim 1, When the phase amount calculation unit 6b varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit detects only the upper limit position where an error occurs, the value obtained by subtracting half of the phase margin from the value of the detected upper limit position of the error is calculated for each component of the device to be adjusted as the phase amount for fine adjustment.

[0013] The error rate measuring device according to claim 5 is the error rate measuring device according to claim 1, When the phase quantity calculation unit 6b calculates the value obtained by adding the value of the lower limit position at which an error occurs, which is detected only by the error detection unit, and half of the phase margin as the phase quantity for fine adjustment for each component of the device to be adjusted when varying the phase of the clock by controlling the increase and decrease of the phase quantity of the fine adjustment phase shifter.

[0014] An automatic phase adjustment method using the error rate measurement device according to claim 6 is an automatic phase adjustment method using an error rate measurement device 1 including an adjustment target device 2 that processes data from a control unit 6 at the timing of a clock input via a phase shifter 5 whose phase quantity is controllable to output a test signal for measuring an error rate with respect to a measurement target in order to automatically perform phase adjustment for each of a plurality of components of the adjustment target device 2 inside the error rate measurement device. Providing the phase shifter, which includes a coarse adjustment phase shifter and a fine adjustment phase shifter with a finer resolution than the coarse adjustment phase shifter, in a number corresponding to the components of the device to be adjusted. After varying the phase of the clock by controlling the increase and decrease of the phase quantity of the coarse adjustment phase shifter for each component of the device to be adjusted, varying the phase of the clock by controlling the increase and decrease of the phase quantity of the fine adjustment phase shifter for each component of the device to be adjusted based on the coarse adjustment result when controlling the increase and decrease of the phase quantity of the coarse adjustment phase shifter. When varying the phase of the clock by controlling the increase and decrease of the phase quantity of the coarse adjustment phase shifter for each component of the device to be adjusted, detecting the upper limit position and the lower limit position at which an error occurs for each component of the device to be adjusted, and when varying the phase of the clock by controlling the increase and decrease of the phase quantity of the fine adjustment phase shifter for each component of the device to be adjusted, detecting the position at which an error occurs for each component of the device to be adjusted. By controlling the increase and decrease of the phase amount of the coarse adjustment phase shifter, the phase of the clock is varied to calculate, for each component of the device under adjustment, the phase amount corresponding to the center position between the upper limit position and the lower limit position at which the error is detected as the phase amount for coarse adjustment, and calculate, for each component of the device under adjustment, the phase amount corresponding to the presence or absence of detection of the error when the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter as the phase amount for fine adjustment. After controlling the phase amount of the coarse adjustment phase shifter for each component of the device under adjustment so that the phase of the clock becomes the phase amount for coarse adjustment, controlling the phase amount of the fine adjustment phase shifter so that the phase of the clock becomes the phase amount for fine adjustment, and automatically adjusting the phase of the clock for each component of the device under adjustment.

[0015] The automatic phase adjustment method using the error rate measurement device according to claim 7 is the automatic phase adjustment method using the error rate measurement device according to claim 6, When detecting the upper limit position and the lower limit position where an error occurs when the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, calculating, for each component of the device under adjustment, the phase amount corresponding to the center position between the upper limit position and the lower limit position where the error is detected as the phase amount for fine adjustment.

[0016] The automatic phase adjustment method using the error rate measurement device according to claim 8 is the automatic phase adjustment method using the error rate measurement device according to claim 6, When the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter and no error is detected, calculating, for each component of the device under adjustment, the phase amount for coarse adjustment as the phase amount for fine adjustment.

[0017] The automatic phase adjustment method using the error rate measurement device according to claim 9 is the automatic phase adjustment method using the error rate measurement device according to claim 6, When the phase of the clock is varied by controlling the increase or decrease of the phase amount of the fine adjustment phase shifter, if only the upper limit position where an error occurs is detected, a value obtained by subtracting half of the phase margin from the value of the upper limit position where the error is detected is calculated for each component of the device to be adjusted as the phase amount for fine adjustment. It is characterized by including this step.

[0018] The automatic phase adjustment method using the error rate measuring device according to claim 10 is the automatic phase adjustment method using the error rate measuring device according to claim 6, When the phase of the clock is varied by controlling the increase or decrease of the phase amount of the fine adjustment phase shifter, if only the lower limit position where an error occurs is detected, a value obtained by adding the value of the lower limit position where the error is detected and half of the phase margin is calculated for each component of the device to be adjusted as the phase amount for fine adjustment. It is characterized by including this step.

[0019] The error rate measuring device according to claim 11 is the error rate measuring device according to any one of claims 1 to 5, The error detection unit 6a is characterized by detecting a bit error of the input data received from the object to be measured along with the input of the test signal.

[0020] The automatic phase adjustment method using the error rate measuring device according to claim 12 is the automatic phase adjustment method using the error rate measuring device according to any one of claims 6 to 10, It is characterized by including a step of detecting a bit error of the input data received from the object to be measured along with the input of the test signal.

Advantages of the Invention

[0021] According to the present invention, the phase of the clock input to the device to be measured can be accurately adjusted to the center of the phase margin. In particular, even for the phase margin narrowed by increasing the bit rate, the phase of the clock can be adjusted to the center of the phase margin with high precision, and even if the phase relationship between the data and the clock drifts due to temperature changes, bit errors are less likely to occur in the error rate measuring device.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0024] The error rate measurement device according to the present invention inputs a pattern signal of a known pattern to a measurement target, and measures the bit error rate of input data received from the measurement target in association with the input of this pattern signal, and has a function of automatically adjusting the phase of a clock input to an adjustment target device that processes data from a control unit such as an FPGA built in the device.

[0025] FIG. 1 is a block diagram showing a schematic configuration of an error rate measurement device 1 according to the present embodiment. The error rate measurement device 1 incorporates an adjustment target device 2, a clock distributor 3, a 1 / N frequency divider 4, a phase shifter 5, and a control unit (FPGA) 6 in the device. Note that in FIG. 1, only the configuration necessary for automatically adjusting the phase of the adjustment target device 2 which is a main part of the present invention is shown. Hereinafter, the configuration of each part will be described.

[0026] The adjustment target device 2 is a device that requires phase adjustment of a clock for data synchronization. In this example, a waveform shaping IC that shapes the waveform of data Tx (Tx1 to Tx5) output from the control unit 6 is used as the adjustment target device 2.

[0027] As a device that processes data input from the control unit 6, the waveform shaping IC 2 is configured to include a MUX (multiplexer) 2a, a MUX (multiplexer) 2b, and a D-FF (D-type flip-flop) as shown in FIG. 1. The MUX 2a selects and outputs either the data Tx1 or the data Tx2 from the control unit 6 using the clock input via the clock distributor 3 and the phase shifter 5 as a timing signal. The MUX 2b selects and outputs either the data Tx3 or the data Tx4 from the control unit 6 using the clock input via the clock distributor 3 and the phase shifter 5 as a timing signal. The D-FF 2c holds the value of the D input (data Tx5 from the control unit 6) as the Q output at the rising edge of the clock input via the clock distributor 3 and the phase shifter 5.

[0028] The data output from these MUX 2a, MUX 2b, and D-FF 2c can be used as a test signal for measuring the error rate with respect to a measurement target (not shown), for example.

[0029] The clock distributor 3 distributes and outputs the clock input as a periodic signal for synchronizing each part to each of the 1 / N frequency divider 4 and the phase shifter 5.

[0030] The 1 / N frequency divider 4 divides the clock input via the clock distributor 3 by 1 / N and inputs it to the control unit 6.

[0031] The phase shifter 5 can be automatically controlled in terms of the phase amount by a phase amount control unit 6c (to be described later) of the control unit 6, and is provided in a number corresponding to the components of the device to be adjusted (waveform shaping IC) 2. The phase shifter 5 in FIG. 1 is composed of a phase shifter 5A corresponding to the MUX 2a, a phase shifter 5B corresponding to the MUX 2b, and a phase shifter 5C corresponding to the D-FF 2c.

[0032] Each of the phase shifters 5A, 5B, 5C has its phase amount automatically controlled by a control signal from the control unit 6, and varies the phase of the clock input via the clock distributor 3.

[0033] Here, since the phase difference between the data path and the clock path becomes up to several nanoseconds at maximum, a maximum phase variable amount is required (requirement 1). Also, since the phase margin becomes as small as about several tens of picoseconds in the high bit rate and jitter-allowed state, high resolution is required (requirement 2).

[0034] Therefore, in the present embodiment, in order to meet the above-described requirements (requirement 1, requirement 2), as shown in FIG. 1, each of the phase shifters 5A, 5B, 5C is configured to include a coarse adjustment phase shifter 5a and a fine adjustment phase shifter 5b.

[0035] The coarse adjustment phase shifter 5a, for example, has a resolution of 12 ps, 8-bit control, and a maximum variable amount of 12 ps × 255 = 3.06 ns to meet the above-described requirement 1, and roughly adjusts the phase relationship between the data and the clock by a control signal from the control unit 6.

[0036] The fine-tuning phase shifter 5b is a phase shifter with a finer resolution than the coarse-tuning phase shifter 5a. To meet the above-mentioned requirement 2, for example, it has a resolution of 3 ps, 5-bit control, and a maximum variable amount of 3 ps × 31 = 93 ps. After the phase relationship between the data and the clock is coarsely adjusted by the coarse-tuning phase shifter 5a, the phase relationship between the data and the clock is finely adjusted by the control signal from the control unit 6, and the phase of the clock is accurately adjusted to the center of the phase margin.

[0037] Using the clock from the 1 / N frequency divider 4 as a timing signal, the control unit 6 outputs data consisting of a binary pattern such as PRBS to the device under adjustment (waveform shaping IC) 2. In the example of FIG. 1, data Tx1 and Tx2 are output to the MUX2a of the device under adjustment (waveform shaping IC) 2, data Tx3 and Tx4 are output to the MUX2b, and data Tx5 is output to the D-FF2c.

[0038] The control unit 6 includes an error detection unit 6a, a phase amount calculation unit 6b, and a phase amount control unit 6c as a configuration for controlling the phase amount of the phase shifter 5 (coarse-tuning phase shifter 5a, fine-tuning phase shifter 5b).

[0039] The error detection unit 6a takes the data Rx1, Rx2, and Rx3 from the MUX2a, MUX2b, and D-FF2c of the device under adjustment (waveform shaping IC) 2 as inputs. First, it increases or decreases the phase amount of the coarse-tuning phase shifter 5a and detects the positions (upper limit position, lower limit position) of the two places where errors occur when the phase of the clock is changed for each data of the MUX2a, MUX2b, and D-FF2c.

[0040] More specifically, the error detection unit 6a takes the data Rx1 from MUX2a as input, increases or decreases the phase amount of the coarse adjustment phase shifter 5a, changes the phase of the clock input to the coarse adjustment phase shifter 5a, and detects the positions (upper limit position, lower limit position) of two places where an error enters the data Rx1. The error detection unit 6a takes the data Rx2 from MUX2b as input, increases or decreases the phase amount of the coarse adjustment phase shifter 5a, changes the phase of the clock input to the coarse adjustment phase shifter 5a, and detects the positions (upper limit position, lower limit position) of two places where an error enters the Rx2. The error detection unit 6a takes the data Rx3 from D-FF2c as input, increases or decreases the phase amount of the coarse adjustment phase shifter 5a, changes the phase of the clock input to the coarse adjustment phase shifter 5a, and detects the positions (upper limit position, lower limit position) of two places where an error enters the Rx3.

[0041] Also, after adjusting the phase amount by the coarse adjustment phase shifter 5a, the error detection unit 6a, based on the coarse adjustment result (taking the value of the phase amount of the coarse adjustment result as the initial value), increases or decreases the phase amount of the fine adjustment phase shifter 5b, and detects the positions (upper limit position, lower limit position) where an error enters when changing the phase of the clock for each of the data of MUX2a, MUX2b, and D-FF2c.

[0042] In this way, for each of MUX2a, MUX2b, and D-FF2c that require clock phase adjustment, the error detection unit 6a detects the positions (upper limit position, lower limit position) where an error enters when the phase of the clock input to the corresponding phase shifter 5 (5A, 5B, 5C) is delayed and advanced.

[0043] The phase amount calculation unit 6b calculates the phase amount corresponding to the center position between the position (upper limit position) where an error is detected by delaying the phase of the clock input to the coarse adjustment phase shifter 5a and the position (lower limit position) where an error is detected by advancing the phase of the clock input to the coarse adjustment phase shifter 5a as the phase amount for coarse adjustment. This calculation of the phase amount for coarse adjustment is performed for each of MUX2a, MUX2b, and D-FF2c of the device to be adjusted (waveform shaping IC) 2.

[0044] After the coarse adjustment, the phase quantity calculation unit 6b calculates the phase quantity for fine adjustment according to the presence or absence of error detection by the error detection unit 6a when the phase of the clock input to the fine adjustment phase variable device 5b is delayed (using the value of the phase quantity of the coarse adjustment result as the initial value) and advanced (the presence or absence of errors at the upper limit position and the lower limit position of the phase margin). The calculation of this phase quantity for fine adjustment is performed for each of the MUX2a, MUX2b, and D-FF2c of the device under adjustment (waveform shaping IC) 2.

[0045] More specifically, when the error detection unit 6a detects errors at both the upper limit position and the lower limit position after the coarse adjustment, the phase quantity corresponding to the center position between the detected upper limit position and the lower limit position is calculated as the phase quantity for fine adjustment. When the error detection unit 6a does not detect errors at both the upper limit position and the lower limit position after the coarse adjustment, the phase quantity during the coarse adjustment is calculated as the phase quantity for fine adjustment. When the error detection unit 6a detects an error at either the upper limit position or the lower limit position after the coarse adjustment, the phase quantity for fine adjustment is calculated based on the value of the detected position (upper limit position or lower limit position) and half of the value of the phase margin.

[0046] That is, when the error detection unit 6a detects only the upper limit position of the error after the coarse adjustment, the value obtained by subtracting half of the value of the phase margin (the phase offset amount corresponding to half of the phase margin in FIG. 8 described later) from the value of the detected upper limit position is calculated as the phase quantity for fine adjustment. On the contrary, when the error detection unit 6a detects only the lower limit position of the error after the coarse adjustment, the value obtained by adding the value of the detected lower limit position and half of the value of the phase margin (the phase offset amount corresponding to half of the phase margin in FIG. 8 described later) is calculated as the phase quantity for fine adjustment.

[0047] The phase quantity control unit 6c controls the phase quantity of the coarse adjustment phase variable device 5a so as to be the phase quantity for coarse adjustment calculated by the phase quantity calculation unit 6b. Further, after the coarse adjustment, the phase quantity control unit 6c controls the phase quantity of the fine adjustment variable device 5b so as to be the phase quantity for fine adjustment calculated by the phase quantity calculation unit 6b.

[0048] Note that, although the error rate measurement device in this example was described by taking a waveform shaping IC including MUX2a, 2b, and D-FF2c as the device 2 to be phase-adjusted of the clock, it is not limited thereto. Any device that requires phase adjustment of the clock in the error rate measurement device 1 may be used. For example, it can also be used for automatic phase adjustment of data and clock input to a DEMUX (demultiplexer).

[0049] Next, an automatic phase adjustment method of the error rate measurement device 1 with the above-described configuration will be described. Here, a case where the phase of the clock of MUX2a of the device 2 to be phase-adjusted (waveform shaping IC) is adjusted by the coarse adjustment phase shifter 5a and the fine adjustment phase shifter 5b of the phase shifter 5A will be described as an example. The phase of MUX2b is adjusted in the same manner by the coarse adjustment phase shifter 5a and the fine adjustment phase shifter 5b of the phase shifter 5B, and the phase of D-FF2c is adjusted in the same manner by the coarse adjustment phase shifter 5a and the fine adjustment phase shifter 5b of the phase shifter 5C.

[0050] First, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the coarse adjustment phase shifter 5a of the phase shifter 5A is delayed by a predetermined step until the error detection unit 6a detects the upper limit position of the phase margin where an error occurs.

[0051] Next, the phase amount control unit 6c of the control unit 6 controls the phase amount of the coarse adjustment phase shifter 5a of the phase shifter 5A to the state before the phase is delayed to return the phase of the clock input to the coarse adjustment phase shifter 5a. Thereafter, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the coarse adjustment phase shifter 5a advances by a predetermined step until the error detection unit 6a detects the lower limit position of the phase margin where an error occurs.

[0052] Then, the phase amount calculation unit 6b of the control unit 6 calculates the phase amount for coarse adjustment corresponding to the center position between the upper limit position where an error is detected by delaying the phase of the clock and the lower limit position where an error is detected by advancing the phase of the clock.

[0053] The phase amount control unit 6c of the control unit 6 controls the phase amount of the coarse adjustment phase shifter 5a of the phase shifter 5A so that the phase of the clock is adjusted only by the phase amount for coarse adjustment calculated by the phase amount calculation unit 6b, and automatically coarsely adjusts the phase of the clock input to the MUX2a.

[0054] After that, the phase amount control unit 6c of the control unit 6 controls the phase amount of the fine adjustment phase shifter 5b of the phase shifter 5A with the coarse adjustment result by the coarse adjustment phase shifter 5a of the phase shifter 5A as the initial value. That is, the phase amount control unit 6c of the control unit 6 controls the phase amount so that the phase of the clock input to the fine adjustment phase shifter 5b is delayed by a predetermined step with the coarse adjustment result as the initial value, and then controls the phase amount so that the phase of the clock input to the fine adjustment phase shifter 5b advances by a predetermined step.

[0055] Then, the phase amount calculation unit 6b of the control unit 6 calculates the phase amount for fine adjustment according to the presence or absence of error detection by the error detection unit 6a (the presence or absence of errors at the upper limit position and the lower limit position of the phase margin) when controlling the phase amount of the fine adjustment phase shifter 5b of the phase shifter 5A.

[0056] The phase amount control unit 6c of the control unit 6 controls the phase amount of the fine adjustment phase shifter 5b of the phase shifter 5A so that the phase of the clock is adjusted only by the phase amount for fine adjustment calculated by the phase amount calculation unit 6b, and automatically finely adjusts the phase of the clock input to the MUX2a.

[0057] Here, in the automatic phase adjustment method described above, a case-by-case explanation will be given with reference to FIGS. 2 to 8 regarding specific examples of phase adjustment by the coarse adjustment phase shifter 5a and the fine adjustment phase shifter 5b of the phase shifter 5 (5A, 5B, 5C). In FIGS. 2 to 7, as an example of the numerical values of the specific setting values of the phase shifter 5, the setting value of the coarse adjustment phase shifter 5a is set to 0 to 255, and the setting value of the fine adjustment phase shifter 5b is set to 0 to 31.

[0058] (1) Automatic phase adjustment by the coarse adjustment phase shifter 5a in the case of a low bit rate (for example, less than 5 Gbit / s) will be described with reference to FIG. 2.

[0059] When the phase amount of the coarse adjustment phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin, and as shown in FIG. 2, the value of the lower limit position of the phase margin: 98 and the value of the upper limit position of the phase margin: 107 are obtained. As a result, the value of the center of the phase margin by the coarse adjustment phase shifter 5a = (the value of the lower limit position of the phase margin + the value of the upper limit position of the phase margin) / 2 = (98 + 107) / 2 = 102.5, and as shown in FIG. 2, the value obtained by rounding down the decimal part: 102 becomes the coarse adjustment result by the coarse adjustment phase shifter 5a.

[0060] As described above, in the case of a low bit rate as shown in FIG. 2, since the phase margin is wide, the phase of the clock can be adjusted to the center of the phase margin with a certain degree of accuracy even with the resolution of the coarse adjustment phase shifter 5a. That is, without using the fine adjustment phase shifter 5b, the phase of the clock can be adjusted to the center of the phase margin only with the coarse adjustment phase shifter 5a.

[0061] (2) Automatic phase adjustment by the coarse adjustment phase shifter 5a in the case of a high bit rate (for example, 5 Gbit / s or more) will be described with reference to FIG. 3.

[0062] When the phase amount of the coarse adjustment phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin, and as shown in FIG. 3, the value of the lower limit position of the phase margin: 101 and the value of the upper limit position of the phase margin: 104 are obtained. As a result, the value of the center of the phase margin by the coarse adjustment phase shifter 5a = (the value of the lower limit position of the phase margin + the value of the upper limit position of the phase margin) / 2 = (101 + 104) / 2 = 102.5, and as shown in FIG. 3, the value obtained by rounding down the decimal part: 102 becomes the coarse adjustment result by the coarse adjustment phase shifter 5a.

[0063] Thus, in the case of a high bit rate as shown in FIG. 3, the phase margin is narrowed, and the phase margin is only several times (for example, four times) the resolution of the coarse adjustment phase shifter 5a. Therefore, there is a problem that the phase of the clock cannot be accurately adjusted to the center of the phase margin. That is, the phase of the clock cannot be adjusted to the center of the phase margin only by the coarse adjustment phase shifter 5a as in the case of a low bit rate.

[0064] And in the error rate measuring device 1 today, it is necessary to support a wide bandwidth from a low bit rate (for example, a bit rate less than 5 Gbit / s such as PCI Express 1.0 (2.5 Gbit / s)) to a high bit rate (for example, a bit rate of 5 Gbit / s or more such as PCI Express 5.0 (32 Gbit / s)), and it cannot be covered only by one type of coarse adjustment phase shifter 5a.

[0065] Therefore, in the error rate measuring device of the present embodiment, in order to solve the above-described problem, after the phase adjustment by the coarse adjustment phase shifter 5a, fine adjustment of the phase is performed by the fine adjustment phase shifter 5b.

[0066] (3) Automatic phase adjustment when the upper and lower limits of the error are found by phase adjustment using the fine adjustment phase shifter 5b after phase adjustment using the coarse adjustment phase shifter 5a will be described with reference to FIG. 4.

[0067] When the phase amount of the coarse adjustment phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin, and as shown in FIG. 4, the value at the lower limit position of the phase margin: 101, the value at the upper limit position of the phase margin: 104 are obtained. Thereby, the value at the center of the phase margin by the coarse adjustment phase shifter 5a = (the value at the lower limit position of the phase margin + the value at the upper limit position of the phase margin) / 2 = (101 + 104) / 2 = 102.5, and as shown in FIG. 4, the value obtained by truncating the decimal part: 102 becomes the coarse adjustment result by the coarse adjustment phase shifter 5a.

[0068] Then, when the phase of the fine-tuning phase shifter 5b is controlled by the phase amount control unit 6c of the control unit 6 after the coarse adjustment, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin, and as shown in FIG. 4, the value of the lower limit position of the phase margin: 11 and the value of the upper limit position of the phase margin: 26 are obtained. Thereby, the value of the center of the phase margin by the fine-tuning phase shifter 5b = (the value of the lower limit position of the phase margin + the value of the upper limit position of the phase margin) / 2 = (11 + 26) / 2 = 18.5, and as shown in FIG. 4, the value obtained by truncating the decimal part: 18 becomes the fine-tuning result (final adjustment result) by the fine-tuning phase shifter 5b.

[0069] (4) The automatic phase adjustment when the upper and lower limits of the error cannot be found in the phase adjustment by the fine-tuning phase shifter 5b after the phase adjustment by the coarse-tuning phase shifter 5a will be described with reference to FIG. 5.

[0070] When the phase amount of the coarse-tuning phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin, and as shown in FIG. 5, the value of the lower limit position of the phase margin: 98 and the value of the upper limit position of the phase margin: 107 are obtained. Thereby, the value of the center of the phase margin by the coarse-tuning phase shifter 5a = (the value of the lower limit position of the phase margin + the value of the upper limit position of the phase margin) / 2 = (98 + 107) / 2 = 102.5, and as shown in FIG. 5, the value obtained by truncating the decimal part: 102 becomes the coarse adjustment result by the coarse-tuning phase shifter 5a.

[0071] In this case, when the phase amount of the fine-tuning phase shifter 5b is controlled by the phase amount control unit 6c of the control unit 6 after the coarse adjustment, the error detection unit 6a does not detect an error even if the phase is swung to the upper and lower limit positions of the phase margin, so the initial value: 16, which is the coarse adjustment result by the coarse-tuning phase shifter 5a, is reset. In this case, since the phase margin is wide, similar to the case of (1) described above, the phase of the clock can be adjusted to the center of the phase margin with a certain degree of accuracy even with the resolution of the coarse-tuning phase shifter 5a.

[0072] (5) The automatic phase adjustment when only the lower limit of the error is found by the phase adjustment with the fine adjustment phase shifter 5b after the phase adjustment with the coarse adjustment phase shifter 5a will be described with reference to FIGS. 6 and 8. Note that the bit rate of the data is 8 Gbit / s and the jitter is 30 ps.

[0073] When the phase amount of the coarse adjustment phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects errors at both the upper limit position and the lower limit position of the phase margin. As shown in FIG. 6, the value of the lower limit position of the phase margin: 98 and the value of the upper limit position of the phase margin: 105 are obtained. Thereby, the value of the center of the phase margin by the coarse adjustment phase shifter 5a = (the value of the lower limit position of the phase margin + the value of the upper limit position of the phase margin) / 2 = (98 + 105) / 2 = 101.5, and as shown in FIG. 6, the value obtained by truncating the decimal part: 101 becomes the coarse adjustment result by the coarse adjustment phase shifter.

[0074] Then, when the phase amount of the fine adjustment phase shifter 5b is controlled by the phase amount control unit 6c of the control unit 6 after the coarse adjustment, the error detection unit 6a detects only the error at the lower limit position of the phase margin, and only the value of the lower limit position of the phase margin: 4 is obtained. From the table in FIG. 8, since the phase offset amount corresponding to half of the phase margin for the bit rate of the data: 8 Gbit / s is 16, the fine adjustment result by the fine adjustment phase shifter 5b = the value of the lower limit position of the phase margin + half of the value of the phase margin = 4 + 16 = 20.

[0075] (6) The automatic phase adjustment when only the upper limit of the error is found by the phase adjustment with the fine adjustment phase shifter 5b after the phase adjustment with the coarse adjustment phase shifter 5a will be described with reference to FIGS. 7 and 8. Note that the bit rate of the data is 8 Gbit / s and the jitter is 30 ps.

[0076] When the phase amount of the coarse adjustment phase shifter 5a is controlled by the phase amount control unit 6c of the control unit 6, the error detection unit 6a detects an error at the lower limit position of the phase margin and obtains the value of the lower limit position of the phase margin: 98. In contrast, although the true error-free upper limit value at the upper limit position of the phase margin is 105, as shown in FIG. 7, due to the error caused by jitter, 106 is obtained as the value of the upper limit position of the phase margin. As a result, as shown in FIG. 7, the center value of the phase margin by the coarse adjustment phase shifter 5a = (98 + 106) / 2 = 102 becomes the coarse adjustment result.

[0077] Then, when the phase amount of the fine adjustment phase shifter 5b is controlled by the phase amount control unit 6c of the control unit 6 after the coarse adjustment, the error detection unit 6a detects an error only at the upper limit position of the phase margin, and only obtains the value of the upper limit position of the phase margin: 28. From the table in FIG. 8, since the phase offset amount corresponding to half of the phase margin for a data bit rate of 8 Gbit / s is 16, the fine adjustment result by the fine adjustment phase shifter 5b = the value of the upper limit position of the phase margin - half of the value of the phase margin = 28 - 16 = 12.

[0078] The table in FIG. 8 used in (5) and (6) above is an example of a table showing the relationship between the bit rate and the phase offset amount corresponding to half of the phase margin. The values in the table in FIG. 8 can be calculated based on the measurement results by the actual machine (error rate measurement device 1), or can be calculated in advance using the calculation formula: the phase offset amount corresponding to half of the phase margin = ((1000 / bit rate [Gbit / s]) - jitter [ps]) / (2×3 [ps]) based on the bit rate and jitter. Note that 3 [ps] in the above calculation formula is the resolution of the fine adjustment phase shifter 5b.

[0079] Incidentally, in the above-described embodiment, the error detection unit 6a configured by the control unit 6 is used as part of a configuration for automatically adjusting the phase of the clock input to the device 2 to be adjusted. However, it can also be used to detect bit errors in the input data received from the object to be measured in accordance with the input of a pattern signal of a known pattern to the object to be measured (not shown). Alternatively, a configuration may be provided in which an error detection unit for detecting bit errors in the input data received from the object to be measured is provided separately from the error detection unit 6a.

[0080] As described above, according to the present embodiment, without the need for other measuring instruments, the error rate measuring apparatus alone can automatically adjust the phase of the clock input to the device 2 to be adjusted (waveform shaping IC) using the error detection function of the control unit (FPGA) provided inside the error rate measuring apparatus.

[0081] At that time, automatic phase adjustment of the clock can be performed without using devices such as logic circuits and flip-flop circuits as disclosed in the conventional Patent Document 2.

[0082] More specifically, in the present embodiment, the phase shifter 5 (5A, 5B, 5C) includes a coarse adjustment phase shifter 5a with a large variable amount but a coarse resolution, and a fine adjustment phase shifter 5b with a small variable amount but a fine resolution. The phase shifter 5 is mounted in the error rate measuring apparatus 1, and under the control of the control unit 6, the fine adjustment phase shifter 5b is controlled starting from a state preliminarily coarsely adjusted by the coarse adjustment phase shifter 5a to complete the adjustment in a short time and optimize the phase.

[0083] At that time, by performing the adjustment using the fine adjustment phase shifter with a fine resolution, it is possible to accurately align the phase of the clock with the center of the phase margin even for the phase margin narrowed by increasing the bit rate, and it becomes difficult for bit errors to occur in the error rate measuring apparatus even if the phase relationship between the data and the clock drifts due to temperature changes.

[0084] In addition, in the case of a high-resolution fine-tuning phase comparator, phase adjustment can be performed even for the phase margin that has become extremely small due to the application of jitter. As a result, a larger jitter can be applied without generating bit errors in the error rate measurement device.

[0085] Furthermore, by controlling the phase shifters (coarse adjustment phase shifter, fine adjustment phase shifter) in the control unit, adjustment can be performed in a short time. Therefore, adjustment can be automatically performed before starting the error rate measurement, and the phase can always be adjusted when the user uses it. Moreover, by adjusting immediately before the user uses it, differences due to the user's usage environment can be absorbed, and the device can operate with stable performance.

[0086] As described above, the best mode of the error rate measurement device according to the present invention and the automatic phase adjustment method using the device has been described. However, the present invention is not limited by the description and drawings of this mode. That is, of course, all other modes, embodiments, operation techniques, etc. made by those skilled in the art based on this mode are included in the scope of the present invention.

Explanation of Reference Numerals

[0087] 1 Error rate measurement device 2 Device to be adjusted 2a, 2b MUX 2c D-FF 3 Clock distributor 4 1 / N frequency divider 5 (5A, 5B, 5C) Phase shifter 5a Coarse adjustment phase shifter 5b Fine adjustment phase shifter 6 Control unit (FPGA) 6a Error detection unit 6b Phase amount calculation unit 6c Phase amount control unit

Claims

1. In order to automatically perform phase adjustment for each of a plurality of components of an adjustable device (2) inside an error rate measurement device, data from a control unit (6) is processed at the timing of a clock input via a phase shifter (5) whose phase amount is controllable, and a test signal for measuring an error rate with respect to a measurement object is output. An error rate measurement device (1) comprising the adjustable device (2), The phase shifter includes a coarse adjustment phase shifter (5a) and a fine adjustment phase shifter (5b) having a finer resolution than the coarse adjustment phase shifter, and is provided in a number corresponding to the components of the adjustable device for a few minutes, The control unit is, After variably controlling the phase amount of the coarse adjustment phase shifter for each component of the adjustable device to vary the phase of the clock, a phase amount control unit (6c) that variably controls the phase amount of the fine adjustment phase shifter for each component of the adjustable device based on the coarse adjustment result when the phase amount of the coarse adjustment phase shifter is variably controlled to vary the phase of the clock, When the phase amount of the coarse adjustment phase shifter is variably controlled for each component of the adjustable device by the phase amount control unit to vary the phase of the clock, an upper limit position and a lower limit position where an error occurs for each component of the adjustable device are detected. An error detection unit (6a) that detects a position where an error occurs for each component of the adjustable device when the phase amount of the fine adjustment phase shifter is variably controlled for each component of the adjustable device by the phase amount control unit to vary the phase of the clock, A phase amount calculation unit that calculates, for each component of the adjustable device, a phase amount corresponding to a center position between the upper limit position and the lower limit position where an error is detected by the error detection unit by variably controlling the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter as a phase amount for coarse adjustment, and calculates, for each component of the adjustable device, a phase amount according to the presence or absence of error detection by the error detection unit when the phase of the clock is variably controlled by increasing or decreasing the phase amount of the fine adjustment phase shifter as a phase amount for fine adjustment (6b) is provided, After controlling the phase amount of the coarse adjustment phase shifter for each component of the device to be adjusted so that the phase of the clock becomes the phase amount for coarse adjustment, the phase amount of the fine adjustment phase shifter is controlled so that the phase of the clock becomes the phase amount for fine adjustment, and the phase of the clock for each component of the device to be adjusted is automatically adjusted. An error rate measuring device characterized by the above.

2. When the phase amount calculation unit (6b) varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit detects the upper limit position and the lower limit position where an error occurs, the phase amount corresponding to the center position between the detected upper limit position and the lower limit position of the detected error is used as the phase amount for fine adjustment for each component of the device to be adjusted. The error rate measuring device according to claim 1, characterized by calculating.

3. When the phase amount calculation unit (6b) varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit does not detect an error, the phase amount for coarse adjustment is used as the phase amount for fine adjustment for each component of the device to be adjusted. The error rate measuring device according to claim 1, characterized by calculating.

4. When the phase amount calculation unit (6b) varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit detects only the upper limit position where an error occurs, the value obtained by subtracting half of the phase margin from the value of the detected upper limit position of the error is used as the phase amount for fine adjustment for each component of the device to be adjusted. The error rate measuring device according to claim 1, characterized by calculating.

5. When the phase amount calculation unit (6b) varies the phase of the clock by controlling the increase and decrease of the phase amount of the fine adjustment phase shifter, and the error detection unit detects only the lower limit position where an error occurs, the value obtained by adding the value of the detected lower limit position of the error and half of the phase margin is used as the phase amount for fine adjustment for each component of the device to be adjusted. The error rate measuring device according to claim 1, characterized by calculating.

6. In order to automatically perform phase adjustment for each of a plurality of components of an adjustable device (2) inside an error rate measurement device, data from a control unit (6) is processed at the timing of a clock input via a phase shifter (5) whose phase amount is controllable, and a test signal for measuring an error rate with respect to a measurement object is output. An automatic phase adjustment method using an error rate measurement device (1) provided with the adjustable device (2), providing the phase shifter, which consists of a coarse adjustment phase shifter and a fine adjustment phase shifter with a finer resolution than the coarse adjustment phase shifter, in a number corresponding to the components of the adjustable device for a few minutes; after variably controlling the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter for each component of the adjustable device, variably controlling the phase amount of the fine adjustment phase shifter for each component of the adjustable device based on the coarse adjustment result when the phase amount of the coarse adjustment phase shifter is increased or decreased to vary the phase of the clock; when variably controlling the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter for each component of the adjustable device, detecting an upper limit position and a lower limit position where an error for each component of the adjustable device enters, and when variably controlling the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase shifter for each component of the adjustable device, detecting a position where an error for each component of the adjustable device enters; calculating, for each component of the adjustable device, a phase amount corresponding to a center position between the detected upper limit position and lower limit position where the error is detected by variably controlling the phase of the clock by increasing or decreasing the phase amount of the coarse adjustment phase shifter as the phase amount for coarse adjustment, and calculating, for each component of the adjustable device, a phase amount according to the presence or absence of detection of the error when variably controlling the phase of the clock by increasing or decreasing the phase amount of the fine adjustment phase shifter as the phase amount for fine adjustment; controlling the phase amount of the coarse adjustment phase shifter for each component of the adjustable device so that the phase of the clock becomes the phase amount for coarse adjustment, then controlling the phase amount of the fine adjustment phase shifter so that the phase of the clock becomes the phase amount for fine adjustment, and automatically adjusting the phase of the clock for each component of the adjustable device. An automatic phase adjustment method using an error rate measurement device, characterized by including the steps above.

7. When the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine-adjustment phase shifter, if the upper limit position and the lower limit position at which an error occurs are detected, a step of calculating, for each component of the device to be adjusted, a phase amount corresponding to the center position between the detected upper limit position and the lower limit position at which the error occurs as the fine-adjustment phase amount is included. The automatic phase adjustment method using the error rate measuring device according to claim 6, characterized in that.

8. When the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine-adjustment phase shifter, if no error is detected, a step of calculating, for each component of the device to be adjusted, the phase amount for coarse adjustment as the phase amount for fine adjustment is included. The automatic phase adjustment method using the error rate measuring device according to claim 6, characterized in that.

9. When the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine-adjustment phase shifter, if only the upper limit position at which an error occurs is detected, a step of calculating, for each component of the device to be adjusted, a value obtained by subtracting half of the phase margin value from the value of the detected upper limit position as the fine-adjustment phase amount is included. The automatic phase adjustment method using the error rate measuring device according to claim 6, characterized in that.

10. When the phase of the clock is varied by controlling the increase and decrease of the phase amount of the fine-adjustment phase shifter, if only the lower limit position at which an error occurs is detected, a step of calculating, for each component of the device to be adjusted, a value obtained by adding the value of the detected lower limit position and half of the phase margin value as the fine-adjustment phase amount is included. The automatic phase adjustment method using the error rate measuring device according to claim 6, characterized in that.

11. The error detection unit (6a) detects a bit error in the input data received from the object to be measured in accordance with the input of the test signal. The error rate measuring device according to any one of claims 1 to 5, characterized in that.

12. A step of detecting a bit error in the input data received from the object to be measured in accordance with the input of the test signal is included. The automatic phase adjustment method using the error rate measuring device according to any one of claims 6 to 10, characterized in that.

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