Distributed control computing system and method for high altitude long endurance aircraft

Abstract

To provide a flight control computer for an Unmanned Aerial Vehicle (UAV) that detects and reacts against a fault.SOLUTION: A computing device includes: a first flight control computer (FCC) (112); a second FCC (113); at least one selector (182) in communication with the first FCC; and at least one watchdog window (180) in communication with the at least one selector (182), the at least one watchdog window monitoring a performance of the first FCC (112) based on an electrical pulse emitted by the FCC (112). The watchdog window detects a fault pulse of the electrical pulse emitted by the first FCC (112), and the selector (182) toggles to the second FCC based on the detected fault pulse emitted by the first FCC.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention generally relates to a flight control computer, and more particularly to a flight control computer for an unmanned aerial vehicle (UAV).

[0002] Cross - reference to related applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 62 / 838,783, filed Apr. 25, 2019, U.S. Provisional Patent Application No. 62 / 838,833, filed Apr. 25, 2019, and U.S. Provisional Patent Application No. 62 / 855,593, filed May 31, 2019, the entire contents of all of which are incorporated herein by reference for all purposes.

Background Art

[0003] An unmanned aerial vehicle (UAV) is an aircraft capable of controlled and sustained flight. The UAV has no on - board pilot, and the flight control computer (FCC) mounted on the UAV serves as the central information unit of the aircraft. The FCC includes one or more processors, and the FCC controls the functions of the UAV.

Summary of the Invention

[0004] Embodiments of the system can include a first flight control computer (FCC) of two or more FCCs, a second FCC of two or more FCCs, at least one selector communicating with the first FCC, and at least one watchdog window communicating with at least one selector and configured to monitor the performance of the first FCC based on electrical pulses emitted by the FCC. The at least one watchdog window can be configured to detect a fault pulse among the electrical pulses emitted by the first FCC, and the selector can be configured to toggle to the second FCC based on the detected fault pulse emitted by the first FCC.

[0005] In an embodiment of the additional system, the detected fault pulse may be a pulse outside the preferred range. In an embodiment of the additional system, the detected fault pulse may be a pulse that skips a beat. In an embodiment of the additional system, the detected fault pulse may be a pulse having a frequency and amplitude outside the preferred range of the baseline pulse.

[0006] In an embodiment of the additional system, the selector may be further configured to reset the power to the first FCC. In an embodiment of the additional system, the selector may be configured to toggle to the first FCC after resetting the power to the first FCC. In an embodiment of the additional system, at least one watchdog window may be further configured to monitor the performance of the first FCC after toggling to the first FCC by the selector.

[0007] An embodiment of the method can include monitoring, by a watchdog window, the performance of a first flight control computer (FCC) among two or more flight control computers, the performance being based on electrical pulses emitted by the first FCC; detecting, via the watchdog window, a fault pulse among the electrical pulses emitted by the first FCC; and toggling, by a selector in communication with the watchdog window, to a second FCC based on the detected fault pulse emitted by the first FCC.

[0008] In an embodiment of the additional method, the detected fault pulse may be a pulse outside the preferred range. In an embodiment of the additional method, the detected fault pulse may be a pulse that skips a beat. In an embodiment of the additional method, the detected fault pulse may be a pulse having a frequency and amplitude outside the preferred range of the baseline pulse.

[0009] Embodiments of the additional method can further include the step of resetting the power to the first FCC via a selector. Embodiments of the additional method can further include the step of toggling to the first FCC by the selector after resetting the power to the first FCC. Embodiments of the additional method can include the step of monitoring the performance of the first flight control computer (FCC) after toggling the first FCC by the selector via a watchdog window.

[0010] Embodiments of the flight control computer can include a field programmable gate array (FPGA), a flight control computer (FCC) processor that communicates with the FPGA via an FCC bus, a plurality of serial ports that communicate with the FPGA and the FCC processor, and a controller chip that communicates with the plurality of serial ports and is configured to convert the parallel output of the FCC bus into a serial format for transmission via a serial port among the plurality of serial ports.

Brief Description of the Drawings

[0011] The components in the drawings are not necessarily to scale and instead emphasis is placed on explaining the principles of the present invention. Like reference numerals indicate corresponding parts throughout the various figures. The embodiments are shown by way of example and are not limited to the figures of the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0012] The following description is made for the purpose of explaining the general principles of the embodiments disclosed herein and is not meant to limit the concepts disclosed herein. Further, the specific features described herein can be used in combination with other described features in each of various possible combinations and permutations. Unless otherwise specifically defined herein, all terms should be given the broadest possible interpretation including meanings implied from the description and understood by those skilled in the art and / or defined in dictionaries, treatises, etc.

[0013] Embodiments of the systems and methods disclosed herein can include distributed computing for a flight control computer (FCC) of an unmanned aerial vehicle (UAV). In one example, the UAV is a high-altitude long-endurance solar aircraft. For the FCC, it is difficult to physically accommodate all of the desired communication lines, so-called "input / output" or "I / O", between the information processing system and the external system. The FCC can be controlled and programmed using a field programmable gate array (FPGA). An FPGA is a field-programmable integrated circuit in the sense that it can be programmed after manufacture to perform one or more logical operations. The FPGA is connected to a central processing unit (CPU) by a bus and can handle all the necessary I / O. In such a point-to-point design, only one connection is established for each node of the aircraft's avionics, and a specific task is assigned to each node. Such a configuration can lead to high serial traffic that burdens the CPU.

[0014] Furthermore, it is important to have a system that monitors the performance of the FCC so that the UAV can maintain flight if the FCC does not operate properly. The UAV can have at least two FCCs, and at least one of the FCCs functions as a backup if the other FCCs do not operate properly. Additionally, a matrix of checkers or selectors may monitor the performance of each FCC. Even if a failure occurs in one FCC, the UAV can maintain flight by switching to the backup FCC. This approach becomes complex, increasing the likelihood of a failure in any one of the selectors. Moreover, the matrix configuration is difficult to debug, requires a large amount of wiring, and can be very costly to implement. Additionally, the matrix configuration may require a significant amount of power and may be difficult to architect.

[0015] In one embodiment, the FCC has a processor with an FPGA fabric proximate to the processor. The FPGA has radiation tolerance that helps protect the computer from high-frequency solar radiation that could potentially damage the electronics housed therein. A plurality of serial ports are connected to the processor / FPGA system. Using the FPGA to create circuits can increase the flexibility of serial port and pin connections. In one embodiment, the FCC has an increased capacity of serial ports. Generally, the constraints on the total number of serial ports are the number of physical I / O pins and the size of the FPGA. In one embodiment, 20 serial ports are disposed on the FCC to provide substantial I / O. This configuration provides a so-called "party line" where all nodes of the aircraft avionics listen and communicate.

[0016] Each of the 20 serial ports can be connected to different elements of the flight control system. For example, there may be ports for buses, data links, transponders, etc. This system requires minimal maintenance and can accurately distribute control without overburdening the processor. Further, this system can operate at low power. For example, in a typical Ethernet connection configuration, about 1 watt of power is used, whereas the FCC has a power usage in an approximate range measured in milliwatts (mW).

[0017] The system for distributed control computing of the FCC described above further includes monitoring the performance of the FCC. More specifically, a system for automatic switching from one FCC to another identical FCC in case of a failure is described herein. In one embodiment, a selector connected to the FCC has a simple configuration and does not include, for example, logic gates, transistors, etc. Individual aspects of the selector can fail. However, because the selector is simple, there are few failure modes in the system and thus the reliability can be much higher.

[0018] In one embodiment, each FCC has a pulse or "watchdog" generated by the FCC programming and FCC circuitry. A watchdog window associated with the selector can detect an electrical pulse. If the watchdog window detects that the performance specifications are not met, e.g., the absence of a pulse, the selector can toggle to a second FCC, while the first FCC can power cycle, e.g., turn off and then back on. Further, the power of the first FCC may be reset and the identified problem may be resolved. The FCC may recover and operate again in a sufficiently short time such that the safety of the aircraft is ensured. Thus, since the selector toggles to a normal backup FCC, the UAV can maintain continuous flight.

[0019] Referring to FIG. 1, a system 100 for distributed computing for a flight control computer (FCC) 112 of an unmanned aerial vehicle (UAV) 101 is shown. A UAV is an aircraft without a pilot on board and can fly autonomously or remotely. In one embodiment, the UAV 101 is a high-altitude long-endurance aircraft. In one embodiment, the UAV 101 has one or more motors, e.g., 1 to 40 motors, and can have a wingspan of 100 feet to 400 feet. In one embodiment, the UAV 101 can have a wingspan of about 260 feet and can be propelled by a plurality of motors driven by a solar cell array covering the surface of the wings, 10 electric motors, thereby providing zero emissions. The UAV 101 is designed to fly at an altitude of about 65,000 feet above sea level, above the clouds, and perform continuous long-term missions for up to several months without landing.

[0020] The high-altitude long-endurance UAV 101 optimally functions at high altitudes, at least partially due to the lightweight payload of the UAV, and can fly continuously for a significant period without relying on landing. In one embodiment, the high-altitude long-endurance UAV 101 weighs approximately 3,000 pounds and includes two or more outer wing panel sections and one or more central wing panel sections, and the mutual detachment and / or attachment to the central panel of the wing panel sections are possible, so that efficient assembly and disassembly of the UAV 101 can be provided.

[0021] In one embodiment, there is no on-board pilot in the UAV 101. Therefore, the flight control computer (FCC) 112 installed in the UAV 101 is the central information department of the aircraft. The FCC 112 can partially or fully control many functions of the UAV 101, such as determining the flight pattern and changing the direction of the UAV 101. In one embodiment, the FCC 112 can determine the flight pattern based on weather conditions, the purpose of the payload operator, the flight patterns of other UAVs in the air fleet, and various external sensors. In one embodiment, the operator determines the flight pattern of the UAV 101.

[0022] Figure 2 shows an example of the top-level functional block diagram of the FCC 112 of the high-altitude long-endurance aircraft. The FCC 112 includes at least a processor 153 such as a central processing unit (CPU), an addressable memory 154, and an external device interface 156, for example, an optional USB port and related processing, and / or an Ethernet port and related processing, and an optional user interface, for example, an array of status lights, sensors, and one or more toggle switches, and / or a touch screen. Optionally, the addressable memory may be, for example, flash memory, EPROM, and / or a disk drive or other hard drive. These elements can communicate with each other via a data bus 160.

[0023] In some embodiments, the processor 153 may be configured to perform steps of a process of establishing a communication channel via an operating system 162 that supports the application 164 or the like.

[0024] The FCC 112 may further be connected to or communicate with a global positioning system (GPS) 126 configured to receive position data from a group of satellites. Further, the FCC 112 may include a transmitter 157 for transmitting repetitive GPS signals on the ground and / or for transmitting GPS signals converted in an auxiliary frequency band on the ground to a ground RF receiver in cooperation with a ground GPS receiver.

[0025] As shown in FIG. 3, the FCC processor 153 can be connected to a field programmable gate array (FPGA) fabric 152. The FPGA 152 can be a field programmable integrated circuit in the sense that the FPGA can be programmed after manufacture to perform one or more logical operations. More specifically, the FPGA 152 can include a collection of logic cells surrounded by an interconnect fabric, or a "look-up table" (LUT). The LUT and the interconnect fabric are programmable and provide a system for implementing algorithms. In one embodiment, the FPGA 152 can be reprogrammed to implement different logical functions, thereby providing flexible reconfigurable computing.

[0026] The FPGA 152 can help expand the I / O capabilities of the processor 153. The FPGA 152 can have a large resource of logic gates and RAM blocks for implementing complex algorithms. The architecture of the FPGA 152 can be composed of LUTs, routing channels, and I / O pads, and the I / O pads enable memory mapping between the processor 153 and other peripheral devices within the FCC 112.

[0027] The FPGA 152 can have radiation tolerance that helps protect the computer from high-frequency solar radiation that can potentially damage the electronic devices housed therein. In one embodiment, the FPGA 152 may be a SmartFusion® 2 FPGA from Microsemi Corporation of Aliso Viejo, California.

[0028] The plurality of serial ports 170 are connected to the FCC 112 and can communicate with the processor 153 and the FPGA 152 via an input 176 such as a bus. In one embodiment, each serial port 170 may be a serial communication interface through which information enters and exits the FCC 112 one bit at a time. In one embodiment, the serial port 170 interfaces with a controller chip, such as a general-purpose asynchronous transceiver circuit. The controller chip may be configured to receive the parallel output of the FCC bus 160 and convert the output to serial format for transmission via the serial port 170, as shown in FIG. 2. The serial port 170 may require minimal support software from the FPGA 152. The serial ports 170 can be divided into male and female, and the connectors of the serial ports 170 can only mate with connectors of the opposite male-female type. Generally, male serial port connectors have protruding pins and female connectors have sockets. In one embodiment, the serial port 170 can have a male connector that can mate with a female-type output 174. The output 174 may be a cable that connects to an external element 172, such as a modem, transponder, and other external elements related to the avionics of the UAV.

[0029] The configuration can be created by the FPGA 152, thereby enhancing the flexibility of the serial port and pins. In one embodiment, the FCC 112 can increase the capacity of the serial port. Generally, the constraints on the total number of serial ports are the number of physical I / O pins of the serial port 170 and the size of the FPGA 152. In one embodiment, a plurality of serial ports, for example 20 serial ports, are arranged in the FCC 112.

[0030] An embodiment with 20 serial ports can provide substantial I / O to the FCC 112. Each of the 20 serial ports 170 may be connected to a different external element 172 of the FCC 112. For example, there may be ports for a bus, modem, data link, transponder, etc. The 20 serial ports 170 require minimal maintenance and can accurately distribute control without overloading the processor 153. In one embodiment, the serial ports 170 can reduce the processing load required by the processor 153. Furthermore, the configuration of 20 serial ports can operate the FCC 112 at low power. For example, in a typical Ethernet connection configuration, about 1 watt of power is used, whereas the FCC has a power consumption in the approximate range measured in milliwatts (mW).

[0031] The system for distributed control computing can further provide for monitoring the performance of FCC112. More specifically, as shown in FIG. 4, the system includes an automatic switch that toggles from a first FCC112 to a second FCC113 when it does not operate properly. The FCC112 and 113 are shown without the serial port 170 as shown in FIG. 3 for clarity. In one embodiment, the first FCC112 can be the same as the second FCC113. In one embodiment, the selector 182 can be a microcontroller connected to the FCC112 and 113 via an output 185. Further, the selector 182 can have a configuration without having logic gates or transistors, etc. In another embodiment, a plurality of selectors can be connected to the FCC112 and 113.

[0032] In one embodiment, the integrated watchdog window 180 can be disposed on the chip of the selector 182. In another embodiment, the watchdog window 180 can be disposed on an external expansion card within the FCC chassis. The watchdog window 180 can communicate with at least one selector 182 to monitor the electrical pulses, or "watchdogs", emitted by each of the FCC112 and 113. The watchdog window may be found in an embedded system that is not easily accessible to an operator, such as the FCC112 and 113 mounted on a UAV. In such a system, the FCC112 and 113 may not rely on an operator to restart the FCC when it does not operate properly.

[0033] In one embodiment, one or more sensors 190 can be connected to both FCCs 112, 113. In one embodiment, the system can include three sensors 190. In one embodiment, each sensor may be identical. Each sensor 190 can detect information related to the health and performance of the FCC via output 184. The three sensors 190 can provide a triple-redundant critical flight sensor system. In one embodiment, FCCs 112, 113 can select the median value of a redundant set of three sensors 190 to evaluate the performance of FCCs 112, 113.

[0034] In one embodiment, watchdog window 180 monitors the electrical pulse, or "heartbeat," generated by FCC 112 as the heartbeat passes through the circuitry of FCC 112. For example, as shown in FIG. 5, a normal signal 192 is monitored by watchdog window 180, where the frequency window of signal 192 is within the preferred range for a first functioning FCC 112 as shown in FIG. 4. At another point in time, watchdog window 180 can detect a pulse, such as pulse 194, where the beat is too slow or a pulse that skips a beat. At yet another point in time, watchdog window 180 can detect a pulse, such as pulse 196, where the beat is too fast. In one embodiment, the performance specification may require that the frequency and amplitude of the FCC heartbeat be within a specific percentage range of the baseline pulse. In one embodiment, if signal 192 is outside the frequency window, e.g., the heartbeat is too fast or too slow, FCC 112 will be reset. Faulty pulses can be pulses outside the preferred range, pulses that skip a beat, pulses slower than the preferred range, pulses faster than the preferred range, and pulses having a frequency and amplitude outside the preferred range of the baseline pulse.

[0035] In one embodiment, if the watchdog window 180 does not detect a heartbeat, or if the detected heartbeat is abnormal for the first or active FCC 112, e.g., there is a time delay between consecutive pulses, the watchdog window 180 can tell the selector 182 to toggle to the second or backup FCC 113. In one embodiment, the power to the first FCC 112 is reset, and the identified problem may be resolved by resetting the memory and the processor. Thus, the first FCC 112 can back up and operate again immediately after powering on, allowing the UAV to maintain continuous flight. Further, since the selector 182 toggles to the normal second or backup FCC 113, continuous flight is not interrupted while operating on the second or backup FCC 113. In some embodiments, the second or backup FCC 113 may be a copy of the first FCC 112.

[0036] In one embodiment, if the watchdog window 180 detects normal pulses for the operating FCC 112 but does not detect pulses for the backup FCC 113, the selector 182 does not toggle to the backup FCC 113. In one embodiment, each FCC 112, 113 can last for about eight hours or more, which may be sufficient time to land the UAV after one of the FCCs 112, 113 fails. If the power is completely cut off and neither FCC can power on and function, the UAV can execute a landing procedure. In one embodiment, the landing procedure may be executed by activating a flight termination system.

[0037] FIG. 6 illustrates a flowchart of a method 200 of distributed computing for monitoring the performance of an FCC. In one embodiment, a watchdog window, such as watchdog window 180, can communicate with at least one selector, such as selector 182, to monitor electrical pulses emitted by an FCC, such as FCCs 112, 113, or a “watchdog”. The watchdog window monitors an electrical pulse (or “heartbeat”) generated by a first FCC as the heartbeat passes through the circuit of the first FCC (step 202). In one embodiment, the performance specification may require that the frequency and amplitude of the heartbeat of the first FCC be within a specific percentage range of the baseline pulse. The watchdog window can detect the absence of a pulse, or that the pulse is outside the frequency window of the preferred frequency range for an FCC that is functioning properly (step 204). The watchdog window can detect a fault pulse. A fault pulse can be a pulse outside the preferred range, a pulse that skips a beat, a pulse that is slower than the preferred range, a pulse that is faster than the preferred range, or a pulse having a frequency and amplitude outside the preferred range of the baseline pulse. The watchdog window can tell the selector to toggle to a backup second FCC (step 206). Thereafter, the second FCC can control the UAV and maintain the flight of the UAV (step 208). The power to the first FCC can be reset, and if the identified problem is resolved by resetting the memory and processor, it may be (step 210). Thus, the first FCC can back up and operate again immediately after powering on, and thus the UAV can maintain continuous flight. The selector can tell the watchdog window to toggle back to the first FCC when the first FCC becomes operational (step 212). The UAV can continue to fly with the first FCC once the first FCC becomes operational (step 214).The watchdog window can continue to monitor the electrical pulses generated by the first FCC (step 216).

[0038] FIG. 7 is a high-level block diagram 500 showing a computing system comprising a computer system useful for implementing one embodiment of the systems and processes disclosed herein. Embodiments of the system can be implemented in different computing environments. The computer system includes one or more processors 502 and further includes an electronic display device 504 (e.g., for displaying graphics, text, and other data), a main memory 506 (e.g., random access memory (RAM)), a storage device 508, a removable storage device 510 (e.g., a removable storage drive, a removable memory module, a magnetic tape drive, an optical disk drive, a computer-readable medium storing computer software and / or data therein), a user interface device 511 (e.g., a keyboard, a touch screen, a keypad, a pointing device), and a communication interface 512 (e.g., a modem, a network interface (such as an Ethernet card), a communication port, or a PCMCIA slot and card). The communication interface 512 enables software and data to be transferred between the computer system and external devices. The system further includes a communication infrastructure 514 (e.g., a communication bus, a crossover bar, or a network) to which the aforementioned devices / modules are connected as shown.

[0039] The information transferred via communication interface 514 can be in the form of signals such as electronic, electromagnetic, optical or other signals that can be transmitted and received by communication interface 514 via a communication link 516 that can be implemented using a wire or cable, optical fiber, telephone line, cellular phone / cellular phone link, radio frequency (RF) link and / or other communication channels. Computer program instructions representing the block diagrams and / or flowcharts herein can be loaded into a computer, programmable data processing apparatus or processing apparatus, where they cause a series of operations to be performed to generate a computer implemented process.

[0040] Embodiments have been described with reference to the flowchart diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to the embodiments. Each block of such example / diagram, or combinations thereof, can be implemented by computer program instructions. When the computer program instructions are provided to a processor, they generate a machine that creates means for performing the functions / operations specified in the flowchart and / or block diagram via the processor. Each block of the flowchart / block diagram can represent a hardware and / or software module or logic for implementing the embodiment. In alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures and may occur concurrently.

[0041] The computer program (i.e., computer control logic) is stored in main memory and / or auxiliary memory. The computer program can also be received via communication interface 512. When such computer program is executed, it enables the computer system to perform the features of the embodiments as discussed herein. In particular, when the computer program is executed, it enables the processor and / or multi-core processor to perform the features of the computer system. Such computer program represents the controller of the computer system.

[0042] FIG. 8 shows a block diagram of an exemplary system 600 in which one embodiment may be implemented. System 600 includes one or more client devices 601, such as household electronic devices, connected to one or more server computing systems 630. Server 630 includes a bus 602 or other communication mechanism for communicating information, and a processor (CPU) 604 coupled to bus 602 for processing information. Server 630 also includes main memory 606, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 602 for storing information and instructions to be executed by processor 604. Main memory 606 may also be used to store temporary variables or other intermediate information during execution, or instructions being executed by processor 604. Server computer system 630 further includes a read only memory (ROM) 608 or other static storage device coupled to bus 602 for storing static information and instructions for processor 604. A storage device 610, such as a magnetic disk or optical disk, is provided and coupled to bus 602 for storing information and instructions. Bus 602 may include, for example, 32 address lines for addressing video memory or main memory 606. Bus 602 may also include, for example, a 32-bit data bus for transferring data among and within components, such as CPU 604, main memory 606, video memory, and storage 610. Alternatively, multiplexed data / address lines may be used instead of separate data and address lines.

[0043] Server 630 may be coupled via bus 602 to a display 612 for displaying information to a computer user. An input device 614 including alphanumeric and other keys is coupled to bus 602 for communicating information and command selections to processor 604. Another type of user input device includes cursor control 616, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 604 and for controlling cursor movement on display 612.

[0044] According to one embodiment, functionality is performed by a processor 604 executing one or more sequences of one or more instructions contained in main memory 606. Such instructions may be read into main memory 606 from another computer-readable medium, such as storage device 610. Execution of the sequences of instructions contained in main memory 606 causes processor 604 to perform the process steps described herein. One or more processors in a multiprocessing configuration may be employed to execute the sequences of instructions contained in main memory 606. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions to implement the embodiments. Accordingly, the embodiments are not limited to any specific combination of hardware circuitry and software.

[0045] The terms "computer program medium", "computer-usable medium", "computer-readable medium", and "computer program product" are generally used to refer to media such as main memory, auxiliary memory, removable storage drives, hard disks installed in hard disk drives, and signals. These computer program products are means for providing software to a computer system. A computer-readable medium enables a computer system to read data, instructions, messages or message packets, and other computer-readable information from the computer-readable medium. A computer-readable medium can include, for example, non-volatile memory such as floppy disks, ROM, flash memory, disk drive memory, CD-ROM, and other permanent storage. For example, it is useful when transferring information such as data and computer instructions between computer systems. Further, a computer-readable medium can include computer-readable information in a transitory state medium such as a network link and / or network interface including a wired network or a wireless network that enables a computer to read such computer-readable information. A computer program (also referred to as computer control logic) is stored in main memory and / or auxiliary memory. A computer program can also be received via a communication interface. When such a computer program is executed, it enables a computer system to perform the features of the embodiments discussed herein. In particular, when a computer program is executed, it enables a processor multi-core processor to perform the features of a computer system. Thus, such a computer program represents the controller of a computer system.

[0046] In general, the term "computer-readable medium" as used herein refers to any medium that participates in providing instructions to a processor 604 for execution. Such a medium can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 610. Volatile media includes dynamic memory, such as main memory 606. Transmission media includes coaxial cables, copper wire, and fiber optics, including the wires that make up bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio-wave or infrared data communications.

[0047] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, or any other magnetic medium, CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium that can be read by a computer.

[0048] Various forms of computer-readable media may be involved in holding one or more sequences of one or more instructions for execution by processor 604. For example, the instructions may initially be executed on the magnetic disk of a remote computer. The remote computer can load the instructions into dynamic memory and transmit the instructions over a telephone line using a modem. A modem local to server 630 can receive the data over the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to bus 602 can receive the data held in the infrared signal and place that data on bus 602. Bus 602 transmits the data to main memory 606, from which processor 604 reads and executes the instructions. The instructions received from main memory 606 may optionally be stored on storage device 610 either before or after execution by processor 604.

[0049] Server 630 also includes a communication interface 618 coupled to bus 602. Communication interface 618 provides bi-directional data communication coupling to a network link 620 that is connected to a worldwide packet data communication network now commonly referred to as the Internet 628. The Internet 628 uses electrical, electromagnetic, or optical signals that carry digital data streams. Signals via various networks and on network link 620, as well as signals through communication interface 618 that hold digital data to and from server 630, are exemplary forms or carrier waves that convey information.

[0050] In another embodiment of server 630, interface 618 is connected to network 622 via communication link 620. For example, communication interface 618 can be an integrated services digital network (ISDN) card or modem for providing a data communication connection to a corresponding type of telephone line that can form part of network link 620. As another example, communication interface 618 can be a local area network (LAN) card for providing a data communication connection to a compatible LAN. A wireless link can also be implemented. In any such implementation, communication interface 618 transmits and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0051] Network link 620 typically provides data communication to other data devices through one or more networks. For example, network link 620 may provide a connection through local network 622 to a data device operated by host computer 624 or an Internet service provider (ISP). The ISP then provides data communication services through Internet 628. Both local network 622 and Internet 628 use electrical, electromagnetic, or optical signals that carry digital data streams. Signals through various networks and on network link 620, as well as signals through communication interface 618 that transmit digital data to and from server 630, are exemplary forms or carriers that transmit information.

[0052] Server 630 can send and receive messages and data, including e-mail, and program code, through the network, network link 620, and communication interface 618. Further, communication interface 618 can include a USB / tuner, and network link 620 can be an antenna or cable for connecting server 630 to a cable provider, satellite provider, or other terrestrial transmission system for receiving messages, data, and program code from another source.

[0053] An exemplary version of the embodiments described herein can be implemented as logical operations in a distributed processing system such as system 600 that includes server 630. The logical operations of the embodiments can be implemented as a series of steps executed within server 630 and as interconnected machine modules within system 600. The implementation is a matter of choice and can depend on the performance of system 600 implementing the embodiments. Accordingly, the logical operations that make up the exemplary version of the embodiments are referred to as operations, steps, or modules, for example.

[0054] Similar to the server 630 described above, the client device 601 can include a processor, a memory, a storage device, a display, an input device, and a communication interface (e.g., an email interface) for connecting the client device to the Internet 628, an ISP, or a LAN 622 for communication with the server 630.

[0055] The system 600 can further include a computer (e.g., a personal computer, a computing node) 605 that operates in the same manner as the client device 601, and a user can use one or more computers 605 to manage data within the server 630.

[0056] Referring now to FIG. 9, an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 that can communicate with local computing devices used by cloud consumers such as, for example, a personal digital assistant (PDA), smartphone, smartwatch, set-top box, video game system, tablet, mobile computing device or cellular phone 54A, desktop computer 54B, laptop computer 54C, and / or automotive computer system 54N. The nodes 10 can communicate with each other. They can be grouped physically or virtually into one or more networks such as the private, community, public, or hybrid clouds described above, or combinations thereof (not shown). Thereby, the cloud computing environment 50 can provide infrastructure, platform, and / or software as a service such that cloud consumers need not maintain resources on local computing devices. It is to be understood that the types of computing devices 54A - N shown in FIG. 9 are for illustrative purposes only and that the computing nodes 10 and the cloud computing environment 50 can communicate with any type of computerized device via any type of network and / or network addressable connection (e.g., using a web browser).

[0057] It is contemplated that various combinations and / or sub - combinations of the specific features and aspects of the above - described embodiments may be made and still fall within the scope of the present invention. Accordingly, it should be understood that the various features and aspects of the disclosed embodiments may be combined with each other or replaced with each other to form various modes of the disclosed invention. Further, it is intended that the scope of the present invention as disclosed herein by way of example should not be limited by the specific disclosed embodiments described above.

Claims

1. a first FCC (112) of two or more flight control computers (FCCs) (112, 113); a second FCC (113) of the two or more FCCs; and at least one selector (182) in communication with the first FCC; at least one watchdog window (180) in communication with the at least one selector (182), the at least one watchdog window monitoring performance of the first FCC (112) based on electrical pulses (192, 194, 196) emitted by the FCC (112); the at least one watchdog window is configured to detect fault pulses among electrical pulses emitted by the first FCC; The system of claim 1, wherein the selector is configured to toggle to the second FCC based on a detected fault pulse emitted by the first FCC.

2. 2. The system of claim 1, The system wherein the detected fault pulse is a pulse that is outside a preferred range.

3. 2. The system of claim 1, The system according to claim 1, wherein the detected interfering pulse is a beat skipping pulse.

4. 2. The system of claim 1, The system wherein the detected interfering pulse is a pulse having a frequency and amplitude outside a preferred range of a baseline pulse.

5. 2. The system of claim 1, The system, wherein the selector is further configured to reset power to the first FCC.

6. 6. The system of claim 5, The system according to claim 1, wherein the selector is configured to reset power to the first FCC and then toggle to the first FCC.

7. 7. The system of claim 6, The system, wherein the at least one watchdog window is further configured to monitor performance of the first FCC after toggling to the first FCC by the selector.

8. monitoring, with a watchdog window (180), performance of a first FCC (112) of two or more flight control computers (FCCs), said performance being based on electrical pulses (192, 194, 196) emitted by the first FCC; detecting, via the watchdog window, a fault pulse among the electrical pulses emitted by the first FCC; and toggling, by a selector in communication with the watchdog window, to a second FCC (113) based on a detected fault pulse emitted by the first FCC.

9. 9. The method of claim 8, The method, wherein the detected fault pulse is a pulse that is outside a preferred range.

10. 9. The method of claim 8, 4. The method of claim 3, wherein the detected interfering pulse is a beat skipping pulse.

11. 9. The method of claim 8, The method of claim 1, wherein the detected interfering pulse is a pulse having a frequency and amplitude outside a preferred range of a baseline pulse.

12. 9. The method of claim 8, The method of claim 1, further comprising the step of resetting power to the first FCC via the selector.

13. 13. The method of claim 12, The method of claim 1, further comprising the step of toggling the first FCC with the selector after resetting power to the first FCC.

14. 14. The method of claim 13, the method further comprising monitoring performance of the first flight control computer (FCC) after toggling the first FCC with the selector via the watchdog window.

15. A flight control computer (112), A field programmable gate array (FPGA) (152); a Flight Control Computer (FCC) processor (153) in communication with said FPGA via an FCC bus (160); a plurality of serial ports (170) in communication with said FPGA and FCC processor; a controller chip in communication with the plurality of serial ports, the controller chip configured to convert a parallel output of the FCC bus to a serial format for transmission over a serial port of the plurality of serial ports.

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