Display device

Abstract

To provide a display device with a narrowed frame.SOLUTION: A display device includes a first layer, a second layer, and a third layer that are stacked. The first layer includes a gate driver circuit and a data driver circuit. The second layer includes a demultiplexer circuit. The third layer includes a display part. In the display part, pixels are arranged in matrix. An input terminal of the demultiplexer circuit is electrically connected to the data driver circuit. An output terminal of the demultiplexer circuit is electrically connected to the pixel. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the pixel. The gate driver circuit and the data driver circuit are not clearly separated and include an overlapping region. Five or more gate driver circuits and five or more data driver circuits can be provided.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a semiconductor device is disclosed in which a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer serving as a channel contains indium and gallium, and the ratio of indium is made larger than the ratio of gallium to increase the field-effect mobility (sometimes simply referred to as mobility or μFE).

[0004] Since the metal oxide that can be used for the semiconductor layer can be formed by a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large display device. In addition, since it is possible to improve and use a part of the production equipment of a transistor using polycrystalline silicon or amorphous silicon, capital investment can be suppressed. Further, a transistor using a metal oxide has a higher field-effect mobility than a case where amorphous silicon is used, so that a high-functional display device provided with a driving circuit can be realized.

[0005] In addition, as display devices for augmented reality (AR) or virtual reality (VR), wearable display devices and stationary display devices are becoming increasingly popular. Examples of wearable display devices include head-mounted displays (HMDs) and glasses-type display devices. Examples of stationary display devices include head-up displays (HUDs).

[0006] Furthermore, an electronic viewfinder is used as a viewfinder provided in an electronic device having an imaging device, such as a digital camera, for confirming an image to be captured before capturing. The electronic viewfinder is provided with a display unit, and an image obtained by an imaging device can be displayed as an image on the display unit. For example, Patent Document 2 discloses an electronic viewfinder capable of obtaining a good visibility state from the center portion to the peripheral portion of an image.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] In a display device such as a head-mounted display (HMD) where the distance between the display surface and the user is short, the user can easily see the pixels, and thus may strongly feel the granularity, which may reduce the immersion and presence of AR or VR. In addition, an electronic viewfinder is provided with an eyepiece portion similar to an optical viewfinder, and an image displayed on the display portion of the electronic viewfinder is viewed by bringing the user's eye close to the eyepiece portion. Therefore, the distance between the display portion of the electronic viewfinder and the user becomes short. As a result, since the user can easily see the pixels provided in the display portion, the user may strongly feel the granularity. For the above reasons, in an HMD and an electronic viewfinder, a display device having fine pixels is desired so that the user does not see the pixels. For example, it is preferable that the pixel density is 1000 ppi or more, more preferably 2000 ppi or more, and even more preferably 5000 ppi or more. Further, for example, in a display device provided in an electronic viewfinder, it is preferable that an image with a resolution of 4K (number of pixels: 3840 × 2160), 5K (number of pixels: 5120 × 2880), or higher can be displayed.

[0009] On the other hand, when the pixel density increases, transistors and the like provided in a drive circuit such as a data driver circuit also need to be provided with high-density integration. However, due to reasons such as the limit of high-density integration, the occupied area of the data driver circuit may be larger than the area of the display portion. As a result, the frame, which is the area where the display portion is not provided, may become larger.

[0010] One aspect of the present invention aims to provide a display device with a narrow bezel. Or, one aspect of the present invention aims to provide a small-sized display device. Or, one aspect of the present invention aims to provide a display device with a high degree of layout freedom. Or, one aspect of the present invention aims to provide a display device with a high pixel density. Or, one aspect of the present invention aims to provide a display device capable of displaying a high-definition image. Or, one aspect of the present invention aims to provide a display device capable of displaying a high-quality image. Or, one aspect of the present invention aims to provide a display device capable of displaying an image with a high sense of presence. Or, one aspect of the present invention aims to provide a display device capable of displaying a high-brightness image. Or, one aspect of the present invention aims to provide a display device that operates at high speed. Or, one aspect of the present invention aims to provide a display device with low power consumption. Or, one aspect of the present invention aims to provide an inexpensive display device. Or, one aspect of the present invention aims to provide a highly reliable display device. Or, one aspect of the present invention aims to provide a novel display device. Or, one aspect of the present invention aims to provide an operation method for the above display device. Or, one aspect of the present invention aims to provide an electronic device having the above display device.

[0011] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention is a display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit. The second layer has a demultiplexer circuit. The third layer has a display unit. In the display unit, pixels are arranged in a matrix. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit. The output terminals of the demultiplexer circuit are electrically connected to the pixels. The gate driver circuit has a region overlapping with the pixels. The data driver circuit has a region overlapping with the pixels. The gate driver circuit has a region overlapping with the data driver circuit.

[0013] Alternatively, in the above aspect, the demultiplexer circuit may have a region overlapping with the pixels.

[0014] Alternatively, in the above aspect, the display device has a D / A conversion circuit. The D / A conversion circuit has a potential generation circuit and a pass transistor logic circuit. The potential generation circuit is provided outside the data driver circuit. The pass transistor logic circuit is provided in the data driver circuit. The number of pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of pixels provided in the display unit. The number of potential generation circuits provided in the D / A conversion circuit is less than the number of pass transistor logic circuits. The potential generation circuit has a function of generating a plurality of potentials having different magnitudes from each other. The pass transistor logic circuit may have a function of receiving image data and outputting any one of the potentials generated by the potential generation circuit based on the digital value of the image data.

[0015] Alternatively, in the above aspect, the number of pass transistor logic circuits may be 1 / 2 or less of the number of columns of pixels.

[0016] Alternatively, in the above aspect, the pixel has a transistor having a metal oxide in a channel formation region. The metal oxide may have In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0017] Alternatively, one aspect of the present invention is a display device in which a first layer, a second layer, and a third layer are laminated. The first layer includes a gate driver circuit, a first data driver circuit, a second data driver circuit, a third data driver circuit, a fourth data driver circuit, and a fifth data driver circuit. The second layer includes a first demultiplexer circuit, a second demultiplexer circuit, a third demultiplexer circuit, a fourth demultiplexer circuit, and a fifth demultiplexer circuit. The third layer includes a first display portion, a second display portion, a third display portion, a fourth display portion, and a fifth display portion. In the first display portion, first pixels are arranged in a matrix. In the second display portion, second pixels are arranged in a matrix. In the third display portion, third pixels are arranged in a matrix. In the fourth display portion, fourth pixels are arranged in a matrix. In the fifth display portion, fifth pixels are arranged in a matrix. The input terminals of the first demultiplexer circuit are electrically connected to the first data driver circuit. The input terminals of the second demultiplexer circuit are electrically connected to the second data driver circuit. The input terminals of the third demultiplexer circuit are electrically connected to the third data driver circuit. The input terminals of the fourth demultiplexer circuit are electrically connected to the fourth data driver circuit. The input terminals of the fifth demultiplexer circuit are electrically connected to the fifth data driver circuit. The output terminals of the first demultiplexer circuit are electrically connected to the first pixels. The output terminals of the second demultiplexer circuit are electrically connected to the second pixels. The output terminals of the third demultiplexer circuit are electrically connected to the third pixels. The output terminals of the fourth demultiplexer circuit are electrically connected to the fourth pixels. The output terminals of the fifth demultiplexer circuit are electrically connected to the fifth pixels. The gate driver circuit has an area overlapping with the first pixels. The first data driver circuit has an area overlapping with the first pixels. The second data driver circuit has an area overlapping with the second pixels. The third data driver circuit has an area overlapping with the third pixels. The fourth data driver circuit has an area overlapping with the fourth pixels. The fifth data driver circuit has an area overlapping with the fifth pixels. The gate driver circuit isA display device having an area overlapping with the first data driver circuit.

[0018] Alternatively, in the above aspect, the first demultiplexer circuit may have an area overlapping with the first pixel, the second demultiplexer circuit may have an area overlapping with the second pixel, the third demultiplexer circuit may have an area overlapping with the third pixel, the fourth demultiplexer circuit may have an area overlapping with the fourth pixel, and the fifth demultiplexer circuit may have an area overlapping with the fifth pixel.

[0019] Alternatively, in the above aspect, the display device has a D / A conversion circuit, and the D / A conversion circuit includes a potential generation circuit, a first pass transistor logic circuit, a second pass transistor logic circuit, a third pass transistor logic circuit, a fourth pass transistor logic circuit, and a fifth pass transistor logic circuit. The potential generation circuit is provided outside the first to fifth data driver circuits. The first pass transistor logic circuit is provided in the first data driver circuit. The second pass transistor logic circuit is provided in the second data driver circuit. The third pass transistor logic circuit is provided in the third data driver circuit. The fourth pass transistor logic circuit is provided in the fourth data driver circuit. The fifth pass transistor logic circuit is provided in the fifth data driver circuit. The number of the first pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the first pixels provided in the first display unit. The number of the second pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the second pixels provided in the second display unit. The number of the third pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the third pixels provided in the third display unit. The number of the fourth pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the fourth pixels provided in the fourth display unit. The number of the fifth pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the fifth pixels provided in the fifth display unit. The number of the potential generation circuits provided in the D / A conversion circuit is less than the number of the first pass transistor logic circuits. The number of the potential generation circuits provided in the D / A conversion circuit is less than the number of the second pass transistor logic circuits. The number of the potential generation circuits provided in the D / A conversion circuit is less than the number of the third pass transistor logic circuits. The number of the potential generation circuits provided in the D / A conversion circuit is less than the number of the fourth pass transistor logic circuits. The number of the potential generation circuits provided in the D / A conversion circuit is less than the number of the fifth pass transistor logic circuits. The potential generation circuit has a function of generating a plurality of potentials having different magnitudes from each other. The first to fifth pass transistor logic circuits receive image data,It may have a function of outputting any one of the potentials generated by the potential generation circuit based on the digital value of the image data.

[0020] Alternatively, in the above aspect, the number of the first pass transistor logic circuits is 1 / 2 or less of the number of columns of the first pixel, the number of the second pass transistor logic circuits is 1 / 2 or less of the number of columns of the second pixel, the number of the third pass transistor logic circuits is 1 / 2 or less of the number of columns of the third pixel, the number of the fourth pass transistor logic circuits is 1 / 2 or less of the number of columns of the fourth pixel, and the number of the fifth pass transistor logic circuits may be 1 / 2 or less of the number of columns of the fifth pixel.

[0021] Alternatively, in the above aspect, the first to fifth pixels may have a transistor having a metal oxide in a channel formation region, and the metal oxide may contain In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Advantages of the Invention

[0022] According to one aspect of the present invention, a display device with a narrow bezel can be provided. Or, according to one aspect of the present invention, a small-sized display device can be provided. Or, according to one aspect of the present invention, a display device with a high degree of layout freedom can be provided. Or, according to one aspect of the present invention, a display device with a high pixel density can be provided. Or, according to one aspect of the present invention, a display device capable of displaying a high-definition image can be provided. Or, according to one aspect of the present invention, a display device capable of displaying a high-quality image can be provided. Or, according to one aspect of the present invention, a display device capable of displaying an image with a high sense of presence can be provided. Or, according to one aspect of the present invention, a display device capable of displaying a high-brightness image can be provided. Or, according to one aspect of the present invention, a display device that operates at high speed can be provided. Or, according to one aspect of the present invention, a display device with low power consumption can be provided. Or, according to one aspect of the present invention, an inexpensive display device can be provided. Or, according to one aspect of the present invention, a highly reliable display device can be provided. Or, according to one aspect of the present invention, a novel display device can be provided. Or, according to one aspect of the present invention, an operation method of the above display device can be provided. Or, according to one aspect of the present invention, an electronic device having the above display device can be provided.

[0023] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0024]

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Mode for Carrying Out the Invention

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0026] Also, in each figure described in this specification, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity.

[0027] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are attached to avoid confusion of components and are not numerically limiting.

[0028] Also, in this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0029] Also, in this specification and the like, the functions of the source and drain of a transistor may be interchanged in cases such as when the polarity of the transistor or the direction of current changes in the circuit operation. For this reason, the terms source and drain can be used interchangeably.

[0030] In this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Further, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and for example, a "terminal" can be part of "wiring" or "electrode". Also, the terms "electrode", "wiring", "terminal", etc. may be replaced by terms such as "region" in some cases.

[0031] In addition, in this specification and the like, the resistance value of "resistance" may be determined by the length of the wiring. Alternatively, the resistance value may be determined by connecting a conductor having a resistivity different from that of the conductor used in the wiring. Alternatively, the resistance value may be determined by doping a semiconductor with an impurity.

[0032] In addition, in this specification and the like, "electrically connected" includes both the case of direct connection and the case of being connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only the wiring extends. Also, even when expressed as "direct connection", the case where different conductors are connected via a contact is included. Note that the wiring may be such that different conductors contain one or more of the same elements or different elements.

[0033] In addition, in this specification and the like, the term "film" and the term "layer" can be interchanged with each other. For example, terms such as "conductive layer" and "insulating layer" may be mutually interchangeable with terms such as "conductive film" and "insulating film".

[0034] In addition, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor, is a state where the voltage V gs between the gate and the source is lower than the threshold voltage V th (for a p-channel type transistor, higher than V th ).

[0035] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally reduced in thickness due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same part or parts having the same function, material, etc. between different drawings, and repeated explanations may be omitted. Also, when referring to parts having the same function, material, etc., the hatching pattern may be the same and may not be particularly labeled with a reference numeral.

[0036] In this specification, etc., a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be paraphrased as a transistor having an oxide or an oxide semiconductor.

[0037] (Embodiment 1) In this embodiment, a display device which is one aspect of the present invention will be described.

[0038] One aspect of the present invention relates to a display device in which a first layer, a second layer, and a third layer are laminated. The first layer has a gate driver circuit and a data driver circuit, the second layer has a demultiplexer circuit, and the third layer has a display section. Pixels are arranged in a matrix in the display section. The gate driver circuit and the data driver circuit are provided so as to have a region overlapping with the display section. Thereby, the display device of one aspect of the present invention can be made to have a narrow bezel and can also be miniaturized.

[0039] In addition, the gate driver circuit and the data driver circuit are not clearly separated and have an overlapping region. As a result, the display device can be made narrower and smaller than in the case where there is no such overlapping region.

[0040] Here, when the gate driver circuit and the data driver circuit are configured not to overlap with the display portion, the gate driver circuit and the data driver circuit are provided, for example, on the outer peripheral portion of the display portion. In this case, it is difficult to provide more display portions than two rows and two columns from the viewpoint of the installation location of the data driver circuit and the like. On the other hand, in the display device according to one aspect of the present invention, the gate driver circuit and the data driver circuit can be provided in a layer different from the layer in which the display portion is provided so as to have an overlapping region with the display portion. Therefore, more display portions than two rows and two columns can be provided. That is, in the display device according to one aspect of the present invention, five or more gate driver circuits and data driver circuits can be provided respectively.

[0041] As described above, by providing the gate driver circuit and the data driver circuit so as to have an overlapping region with the display portion, the gate driver circuit and the data driver circuit can be operated, for example, at a higher speed than in a display device configured such that the gate driver circuit and the data driver circuit do not overlap with the display portion. Therefore, the pixel density of the display device according to one aspect of the present invention can be increased compared to a display device configured such that the gate driver circuit and the data driver circuit do not overlap with the display portion. For example, the pixel density of the display device according to one aspect of the present invention can be 1000 ppi or more, 2000 ppi or more, and 5000 ppi or more. As a result, the display device according to one aspect of the present invention can display a high-definition image.

[0042] Here, when increasing the pixel density of the display device according to one aspect of the present invention, transistors and the like provided in a driving circuit such as a data driver circuit also need to be provided with high-density integration. However, due to reasons such as the limit of high-density integration, the occupied area of the data driver circuit may become larger compared to the area of the display unit. As a result, the area of the portion of the data driver circuit that does not overlap with the display unit becomes larger, and thus the frame, which is the area where the display unit is not provided, may become larger.

[0043] On the other hand, in the display device according to one aspect of the present invention, as described above, a demultiplexer circuit is provided in the second layer. The input terminals of the demultiplexer circuit are electrically connected to the data driver circuit, and the output terminals of the demultiplexer circuit are electrically connected to the pixels. Specifically, when the demultiplexer circuit has a first output terminal and a second output terminal as output terminals, the first output terminal and the second output terminal are electrically connected to pixels in different columns. Thereby, the demultiplexer circuit can have a function of switching the supply destination of the image data generated by the data driver circuit. Therefore, the configuration of the data driver circuit can be made simple. Specifically, for example, the number of elements such as transistors included in the data driver circuit can be reduced. Thereby, the occupied area of the data driver circuit can be reduced. Therefore, the area of the portion of the data driver circuit that does not overlap with the display unit can be reduced. Thereby, the display device according to one aspect of the present invention can be made into a narrow frame.

[0044] The demultiplexer circuit is provided in a layer different from both the layer in which the data driver circuit is provided and the layer in which the display unit is provided as described above. Thereby, while increasing the degree of freedom of layout, the demultiplexer circuit can be provided so as to have an area overlapping with the display unit. Therefore, compared to the case where the demultiplexer circuit is provided in the same layer as the data driver circuit, for example, the display device according to one aspect of the present invention can be made into an even narrower frame and can also be miniaturized.

[0045] <Configuration Example 1 of Display Device 10> FIG. 1A is a block diagram showing a configuration example of a display device 10 which is an aspect of the present invention. The display device 10 includes a gate driver circuit 21, a data driver circuit 22, and a circuit 40. The display device 10 also includes a display unit 33 in which pixels 34 are arranged in a matrix of m rows and n columns (m and n are integers of 1 or more). Further, the display device 10 includes a demultiplexer circuit 81.

[0046] In this specification etc., when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, a distinguishing reference numeral such as “_1”, “_2”, “[n]”, “[m,n]” etc. may be appended to the reference numeral for description. For example, the pixel 34 at the first row and first column is described as pixel 34[1,1], and the pixel 34 at the m-th row and n-th column is described as pixel 34[m,n].

[0047] The data driver circuit 22 is electrically connected to the input terminal of the demultiplexer circuit 81 via a wiring 82. Also, the selection control signal input terminal of the demultiplexer circuit 81 is electrically connected to a wiring 83. Further, the demultiplexer circuit 81 has a plurality of output terminals, and the plurality of output terminals are electrically connected to the pixels 34 via different wirings 32.

[0048] In this specification etc., when referring to “the output terminal of the demultiplexer circuit”, it may indicate any one of the plurality of output terminals of the demultiplexer circuit. For example, in the case of “the wiring is electrically connected to the output terminal of the demultiplexer circuit.”, the wiring may be electrically connected to one of the plurality of output terminals.

[0049] The gate driver circuit 21 is electrically connected to the pixels 34 via a wiring 31. Also, the circuit 40 is electrically connected to the data driver circuit 22. Note that the circuit 40 may be electrically connected to other circuits etc.

[0050] In FIG. 1A, it shows a configuration where pixels 34 in the same column are electrically connected to the same wiring 32, and pixels 34 in the same row are electrically connected to the same wiring 31. In this specification and the like, for example, the wiring 32 electrically connected to the pixels 34 in the first column is described as wiring 32[1], and the wiring 32 electrically connected to the pixels 34 in the nth column is described as wiring 32[n]. Also, for example, the wiring 31 electrically connected to the pixels 34 in the first row is described as wiring 31[1], and the wiring 31 electrically connected to the pixels 34 in the mth row is described as wiring 31[m].

[0051] The data driver circuit 22 has a function of generating image data. The image data is supplied to the demultiplexer circuit 81 via the wiring 82.

[0052] The demultiplexer circuit 81 has a function of outputting the image data input from the input terminal from any one of a plurality of output terminals according to the signal input to the selection control signal input terminal, that is, according to the potential of the wiring 83. For example, when the demultiplexer circuit 81 has a first output terminal and a second output terminal, and the selection control signal is a 1-bit digital signal, when the selection control signal is at a high potential, the input image data can be output from the first output terminal. On the other hand, when the selection control signal is at a low potential, the image data input to the demultiplexer circuit 81 can be output from the second output terminal. Note that when the selection control signal is at a low potential, the image data input to the demultiplexer circuit 81 may be output from the first output terminal, and when it is at a high potential, it may be output from the second output terminal.

[0053] As described above, the image data input to the demultiplexer circuit 81 is output to the wiring 32 and supplied to the pixels 34. Therefore, the wiring 32 can have a function as a data line.

[0054] As described above, the demultiplexer circuit 81 has a plurality of output terminals and can be electrically connected to one wiring 32 per output terminal. Therefore, the number of demultiplexer circuits 81 included in the display device 10 can be made less than n, which is the number of columns of the pixels 34. For example, when the demultiplexer circuit 81 has a first output terminal and a second output terminal as output terminals, the display device 10 can have n / 2 demultiplexer circuits 81. Also, when the demultiplexer circuit 81 has a first output terminal, a second output terminal, and a third output terminal as output terminals, the display device 10 can have n / 3 demultiplexer circuits 81. Further, when the demultiplexer circuit 81 has first to k (k is an integer of 2 or more and n or less) output terminals as output terminals, the display device 10 can have n / k demultiplexer circuits 81.

[0055] Note that the number of bits of the selection control signal can be set according to the number of output terminals of the demultiplexer circuit 81. For example, when the demultiplexer circuit 81 has first to fourth output terminals, the selection control signal can be a 2-bit digital signal. For example, when the demultiplexer circuit 81 has first to k output terminals, the selection control signal can be a log2(k)-bit digital signal.

[0056] FIG. 1A shows a case where the demultiplexer circuit 81 has a first output terminal and a second output terminal as output terminals. In this case, as described above, the display device 10 can have n / 2 demultiplexer circuits 81.

[0057] In this specification and the like, a plurality of demultiplexer circuits 81 are described and distinguished as demultiplexer circuit 81[1], demultiplexer circuit 81[2], etc. For example, n / 2 demultiplexer circuits 81 are described as demultiplexer circuit 81[1] to demultiplexer circuit 81[n / 2] to distinguish them from each other. Note that, for example, the wiring 82 electrically connected to the input terminal of the demultiplexer circuit 81[1] is described as wiring 82[1], and the wiring 83 electrically connected to the selection control signal input terminal of the demultiplexer circuit 81[1] is described as wiring 83[1]. Also, for example, the wiring 82 electrically connected to the input terminal of the demultiplexer circuit 81[n / 2] is described as wiring 82[n / 2], and the wiring 83 electrically connected to the selection control signal input terminal of the demultiplexer circuit 81[n / 2] is described as wiring 83[n / 2].

[0058] The gate driver circuit 21 has a function of selecting a pixel 34 to which a potential corresponding to the image data generated by the data driver circuit 22 is written. For example, the gate driver circuit 21 can generate a selection signal and supply the selection signal to the pixels 34 in a specific row. A potential corresponding to the image data can be written to the pixel 34 to which the selection signal is supplied.

[0059] Here, the gate driver circuit 21, for example, selects the pixels 34 in the first row and then the pixels 34 in the second row, sequentially selects the pixels 34 up to the m-th row, and then selects the pixels 34 in the first row again. That is, it can be said that the gate driver circuit 21 has a function of scanning the pixels 34. Also, the selection signal can be supplied from the gate driver circuit 21 to the pixel 34 via the wiring 31. From the above, it can be said that the wiring 31 has a function as a scanning line. Note that when performing interlace driving, after selecting the pixels 34 in the first row, the pixels 34 in the second row are not selected, and for example, the pixels 34 in the third row or the fourth row and later are selected. For example, when m is an even number, the pixels 34 in the odd rows can be sequentially selected, and then the pixels 34 in the even rows can be sequentially selected.

[0060] Circuit 40 has a function of receiving, for example, data that serves as the basis for the image data generated by data driver circuit 22 and supplying the received data to data driver circuit 22. Also, circuit 40 has a function as a control circuit that generates a start pulse signal, a clock signal, etc. In addition, circuit 40 can be a circuit having functions that gate driver circuit 21 and data driver circuit 22 do not have.

[0061] Display unit 33 has a function of displaying an image corresponding to the image data supplied to pixel 34. Specifically, an image is displayed on display unit 33 by emitting light with a luminance corresponding to the image data from pixel 34.

[0062] Note that the color of the light emitted from pixel 34 can be, for example, red, green, blue, etc. For example, by providing display unit 33 with pixel 34 that emits red light, pixel 34 that emits green light, and pixel 34 that emits blue light, display device 10 can perform full-color display. In this case, pixel 34 can be said to be a sub-pixel.

[0063] FIG. 1B is a schematic diagram showing a configuration example of display device 10. As shown in FIG. 1B, display device 10 can have a stacked configuration of layer 20, layer 80, and layer 30. FIG. 1B shows a configuration in which layer 80 is provided above layer 20 and layer 30 is provided above layer 80. An interlayer insulating layer can be provided between layer 20 and layer 80 and between layer 80 and layer 30. Note that the stacking order of layer 20, layer 80, and layer 30 is not limited to that shown in FIG. 1B. For example, layer 80 may be provided above layer 30 and layer 20 may be provided above layer 80.

[0064] In layer 20, for example, a gate driver circuit 21, a data driver circuit 22, and a circuit 40 can be provided. In layer 80, for example, a demultiplexer circuit 81 can be provided. In layer 30, for example, a display unit 33 can be provided. Here, the gate driver circuit 21, the data driver circuit 22, and the circuit 40 etc. provided in layer 20 are circuits necessary for driving the display device 10. Therefore, these circuits can be called driving circuits. Note that the demultiplexer circuit 81 may also be called a driving circuit.

[0065] FIG. 2 is a diagram showing a configuration example of layer 20, layer 80, and layer 30 shown in FIG. 1B. In FIG. 2, the positional relationship between layer 20 and layer 30 is shown by a dashed line and an open circle, and the open circles of layer 20 and the open circles of layer 30 connected by the dashed line overlap each other. Note that the same notation is used in other figures as well.

[0066] The display device 10 has a region where the gate driver circuit 21 and the data driver circuit 22 provided in layer 20 overlap with the display unit 33. For example, the gate driver circuit 21 and the data driver circuit 22 have a region that overlaps with the pixel 34. By laminating the gate driver circuit 21 and the data driver circuit 22 and the display unit 33 so as to have an overlapping region with each other, the area of the frame, which is the region where the display unit 33 is not provided, can be reduced. Therefore, the display device 10 can be made to have a narrow frame. Also, by making the display device 10 have a narrow frame, the display device 10 can be miniaturized.

[0067] Further, the gate driver circuit 21 and the data driver circuit 22 are not clearly separated and have an overlapping area. Let this area be area 23. By having area 23, the total occupied area of the gate driver circuit 21 and the data driver circuit 22 can be reduced. Thus, even when the area of the display unit 33 is small, the gate driver circuit 21 and the data driver circuit 22 can be provided without protruding from the display unit 33. Or, the area of the region of the gate driver circuit 21 and the data driver circuit 22 that does not overlap with the display unit 33 can be reduced. From the above, the display device 10 can be made to have a narrower bezel and be made smaller than in the case where it does not have area 23.

[0068] Here, by configuring the display device 10 to have the demultiplexer circuit 81, the data driver circuit 22 does not need to generate all of the image data supplied to the pixels 34 in, for example, the first column to the nth column at the same time. For example, consider a case where the demultiplexer circuit 81 has a first output terminal and a second output terminal as output terminals, the odd-numbered column wirings 32 are electrically connected to the first output terminal, and the even-numbered column wirings 32 are electrically connected to the second output terminal. In this case, the data driver circuit 22 may generate the image data to be supplied to the pixels 34 in the odd-numbered columns and then generate the image data to be supplied to the pixels 34 in the even-numbered columns. From the above, since the amount of data generated by the data driver circuit 22 at one time can be reduced, the configuration of the data driver circuit 22 can be made simple. Specifically, for example, the number of elements such as transistors included in the data driver circuit 22 can be reduced. Thereby, the occupied area of the data driver circuit 22 can be reduced. Therefore, even when the area of the display unit 33 is small, it is possible to suppress the data driver circuit 22 from protruding from the display unit 33. Or, the area of the region of the data driver circuit 22 that does not overlap with the display unit 33 can be reduced. From the above, the display device 10 can be made to have a narrower bezel and be made smaller.

[0069] Further, the demultiplexer circuit 81 is provided in a layer different from both the layer where the data driver circuit 22 is provided and the layer where the display unit 33 is provided. Thereby, while increasing the degree of freedom of layout, the demultiplexer circuit 81 can be provided so as to have an area overlapping with the display unit 33. For example, the demultiplexer circuit 81 can be provided so as to have an area overlapping with the pixel 34. For this reason, for example, compared with the case where the demultiplexer circuit 81 is provided in the layer 20 where the data driver circuit 22 is provided, the display device 10 can be made to have a narrower bezel and can also be made smaller. From the viewpoint of suppressing signal delay due to the resistance of the wiring 82 and the resistance of the wiring 32, it is preferable that the lengths of the wiring 82 and the wiring 32 are as short as possible. For this reason, the demultiplexer circuit 81 is preferably provided so as to have an area overlapping with the data driver circuit 22.

[0070] The circuit 40 can be provided so as not to overlap with the display unit 33. Note that the circuit 40 may be provided so as to have an area overlapping with the display unit 33.

[0071] Further, the gate driver circuit 21 and / or the circuit 40 may be provided in the layer 80. When the gate driver circuit 21 is provided in the layer 80, the gate driver circuit 21 and the demultiplexer circuit 81 may be configured to have an overlapping area without being clearly separated.

[0072] <Configuration example of circuit 40 and data driver circuit 22> FIG. 3 is a block diagram showing a configuration example of the circuit 40 and the data driver circuit 22. Note that in FIG. 3, as shown in FIGS. 1A and 2, the case where the demultiplexer circuit 81 has two output terminals and the display device 10 has n / 2 demultiplexer circuits 81 is shown.

[0073] The circuit 40 includes a receiving circuit 41, a serial-parallel conversion circuit 42, and a potential generation circuit 46a. In addition to the above circuits, the circuit 40 can be provided with various other circuits. For example, a control circuit having a function of generating a start pulse signal, a clock signal, etc. can be provided in the circuit 40.

[0074] The data driver circuit 22 includes a buffer circuit 43, a shift register circuit 44, a latch circuit 45, a pass transistor logic circuit 46b, and an amplifier circuit 47. Here, the latch circuit 45, the pass transistor logic circuit 46b, and the amplifier circuit 47 can be provided in the same number as the demultiplexer circuit 81. In FIG. 3, a case where the data driver circuit 22 has one shift register circuit 44 and n / 2 each of the latch circuit 45, the pass transistor logic circuit 46b, and the amplifier circuit 47 is shown. In this specification and the like, for example, n / 2 latch circuits 45, pass transistor logic circuits 46b, and amplifier circuits 47 are described as latch circuits 45[1] to latch circuits 45[n / 2], pass transistor logic circuits 46b[1] to pass transistor logic circuits 46b[n / 2], and amplifier circuits 47[1] to amplifier circuits 47[n / 2], respectively, for distinction. Here, for example, when the data driver circuit 22 has n / 2 pass transistor logic circuits 46b, the potential generation circuit 46a and the pass transistor logic circuits 46b[1] to pass transistor logic circuits 46b[n / 2] constitute a D / A (Digital to Analog) conversion circuit 46.

[0075] The receiving circuit 41 has a function of receiving data that serves as the basis for the image data generated by the data driver circuit 22. The data can be single-ended digital data. When the receiving circuit 41 receives data using a data transmission signal such as LVDS (Low Voltage Differential Signaling), it may have a function of converting it into a signal standard that can be processed internally.

[0076] The serial-parallel conversion circuit 42 has a function of converting the single-ended data output from the reception circuit 41 into parallel data. By providing the serial-parallel conversion circuit 42 in the circuit 40, even if the load during the transmission of data or the like from the circuit 40 to the data driver circuit 22 or the like is large, the data or the like can be transmitted from the circuit 40 to the data driver circuit 22 or the like.

[0077] The buffer circuit 43 can be, for example, a unity-gain buffer. The buffer circuit 43 has a function of outputting the same data as the data output from the serial-parallel conversion circuit 42. By providing the buffer circuit 43 in the data driver circuit 22, even if the potential corresponding to the data output from the serial-parallel conversion circuit 42 decreases due to wiring resistance or the like when being transmitted from the circuit 40 to the data driver circuit 22, the decreased amount can be recovered. Thereby, even if the load during the transmission of data or the like from the circuit 40 to the data driver circuit 22 or the like is large, the decrease in the driving ability of the data driver circuit 22 or the like can be suppressed.

[0078] The shift register circuit 44 has a function of generating a signal for controlling the operation of the latch circuit 45. The latch circuit 45 has a function of holding or outputting the data output from the buffer circuit 43. In the latch circuit 45, which operation of holding or outputting the data is performed is selected based on the signal supplied from the shift register circuit 44.

[0079] The D / A conversion circuit 46 has a function of converting the digital data output from the latch circuit 45 into analog image data. The potential generation circuit 46a has a function of generating a type of potential corresponding to the number of bits of the data that can be D / A-converted and supplying it to the pass transistor logic circuit 46b. For example, when the D / A conversion circuit 46 has a function of converting 8-bit digital data into analog image data, the potential generation circuit 46a can generate 256 types of potentials having different magnitudes from each other.

[0080] The pass transistor logic circuit 46b receives data from the latch circuit 45 and has a function of outputting, as an analog signal, any of the potentials generated by the potential generation circuit 46a based on the digital value of the received data. For example, the larger the digital value of the data, the larger the potential output by the pass transistor logic circuit 46b can be.

[0081] As shown in FIG. 3, in the display device 10, the circuits constituting the D / A conversion circuit 46 can be provided in a distributed manner in the data driver circuit 22 and the circuit 40. Specifically, a circuit such as the pass transistor logic circuit 46b, which is preferably provided for each data driver circuit, is provided in the data driver circuit 22, and a circuit such as the potential generation circuit 46a, which does not necessarily need to be provided for each data driver circuit, is provided in the circuit 40. Thereby, for example, the number of potential generation circuits 46a included in the display device 10 can be made smaller than the number of pass transistor logic circuits 46b. Therefore, the occupied area of the data driver circuit 22 can be reduced. Accordingly, even when the area of the display unit 33 is small, it is possible to suppress the data driver circuit 22 from protruding from the display unit 33. Or, the area of the region of the data driver circuit 22 that does not overlap with the display unit 33 can be reduced. From the above, the display device 10 can be made into a narrow bezel and can also be miniaturized. Here, also in circuits other than the D / A conversion circuit 46, the components of the circuit can be provided in a distributed manner in the data driver circuit 22 and the circuit 40.

[0082] The amplifier circuit 47 has a function of amplifying the analog signal output by the pass transistor logic circuit 46b and outputting it to the wiring 82. By providing the amplifier circuit 47, the image data represented by the analog signal can be stably supplied to the demultiplexer circuit 81. As the amplifier circuit 47, a voltage follower circuit having an operational amplifier or the like can be applied. When a circuit having a differential input circuit is used as the amplifier circuit, it is preferable that the offset voltage of the differential input circuit be as close to 0V as possible.

[0083] When the display device 10 does not have the demultiplexer circuit 81, the data driver circuit 22 needs to have, for example, n latch circuits 45, n pass transistor logic circuits 46b, and n amplifier circuits 47 respectively. On the other hand, when the display device 10 has the demultiplexer circuit 81, as shown in FIG. 3, the data driver circuit 22 can have, for example, n / 2 latch circuits 45, n / 2 pass transistor logic circuits 46b, and n / 2 amplifier circuits 47 respectively. As described above, the number of the latch circuit 45, the pass transistor logic circuit 46b, and the amplifier circuit 47 included in the data driver circuit 22 can be reduced. Specifically, the number of the latch circuit 45, the pass transistor logic circuit 46b, and the amplifier circuit 47 included in the data driver circuit 22 can be made less than the number n of the columns of the pixels 34. Thereby, for example, the number of elements such as transistors included in the data driver circuit 22 can be reduced, so that the occupied area of the data driver circuit 22 can be reduced. Therefore, even when the area of the display unit 33 is small, it is possible to suppress the data driver circuit 22 from protruding from the display unit 33. Or, the area of the region where the data driver circuit 22 does not overlap with the display unit 33 can be reduced. From the above, the display device 10 can be made into a narrow bezel and can also be miniaturized.

[0084] Here, FIG. 3 shows the case where the demultiplexer circuit 81 has two output terminals. When the demultiplexer circuit 81 has three or more output terminals, the number of the latch circuit 45, the pass transistor logic circuit 46b, and the amplifier circuit 47 included in the data driver circuit 22 can be further reduced. Thereby, the occupied area of the data driver circuit 22 can be further reduced.

[0085] <Configuration example of pixel 34> FIG. 4A and FIG. 4B are circuit diagrams showing a configuration example of the pixel 34. The pixel 34 having the configuration shown in FIG. 4A includes a liquid crystal element 570, a transistor 550, and a capacitor element 560. Note that in the pixel 34 having the configuration shown in FIG. 4A, if the capacitance of the liquid crystal element 570 or the like is sufficiently large, the capacitor element 560 may not be provided.

[0086] One of the source or drain of the transistor 550 is electrically connected to one electrode of the liquid crystal element 570. One electrode of the liquid crystal element 570 is electrically connected to one electrode of the capacitor element 560. The other of the source or drain of the transistor 550 is electrically connected to the wiring 32. The gate of the transistor 550 is electrically connected to the wiring 31. The other electrode of the capacitor element 560 is electrically connected to the wiring 35. Note that a node where one of the source or drain of the transistor 550, one electrode of the liquid crystal element 570, and one electrode of the capacitor element 560 are electrically connected is defined as a node FD.

[0087] The potential of the other electrode of the liquid crystal element 570 is appropriately set according to the specification of the pixel 34. The liquid crystal element 570 has its alignment state set by the image data written to the pixel 34. Note that a common potential (common potential) may be supplied to the other electrodes of the liquid crystal elements 570 included in each of the plurality of pixels 34. Alternatively, different potentials may be supplied to the other electrodes of the liquid crystal elements 570 of the pixels 34 in each row.

[0088] The pixel 34 having the configuration shown in FIG. 4B includes a transistor 552, a transistor 554, a capacitor element 562, and a light-emitting element 572. Note that if the gate capacitance or the like of the transistor 554 is sufficiently large, the capacitor element 562 may not be provided.

[0089] One of the source or drain of transistor 552 is electrically connected to the gate of transistor 554. The gate of transistor 554 is electrically connected to one electrode of capacitor element 562. One of the source or drain of transistor 554 is electrically connected to one electrode of light-emitting element 572. The other of the source or drain of transistor 552 is electrically connected to wiring 32. The gate of transistor 552 is electrically connected to wiring 31. The other of the source or drain of transistor 554 and the other electrode of capacitor element 562 are electrically connected to wiring 35a. The other electrode of light-emitting element 572 is electrically connected to wiring 35b. Here, a node where one of the source or drain of transistor 552, the gate of transistor 554, and one electrode of capacitor element 562 are electrically connected is defined as node FD.

[0090] In pixel 34 having the configuration shown in FIG. 4B, for example, a low potential can be supplied to wiring 35a and a high potential can be supplied to wiring 35b.

[0091] In pixel 34 having the configuration shown in FIG. 4B, according to the potential of node FD, the current flowing through light-emitting element 572 is controlled, whereby the emission luminance from light-emitting element 572 is controlled.

[0092] As the light-emitting element 572, for example, an EL element utilizing electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (hereinafter also referred to as an EL layer) between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting substance contained in the EL layer emits light.

[0093] Also, EL elements are distinguished according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0094] In an organic EL element, when a voltage is applied, electrons are injected into the EL layer from one electrode and holes are injected into the EL layer from the other electrode. Then, when these carriers (electrons and holes) recombine, a light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Based on such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0095] In this specification and the like, the voltage supplied to a display element such as a light-emitting element or a liquid crystal element indicates the difference between the potential applied to one electrode of the display element and the potential applied to the other electrode of the display element.

[0096] Note that in addition to the light-emitting compound, the EL layer may contain a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property).

[0097] The EL layer can be formed by methods such as vapor deposition method (including vacuum vapor deposition method), transfer method, printing method, inkjet method, coating method, etc.

[0098] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their device configurations. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission using donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission using inner-shell electron transitions of metal ions.

[0099] For the light-emitting element, at least one of the pair of electrodes may be transparent in order to extract light emission. Then, a transistor and a light-emitting element are formed on a substrate, and there are a top emission structure for extracting light emission from the surface on the side opposite to the substrate, a bottom emission structure for extracting light emission from the surface on the substrate side, and a dual emission structure for extracting light emission from both surfaces. Any of these light-emitting elements with different emission structures can be applied.

[0100] A modification of the pixel 34 having the configuration shown in FIG. 4B is shown in FIG. 4C. In the pixel 34 having the configuration shown in FIG. 4C, one of the source or drain of the transistor 554 is electrically connected to the other electrode of the capacitor element 562 in addition to one electrode of the light-emitting element 572. On the other hand, the wiring 35a can be configured not to be electrically connected to the other electrode of the capacitor element 562. In the pixel 34 having the configuration shown in FIG. 4C, for example, a high potential can be supplied to the wiring 35a, and a low potential can be supplied to the wiring 35b.

[0101] <An example of the operation method of the display device 10> FIG. 5 is a timing chart for explaining an example of the operation method of the display device 10 having the pixel 34 with the configuration shown in FIGS. 4A to 4C. In the timing chart shown in FIG. 5, for example, when the demultiplexer circuit 81 has two output terminals and the display device 10 has n / 2 demultiplexer circuits 81, an example of the operation method of the display device 10 is shown. In FIG. 5, an example of the operation method of the pixel 34[i,j-1] and the pixel 34[i,j] (i is an integer from 1 to m, and j is an even number from 2 to n) is shown. Specifically, it shows the change over time of the potential of the wiring 31[i], the potential of the wiring 83[j / 2], the potential of the wiring 82[j / 2], the potential of the wiring 32[j-1], the potential of the wiring 32[j], the potential of the node FD[j-1], and the potential of the node FD[j]. Here, the node FD[j-1] indicates the node FD of the pixel 34 in the (j-1)-th column, and the node FD[j] indicates the node FD of the pixel 34 in the j-th column.

[0102] In the timing chart shown in FIG. 5, the operations performed by the data driver circuit 22 to generate image data and display an image corresponding to the image data on the display unit 33 are shown. Specifically, it shows the operation of supplying an analog signal of a potential corresponding to the data D[i, j - 1] to the pixel 34[i, j - 1] and supplying an analog signal of a potential corresponding to the data D[i, j] to the pixel 34[i, j]. Also, the selection control signal input from the wiring 83 to the demultiplexer circuit 81 is set as a 1-bit digital signal. And when the potential of the wiring 83[j / 2] is at a high potential, the demultiplexer circuit 81[j / 2] is assumed to output the above analog signal input from the input terminal to the wiring 32[j - 1]. On the other hand, when the potential of the wiring 83[j / 2] is at a low potential, the demultiplexer circuit 81[j / 2] is assumed to output the above analog signal input from the input terminal to the wiring 32[j].

[0103] In the timing chart shown in FIG. 5, the high potential is indicated by "H" and the low potential is indicated by "L". Also, for ease of explanation, the effects of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, and threshold voltages of transistors are not considered.

[0104] During the period T1, the potential of the wiring 83[j / 2] is set to a high potential, and the potential of the wiring 82[j / 2] is set to the potential corresponding to the data D[i, j - 1]. Thereby, the potential of the wiring 32[j - 1] becomes the potential corresponding to the data D[i, j - 1]. Also, by setting the potential of the wiring 31[i] to a high potential, the wiring 32[j - 1] and the node FD[i, j - 1] are made conductive. As described above, the potential of the node FD[j - 1] becomes the potential corresponding to the data D[i, j - 1], and the data D[i, j - 1] is written into the pixel 34[i, j - 1].

[0105] During period T2, the potential of wiring 83[j / 2] is set to a low potential, and the potential of wiring 82[j / 2] is set to the potential corresponding to data D[i,j]. As a result, the potential of wiring 32[j] becomes the potential corresponding to data D[i,j]. Also, by setting the potential of wiring 31[i] to a high potential, wiring 32[j] and node FD[i,j] are made conductive. Thus, the potential of node FD[j] becomes the potential corresponding to data D[i,j], and data D[i,j] is written into pixel 34[i,j]. The operations described above are performed for all pixels 34, for example, in display device 10. Thereby, an image can be displayed on display unit 33.

[0106] <Configuration Example 2 of Display Device 10> FIG. 6 is a diagram showing a configuration example of display device 10. The display device 10 having the configuration shown in FIG. 6 differs from the display device 10 having the configuration shown in FIG. 2 in that a plurality of display units 33 are provided in layer 30, that is, the display units provided in layer 30 are divided. In FIG. 6, a configuration example of display device 10 is shown when three rows and three columns of display units 33 are provided in layer 30. Note that in layer 30, two rows and two columns of display units 33 may be provided, or four rows and four columns or more of display units 33 may be provided. Also, the number of rows and columns of display units 33 provided in layer 30 may be different. In the display device 10 having the configuration shown in FIG. 6, for example, a single image can be displayed using all display units 33.

[0107] In FIG. 6, for clarity of the figure, wirings 31, 32, 82, and 83 are omitted, but actually, wirings 31, 32, 82, and 83 are provided in display device 10 having the configuration shown in FIG. 6. Also, the electrical connection relationship of circuit 40 is omitted, but actually, it is electrically connected to data driver circuit 22. Note that in other figures as well, some components etc. may be omitted in the same manner as in FIG. 6.

[0108] In layer 20, the same number of gate driver circuits 21 and data driver circuits 22 as, for example, the number of display units 33 can be provided. In this case, the gate driver circuit 21 can be provided so as to overlap with the display unit 33 where the pixels 34 to which the gate driver circuit 21 supplies signals are provided. Also, the data driver circuit 22 can be provided so as to overlap with the display unit 33 where the pixels 34 to which the data driver circuit 22 supplies image data are provided.

[0109] By providing a plurality of display units 33 and providing the gate driver circuit 21 and the data driver circuit 22 accordingly, the number of pixels 34 provided in one display unit 33 can be reduced. The plurality of provided gate driver circuits 21 can each be operated in parallel, and the plurality of provided data driver circuits 22 can each be operated in parallel. Therefore, for example, the time required to write image data corresponding to one frame of an image to the pixels 34 can be shortened. Thus, the length of one frame period can be shortened, and the operation of the display device 10 can be speeded up. For this reason, the number of pixels 34 included in the display device 10 can be increased, and the definition of the image displayed by the display device 10 can be enhanced. Also, the resolution of the image that can be displayed by the display device according to one aspect of the present invention can be made higher than the resolution of the image that can be displayed by a display device having a configuration in which the gate driver circuit and the data driver circuit do not overlap with the display unit. Furthermore, since the clock frequency can be reduced, the power consumption of the display device 10 can be reduced.

[0110] Here, when the gate driver circuit and the data driver circuit are configured not to overlap with the display unit, the gate driver circuit and the data driver circuit are provided, for example, on the outer peripheral portion of the display unit. In this case, it is difficult to provide more display units than two rows and two columns from the viewpoint of the installation location of the data driver circuit and the like. On the other hand, in the display device 10, the gate driver circuit and the data driver circuit can be provided in a layer different from the layer where the display unit is provided, so that they can be provided to have an area overlapping with the display unit. Therefore, as shown in FIG. 6, more display units than two rows and two columns can be provided. That is, five or more gate driver circuits and data driver circuits can be provided in the display device 10, respectively.

[0111] From the above, the display device 10 can be operated, for example, at a higher speed than a display device having a configuration in which the gate driver circuit and the data driver circuit do not overlap with the display unit. Therefore, the pixel density of the display device 10 can be increased compared to a display device having a configuration in which the gate driver circuit and the data driver circuit do not overlap with the display unit. For example, the pixel density of the display device 10 can be 1000 ppi or more, 2000 ppi or more, and 5000 ppi or more. Thereby, a high-definition image can be displayed on the display device 10. Therefore, a high-quality image with less graininess can be displayed on the display device 10, and an image with a high sense of presence can be displayed. Therefore, the display device 10 is particularly suitable for use in devices where the distance between the display surface and the user is close, particularly portable electronic devices, wearable electronic devices (wearable devices), and electronic book terminals. It can also be suitably used for VR devices, AR devices, and the like. Furthermore, it can also be suitably used for viewfinders such as electronic viewfinders provided in digital cameras and other electronic devices having an imaging device.

[0112] In addition, the resolution of the image that can be displayed by the display device 10 can be increased compared to the resolution of the image that can be displayed by a display device configured such that the gate driver circuit and the data driver circuit do not overlap with the display unit. For example, when the display device 10 is used as a viewfinder, the display device 10 can display an image with a resolution of 4K, 5K, or higher.

[0113] Here, when the pixel density of the display device 10 is increased, transistors and the like provided in the drive circuit such as the data driver circuit 22 also need to be provided with high-density integration. However, due to reasons such as the limit of high-density integration, the occupied area of the data driver circuit 22 may be larger than the area of the display unit 33. As a result, the data driver circuit 22 may protrude from the display unit 33. Or, the area of the region where the data driver circuit 22 does not overlap with the display unit 33 may increase. Therefore, the frame may become larger.

[0114] On the other hand, by providing the demultiplexer circuit 81 in the display device 10, the number of elements such as transistors included in the data driver circuit 22 can be reduced as described above, so that the occupied area of the data driver circuit 22 can be reduced. Therefore, even when the pixel density of the display device 10 is high, it is possible to suppress the data driver circuit 22 from protruding from the display unit 33. Or, the area of the region where the data driver circuit 22 does not overlap with the display unit 33 can be reduced. From the above, the display device 10 can be made to have a narrow frame and can also be miniaturized.

[0115] Note that even in a configuration in which a plurality of data driver circuits 22 and the like are provided in the layer 20 and a plurality of display units 33 are provided in the layer 30, the number of circuits 40 provided in the display device 10 can be set to 1, similar to the case shown in FIG. 2. Therefore, as shown in FIG. 6, the circuit 40 can be provided so as not to overlap any of the display units 33. Note that the circuit 40 may be provided so as to have a region overlapping with any one of the display units 33.

[0116] 6 shows a configuration example in which the number of gate driver circuits 21 is the same as the number of display units 33, but one embodiment of the present invention is not limited to this. Fig. 7 is a modified example of the configuration shown in Fig. 6, and shows a configuration example of the display device 10 in which the number of gate driver circuits 21 is the same as the number of columns of the display unit 33. In the display device 10 shown in Fig. 7, three columns of display units 33 are provided, and therefore three gate driver circuits 21 are provided. In addition, three rows of display units 33 are provided, and one gate driver circuit 21 is shared by the display units 33 in three rows and one column.

[0117] Fig. 8 is a modified example of the configuration shown in Fig. 6, and shows a configuration example of the display device 10 in which a plurality of display units 33 are provided and one gate driver circuit 21 is provided. In the display device 10 configured as shown in Fig. 8, three rows and three columns of display units 33 share one gate driver circuit 21. Note that in the display device 10 configured as shown in Fig. 8, the gate driver circuit 21 can be configured not to overlap the display unit 33.

[0118] Although not shown, the data driver circuits 22 do not have to be configured to be provided in the same number as the display units 33. The number of data driver circuits 22 included in the display device 10 may be more or less than the number of display units 33 provided in the display device 10.

[0119] 2 shows a configuration example in which the circuit 40 is provided on the layer 20, but the circuit 40 does not have to be provided on the layer 20. FIG. 9 shows a modified example of the configuration shown in FIG. 2, showing a configuration example of the display device 10 in which the circuit 40 is provided on the layer 30. The circuit 40 may also be provided on the layer 80. Note that the elements constituting the circuit 40 may be distributed across two or three of the layers 20, 80, and 30.

[0120] FIG. 2 shows a configuration example in which one display unit 33 and one data driver circuit are provided, but more data driver circuits 22 may be provided than the display unit 33. FIG. 10 is a modification of the configuration shown in FIG. 2, and shows a configuration example of the display device 10 when two data driver circuits (data driver circuit 22a and data driver circuit 22b) are provided for one display unit 33.

[0121] In the display device 10 having the configuration shown in FIG. 10, the input terminals of the odd-numbered demultiplexer circuits 81 (demultiplexer circuit 81[1], demultiplexer circuit 81[3], etc.) are electrically connected to the data driver circuit 22a, and the input terminals of the even-numbered demultiplexer circuits 81 (demultiplexer circuit 81[2], demultiplexer circuit 81[4], etc.) are electrically connected to the data driver circuit 22b. Note that in FIG. 10, n / 2 is assumed to be an even number.

[0122] The data driver circuit 22a has a function of generating image data representing an image to be displayed using the pixel 34 that is electrically connected to the output terminal of the odd-numbered demultiplexer circuit 81. The data driver circuit 22b has a function of generating image data representing an image to be displayed using the pixel 34 that is electrically connected to the output terminal of the even-numbered demultiplexer circuit 81. Note that the image data generated by the data driver circuit 22a and the image data generated by the data driver circuit 22b can represent one image.

[0123] The data driver circuit 22a and the data driver circuit 22b have a region overlapping with the display unit 33, similar to the data driver circuit 22. For example, the data driver circuit 22a and the data driver circuit 22b have a region overlapping with the pixel 34, similar to the data driver circuit 22. Further, the data driver circuit 22a is not clearly separated from the gate driver circuit 21 and has a region 23a that is an overlapping region. Furthermore, the data driver circuit 22b is not clearly separated from the gate driver circuit 21 and has a region 23b that is an overlapping region.

[0124] As shown in FIG. 10, by providing more data driver circuits than the display unit 33, the density of transistors and the like constituting the data driver circuits can be reduced. Thereby, the degree of freedom in the layout of the display device 10 can be increased.

[0125] Note that the configurations of the data driver circuit 22a and the data driver circuit 22b can be the same as the data driver circuit 22 shown in FIG. 3.

[0126] FIG. 2 shows a configuration example in which one display unit 33 and one gate driver circuit are provided, but more gate driver circuits may be provided than the display unit 33. FIG. 11 is a modified example of the configuration shown in FIG. 2, and shows a configuration example of the display device 10 when two gate driver circuits (gate driver circuit 21a, gate driver circuit 21b) are provided for one display unit 33.

[0127] In the display device 10 having the configuration shown in FIG. 11, the pixels 34 in the odd rows are electrically connected to the gate driver circuit 21a via the wiring 31a, and the pixels 34 in the even rows are electrically connected to the gate driver circuit 21b via the wiring 31b. The wiring 31a and the wiring 31b have the function of a scanning line in the same manner as the wiring 31.

[0128] The gate driver circuit 21a has a function of generating a signal for controlling the operation of the pixels 34 in the odd rows and supplying the signal to the pixels 34 via the wiring 31a. The gate driver circuit 21b has a function of generating a signal for controlling the operation of the pixels 34 in the even rows and supplying the signal to the pixels 34 via the wiring 31b.

[0129] The gate driver circuits 21a and 21b have regions overlapping with the display unit 33, similar to the gate driver circuit 21. For example, the gate driver circuits 21a and 21b have regions overlapping with the pixels 34, similar to the gate driver circuit 21. Also, the gate driver circuit 21a is not clearly separated from the data driver circuit 22 and has a region 23c which is an overlapping region. Further, the gate driver circuit 21b is not clearly separated from the data driver circuit 22 and has a region 23d which is an overlapping region.

[0130] As shown in FIG. 11, by providing more gate driver circuits than the display unit 33, the density of transistors and the like constituting the gate driver circuits can be reduced. Thereby, the degree of freedom in the layout of the display device 10 can be increased.

[0131] Also, in the display device 10 having the configuration shown in FIG. 11, after operating the gate driver circuit 21a to write image data to all the pixels 34 in the odd-numbered rows, the gate driver circuit 21b can be operated to write image data to all the pixels 34 in the even-numbered rows. That is, the display device 10 having the configuration shown in FIG. 11 can be operated in an interlace method. By operating in the interlace method, the operation of the display device 10 can be speeded up and the frame frequency can be increased. Also, the number of pixels 34 to which image data is written in one frame period can be made half of that when the display device 10 is operated in the progressive method. Therefore, when the display device 10 is operated in the interlace method, the clock frequency can be made smaller than when it is operated in the progressive method, so that the power consumption of the display device 10 can be reduced.

[0132] FIG. 2 shows a configuration in which only one end of the wiring 32 is connected to the output terminal of the demultiplexer circuit 81, but a plurality of locations on the wiring 32 may be connected to the output terminals of the demultiplexer circuit. By connecting a plurality of locations on the wiring 32 to the data driver circuit 22, the wiring distance from the output terminal of the demultiplexer circuit to the pixel 34 can be shortened. As a result, signal delay and the like caused by wiring resistance, parasitic capacitance, etc. can be suppressed, so that the operation of the display device 10 can be speeded up. FIG. 12 shows a configuration example of the display device 10 when both ends of the wiring 32 are connected to the output terminals of the demultiplexer circuit.

[0133] In FIG. 12, the demultiplexer circuit connected to one end of the wiring 32 is designated as the demultiplexer circuit 81a, and the demultiplexer circuit connected to the other end of the wiring 32 is designated as the demultiplexer circuit 81b. Also, the input terminal of the demultiplexer circuit 81a is electrically connected to the wiring 82a, and the input terminal of the demultiplexer circuit 81b is electrically connected to the wiring 82b. Further, the selection control signal input terminal of the demultiplexer circuit 81a is electrically connected to the wiring 83a, and the selection control signal input terminal of the demultiplexer circuit 81b is electrically connected to the wiring 83b.

[0134] Note that not only one end and the other end of the wiring 32 but also other portions of the wiring 32 may be connected to the output terminals of the demultiplexer circuit. For example, the central portion of the wiring 32 may be connected to the output terminal of the demultiplexer circuit. By increasing the connection points between the wiring 32 and the output terminals of the demultiplexer circuit, signal delay and the like can be further suppressed, and the operation of the display device 10 can be further speeded up. Note that, for example, one end of the wiring 32 and the central portion of the wiring 32 may be connected to the output terminals of the demultiplexer circuit, and the other end of the wiring 32 may not be connected to the output terminal of the demultiplexer circuit.

[0135] Note that a plurality of locations on the wiring 31 may be connected to one gate driver circuit 21. Also by this, signal delay and the like can be suppressed, and the operation of the display device 10 can be speeded up.

[0136] <Configuration example of D / A conversion circuit 46> FIG. 13 is a circuit diagram showing a configuration example of a potential generation circuit 46a and a pass transistor logic circuit 46b that constitute the D / A conversion circuit 46. The D / A conversion circuit 46 having the configuration shown in FIG. 13 can convert 8-bit digital data DD into analog image data IS. As shown in FIG. 3, the data driver circuit 22 can have a plurality of pass transistor logic circuits 46b, but in FIG. 13, one pass transistor logic circuit 46b is shown for convenience of explanation.

[0137] Here, for example, when the digital data DD is 8-bit digital data, it can be said that the digital data DD is composed of 8-digit digital values DV. In this specification and the like, for example, 8-digit digital values DV are described and shown in order from the smallest digit as digital values DV<1> to digital values DV<8>. That is, for example, digital values DV<1> to digital values DV<8> each indicate a 1-bit value (for example, 0 or 1).

[0138] The potential generation circuit 46a having the configuration shown in FIG. 13 has resistor elements 48[1] to resistor element 48

[0256] , and these are connected in series. That is, the D / A conversion circuit 46 can be a resistor string type D / A conversion circuit.

[0139] One terminal of the resistor element 48[1] can be supplied with a potential VDD. One terminal of the resistor element 48

[0256] can be supplied with a potential VSS. Thereby, potentials V1 to V of different magnitudes can be output from each terminal of the resistor elements 48[1] to resistor element 48

[0256] . Note that FIG. 13 shows a configuration example of the potential generation circuit 46a when the potential V1 is the potential VDD, but the potential V 256 can also be set to the potential VSS. Also, the resistor element 48

[0256] may not be provided, and the potential V1 may be the potential VDD and the potential V 256 may be the potential VSS. 256 ​

[0140] In this specification and the like, the potential VDD can be, for example, a high potential, and the potential VSS can be, for example, a low potential.

[0141] The pass transistor logic circuit 46b having the configuration shown in FIG. 13 is composed of eight stages of pass transistors 49. Specifically, the pass transistor logic circuit 46b is configured such that, for each stage, it branches electrically into two paths, and has a total of 256 paths. That is, it can be said that the pass transistors 49 are electrically connected in a tournament system. An analog image data IS can be output from one of the source or drain of the pass transistor 49 at the eighth stage, which is the final stage.

[0142] For example, the digital value DV<1> can be supplied to the pass transistor 49 at the first stage, the digital value DV<2> can be supplied to the pass transistor 49 at the second stage, and the digital value DV<8> can be supplied to the pass transistor 49 at the eighth stage. As described above, the potential of the image data IS can be set to any one of the potentials V1 to V 256 depending on the digital data DD. Therefore, digital image data can be converted into analog image data IS.

[0143] Note that both an n-channel type pass transistor 49 and a p-channel type pass transistor 49 are provided in the pass transistor logic circuit 46b shown in FIG. 13, but it is also possible to adopt a configuration in which only the n-channel type pass transistor 49 is provided. For example, in addition to the digital values DV<1> to DV<8>, by supplying these complementary data to the gates of the pass transistors 49, all the pass transistors 49 provided in the pass transistor logic circuit 46b can be made n-channel type transistors.

[0144] The configuration shown in FIG. 13 can also be applied to a D / A conversion circuit 46 having a function of D / A converting digital data DD with a number of bits other than 8 bits. For example, by providing 1024 or 1023 resistor elements 48 in a potential generation circuit 46a and providing 10 stages of pass transistors 49 in a pass transistor logic circuit 46b, the D / A conversion circuit 46 can have a function of D / A converting 10-bit digital data DD.

[0145] <Configuration Example of Gate Driver Circuit 21> FIG. 14 is a block diagram showing a configuration example of the gate driver circuit 21. Note that the gate driver circuit 21a and the gate driver circuit 21b shown in FIG. 11 can also have the same configuration.

[0146] The gate driver circuit 21 has a register circuit R composed of a plurality of set-reset flip-flops. The register circuit R is electrically connected to a wiring 31 having a function as a scanning line and has a function of outputting a signal to the wiring 31.

[0147] The signal RES is a reset signal, and by setting the signal RES to a high potential, for example, all outputs of the register circuit R can be set to a low potential. The signal SP is a start pulse signal, and by inputting the signal to the gate driver circuit 21, the shift operation by the register circuit R can be started. The signal PWC is a pulse width control signal and has a function of controlling the pulse width of the signal output from the register circuit R to the wiring 31. The signals CLK[1], CLK[2], CLK[3], and CLK[4] are clock signals, and for one register circuit R, for example, two of the signals CLK[1] to CLK[4] can be input.

[0148] Note that the configuration shown in FIG. 14 can also be applied to a shift register circuit 44 or the like included in the data driver circuit 22 by using another wiring as the wiring 31 electrically connected to the register circuit R or the like.

[0149] FIG. 15A is a diagram showing signals input to register circuit R and signals output from register circuit R. Here, FIG. 15A shows a case where signal CLK[1] and signal CLK[3] are input as clock signals.

[0150] Signal FO is an output signal, for example, a signal output to wiring 31. Signal SROUT is a shift signal and can be used as signal LIN input to the next-stage register circuit R. Among the signals shown in FIG. 15A above, signals RES, PWC, CLK[1], CLK[3], and LIN are signals input to register circuit R, and signals FO and SROUT are signals output from register circuit R.

[0151] FIG. 15B is a circuit diagram showing a configuration example of register circuit R where the input / output signals are the signals shown in FIG. 15A. Register circuit R includes transistors 51 to 63 and capacitor elements 64 to 66.

[0152] One of the source or drain of transistor 51 is electrically connected to one of the source or drain of transistor 52, one of the source or drain of transistor 56, and one of the source or drain of transistor 59. The gate of transistor 52 is electrically connected to one of the source or drain of transistor 53, one of the source or drain of transistor 54, one of the source or drain of transistor 55, the gate of transistor 58, the gate of transistor 61, and one electrode of capacitor element 64. The other of the source or drain of transistor 56 is electrically connected to the gate of transistor 57 and one electrode of capacitor element 65. The other of the source or drain of transistor 59 is electrically connected to the gate of transistor 60 and one electrode of capacitor element 66. One of the source or drain of transistor 60 is electrically connected to one of the source or drain of transistor 61, the gate of transistor 62, and the other electrode of capacitor element 66.

[0153] The signal LIN is input to the gates of transistor 51 and transistor 55. The signal CLK[3] is input to the gate of transistor 53. The signal RES is input to the gate of transistor 54. The signal CLK[1] is input to one of the source or drain of transistor 57. The signal PWC is input to the other of the source or drain of transistor 60.

[0154] One of the source or drain of transistor 62 and one of the source or drain of transistor 63 are electrically connected to wiring 31, and as described above, the signal FO is output from wiring 31. The signal SROUT is output from the other of the source or drain of transistor 57, one of the source or drain of transistor 58, and the other electrode of capacitor element 65.

[0155] The potential VDD is supplied to the other of the source or drain of transistor 51, the other of the source or drain of transistor 53, the other of the source or drain of transistor 54, the gate of transistor 56, the gate of transistor 59, and the other of the source or drain of transistor 62. The potential VSS is supplied to the other of the source or drain of transistor 52, the other of the source or drain of transistor 55, the other of the source or drain of transistor 58, the other of the source or drain of transistor 61, the other of the source or drain of transistor 63, and the other electrode of capacitor element 64.

[0156] Transistor 63 is a bias transistor and has a function as a constant current source. The potential Vbias, which is a bias potential, can be supplied to the gate of transistor 63.

[0157] The source follower circuit 67 is constituted by the transistor 62 and the transistor 63. The source follower circuit can have a function as a buffer circuit. Therefore, by providing the source follower circuit 67 in the register circuit R, even if signal attenuation or the like due to wiring resistance, parasitic capacitance, etc. occurs inside the register circuit R, it is possible to suppress a decrease in the potential of the signal FO caused thereby. As a result, the operation of the display device 10 can be speeded up. Note that the source follower circuit 67 may be a circuit other than the source follower circuit as long as it has a function as a buffer. For example, it may be a source ground circuit.

[0158] <Configuration example of region 23> FIG. 16 is a diagram showing a configuration example of a region 23 which is a region where the gate driver circuit 21 and the data driver circuit 22 overlap. Note that the regions 23a and 23b shown in FIG. 10 and the regions 23c and 23d shown in FIG. 11 can also have the same configuration.

[0159] As shown in FIG. 16, in the region 23, a region having elements constituting the gate driver circuit 21 and a region having elements constituting the data driver circuit 22 are provided with a certain regularity. In FIG. 16, the transistor 71 is shown as an element constituting the gate driver circuit 21, and the transistor 72 is shown as an element constituting the data driver circuit 22.

[0160] In FIG. 16, a case is shown where a region having elements constituting the gate driver circuit 21 is provided in the first row and the third row, and a region having elements constituting the data driver circuit 22 is provided in the second row and the fourth row. In the region 23, dummy elements are provided between the regions having elements constituting the gate driver circuit 21. Also, dummy elements are provided between the regions having elements constituting the data driver circuit 22. FIG. 16 shows a configuration example of the region 23 in the case where dummy transistors 73 are provided as dummy elements on the four sides of the transistor 71 and on the four sides of the transistor 72.

[0161] By providing dummy elements such as dummy transistor 73 in region 23, the dummy elements can absorb impurities, and it is possible to suppress the diffusion of impurities into transistors 71, 72, etc. As a result, the reliability of transistors 71, 72, etc. can be improved, and thus the reliability of display device 10 can be improved. In FIG. 16, transistors 71, 72, and dummy transistor 73 are arranged in a matrix, but they do not have to be arranged in a matrix.

[0162] FIG. 17 is a top view showing a configuration example of region 70 which is a part of region 23. As shown in FIGS. 16 and 17, region 70 is provided with one transistor 71, one transistor 72, and two dummy transistors 73. As shown in FIG. 17, transistor 71 has a channel formation region 110, a source region 111, and a drain region 112. Further, it has a gate electrode 113 so as to have a region overlapping with channel formation region 110.

[0163] Note that in FIG. 17, components such as a gate insulator are omitted. Also, in FIG. 17, the channel formation region, the source region, and the drain region are not clearly separated and described.

[0164] An opening 114 is provided in source region 111, and source region 111 is electrically connected to wiring 115 through opening 114. An opening 116 is provided in drain region 112, and drain region 112 is electrically connected to wiring 117 through opening 116.

[0165] The gate electrode 113 is provided with an opening 118, and through the opening 118, the gate electrode 113 is electrically connected to the wiring 121. The wiring 115 is provided with an opening 119, and through the opening 119, the wiring 115 is electrically connected to the wiring 122. The wiring 117 is provided with an opening 120, and through the opening 120, the wiring 117 is electrically connected to the wiring 123. That is, the source region 111 is electrically connected to the wiring 122 through the wiring 115, and the drain region 112 is electrically connected to the wiring 123 through the wiring 117.

[0166] The transistor 72 has a channel formation region 130, a source region 131, and a drain region 132. Further, it has a gate electrode 133 so as to have a region overlapping with the channel formation region 130.

[0167] The source region 131 is provided with an opening 134, and through the opening 134, the source region 131 is electrically connected to the wiring 135. The drain region 132 is provided with an opening 136, and through the opening 136, the drain region 132 is electrically connected to the wiring 137.

[0168] The gate electrode 133 is provided with an opening 138, and through the opening 138, the gate electrode 133 is electrically connected to the wiring 141. The wiring 135 is provided with an opening 139, and through the opening 139, the wiring 135 is electrically connected to the wiring 142. The wiring 137 is provided with an opening 140, and through the opening 140, the wiring 137 is electrically connected to the wiring 143. That is, the source region 131 is electrically connected to the wiring 142 through the wiring 135, and the drain region 132 is electrically connected to the wiring 143 through the wiring 137.

[0169] Note that the channel formation region 110 and the channel formation region 130 can be provided in the same layer as each other. Also, the source region 111 and the drain region 112, and the source region 131 and the drain region 132 can be provided in the same layer as each other. Also, the gate electrode 113 and the gate electrode 133 can be provided in the same layer as each other. Also, the wiring 115 and the wiring 117, and the wiring 135 and the wiring 137 can be provided in the same layer as each other. That is, the transistor 71 and the transistor 72 can be provided in the same layer as each other. Thereby, the manufacturing process of the display device 10 can be simplified and the display device 10 can be made less expensive than the case where the transistor 71 and the transistor 72 are provided in different layers from each other.

[0170] The wirings 121 to 123 electrically connected to the transistor 71 constituting the gate driver circuit 21 are provided in the same layer as each other. Also, the wirings 141 to 143 electrically connected to the transistor 72 constituting the data driver circuit 22 are provided in the same layer as each other. Further, the wirings 121 to 123 are provided in a layer different from the wirings 141 to 143. As described above, it is possible to suppress the transistor 71 which is an element constituting the gate driver circuit 21 and the transistor 72 which is an element constituting the data driver circuit 22 from being electrically short-circuited. Therefore, even if the gate driver circuit 21 and the data driver circuit 22 are not clearly separated and have an overlapping region, malfunction of the gate driver circuit 21 and the data driver circuit 22 can be suppressed. Thereby, the reliability of the display device 10 can be enhanced.

[0171] In this specification and the like, the phrase "the same layer as A" means, for example, a layer having the same material formed in the same process as A.

[0172] FIG. 17 shows a configuration in which the wirings 141 to 143 are provided in a layer above the wirings 121 to 123, but the wirings 141 to 143 may be provided in a layer below the wirings 121 to 123.

[0173] In addition, FIG. 17 shows a configuration in which wirings 121 to 123 extend in the horizontal direction and wirings 141 to 143 extend in the vertical direction. However, one aspect of the present invention is not limited to this. For example, the wirings 121 to 123 may extend in the vertical direction and the wirings 141 to 143 may extend in the horizontal direction. Alternatively, both the wirings 121 to 123 and the wirings 141 to 143 may extend in the horizontal direction or in the vertical direction.

[0174] The dummy transistor 73 includes a semiconductor 151 and a conductor 152. The conductor 152 has a region overlapping with the semiconductor 151. The semiconductor 151 can be formed in the same layer as the channel formation regions of the transistors 71 and 72. Also, the conductor 152 can be formed in the same layer as the gate electrodes of the transistors 71 and 72. Note that the dummy transistor 73 may be configured not to have either the semiconductor 151 or the conductor 152.

[0175] The semiconductor 151 and the conductor 152 can be configured not to be electrically connected to other wirings or the like. A fixed potential may be supplied to the semiconductor 151 and / or the conductor 152. For example, a ground potential may be supplied.

[0176] <Cross-sectional configuration example of the display device 10> FIG. 18 is a cross-sectional view showing a configuration example of the display device 10. The display device 10 includes a substrate 701 and a substrate 705, and the substrate 701 and the substrate 705 are bonded together by a sealing material 712.

[0177] As the substrate 701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. Note that a semiconductor substrate other than the single crystal semiconductor substrate may be used as the substrate 701.

[0178] Transistors 441 and 601 are provided on a substrate 701. Transistor 441 can be a transistor provided in circuit 40. Transistor 601 can be a transistor provided in gate driver circuit 21 or data driver circuit 22. That is, transistors 441 and 601 can be provided in layer 20 shown in FIG. 1B or the like.

[0179] Transistor 441 includes a conductor 443 having a function as a gate electrode, an insulator 445 having a function as a gate insulator, and a part of substrate 701, and has a semiconductor region 447 including a channel formation region, a low-resistance region 449a having a function as one of a source region or a drain region, and a low-resistance region 449b having a function as the other of the source region or the drain region. Transistor 441 can be either p-channel type or n-channel type.

[0180] Transistor 441 is electrically separated from other transistors by an element isolation layer 403. FIG. 18 shows a case where transistor 441 and transistor 601 are electrically separated by element isolation layer 403. Element isolation layer 403 can be formed using a method such as the LOCOS (LOCal Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method.

[0181] Here, in the transistor 441 shown in FIG. 18, the semiconductor region 447 has a convex shape. Also, the side surface and the upper surface of the semiconductor region 447 are provided so as to be covered by the conductor 443 via the insulator 445. Note that in FIG. 18, the state where the conductor 443 covers the side surface of the semiconductor region 447 is not illustrated. Also, a material for adjusting the work function can be used for the conductor 443.

[0182] A transistor in which a semiconductor region such as transistor 441 has a convex shape can be called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator having a function as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Also, although FIG. 18 shows a configuration in which a part of substrate 701 is processed to form a convex portion, an SOI substrate may be processed to form a semiconductor having a convex shape.

[0183] Note that the configuration of transistor 441 shown in FIG. 18 is an example and is not limited to that configuration, and an appropriate configuration may be adopted according to the circuit configuration or the operation method of the circuit, etc. For example, transistor 441 may be a planar-type transistor.

[0184] Transistor 601 can have the same configuration as transistor 441.

[0185] On substrate 701, an element isolation layer 403, transistors 441 and 601, and insulators 405, 407, 409, and 411 are provided. A conductor 451 is embedded in insulator 405, insulator 407, insulator 409, and insulator 411. Here, the height of the upper surface of conductor 451 and the height of the upper surface of insulator 411 can be made approximately the same.

[0186] Insulators 413 and 415 are provided on conductor 451 and on insulator 411. Also, a conductor 457 is embedded in insulator 413 and in insulator 415. Conductor 457 can be provided in the same layer as wirings 121 to 123 shown in FIG. 17. Here, the height of the upper surface of conductor 457 and the height of the upper surface of insulator 415 can be made approximately the same.

[0187] Insulator 417 and insulator 419 are provided on conductor 457 and on insulator 415. Also, conductor 459 is embedded in insulator 417 and in insulator 419. Conductor 459 can be provided in the same layer as wirings 141 to 143 shown in FIG. 17. Here, the height of the upper surface of conductor 459 and the height of the upper surface of insulator 419 can be made approximately the same.

[0188] Insulator 821 and insulator 814 are provided on conductor 459 and on insulator 419. Conductor 853 is embedded in insulator 821 and in insulator 814. Here, the height of the upper surface of conductor 853 and the height of the upper surface of insulator 814 can be made approximately the same.

[0189] Insulator 816 is provided on conductor 853 and on insulator 814. Conductor 855 is embedded in insulator 816. Here, the height of the upper surface of conductor 855 and the height of the upper surface of insulator 816 can be made approximately the same.

[0190] Insulator 822, insulator 824, insulator 854, insulator 844, insulator 880, insulator 874, and insulator 881 are provided on conductor 855 and on insulator 816. Conductor 805 is embedded in insulator 822, in insulator 824, in insulator 854, in insulator 844, in insulator 880, in insulator 874, and in insulator 881. Here, the height of the upper surface of conductor 805 and the height of the upper surface of insulator 881 can be made approximately the same.

[0191] Insulator 421 and insulator 214 are provided on conductor 817 and on insulator 881. Conductor 453 is embedded in insulator 421 and in insulator 214. Here, the height of the upper surface of conductor 453 and the height of the upper surface of insulator 214 can be made approximately the same.

[0192] Insulator 216 is provided on conductor 453 and on insulator 214. Conductor 455 is embedded in insulator 216. Here, the height of the upper surface of conductor 455 and the height of the upper surface of insulator 216 can be made approximately the same.

[0193] An insulator 222, an insulator 224, an insulator 254, an insulator 244, an insulator 280, an insulator 274, and an insulator 281 are provided on the conductor 455 and on the insulator 216. A conductor 305 is embedded in the insulator 222, in the insulator 224, in the insulator 254, in the insulator 244, in the insulator 280, in the insulator 274, and in the insulator 281. Here, the height of the upper surface of the conductor 305 and the height of the upper surface of the insulator 281 can be made approximately the same.

[0194] An insulator 361 is provided on the conductor 305 and on the insulator 281. A conductor 317 and a conductor 337 are embedded in the insulator 361. Here, the height of the upper surface of the conductor 337 and the height of the upper surface of the insulator 361 can be made approximately the same.

[0195] An insulator 363 is provided on the conductor 337 and on the insulator 361. A conductor 347, a conductor 353, a conductor 355, and a conductor 357 are embedded in the insulator 363. Here, the height of the upper surface of the conductor 353, the height of the upper surface of the conductor 355, and the height of the upper surface of the conductor 357 and the height of the upper surface of the insulator 363 can be made approximately the same.

[0196] A connection electrode 760 is provided on the conductor 353, on the conductor 355, on the conductor 357, and on the insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connection electrode 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from the outside of the display device 10 by the FPC 716.

[0197] As shown in FIG. 18, the low-resistance region 449b having a function as the other of the source region or the drain region of the transistor 441 is electrically connected to the FPC 716 via the conductor 451, the conductor 457, the conductor 459, the conductor 853, the conductor 855, the conductor 805, the conductor 817, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. Here, in FIG. 18, three conductors, i.e., the conductor 353, the conductor 355, and the conductor 357, are shown as the conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, but one aspect of the present invention is not limited to this. The number of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, the contact resistance can be reduced.

[0198] A transistor 800 is provided on the insulator 814. The transistor 800 can be a transistor provided in the demultiplexer circuit 81. That is, the transistor 800 can be a transistor provided in the layer 80 shown in FIG. 1B. The transistor 800 can be an OS transistor.

[0199] Conductors 801a and 801b are embedded in the insulator 854, the insulator 844, the insulator 880, the insulator 874, and the insulator 881. The conductor 801a is electrically connected to one of the source or the drain of the transistor 800, and the conductor 801b is electrically connected to the other of the source or the drain of the transistor 800. Here, the height of the upper surfaces of the conductor 801a and the conductor 801b can be made approximately the same as the height of the upper surface of the insulator 881.

[0200] A transistor 550 is provided on the insulator 214. As described above, the transistor 550 can be a transistor provided in the pixel 34. That is, the transistor 550 can be provided in the layer 30 shown in FIG. 1B or the like. The transistor 550 can be an OS transistor. The OS transistor has a feature that the off-current is extremely low. Therefore, since the holding time of the image data can be lengthened, the frequency of the refresh operation can be reduced. Therefore, the power consumption of the display device 10 can be reduced.

[0201] In the insulator 254, the insulator 244, the insulator 280, the insulator 274, and the insulator 281, a conductor 301a and a conductor 301b are embedded. The conductor 301a is electrically connected to one of the source or drain of the transistor 550, and the conductor 301b is electrically connected to the other of the source or drain of the transistor 550. Here, the height of the upper surfaces of the conductor 301a and the conductor 301b and the height of the upper surface of the insulator 281 can be made approximately the same.

[0202] Note that an OS transistor or the like may be provided between the layer in which the transistors 441 and 601 or the like are provided and the layer in which the transistor 800 or the like is provided. Also, an OS transistor or the like may be provided between the layer in which the transistor 800 or the like is provided and the layer in which the transistor 550 or the like is provided. Further, an OS transistor or the like may be provided in a layer above the layer in which the transistor 550 or the like is provided.

[0203] In the insulator 361, a conductor 311, a conductor 313, a conductor 331, a capacitor element 560, a conductor 333, and a conductor 335 are embedded. The conductor 311 and the conductor 313 are electrically connected to the transistor 550 and have a function as wiring. The conductor 333 and the conductor 335 are electrically connected to the capacitor element 560. Here, the height of the upper surfaces of the conductor 331, the conductor 333, and the conductor 335 and the height of the upper surface of the insulator 361 can be made approximately the same.

[0204] Conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the upper surface of the conductor 351 can be made approximately the same as the height of the upper surface of the insulator 363.

[0205] Insulators 405, 407, 409, 411, 413, 415, 417, 419, 821, 814, 880, 874, 881, 421, 214, 280, 274, 281, 361, and 363 may function as an interlayer film and may also function as a planarization film that covers the underlying uneven shape. For example, the upper surface of the insulator 363 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0206] As shown in FIG. 18, the capacitor element 560 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor element 560 has a stacked structure in which the insulator 323 that functions as a dielectric is sandwiched between a pair of electrodes. Although FIG. 18 shows an example in which the capacitor element 560 is provided on the insulator 281, the capacitor element 560 may be provided on an insulator different from the insulator 281.

[0207] In FIG. 18, an example is shown in which the conductor 801a, the conductor 801b, and the conductor 805 are formed in the same layer. Also, an example is shown in which the conductor 811, the conductor 813, and the conductor 817 are formed in the same layer. Also, an example is shown in which the conductor 301a, the conductor 301b, and the conductor 305 are formed in the same layer. Also, an example is shown in which the conductor 311, the conductor 313, the conductor 317, and the lower electrode 321 are formed in the same layer. Also, an example is shown in which the conductor 331, the conductor 333, the conductor 335, and the conductor 337 are formed in the same layer. Also, an example is shown in which the conductor 341, the conductor 343, and the conductor 347 are formed in the same layer. Further, an example is shown in which the conductor 351, the conductor 353, the conductor 355, and the conductor 357 are formed in the same layer. By forming a plurality of conductors in the same layer in this way, the manufacturing process of the display device 10 can be simplified, so that the display device 10 can be made at a low cost. Note that these may be formed in different layers and may have different types of materials.

[0208] The display device 10 shown in FIG. 18 includes a liquid crystal element 570. The liquid crystal element 570 includes a conductor 772, a conductor 774, and a liquid crystal layer 776 therebetween. The conductor 774 is provided on the substrate 705 side and functions as a common electrode. Also, the conductor 772 is electrically connected to the other of the source or drain of the transistor 550 via the conductor 351, the conductor 341, the conductor 331, the conductor 313, and the conductor 301b. The conductor 772 is formed on the insulator 363 and functions as a pixel electrode.

[0209] For the conductor 772, a material that is transparent or reflective to visible light can be used. As the transparent material, for example, an oxide material containing indium, zinc, tin, or the like may be used. As the reflective material, for example, a material containing aluminum, silver, or the like may be used.

[0210] When a reflective material is used for the conductor 772, the display device 10 becomes a reflective liquid crystal display device. On the other hand, when a light-transmissive material is used for the conductor 772 and also for the substrate 701 etc., the display device 10 becomes a transmissive liquid crystal display device. When the display device 10 is a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, when the display device 10 is a transmissive liquid crystal display device, a pair of polarizing plates is provided so as to sandwich the liquid crystal element.

[0211] Although not shown in FIG. 18, it may be configured to provide an alignment film in contact with the liquid crystal layer 776. Also, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members, and light sources such as backlights and side lights can be appropriately provided.

[0212] A structure 778 is provided between the insulator 363 and the conductor 774. The structure 778 is a columnar spacer and has a function of controlling the distance (cell gap) between the substrate 701 and the substrate 705. Note that a spherical spacer may be used as the structure 778.

[0213] On the substrate 705 side, a light-shielding layer 738, a coloring layer 736, and an insulator 734 in contact with these are provided. The light-shielding layer 738 has a function of blocking light emitted from adjacent regions. Or, the light-shielding layer 738 has a function of blocking external light from reaching the transistor 550 etc. Note that the coloring layer 736 is provided so as to have a region overlapping with the liquid crystal element 570.

[0214] For the liquid crystal layer 776, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used.

[0215] In addition, as the mode of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, etc. can be used.

[0216] In addition, a scattered liquid crystal using polymer dispersed liquid crystal, polymer network liquid crystal, etc. in the liquid crystal layer 776 can also be used. At this time, it may be configured to perform black and white display without providing the color layer 736, or it may be configured to perform color display using the color layer 736.

[0217] In addition, as a driving method of the liquid crystal element, a time-division display method (also called a field sequential driving method) that performs color display based on a sequential addition color mixing method may be applied. In that case, the configuration may be such that the color layer 736 is not provided. When the time-division display method is used, for example, since it is not necessary to provide pixels that exhibit each color of R (red), G (green), and B (blue), there are advantages such as improving the aperture ratio of the pixels and enhancing the fineness.

[0218] The display device 10 having the configuration shown in FIG. 18 uses a liquid crystal element as a display element, but one aspect of the present invention is not limited to this. FIG. 19 is a modification of the display device 10 shown in FIG. 18, and is different from the display device 10 shown in FIG. 18 in that a light-emitting element is used as a display element.

[0219] The display device 10 shown in FIG. 19 has a light-emitting element 572. The light-emitting element 572 has a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 can have an organic compound as a light-emitting material. Alternatively, it can have an inorganic compound such as quantum dots. In FIG. 19, a transistor 554 is shown instead of the transistor 550, and a capacitor element 562 is shown instead of the capacitor element 560. As shown in FIG. 19, the transistor 554 can have the same configuration as the transistor 550, and the capacitor element 562 can have the same configuration as the capacitor element 560.

[0220] Examples of materials that can be used for the organic compound include fluorescent materials or phosphorescent materials, etc. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc.

[0221] In the display device 10 shown in FIG. 19, an insulator 730 is provided on the insulator 363. Here, the insulator 730 can be configured to cover a part of the conductor 772. Further, the light-emitting element 572 has a translucent conductor 788 and is a top-emission type light-emitting element. Note that the light-emitting element 572 may have a bottom-emission structure that emits light toward the conductor 772 side or a dual-emission structure that emits light toward both the conductor 772 and the conductor 788.

[0222] Although details will be described later, the light-emitting element 572 can have a microcavity structure. Thereby, light of a predetermined color (for example, RGB) can be extracted without providing a coloring layer, and the display device 10 can perform color display. By adopting a configuration without providing a coloring layer, absorption of light by the coloring layer can be suppressed. Thereby, the display device 10 can display a high-brightness image, and the power consumption of the display device 10 can be reduced. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, by painting, a configuration without providing a coloring layer can be adopted.

[0223] Note that the light-shielding layer 738 is provided so as to have a region overlapping with the insulator 730. Further, the light-shielding layer 738 is covered with the insulator 734. Further, the space between the light-emitting element 572 and the insulator 734 is filled with the sealing layer 732.

[0224] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. Also, the structure 778 is provided between the insulator 730 and the insulator 734.

[0225] FIG. 20 is a modified example of the display device 10 shown in FIG. 19, and is different from the display device 10 shown in FIG. 19 in that the coloring layer 736 is provided. By providing the coloring layer 736, the color purity of the light extracted from the light-emitting element 572 can be increased. As a result, a high-quality image can be displayed on the display device 10. Further, since, for example, all the light-emitting elements 572 of the display device 10 can be light-emitting elements that emit white light, the EL layer 786 does not have to be formed by painting, and the pixel density of the display device 10 can be increased.

[0226] In FIGS. 18 to 20, the transistors 441 and 601 are provided such that a channel formation region is formed inside the substrate 701, and an OS transistor is provided by laminating them on the transistors 441 and 601. However, one aspect of the present invention is not limited to this. FIG. 21 is a modified example of FIG. 18, FIG. 22 is a modified example of FIG. 19, and FIG. 23 is a modified example of FIG. 20. The difference from the display device 10 having the configuration shown in FIGS. 18 to 20 is that a transistor 800, a transistor 550, or a transistor 554 is provided by laminating them on the transistors 602 and 603, which are OS transistors, instead of the transistors 441 and 601. That is, in the display device 10 having the configuration shown in FIGS. 21 to 23, the OS transistors are provided in a three-layer laminate.

[0227] An insulator 613 and an insulator 614 are provided on a substrate 701, and a transistor 602 and a transistor 603 are provided on the insulator 614. Note that transistors or the like may be provided between the substrate 701 and the insulator 613. For example, transistors having the same configuration as the transistor 441 and the transistor 601 shown in FIGS. 18 to 20 may be provided between the substrate 701 and the insulator 613. Also, an OS transistor or the like may be provided between the layer in which the transistor 602 and the transistor 603 or the like are provided and the layer in which the transistor 800 or the like is provided. Further, an OS transistor or the like may be provided between the layer in which the transistor 800 or the like is provided and the layer in which the transistor 550 or the transistor 554 or the like is provided. Furthermore, an OS transistor or the like may be provided in a layer above the layer in which the transistor 550 or the transistor 554 or the like is provided.

[0228] The transistor 602 can be a transistor provided in the circuit 40. The transistor 603 can be a transistor provided in the gate driver circuit 21 or a transistor provided in the data driver circuit 22. That is, the transistor 602 and the transistor 603 can be provided in the layer 20 shown in FIG. 1B or the like.

[0229] The transistor 602 and the transistor 603 can be transistors having the same configuration as the transistor 550 or the like. Note that the transistor 602 and the transistor 603 may be OS transistors having a configuration different from that of the transistor 550 and the transistor 554 or the like.

[0230] On the insulator 614, in addition to the transistor 602 and the transistor 603, an insulator 616, an insulator 622, an insulator 624, an insulator 654, an insulator 644, an insulator 680, an insulator 674, and an insulator 681 are provided. A conductor 461 is embedded in the insulator 654, the insulator 644, the insulator 680, the insulator 674, and the insulator 681. Here, the height of the upper surface of the conductor 461 and the height of the upper surface of the insulator 681 can be made approximately the same.

[0231] An insulator 501 is provided on a conductor 461 and on an insulator 681. A conductor 463 is embedded in the insulator 501. Here, the height of the upper surface of the conductor 463 and the height of the upper surface of the insulator 501 can be made approximately the same.

[0232] An insulator 503 is provided on a conductor 463 and on an insulator 501. A conductor 465 is embedded in the insulator 503. Here, the height of the upper surface of the conductor 465 and the height of the upper surface of the insulator 503 can be made approximately the same.

[0233] An insulator 505 is provided on a conductor 465 and on an insulator 503. Also, a conductor 467 is embedded in the insulator 505. The conductor 467 can be provided in the same layer as the wirings 121 to 123 shown in FIG. 19. Here, the height of the upper surface of the conductor 467 and the height of the upper surface of the insulator 505 can be made approximately the same.

[0234] An insulator 507 is provided on a conductor 467 and on an insulator 505. A conductor 469 is embedded in the insulator 507. Here, the height of the upper surface of the conductor 469 and the height of the upper surface of the insulator 507 can be made approximately the same.

[0235] An insulator 509 is provided on a conductor 469 and on an insulator 507. Also, a conductor 471 is embedded in the insulator 509. The conductor 471 can be provided in the same layer as the wirings 141 to 143 shown in FIG. 19. Here, the height of the upper surface of the conductor 471 and the height of the upper surface of the insulator 509 can be made approximately the same.

[0236] An insulator 821 and an insulator 814 are provided on a conductor 471 and on an insulator 509. A conductor 853 is embedded in the insulator 821 and in the insulator 814. Here, the height of the upper surface of the conductor 853 and the height of the upper surface of the insulator 814 can be made approximately the same.

[0237] As shown in FIGS. 21 to 23, one of the source or drain of the transistor 602 is electrically connected to the FPC 716 via the conductor 461, the conductor 463, the conductor 465, the conductor 467, the conductor 469, the conductor 471, the conductor 853, the conductor 855, the conductor 805, the conductor 817, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780.

[0238] The insulators 613, 614, 680, 674, 681, 501, 503, 505, 507, and 509 may function as an interlayer film and may also function as a planarization film covering the uneven shape below each of them.

[0239] By configuring the display device 10 as shown in FIGS. 21 to 23, while making the display device 10 have a narrow bezel and be miniaturized, all the transistors included in the display device 10 can be OS transistors. As a result, since it is not necessary to fabricate different types of transistors, the manufacturing cost of the display device 10 can be reduced, and the display device 10 can be made inexpensive.

[0240] <Configuration Example of Sub-Pixel> FIGS. 24A and 24B are top views showing a configuration example of a sub-pixel 901 that can be applied to a display device according to an aspect of the present invention. The sub-pixel 901 can have the circuit configuration shown in FIG. 4C. That is, when the pixel 34 has the light-emitting element 572, the pixel 34 can have the same configuration as the sub-pixel 901 shown in FIGS. 24A and 24B. Here, in addition to the gate, the transistor 552 has a back gate, and the back gate is electrically connected to the wiring 31. Further, in addition to the gate, the transistor 554 has a back gate, and the back gate is electrically connected to the other of the source or drain of the transistor 554, the other electrode of the capacitor element 562, and one electrode of the light-emitting element 572.

[0241] FIG. 24A shows a transistor, a capacitor element, a conductor such as wiring, and a semiconductor included in the sub-pixel 901. FIG. 24B shows a conductor 772 having a function as one electrode of the light-emitting element 572 in addition to the configuration shown in FIG. 24A. In both FIGS. 24A and 24B, a conductor or the like having a function as the other electrode of the light-emitting element 572 is omitted. Here, one electrode of the light-emitting element 572 has a function as a pixel electrode, and the other electrode of the light-emitting element 572 has a function as a common electrode.

[0242] As shown in FIGS. 24A and 24B, the sub-pixel 901 includes a conductor 911, a conductor 912, a semiconductor 913, a semiconductor 914, a conductor 915a, a conductor 915b, a conductor 916a, a conductor 916b, a conductor 917, a conductor 918, a conductor 919, a conductor 920, a conductor 921, a conductor 922, a conductor 923, a conductor 924, a conductor 925, a conductor 926, a conductor 927, a conductor 928, a conductor 929, a conductor 930, a conductor 931, and a conductor 772.

[0243] The conductor 911 and the conductor 912 can be formed in the same process. The semiconductors 913 and 914 are formed in the same process and can be formed in a process after the conductor 911 and the conductor 912. The conductors 915a and 915b, and the conductors 916a and 916b are formed in the same process and can be formed in a process after the conductor 911 and the conductor 912. The conductors 917 and 918 are formed in the same process and can be formed in a process after the semiconductors 913 and 914, and the conductors 915a, 915b, 916a, and 916b.

[0244] Conductors 919 to 923 are formed in the same process and can be formed in a process after conductors 917 and 918. Conductor 924 can be formed in a process after conductors 919 to 923. Conductors 925 to 928 are formed in the same process and can be formed in a process after conductor 924. Conductors 929 to 931 are formed in the same process and can be formed in a process after conductors 925 to 928. Conductor 772 can be formed in a process after conductors 929 to 931.

[0245] In this specification and the like, it can be said that elements formed in the same process are provided in the same layer. For example, since conductor 911 and conductor 912 can be formed in the same process, it can be said that conductor 911 and conductor 912 are provided in the same layer. Also, it can be said that elements formed in a later process are provided in a layer above the elements formed in an earlier process. For example, since conductors 929 to 931 can be formed in a process after conductors 925 to 928, it can be said that conductors 929 to 931 are provided in a layer above conductors 925 to 928.

[0246] Conductor 911 has a function as the back gate electrode of transistor 552. Semiconductor 913 has the channel formation region of transistor 552. Conductor 915a has a function as one of the source electrode or drain electrode of transistor 552. Conductor 915b has a function as the other of the source electrode or drain electrode of transistor 552. Conductor 917 has a function as the gate electrode of transistor 552.

[0247] Conductor 912 functions as the back gate electrode of transistor 554. Semiconductor 914 has the channel formation region of transistor 554. Conductor 916a functions as one of the source or drain electrodes of transistor 554. Conductor 916b functions as the other of the source or drain electrodes of transistor 554. Conductor 918 functions as the gate electrode of transistor 554.

[0248] Conductor 919 functions as one electrode of capacitor element 562. Conductor 924 functions as the other electrode of capacitor element 562. Conductor 925 corresponds to wiring 31 which functions as a scanning line. Conductor 929 corresponds to wiring 32 which functions as a data line. Conductor 930 corresponds to wiring 35a which functions as a power supply line. Conductor 772 functions as one electrode of light-emitting element 572 as described above.

[0249] Conductor 911 is electrically connected to conductor 920. Conductor 912 is electrically connected to conductor 923. Conductor 915a is electrically connected to conductor 921. Conductor 915b is electrically connected to conductor 919. Conductor 916a is electrically connected to conductor 922.

[0250] Conductor 916b is electrically connected to conductor 923. That is, conductor 912 which functions as the back gate electrode of transistor 554 and conductor 916b which functions as the other of the source or drain electrodes of transistor 554 are electrically connected via conductor 923.

[0251] Conductor 917 is electrically connected to conductor 920. That is, conductor 911 which functions as the back gate electrode of transistor 552 and conductor 917 which functions as the gate electrode of transistor 552 are electrically connected via conductor 920.

[0252] Conductor 920 is electrically connected to conductor 925. That is, conductor 917, which functions as the gate electrode of transistor 552, and conductor 925, which functions as a scanning line, are electrically connected via conductor 920.

[0253] Conductor 918 is electrically connected to conductor 919. Conductor 921 is electrically connected to conductor 926. Conductor 922 is electrically connected to conductor 927. Conductor 923 is electrically connected to conductor 928. Conductor 924 is electrically connected to conductor 928.

[0254] Conductor 926 is electrically connected to conductor 929. That is, conductor 915a, which functions as one of the source electrode or drain electrode of transistor 552, and conductor 929, which functions as a data line, are electrically connected via conductor 921 and conductor 926.

[0255] Conductor 927 is electrically connected to conductor 930. That is, conductor 916a, which functions as one of the source electrode or drain electrode of transistor 554, and conductor 930, which functions as a power supply line, are electrically connected via conductor 922 and conductor 927.

[0256] Conductor 928 is electrically connected to conductor 931. Conductor 931 is electrically connected to conductor 772.

[0257] Semiconductors 913 and 914 can have, for example, metal oxides. Therefore, transistors 552 and 554 can be OS transistors.

[0258] FIG. 25 is a top view showing a configuration example of a pixel 902 constituted by sub-pixels 901 having the configuration shown in FIG. 24B. In FIG. 25, sub-pixel 901R represents a sub-pixel 901 having a function of emitting red light, sub-pixel 901G represents a sub-pixel 901 having a function of emitting green light, and sub-pixel 901B represents a sub-pixel 901 having a function of emitting blue light. As shown in FIG. 25, the pixel 902 is constituted by a sub-pixel 901R, a sub-pixel 901G, and a sub-pixel 901B. Specifically, one pixel 902 is constituted by a sub-pixel 901R and a sub-pixel 901B provided in the upper row and a sub-pixel 901G provided in the lower row. Also, one pixel 902 is constituted by a sub-pixel 901G provided in the upper row and a sub-pixel 901R and a sub-pixel 901B provided in the lower row.

[0259] In FIG. 25, the sub-pixels 901R, 901G, and 901B provided in the upper row and the sub-pixels 901R, 901G, and 901B provided in the lower row have a configuration that is inverted left and right. By adopting such a configuration, sub-pixels 901 of the same color can be alternately arranged in the extending direction of the conductor 925 having a function as a scanning line. As a result, a configuration can be adopted in which sub-pixels 901 having a function of emitting light of the same color are electrically connected to one data line. That is, it is possible to suppress two or more types of sub-pixels 901 among the sub-pixels 901R, 901G, and 901B from being electrically connected to one data line.

[0260] FIG. 26 is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 24B. A transistor 552 and a transistor 554 are provided on an insulator 1021. Also, an insulator 1022 is provided on the transistor 552 and on the transistor 554, and an insulator 1023 is provided on the insulator 1022. Note that a substrate is provided in a layer lower than the insulator 1021. Also, components of layer 20 (gate driver circuit 21, data driver circuit 22, circuit 40, etc.) and components of layer 80 (demultiplexer circuit 81, etc.) shown in FIG. 1B etc. can be provided between the substrate and the insulator 1021.

[0261] As shown in FIG. 26, conductors provided in different layers are electrically connected via a conductor 990 having a function as a plug. For example, a conductor 915a and a conductor 921 provided in a layer above the conductor 915a are electrically connected via the conductor 990. The conductor 990 can have the same configuration as the conductors 853, 805, 453, 305, 337, 353, 355, 357, 301a, 301b, 331, 351, 333, 335 shown in FIG. 18 and the like.

[0262] An insulator 1024 is provided on the conductors 919 to 923 and on the insulator 1023. A conductor 924 is provided on the insulator 1024. A capacitor element 562 is constituted by the conductor 919, the insulator 1024, and the conductor 924.

[0263] An insulator 1025 is provided on the conductor 924 and on the insulator 1024. An insulator 1026 is provided on the conductors 925 to 928 and on the insulator 1025. An insulator 1027 is provided on the conductors 929 to 931 and on the insulator 1026.

[0264] A conductor 772 and an insulator 730 are provided on the insulator 1027. Here, the insulator 730 can be configured to cover a part of the conductor 772. A light-emitting element 572 is constituted by the conductor 772, the EL layer 786, and the conductor 788.

[0265] An adhesive layer 991 is provided on the conductor 788, and an insulator 992 is provided on the adhesive layer 991. The insulator 992 on the adhesive layer 991 can be formed by the following procedure. First, the insulator 992 is formed on a substrate different from the substrate on which the light-emitting element 572 and the like are formed. Next, the conductor 788 and the insulator 992 are adhered by the adhesive layer 991. Then, the substrate on which the insulator 992 is formed is peeled off. Thus, the insulator 992 can be formed on the conductor 788.

[0266] On the insulator 992, a colored layer 993 is provided. In FIG. 26, the colored layers 993a and 993b are illustrated as the colored layer 993. On the colored layer 993, a substrate 995 is bonded by an adhesive layer 994.

[0267] The colored layer 993b has a function of transmitting light of a color different from that of the colored layer 993a. For example, if the pixel 902 is composed of a sub-pixel 901R having a function of emitting red light, a sub-pixel 901G having a function of emitting green light, and a sub-pixel 901B having a function of emitting blue light, and the colored layer 993a has a function of transmitting red light, the colored layer 993b has a function of transmitting green light or blue light.

[0268] By forming the colored layer 993 on the insulator 992, the alignment between the colored layer 993 and the light-emitting element 572 can be easily performed. Thereby, the pixel density of the display device according to one aspect of the present invention can be increased.

[0269] <Configuration example of the light-emitting element 572> FIGS. 27A to 27E are diagrams showing a configuration example of the light-emitting element 572. FIG. 27A shows a structure (single structure) in which an EL layer 786 is sandwiched between a conductor 772 and a conductor 788. As described above, the EL layer 786 contains a light-emitting material, and for example, a light-emitting material that is an organic compound is contained.

[0270] FIG. 27B is a diagram showing a stacked structure of the EL layer 786. Here, in the light-emitting element 572 having the structure shown in FIG. 27B, the conductor 772 functions as an anode, and the conductor 788 functions as a cathode.

[0271] The EL layer 786 has a structure in which a hole injection layer 721, a hole transport layer 722, a light-emitting layer 723, an electron transport layer 724, and an electron injection layer 725 are sequentially stacked on the conductor 772. When the conductor 772 functions as a cathode and the conductor 788 functions as an anode, the stacking order is reversed.

[0272] The light-emitting layer 723 has a light-emitting material and a plurality of materials appropriately combined, and can be configured to obtain fluorescence emission or phosphorescence emission that exhibits a desired emission color. Further, the light-emitting layer 723 may have a stacked structure with different emission colors. In this case, different materials may be used for the light-emitting substances and other substances used in each of the stacked light-emitting layers.

[0273] In the light-emitting element 572, for example, by using the conductor 772 shown in FIG. 27B as a reflective electrode, the conductor 788 as a semi-transmissive / semi-reflective electrode, and forming a microcavity structure, the light emission obtained from the light-emitting layer 723 included in the EL layer 786 can be resonated between both electrodes, and the light emission transmitted through the conductor 788 and emitted can be enhanced.

[0274] When the conductor 772 of the light-emitting element 572 is a reflective electrode having a laminated structure of a conductive material having reflectivity and a conductive material having translucency (transparent conductive film), optical adjustment can be performed by controlling the film thickness of the transparent conductive film. Specifically, it is preferable to adjust so that the electrode distance between the conductor 772 and the conductor 788 is in the vicinity of mλ / 2 (where m is a natural number) with respect to the wavelength λ of the light obtained from the light-emitting layer 723.

[0275] Further, in order to amplify the desired light (wavelength: λ) obtained from the light-emitting layer 723, the optical distance from the conductor 772 to the region (light-emitting region) where the desired light of the light-emitting layer 723 can be obtained, and the optical distance from the conductor 788 to the region (light-emitting region) where the desired light of the light-emitting layer 723 can be obtained are each preferably adjusted to be in the vicinity of (2m'+1)λ / 4 (where m' is a natural number). Here, the light-emitting region refers to the recombination region of holes and electrons in the light-emitting layer 723.

[0276] By performing such optical adjustment, the spectrum of a specific monochromatic light obtained from the light-emitting layer 723 can be narrowed, and light emission with good color purity can be obtained.

[0277] However, in the above case, the optical distance between the conductor 772 and the conductor 788 can be strictly said to be the total thickness from the reflection region in the conductor 772 to the reflection region in the conductor 788. However, since it is difficult to strictly determine the reflection regions in the conductor 772 and the conductor 788, it is assumed that the above effects can be sufficiently obtained by assuming any positions of the conductor 772 and the conductor 788 as the reflection regions. Also, the optical distance between the conductor 772 and the light-emitting layer from which desired light is obtained can be strictly said to be the optical distance between the reflection region in the conductor 772 and the light-emitting region in the light-emitting layer from which desired light is obtained. However, since it is difficult to strictly determine the reflection region in the conductor 772 and the light-emitting region in the light-emitting layer from which desired light is obtained, it is assumed that the above effects can be sufficiently obtained by assuming any position of the conductor 772 as the reflection region and any position of the light-emitting layer from which desired light is obtained as the light-emitting region.

[0278] Since the light-emitting element 572 shown in FIG. 27B has a microcavity structure, even if it has the same EL layer, light (monochromatic light) of different wavelengths can be extracted. Therefore, painting (for example, RGB) for obtaining different emission colors becomes unnecessary. Therefore, it is easy to achieve high definition. Also, a combination with a coloring layer is possible. Furthermore, since it is possible to enhance the emission intensity in the front direction of a specific wavelength, power consumption can be reduced.

[0279] Note that the light-emitting element 572 shown in FIG. 27B does not necessarily have a microcavity structure. In this case, the light-emitting layer 723 has a structure that emits white light, and by providing a coloring layer, light of a predetermined color (for example, RGB) can be extracted. Also, when forming the EL layer 786, if painting for obtaining different emission colors is performed, light of a predetermined color can be extracted without providing a coloring layer.

[0280] At least one of the conductor 772 and the conductor 788 can be an electrode with translucency (such as a transparent electrode, a semi-transmissive and semi-reflective electrode, etc.). When the electrode with translucency is a transparent electrode, the transmittance of visible light of the transparent electrode shall be 40% or more. Also, in the case of a semi-transmissive and semi-reflective electrode, the reflectance of visible light of the semi-transmissive and semi-reflective electrode shall be 20% or more and 80% or less, preferably 40% or more and 70% or less. Further, the resistivity of these electrodes is preferably 1×10 -2 Ω·cm or less.

[0281] When the conductor 772 or the conductor 788 is an electrode with reflectivity (reflective electrode), the reflectance of visible light of the electrode with reflectivity shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Also, the resistivity of this electrode is preferably 1×10 -2 Ω·cm or less.

[0282] The configuration of the light-emitting element 572 may be the configuration shown in FIG. 27C. FIG. 27C shows a light-emitting element 572 having a stacked structure (tandem structure) in which two EL layers (EL layer 786a and EL layer 786b) are provided between the conductor 772 and the conductor 788, and a charge generation layer 792 is provided between the EL layer 786a and the EL layer 786b. By making the light-emitting element 572 have a tandem structure, the current efficiency and external quantum efficiency of the light-emitting element 572 can be increased. Therefore, a high-brightness image can be displayed on the display device 10. Also, the power consumption of the display device 10 can be reduced. Here, the EL layer 786a and the EL layer 786b can have the same configuration as the EL layer 786 shown in FIG. 27B.

[0283] The charge generation layer 792 has a function of injecting electrons into one of the EL layer 786a and the EL layer 786b and injecting holes into the other when a voltage is supplied between the conductor 772 and the conductor 788. Therefore, when a voltage is supplied so that the potential of the conductor 772 becomes higher than the potential of the conductor 788, electrons are injected from the charge generation layer 792 into the EL layer 786a, and holes are injected from the charge generation layer 792 into the EL layer 786b.

[0284] Note that, from the viewpoint of light extraction efficiency, the charge generation layer 792 preferably transmits visible light (specifically, the transmittance of visible light of the charge generation layer 792 is 40% or more). Further, the conductivity of the charge generation layer 792 may be lower than the conductivity of the conductor 772 or the conductivity of the conductor 788.

[0285] The configuration of the light-emitting element 572 may be the configuration shown in FIG. 27D. In FIG. 27D, three EL layers (EL layer 786a, EL layer 786b, and EL layer 786c) are provided between the conductor 772 and the conductor 788, and a tandem-structured light-emitting element 572 having a charge generation layer 792 between the EL layer 786a and the EL layer 786b and between the EL layer 786b and the EL layer 786c is shown. Here, the EL layer 786a, the EL layer 786b, and the EL layer 786c can have the same configuration as the EL layer 786 shown in FIG. 27B. By setting the configuration of the light-emitting element 572 to the configuration shown in FIG. 27D, the current efficiency and the external quantum efficiency of the light-emitting element 572 can be further increased. Therefore, an image with higher brightness can be displayed on the display device 10. Further, the power consumption of the display device 10 can be further reduced.

[0286] The configuration of the light-emitting element 572 may be the configuration shown in FIG. 27E. In FIG. 27E, n EL layers (EL layer 786(1) to EL layer 786(n)) are provided between the conductor 772 and the conductor 788, and a tandem-structured light-emitting element 572 having a charge generation layer 792 between each EL layer 786 is shown. Here, the EL layer 786(1) to the EL layer 786(n) can have the same configuration as the EL layer 786 shown in FIG. 27B. Note that FIG. 27E shows the EL layer 786(1), the EL layer 786(m), the EL layer 786(m + 1), and the EL layer 786(n) among the EL layers 786. Here, m is an integer of 2 or more and less than n, and n is an integer larger than m. The larger the value of n, the higher the current efficiency and the external quantum efficiency of the light-emitting element 572 can be. Therefore, a high-brightness image can be displayed on the display device 10. Further, the power consumption of the display device 10 can be reduced.

[0287] <Constituent Materials of the Light-Emitting Element 572> Next, the constituent materials that can be used for the light-emitting element 572 will be described.

[0288] <<Conductors 772 and 788>> For the conductors 772 and 788, as long as the functions of the anode and the cathode can be satisfied, the materials shown below can be appropriately combined and used. For example, metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used. Specifically, indium-tin oxide (also referred to as ITO), indium-silicon-tin oxide (also referred to as ITSO), indium-zinc oxide, indium-tungsten-zinc oxide can be mentioned. In addition, metals such as aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y), neodymium (Nd), etc., and alloys containing these appropriately combined can also be used. In addition, elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (for example, lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr)), rare earth metals such as europium (Eu), ytterbium (Yb), and alloys containing these appropriately combined, and other graphene, etc. can be used.

[0289] <<Hole injection layer 721 and hole transport layer 722>> The hole injection layer 721 is a layer that injects holes from the conductor 772, which is the anode, or the charge generation layer 792 into the EL layer 786, and is a layer containing a material with high hole injection properties. Here, the EL layer 786 shall include the EL layer 786a, the EL layer 786b, the EL layer 786c, and the EL layers 786(1) to 786(n).

[0290] Examples of materials with high hole injection properties include transition metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide. In addition, phthalocyanine-based compounds such as phthalocyanine (abbreviation: H2Pc) and copper phthalocyanine (abbreviation: CuPc), aromatic amine compounds such as 4,4'-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (abbreviation: DPAB), N,N'-bis{4-[bis(3-methylphenyl)amino]phenyl}-N,N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine (abbreviation: DNTPD), or polymers such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (abbreviation: PEDOT / PSS) can be used.

[0291] In addition, as a material with high hole injection properties, a composite material containing a hole transporting material and an acceptor material (electron accepting material) can also be used. In this case, electrons are extracted from the hole transporting material by the acceptor material, and holes are generated in the hole injection layer 721, and the holes are injected into the light emitting layer 723 through the hole transport layer 722. Note that the hole injection layer 721 may be formed of a single layer made of a composite material containing a hole transporting material and an acceptor material (electron accepting material), or may be formed by laminating the hole transporting material and the acceptor material (electron accepting material) in separate layers.

[0292] The hole transport layer 722 is a layer that transports the holes injected from the conductor 772 to the light emitting layer 723 by the hole injection layer 721. Note that the hole transport layer 722 is a layer containing a hole transporting material. It is preferable to use a hole transporting material for the hole transport layer 722 that has the same or nearly the same HOMO level as that of the hole injection layer 721.

[0293] As the acceptor material used for the positive hole injection layer 721, metal oxides belonging to Groups 4 to 8 in the periodic table can be used. Specifically, molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide can be mentioned. Among them, molybdenum oxide is particularly preferable because it is stable in the air, has low hygroscopicity, and is easy to handle. In addition, organic acceptors such as quinodimethane derivatives, chloranil derivatives, and hexaazatriphenylene derivatives can be used. Specifically, 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviation: F4-TCNQ), chloranil, 2,3,6,7,10,11-hexacyano-1,4,5,8,9,12-hexaazatriphenylene (abbreviation: HAT-CN), etc. can be used.

[0294] As the hole transporting material used for the hole injection layer 721 and the hole transport layer 722, a substance having a hole mobility of 10 -6 cm 2 / Vs or more is preferable. In addition, as long as the substance has higher hole transportability than electrons, other substances can be used.

[0295] As the positive hole transporting material, π - electron - rich heteroaromatic compounds (such as carbazole derivatives and indole derivatives) and aromatic amine compounds are preferred. Specific examples include 4,4'-bis[N-(1 - naphthyl)-N - phenylamino]biphenyl (abbreviation: NPB or α - NPD), N,N'-bis(3 - methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (abbreviation: TPD), 4,4'-bis[N-(spiro - 9,9'-bifluorene - 2 - yl)-N - phenylamino]biphenyl (abbreviation: BSPB), 4 - phenyl - 4'-(9 - phenylfluorene - 9 - yl)triphenylamine (abbreviation: BPAFLP), 4 - phenyl - 3'-(9 - phenylfluorene - 9 - yl)triphenylamine (abbreviation: mBPAFLP), 4 - phenyl - 4'-(9 - phenyl - 9H - carbazol - 3 - yl)triphenylamine (abbreviation: PCBA1BP), 3 - [4-(9 - phenanthryl)-phenyl]-9 - phenyl - 9H - carbazole (abbreviation: PCPPn), N-(4 - biphenyl)-N-(9,9 - dimethyl - 9H - fluorene - 2 - yl)-9 - phenyl - 9H - carbazole - 3 - amine (abbreviation: PCBiF), N-(1,1'-biphenyl - 4 - yl)-N-[4-(9 - phenyl - 9H - carbazol - 3 - yl)phenyl]-9,9 - dimethyl - 9H - fluorene - 2 - amine (abbreviation: PCBBiF), 4,4'-diphenyl - 4''-(9 - phenyl - 9H - carbazol - 3 - yl)triphenylamine (abbreviation: PCBBi1BP), 4-(1 - naphthyl)-4'-(9 - phenyl - 9H - carbazol - 3 - yl)triphenylamine (abbreviation: PCBANB), 4,4'-di(1 - naphthyl)-4''-(9 - phenyl - 9H - carbazol - 3 - yl)triphenylamine (abbreviation: PCBNBB), 9,9 - dimethyl - N - phenyl - N-[4-(9 - phenyl - 9H - carbazol - 3 - yl)phenyl]fluorene - 2 - amine (abbreviation: PCBAF), N - phenyl - N-[4-(9 - phenyl - 9H - carbazol - 3 - yl)phenyl]spiro - 9,9'-bifluorene - 2 - amine (abbreviation: PCBASF), 4,4',4''-tris(carbazol - 9 - yl)triphenylamine (abbreviation: TCTA), 4,4',4''-tris(N,Compounds having an aromatic amine skeleton such as (N-diphenylamino)triphenylamine (abbreviation: TDATA), 4,4',4''-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (abbreviation: MTDATA), compounds having a carbazole skeleton such as 1,3-bis(N-carbazolyl)benzene (abbreviation: mCP), 4,4'-di(N-carbazolyl)biphenyl (abbreviation: CBP), 3,6-bis(3,5-diphenylphenyl)-9-phenylcarbazole (abbreviation: CzTP), 3,3'-bis(9-phenyl-9H-carbazole) (abbreviation: PCCP), 3-[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA1), 3,6-bis[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA2), 3-[N-(1-naphthyl)-N-(9-phenylcarbazol-3-yl)amino]-9-phenylcarbazole (abbreviation: PCzPCN1), 1,3,5-tris[4-(N-carbazolyl)phenyl]benzene (abbreviation: TCPB), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), compounds having a thiophene skeleton such as 4,4',4''-(benzene-1,3,5-triyl)tri(dibenzothiophene) (abbreviation: DBT3P-II), 2,8-diphenyl-4-[4-(9-phenyl-9H-fluorene-9-yl)phenyl]dibenzothiophene (abbreviation: DBTFLP-III), 4-[4-(9-phenyl-9H-fluorene-9-yl)phenyl]-6-phenyldibenzothiophene (abbreviation: DBTFLP-IV), compounds having a furan skeleton such as 4,4',4''-(benzene-1,3,5-triyl)tri(dibenzofuran) (abbreviation: DBF3P-II), 4-{3-[3-(9-phenyl-9H-fluorene-9-yl)phenyl]phenyl}dibenzofuran (abbreviation: mmDBFFLBi-II), etc.

[0296] Furthermore, high molecular compounds such as poly(N-vinylcarbazole) (abbreviation: PVK), poly(4-vinyltriphenylamine) (abbreviation: PVTPA), poly[N-(4-{N’-[4-(4-diphenylamino)phenyl]phenyl-N’-phenylamino}phenyl)methacrylamide] (abbreviation: PTPDMA), poly[N,N’-bis(4-butylphenyl)-N,N’-bis(phenyl)benzidine] (abbreviation: Poly-TPD), etc. can also be used.

[0297] However, the hole transporting material is not limited to the above, and various known materials can be used alone or in combination of one or more kinds as the hole transporting material for the hole injection layer 721 and the hole transport layer 722. Note that the hole transport layer 722 may be formed of a plurality of layers. That is, for example, a first hole transport layer and a second hole transport layer may be laminated.

[0298] <<Light-emitting layer 723>> The light-emitting layer 723 is a layer containing a light-emitting substance. As the light-emitting substance, substances exhibiting light-emitting colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, red, etc. are appropriately used. Here, as shown in FIGS. 27C to 27E, when the light-emitting element 572 has a plurality of EL layers, by using different light-emitting substances for the light-emitting layers 723 provided in each EL layer, a configuration exhibiting different light-emitting colors (for example, white light emission obtained by combining light-emitting colors in a complementary color relationship) can be achieved. For example, when the light-emitting element 572 has the configuration shown in FIG. 27C, by making the light-emitting substance used for the light-emitting layer 723 provided in the EL layer 786a different from the light-emitting substance used for the light-emitting layer 723 provided in the EL layer 786b, the light-emitting color exhibited by the EL layer 786a and the light-emitting color exhibited by the EL layer 786b can be made different. Note that one light-emitting layer may have a laminated structure having different light-emitting substances.

[0299] In addition, the light-emitting layer 723 may have one or more organic compounds (host materials, assist materials) in addition to the light-emitting substance (guest material). Further, as the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used.

[0300] The light-emitting substance that can be used in the light-emitting layer 723 is not particularly limited, and a light-emitting substance that converts singlet excitation energy into light emission in the visible light region or a light-emitting substance that converts triplet excitation energy into light emission in the visible light region can be used. Examples of the above light-emitting substance include the following.

[0301] Examples of the luminescent material that converts singlet excitation energy into luminescence include substances that emit fluorescence (fluorescent materials), such as pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, naphthalene derivatives, and the like. In particular, pyrene derivatives are preferred because of their high luminescence quantum yield. Specific examples of pyrene derivatives include N,N'-bis(3-methylphenyl)-N,N'-bis[3-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6-diamine (abbreviation: 1,6mMemFLPAPrn), N,N'-diphenyl-N,N'-bis[4-(9-phenyl-9H-fluoren-9-yl)phenyl]pyrene-1,6-diamine (abbreviation: 1,6FLPAPrn), N,N'-bis(dibenzofuran-2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviation: 1,6FrAPrn), N,N'-bis(dibenzothiophene-2-yl)-N,N'-diphenylpyrene-1,6-diamine (abbreviation: 1,6ThAPrn), N,N'-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b]naphtho[1,2-d]furan)-6-amine] (abbreviation: 1,6BnfAPrn), N,N'-(pyrene-1,6-diyl)bis[(N-phenylbenzo[b]naphtho[1,2-d]furan)-8-amine] (abbreviation: 1,6BnfAPrn-02), N,N'-(pyrene-1,6-diyl)bis[(6,N-diphenylbenzo[b]naphtho[1,2-d]furan)-8-amine] (abbreviation: 1,6BnfAPrn-03), and the like. Further, pyrene derivatives are a group of compounds useful for achieving the blue chromaticity in one aspect of the present invention.

[0302] In addition, 5,6-bis[4-(10-phenyl-9-anthryl)phenyl]-2,2'-bipyridine (abbreviation: PAP2BPy), 5,6-bis[4'-(10-phenyl-9-anthryl)biphenyl-4-yl]-2,2'-bipyridine (abbreviation: PAPP2BPy), N,N'-bis[4-(9H-carbazol-9-yl)phenyl]-N,N'-diphenylstilbene-4,4'-diamine (abbreviation: YGA2S), 4-(9H-carbazol-9-yl)-4'-(10-phenyl-9-anthryl)triphenylamine (abbreviation: YGAPA), 4-(9H-carbazol-9-yl)-4'-(9,10-diphenyl-2-anthryl)triphenylamine (abbreviation: 2YGAPPA), N,9-diphenyl-N-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole-3-amine (abbreviation: PCAPA), 4-(10-phenyl-9-anthryl)-4'-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBAPA), 4-[4-(10-phenyl-9-anthryl)phenyl]-4'-(9-phenyl-9H-carbazol-3-yl)triphenylamine (abbreviation: PCBAPBA), perylene, 2,5,8,11-tetra(tert-butyl)perylene (abbreviation: TBP), N,N''-(2-tert-butylanthracene-9,10-diyl-di-4,1-phenylene)bis[N,N',N'-triphenyl-1,4-phenylenediamine] (abbreviation: DPABPA), N,9-diphenyl-N-[4-(9,10-diphenyl-2-anthryl)phenyl]-9H-carbazole-3-amine (abbreviation: 2PCAPPA), N-[4-(9,10-diphenyl-2-anthryl)phenyl]-N,N',N'-triphenyl-1,4-phenylenediamine (abbreviation: 2DPAPPA), etc. can be used.

[0303] In addition, examples of the luminescent substance that converts triplet excitation energy into luminescence include substances that emit phosphorescence (phosphorescent materials) and thermally activated delayed fluorescence (TADF) materials that exhibit thermally activated delayed fluorescence.

[0304] Examples of the phosphorescent material include organometallic complexes, metal complexes (platinum complexes), rare earth metal complexes, etc. Since these exhibit different emission colors (emission peaks) for each substance, they are appropriately selected and used as needed.

[0305] Examples of the phosphorescent material that exhibits blue or green and has a peak wavelength of the emission spectrum in the range of 450 nm or more and 570 nm or less include the following substances.

[0306] For example, organometallic complexes having a 4H-triazole skeleton such as tris{2-[5-(2-methylphenyl)-4-(2,6-dimethylphenyl)-4H-1,2,4-triazol-3-yl-κN2]phenyl-κC}iridium(III) (abbreviation: [Ir(mpptz-dmp)3]), tris(5-methyl-3,4-diphenyl-4H-1,2,4-triazolato)iridium(III) (abbreviation: [Ir(Mptz)3]), tris[4-(3-biphenyl)-5-isopropyl-3-phenyl-4H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(iPrptz-3b)3]), tris[3-(5-biphenyl)-5-isopropyl-4-phenyl-4H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(iPr5btz)3]); organometallic complexes having a 1H-triazole skeleton such as tris[3-methyl-1-(2-methylphenyl)-5-phenyl-1H-1,2,4-triazolato]iridium(III) (abbreviation: [Ir(Mptz1-mp)3]), tris(1-methyl-5-phenyl-3-propyl-1H-1,2,4-triazolato)iridium(III) (abbreviation: [Ir(Prptz1-Me)3]); organometallic complexes having an imidazole skeleton such as fac-tris[1-(2,6-diisopropylphenyl)-2-phenyl-1H-imidazole]iridium(III) (abbreviation: [Ir(iPrpmi)3]), tris[3-(2,6-dimethylphenyl)-7-methylimidazo[1,2-f]phenanthridinato]iridium(III) (abbreviation: [Ir(dmpimpt-Me)3]); bis[2-(4’,6’-difluorophenyl)pyridinato-N,C 2’Iridium(III) tetrakis(1-pyrazolyl)borate (abbreviation: FIr6), bis[2-(4’,6’-difluorophenyl)pyridinato-N,C 2’ Iridium(III) picolinate (abbreviation: FIrpic), bis[2-(3,5-bistrifluoromethylphenyl)pyridinato-N,C 2’ Iridium(III) picolinate (abbreviation: [Ir(CF3ppy)2(pic)]), bis[2-(4’,6’-difluorophenyl)pyridinato-N,C 2’ Examples include organometallic complexes having a phenylpyridine derivative having an electron-withdrawing group as a ligand, such as iridium(III) acetylacetonate (abbreviation: FIr(acac)).

[0307] Examples of the phosphorescent material that exhibits green or yellow and has a peak wavelength of the emission spectrum in the range of 495 nm or more and 590 nm or less include the following substances.

[0308] For example, organometallic iridium complexes having a pyrimidine skeleton such as tris(4-methyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(mppm)3]), tris(4-t-butyl-6-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm)3]), (acetylacetonato)bis(6-methyl-4-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(mppm)2(acac)]), (acetylacetonato)bis(6-tert-butyl-4-phenylpyrimidinato)iridium(III) (abbreviation: [Ir(tBuppm)2(acac)]), (acetylacetonato)bis[6-(2-norbornyl)-4-phenylpyrimidinato]iridium(III) (abbreviation: [Ir(nbppm)2(acac)]), (acetylacetonato)bis[5-methyl-6-(2-methylphenyl)-4-phenylpyrimidinato]iridium(III) (abbreviation: [Ir(mpmppm)2(acac)]), (acetylacetonato)bis{4,6-dimethyl-2-[6-(2,6-dimethylphenyl)-4-pyrimidinyl-κN3]phenyl-κC}iridium(III) (abbreviation: [Ir(dmppm-dmp)2(acac)]), (acetylacetonato)bis(4,6-diphenylpyrimidinato)iridium(III) (abbreviation: [Ir(dppm)2(acac)]); organometallic iridium complexes having a pyrazine skeleton such as (acetylacetonato)bis(3,5-dimethyl-2-phenylpyrazinato)iridium(III) (abbreviation: [Ir(mppr-Me)2(acac)]), (acetylacetonato)bis(5-isopropyl-3-methyl-2-phenylpyrazinato)iridium(III) (abbreviation: [Ir(mppr-iPr)2(acac)]); tris(2-phenylpyridinato-N,C 2’ )iridium(III) (abbreviation: [Ir(ppy)3]), bis(2-phenylpyridinato-N,C 2’Iridium(III) acetylacetonate (abbreviation: [Ir(ppy)2(acac)]), bis(benzo[h]quinolinato)iridium(III) acetylacetonate (abbreviation: [Ir(bzq)2(acac)]), tris(benzo[h]quinolinato)iridium(III) (abbreviation: [Ir(bzq)3]), tris(2-phenylquinolinato-N,C 2’ ) iridium(III) (abbreviation: [Ir(pq)3]), bis(2-phenylquinolinato-N,C 2’ ) organometallic iridium complexes having a pyridine skeleton such as iridium(III) acetylacetonate (abbreviation: [Ir(pq)2(acac)]), bis(2,4-diphenyl-1,3-oxazolato-N,C 2’ ) iridium(III) acetylacetonate (abbreviation: [Ir(dpo)2(acac)]), bis{2-[4’-(perfluorophenyl)phenyl]pyridinato-N,C 2’} iridium(III) acetylacetonate (abbreviation: [Ir(p-PF-ph)2(acac)]), bis(2-phenylbenzothiazolato-N,C 2’ ) iridium(III) acetylacetonate (abbreviation: [Ir(bt)2(acac)]) and other organometallic complexes, and rare earth metal complexes such as tris(acetylacetonato)(monophenanthroline)terbium(III) (abbreviation: [Tb(acac)3(Phen)]).

[0309] Among the above, organometallic iridium complexes having a pyridine skeleton (especially a phenylpyridine skeleton) or a pyrimidine skeleton are a group of compounds useful for achieving the green chromaticity in one aspect of the present invention.

[0310] Examples of the phosphorescent material that exhibits yellow or red and has a peak wavelength of the emission spectrum in the range of 570 nm or more and 750 nm or less include the following substances.

[0311] For example, organometallic complexes having a pyrimidine skeleton such as (diisobutyrylmethanato)bis[4,6-bis(3-methylphenyl)pyrimidinato]iridium(III) (abbreviation: [Ir(5mdppm)2(dibm)]), bis[4,6-bis(3-methylphenyl)pyrimidinato](dipivaloylmethanato)iridium(III) (abbreviation: [Ir(5mdppm)2(dpm)]), (dipivaloylmethanato)bis[4,6-di(naphthalen-1-yl)pyrimidinato]iridium(III) (abbreviation: [Ir(d1npm)2(dpm)]), (acetylacetonato)bis(2,3,5-triphenylpyrazinato)iridium(III) (abbreviation: [Ir(tppr)2(acac)]), bis(2,3,5-triphenylpyrazinato)(dipivaloylmethanato)iridium(III) (abbreviation: [Ir(tppr)2(dpm)]), bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-5-phenyl-2-pyrazinyl-κN]phenyl-κC}(2,6-dimethyl-3,5-heptanedionato-κ 2 O,O’)iridium(III) (abbreviation: [Ir(dmdppr-P)2(dibm)]), bis{4,6-dimethyl-2-[5-(4-cyano-2,6-dimethylphenyl)-3-(3,5-dimethylphenyl)-2-pyrazinyl-κN]phenyl-κC}(2,2,6,6-tetramethyl-3,5-heptanedionato-κ 2 O,O’)iridium(III) (abbreviation: [Ir(dmdppr-dmCP)2(dpm)]), (acetylacetonato)bis[2-methyl-3-phenylquinoxalinato-N,C 2’ iridium(III) (abbreviation: [Ir(mpq)2(acac)]), (acetylacetonato)bis(2,3-diphenylquinoxalinato-N,C 2’ )iridium(III) (abbreviation: [Ir(dpq)2(acac)]), (acetylacetonato)bis[2,3-bis(4-fluorophenyl)quinoxalinato]iridium(III) (abbreviation: [Ir(Fdpq)2(acac)]) and other organometallic complexes having a pyrazine skeleton, tris(1-phenylisoquinolinato-N,C 2’)Iridium(III) (abbreviation: [Ir(piq)3]), bis(1-phenylisoquinolinato-N,C 2’ )Organometallic complexes having a pyridine skeleton such as iridium(III) acetylacetonate (abbreviation: [Ir(piq)2(acac)]), platinum complexes such as platinum(II) 2,3,7,8,12,13,17,18-octaethyl-21H,23H-porphyrin (abbreviation: [PtOEP]), rare earth metal complexes such as tris(1,3-diphenyl-1,3-propanedionato)(monophenanthroline)europium(III) (abbreviation: [Eu(DBM)3(Phen)]), tris[1-(2-thenoyl)-3,3,3-trifluoroacetonato](monophenanthroline)europium(III) (abbreviation: [Eu(TTA)3(Phen)]) can be mentioned.

[0312] Among the above, the organometallic iridium complexes having a pyrazine skeleton are a group of compounds useful for achieving the red chromaticity in one aspect of the present invention. In particular, organometallic iridium complexes having a cyano group such as [Ir(dmdppr-dmCP)2(dpm)] are highly stable and preferable.

[0313] In addition, as the blue light-emitting substance, a substance having a photoluminescence peak wavelength of 430 nm or more and 470 nm or less, more preferably 430 nm or more and 460 nm or less may be used. Further, as the green light-emitting substance, a substance having a photoluminescence peak wavelength of 500 nm or more and 540 nm or less, more preferably 500 nm or more and 530 nm or less may be used. As the red light-emitting substance, a substance having a photoluminescence peak wavelength of 610 nm or more and 680 nm or less, more preferably 620 nm or more and 680 nm or less may be used. Note that the photoluminescence measurement may be performed on either a solution or a thin film.

[0314] By using such a compound in combination with the microcavity effect, the above-described chromaticity can be achieved more easily. At this time, the film thickness of the semi-transmissive / semi-reflective electrode (metal thin film portion) required to obtain the microcavity effect is preferably 20 nm or more and 40 nm or less. More preferably, it is greater than 25 nm and 40 nm or less. Note that if it exceeds 40 nm, the efficiency may decrease.

[0315] As the organic compound (host material, assist material) used in the light-emitting layer 723, a substance having an energy gap larger than the energy gap of the light-emitting substance (guest material) may be selected and used singly or in combination of two or more. Note that the above-described hole-transporting material and the electron-transporting material described later can also be used as the host material or the assist material, respectively.

[0316] When the light-emitting substance is a fluorescent material, it is preferable to use an organic compound having a large energy level of the singlet excited state and a small energy level of the triplet excited state as the host material. For example, it is preferable to use an anthracene derivative or a tetracene derivative. Specifically, 9-phenyl-3-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: PCzPA), 3-[4-(1-naphthyl)-phenyl]-9-phenyl-9H-carbazole (abbreviation: PCPN), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 7-[4-(10-phenyl-9-anthryl)phenyl]-7H-dibenzo[c,g]carbazole (abbreviation: cgDBCzPA), 6-[3-(9,10-diphenyl-2-anthryl)phenyl]-benzo[b]naphtho[1,2-d]furan (abbreviation: 2mBnfPPA), 9-phenyl-10-{4-(9-phenyl-9H-fluoren-9-yl)biphenyl-4'-yl}anthracene (abbreviation: FLPPA), 5,12-diphenyltetracene, 5,12-bis(biphenyl-2-yl)tetracene, etc. can be mentioned.

[0317] When the luminescent substance is a phosphorescent material, as the host material, an organic compound having a triplet excitation energy greater than the triplet excitation energy of the luminescent substance (the energy difference between the ground state and the triplet excited state) may be selected. In this case, in addition to zinc and aluminum-based metal complexes, oxadiazole derivatives, triazole derivatives, benzimidazole derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, pyrimidine derivatives, triazine derivatives, pyridine derivatives, bipyridine derivatives, phenanthroline derivatives, etc., aromatic amines, carbazole derivatives, etc. can also be used.

[0318] Specifically, metal complexes such as tris(8-quinolinolato)aluminum(III) (abbreviation: Alq), tris(4-methyl-8-quinolinolato)aluminum(III) (abbreviation: Almq3), bis(10-hydroxybenzo[h]quinolinato)beryllium(II) (abbreviation: BeBq2), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum(III) (abbreviation: BAlq), bis(8-quinolinolato)zinc(II) (abbreviation: Znq), bis[2-(2-benzoxazolyl)phenolato]zinc(II) (abbreviation: ZnPBO), bis[2-(2-benzothiazolyl)phenolato]zinc(II) (abbreviation: ZnBTZ), heterocyclic compounds such as 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD-7), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butylphenyl)-1,2,4-triazole (abbreviation: TAZ), 2,2’,2’’-(1,3,5-benzenetriyl)-tris(1-phenyl-1H-benzimidazole) (abbreviation: TPBI), bathophenanthroline (abbreviation: BPhen), bathocuproine (abbreviation: BCP), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBphen), 9-[4-(5-phenyl-1,3,4-oxadiazol-2-yl)phenyl]-9H-carbazole (abbreviation: CO11), and aromatic amine compounds such as NPB, TPD, and BSPB can be mentioned.

[0319] In addition, condensed polycyclic aromatic compounds such as anthracene derivatives, phenanthrene derivatives, pyrene derivatives, chrysene derivatives, dibenzo[g,p]chrysene derivatives, etc. can be mentioned. Specifically, 9,10-diphenylanthracene (abbreviation: DPAnth), N,N-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole-3-amine (abbreviation: CzA1PA), 4-(10-phenyl-9-anthryl)triphenylamine (abbreviation: DPhPA), YGAPA, PCAPA, N,9-diphenyl-N-{4-[4-(10-phenyl-9-anthryl)phenyl]phenyl}-9H-carbazole-3-amine (abbreviation: PCAPBA), 9,10-diphenyl-2-[N-phenyl-N-(9-phenyl-9H-carbazole-3-yl)amino]anthracene (abbreviation: 2PCAPA), 6,12-dimethoxy-5,11-diphenylchrysene, N,N,N’,N’,N’’,N’’,N’’’,N’’’-octaphenyldibenzo[g,p]chrysene-2,7,10,15-tetraamine (abbreviation: DBC1), 9-[4-(10-phenyl-9-anthracenyl)phenyl]-9H-carbazole (abbreviation: CzPA), 3,6-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: DPCzPA), 9,10-bis(3,5-diphenylphenyl)anthracene (abbreviation: DPPA), 9,10-di(2-naphthyl)anthracene (abbreviation: DNA), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA), 9,9’-bianthryl (abbreviation: BANT), 9,9’-(stilbene-3,3’-diyl)diphenanthrene (abbreviation: DPNS), 9,9’-(stilbene-4,4’-diyl)diphenanthrene (abbreviation: DPNS2), 1,3,5-tri(1-pyrenyl)benzene (abbreviation: TPB3), etc. can be used.

[0320] Also, when using a plurality of organic compounds in the light-emitting layer 723, it is preferable to mix and use a compound that forms an exciplex with a light-emitting substance. In this case, various organic compounds can be used in appropriate combinations. However, in order to efficiently form an exciplex, it is particularly preferable to combine a compound that easily receives holes (hole-transporting material) and a compound that easily receives electrons (electron-transporting material). Specific examples of the hole-transporting material and the electron-transporting material can be the materials shown in this embodiment mode.

[0321] A TADF material is a material that can up-convert (reverse intersystem crossing) from a triplet excited state to a singlet excited state by a small amount of thermal energy and efficiently exhibits light emission (fluorescence) from the singlet excited state. Further, as conditions for efficiently obtaining thermally activated delayed fluorescence, the energy difference between the triplet excitation level and the singlet excitation level is 0 eV or more and 0.2 eV or less, preferably 0 eV or more and 0.1 eV or less. Also, the delayed fluorescence in a TADF material refers to light emission that has a spectrum similar to that of normal fluorescence but has a significantly long lifetime. The lifetime is 10 -6 seconds or more, preferably 10 -3 seconds or more.

[0322] Examples of the TADF materials include fullerenes and their derivatives, acridine derivatives such as proflavine, eosin, etc. Further, metal-containing porphyrins containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), or palladium (Pd), etc. are also included. Examples of the metal-containing porphyrins include protoporphyrin-tin fluoride complex (SnF2(Proto IX)), mesoporphyrin-tin fluoride complex (SnF2(Meso IX)), hematoporphyrin-tin fluoride complex (SnF2(Hemato IX)), coproporphyrin tetramethyl ester-tin fluoride complex (SnF2(Copro III-4Me)), octaethylporphyrin-tin fluoride complex (SnF2(OEP)), etioporphyrin-tin fluoride complex (SnF2(Etio I)), octaethylporphyrin-platinum chloride complex (PtCl2OEP), etc.

[0323] In addition, heterocyclic compounds having a π-electron-excessive heteroaromatic ring and a π-electron-deficient heteroaromatic ring such as 2-(biphenyl-4-yl)-4,6-bis(12-phenylindolo[2,3-a]carbazol-11-yl)-1,3,5-triazine (PIC-TRZ), 2-{4-[3-(N-phenyl-9H-carbazol-3-yl)-9H-carbazol-9-yl]phenyl}-4,6-diphenyl-1,3,5-triazine (PCCzPTzn), 2-[4-(10H-phenoxazin-10-yl)phenyl]-4,6-diphenyl-1,3,5-triazine (PXZ-TRZ), 3-[4-(5-phenyl-5,10-dihydrophenazin-10-yl)phenyl]-4,5-diphenyl-1,2,4-triazole (PPZ-3TPT), 3-(9,9-dimethyl-9H-acridin-10-yl)-9H-xanthen-9-one (ACRXTN), bis[4-(9,9-dimethyl-9,10-dihydroacridine)phenyl]sulfone (DMAC-DPS), 10-phenyl-10H,10’H-spiro[acridine-9,9’-anthracene]-10’-one (ACRSA), etc. can be used. Note that a substance in which a π-electron-excessive heteroaromatic ring and a π-electron-deficient heteroaromatic ring are directly bonded is particularly preferable because the donor property of the π-electron-excessive heteroaromatic ring and the acceptor property of the π-electron-deficient heteroaromatic ring both become strong, and the energy difference between the singlet excited state and the triplet excited state becomes small.

[0324] In addition, when using a TADF material, it can also be used in combination with other organic compounds.

[0325] <<Electron transport layer 724>> The electron transport layer 724 is a layer that transports electrons injected from the conductor 788 to the light-emitting layer 723 by the electron injection layer 725. Note that the electron transport layer 724 is a layer containing an electron-transporting material. The electron-transporting material used for the electron transport layer 724 preferably has an electron mobility of 1×10 -6 cm 2 / Vs or more. Note that other substances can be used as long as they have higher electron transportability than holes.

[0326] Examples of the electron transporting material include metal complexes having a quinoline ligand, a benzoquinoline ligand, an oxazole ligand, or a thiazole ligand, oxadiazole derivatives, triazole derivatives, phenanthroline derivatives, pyridine derivatives, bipyridine derivatives, and the like. In addition, π-electron deficient heteroaromatic compounds such as nitrogen-containing heteroaromatic compounds can also be used.

[0327] Specifically, metal complexes such as Alq3, tris(4-methyl-8-quinolinolato)aluminum(III) (abbreviation: Almq3), bis(10-hydroxybenzo[h]quinolinato)beryllium (abbreviation: BeBq2), BAlq, Zn(BOX)2, bis[2-(2-hydroxyphenyl)benzothiazolato]zinc(II) (abbreviation: Zn(BTZ)2), etc., 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD-7), 3-(4’-tert-butylphenyl)-4-phenyl-5-(4’’-biphenyl)-1,2,4-triazole (abbreviation: TAZ), 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: Bphen), bathocuproine (abbreviation: BCP), 4,4’-bis(5-methylbenzoxazol-2-yl)stilbene (abbreviation: BzOs) and other heteroaromatic compounds, 2-[3-(dibenzothiophen-4-yl)phenyl]dibenz[f,h]quinoxaline (abbreviation: 2mDBTPDBq-II), 2-[3’-(dibenzothiophen-4-yl)biphenyl-3-yl]dibenz[f,h]quinoxaline (abbreviation: 2mDBTBPDBq-II), 2-[4-(3,6-diphenyl-9H-carbazol-9-yl)phenyl]dibenz[f,h]quinoxaline (abbreviation: 2CzPDBq-III), 7-[3-(dibenzothiophen-4-yl)phenyl]dibenz[f,h]quinoxaline (abbreviation: 7mDBTPDBq-II), 6-[3-(dibenzothiophen-4-yl)phenyl]dibenz[f,h]quinoxaline (abbreviation: 6mDBTPDBq-II) and other quinoxaline or dibenzoquinoxaline derivatives can be used.

[0328] In addition, high-molecular compounds such as poly(2,5-pyridinediyl) (abbreviation: PPy), poly[(9,9-dihexylfluorene-2,7-diyl)-co-(pyridine-3,5-diyl)] (abbreviation: PF-Py), and poly[(9,9-dioctylfluorene-2,7-diyl)-co-(2,2'-bipyridine-6,6'-diyl)] (abbreviation: PF-BPy) can also be used.

[0329] In addition, the electron transport layer 724 may be not only a single layer but also a structure in which two or more layers made of the above substances are laminated.

[0330] <<Electron injection layer 725>> The electron injection layer 725 is a layer containing a substance with high electron injection properties. In the electron injection layer 725, alkali metals, alkaline earth metals, or their compounds such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), lithium oxide (LiO x ) etc. can be used. In addition, rare earth metal compounds such as erbium fluoride (ErF3) can be used. Also, electride may be used for the electron injection layer 725. Examples of electride include substances obtained by adding electrons at a high concentration to a mixed oxide of calcium and aluminum. Note that the substances constituting the above-described electron transport layer 724 can also be used.

[0331] Alternatively, a composite material formed by mixing an organic compound and an electron donor may be used for the electron injection layer 725. Since electrons are generated in the organic compound by the electron donor in such a composite material, it is excellent in electron injection property and electron transport property. In this case, the organic compound is preferably a material excellent in transporting the generated electrons. Specifically, for example, the electron transport materials (such as metal complexes and heteroaromatic compounds) used for the above-described electron transport layer 724 can be used. Any substance that exhibits electron-donating properties with respect to the organic compound may be used as the electron donor. Specifically, an alkali metal, an alkaline earth metal, or a rare earth metal is preferable, and examples include lithium, cesium, magnesium, calcium, erbium, ytterbium, etc. Also, an alkali metal oxide or an alkaline earth metal oxide is preferable, and examples include lithium oxide, calcium oxide, barium oxide, etc. Also, a Lewis base such as magnesium oxide can be used. Also, an organic compound such as tetrathiafulvalene (abbreviation: TTF) can be used.

[0332] <<Charge generation layer 792>> When a voltage is applied between the conductor 772 and the conductor 788, the charge generation layer 792 has a function of injecting electrons into the EL layer 786 closer to the conductor 772 and injecting holes into the EL layer 786 closer to the conductor 788 among the two EL layers 786 in contact with the charge generation layer 792. For example, in the light-emitting element 572 having the configuration shown in FIG. 27C, the charge generation layer 792 has a function of injecting electrons into the EL layer 786a and injecting holes into the EL layer 786b. Note that the charge generation layer 792 may have a configuration in which an electron acceptor is added to a hole transport material, or a configuration in which an electron donor is added to an electron transport material. Also, both of these configurations may be laminated. By forming the charge generation layer 792 using the above-described materials, an increase in the driving voltage of the display device 10 when the EL layers are laminated can be suppressed.

[0333] In the charge generation layer 792, when the configuration is such that an electron acceptor is added to the hole transporting material, examples of the electron acceptor include 7,7,8,8 - tetracyano - 2,3,5,6 - tetrafluoroquinodimethane (abbreviation: F4 - TCNQ), chloranil, etc. Also, metal oxides belonging to Groups 4 to 8 in the periodic table of elements can be mentioned. Specifically, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, rhenium oxide, etc. can be mentioned.

[0334] In the charge generation layer 792, when the configuration is such that an electron donor is added to the electron transporting material, as the electron donor, an alkali metal, an alkaline earth metal, a rare earth metal, a metal belonging to Groups 2 and 13 in the periodic table of elements, and their oxides and carbonates can be used. Specifically, it is preferable to use lithium (Li), cesium (Cs), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium oxide, cesium carbonate, etc. Also, an organic compound such as tetrathianaphthacene may be used as the electron donor.

[0335] In addition, for the fabrication of the light - emitting element 572, a vacuum process such as a vapor deposition method or a solution process such as a spin - coating method or an ink - jet method can be used. When using the vapor deposition method, a physical vapor deposition method (PVD method) such as a sputtering method, an ion plating method, an ion beam vapor deposition method, a molecular beam vapor deposition method, a vacuum vapor deposition method, etc., or a chemical vapor deposition method (CVD method) can be used. In particular, for the functional layers (hole injection layer, hole transport layer, light - emitting layer, electron transport layer, electron injection layer) and the charge generation layer included in the EL layer of the light - emitting element, they can be formed by methods such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (dip - coating method, die - coating method, bar - coating method, spin - coating method, spray - coating method, etc.), a printing method (ink - jet method, screen (stencil printing) method, offset (lithographic printing) method, flexo (letterpress printing) method, gravure method, micro - contact method, etc.).

[0336] In addition, each functional layer (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer) and charge generation layer that constitute the EL layer of the light-emitting element shown in this embodiment are not limited to the materials described above, and other materials can be used in combination as long as they can satisfy the functions of each layer. As an example, a polymer compound (oligomer, dendrimer, polymer, etc.), a medium molecule compound (a compound in the intermediate region between low molecules and high molecules: molecular weight 400 to 4000), an inorganic compound (quantum dot material, etc.) can be used. As the quantum dot material, a colloidal quantum dot material, an alloy-type quantum dot material, a core-shell type quantum dot material, a core-type quantum dot material, etc. can be used.

[0337] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other configuration examples, or drawings, etc.

[0338] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0339] (Embodiment 2) In this embodiment, a transistor that can be used in a display device, which is one aspect of the present invention, will be described.

[0340] <Configuration Example 1 of Transistor> FIGS. 28A, 28B, and 28C are top views and cross-sectional views of a transistor 200A that can be used in a display device, which is one aspect of the present invention, and the periphery of the transistor 200A. The transistor 200A can be applied to a display device of one aspect of the present invention.

[0341] FIG. 28A is a top view of transistor 200A. FIGS. 28B and 28C are cross-sectional views of transistor 200A. Here, FIG. 28B is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 28A, and is also a cross-sectional view in the channel length direction of transistor 200A. Further, FIG. 28C is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 28A, and is also a cross-sectional view in the channel width direction of transistor 200A. Note that in the top view of FIG. 28A, some elements are omitted for clarity of the drawing.

[0342] As shown in FIG. 28, transistor 200A includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, conductors 242a and 242b disposed separately from each other on the metal oxide 230b, an insulator 280 disposed on the conductors 242a and 242b with an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed between the metal oxide 230b, the conductors 242a, 242b, and the insulator 280, and the conductor 260, and a metal oxide 230c disposed between the metal oxide 230b, the conductors 242a, 242b, and the insulator 280, and the insulator 250. Here, as shown in FIGS. 28B and 28C, it is preferable that the upper surface of the conductor 260 substantially coincides with the upper surfaces of the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280. In the following, the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may be collectively referred to as the metal oxide 230. Also, the conductors 242a and 242b may be collectively referred to as the conductor 242.

[0343] In the transistor 200A shown in FIG. 28, the side surfaces of the conductor 242a and the conductor 242b on the side of the conductor 260 have a substantially perpendicular shape. Note that the transistor 200A shown in FIG. 28 is not limited to this, and the angle formed by the side surface and the bottom surface of the conductor 242a and the conductor 242b may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Further, the opposing side surfaces of the conductor 242a and the conductor 242b may have a plurality of surfaces.

[0344] Further, as shown in FIG. 28, it is preferable that an insulator 254 is disposed between the insulator 224, the metal oxides 230a, 230b, the conductors 242a, 242b, and the metal oxide 230c, and the insulator 280. Here, as shown in FIGS. 28B and 28C, the insulator 254 preferably contacts the side surface of the metal oxide 230c, the upper surface and the side surface of the conductor 242a, the upper surface and the side surface of the conductor 242b, the side surfaces of the metal oxides 230a and 230b, and the upper surface of the insulator 224.

[0345] In the transistor 200A, a configuration in which three layers of the metal oxides 230a, 230b, and 230c are laminated in the region where the channel is formed (hereinafter, also referred to as the channel formation region) and in the vicinity thereof is shown, but the present invention is not limited to this. For example, a two-layer structure of the metal oxides 230b and 230c or a laminated structure of four or more layers may be provided. In the transistor 200A, the conductor 260 is shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. Further, each of the metal oxides 230a, 230b, and 230c may have a laminated structure of two or more layers.

[0346] For example, when the metal oxide 230c has a laminated structure composed of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide preferably has the same composition as the metal oxide 230b, and the second metal oxide preferably has the same composition as the metal oxide 230a.

[0347] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode or the drain electrode, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductor 260, the conductor 242a, and the conductor 242b is self-alignedly selected with respect to the opening of the insulator 280. That is, in the transistor 200A, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing an alignment margin, the occupied area of the transistor 200A can be reduced. Thereby, the pixel density of the display device can be increased. Also, the display device can have a narrow bezel.

[0348] Also, as shown in FIG. 28, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0349] Also, the transistor 200A preferably has an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. It is preferable that a metal oxide 230a is disposed on the insulator 224.

[0350] Also, it is preferable that an insulator 274 functioning as an interlayer film and an insulator 281 are disposed on the transistor 200A. Here, the insulator 274 is preferably disposed in contact with the upper surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

[0351] The insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 222, the insulator 254, and the insulator 274 preferably have lower hydrogen permeability than the insulator 224, the insulator 250, and the insulator 280. Further, the insulator 222 and the insulator 254 preferably have a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 and the insulator 254 preferably have lower oxygen permeability than the insulator 224, the insulator 250, and the insulator 280.

[0352] Here, the insulator 224, the metal oxide 230, and the insulator 250 are separated from the insulator 280 and the insulator 281 by the insulator 254 and the insulator 274. Therefore, it is possible to suppress the mixing of impurities such as hydrogen and excessive oxygen contained in the insulator 280 and the insulator 281 into the insulator 224, the metal oxide 230, and the insulator 250.

[0353] Further, it is preferable to provide a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200A and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. That is, the insulator 241 is provided in contact with the inner wall of the openings of the insulator 254, the insulator 280, the insulator 274, and the insulator 281. Further, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. Note that in the transistor 200A, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited thereto. For example, the conductor 240 may be provided in a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned in the formation order for distinction.

[0354] In addition, for the transistor 200A, it is preferable to use, as the metal oxide 230 (metal oxides 230a, 230b, and 230c) including a channel formation region, a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). For example, as the metal oxide serving as the channel formation region of the metal oxide 230, those having a band gap of 2 eV or more, preferably 2.5 eV or more are preferably used.

[0355] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it preferably contains indium (In) and zinc (Zn). In addition to these, it is preferable that an element M is contained. The element M can be one or more selected from aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), cobalt (Co), etc. In particular, the element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn).

[0356] In addition, as shown in FIG. 28B, the film thickness of the region where the metal oxide 230b does not overlap with the conductor 242 may be thinner than the film thickness of the region where the metal oxide 230b overlaps with the conductor 242. This is formed by removing a part of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film serving as the conductor 242 is formed on the upper surface of the metal oxide 230b, a region with low resistance may be formed in the vicinity of the interface with the conductive film. In this way, by removing the region with low resistance located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent a channel from being formed in the region.

[0357] According to one aspect of the present invention, a display device having a small-sized transistor and a high pixel density can be provided. Alternatively, a display device having a transistor with a large on-current and a high luminance can be provided. Alternatively, a display device having a fast-operating transistor and a fast-operating display device can be provided. Alternatively, a display device having a transistor with stable electrical characteristics and a high reliability can be provided. Alternatively, a display device having a transistor with a small off-current and a low power consumption can be provided.

[0358] A detailed configuration of the transistor 200A that can be used in the display device according to one aspect of the present invention will be described.

[0359] The conductor 205 is arranged so as to have an overlapping region with the metal oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided by being embedded in the insulator 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Thereby, the flatness of the insulator 224 formed on the conductor 205 can be improved, and the crystallinity of the metal oxides 230b and 230c can be improved.

[0360] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the V th of the transistor 200A can be controlled. In particular, by applying a negative potential to the conductor 205, the V th of the transistor 200A can be made larger than 0 V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when no potential is applied.

[0361] Also, the conductor 205 may be provided to be larger than the channel formation region in the metal oxide 230. In particular, as shown in FIG. 28C, it is preferable that the conductor 205 extends also in a region outside the end portion intersecting the channel width direction of the metal oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap via an insulator outside the side surface in the channel width direction of the metal oxide 230.

[0362] By having the above configuration, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 having the function as the first gate electrode and the electric field of the conductor 205 having the function as the second gate electrode.

[0363] Also, as shown in FIG. 28C, the conductor 205 is extended to function also as a wiring. However, it is not limited thereto, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 205.

[0364] Also, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205. Although the conductor 205 is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above conductive material.

[0365] Also, a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate) may be used under the conductor 205. Alternatively, it is preferable to use a conductor having a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). In the present specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0366] By using a conductor having a function of suppressing oxygen diffusion under the conductor 205, it is possible to suppress the oxidation of the conductor 205 and the decrease in conductivity. As the conductor having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, as the conductor 205, the above conductive material may be used as a single layer or a laminate.

[0367] The insulator 214 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200A from the substrate side. Therefore, the insulator 214 preferably uses an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0368] For example, as the insulator 214, it is preferable to use aluminum oxide, silicon nitride, or the like. Thereby, it is possible to suppress the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200A side rather than the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side rather than the insulator 214.

[0369] In addition, the insulators 216, 280, and 281 that function as interlayer films preferably have a lower relative dielectric constant than the insulator 214. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 280, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide having pores may be appropriately used.

[0370] The insulators 222 and 224 have a function as a gate insulator.

[0371] Here, the insulator 224 in contact with the metal oxide 230 preferably desorbs oxygen upon heating. In this specification, the oxygen desorbed upon heating may be referred to as excess oxygen. For example, the insulator 224 may be appropriately silicon oxide, silicon oxynitride, or the like. By providing an oxygen-containing insulator in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, and the reliability of the transistor 200A can be improved.

[0372] Specifically, as the insulator 224, it is preferable to use an oxide material in which a part of oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating means that, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0373] Also, as shown in FIG. 28C, the film thickness of the region where the insulator 224 does not overlap with the insulator 254 and does not overlap with the metal oxide 230b may be thinner than the film thickness of the other regions. In the insulator 224, the film thickness of the region where it does not overlap with the insulator 254 and does not overlap with the metal oxide 230b is preferably a film thickness that allows sufficient diffusion of the above oxygen.

[0374] The insulator 222 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen into the transistor 200A from the substrate side, similar to the insulator 214 and the like. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, etc. with the insulator 222, the insulator 254, and the insulator 274, it is possible to suppress the entry of impurities such as water or hydrogen from the outside into the transistor 200A.

[0375] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen and impurities because it can reduce the diffusion of the oxygen possessed by the metal oxide 230 to the substrate side. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen possessed by the insulator 224 and the metal oxide 230.

[0376] As the insulator 222, an insulator containing one or both of the oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator containing one or both of the oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 230 and the entry of impurities such as hydrogen from the peripheral portion of the transistor 200A into the metal oxide 230.

[0377] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators and used.

[0378] Further, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0379] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. For example, a structure may be adopted in which an insulator similar to the insulator 224 is provided under the insulator 222.

[0380] The metal oxide 230 has a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By having the metal oxide 230a under the metal oxide 230b, the diffusion of impurities from the structure formed below the metal oxide 230a to the metal oxide 230b can be suppressed. Also, by having the metal oxide 230c on the metal oxide 230b, the diffusion of impurities from the structure formed above the metal oxide 230c to the metal oxide 230b can be suppressed.

[0381] Note that the metal oxide 230 preferably has a laminated structure of a plurality of oxide layers with different atomic number ratios of each metal atom. For example, when the metal oxide 230 contains at least indium (In) and element M, the ratio of the number of atoms of element M contained in the metal oxide 230a to the total number of atoms of all elements constituting the metal oxide 230a is preferably higher than the ratio of the number of atoms of element M contained in the metal oxide 230b to the total number of atoms of all elements constituting the metal oxide 230b. Further, the atomic number ratio of element M contained in the metal oxide 230a to In is preferably larger than the atomic number ratio of element M contained in the metal oxide 230b to In. Here, the metal oxide 230c can be a metal oxide that can be used for the metal oxide 230a or the metal oxide 230b.

[0382] Further, it is preferable that the energy of the lower end of the conduction band of the metal oxide 230a and the metal oxide 230c is higher than the energy of the lower end of the conduction band of the metal oxide 230b. In other words, it is preferable that the electron affinity of the metal oxide 230a and the metal oxide 230c is smaller than the electron affinity of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, the ratio of the number of atoms of element M contained in the metal oxide 230c to the total number of atoms of all elements constituting the metal oxide 230c is preferably higher than the ratio of the number of atoms of element M contained in the metal oxide 230b to the total number of atoms of all elements constituting the metal oxide 230b. Further, the atomic number ratio of element M contained in the metal oxide 230c to In is preferably larger than the atomic number ratio of element M contained in the metal oxide 230b to In.

[0383] Here, at the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c changes continuously or is continuously junctioned. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c.

[0384] Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c have a common element other than oxygen (as a main component), so that a mixed layer with a low defect level density can be formed. For example, when the metal oxide 230b is an In-Ga-Zn oxide, the metal oxide 230a and the metal oxide 230c may be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like. The metal oxide 230c may also have a laminated structure. For example, a laminated structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a laminated structure of In-Ga-Zn oxide and an oxide not containing In may be used as the metal oxide 230c.

[0385] Specifically, as the metal oxide 230a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. Further, as the metal oxide 230b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. Further, as the metal oxide 230c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Further, as a specific example of the case where the metal oxide 230c has a stacked structure, examples include a stacked structure of In:Ga:Zn = 4:2:3 and Ga:Zn = 2:1, a stacked structure of In:Ga:Zn = 4:2:3 and Ga:Zn = 2:5, a stacked structure of In:Ga:Zn = 4:2:3 and gallium oxide, etc.

[0386] At this time, the main path of the carriers becomes the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the density of defect levels at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be lowered. Therefore, the influence of carrier conduction due to interface scattering is reduced, and the transistor 200A can obtain a high on-current and high frequency characteristics. When the metal oxide 230c has a stacked structure, in addition to the effect of lowering the density of defect levels at the interface between the metal oxide 230b and the metal oxide 230c described above, it is expected to suppress the diffusion of the constituent elements of the metal oxide 230c toward the insulator 250 side. More specifically, since the metal oxide 230c has a stacked structure and an oxide containing no In is positioned above the stacked structure, In that may diffuse toward the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, if In diffuses, the characteristics of the transistor deteriorate. Therefore, by forming the metal oxide 230c into a stacked structure, it becomes possible to provide a highly reliable display device.

[0387] On the metal oxide 230b, conductors 242 (conductor 242a and conductor 242b) that function as source and drain electrodes are provided. As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0388] By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration may be reduced in the vicinity of the conductor 242 of the metal oxide 230. Further, in the vicinity of the conductor 242 of the metal oxide 230, a metal compound layer containing the metal contained in the conductor 242 and the components of the metal oxide 230 may be formed. In such a case, in the region near the conductor 242 of the metal oxide 230, the carrier density increases, and the region becomes a low-resistance region.

[0389] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. Thereby, the conductor 260 can be self-alignedly disposed between the conductor 242a and the conductor 242b.

[0390] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0391] Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0392] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. Thereby, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0393] Also, the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, etc. are used for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure which is stable against heat and has a high relative permittivity can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0394] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing one or both of aluminum and hafnium oxides.

[0395] Although the conductor 260 is shown as a two-layer structure in FIG. 28, it may have a single-layer structure or a laminated structure of three or more layers.

[0396] For the conductor 260a, it is preferable to use a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms as described above. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.).

[0397] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by oxygen contained in the insulator 250 and a decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0398] For the conductor 260b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0399] Also, as shown in FIGS. 28A and 28C, in a region that does not overlap with the conductor 242 of the metal oxide 230b, in other words, in the channel formation region of the metal oxide 230, the side surfaces of the metal oxide 230 are arranged to be covered by the conductor 260. Thereby, the electric field of the conductor 260 having the function as the first gate electrode can be easily applied to the side surfaces of the metal oxide 230. Therefore, the on-current of the transistor 200A can be increased, and the frequency characteristics can be improved.

[0400] The insulator 254 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200A from the insulator 280 side, similar to the insulator 214 and the like. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Further, as shown in FIGS. 28B and 28C, the insulator 254 preferably contacts the side surfaces of the metal oxide 230c, the upper and side surfaces of the conductor 242a, the upper and side surfaces of the conductor 242b, the side surfaces of the metal oxides 230a and 230b, and the upper surface of the insulator 224. By adopting such a configuration, it is possible to suppress hydrogen contained in the insulator 280 from entering the metal oxide 230 from the upper or side surfaces of the conductor 242a, the conductor 242b, the metal oxides 230a, 230b, and the insulator 224.

[0401] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate). For example, the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224.

[0402] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added in the vicinity of the region where the insulator 254 contacts the insulator 224. Thereby, oxygen can be supplied from the said area | region into the metal oxide 230 through the insulator 224. Here, since the insulator 254 has a function of suppressing the upward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the metal oxide 230 to the insulator 280. Further, since the insulator 222 has a function of suppressing the downward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the metal oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. Thereby, the oxygen deficiency of the metal oxide 230 can be reduced, and the normal ionization of the transistor can be suppressed.

[0403] As the insulator 254, for example, it is preferable to form an insulator containing one or both of oxides of aluminum and hafnium. Note that, as the insulator containing one or both of oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0404] By covering the insulator 224, the insulator 250, and the metal oxide 230 with the insulator 254 having a barrier property against hydrogen, the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. Thereby, since it can suppress that impurities, such as hydrogen, penetrate | invade from the exterior of the transistor 200A, favorable electrical characteristics and reliability can be given to the transistor 200A.

[0405] Insulator 280 is provided on insulator 224, metal oxide 230, and conductor 242 via insulator 254. For example, as insulator 280, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.

[0406] It is preferable that the concentration of impurities such as water or hydrogen in insulator 280 is reduced. Also, the upper surface of insulator 280 may be planarized.

[0407] Insulator 274 preferably functions as a barrier insulating film that suppresses the mixing of impurities such as water or hydrogen into insulator 280 from above, similar to insulator 214, etc. As insulator 274, for example, an insulator that can be used for insulator 214, insulator 254, etc. may be used.

[0408] Also, it is preferable to provide insulator 281 that functions as an interlayer film on insulator 274. Similar to insulator 224, etc., it is preferable that the concentration of impurities such as water or hydrogen in the film of insulator 281 is reduced.

[0409] Also, conductor 240a and conductor 240b are arranged in the openings formed in insulator 281, insulator 274, insulator 280, and insulator 254. Conductor 240a and conductor 240b are provided to face each other with conductor 260 interposed therebetween. Note that the height of the upper surfaces of conductor 240a and conductor 240b may be on the same plane as the upper surface of insulator 281.

[0410] In addition, an insulator 241a is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240a is formed in contact with its side surface. At least a part of the bottom of the opening is occupied by the conductor 242a, and the conductor 240a is in contact with the conductor 242a. Similarly, an insulator 241b is provided in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240b is formed in contact with its side surface. At least a part of the bottom of the opening is occupied by the conductor 242b, and the conductor 240b is in contact with the conductor 242b.

[0411] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 240a and the conductor 240b. Also, the conductor 240a and the conductor 240b may have a laminated structure.

[0412] When the conductor 240 has a laminated structure, for the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281, it is preferable to use a conductor having the function of suppressing the diffusion of impurities such as water or hydrogen as described above. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Also, the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or in a laminated form. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b. Also, it is possible to suppress impurities such as water or hydrogen from the upper layer of the insulator 281 from mixing into the metal oxide 230 through the conductor 240a and the conductor 240b.

[0413] As the insulators 241a and 241b, for example, insulators that can be used for the insulator 254 or the like may be used. Since the insulators 241a and 241b are provided in contact with the insulator 254, it is possible to suppress impurities such as water or hydrogen from the insulator 280 or the like from mixing into the metal oxide 230 through the conductors 240a and 240b. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0414] Also, although not shown, conductors that function as wiring may be arranged in contact with the upper surfaces of the conductor 240a and the conductor 240b. The conductor that functions as wiring is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

[0415] <Example Configuration 2 of Transistor> FIGS. 29A, 29B, and 29C are top views and cross-sectional views of the transistor 200B that can be used in a display device according to an aspect of the present invention and the periphery of the transistor 200B. The transistor 200B is a modified example of the transistor 200A.

[0416] FIG. 29A is a top view of the transistor 200B. FIGS. 29B and 29C are cross-sectional views of the transistor 200B. Here, FIG. 29B is a cross-sectional view of the portion indicated by the dashed-dotted line B1 - B2 in FIG. 29A and is also a cross-sectional view in the channel length direction of the transistor 200B. FIG. 29C is a cross-sectional view of the portion indicated by the dashed-dotted line B3 - B4 in FIG. 29A and is also a cross-sectional view in the channel width direction of the transistor 200B. In the top view of FIG. 29A, some elements are omitted for clarity of the drawing.

[0417] In the transistor 200B, the conductor 242a and the conductor 242b have a region overlapping with the metal oxide 230c, the insulator 250, and the conductor 260. Thereby, the transistor 200B can be a transistor with a high on-current. Also, the transistor 200B can be a transistor that is easy to control.

[0418] The conductor 260 functioning as a gate electrode has the conductor 260a and the conductor 260b on the conductor 260a. It is preferable to use a conductive material for the conductor 260a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.).

[0419] Since the conductor 260a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 260b can be improved. That is, by having the conductor 260a, oxidation of the conductor 260b can be suppressed, and a decrease in conductivity can be prevented.

[0420] Also, it is preferable to provide an insulator 254 so as to cover the upper surface and side surface of the conductor 260, the side surface of the insulator 250, and the side surface of the metal oxide 230c. Note that the insulator 254 may be made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0421] By providing the insulator 254, oxidation of the conductor 260 can be suppressed. Also, by having the insulator 254, diffusion of impurities such as water and hydrogen that the insulator 280 has into the transistor 200B can be suppressed.

[0422] <Configuration Example 3 of Transistor> FIGS. 30A, 30B, and 30C are top views and cross-sectional views of the transistor 200C that can be used in a display device according to an aspect of the present invention, and the periphery of the transistor 200C. The transistor 200C is a modified example of the transistor 200A.

[0423] FIG. 30A is a top view of transistor 200C. FIGS. 30B and 30C are cross-sectional views of transistor 200C. Here, FIG. 30B is a cross-sectional view of the portion indicated by the one-dot chain line C1-C2 in FIG. 30A, and is also a cross-sectional view in the channel length direction of transistor 200C. Further, FIG. 30C is a cross-sectional view of the portion indicated by the one-dot chain line C3-C4 in FIG. 30A, and is also a cross-sectional view in the channel width direction of transistor 200C. Note that in the top view of FIG. 30A, some elements are omitted for clarity of the drawing.

[0424] In transistor 200C, insulator 250 is provided on metal oxide 230c, and metal oxide 252 is provided on insulator 250. Further, conductor 260 is provided on metal oxide 252, and insulator 270 is provided on conductor 260. Also, insulator 271 is provided on insulator 270.

[0425] Metal oxide 252 preferably has a function of suppressing oxygen diffusion. By providing metal oxide 252 that suppresses oxygen diffusion between insulator 250 and conductor 260, diffusion of oxygen into conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to metal oxide 230. In addition, oxidation of conductor 260 by oxygen can be suppressed.

[0426] Note that metal oxide 252 may have a function as part of a gate electrode. For example, an oxide semiconductor that can be used as metal oxide 230 can be used as metal oxide 252. In that case, by forming conductor 260 by a sputtering method, the electrical resistance value of metal oxide 252 can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0427] In addition, the metal oxide 252 may function as part of the gate insulator. Therefore, when using silicon oxide, silicon oxynitride, etc. for the insulator 250, it is preferable to use a metal oxide, which is a high-k material with a high relative permittivity, as the metal oxide 252. By adopting such a stacked structure, a stacked structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Also, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulator.

[0428] In the transistor 200C, although the metal oxide 252 is shown as a single layer, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulator may be stacked and provided.

[0429] By having the metal oxide 252, when it functions as a gate electrode, it is possible to improve the on-current of the transistor 200C without weakening the influence of the electric field from the conductor 260. Or, when it functions as a gate insulator, by maintaining the distance between the conductor 260 and the metal oxide 230 due to the physical thicknesses of the insulator 250 and the metal oxide 252, it is possible to suppress the leakage current between the conductor 260 and the metal oxide 230. Therefore, by providing a stacked structure of the insulator 250 and the metal oxide 252, it is possible to easily adjust the physical distance between the conductor 260 and the metal oxide 230 and the electric field strength applied from the conductor 260 to the metal oxide 230.

[0430] Specifically, as the metal oxide 252, an oxide semiconductor with reduced resistance that can be used for the metal oxide 230 can be used. Or, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium, etc. can be used.

[0431] In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulating layers containing one or both of aluminum and hafnium oxides. In particular, hafnium aluminate has higher heat resistance than hafnium oxide. Therefore, it is preferable because it is less likely to crystallize during the heat treatment in the subsequent process. Note that the metal oxide 252 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0432] For the insulator 270, an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide or hafnium oxide, etc. Thereby, it is possible to suppress the oxidation of the conductor 260 by oxygen from above the insulator 270. Also, it is possible to suppress the mixing of impurities such as water or hydrogen from above the insulator 270 into the metal oxide 230 through the conductor 260 and the insulator 250.

[0433] The insulator 271 functions as a hard mask. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 can be made substantially perpendicular, specifically, the angle formed by the side surface of the conductor 260 and the substrate surface can be 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less.

[0434] Note that, by using an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen for the insulator 271, it may also function as a barrier layer. In that case, the insulator 270 may not be provided.

[0435] By selectively removing a part of the insulator 270, the conductor 260, the metal oxide 252, the insulator 250, and the metal oxide 230c using the insulator 271 as a hard mask, their side surfaces can be made substantially coincident, and a part of the surface of the metal oxide 230b can be exposed.

[0436] In addition, the transistor 200C has a region 243a and a region 243b on a part of the exposed surface of the metal oxide 230b. One of the region 243a or the region 243b functions as a source region, and the other of the region 243a or the region 243b functions as a drain region.

[0437] The formation of the region 243a and the region 243b can be realized, for example, by introducing impurity elements such as phosphorus or boron into the exposed surface of the metal oxide 230b using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment or the like. In the present embodiment and the like, the "impurity element" refers to an element other than the main component element.

[0438] Alternatively, after a part of the surface of the metal oxide 230b is exposed, a metal film is formed, and then heat treatment is performed to diffuse the elements contained in the metal film into the metal oxide 230b to form the region 243a and the region 243b.

[0439] In the region where the impurity element of the metal oxide 230b is introduced, the electrical resistivity decreases. Therefore, the region 243a and the region 243b may be referred to as an "impurity region" or a "low resistance region".

[0440] By using the insulator 271 and / or the conductor 260 as a mask, the region 243a and the region 243b can be formed in a self-aligned manner. Therefore, the region 243a and / or the region 243b do not overlap with the conductor 260, and the parasitic capacitance can be reduced. In addition, an offset region is not formed between the channel formation region and the source-drain region (the region 243a or the region 243b). By forming the region 243a and the region 243b in a self-aligned manner, an increase in the on-current, a reduction in the threshold voltage, an improvement in the operating frequency, etc. can be realized.

[0441] Transistor 200C has an insulator 272 on the side surfaces of an insulator 271, an insulator 270, a conductor 260, a metal oxide 252, an insulator 250, and a metal oxide 230c. The insulator 272 is preferably an insulator having a low relative permittivity. For example, it is preferably silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or a resin or the like. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having pores is used for the insulator 272, it is preferable because an excess oxygen region can be easily formed in the insulator 272 in a subsequent process. Further, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Further, the insulator 272 preferably has a function of diffusing oxygen.

[0442] Note that in order to further reduce the off-current, an offset region may be provided between the channel formation region and the source-drain region. The offset region is a region having a high electrical resistivity and is a region where the introduction of the above-described impurity elements is not performed. The formation of the offset region can be realized by introducing the above-described impurity elements after the formation of the insulator 272. In this case, the insulator 272 also functions as a mask in the same manner as the insulator 271 and the like. Therefore, impurity elements are not introduced into the region overlapping with the insulator 272 of the metal oxide 230b, and the electrical resistivity of the region can be kept high.

[0443] Further, the transistor 200C has an insulator 254 on the insulator 272 and the metal oxide 230. The insulator 254 is preferably formed by a sputtering method. By using the sputtering method, an insulator with few impurities such as water or hydrogen can be formed.

[0444] Note that an oxide film formed by the sputtering method may extract hydrogen from the film formation target structure. Therefore, by the insulator 254 absorbing hydrogen and water from the metal oxide 230 and the insulator 272, the hydrogen concentration of the metal oxide 230 and the insulator 272 can be reduced.

[0445] <Constituent Materials of Transistor> The constituent materials that can be used for transistors will be described.

[0446] <<Substrate>> As the substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, etc. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. Or, there are substrates having a metal nitride, substrates having a metal oxide, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulator substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, substrates in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, etc.

[0447] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0448] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0449] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0450] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resins.

[0451] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with insulators (such as insulator 214, insulator 222, insulator 254, and insulator 274, etc.) having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminate. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0452] In addition, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the metal oxide 230, the oxygen deficiency of the metal oxide 230 can be compensated.

[0453] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0454] In addition, a plurality of conductors formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen may be used. Further, a laminated structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0455] In the case of using a metal oxide in the channel formation region of the transistor, for the conductor functioning as the gate electrode, it is preferable to use a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

[0456] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0457] The configuration examples illustrated in the present embodiment, and the drawings corresponding thereto, etc. can be implemented by appropriately combining at least a part thereof with other configuration examples, drawings, etc.

[0458] The present embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0459] (Embodiment 3) In the present embodiment, a metal oxide (hereinafter, also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0460] <Classification of Crystal Structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 31A. FIG. 31A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0461] As shown in FIG. 31A, oxide semiconductors are roughly classified into "Amorphous (amorphous)", "Crystalline (crystalline)", and "Crystal (crystal)". Further, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, "Crystal" includes single crystal and poly crystal.

[0462] Note that the structure within the thick frame shown in FIG. 31A is an intermediate state between "Amorphous (amorphous)" and "Crystal (crystal)", and belongs to a new boundary region (New crystalline phase). That is, the structure can be paraphrased as a structure that is energetically unstable "Amorphous (amorphous)" and is completely different from "Crystal (crystal)".

[0463] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, FIG. 31B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 31B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 31B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Further, the thickness of the CAAC-IGZO film shown in FIG. 31B is 500 nm.

[0464] As shown in FIG. 31B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating clear crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in FIG. 31B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity is detected.

[0465] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 31C. FIG. 31C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 31C is near In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0466] As shown in FIG. 31C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0467] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 31A. For example, the oxide semiconductor can be divided into a single-crystal oxide semiconductor and other non-single-crystal oxide semiconductors. Examples of the non-single-crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. The non-single-crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0468] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0469] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are such that the c-axis is oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a location where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0470] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0471] Also, in an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0472] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type, composition, etc. of the metal elements constituting CAAC-OS.

[0473] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0474] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate the distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0475] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carriers being trapped. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0476] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when using CAAC-OS for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0477] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when performing a structural analysis on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when performing electron beam diffraction (also referred to as restricted-view electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on an nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0478] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared with the nc-OS and the CAAC-OS. Further, the a-like OS has a higher hydrogen concentration in the film compared with the nc-OS and the CAAC-OS.

[0479] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0480] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. Hereinafter, in the metal oxide, a state in which one or more metal elements are unevenly distributed and regions having the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0481] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is a configuration (hereinafter also referred to as a cloud state) distributed in the film. That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0482] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0483] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0484] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0485] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0486] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0487] Oxide semiconductors have various structures, each with different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0488] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0489] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0490] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor in some cases.

[0491] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0492] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0493] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0494] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0495] In an oxide semiconductor, when silicon or carbon, which is one of the group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0496] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0497] In the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0498] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen that binds to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bind to oxygen that binds to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0499] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0500] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0501] (Embodiment 4) In this embodiment, an electronic device including a display device, which is one aspect of the present invention, will be described.

[0502] FIG. 32A is a diagram showing the appearance of a camera 8000 with a viewfinder 8100 attached. The camera 8000 is provided with an imaging device. The camera 8000 can be, for example, a digital camera. In FIG. 32A, the camera 8000 and the viewfinder 8100 are shown as separate electronic devices with a detachable configuration, but a viewfinder including a display device may be built into the housing 8001 of the camera 8000.

[0503] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. A detachable lens 8006 is attached to the camera 8000.

[0504] Here, the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

[0505] The camera 8000 can take an image by pressing the shutter button 8004. Also, the display unit 8002 has a function as a touch panel, and it is also possible to take an image by touching the display unit 8002.

[0506] The housing 8001 of the camera 8000 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe device or the like can be connected.

[0507] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. The viewfinder 8100 can be an electronic viewfinder.

[0508] The housing 8101 has a mount that engages with the mount of the camera 8000, and the viewfinder 8100 can be attached to the camera 8000. Also, the mount has electrodes, and images or the like received from the camera 8000 via the electrodes can be displayed on the display unit 8102.

[0509] The button 8103 has a function as a power button. By operating the button 8103, the display on the display unit 8102 can be switched on and off.

[0510] The display device according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Since the display device according to an aspect of the present invention has an extremely high pixel density, even when the distance between the display unit 8002 or the display unit 8102 and the user is close, the user cannot visually recognize the pixels, and a more immersive image can be displayed on the display unit 8002 or the display unit 8102. In particular, since the image displayed on the display unit 8102 provided in the viewfinder 8100 is visually recognized by bringing the user's eye close to the eyepiece of the viewfinder 8100, the distance between the user and the display unit 8102 becomes very close. Therefore, it is particularly preferable to apply the display device according to an aspect of the present invention to the display unit 8102. When applying the display device according to an aspect of the present invention to the display unit 8102, the resolution of the image that can be displayed on the display unit 8102 can be 4K, 5K, or higher.

[0511] In addition, it is preferable that the resolution of the image that can be captured by the imaging device provided in the camera 8000 is equal to or higher than the resolution of the image that can be displayed on the display unit 8002 or the display unit 8102. For example, when an image with a resolution of 4K can be displayed on the display unit 8102, it is preferable to provide the camera 8000 with an imaging device that can capture an image with a resolution of 4K or higher. Also, for example, when an image with a resolution of 5K can be displayed on the display unit 8102, it is preferable to provide the camera 8000 with an imaging device that can capture an image with a resolution of 5K or higher.

[0512] FIG. 32B is a diagram showing the appearance of the head-mounted display 8200.

[0513] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, etc. A battery 8206 is built in the mounting portion 8201.

[0514] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 is equipped with a wireless receiver or the like, and can display an image corresponding to the received image data or the like on the display unit 8204. Also, the camera provided in the main body 8203 captures the movement of the user's eyeballs and eyelids, and calculates the coordinates of the user's line of sight based on that information, so that the user's line of sight can be used as an input means.

[0515] In addition, the wearing part 8201 may be provided with a plurality of electrodes at positions that touch the user. The main body 8203 may have a function of recognizing the user's line of sight by detecting the current flowing through the electrodes as the user's eyeballs move. Also, by detecting the current flowing through the electrodes, it may have a function of monitoring the user's pulse. Further, the wearing part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204. Also, it may detect the movement of the user's head or the like, and change the image displayed on the display unit 8204 according to the movement.

[0516] The display device according to an aspect of the present invention can be applied to the display unit 8204. As a result, the head-mounted display 8200 can be made to have a narrow bezel, and a high-quality image can be displayed on the display unit 8204, and an image with a high sense of presence can be displayed.

[0517] Figures 32C to 32E are diagrams showing the appearance of the head-mounted display 8300. The head-mounted display 8300 has a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0518] The user can visually recognize the display of the display unit 8302 through the lens 8305. It is preferable to arrange the display unit 8302 in a curved manner. By arranging the display unit 8302 in a curved manner, the user can feel a high sense of immersion. In the present embodiment, a configuration in which one display unit 8302 is provided is illustrated, but the present invention is not limited thereto. For example, a configuration in which two display units 8302 are provided may be adopted. In this case, if a configuration is adopted such that one display unit is arranged in front of one eye of the user, it is also possible to perform three-dimensional display using parallax and the like.

[0519] In addition, the display device according to an aspect of the present invention can be applied to the display unit 8302. Since the display device according to an aspect of the present invention has an extremely high pixel density, even when enlarged using the lens 8305 as shown in FIG. 32E, an image with a higher sense of immersion can be displayed without the user visually recognizing the pixels.

[0520] Next, an example of an electronic device different from the electronic device shown in FIGS. 32A to 32E is shown in FIGS. 33A to 33G.

[0521] The electronic device shown in FIGS. 33A to 33G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 9008, and the like.

[0522] The electronic devices shown in FIGS. 33A to 33G have various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. Note that the functions that the electronic devices shown in FIGS. 33A to 33G can have are not limited to these, and they can have various functions. Also, although not shown in FIGS. 33A to 33G, the electronic device may have a configuration with a plurality of display units. Further, a camera or the like may be provided in the electronic device, and it may have functions such as a function of taking a still image, a function of taking a moving image, a function of saving the taken image in a recording medium (external or built into the camera), a function of displaying the taken image on the display unit, etc.

[0523] Details of the electronic devices shown in FIGS. 33A to 33G will be described below.

[0524] FIG. 33A is a perspective view showing a television device 9100. The television device 9100 can incorporate a large screen display unit 9001, for example, 50 inches or more, or 100 inches or more.

[0525] The display device according to one aspect of the present invention can be applied to the display unit 9001 of the television device 9100. Thereby, the television device 9100 can be made to have a narrow bezel, and high-quality images can be displayed on the display unit 9001, and images with a high sense of presence can be displayed.

[0526] FIG. 33B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, or an information browsing device, etc. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Also, the portable information terminal 9101 can display characters and images on its multiple surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display unit 9001. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Note that as an example of the information 9051, there are displays for notifying incoming calls such as e-mails, SNS (Social Networking Service), and telephone calls, titles of e-mails, SNS, etc., sender names of e-mails, SNS, etc., date and time, time, remaining battery level, antenna reception strength, etc. Or, instead of the information 9051, operation buttons 9050, etc. may be displayed at the position where the information 9051 is displayed.

[0527] The display device according to one aspect of the present invention can be applied to the display unit 9001 included in the portable information terminal 9101. Thereby, the portable information terminal 9101 can be miniaturized, and high-quality images can be displayed on the display unit 9001, and images with a high sense of presence can be displayed.

[0528] FIG. 33C is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different surfaces. For example, the user of the portable information terminal 9102 can confirm the display (here, information 9053) in a state where the portable information terminal 9102 is stored in the breast pocket of a suit. Specifically, the telephone number or name of the caller of an incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can confirm the display and determine whether to answer the call without taking the portable information terminal 9102 out of the pocket.

[0529] The display device according to an aspect of the present invention can be applied to the display unit 9001 of the mobile information terminal 9102. As a result, the mobile information terminal 9102 can be miniaturized, and high-quality images can be displayed on the display unit 9001, and images with a high sense of presence can be displayed.

[0530] FIG. 33D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can execute various applications such as mobile phones, e-mails, text browsing and creation, music playback, Internet communication, and computer games. In addition, the display surface of the display unit 9001 is provided in a curved shape, and display can be performed along the curved display surface. Further, the mobile information terminal 9200 can execute short-range wireless communication conforming to a communication standard. For example, it is also possible to make a hands-free call by communicating with a wireless communication-capable headset. In addition, the mobile information terminal 9200 has a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply without using the connection terminal 9006.

[0531] The display device according to an aspect of the present invention can be applied to the display unit 9001 of the mobile information terminal 9200. As a result, the mobile information terminal 9200 can be made into a narrow bezel, and high-quality images can be displayed on the display unit 9001, and images with a high sense of presence can be displayed.

[0532] Figs. 33E to 33G are perspective views showing the foldable mobile information terminal 9201. Fig. 33E is a perspective view of the mobile information terminal 9201 in the unfolded state, Fig. 33F is a perspective view of the state in the middle of changing from one of the unfolded state or the folded state of the mobile information terminal 9201 to the other, and Fig. 33G is a perspective view of the mobile information terminal 9201 in the folded state. The mobile information terminal 9201 has excellent portability in the folded state and excellent display comprehensibility due to a seamless and wide display area in the unfolded state. The display unit 9001 included in the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the mobile information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0533] The display device according to an aspect of the present invention can be applied to the display unit 9001 included in the mobile information terminal 9201. Thereby, the mobile information terminal 9201 can be made to have a narrow bezel, and a high-quality image can be displayed on the display unit 9001, and an image with a high sense of presence can be displayed.

[0534] The configuration examples illustrated in the present embodiment, and the drawings and the like corresponding thereto can be implemented by appropriately combining at least a part thereof with other configuration examples, drawings, or the like.

[0535] The present embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

Explanation of Reference Numerals

[0536] 10: Display device, 20: Layer, 21: Gate driver circuit, 21a: Gate driver circuit, 21b: Gate driver circuit, 22: Data driver circuit, 22a: Data driver circuit, 22b: Data driver circuit, 23: Region, 23a: Region, 23b: Region, 23c: Region, 23d: Region, 30: Layer, 31: Wiring, 31a: Wiring, 31b...

Claims

1. A display device including a first layer, a second layer, and a third layer stacked together, the first layer includes a gate driver circuit, a data driver circuit, and a potential generating circuit; the second layer includes a demultiplexer circuit; the third layer has a display portion, The display unit has pixels arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit; an output terminal of the demultiplexer circuit is electrically connected to the pixel; the gate driver circuit has an area overlapping with the display unit, the data driver circuit has an area overlapping with the display unit, the first layer has, in a plan view, a first region, a second region, a third region, and a fourth region; the first region, the second region, the third region, and the fourth region are arranged in this order in a row direction or a column direction, a part of transistors constituting the gate driver circuit is disposed in the first region and the third region; a part of transistors constituting the data driver circuit is disposed in the second region and the fourth region; the data driver circuit includes a pass transistor logic circuit; the potential generating circuit and the pass transistor logic circuit constitute a D / A conversion circuit, the potential generating circuit is disposed in a region different from the data driver circuit; the number of the pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the pixels provided in the display unit; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the pass transistor logic circuits; the potential generating circuit has a function of generating a plurality of potentials having different magnitudes; The pass transistor logic circuit is a display device having a function of receiving image data and outputting one of the potentials generated by the potential generating circuit based on the digital value of the image data.

2. In claim 1, The demultiplexer circuit has an area overlapping with the pixel.

3. In claim 1 or 2, The number of the pass transistor logic circuits is equal to or less than half the number of columns of the pixels.

4. In any one of claims 1 to 3, The pixel includes a transistor having a metal oxide in a channel formation region, The metal oxide comprises In, an element M (M is Al, Ga, Y, or Sn), and Zn.

5. A display device including a first layer, a second layer, and a third layer stacked together, the first layer includes a gate driver circuit, a first data driver circuit, a second data driver circuit, a third data driver circuit, a fourth data driver circuit, a fifth data driver circuit, and a potential generating circuit; the second layer includes a first demultiplexer circuit, a second demultiplexer circuit, a third demultiplexer circuit, a fourth demultiplexer circuit, and a fifth demultiplexer circuit; the third layer has a first display portion, a second display portion, a third display portion, a fourth display portion, and a fifth display portion; The first display unit has first pixels arranged in a matrix, The second display unit has second pixels arranged in a matrix, The third display unit includes third pixels arranged in a matrix, The fourth display unit includes fourth pixels arranged in a matrix, The fifth display unit includes fifth pixels arranged in a matrix, an input terminal of the first demultiplexer circuit is electrically connected to the first data driver circuit; an input terminal of the second demultiplexer circuit is electrically connected to the second data driver circuit; an input terminal of the third demultiplexer circuit is electrically connected to the third data driver circuit; an input terminal of the fourth demultiplexer circuit is electrically connected to the fourth data driver circuit; an input terminal of the fifth demultiplexer circuit is electrically connected to the fifth data driver circuit; an output terminal of the first demultiplexer circuit electrically connected to the first pixel; an output terminal of the second demultiplexer circuit electrically connected to the second pixel; an output terminal of the third demultiplexer circuit electrically connected to the third pixel; an output terminal of the fourth demultiplexer circuit electrically connected to the fourth pixel; an output terminal of the fifth demultiplexer circuit electrically connected to the fifth pixel; the gate driver circuit has an area overlapping with the first pixel, the first data driver circuit has an area overlapping with the first display unit, the second data driver circuit has an area overlapping with the second display section, the third data driver circuit has an area overlapping with the third display section, the fourth data driver circuit has an area overlapping with the fourth display unit, the fifth data driver circuit has an area overlapping with the fifth display section, the first layer has, in a plan view, a first region, a second region, a third region, and a fourth region; the first region, the second region, the third region, and the fourth region are arranged in this order in a row direction or a column direction, a part of transistors constituting the gate driver circuit is disposed in the first region and the third region; a part of a transistor constituting the first data driver circuit is disposed in the second region and the fourth region; the first data driver circuit includes a first pass transistor logic circuit; the second data driver circuit includes a second pass transistor logic circuit; the third data driver circuit includes a third pass transistor logic circuit; the fourth data driver circuit includes a fourth pass transistor logic circuit; the fifth data driver circuit includes a fifth pass transistor logic circuit; the potential generating circuit, the first pass transistor logic circuit, the second pass transistor logic circuit, the third pass transistor logic circuit, the fourth pass transistor logic circuit, and the fifth pass transistor logic circuit constitute a D / A conversion circuit, the potential generating circuit is disposed in a region different from the first to fifth data driver circuits; the number of the first pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the first pixels provided in the first display unit; the number of the second pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the second pixels provided in the second display unit; the number of the third pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the third pixels provided in the third display unit; the number of the fourth pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the fourth pixels provided in the fourth display unit; the number of the fifth pass transistor logic circuits provided in the D / A conversion circuit is less than the number of columns of the fifth pixels provided in the fifth display unit; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the first pass transistor logic circuits; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the second pass transistor logic circuits; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the third pass transistor logic circuits; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the fourth pass transistor logic circuits; the number of the potential generating circuits provided in the D / A conversion circuit is less than the number of the fifth pass transistor logic circuits; the potential generating circuit has a function of generating a plurality of potentials having different magnitudes; The display device has a function in which the first to fifth pass transistor logic circuits receive image data and output one of the potentials generated by the potential generating circuit based on the digital value of the image data.

6. In claim 5, the first demultiplexer circuit has an area overlapping the first pixel; the second demultiplexer circuit has an area overlapping with the second pixel; the third demultiplexer circuit has an area overlapping with the third pixel; the fourth demultiplexer circuit has an area overlapping with the fourth pixel; The fifth demultiplexer circuit has an area overlapping with the fifth pixel.

7. In claim 5 or 6, the number of the first pass transistor logic circuits is equal to or less than half the number of columns of the first pixels; the number of the second pass transistor logic circuits is equal to or less than half the number of columns of the second pixels; the number of the third pass transistor logic circuits is equal to or less than half the number of columns of the third pixels; the number of the fourth pass transistor logic circuits is equal to or less than half the number of columns of the fourth pixels; A display device, wherein the number of the fifth pass transistor logic circuits is equal to or less than half the number of columns of the fifth pixels.

8. In any one of claims 5 to 7, the first to fifth pixels each include a transistor having a metal oxide in a channel formation region; The metal oxide comprises In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Images