Magnetic sensor device

Abstract

To provide a magnetic sensor device which allows sampling to be performed faster.SOLUTION: A magnetic sensor device 1 includes: a magnetism detection element 2; a conduction circuit 3 for periodically exciting the magnetic detection element 2; and a magnetism detection circuit 4 for receiving input of a detection signal S1 generated in the magnetic detection element 2 in association with periodic excitation. The magnetism detection circuit 4 includes: a plurality of sample hold circuits 41 electrically connected to the magnetism detection element 2 in parallel, the sample hold circuits 41 holding detection signals S1 at different excitation timings of the conduction circuit 3 and outputting the detection signals S1 as analog hold signals S2; and an AD converter circuit 42 for converting the hold signals S2 to digital signals.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a magnetic sensor device.

Background Art

[0002] A magnetic sensor device using a magnetic detection element generally includes a current-carrying circuit that excites the magnetic detection element, and a magnetic detection circuit to which a detection signal generated in the magnetic detection element due to the excitation is input. The magnetic detection circuit is configured to periodically sample at a predetermined timing synchronized with the energization timing of the magnetic detection element, and detect the strength of an external magnetic field to be measured.

[0003] Magnetic sensor devices have been studied for applications in various fields. For example, Patent Document 1 proposes a small sensor package mounted on an electronic device. This sensor package has two electronic component chips that can operate independently of each other as magnetic sensors, which are spaced apart on a substrate. The two electronic component chips each include a sensor element and an integrated circuit to which a signal from the sensor element is input. The two electronic component chips are electrically insulated from each other and are connected to separate power supplies. Further, terminals for each electronic component chip are collectively arranged on adjacent sides of the substrate so that conductors such as wires connected to each electronic component chip do not come into contact with each other.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, there has been a demand for speeding up magnetic detection by magnetic sensor devices. On the other hand, the sensor package disclosed in Patent Document 1 uses one of two electronic component chips as a spare, and attempts to improve the reliability of operation, for example, by operating it in case of failure, and does not address speeding up. Also, although it is conceivable to shorten the sampling interval by operating both of the two electronic component chips, if, for example, the number of electronic component chips is further increased in order to achieve further speeding up, the following problems occur. That is, not only are components corresponding to the number of electronic component chips required, but also the arrangement of terminals and conductors is restricted from the viewpoint of electrical insulation, making it easy for the device to become larger. Also, it becomes difficult to arrange the sensor elements of each electronic component chip in close proximity, and there is a risk that errors depending on the positions of the sensor elements are likely to occur.

[0006] The present invention has been made in view of such problems, and aims to provide a magnetic sensor device capable of speeding up sampling.

Means for Solving the Problems

[0007] In order to solve the above problems, a magnetic sensor device according to one aspect of the present disclosure includes: a magnetic detection element; a power supply circuit that periodically excites the magnetic detection element; a magnetic detection circuit into which a detection signal generated in the magnetic detection element accompanying the periodic excitation is input, the magnetic sensor device comprising: the magnetic detection circuit includes: a plurality of sample-and-hold circuits that are electrically connected in parallel to the magnetic detection element and hold the detection signals at different excitation timings by the power supply circuit and output them as analog hold signals; an AD conversion circuit that performs analog-to-digital conversion processing for converting the hold signal into a digital signal.

Effects of the Invention

[0008] In the magnetic sensor device with the above configuration, the magnetic detection element is periodically excited by an energization circuit, and accordingly, the detection signal generated in the magnetic detection element is periodically input to the magnetic detection circuit. Since the plurality of sample-and-hold circuits in the magnetic detection circuit can hold the detection signals at different excitation timings, it is possible to increase the sampling speed by adjusting the excitation period. The hold signals from the plurality of sample-and-hold circuits are output to the AD conversion circuit in a timely manner, subjected to analog-to-digital conversion processing, and output as digital signals. At this time, the timing of the analog-to-digital conversion processing can be arbitrarily set. For example, the processing period can be shortened by collectively processing the plurality of hold signals. As a result, it becomes possible to further shorten the excitation period, making it easier to increase the sampling speed.

[0009] As described above, according to the above aspect, it is possible to provide a magnetic sensor device capable of increasing the sampling speed.

Brief Description of the Drawings

[0010]

Figure 1

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[0011] Hereinafter, each embodiment will be specifically described with reference to the drawings.

[0012] Note that each of the embodiments described below shows inclusive or specific examples, and numerical values, shapes, components, arrangement positions of components, connection forms, etc. shown in the embodiments are merely examples and are not intended to limit the present disclosure. Also, among the components in the following embodiments, components not described in the independent claims indicating the most general concept shall be described as optional components.

[0013] In addition, the magnetic sensor device of the present disclosure will be described based on the embodiments, but the magnetic sensor device according to the present disclosure is not limited to the following embodiments. Modifications obtained by making various modifications that those skilled in the art can come up with without departing from the gist of the present disclosure to the following embodiments or the following embodiments, and various devices incorporating the magnetic sensor device according to the present disclosure are also included in the present disclosure.

[0014] (Embodiment 1) FIG. 1 is a block diagram showing the basic configuration of the magnetic sensor device 1 according to Embodiment 1. Also, FIG. 2 is a circuit diagram showing an example of a specific configuration of the magnetic sensor device 1.

[0015] [Basic Configuration of Magnetic Sensor Device 1] In FIG. 1, the magnetic sensor device 1 includes a magnetic detection element 2, an energization circuit 3, and a magnetic detection circuit 4. The magnetic sensor device 1 can further include a control circuit 5 and a signal processing circuit 6.

[0016] The energization circuit 3 periodically energizes the magnetic detection element 2. The magnetic detection element 2 is excited by the energization from the energization circuit 3 and generates a detection signal S1. The magnetic detection element 2 includes, for example, a magnetosensitive body 21 and a detection coil 22.

[0017] The magnetic detection circuit 4 receives the detection signal S1 generated in the magnetic detection element 2 accompanying the periodic excitation. The magnetic detection circuit 4 includes a plurality of sample-and-hold circuits 41 and an AD (Analog Digital) conversion circuit 42.

[0018] The plurality of sample-and-hold circuits 41 are electrically connected in parallel to the magnetic detection element 2. Each sample-and-hold circuit 41 holds the detection signal S1 at different excitation timings by the energization circuit 3 and outputs it as an analog hold signal S2. The AD conversion circuit 42 performs an analog-to-digital conversion process (hereinafter also referred to as "AD conversion process") for converting the analog hold signal S2 into a digital signal S3.

[0019] The number (m) of the sample-and-hold circuits 41 electrically connected in parallel to the magnetic detection element 2 can be any number of two or more. Also, a plurality of AD conversion circuits 42 corresponding to each of the plurality of sample-and-hold circuits 41 are provided. That is, here, the number (n) of the AD conversion circuits 42 is the same as the number of the plurality of sample-and-hold circuits 41 (m = n).

[0020] In an example shown in FIG. 2, four AD conversion circuits 42a to 42d corresponding to the four sample hold circuits 41a to 41d are provided. At this time, the magnetic detection circuit 4 can perform AD conversion processing on the hold signals S2 held by the four sample hold circuits 41a to 41d respectively by the corresponding AD conversion circuits 42a to 42d, and output them as digital signals S3.

[0021] In this way, since the magnetic detection circuit 4 includes a plurality of sample hold circuits 41 for one magnetic detection element 2, the detection signal S1 output from the magnetic detection element 2 can be sampled in order and processed at an arbitrary timing using the corresponding AD conversion circuit 42. Therefore, by adjusting the excitation timing by the energization circuit 3 to repeatedly excite the magnetic detection element 2 at a shorter cycle and performing parallel processing of the detection signal S1 using a plurality of sample hold circuits 41, sampling can be performed at high speed.

[0022] The plurality of AD conversion processes by the plurality of AD conversion circuits 42 are performed at the same timing or different timings. Also, the plurality of AD conversion circuits 42 may be divided into a plurality of groups, and the AD conversion process may be performed at the same timing for each group. In that case, for example, by dividing into two or more groups, the periods during which the AD conversion process is performed can be grouped for each group, and the time required for the AD conversion process can be shortened.

[0023] Specifically, for a first group constituting a part of the plurality of sample hold circuits 41, the corresponding AD conversion circuit 42 can perform the AD conversion process at the same timing. Also, for a second group constituting another part of the plurality of sample hold circuits 41, the corresponding AD conversion circuit 42 can perform the AD conversion process at the same timing.

[0024] In that case, the AD conversion process in the first group and the AD conversion process in the second group are performed at different timings. As a result, since the AD conversion process is not concentrated in a specific period but is distributed for each group, the influence of noise associated with the AD conversion process can be suppressed during magnetic detection.

[0025] The control circuit 5 can output various control command signals to each circuit such as the energization circuit 3, the magnetic detection circuit 4, and the signal processing circuit 6 at a predetermined timing. The signal processing circuit 6 can perform a signal generation process for generating magnetic detection information based on the digital signal S3 from the AD conversion circuit 42.

[0026] Specifically, the signal processing circuit 6 can acquire a plurality of digital signals S3 based on a plurality of hold signals S2 at the same timing. Also, the signal processing circuit 6 can perform a signal generation process based on the acquired digital signal S3 at a timing different from the AD conversion process. And, for example, a plurality of magnetic detection information based on each of the plurality of digital signals S3 can be generated. In this way, when performing the signal generation process, it is desirable to set the timing of signal acquisition, its processing, and further the output of the processed signal in consideration of the timing of the AD conversion process, suppress the influence of noise associated with the AD conversion process, and enable highly accurate magnetic detection.

[0027] Note that the signal generation process and the output of the processed signal in the first and second groups may be performed at different timings after each AD conversion process, or may be performed at the same timing. When performed at different timings, the magnetic detection information is output at shorter intervals, and when performed at the same timing, the setting of a timing different from the AD conversion process becomes easy and the overall processing period is shortened. In any case, it is possible to generate a plurality of magnetic detection information in a short period, and responsive magnetic detection is possible. Alternatively, using a plurality of digital signals S3 acquired at the same timing, for example, it can also be output as averaged magnetic detection information. In that case, variations due to factors such as the sampling timing are suppressed, enabling more accurate magnetic detection.

[0028] [Configuration of Each Part of Magnetic Sensor Device 1] Next, each part constituting the magnetic sensor device 1 of this embodiment will be specifically described. In FIG. 2, the magnetic sensor device 1 includes a magnetic detection element 2 and an integrated circuit 10 in which various circuits connected to the magnetic detection element 2 are integrated. The integrated circuit 10 includes a power supply circuit 3, a magnetic detection circuit 4 including a plurality of analog blocks 40, a control circuit 5, a signal processing circuit 6, and an output circuit 61.

[0029] The magnetic detection element 2 is configured, for example, as a magneto impedance (MI) element including a magnetosensitive body 21 and a detection coil 22 (in the following description, it will also be referred to as "MI element 2"). When an excitation current is supplied to the magnetosensitive body 21 of the MI element 2, the induced electromotive voltage generated in the detection coil 22 is output as a detection signal S1.

[0030] Here, the magnetic detection circuit 4 includes four analog blocks 40a to 40d. Each of the analog blocks 40a to 40d includes one sample-and-hold circuit 41a to 41d, and also includes amplification circuits 43a to 43d corresponding to the sample-and-hold circuits 41a to 41d, AD conversion circuits 42a to 42d, and latch circuits 44a to 44d. For simplicity, in FIG. 2, only the analog block 40a and the corresponding sample-and-hold circuit 41a, amplification circuit 43a, AD conversion circuit 42a, and latch circuit 44a are labeled with subscripts. Although the internal illustration of the AD conversion circuit 42a is omitted for the analog blocks 40b to 40d, they have the same configuration.

[0031] The four analog blocks 40a to 40d are electrically connected in parallel to the MI element 2 via a pair of signal lines 71 and 72, and the output detection signal S1 is held as a hold signal S2 by one of the four sample-and-hold circuits 41a to 41d.

[0032] A precharge circuit 7 is arranged between the magnetic detection element 2 and the magnetic detection circuit 4. The precharge circuit 7 is electrically connected to each of the pair of signal lines 71 and 72, and can precharge each signal line 71, 72 to a predetermined reference voltage.

[0033] The control circuit 5 outputs a power-on command signal MI_SW to the power-on circuit 3, and outputs a sampling command signal SH_SW for holding the detection signal S1 at a predetermined timing to the corresponding sample-and-hold circuits 41a to 41d. Further, an amplification command signal PRE_SW, an AD reset command signal AD_RST, an AD conversion command signal AD_EN, and a latch command signal AD_LAT are output to the corresponding amplification circuits 43a to 43d, AD conversion circuits 42a to 42d, and latch circuits 44a to 44d, respectively.

[0034] Also, the control circuit 5 can generate and output a precharge command signal PREC_SW for driving the precharge circuit 7, a signal processing command signal SIG_EN for driving the signal processing circuit 6, and the like.

[0035] A level shift block 50 including a plurality of level shift circuits 51 is arranged on the output side of the control circuit 5. These control command signals output from the control circuit 5 are appropriately input to the level shift circuit 51, shifted to a predetermined signal level, and then output to each circuit. Note that, like the sampling command signal SH_SWa shown in FIG. 2, the subscripts a to d appended to these control command signals indicate signals corresponding to the respective circuits of the analog blocks 40a to 40d. Also, for simplicity, for some of the control command signals, the subscripts are shown together like the AD reset command signal AD_RSTab (AD reset command signals AD_RSTa and AD_RSTb). The same shall apply to the figures other than FIG. 2 hereinafter.

[0036] Specifically, the MI element 2 includes an element substrate 20, a magneto-sensitive body 21 disposed on the element substrate 20, and a detection coil 22. The magneto-sensitive body 21 is made of, for example, amorphous wire, and the detection coil 22 is wound around the magneto-sensitive body 21 with an insulating layer therebetween. The element substrate 20 is provided with a pair of wire pads 23 electrically connected to both ends of the magneto-sensitive body 21 respectively, and a pair of coil pads 24 electrically connected to both ends of the detection coil 22 respectively.

[0037] The pair of wire pads 23 of the MI element 2 are electrically connected to the pair of terminal portions 311 and 312 of the energization circuit 3. The pair of coil pads 24 of the MI element 2 are electrically connected to a pair of signal lines 71 and 72 leading to the four sample-and-hold circuits 41a to 41d of the magnetic detection circuit 4. A pulse current is supplied to the MI element 2 from the energization circuit 3 via the wire pads 23, and a detection signal S1 is output from the MI element 2 to the magnetic detection circuit 4 via the coil pads 24.

[0038] Note that the magnetic detection element 2 may be any element capable of detecting magnetism. In addition to the MI element 2, for example, a Hall element, an MR element (magnetoresistive effect element), a GMR element (giant magnetoresistive effect element), a TMR element (tunnel junction magnetoresistive effect element), etc. can be used.

[0039] The energization circuit 3 periodically supplies an excitation current to the MI element 2. For example, a pulse current can be used as the excitation current. Here, as an example, the energization circuit 3 is configured as a pulse energization circuit that can energize the magnetizer 21 with a pulse current. The excitation current only needs to be a periodic current. For example, a high-frequency current can also be used.

[0040] The energization circuit 3 includes a pair of switches 31 and 32 driven by an energization command signal MI_SW from the control circuit 5, and a variable resistor 33. One of the pair of switches 31 is composed of a pMOS transistor and is inserted between one terminal portion 311 leading to one end side of the magnetizer 21 and the power supply terminal AVDD. The other switch 32 of the pair is composed of an nMOS transistor and is inserted between the other terminal portion 312 leading to the other end side of the magnetizer 21 and the ground terminal GND via the variable resistor 33.

[0041] The energization circuit 3 is driven by a signal obtained by level-shifting the energization command signal MI_SW being input to the switch 32 and the inverted signal of the level-shifted signal being input to the switch 31. That is, according to the energization command signal MI_SW from the control circuit 5, the pair of switches 31 and 32 are simultaneously turned on or off, so that the supply of the pulse current to the magnetizer 21 can be started or interrupted.

[0042] When a pulse current flows through the magnetizer 21, an induced electromotive force is generated in the detection coil 22 due to the magnetization change of the amorphous wire. Specifically, the amorphous wire changes its permeability in the circumferential direction corresponding to the strength of the acting external magnetic field, thereby changing its impedance. Due to this magnetization change, the induced electromotive force generated at both ends of the detection coil 22 is output as the detection signal S1.

[0043] The detection signal S1 is input to the magnetic detection circuit 4 via branch signal lines 711a to 711d and 721a to 721d branched from a pair of signal lines 71 and 72, and is held as a hold signal S2 in corresponding sample-and-hold circuits 41a to 41d in response to a sampling command signal SH_SW from the control circuit 5. The four sample-and-hold circuits 41a to 41d have the same configuration.

[0044] As an example, the sample-and-hold circuit 41a shown has a pair of switches 411 and 412 arranged between a pair of input terminal portions 415 and 416 and a pair of output terminal portions 417 and 418, and a pair of capacitors 413 and 414.

[0045] In the sample-and-hold circuit 41a, one of the pair of switches 411 opens and closes between one of the pair of input terminal portions 415 and the output terminal portion 417. One end of the capacitor 413 is connected between the switch 411 and the output terminal portion 417, and the other end is grounded. Also, the other of the pair of switches 412 opens and closes between the other of the pair of input terminal portions 416 and the output terminal portion 418. One end of the capacitor 414 is connected between the switch 412 and the output terminal portion 418, and the other end is grounded.

[0046] A signal obtained by level-shifting the sampling command signal SH_SW (SH_SWa) from the control circuit 5 and its inverted signal are input to the control terminals of the pair of switches 411 and 412. The sampling command signal SH_SW is a pulse signal that rises earlier than the energization command signal MI_SW is output and falls at the time when the detection signal S1 reaches its peak value, as will be described later. Thereby, while the sampling command signal SH_SW is being output, the detection signal S1 from the pair of signal lines 71 and 72 is input to the sample-and-hold circuit 41a, and the peak value of the detection signal S1 is held by the pair of capacitors 413 and 414.

[0047] For the sample-and-hold circuits 41b to 41d as well, a pair of switches 411 and 412 are used to open and close between a pair of input terminal portions 415 and 416 and a pair of output terminal portions 417 and 418, and the configuration for obtaining the hold signal S2 is the same, and the illustration and description are omitted.

[0048] The hold signal S2 is amplified at a predetermined amplification factor in the amplification circuits 43a to 43d arranged at the subsequent stage of the sample-and-hold circuits 41a to 41d. This amplified signal S21 is input to the AD conversion circuits 42a to 42d via the output lines 73a to 73d. Note that the amplification circuits 43a to 43d can also be omitted. The latch circuits 44a to 44d are here incorporated in the AD conversion circuits 42a to 42d, and latch the digitally converted digital signal S3 via the digital signal lines 74a to 74d. The digital signal S3 is output from the digital output lines 75a to 75d to the signal processing circuit 6 at a predetermined timing.

[0049] The precharge circuit 7 has, for example, a configuration in which a pair of precharge switches 701 and 702 are electrically connected in series between a pair of signal lines 71 and 72. A reference voltage generation circuit 70 is connected to the series connection point that becomes the input side terminals of the precharge switches 701 and 702, and the output side terminals of the precharge switches 701 and 702 are connected to the signal lines 71 and 72, respectively. To the control terminals of the precharge switches 701 and 702, a signal obtained by level-shifting the precharge command signal PREC_SW from the control circuit 5 and its inverted signal are input.

[0050] The precharge circuit 7 is driven, for example, prior to the input of the detection signal S1 based on the energization command signal MI_SW. Thereby, the pair of signal lines 71 and 72 are precharged to a predetermined reference voltage, suppressing errors due to fluctuations in the potential of each of the signal lines 71 and 72 and enabling stable magnetic detection.

[0051] [Operation of the magnetic sensor device 1] Hereinafter, with reference to FIGS. 3 to 5, the operation of the magnetic sensor device 1 having the above-described configuration will be described. FIGS. 4 and 5 are timing charts showing the operations in each part of the magnetic sensor device 1. FIG. 3 shows a timing chart of a sampling operation using the analog block 40a including the sample hold circuit 41a as its basic operation.

[0052] In FIGS. 3 and 4, the control circuit 5 outputs a sampling command signal SH_SW (SH_SWa to SH_SWd) as a pulse signal that rises before the energization command signal MI_SW is output and falls at the time when the detection signal S1 reaches the peak value. Thereby, the hold signal S2, which is the peak value of the detection signal S1, is acquired by the corresponding sample hold circuits 41a to 41d, and its amplified signal S21 is subjected to AD conversion processing for each group.

[0053] Prior to this, the control circuit 5 outputs a precharge command signal PREC_SW to drive the precharge circuit 7. Also, it is desirable that the AD conversion circuits 42a to 42d and the amplifier circuits 43a to 43d corresponding to the sampling command signal SH_SW are reset to their initial states prior to their respective operations.

[0054] [Basic Operation by Analog Block 40a] Specifically, first, at time T1 in FIG. 3, the control circuit 5 outputs a sampling command signal SH_SWa to the sample hold circuit 41a and also outputs a precharge command signal PREC_SW. Also, an amplification command signal PRE_SWa is output to the amplifier circuit 43a.

[0055] Thereafter, at time T2, an energization command signal MI_SW is output from the control circuit 5, and the excitation of the MI element 2 is started by the energization circuit 3. Note that FIG. 3 extracts the sampling operation using the analog block 40a from FIGS. 4 and 5. The period from time T1 to time T21 (from the rising edge of the sampling command signal SH_SWa to the next rising edge) indicated by the arrow in the figure corresponds to the sampling frequency (20T).

[0056] Immediately before time T1, the detection signal S1 is not output, and the sample and hold circuit 41a is in a state of holding the hold signal S2 in the previous detection. At time T1, when the precharge command signal PREC_SW and the sampling command signal SH_SWa rise, the potential difference between the pair of branch signal lines 711a and 721a gradually decreases and becomes the same reference potential by time T2. Accordingly, the potential of the output line 73a of the corresponding amplifier circuit 43a also decreases.

[0057] In this way, while the precharge command signal PREC_SW is being output, the precharge switches 701 and 702 are turned on, and the reference voltage from the reference voltage generation circuit 70 is supplied to the pair of signal lines 71 and 72. Since the pair of signal lines 71 and 72 to which the detection signal S1 is output are in a floating state, the potential may not stabilize after the previous detection. Even in that case, prior to the current detection, by precharging the pair of signal lines 71 and 72 to a predetermined reference voltage, for example, the potential difference generated in the pair of signal lines 71 and 72 can be reset.

[0058] Also, the amplifier circuit 43a to which the hold signal S2 is input is reset to an initial state, for example, with the input of the amplification command signal PRE_SWa. By these processes, the potential of the output line 73a corresponding to the amplified signal S21 rapidly decreases, and the current detection can be performed in a stable state.

[0059] At time T2, when the energization command signal MI_SW starts the excitation of the MI element 2, the potential difference (detection signal S1) between the pair of signal lines 71 and 72 gradually increases. Then, as the potential difference between the pair of branch signal lines 711a and 721a increases, the potential of the output line 73a of the amplifier circuit 43 rises. The sampling command signal SH_SWa is set in consideration of the delay time until the detection signal S1 reaches the peak value, and for example, it falls at time T3. Accordingly, the sample and hold circuit 41a holds the peak value of the detection signal S1 as the hold signal S2, and its amplified signal S21 is output from the output line 73a.

[0060] After that, at time T5, when the energization command signal MI_SW falls, the potential difference signal between the pair of signal lines 71 and 72 is inverted from the plus side to the minus side and then returns to a state with almost no potential difference, for example, by around time T6. Therefore, for example, during the period from time T6 to time T8, the AD reset command signal AD_RSTa is output, and the AD conversion circuit 42a is reset to the initial state.

[0061] Next, at time T9, when the AD conversion command signal AD_ENa rises, the amplified signal S21 of the hold signal S2 is read from the output line 73a into the AD conversion circuit 42a, and the AD conversion process is started. The AD conversion circuit 42a has, for example, an N-bit resolution, compares the input analog voltage signal with a reference voltage, and converts it into an N-bit digital signal S3 for storage.

[0062] The AD conversion circuit 42a ends the AD conversion process when the digital signal S3 is determined. For example, at time T15, when the AD conversion process ends and the AD conversion command signal AD_ENa falls, the control circuit 5 outputs a latch command signal AD_LATa from time T15 to time T16. Thereby, the latch circuit 44a latches the digital signal S3 stored in the AD conversion circuit 42a.

[0063] Thereafter, for example, at time T26, when a signal processing command signal SIG_EN is output from the control circuit 5, the signal processing circuit 6 reads the digital signal S3 latched in the latch circuit 44a. Then, a predetermined arithmetic process as a signal generation process is performed to generate magnetic detection information and output it to the output circuit 61. As the arithmetic process, for example, calculations for suppressing individual variations, calculations for detecting the position of an object, etc. are performed.

[0064] The output circuit 61 can output the result of the signal generation process to the outside as magnetic detection data D (or its inverted data / D) (time T27).

[0065] Here, it is desirable that the timings at which the signal processing command signal SIG_EN and the magnetic detection data D are output are periods during which the AD conversion process is not performed. For example, when the AD conversion process period is set until time T25, the timings are later than that and within the period (time T26 to time T28) before the start of the next AD conversion process period (time T29), the signal processing command signal SIG_EN and the magnetic detection data D are output.

[0066] During this period, an AD reset command signal AD_RSTa before the next AD conversion process is also output. In other words, it is desirable that the previous signal generation process and data output are performed during the output period (time T6 to time T8) of the current AD reset command signal AD_RSTa. Thereby, the influence of noise generated during the AD conversion process can be suppressed, and accurate signal generation processing can be performed.

[0067] In this way, the magnetic detection data D based on the Mth digital signal S3 (N-bit(M) in the figure) obtained by the current AD conversion process is output before the next AD conversion process. Similarly, before the current AD conversion process, at the timing when the AD reset command signal AD_RSTa is output, the (M - 1)th digital signal S3 (N-bit(M - 1) in the figure) obtained by the previous AD conversion process is read, and the magnetic detection data D based on it is output.

[0068] [Operation by Group with Analog Blocks 40a to 40d] As shown in FIGS. 4 and 5, in analog blocks 40b to 40d, sampling using sample-and-hold circuits 41b to 41d and AD conversion processing by AD conversion circuits 42b to 42d can also be performed in the same manner.

[0069] At this time, since each process by analog blocks 40a to 40d is performed in parallel, it is possible to increase the speed of sampling by adjusting the excitation timing of MI element 2. In that case, analog blocks 40a to 40d can be divided into a plurality of groups, and corresponding AD conversion processing can be performed for each group.

[0070] As an example, the AD conversion processing in FIG. 5 is performed by dividing analog blocks 40a to 40d into two groups. That is, among the four sample-and-hold circuits 41a to 41d, two sample-and-hold circuits 41a and 41b are set as the first group, and the AD conversion processing by the corresponding AD conversion circuits 42a and 42b is performed at the same timing. Also, the other two sample-and-hold circuits 41c and 41d are set as the second group, and the AD conversion processing by the corresponding AD conversion circuits 42c and 42d is performed at the same timing.

[0071] The AD conversion processing in the same group is performed at the same timing after obtaining a plurality of corresponding hold signals S2. Also, the AD conversion processing in the first group is performed at a timing different from that of the AD conversion processing in the second group. Note that the number and division method of the groups are just examples and can be arbitrarily set according to the number of analog blocks, the AD conversion processing, and other processing timings.

[0072] In FIGS. 4 and 5, the sampling using the sample hold circuit 41a of the first group (during the period from time T1 to time T6) and the operations of the respective circuits including the corresponding AD conversion circuit 42a are the same as the example shown in FIG. 3. Subsequently, the sample hold circuit 41b of the first group performs sampling in the same manner as the sample hold circuit 41a based on the control command signal output from the control circuit 5 during the period from time T6 to time T11.

[0073] Specifically, at time T6, prior to exciting the MI element 2, the control circuit 5 outputs a sampling command signal SH_SWb and a precharge command signal PREC_SW. Further, an amplification command signal PRE_SWb is output to the amplifier circuit 43b.

[0074] Thereafter, when a conduction command signal MI_SW is output during the period from time T7 to time 10, the MI element 2 is excited and a detection signal S1 is output. Next, when the sampling command signal SH_SWb falls at time T8, the sample hold circuit 41b holds the peak value of the detection signal S1 as a hold signal S2 based on the potential difference signal of the branch signal lines 711b and 721b. The hold signal S2 is further amplified by the amplifier circuit 43b and output as an amplified signal S21 to its output line 73b.

[0075] Also, during the period from time T6 to time T8, AD reset command signals AD_RSTa and AD_RSTb are output from the control circuit 5 prior to the AD conversion processing by the AD conversion circuits 42a and 42b. Subsequently, when the AD conversion command signals AD_ENa and AD_ENb rise at time T9, the amplified signal S21 of the hold signal S2 is read from the output lines 73a and 73b into the AD conversion circuits 42a and 42b respectively, and the AD conversion processing is started.

[0076] Then, when the AD conversion process ends at time T15, the AD conversion command signals AD_ENa and AD_ENb fall, and the latch command signals AD_LATa and AD_LATb are output from time T15 to time T16. As a result, the latch circuit 44a latches the M-th digital signal S3 (N-bit(M) in the figure) stored in the AD conversion circuit 42a. Also, the latch circuit 44b latches the (M + 1)-th digital signal S3 (N-bit(M + 1) in the figure) stored in the AD conversion circuit 42b.

[0077] Subsequently, the sampling by the sample-and-hold circuits 41c and 41d of the second group and the operations of the respective circuits including the corresponding AD conversion circuits 42c and 42d are performed in the same manner as the first group.

[0078] That is, at time T11, the control circuit 5 outputs the sampling command signal SH_SWc and the precharge command signal PREC_SW prior to the excitation of the MI element 2. Also, an amplification command signal PRE_SWc is output to the amplifier circuit 43c.

[0079] Thereafter, when the energization command signal MI_SW is output during the period from time T12 to time T15, the MI element 2 is excited and the detection signal S1 is output. Then, at time T13, when the sampling command signal SH_SWc falls, the sample-and-hold circuit 41c holds the peak value of the detection signal S1 as the hold signal S2 based on the potential difference signal of the branch signal lines 711c and 721c. The hold signal S2 is further amplified by the amplifier circuit 43c and output as the amplified signal S21 to its output line 73c.

[0080] Also, at time T16, the control circuit 5 outputs the sampling command signal SH_SWd and the precharge command signal PREC_SW prior to the excitation of the MI element 2. Also, an amplification command signal PRE_SWd is output to the amplifier circuit 43d.

[0081] Thereafter, when a power-on command signal MI_SW is output during the period from time T17 to time T20, the MI element 2 is excited and a detection signal S1 is output. Next, at time T18, when a sampling command signal SH_SWd falls, the sample-and-hold circuit 41d holds the peak value of the detection signal S1 as a hold signal S2 based on the potential difference signals of the branch signal lines 711d and 721d. The hold signal S2 is further amplified by the amplifier circuit 43d and output as an amplified signal S21 to its output line 73d.

[0082] On the other hand, during the period from time T16 to time T18, AD reset command signals AD_RSTc and AD_RSTd are output from the control circuit 5 prior to the AD conversion processing by the AD conversion circuits 42c and 42d. Subsequently, at time T19, when the AD conversion command signals AD_ENc and AD_ENd rise, the amplified signal S21 of the hold signal S2 is read from the output lines 73c and 73d into the AD conversion circuits 42c and 42d respectively, and the AD conversion processing is started.

[0083] When the AD conversion processing ends at time T25, the AD conversion command signals AD_ENc and AD_ENd fall, and latch command signals AD_LATc and AD_LATd are output during the period from time T25 to time T26. Thereby, the latch circuit 44c latches the (M + 2)-th digital signal S3 (N-bit (M + 2) in the figure) stored in the AD conversion circuit 42c. Also, the latch circuit 44d latches the (M + 3)-th digital signal S3 (N-bit (M + 3) in the figure) stored in the AD conversion circuit 42d.

[0084] Thereafter, at time T26, when a signal processing command signal SIG_EN is output from the control circuit 5, the digital signal S3 is output from the digital output lines 75a to 75d to the signal processing circuit 6. The signal processing circuit 6 reads the four digital signals S3 latched by the latch circuits 44a to 44d and performs a predetermined signal generation process on each of them. The results of these signal generation processes are output as four magnetic detection data D (or / D) from the output circuit 61 at the subsequent time T27.

[0085] Also, at time T21 in between, a sampling command signal SH_SWa for the next sampling by the sample-and-hold circuit 41a is output. In this way, sampling by the sample-and-hold circuits 41a to 41d can be repeatedly performed during the period from time T1 to time T21. The sampling frequency in that case is, for example, 5T corresponding to the period from time T1 to time T6, and is shortened to one-fourth of the basic operation (sampling frequency: 20T) shown in FIG. 3.

[0086] According to this embodiment, the magnetic sensor device 1 includes four sample-and-hold circuits 41a to 41d that are electrically parallel and four corresponding AD conversion circuits 42a to 42d with respect to one MI element 2, so that sampling and subsequent AD conversion processing can be performed at high speed. Further, the four sample-and-hold circuits 41a to 41d are divided into a first group and a second group, and the corresponding AD conversion processing is performed at the same timing, so that the time required for the AD conversion processing is shortened and further speedup is possible.

[0087] At that time, the reading of the digital signal S3, the signal generation processing, and the subsequent output of the magnetic detection data D by the signal processing circuit 6 can be performed at an arbitrary timing different from the AD conversion processing. Then, since the period during which the output of noise associated with the AD conversion processing is a concern is shortened, the influence on other signals is suppressed. Further, since the AD conversion processing is performed at different timings for each of the first and second groups, the period of the AD conversion processing in one sampling period is dispersed, the variation in the influence of noise is reduced, and the detection accuracy is improved.

[0088] In this way, by providing the magnetic detection circuit 4 in the magnetic sensor device 1 with the same number of AD conversion circuits 42 as the plurality of sample hold circuits 41, the detection signal S1 from the MI element 2 can be processed in parallel at high speed. In that case, it is possible to output a plurality of magnetic detection data D based on the plurality of digital signals S3 in a short time, and by adjusting the timing of each process, highly accurate magnetic detection with good responsiveness becomes possible.

[0089] (Embodiment 2) FIG. 6 is a diagram showing a circuit configuration example of the magnetic sensor device 1 according to Embodiment 2, and FIGS. 7 and 8 are timing charts showing the operations of each part of the magnetic sensor device 1. In this embodiment, the basic configuration and basic operations of the magnetic sensor device 1 are the same as those in the above Embodiment 1, and the configurations and operations of the analog blocks 40a to 40d are partly different. The differences will be described below.

[0090] In this embodiment, the magnetic sensor device 1 is provided with sub-sample hold circuits 45a to 45d in the analog blocks 40a to 40d in the magnetic detection circuit 4. The sub-sample hold circuits 45a to 45d are respectively arranged between the amplifier circuits 43a to 43d and the AD conversion circuits 42a to 42d in the corresponding analog blocks 40a to 40d. The configurations of the other parts of the magnetic detection circuit 4 and the configurations of the other circuits are the same as those in the above Embodiment 1, and the description thereof will be omitted.

[0091] Also, in the above Embodiment 1, the four sample hold circuits 41a to 41d were divided into two groups so that the corresponding AD conversion processes were performed at different timings, but in this embodiment, they are not divided into groups. That is, for all the sample hold circuits 41a to 41d of the analog blocks 40a to 40d, the corresponding AD conversion circuits 42a to 42d perform the AD conversion process at the same timing.

[0092] In FIG. 6, the sub-sample hold circuits 45a to 45d are respectively connected to the output lines 73a to 73d of the amplifier circuits 43a to 43d. The sub-sample hold circuits 45a to 45d have the same configuration as the sample hold circuits 41a to 41d and are driven by the sub-sampling command signals SHS_SWa to SHS_SWd from the control circuit 5. When the sub-sampling command signals SHS_SWa to SHS_SWd are output, the signals level-shifted in the level shift circuit 51 and their inverted signals are input to the corresponding sub-sample hold circuits 45a to 45d.

[0093] The sub-sample hold circuits 45a to 45d hold the amplified signals S21 of the hold signal S2 output to the output lines 73a to 73d, respectively, at the timing when the sub-sampling command signals SHS_SWa to SHS_SWd fall. The held amplified signals S21 are output to the AD conversion circuits 42a to 42d and are AD-converted.

[0094] In FIG. 7, the operation from the time T1 to the time T18 until the amplified signals S21 of the hold signal S2 are output to the output lines 73a to 73d by sampling using the sample hold circuits 41a to 41d is the same as the example shown in the above Embodiment 1 (FIG. 4), and the description thereof is omitted.

[0095] In this embodiment, at the time T18 in FIG. 8, when the sub-sampling command signals SHS_SWa to SHS_SWd rise, the sub-sample hold circuits 45a to 45d are driven at the same timing. Then, at the time T19, the sub-sampling command signals SHS_SWa to SHS_SWd fall and the AD conversion command signals AD_ENa to AD_ENd rise. Also, during the period from the time T15 to the time T17 prior to the AD conversion process, the AD reset command signals AD_RSTa to AD_RSTd are output at the same timing.

[0096] As a result, the sub-sample hold circuits 45a to 45d respectively hold the amplified signals S21 of the hold signal S2 output to the output lines 73a to 73d. The held amplified signals S21 are output to the AD conversion circuits 42a to 42d, and at time T19, the AD conversion process is started.

[0097] Then, when the AD conversion process ends at time T25, the AD conversion command signals AD_ENa to AD_ENd fall, and between time T25 and time T26, the latch command signals AD_LATa to AD_LATd are output. As a result, the latch circuits 44a to 44d respectively latch the M-th to (M + 3)-th digital signals S3 stored in the corresponding AD conversion circuit 42c.

[0098] After that, when the signal processing command signal SIG_EN is output from the control circuit 5 at time T26, the signal processing circuit 6 reads the four digital signals S3 and performs a predetermined signal generation process on each of them. Then, at time T27, four magnetic detection data D (or / D) are output from the output circuit 61.

[0099] In this way, in the magnetic sensor device 1, the AD conversion processes by the four AD conversion circuits 42a to 42d can be performed at the same timing. At that time, each analog block 40a to 40d can use the sub-sample hold circuits 45a to 45d to hold the amplified signals S21 of the hold signal S2 by the sample hold circuits 41a to 41d at the same timing and output them to the AD conversion circuits 42a to 42d. After the conversion process, the signal generation process by the signal processing circuit 6 can be promptly performed to output the magnetic detection information based on the four digital signals S3.

[0100] According to this embodiment, the magnetic sensor device 1 includes the same number of AD conversion circuits 42 as the four sample hold circuits 41a to 41d, and for all of them, AD conversion processing is performed at the same timing. Therefore, the time required for the AD conversion processing is further shortened. Thus, in addition to speeding up sampling, it becomes easier to adjust the timing for performing other processes, and it is possible to further reduce the influence on other signals and the timing variation. As a result, it is possible to perform highly accurate magnetic detection with good responsiveness.

[0101] (Embodiment 3) FIG. 9 is a diagram showing a circuit configuration example of the magnetic sensor device 1 according to Embodiment 3, and FIGS. 10 and 11 are timing charts showing the operations of each part of the magnetic sensor device 1. In this embodiment, the basic configuration of the magnetic sensor device 1 is the same as that of the above-described Embodiment 2, and the configuration of the magnetic detection circuit 4 is partially different. Also, the basic operation of this embodiment is the same as that of the above-described Embodiment 1, and the differences will be described below.

[0102] The magnetic detection circuit 4 does not necessarily have the same number of AD conversion circuits 42 as the plurality of sample hold circuits 41, and one AD conversion circuit 42 may be commonly provided for two or more sample hold circuits 41. In this embodiment, two AD conversion circuits 42e and 42f are provided, corresponding to two of the four sample hold circuits 41a to 41d. Also, switches 46e and 46f are provided for each of the two AD conversion circuits 42e and 42f, and the connection with the corresponding sample hold circuits 41a to 41d can be switched.

[0103] In FIG. 9, the magnetic detection circuit 4 includes four analog blocks 40a to 40d corresponding to the four sample hold circuits 41a to 41d. Each of the analog blocks 40a to 40d includes an amplifier circuit 43a to 43d and a sub-sample hold circuit 45a to 45d corresponding to the sample hold circuits 41a to 41d, respectively.

[0104] Further, the magnetic detection circuit 4 has two AD conversion circuits 42e and 42f, each corresponding to two of the four sample hold circuits 41a to 41d. Among the two AD conversion circuits 42e and 42f, the AD conversion circuit 42e is connected to two sub-sample hold circuits 45a and 45c via a switch 46e. Also, the AD conversion circuit 42f is connected to two sub-sample hold circuits 45b and 45d via a switch 46f.

[0105] The switch 46e has, for example, a switching switch 461 and selectively connects the AD conversion circuit 42e to one of the two sub-sample hold circuits 45a and 45c. Also, the switch 46f has, for example, a switching switch 462 and can selectively connect the AD conversion circuit 42f to one of the two sub-sample hold circuits 45b and 45d.

[0106] The control circuit 5 outputs switching command signals AD_SWa to AD_SWd to drive the switching switch 461 of the switch 46e or the switching switch 462 of the switch 46f. Specifically, it outputs the switching command signal AD_SWa or the switching command signal AD_SWc to drive the switching switch 461 of the switch 46e and connect the AD conversion circuit 42e to the selected one of the two sub-sample hold circuits 45a and 45c. Also, the control circuit 5 outputs the switching command signal AD_SWb or the switching command signal AD_SWd to drive the switching switch 462 of the switch 46f and connect the AD conversion circuit 42f to the selected one of the two sub-sample hold circuits 45b and 45d. In this way, the connection between the AD conversion circuits 42e and 42f and the analog blocks 40a to 40d that perform AD conversion processing can be switched.

[0107] In this embodiment, similar to the first embodiment, the four sample-and-hold circuits 41a to 41d are divided into two groups, and the AD conversion process is performed for each group. Specifically, the two AD conversion circuits 42e and 42f first perform the AD conversion process by being respectively connected to the corresponding analog blocks 40a and 40b for the two sample-and-hold circuits 41a and 41b that form the first group. Next, for the other two sample-and-hold circuits 41c and 41d that form the second group, the AD conversion process is performed by being respectively connected to the corresponding analog blocks 40c and 40d.

[0108] In this way, when the four sample-and-hold circuits 41a to 41d are divided into two and the AD conversion process is performed at different timings, it is sufficient to provide two AD conversion circuits 42e and 42f, and the number of AD conversion circuits 42 can be reduced. The configurations of the AD conversion circuits 42e and 42f are the same as those in the first embodiment. The latch circuits 44e and 44f latch the digital signal S3 that has been AD-converted via the digital signal lines 74e and 74f. The digital signal S3 is output from the digital output lines 75e and 75f to the signal processing circuit 6 at a predetermined timing. The circuit configuration of the other magnetic sensor device 1 is the same as that in the second embodiment, and the description thereof is omitted.

[0109] In FIGS. 10 and 11, the operation (the period from time T1 to time T18) until the amplified signal S21 of the hold signal S2 is output to the output lines 73a to 73d by sampling using the sample-and-hold circuits 41a to 41d is the same as the example shown in the first embodiment (FIG. 4), and the description thereof is omitted.

[0110] Also in this embodiment, for example, during the period from time T6 to time T8, AD reset command signals AD_RSTe and AD_RSTf are output from the control circuit 5 prior to the AD conversion processing by the AD conversion circuits 42e and 42f. Subsequently, at time T8, when the sub-sampling command signals SHS_SWa and SHS_SWb rise, the sub-sample hold circuits 45a and 45b are driven at the same timing. Then, at time T9, the sub-sampling command signals SHS_SWa and SHS_SWb fall and switching command signals AD_SWa and AD_SWb are output. Also, at time T9, the AD conversion command signals AD_ENe and AD_ENf rise. As a result, the AD conversion circuits 42e and 42f are connected to the sub-sample hold circuits 45a and 45b respectively, and the amplified signal S21 of the hold signal S2 that has been held is read in, and the AD conversion processing is started.

[0111] Then, for example, when the AD conversion processing ends at time T15, the AD conversion command signals AD_ENe and AD_ENf fall, and during the period from time T15 to time T16, latch command signals AD_LATe and AD_LATf are output. As a result, the latch circuits 44e and 44f latch the M to M + 1 digital signals S3 of the AD conversion circuits 42e and 42f corresponding to the first group of sample hold circuits 41a and 41b.

[0112] Subsequently, in the same manner as the first group of sample hold circuits 41a and 41b, AD conversion processing by the AD conversion circuits 42e and 42f is performed corresponding to the second group of sample hold circuits 41c and 41d.

[0113] First, during the period from time T16 to time T18, the AD reset command signals AD_RSTe and AD_RSTf are output again from the control circuit 5. In this embodiment, during this period, a signal processing command signal SIG_EN is output. For example, when the signal processing command signal SIG_EN is output at time T16, the two latched digital signals S3 are output from the digital output lines 75e and 75f to the signal processing circuit 6. In the signal processing circuit 6, a predetermined signal generation process is performed on each of the read digital signals S3, and at time T17, two magnetic detection data D (or / D) are output from the output circuit 61.

[0114] Subsequently, at time T18, when the sub-sampling command signals SHS_SWc and SHS_SWd rise, the sub-sample hold circuits 45c and 45d are driven at the same timing. Then, at time T19, the sub-sampling command signals SHS_SWc and SHS_SWd fall, and the switching command signals AD_SWc and AD_SWd are output. Also, at time T19, the AD conversion command signals AD_ENe and AD_ENf rise. As a result, the AD conversion circuits 42e and 42f are respectively connected to the sub-sample hold circuits 45c and 45d, and the amplified signal S21 of the hold signal S2 that was held is read, and the AD conversion process is started.

[0115] Then, for example, when the AD conversion process ends at time T25, the AD conversion command signals AD_ENe and AD_ENf fall, and between time T25 and time T26, the latch command signals AD_LATe and AD_LATf are output. As a result, the latch circuits 44e and 44f latch the M+2 to M+3 digital signals S3 of the AD conversion circuits 42e and 42f corresponding to the second group of sample hold circuits 41c and 41d.

[0116] After that, at time T26, when the signal processing command signal SIG_EN is output from the control circuit 5, the signal processing circuit 6 reads the two latched digital signals S3 and performs a predetermined signal generation process on each of them. Then, at time T27, two magnetic detection data D (or / D) are output from the output circuit 61. In this way, each time the AD conversion process is performed, during the period until the next AD conversion process is performed, the digital signal S3 may be read into the signal processing circuit 6 and signal processing may be performed. Alternatively, only the reading of the digital signal S3 may be performed, and the signal processing and the output of the result may be performed during an arbitrary period when the AD conversion process is not performed.

[0117] According to this embodiment, the magnetic sensor device 1 includes two AD conversion circuits 42e to 42f corresponding to the four sample hold circuits 41a to 41d, and by performing the AD conversion process by dividing them into the first and second groups, sampling and the subsequent AD conversion process can be performed at high speed. In that case, the two AD conversion circuits 42e to 42f are commonly used for the first and second groups, and by switching the connection with the corresponding sample hold circuits 41a to 41d, the configuration required for the AD conversion process can be made more compact, and efficient and accurate detection can be performed. As a result, highly responsive and highly accurate magnetic detection becomes possible.

[0118] In the above-described Embodiment 3, as an example, two AD conversion circuits 42e to 42f are provided for the four sample hold circuits 41a to 41d and are driven simultaneously, but a configuration in which the two AD conversion circuits 42e to 42f are driven separately may also be used. Further, in a configuration including more sample hold circuits 41, a configuration in which one AD conversion circuit 42 corresponds to three or more sample hold circuits 41 may be used, or three or more AD conversion circuits 42 corresponding to two sample hold circuits 41 may be provided.

[0119] In each of the above-described embodiments, as an example, the four hold signals S2 acquired by the four sample hold circuits 41a to 41d are AD-converted by the corresponding AD conversion circuits 42a to 42d, 42e to 42f and then read into the signal processing circuit 6 at the same timing, but the present invention is not limited to this. For example, the digital signals S3 that have been AD-converted by being divided into two groups may be separately read into the signal processing circuit 6 to perform signal generation processing.

[0120] The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the gist thereof.

Explanation of Reference Numerals

[0121] 1 Magnetic sensor device 2 MI element (magnetic detection element) 21 Magnetosensitive body 22 Detection coil 3 Energization circuit 41 Sample-and-hold circuit 42 AD conversion circuit 43 Amplification circuit 44 Latch circuit 5 Control circuit 6 Signal processing circuit 7 Precharge circuit 71, 72 Pair of signal lines 73 Output line

Claims

1. A magnetic detection element, A power supply circuit that periodically excites the magnetic detection element, A magnetic detection circuit into which a detection signal generated in the magnetic detection element along with the periodic excitation is input, the magnetic sensor device comprising: The magnetic detection circuit includes: A plurality of sample-and-hold circuits that are electrically connected in parallel to the magnetic detection element and hold the detection signals at different excitation timings by the power supply circuit and output them as analog hold signals; An AD conversion circuit that performs analog-to-digital conversion processing for converting the hold signal into a digital signal, the magnetic sensor device.

2. The magnetic sensor device according to claim 1, comprising a plurality of the AD conversion circuits corresponding to each of the plurality of the sample-and-hold circuits.

3. For a first group that constitutes a part of the plurality of the sample-and-hold circuits, the corresponding AD conversion circuit performs the analog-to-digital conversion processing at the same timing, For a second group that constitutes another part of the plurality of the sample-and-hold circuits, the corresponding AD conversion circuit performs the analog-to-digital conversion processing at the same timing, The AD conversion circuit corresponding to the first group and the AD conversion circuit corresponding to the second group perform the analog-to-digital conversion processing at different timings, the magnetic sensor device according to claim 2.

4. The magnetic sensor device according to claim 2, wherein for all of the plurality of the sample-and-hold circuits, the corresponding AD conversion circuit performs the analog-to-digital conversion processing at the same timing.

5. Furthermore, the magnetic sensor device according to claim 1, comprising a switch that switches the connection between two or more of the sample-and-hold circuits and one of the AD conversion circuits.

6. Comprising a plurality of the AD conversion circuits that are provided so as to be connectable to two or more of the sample-and-hold circuits, The plurality of the AD conversion circuits perform the analog-to-digital conversion processing at the same timing, the magnetic sensor device according to claim 5.

7. Furthermore, comprising a signal processing circuit that performs signal generation processing for generating magnetic detection information based on the digital signal from the AD conversion circuit, The signal processing circuit acquires the plurality of digital signals based on the plurality of hold signals at the same timing, the magnetic sensor device according to any one of claims 1 to 6.

8. Furthermore, a signal processing circuit is provided that performs a signal generation process for generating magnetic detection information based on the digital signal from the AD conversion circuit. The signal processing circuit performs the signal generation process at a timing different from the analog-to-digital conversion process. The magnetic sensor device according to any one of claims 1 to 6. **Claim 9** Furthermore, a precharge circuit for precharging a reference voltage is provided on a signal line between the magnetic detection element and the sample hold circuit. The magnetic sensor device according to any one of claims 1 to 6. **Claim 10** The magnetic detection element includes a magnetoresistive body and a detection coil, and an induced electromotive force generated in the detection coil when an excitation current is supplied to the magnetoresistive body is output as the detection signal. The energization circuit periodically supplies the excitation current to the magnetic detection element. The magnetic sensor device according to any one of claims 1 to 6.

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