Display apparatus

Abstract

To provide a display apparatus in which the deterioration of an element in a process can be reduced.SOLUTION: A display apparatus in an example includes a substrate including first to third subpixels, a bank layer disposed on the substrate and sectioning the first to third subpixels, a transistor disposed in each of the first to third subpixels, at least one light-emitting element disposed in each of the first to third subpixels and including a first electrode, a light-emitting layer, and a second electrode, an auxiliary electrode disposed on the bank layer, a first pattern and a second pattern with an overhang structure disposed on the bank layer, and a plurality of first encapsulation layers formed in the first to third subpixels and sectioned by the second pattern. The second electrode of the light-emitting element is electrically connected to the auxiliary electrode on the bank layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This specification relates to a display device capable of reducing the deterioration of elements in a process.

Background Art

[0002] With the development of information technology, various forms of small and thin display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, and micro LED display devices have been proposed. In addition, such display devices are adopted in various electronic devices such as smartphones and tablet PCs.

[0003] A display device not only has various electrodes provided therein, but also includes elements such as various layers and display elements that actually display images. The display device includes a plurality of sub-pixels that embody images of different colors, and display elements such as organic light emitting elements are arranged in each sub-pixel.

[0004] The display elements arranged in the sub-pixels are formed for each sub-pixel. That is, after forming a display element in the first sub-pixel that displays an image of the first color, a display element is formed in the second sub-pixel that displays an image of the second color, and then a display element is formed in the third sub-pixel that displays an image of the third color.

[0005] Therefore, in the manufacture of a display device, when forming a display element in a specific sub-pixel, there is a problem that the display elements arranged in sub-pixels of different colors are damaged by chemical substances such as etching solution and developing solution.

Summary of the Invention

Problems to be Solved by the Invention

[0006] This specification aims to provide a display device capable of preventing damage to a light-emitting element in the manufacturing process of other sub-pixels by separately forming a first encapsulation layer on each sub-pixel.

Means for Solving the Problems

[0007] A display device according to an embodiment includes a substrate including first to third sub-pixels, a bank layer partitioning the first to third sub-pixels, transistors disposed in each of the first to third sub-pixels, a light-emitting element disposed in each of the first to third sub-pixels and including a first electrode, a light-emitting layer, and a second electrode, an auxiliary electrode disposed on the bank layer, first and second patterns of an overhang structure disposed on the bank layer, and a first encapsulation layer formed in each of the first to third sub-pixels and partitioned by the second pattern. The second electrode of the light-emitting element is electrically connected to the auxiliary electrode on the bank layer.

[0008] The first and second patterns can be disposed on the auxiliary electrode. The first pattern can be composed of an inorganic material, and the second pattern can be composed of an amorphous semiconductor. At this time, the second electrode extends to the side surface of the first pattern, and the second electrode is electrically connected to the side surface of the auxiliary electrode.

[0009] A protective layer can be disposed between the auxiliary electrode and the first pattern. The protective layer can be composed of a material with stronger oxidizing property than the auxiliary electrode and can be formed with the same width as the auxiliary electrode.

[0010] The bank layer can include a first bank layer and a second bank layer disposed on the first bank layer and having at least one first opening formed therein. The first opening is formed on both sides of the first pattern. The auxiliary electrode is formed inside the first opening, and the second electrode is disposed on the auxiliary electrode inside the first opening.

[0011] A low-potential voltage wiring can be arranged on the bank layer. In this case, the first pattern can be arranged on the bank layer. A second opening is formed in the first pattern, and the low-potential voltage wiring is exposed to the outside through the second opening. A second pattern is formed in the second opening of the first pattern.

[0012] The auxiliary electrode is formed on the side surface and the upper surface of the first pattern and inside the second opening. In the opening, the auxiliary electrode is electrically connected to the low-potential voltage wiring. The second electrode is electrically connected to the auxiliary electrode formed on the side surface of the first pattern.

Advantages of the Invention

[0013] According to this specification, the following effects can be achieved.

[0014] First, in the display device according to one embodiment, since the organic light-emitting elements are formed for each sub-pixel, the light-emitting layers are not connected between adjacent sub-pixels. Therefore, the current path between adjacent sub-pixels is removed, and the side leakage current between adjacent sub-pixels can be prevented.

[0015] Second, since the first encapsulation layer is not formed over the entire substrate but only formed for each sub-pixel, it is possible to prevent components such as organic light-emitting elements arranged in other sub-pixels from being damaged by chemical agents during the photolithography process of a specific sub-pixel.

[0016] Third, by bringing the second electrode into contact with the side surface and the upper surface of the auxiliary electrode, the contact area between the second electrode and the auxiliary electrode can be maximized, and problems due to signal delay in the second electrode can be prevented.

[0017] Fourth, since the first pattern and the second pattern are in an overhang structure to form the light-emitting layer and the second electrode, a separate photolithography process for patterning the light-emitting layer and the second electrode becomes unnecessary. As a result, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

[0018] Fifth, the auxiliary electrode is formed not in the outer region of the display device but on a part of the upper surface of the bank layer in the display region and on the side surface and the upper surface of the first pattern. Therefore, the electrical contact area between the second electrode and the auxiliary electrode increases, signal delay in the second electrode can be prevented over the entire display device, the area of the outer region can be reduced, and a narrow bezel display device can be realized.

[0019] Sixth, since a separate photo process for patterning the light-emitting layer and the second electrode is not required, production energy can be reduced by optimizing the process.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0021] The advantages, features of the present invention, and the methods for achieving them will become clear by referring to the embodiments described in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various different forms. However, this embodiment is provided so that the disclosure of the present invention is complete and that those with ordinary knowledge in the technical field to which the present invention pertains can fully understand the scope of the invention. The present invention is defined by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary and the present invention is not limited thereto. Throughout the specification, the same reference numerals indicate the same components. Also, when explaining the present invention, if it is determined that a specific explanation of related known technologies will obscure the gist of the present invention, the detailed explanation thereof will be omitted. When "comprises", "includes", "has", "holds", "becomes", etc. are described in this specification, other parts can be added unless "only / merely" are both described. Also, when a component is described in the singular form, it can be interpreted in the plural form unless otherwise explicitly stated.

[0023] Also, when interpreting a component, even if there is no explicit description, it shall be assumed to include an error range.

[0024] For example, when describing the positional relationship between two components using terms such as "above", "on the upper part", "on the lower part", "horizontally", etc., if "directly" or "immediately" is not described, one or more other components can also be located between the two components.

[0025] Also, in the description of the time relationship, for example, when describing the temporal precedence relationship using terms such as "after", "subsequent to", "next", "before", etc., if "directly" or "immediately" is not described, discontinuous cases can be included.

[0026] In addition, to distinguish components, terms such as "first" and "second" are used, but the components are not limited to such terms. Therefore, the first component mentioned below can also be the second component within the technical idea of the present invention.

[0027] In describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used, but such terms are only used to distinguish the components and do not limit the essence, order, sequence, number, etc. of the components. When a component is described as being "connected", "coupled", or "joined" to another component, the two components can be directly connected, coupled, or joined, but it should be understood that another component may be interposed between the components, and each component may be "connected", "coupled", or "joined" through another component.

[0028] The "display device" in the present invention can include a display device in a narrow sense such as a display module including a display panel and a driving unit for driving the display panel. Further, it can also include a notebook computer, a television, a computer monitor, which are final products (complete product, final product) equipped with a display module, or an electrical equipment display including other forms of automotive displays or vehicles, a set electronic device such as a mobile electronic device like a smartphone or an electronic pad, or a set device (set apparatus).

[0029] Therefore, the display device in the present invention can include the display device itself in a narrow sense such as a display module, an application product equipped with a display module, or even a set device which is a final product.

[0030] Hereinafter, the present invention will be described in detail with reference to the drawings.

[0031] FIG. 1 is a block diagram schematically showing a display device 100 according to the present invention, and FIG. 2 is a block diagram schematically showing a sub-pixel SP shown in FIG. 1.

[0032] As shown in FIG. 1, the display device 100 includes a video processing unit 102, a timing control unit 104, a gate driving unit 106, a data driving unit 107, a power supply unit 108, and a display panel 109.

[0033] The video processing unit 102 outputs a driving signal for driving any device together with video data from the outside. For example, the driving signal output from the video processing unit 102 can include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like.

[0034] The timing control unit 104 receives the supply of drive signals and the like together with video data from the video processing unit 102. Based on the drive signal input from the video processing unit 102, the timing control unit 104 generates and outputs a gate timing control signal GDC for controlling the operation timing of the gate drive unit 106 and a data timing control signal DDC for controlling the operation timing of the data drive unit 107.

[0035] The gate drive unit 106 outputs a scan signal to the display panel 109 in response to the gate timing control signal GDC from the timing control unit 104. The gate drive unit 106 outputs the scan signal through a plurality of gate lines GL1 to GLm. At this time, the gate drive unit 106 can be in the form of an IC (Integrated Circuit), but is not limited thereto. The gate drive unit 106 includes various gate drive circuits, and the gate drive circuits can be directly formed on the substrate of the display panel 109. In this case, the gate drive unit 106 may be a GIP (Gate-In-Panel).

[0036] The data drive unit 107 outputs a data voltage to the display panel 109 in response to the data timing control signal DDC input from the timing control unit 104. The data drive unit 107 samples and latches the digital data signal DATA from the timing control unit 104 and converts it into an analog data voltage based on the gamma voltage. The data drive unit 107 outputs the data voltage through a plurality of data lines DL1 to DLn. At this time, the data drive unit 107 can be in the form of an IC, but is not limited thereto.

[0037] The power supply unit 108 outputs a high potential voltage VDD, a low potential voltage VSS, etc., and supplies them to the display panel 109. The high potential voltage VDD is supplied to the display panel 109 through the first power line EVDD, and the low potential voltage VSS is supplied to the display panel 109 through the second power line EVSS. At this time, the voltage output from the power supply unit 108 may be output to the gate drive unit 106 and the data drive unit 107 and used for driving them.

[0038] The display panel 109 displays an image in response to a data voltage and a scan signal supplied from the gate driving unit 106 and the data driving unit 107, and a voltage supplied from the power supply unit 108.

[0039] The display panel 109 is composed of a plurality of sub-pixels SP, and an image is actually displayed. The sub-pixel SP may include a red (Red) sub-pixel, a green (Green) sub-pixel, and a blue (Blue) sub-pixel, or may include a white (White, W) sub-pixel, a red (Red, R) sub-pixel, a green (Green, G) sub-pixel, and a blue (Blue, B) sub-pixel. At this time, the sub-pixels SP of white W, red R, green G, and blue B may all have the same area, or may have different areas from each other.

[0040] As shown in FIG. 2, one sub-pixel SP can be connected to a gate line GL1, a data line DL1, a first power line EVDD, and a second power line EVSS. The sub-pixel SP can include a plurality of thin film transistors and a storage capacitor depending on the configuration of the pixel circuit. For example, the sub-pixel SP may be 2 transistors and 1 capacitor 2T1C, but is not limited thereto, and can also be a sub-pixel adopting configurations such as 3T1C, 4T1C, 5T1D, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C.

[0041] FIG. 3 is a circuit diagram schematically showing the sub-pixel SP of the display device 100 according to the present invention.

[0042] As shown in FIG. 3, the display device according to the present invention includes a gate wiring GL, a data wiring DL, and a power supply wiring PL that intersect each other to partition the sub-pixel SP. In the sub-pixel SP, a switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and an organic light emitting element D are arranged.

[0043] The switching transistor Ts is connected to the gate wiring GL and the data wiring DL, the driving transistor Td and the storage capacitor Cst are connected between the switching transistor Ts and the power supply wiring PL, and the organic light-emitting element D is connected to the driving transistor Td.

[0044] In the display device having such a structure, when the switching transistor Ts is turned on by a gate signal applied to the gate wiring GL, the data signal applied to the data wiring DL is applied via the switching transistor Ts to the gate electrode of the driving transistor Td and one electrode of the storage capacitor Cst.

[0045] The driving transistor Td is turned on by the data signal applied to the gate electrode. As a result, a current proportional to the data signal flows from the power supply wiring PL through the driving transistor Td to the organic light-emitting element D, and the organic light-emitting element D emits light with a luminance proportional to the current flowing through the driving transistor Td.

[0046] At this time, the storage capacitor Cst is charged with a voltage proportional to the data signal, so that the voltage of the gate electrode of the driving transistor Td is held constant during one frame.

[0047] In FIG. 3, only two transistors Td and Ts and one capacitor Cst are shown, but the present invention is not limited thereto, and three or more transistors and two or more capacitors can be provided.

[0048] FIG. 4 is a diagram specifically showing the structure of the display device 100 according to the first embodiment of the present invention. Actually, a large number of sub-pixels are formed in the display device 100, but for the sake of convenience of explanation, only three adjacent sub-pixels SP1, SP2, and SP3 are shown.

[0049] The sub-pixels SP1, SP2, and SP3 can each include a sub-pixel of red R, a sub-pixel of green G, and a sub-pixel of blue B. Further, the sub-pixel SP can further include a sub-pixel of white W.

[0050] As shown in FIG. 4, a buffer layer 142 is formed on a substrate 140. The substrate 140 may be made of a hard material such as glass, or may be made of a plastic material such as polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate, but is not limited thereto.

[0051] For example, when the substrate 140 is made of polyimide, it can be composed of a plurality of polyimides, and an inorganic layer can be further disposed between the polyimides, but is not limited thereto.

[0052] The buffer layer 142 is formed over the entire substrate 140 and can play a role in improving the adhesion between the layer formed thereon and the substrate 140 and blocking various foreign substances such as an alkaline component flowing out from the substrate 140. Also, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 140.

[0053] The buffer layer 142 can be a single layer or a multilayer made of SiNx or SiOx. When the buffer layer 142 is a multilayer, SiNx and SiOx may be alternately formed. The buffer layer 142 can also be omitted based on the type and material of the substrate 140, the structure and type of the thin film transistor, etc.

[0054] A thin film transistor T is formed on the buffer layer 142 in each of the sub-pixels SP1, SP2, and SP3. For the sake of convenience of explanation, only the driving thin film transistor is shown in the figure among various thin film transistors that can be arranged, but other transistors such as switching transistors can also be included. Also, although a thin film transistor having a top gate structure is shown, it is not limited thereto, and other structures such as a bottom gate structure can also be adopted.

[0055] The thin film transistor T includes a semiconductor layer 112 disposed on the buffer layer 142, a gate insulating layer 144 formed on the semiconductor layer 112, a gate electrode 114 disposed on the gate insulating layer 144, an interlayer insulating layer 146 formed on the gate electrode 114, a source electrode 115 and a drain electrode 116 disposed on the interlayer insulating layer 146.

[0056] The semiconductor layer 112 may be made of a polycrystalline semiconductor. For example, the polycrystalline semiconductor may be made of low temperature poly silicon (LTPS) with high mobility, but is not limited thereto.

[0057] Alternatively, the semiconductor layer 112 may be made of an oxide semiconductor. For example, it may be made of any one of IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IGO (Indium Gallium Oxide), but is not limited thereto. The semiconductor layer 112 includes a channel region 112a in its central region and source regions 112b and drain regions 112c which are doped layers on both sides thereof.

[0058] The gate insulating layer 144 may be formed over the entire substrate 140, or may be formed only in a partial region, for example, under the gate electrode 114. The gate insulating layer 144 may be a single layer or a multilayer made of an inorganic material such as SiNx or SiOx, but is not limited thereto.

[0059] The gate electrode 114 is made of metal. For example, the gate electrode 114 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0060] The interlayer insulating layer 146 may be formed over the entire substrate 140, or may be formed only in a partial region. The interlayer insulating layer 146 may be made of an organic material such as photoacrylic, or may be a single layer or a multilayer made of an inorganic material such as SiNx or SiOx. Further, the interlayer insulating layer 146 may be a multilayer composed of an organic layer and an inorganic layer, but is not limited thereto.

[0061] The source electrode 115 and the drain electrode 116 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto. The source electrode 115 and the drain electrode 116 can each contact the source region 112b and the drain region 112c of the semiconductor layer 112 through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146.

[0062] Although not shown in the figure, a bottom shield metal layer can be disposed on the substrate 140 under the semiconductor layer 112. The bottom shield metal layer is for reducing the back-channel effect caused by charges trapped in the substrate 140 and preventing afterimages and performance degradation of the transistor, and can be a single layer or a multilayer made of molybdenum (Mo), titanium (Ti), or an alloy thereof, but is not limited thereto.

[0063] A planarization layer 148 is formed on the substrate 140 on which the thin-film transistor T is disposed. The planarization layer 148 may be made of an organic layer such as photoacrylic, but is not limited thereto, and can also be a multilayer composed of an inorganic layer and an organic layer.

[0064] A light-emitting element D is disposed on each of the sub-pixels SP1, SP2, and SP3 on the planarization layer 148. The light-emitting element D is composed of a first electrode 132, a light-emitting layer 134, and a second electrode 136.

[0065] The first electrode 132 is disposed on the planarization layer 148 and is electrically connected to the drain electrode 116 of the thin film transistor T through a contact hole formed in the planarization layer 148. The first electrode 132 can be made of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. Further, the first electrode 132 may be made of a transparent metal oxide material layer such as ITO or IZO.

[0066] When the display device 100 is a top emission type, since the first electrode 132 serves as a reflective electrode that reflects light, it can further contain an opaque conductive material. When the display device 100 is a bottom emission type, the first electrode 132 can use a transparent conductive material that transmits light, such as ITO or IZO.

[0067] A bank layer BNK is formed at the boundary between each sub-pixel SP1 and SP2 on the planarization layer 148. The bank layer BNK can be a partition wall that partitions the sub-pixels SP1 and SP2. The bank layer BNK can partition each sub-pixel SP1 and SP2 and prevent light of a specific color from adjacent pixels from being mixed and emitted.

[0068] The bank layer BNK is formed so as to surround the sub-pixels SP1, SP2, and SP3, and an opening region where the first electrode 132 is exposed to the outside can be formed between the sub-pixels SP1, SP2, and SP3.

[0069] The bank layer BNK can be made of at least one of inorganic insulating materials such as SiNx and SiOx, organic insulating materials such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or a photosensitive agent containing a black (or dark color) pigment, but is not limited thereto.

[0070] An auxiliary electrode 152 is disposed on the bank layer BNK. The auxiliary electrode 152 can be made of a highly conductive metal. For example, the auxiliary electrode 152 can be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a single layer or a multilayer made of an alloy thereof, but is not limited thereto.

[0071] Since the bank layer BNK is formed in a matrix shape across the entire substrate 140, the auxiliary electrode 152 formed thereon is also arranged in a matrix shape. The width of the auxiliary electrode 152 is formed smaller than that of the bank layer BNK, and the upper surface of the bank layer BNK is exposed on both sides of the auxiliary electrode 152, but is not limited thereto. The auxiliary electrode 152 can be formed to have the same width as the bank layer BNK.

[0072] The light-emitting layer 134 is formed on the upper surface of the first electrode 132 that is exposed to the outside through the opening region of the bank layer BNK.

[0073] For example, the light-emitting layer 134 can be composed of an organic light-emitting layer. Alternatively, instead of the organic light-emitting layer, an inorganic light-emitting layer, for example, a nano-sized material layer, a quantum dot, a micro-LED light-emitting layer, or a mini-LED light-emitting layer can be arranged, but is not limited thereto.

[0074] When the light-emitting layer 134 is an organic light-emitting layer, the light-emitting layer 134 is composed of a blue organic light-emitting layer and a yellow fluorescent layer, and white light is emitted from the light-emitting layer 134. Also, the light-emitting layer 134 can have a multilayer stack structure. For example, when the light-emitting layer 134 has a three-layer stack structure, two charge generation layers can be interposed, and the first stack to the third stack can be arranged. Each of the first stack to the third stack can be composed of an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. For example, the organic light-emitting layer of the first stack can emit red light, the organic light-emitting layer of the second stack can emit blue light, and the organic light-emitting layer of the third stack can emit green light.

[0075] A first pattern 154 and a second pattern 156 are formed on the auxiliary electrode 152.

[0076] At this time, since the bank layer BNK and the auxiliary electrode 152 are formed in a matrix shape over the entire substrate 140, the first pattern 154 and the second pattern 156 are also formed in a matrix shape over the entire substrate 140.

[0077] Since the width of the first pattern 154 is formed smaller than that of the auxiliary electrode 152, the upper surfaces of the auxiliary electrode 152 on both sides of the first pattern 154 are exposed to the outside, but it is not limited thereto. Also, the width of the first pattern 154 is formed smaller than that of the second pattern 156, and the first pattern 154 and the second pattern 156 have an overhang structure.

[0078] The first pattern 154 can be composed of an inorganic material such as SiNx or SiOx, but it is not limited thereto. Also, the second pattern 156 can be composed of amorphous silicon, but it is not limited thereto.

[0079] The second electrode 136 is disposed on the organic layer 134. When the display device 100 is a top emission type, the second electrode 136 can be formed using a translucent conductive material that transmits light. For example, the second electrode 136 can be formed of at least one of alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and LiF / Ca:Ag.

[0080] When the display device 100 is a bottom emission type, the second electrode 136 is a reflective electrode that reflects light and can be formed using an opaque conductive material. For example, the second electrode 136 can be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

[0081] The second electrode 136 extends to the upper surface of the bank layer BNK exposed to the outside, the side surface and the upper surface exposed to the outside of the auxiliary electrode 152, and the side surface of the first pattern 154. That is, the second electrode 136 is electrically connected to a part of the side surface and the upper surface of the auxiliary electrode 152.

[0082] In the display device 100 according to the present invention, the second electrodes 136 are respectively formed in the sub-pixels SP1, SP2, and SP3, and the second electrodes 136 in the adjacent sub-pixels SP1, SP2, and SP3 are electrically insulated from each other. However, the auxiliary electrode 152 electrically connects the second electrodes 136 in the adjacent sub-pixels SP1, SP2, and SP3. That is, the auxiliary electrode 152 electrically connects the second electrodes 136 throughout the display device 100, and a signal applied from the outside is supplied to the entire second electrode 136 in the display device 100.

[0083] In addition, the auxiliary electrode 152 can prevent malfunctions of the display device 100 due to signal delay. When the display device 100 is of the top emission type, since the translucent conductive material forming the second electrode 136 has a relatively high resistance, in the case of a large-area display device 100, a problem of signal delay occurs. However, as in the present invention, after forming the auxiliary electrode 152 excellent in conductivity in a matrix form over the entire display device 100 and then electrically connecting the second electrode 136 to the auxiliary electrode 152, it is possible to prevent malfunctions due to signal delay of the second electrode 136.

[0084] The first pattern 154 and the second pattern 156 have an overhang structure where an inverse step occurs. As will be described later, the overhang structures of the first pattern 154 and the second pattern 156 are for patterning the light-emitting layer 134 and the second electrode 136 for each sub-pixel. That is, in the present invention, by making the first pattern 154 and the second pattern 156 have an overhang structure, the light-emitting layer 134 and the second electrode 136 can be formed without using a separate mask, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0085] A sealing layer 180 is formed on the light-emitting element D. When the light-emitting element D is exposed to moisture or oxygen, pixel shrinkage may occur where the light-emitting region shrinks, or a malfunction may occur where black dots are generated in the light-emitting region. Also, moisture and oxygen oxidize the electrode made of metal. The sealing layer 180 blocks the penetration of moisture and oxygen from the outside and prevents malfunctions in the light-emitting element D and the electrode.

[0086] The sealing layer 180 can be composed of a first sealing layer 182a, 182b, 183c, a second sealing layer 184, and a third sealing layer 186, but is not limited thereto, and can also be two layers or four or more layers.

[0087] The first encapsulation layers 182a, 182b, and 182c are formed for each of the sub-pixels SP1, SP2, and SP3. That is, while the second encapsulation layer 184 and the third encapsulation layer 186 are formed across the entire substrate, the first encapsulation layers 182a, 182b, and 182c are formed only for the corresponding sub-pixels SP1, SP2, and SP3. Each of the first encapsulation layers 182a, 182b, and 182c is formed to cover the entire second electrode 136 in the corresponding sub-pixels SP1, SP2, and SP3. In FIG. 4, the upper surfaces of the first encapsulation layers 182a, 182b, and 182c are formed to be at the same level as the lower surface of the second pattern 156, but it is not limited thereto.

[0088] The first encapsulation layers 182a, 182b, 182c, and the third encapsulation layer 186 can be composed of inorganic substances such as SiOx and SiNx, but are not limited thereto. The second encapsulation layer 184 can be composed of an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxycarbide (SiOC), but is not limited thereto. The third encapsulation layer 186 can be composed of a thin-film metal (Face Seal Metal), but is not limited thereto.

[0089] As described above, in the display device 100 according to the present invention, since the organic light-emitting elements D are formed for each of the sub-pixels SP1, SP2, and SP3, the light-emitting layer 134 is not connected between the adjacent sub-pixels SP1, SP2, and SP3. Therefore, the current path between the adjacent sub-pixels SP1, SP2, and SP3 is removed, and the side leakage current between the adjacent sub-pixels SP1, SP2, and SP3 can be prevented.

[0090] In the present invention, the first sealing layers 182a, 182b, and 182c are not formed over the entire substrate 140 but only on each of the sub-pixels SP1, SP2, and SP3. Therefore, during the photolithography process of a specific sub-pixel (for example, the third sub-pixel SP3), components such as the organic light-emitting element D disposed in other sub-pixels (for example, the first sub-pixel SP1 and the second sub-pixel SP2) can be prevented from being damaged by chemicals.

[0091] In the present invention, by bringing the second electrode 136 into contact with the side surface and the upper surface of the auxiliary electrode 152, the contact area between the second electrode 136 and the auxiliary electrode 152 can be maximized, and defects due to signal delay in the second electrode 136 can be prevented.

[0092] Hereinafter, a method for manufacturing the display device 100 according to the first embodiment of the present invention will be described in detail.

[0093] FIGS. 5A to 5G are diagrams showing a method for manufacturing the display device 100 according to the first embodiment of the present invention.

[0094] First, as shown in FIG. 5A, a buffer layer 142 is formed over the entire substrate 140 including a plurality of sub-pixels SP1, SP2, and SP3. The substrate 140 may be made of a hard material such as glass, or may be made of a plastic material such as polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate. The buffer layer 142 may be a single layer or a multi-layer made of SiNx or SiOx.

[0095] Next, on each of the sub-pixels SP1, SP2, and SP3 on the buffer layer 142, a polycrystalline semiconductor such as polysilicon, or an oxide semiconductor such as IGZO, IZO, IGTO, and IGO is laminated, and then etching is performed to form a semiconductor layer 112 on each of the sub-pixels SP1, SP2, and SP3. Further, impurities are doped on both side surfaces of the semiconductor layer 112 to form a channel region 112a, a source region 112b, and a drain region 112c.

[0096] Thereafter, inorganic substances such as SiOx and SiNx are laminated to form the gate insulating layer 144. Then, metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) are laminated by sputtering, and etching is performed by a wet etching method to form the gate electrode 114 for each of the sub-pixels SP1, SP2, and SP3. Thereafter, an organic substance such as photoacrylic or an inorganic substance such as SiNx or SiOx is laminated on the gate electrode 114 to form the interlayer insulating layer 146. Then, the interlayer insulating layer 146 on the upper portions of the source region 112b and the drain region 112c of the semiconductor layer 112 is dry-etched to form contact holes.

[0097] Subsequently, metals such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy are laminated by sputtering and etched to form the source electrode 115 and the drain electrode 116 that make ohmic contact with the source region 112b and the drain region 112c of the semiconductor layer 112 through the contact holes for each of the sub-pixels SP1, SP2, and SP3.

[0098] Thereafter, an organic substance such as photoacrylic is laminated on the source electrode 115 and the drain electrode 116 to form the planarization layer 148. Then, the planarization layer 148 on the drain electrode 116 is dry-etched to form contact holes. Subsequently, metal oxides such as ITO and IZO are laminated by sputtering and wet-etched to form the first electrode 132 on the upper surface of the planarization layer 148 in the sub-pixels SP1, SP2, and SP3. At this time, the first electrode 132 is electrically connected to the drain electrode 116 through the contact hole.

[0099] Next, as shown in FIG. 5B, at least one or more of an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as BCB, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, or a photosensitive agent containing a black (or dark-colored) pigment is laminated on the planarization layer 148 and the ends of the first electrode 132, and dry etching is performed to form the bank layer BNK.

[0100] At this time, the bank layer BNK is formed in a matrix shape across the entire substrate 140 and overlaps the ends of the first electrode 132, so that the first electrode 132 is exposed to the outside through the opening region between the bank layers BNK.

[0101] Thereafter, across the entire substrate 140, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof is laminated to form the metal layer 152a, and an inorganic material such as SiNx or SiOx and amorphous silicon are continuously vapor-deposited thereon to form the first pattern layer 154a and the second pattern layer 156a.

[0102] Subsequently, a photoresist is laminated on the second pattern layer 156a, and the region corresponding to the first sub-pixel SP1 is removed using a mask to form the first photoresist pattern 170.

[0103] Next, as shown in FIG. 5C, using the first photoresist pattern 170 as a mask, the underlying metal layer 152a, the first pattern layer 154a, and the second pattern layer 156a are etched to form the auxiliary electrode 152, the first pattern 154b, and the second pattern 156b in the first sub-pixel SP1, and the first electrode 132 is exposed to the outside.

[0104] At that time, the metal layer 152a, the first pattern layer 154a, and the second pattern layer 156a are etched over a plurality of steps, and the first pattern 154b and the second pattern 156b have an overhang structure. That is, dry etching is performed in a state blocked by the first photoresist pattern 170. After etching the second pattern layer 156a, wet etching is performed to etch the first pattern layer 154a. At this time, the first pattern layer 154a is isotropically etched by the etching solution, and a part of the first pattern layer 154a at the lower part of the second pattern 156b is etched, and the first pattern 154b and the second pattern 156b have an undercut shape. The metal layer 152a is etched by the etching solution in a state blocked by the first pattern 154b and the second pattern 156b, and an auxiliary electrode 152 having the same width as the first pattern 154 is formed.

[0105] Next, as shown in FIG. 5D, an organic substance is applied over the entire substrate 140, and metals such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr) are laminated. At this time, in the first sub-pixel SP1, the first pattern layer 154a and the second pattern layer 156a are etched, and the first electrode 132 below them is exposed to the outside. However, in the second sub-pixel SP2 and the third sub-pixel SP3, they are covered by the first pattern 154b and the second pattern 156b, and since the first pattern 154b and the second pattern 156b have an overhang structure, a light-emitting layer 134 and a second electrode 136 are formed on the first electrode 132 in the first sub-pixel SP1.

[0106] At that time, since the second electrode 136 is formed by a vapor deposition method, regardless of the overhang structure of the first pattern 156ab and the second pattern 156b, the second electrode 136 is also formed on the upper surface of the auxiliary electrode 152 and the side surface of the first pattern 154b and is electrically connected to the auxiliary electrode 152.

[0107] Also, an organic pattern 134a and a metal pattern 136a are formed on the second pattern 156b in the second sub-pixel SP2 and the third sub-pixel SP3.

[0108] Next, an inorganic substance such as SiNx or SiOx is laminated, and an inorganic layer 183 is formed over the entire substrate 140.

[0109] Thereafter, as shown in FIG. 5E, a photoresist is laminated and shaped over the entire substrate 140, and a second photoresist pattern 172 is formed on the inorganic layer 183 in the first sub-pixel SP1.

[0110] Thereafter, as shown in FIG. 5F, with a partial region of the inorganic layer 183 blocked by the second photoresist pattern 172, the organic pattern 134a, the metal pattern 136a, and the inorganic layer 183 are etched to form a first sealing layer 182a in the first sub-pixel SP1, and in the second sub-pixel SP2 and the third sub-pixel SP3, the first pattern 154b and the second pattern 156b are exposed to the outside.

[0111] Subsequently, the steps of FIGS. 5B to 5F are repeated for the second sub-pixel SP2 and the third sub-pixel SP3 to form first sealing layers 182b and 182c, respectively.

[0112] Thereafter, an organic substance is applied over the entire substrate 140 on which the first sealing layers 182a, 182b, and 182c are formed to form a second sealing layer 184, and then an inorganic substance is applied on the second sealing layer 184 to form a third sealing layer 186, thereby forming a sealing layer 180 for sealing the display device 100.

[0113] As described above, in the manufacturing method of the display device 100 according to the present invention, since the first pattern 154b and the second pattern 156b are formed in an overhang structure and the light-emitting layer 134 and the second electrode 136 are formed, a separate photolithography process for patterning the light-emitting layer 134 and the second electrode 136 becomes unnecessary. As a result, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0114] FIG. 6 is a diagram showing a display device 200 according to a second embodiment of the present invention. Description of the same structure as that of the first embodiment in FIG. 4 will be omitted or simplified, and only other structures will be described in detail.

[0115] As shown in FIG. 6, a thin film transistor T and an organic light emitting element D are arranged in each of the sub-pixels SP1, SP2, and SP3 of the substrate 240.

[0116] The thin film transistor T includes a semiconductor layer 212 disposed on the buffer layer 242, a gate electrode 214 disposed on the gate insulating layer 244, and a source electrode 215 and a drain electrode 216 disposed on the interlayer insulating layer 246.

[0117] A planarization layer 248 is formed on the thin film transistor T, and a bank layer BNK is formed in a matrix between the sub-pixels SP1, SP2, and SP3 on the planarization layer 248. The organic light emitting element D includes a first electrode 232, a light emitting layer 234, and a second electrode 236. The first electrode 232, the light emitting layer 234, and the second electrode 236 are arranged in each of the sub-pixels SP1, SP2, and SP3 and are not connected to adjacent sub-pixels.

[0118] An auxiliary electrode 252 is disposed on the bank layer BNK, and a protective layer 253 is disposed on the auxiliary electrode 252. The width of the auxiliary electrode 252 can be formed smaller than that of the bank layer BNK, and the protective layer 253 can be formed with the same width as the auxiliary electrode 252, but is not limited thereto.

[0119] The protective layer 253 can be made of metal. The protective layer 253 is made of a metal that is relatively more oxidizing than the auxiliary electrode 252 below it, and in an environment where the auxiliary electrode 252 oxidizes, it oxidizes instead of the auxiliary electrode 252 to prevent oxidation of the auxiliary electrode 252.

[0120] Similarly, also in the region where the auxiliary electrode 252 and the second electrode 236 are in contact, due to the relative strength of oxidizing property, the protective layer 253 oxidizes instead of the auxiliary electrode 252 and the second electrode 236. As a result, in this region, oxidation of the auxiliary electrode 252 and the second electrode 236 can be prevented.

[0121] Referring to FIG. 6 again, a first pattern 254 and a second pattern 256 are disposed on the protective layer 252. At this time, the first pattern 254 is formed with a width smaller than that of the second pattern 256, and the first pattern 254 and the second pattern 256 have an overhang structure. Due to such an overhang structure, when forming the light-emitting layer 234 and the second electrode 236 in the organic light-emitting element D, a separate mask process becomes unnecessary.

[0122] The second electrode 236 is disposed on the light-emitting layer 234, extends to a partial region on the upper surface of the bank layer BNK, the side surface of the auxiliary electrode 252, and partial regions on the side surface and the upper surface of the first pattern 254, and the second electrode 236 is electrically connected to the side surface of the auxiliary electrode 252. That is, the auxiliary electrode 252 electrically connects the second electrode 236 throughout the display device 200, and a signal (voltage) is simultaneously supplied to the second electrode 236 throughout the display device 200.

[0123] First sealing layers 282a, 282b, and 282c are respectively formed in sub-pixels SP1, SP2, and SP3 partitioned by the second pattern 256. On top of them, a second sealing layer 284 and a third sealing layer 286 are disposed over the entire substrate 240, and a sealing layer 280 that seals the display device 200 is completed.

[0124] Thus, in the display device 200 according to this embodiment, a protective layer 253 made of a metal having relatively stronger oxidizing property than the auxiliary electrode 252 is formed on the auxiliary electrode 252, and by oxidizing the protective layer 253 instead of the auxiliary electrode 252, oxidation of the auxiliary electrode 252 can be prevented.

[0125] FIG. 7 is a cross-sectional view showing the structure of a display device 300 according to a third embodiment of the present invention. Description of the same structure as that of the first embodiment in FIG. 4 is omitted or simplified, and only other structures will be described in detail.

[0126] As shown in FIG. 7, a thin-film transistor T and an organic light-emitting element D are arranged in each of the sub-pixels SP1, SP2, and SP3 of the substrate 340.

[0127] The thin-film transistor T includes a semiconductor layer 312 disposed on the buffer layer 342, a gate electrode 314 disposed on the gate insulating layer 344, and a source electrode 315 and a drain electrode 316 disposed on the interlayer insulating layer 346.

[0128] A planarization layer 348 is formed on the thin-film transistor T, and a bank layer BNK is formed in a matrix between the sub-pixels SP1, SP2, and SP3 on the planarization layer 348. The bank layer BNK can be composed of a first bank layer BNK1 and a second bank layer BNK2 on top of it. In FIG. 7, the first bank layer BNK1 and the second bank layer BNK2 are formed with the same width, but the first bank layer BNK1 may be formed significantly wider than the second bank layer BNK2, and the first bank layer BNK1 may extend to both sides of the second bank layer BNK2. The first bank layer BNK1 can be composed of a hydrophilic substance, and the second bank layer BNK2 can be composed of a hydrophobic substance, but it is not limited thereto.

[0129] Openings are formed in the second bank layer BNK2 along the long side direction. In FIG. 7, two openings are formed, but it is not limited thereto, and two or more openings may be formed, or only one opening may be formed.

[0130] The opening is formed only in the second bank layer BNK2, and through the opening, the first bank layer BNK1 below it can be exposed to the outside, but it is not limited thereto. Only a part of the depth of the second bank layer BNK2 may be removed, and the bottom of the opening may be the second bank layer BNK2. All of the depth of the second bank layer BNK2 and a part of the first bank layer BNK1 may be removed, and the bottom of the opening may be the first bank layer BNK1.

[0131] The organic light-emitting elements D disposed in each of the sub-pixels SP1, SP2, and SP3 partitioned by the bank layer BNK include a first electrode 332, a light-emitting layer 334, and a second electrode 336. The first electrode 332, the light-emitting layer 334, and the second electrode 336 are respectively disposed in the sub-pixels SP1, SP2, and SP3 and are not connected to adjacent sub-pixels.

[0132] An auxiliary electrode 352 is disposed on the second bank layer BNK2, and a first pattern 354 and a second pattern 356 having an overhang structure are disposed on the auxiliary electrode 352. The auxiliary electrode 352 is also formed inside the opening. In FIG. 7, the auxiliary electrode 352 is formed only in a partial region of the opening, but may be formed in the entire region of the opening.

[0133] At this time, the opening can be formed on both sides of the first pattern 354, but it is not limited thereto.

[0134] The first electrode 332 of the organic light-emitting element D is formed on the planarization layer 348 in each of the sub-pixels SP1, SP2, and SP3, and the light-emitting layer 334 is formed on the first electrode 332. The second electrode 336 is formed on the light-emitting layer 334 and extends onto the second bank layer BNK2. At this time, the second electrode 336 extends over the side surfaces of the first bank layer BNK1 and the second bank layer BNK2, the upper surface of the second bank layer BNK2, the inside of the opening formed in the second bank layer BNK2, and the side surface of the first pattern 354.

[0135] Compared with the display device 100 of the first embodiment shown in FIG. 4, the second electrode 336 of this embodiment is also formed inside the opening, so the length of the second electrode 336 increases compared with the first embodiment.

[0136] Generally, the light-emitting layer 334 made of an organic material deteriorates due to the penetration of moisture and oxygen. Therefore, in order to prevent defects in the organic light-emitting element D, it is necessary to prevent the penetration of moisture and oxygen. Moisture and oxygen penetrate into the light-emitting layer 334 from the interface between the second electrode 336 and the bank layer BNK.

[0137] In this embodiment, an opening is formed to increase the length of the interface between the second electrode 336 and the second bank layer BNK2, and the penetration distance of moisture and oxygen can be increased. As a result, the penetration of moisture and oxygen into the light-emitting layer 334 can be reduced.

[0138] Also, in this embodiment, the auxiliary electrode 352 is formed in a partial region or the entire region of the opening, and the second electrode 336 extends into the opening, so the contact area between the second electrode 336 and the auxiliary electrode 352 is greatly increased by the opening. As a result, the signal delay in the second electrode 336 can be reduced over the entire display device 300.

[0139] The first sealing layers 382a, 382b, and 382c are respectively formed on the sub-pixels SP1, SP2, and SP3 partitioned by the second pattern 356. On top of them, the second sealing layer 384 and the third sealing layer 386 are disposed over the entire substrate 340, and the sealing layer 380 that seals the display device 300 is completed.

[0140] As described above, in the display device 300 of this embodiment, the bank layer BNK is made into two bank layers BNK1 and BNK2, an opening is formed in the upper second bank layer BNK2, and the second electrode 336 is formed in the opening, so that the electrical contact area between the second electrode 336 and the auxiliary electrode 352 can be increased, and the penetration of moisture and oxygen from the outside can be easily blocked.

[0141] FIG. 8 is a cross-sectional view showing the structure of a display device 400 according to a fourth embodiment of the present invention. Description of the same structure as that in the first embodiment of FIG. 4 will be omitted or simplified, and only other structures will be described in detail.

[0142] As shown in FIG. 8, a thin-film transistor T and an organic light-emitting element D are arranged in each of the sub-pixels SP1, SP2, and SP3 of the substrate 440.

[0143] The thin-film transistor T includes a semiconductor layer 412 disposed on the buffer layer 442, a gate electrode 414 disposed on the gate insulating layer 444, and a source electrode 415 and a drain electrode 416 disposed on the interlayer insulating layer 446.

[0144] A planarization layer 448 is formed on the thin-film transistor T, and a bank layer BNK is formed in a matrix between the sub-pixels SP1, SP2, and SP3 on the planarization layer 448.

[0145] A low-potential voltage wiring 458 is disposed on the bank layer BNK. The low-potential voltage wiring 458 is electrically connected to an external power supply unit and supplies an external low-potential voltage to the organic light-emitting element D. The low-potential voltage wiring 458 may be disposed on all the bank layers BNK formed on the substrate 440, or may be formed only on some of the bank layers BNK.

[0146] A first pattern 454 and a second pattern 456 having an overhang structure are formed on the low-potential voltage wiring 458. At this time, the width of the first pattern 454 is formed to be larger than that of the low-potential voltage wiring 458, the low-potential voltage wiring 458 is formed only below the first pattern 454, and is not formed outside the first pattern 454.

[0147] An opening is formed in the first pattern 454, and the low-potential voltage wiring 458 below it is exposed to the outside through the opening. The second pattern 456 is formed inside the opening. That is, a recess (opening) is formed in the first pattern 454, a convex portion 456a is formed in the second pattern 456, and the convex portion 456a of the second pattern 456 and the recess (opening) of the first pattern 454 fit together without a gap.

[0148] The auxiliary electrode 452 is formed on the bank layer BNK on the side surface of the first pattern 454, the upper surface of the first pattern 454 (that is, between the first pattern 454 and the second pattern 456), and inside the opening. At this time, the auxiliary electrode 452 is electrically connected to the power supply wiring 458 inside the opening.

[0149] The organic light-emitting elements D respectively arranged in the sub-pixels SP1, SP2, and SP3 partitioned by the bank layer BNK include a first electrode 432, a light-emitting layer 434, and a second electrode 436. The first electrode 432, the light-emitting layer 434, and the second electrode 436 are respectively arranged in the sub-pixels SP1, SP2, and SP3 and are not connected to adjacent sub-pixels.

[0150] The second electrode 436 is arranged on the light-emitting layer 434, extends to the upper surface of the auxiliary electrode 452 arranged on the side surface of the first pattern 454, and is electrically connected to the auxiliary electrode 452.

[0151] Compared with the display device 100 of the first embodiment shown in FIG. 4, in the display device 100 of the first embodiment, the auxiliary electrode 152 is arranged under the first pattern 154, and the second electrode 136 is in side contact with the auxiliary electrode 152. On the other hand, in the display device 400 of this embodiment, since the auxiliary electrode 452 is formed on a part of the upper surface of the bank layer BNK, the side surface, and the upper surface of the first pattern 452, the electrical contact area between the second electrode 436 and the auxiliary electrode 452 will increase. As a result, signal delay in the second electrode 436 can be prevented throughout the display device 400.

[0152] In the display device 400 of this embodiment, the low-potential voltage wiring 458 is formed not in the outer region of the display device 400 but on the bank layer BNK in the display region, and a low-potential voltage is applied to the second electrode 436 via the auxiliary electrode 452. Therefore, a uniform low-potential voltage can be applied across the entire display device 400.

[0153] Separate first sealing layers 482a, 482b, and 482c are formed on each of the sub-pixels SP1, SP2, and SP3 partitioned by the second pattern 456. On top of these, a second sealing layer 484 and a third sealing layer 486 are disposed across the entire substrate 440, completing the sealing layer 480 that seals the display device 400.

[0154] As described above, the embodiments of the present invention have been described in more detail with reference to the drawings. However, the present invention is not necessarily limited to these embodiments. The present invention can be variously modified within the scope not departing from the technical idea of the present invention. Therefore, the embodiments disclosed herein are for the purpose of explanation rather than for limiting the technical idea of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the above-described embodiments should all be understood as exemplary and non-limiting.

Description of Reference Numerals

[0155] 112... semiconductor layer 114... gate electrode 115... source electrode 116... drain electrode 132... first electrode 134... light-emitting layer 136... second electrode 140... substrate 142... buffer layer 144... gate insulating layer 146... interlayer insulating layer 148... planarization layer 152... auxiliary electrode 154... first pattern 156... second pattern 180... sealing layer BNK... bank layer D…Organic light-emitting device

Claims

1. A substrate including first to third sub-pixels; A bank layer disposed on the substrate and partitioning the first to third sub-pixels; Transistors respectively disposed in the first to third sub-pixels; At least one light-emitting element respectively disposed in the first to third sub-pixels and including a first electrode, a light-emitting layer, and a second electrode; An auxiliary electrode disposed on the bank layer; A first pattern and a second pattern of an overhang structure disposed on the bank layer; A plurality of first encapsulation layers respectively formed in the first to third sub-pixels and partitioned by the second pattern; and A display device, wherein the second electrode of the light-emitting element is electrically connected to the auxiliary electrode on the bank layer.

2. The display device according to claim 1, wherein the first pattern and the second pattern are disposed on the auxiliary electrode.

3. The display device according to claim 2, wherein the first pattern is made of an inorganic material and the second pattern is made of an amorphous semiconductor.

4. The display device according to claim 2, wherein the second electrode extends to a side surface of the first pattern and the second electrode is connected to a side surface of the auxiliary electrode.

5. The display device according to claim 2, further including a protection layer disposed between the auxiliary electrode and the first pattern.

6. The display device according to claim 5, wherein the protection layer is made of a material having stronger oxidizing property than the auxiliary electrode.

7. The display device according to claim 5, wherein a width of the protection layer is equal to a width of the auxiliary electrode.

8. The bank layer includes: A first bank layer; and A second bank layer disposed on the first bank layer and having at least one bank opening formed therein. The display device according to claim 1.

9. The display device according to claim 8, wherein the bank opening is formed on both sides of the first pattern and / or the second pattern.

10. The display device according to claim 9, wherein the auxiliary electrode is formed inside the bank opening and the second electrode is disposed on the auxiliary electrode inside the bank opening.

11. The display device according to claim 1, further including a low-potential voltage wiring disposed on the bank layer.

12. The display device according to claim 11, wherein the first pattern is disposed on the bank layer, a first pattern opening is formed in the first pattern, and the low-potential voltage wiring is exposed to the outside through the first pattern opening.

13. The display device according to claim 12, wherein the second pattern is formed in the first pattern opening portion.

14. The auxiliary electrode is formed on the side surface and the upper surface of the first pattern and inside the first pattern opening portion, and in the first pattern opening portion, the auxiliary electrode is electrically connected to the low potential voltage wiring. The display device according to claim 13.

15. The display device according to claim 14, wherein the second electrode is electrically connected to the auxiliary electrode formed on the side surface of the first pattern.

16. A second sealing layer formed over the entire substrate and covering the plurality of first sealing layers; The display device according to claim 1, further comprising a third sealing layer formed on the second sealing layer.

17. The light emitting layer is any one of an organic light emitting layer, an inorganic light emitting layer, a nano-sized material layer, a quantum dot, a micro LED light emitting layer, and a mini LED light emitting layer. The display device according to claim 1.

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