Gate drive part and display device including the same

Abstract

To provide a gate drive part and a display device including the same.SOLUTION: In a display part, a gate drive part comprises a plurality of signal transmission parts which are cascaded through a carry line applied with a carry signal from a signal transmission part of a precedent stage, and the plurality of signal transmission parts each include: a first output circuit which inputs a carry signal from a signal transmission part of a precedent stage and outputs a first gate signal according to the voltage between a (1-1)st node and a (1-2)nd control node; a second output part which outputs a second gate signal according to the voltage between a (2-1)st control node connected to the (1-2)nd control node and a (2-2)nd control node connected to the (1-1)st node; and a third output circuit part which outputs a third gate signal according to the voltage between a (3-1)st control node connected to the (1-2)nd control node and a (3-2)nd control node connected to the (1-1)st control node.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a gate driving unit and a display device including the same.

Background Art

[0002] Display devices include a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), a plasma display panel (PDP), and the like.

[0003] Electroluminescence display devices are roughly classified into inorganic electroluminescence display devices and organic electroluminescence display devices according to the material of the light-emitting layer. An active matrix type organic electroluminescence display device includes an organic light-emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle.

[0004] Some of the display devices, for example, a liquid crystal display device and an organic light-emitting display device, include a display panel including a plurality of pixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates a power supply for supplying the display panel or the driving unit. The driving unit includes a gate driving unit that supplies gate signals such as a scan signal and a light emission control signal to the display panel, and a data driving unit that supplies data signals to the display panel.

[0005] When such a display device supplies driving signals, for example, gate signals and data signals, to a plurality of pixels formed on the display panel, the selected pixels can transmit light or emit light by themselves, so that an image can be displayed.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Each of a plurality of pixels includes a pixel circuit, and a plurality of switching elements included in the pixel circuit are driven by a plurality of gate signals. As the number of switching elements increases, the number of gate signals may increase, but a gate driving unit that outputs only that number of gate signals and a signal line must be further provided, so that the size of the bezel increases.

[0007] An object of the present invention is to solve the above-described necessity and / or problems.

[0008] The present invention provides a gate driving unit and a display device including the same.

[0009] The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0010] The gate driving unit according to an embodiment of the present invention includes a plurality of signal transmission units connected in cascade through a carry line to which a carry signal is applied from a signal transmission unit in a previous stage, and each of the plurality of signal transmission units receives a carry signal from a signal transmission unit in a previous stage, and in response to voltages of a first-1 control node and a first-2 control node, a first output circuit unit that outputs a first gate signal; a second-1 control node connected to the first-2 control node; a second output circuit unit that outputs a second gate signal in response to voltages of a second-2 control node connected to the first-1 control node; a third-1 control node connected to the first-2 control node; and a third output circuit unit that outputs a third gate signal in response to voltages of a third-2 control node connected to the first-1 control node.

[0011] The display device according to an embodiment of the present invention includes a display panel on which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels are arranged, a data driving unit that supplies a data voltage of pixel data to the data lines, and a gate driving unit that supplies a gate signal to the gate lines. The gate driving unit includes a plurality of signal transmission units connected in cascade via a carry line to which a carry signal is applied from a signal transmission unit in a previous stage. Each of the plurality of signal transmission units receives a carry signal from a signal transmission unit in a previous stage, and includes a first output circuit unit that outputs a carry signal and a first gate signal according to voltages of a first-1 control node and a first-2 control node, a second-1 control node connected to the first-2 control node, a second output circuit unit that outputs a second gate signal according to voltages of a second-2 control node connected to the first-1 control node, a third-1 control node connected to the first-2 control node, and a third output circuit unit that outputs a third gate signal according to voltages of a third-2 control node connected to the first-1 control node.

Advantages of the Invention

[0012] The present invention can reduce the number of gate driving units by implementing one EM driving unit driven individually and two scan driving units with one gate driving unit, and can reduce the number of signal lines and the number of pins of pads therefor, thereby reducing the size of the bezel.

[0013] The present invention outputs a plurality of gate signals using an internal signal without using another external signal, so that power consumption is reduced and driving with low power is possible.

[0014] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Brief Description of the Drawings

[0015]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0016] The advantages, features, and the method of achieving them of the present invention will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but is embodied in various different forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those having ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention, and the present invention is only defined by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, so the present invention is not limited to the matters shown. Throughout the specification, the same reference numerals indicate the same components. Also, in explaining the present invention, when it is determined that a detailed explanation of related known technologies will obscure the gist of the present invention, the detailed explanation thereof will be omitted.

[0018] When terms such as "comprising", "including", "having", "consisting of", etc. mentioned in this specification are used, unless "only / solely" is used, other parts may be added. When a component is expressed in the singular, it includes the case of including a plurality unless there is a particularly explicit description.

[0019] In interpreting components, even without a separate explicit description, they are interpreted as including an error range.

[0020] In the case of an explanation of a positional relationship, for example, when the positional relationship between two parts is explained such as "on ~", "above ~", "below ~", "on the side of ~", etc., unless "immediately" or "directly" is used, one or more other parts can also be positioned between the two parts.

[0021] In the description of the embodiments, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical concept of the present invention.

[0022] Throughout the specification, the same reference numerals denote the same components.

[0023] The features of many embodiments can be partially or wholly combined or combined with each other, and various linkages and drives are technically possible. Each embodiment can also be implemented independently of each other or implemented together with a correlation relationship.

[0024] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) including an oxide semiconductor, or an LTPSTFT including low temperature poly silicon (LTPS).

[0026] A transistor is a three - electrode device that includes a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In the transistor, carriers flow out from the source. The drain is the electrode through which carriers exit the transistor to the outside. In a transistor, the flow of carriers is from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n - channel transistor, the direction of the current is from the drain to the source side. In the case of a p - channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain side, the current flows from the source to the drain side. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.

[0027] The gate signal can swing between a Gate On Voltage and a Gate Off Voltage. The Gate On Voltage is set to a voltage higher than the threshold voltage of the transistor. The Gate Off Voltage is set to a voltage lower than the threshold voltage of the transistor.

[0028] A transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a Gate High Voltage, and the gate-off voltage can be a Gate Low Voltage. In the case of a p-channel transistor, the gate-on voltage can be a Gate Low Voltage, and the gate-off voltage can be a Gate High Voltage.

[0029] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1.

[0030] Referring to FIGS. 1 and 2, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to the pixels of the display panel 100, and a power supply unit 400 that generates a power supply necessary for driving the pixels and the display panel driving circuit.

[0031] The display panel 100 includes a pixel array AA for displaying an input video. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels 101 arranged in a matrix.

[0032] The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel line share the gate line GL. The pixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period 1H is the time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0033] A touch sensor may be disposed on the display panel 100. The touch sensor is omitted in FIG. 1. Touch input may be sensed using a separate touch sensor or via pixels. The touch sensor may be disposed on the screen of the display panel in an on-cell type or an add-on type, or may be disposed in an in-cell type incorporated in the pixel array AA.

[0034] The display panel 100 may be embodied as a flexible display panel. The flexible display panel may be fabricated with a plastic OLED panel. An organic thin film may be disposed on the back plate of the plastic OLED panel, and a pixel array AA may be formed on the organic thin film.

[0035] The back plate of the plastic OLED may be a PET (Polyethylene terephthalate) substrate. An organic thin film is formed on the back plate. A pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture permeation so that the pixel array AA is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layer buffer film may be formed of an insulating material (not shown) on the organic thin film. Wiring for supplying power and signals applied to the pixel array AA and the touch sensor array may be formed on the organic thin film.

[0036] Each of the pixels may be divided into a red pixel (hereinafter referred to as "R pixel"), a green pixel (hereinafter referred to as "G pixel"), and a blue pixel (hereinafter referred to as "B pixel") for color representation. Each of the pixels may further include a white pixel. Each of the pixels 101 includes a pixel circuit. The pixel circuit is connected to a data line DL and a gate line GL.

[0037] The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light-emitting element layer EMIL, and an encapsulation layer ENC laminated on a substrate SUBS, as shown in FIG. 2.

[0038] The circuit layer CIR may include pixel circuits, a gate driver, a demultiplexer, etc. connected to wirings such as data lines, gate lines, and power lines. The circuit layer CIR includes a plurality of metal layers insulated with an insulating layer therebetween and a semiconductor material layer. All transistors formed in the circuit layer CIR may be embodied as n-channel OxideTFTs.

[0039] The light-emitting element layer EMIL may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a light-emitting element of a red sub-pixel, a light-emitting element of a green sub-pixel, and a light-emitting element of a blue sub-pixel. The light-emitting element layer EMIL may further include a light-emitting element of a white sub-pixel. In each of the sub-pixels, the light-emitting element layer EMIL may have a structure in which a light-emitting element and a color filter are laminated. The light-emitting element EL of the light-emitting element layer EMIL may be covered with a multi-layer protection layer including an organic film and an inorganic film.

[0040] The encapsulation layer ENC covers the light-emitting element layer EMIL so as to seal the circuit layer CIR and the light-emitting element layer EMIL. The encapsulation layer ENC may also have a structure of a multi-insulating film in which an organic film and an inorganic film are alternately laminated. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are laminated in multiple layers, the migration path of moisture and oxygen becomes longer compared to a single layer, and the penetration of moisture and oxygen that affects the light-emitting element layer EMIL can be effectively blocked.

[0041] On the sealing layer ENC, a touch sensor layer (omitted in the drawing) is formed, and a polarizing plate and a color filter layer can be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film can insulate the intersecting portions of the metal wiring pattern and flatten the surface of the touch sensor layer. The polarizing plate can convert the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer to improve visibility and contrast ratio. The polarizing plate can be implemented as a polarizing plate in which a linear polarizing plate and a retardation film are joined or a circular polarizing plate. A cover glass can be adhered onto the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer can absorb a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer, substitute for the role of the polarizing plate, and enhance the color purity of the video reproduced in the pixel array.

[0042] The power supply unit 400 generates a direct current (DC) voltage (or constant voltage) required for driving the pixel array of the display panel 100 and the display panel driving circuit by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 400 adjusts the level of the DC input voltage applied from a host system (not shown) to generate constant voltages such as a gamma reference voltage VGMA, a gate-on voltage VGH, VEH, a gate-off voltage VGL, VEL, a pixel driving voltage EVDD, a low-potential pixel base voltage EVSS, an initialization voltage VINIT, a reference voltage VREF, etc. The gamma reference voltage is supplied to the data driving unit 110. The gate-on voltage VGH and the gate-off voltage VGL are supplied to the gate driving unit 120. The constant voltages such as the pixel driving voltage EVDD, the pixel base voltage EVSS, the initialization voltage VINIT, the reference voltage VREF, etc. may be supplied to the pixel 101 via a power supply line commonly connected to the pixel 101.

[0043] Under the control of the timing controller 130, the display panel driving circuit writes pixel data of the input video into the pixels of the display panel 100.

[0044] The display panel driving circuit includes a data driving unit 110 and a gate driving unit 120.

[0045] A demultiplexer may be further provided between the data driving unit 110 and the data line DL. The demultiplexer is omitted in FIG. 1. The demultiplexer can reduce the number of channels of the data driving unit 110 by sequentially connecting one channel of the data driving unit 110 to a plurality of data lines DL and distributing the data voltage output from one channel of the data driving unit 110 to the data lines DL in a time-division manner.

[0046] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in FIG. 1. In a mobile device, a timing controller 130, a power supply unit 400, a data driving unit 110, etc. may be integrated into one drive IC (Integrated Circuit).

[0047] The data driving unit 110 uses a DAC (Digital to Analog Converter) to convert the pixel data of the input video received from the timing controller 130 every frame period into a gamma compensation voltage to generate a data voltage Vdata. The gamma reference voltage VGMA is divided by a voltage dividing circuit for each gradation. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driving unit 110. The data voltage Vdata is output from each channel of the data driving unit 110 through an output buffer.

[0048] In the data driving unit 110, the output buffer included in one channel may be connected to adjacent data lines DL through a demultiplexer. The demultiplexer may be formed directly on the substrate of the display panel 100 or integrated into one drive IC together with the data driving unit 110.

[0049] The gate driving unit 120 may be implemented by a GIP (Gate in panel) circuit formed directly on the bezel region BZ on the display panel 100 together with the TFT array of the pixel array AA. The gate driving unit 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driving unit 120 can sequentially supply those signals to the gate lines GL by shifting the gate signals using a shift register.

[0050] The clock output from the level shifter 140 can swing between the gate-on voltage VGH and the gate-off voltage VGL and be supplied to the gate driver 120 via the clock line CL. The gate driver 120 can sequentially output gate signals using the clock output from the level shifter 140.

[0051] The timing controller 130 receives digital video data DATA of the input video and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, and a data enable signal (Data Enable) DE, etc. Since the vertical period and the horizontal period can be known by the method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of 1 horizontal period (1H).

[0052] The timing controller 130 can multiply the input frame frequency by i times and control the operation timing of the display panel driving circuit at a frame frequency of Xi (i is a positive integer greater than 0) Hz of the input frame frequency. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase-Alternating Line) system.

[0053] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0054] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into the gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL via a level shifter (not shown) and supplied to the gate driver 120. That is, the level shifter converts the low level voltage of the gate timing control signal into the gate low voltages VGL and VEL, and converts the high level voltage of the gate timing control signal into the gate high voltages VGH and VEH. The gate timing control signal includes a start pulse and a shift clock.

[0055] The host system can be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system. At this time, in the mobile device and the wearable device, the data driver 110, the gate driver 120, the timing controller 130, etc. can be integrated into one drive IC (DIC).

[0056] FIG. 3 is a diagram showing a pixel circuit according to the first embodiment of the present invention, and FIG. 4 is a diagram showing the driving timing of the pixel circuit shown in FIG. 3.

[0057] Referring to FIG. 3, the pixel circuit according to the first embodiment of the present invention includes a light emitting element EL, a driving element DT that supplies current to the light emitting element EL, a plurality of switch elements T1 to T5 that switch the current path connected to the driving element DT, a first capacitor Cst that stores the voltage between the gate and source of the driving element DT, and a second capacitor C2. The driving element DT and the switch elements T1 to T7 can be implemented by n-channel TFTs, but are not limited thereto.

[0058] The light-emitting element EL emits light by the current applied through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT that changes according to the data voltage Vdata. The light-emitting element EL can be embodied as an OLED including an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, an electron injection layer EIL, and the like. The anode of the light-emitting element EL is connected to the driving element DT via the fourth node n4, and the cathode of the light-emitting element EL is connected to a pixel base voltage line to which the pixel base voltage EVSS is applied, or the second power supply line 42.

[0059] The OLED used for the light-emitting element EL may have a tandem structure in which a plurality of light-emitting layers are stacked. The OLED with a tandem structure can improve the luminance and lifetime of the pixel.

[0060] The driving element DT supplies a current to the light-emitting element EL according to the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a gate electrode connected to the second node n2, a first electrode (or drain) connected to the first node n1, and a second electrode (or source) connected to the third node n3.

[0061] The first switch element T1 is turned on according to the gate-on voltage of the first EM signal EM1 to supply the pixel driving voltage EVDD to the driving element DT. The first switch element T1 includes a gate electrode to which the first EM signal EM1 is applied, a first electrode connected to a pixel driving voltage line or the first power supply line 41 to which the pixel driving voltage is applied, and a second electrode connected to the first node n1.

[0062] The second switch element T2 is turned on according to the gate-on voltage of the first scan signal SCAN1, connects the data line DL to the second node n2, and applies the data voltage Vdata. The second switch element T2 includes a gate electrode to which the first scan signal SCAN1 is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0063] The third switch element T3 is turned on according to the gate-on voltage of the second scan signal SCAN2, connects the reference voltage line or the third power supply line 43 to the second node n2, and applies the reference voltage Vref. The third switch element T3 includes a gate electrode to which the second scan signal SCAN2 is applied, a first electrode connected to the third power supply line 43, and a second electrode connected to the second node n2.

[0064] The fourth switch element T4 is turned on according to the gate-on voltage of the second EM signal EM2, and connects the third node n3 and the fourth node n4. The fourth switch element T4 includes a gate electrode to which the second EM signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0065] The fifth switch element T5 is turned on according to the gate-on voltage of the third scan signal SCAN3, connects the initialization voltage line or the fourth power supply line 44 to the fourth node n4, and applies the initialization voltage Vinit. The fifth switch element T5 includes a gate electrode to which the third scan signal SCAN3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth power supply line 44.

[0066] The first capacitor Cst can be connected between the second node n2 and the third node n3. The first capacitor Cst can charge the gate-source voltage Vgs of the driving element DT.

[0067] The second capacitor C2 can be connected between the third node n3 and the first power supply line 41.

[0068] Referring to FIGS. 3 to 4, the pixel circuit according to the embodiment of the present invention can be driven in the order of an initialization stage Tini, a sensing stage Ts, a data writing stage Tw, an OBS stage Tobs, and a light emitting stage Tem.

[0069] In the initialization stage Tini, the pixel circuit is initialized. The reference voltage Vref initializes the second node n2, and the initialization voltage initializes the third node n3. In the sensing stage Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst.

[0070] In the data writing stage Tw, the data voltage Vdata of the pixel data is applied to the first node n1.

[0071] In the OBS stage Tobs, the initialization voltage Vinit is applied to the third node n3 and initialized. Then, in the light emitting stage Tem, after the voltages of the second node n2 and the third node n3 rise, the light emitting element EL can emit light with a luminance corresponding to the gradation value of the pixel data.

[0072] FIG. 5 is a diagram showing the configuration of the gate driving unit according to the embodiment of the present invention, and FIG. 6 is a diagram for explaining the signal application principle of the third gate driving unit shown in FIG. 5.

[0073] Since five gate signals, namely, SCAN1, SCAN2, SCAN3, EM1, and EM2, are required for the pixel circuit shown in FIG. 3, five individual gate driving units must be configured. In order to reduce the number of gate driving units and reduce the size of the bezel, in the embodiment, an attempt is made to configure one gate driving unit that outputs a plurality of gate signals.

[0074] At this time, the gate driving unit that outputs SCAN1 may be implemented in a shift register type, and the gate driving units that output SCAN2, SCAN3, EM1, and EM2 may be implemented in an edge trigger type. Therefore, in the embodiment, SCAN2, SCAN3, and EM2 of the same type can be implemented by one gate driving unit.

[0075] Referring to FIG. 5, the gate driving unit 120 according to an embodiment of the present invention may be configured to include a first gate driving unit 121 that outputs a first scan signal SCAN1, a second gate driving unit 122 that outputs a first EM signal EM1, and a third gate driving unit 123 that outputs a second scan signal SCAN2, a third scan signal SCAN3, and a second EM signal EM2.

[0076] Referring to FIG. 6, the third gate driving unit 123 according to the embodiment can apply the second scan signal SCAN2, the third scan signal SCAN3, and the second EM signal EM2 to the pixel circuit.

[0077] As an example, the third gate driving unit 123 can apply the second scan signal SCAN2(1), the third scan signal SCAN3(1), and the second EM signal EM2(1) to the first pixel circuit P1.

[0078] As another example, the third gate driving unit 123 can apply the second scan signal SCAN2(n), the third scan signal SCAN3(n), and the second EM signal EM2(n) to the nth pixel circuit Pn.

[0079] FIG. 7 is a diagram schematically showing a shift register of a gate driving unit according to an embodiment of the present invention.

[0080] Referring to FIG. 7, the gate driving unit according to the embodiment includes a shift register that sequentially outputs gate signals in synchronization with a shift clock CLK.

[0081] The shift register includes a plurality of signal transmission units ST_D(1), ST_D(2), ST(1), …, ST(n - 2), ST(n - 1), ST(n) that are cascade-connected (subordinately connected) via a carry line through which a carry signal is transmitted.

[0082] The start signal VST is generally input to the first signal transmission unit. Here, the first dummy signal transmission unit ST_D(1) can be the first signal transmission unit to which the start signal VST is input.

[0083] Each of the signal transmission units ST_D(1), ST_D(2), ST(1), …, ST(n - 2), ST(n - 1), ST(n) receives a start pulse or a carry signal output from the previous signal transmission unit, and a shift clock CLK is input. The first signal transmission unit ST_D(1) starts to be driven in response to the start pulse VST, and the other signal transmission units ST_D(2), ST(1), …, ST(n - 2), ST(n - 1), ST(n) start to be driven when a carry signal from the previous signal transmission unit is input. The shift clock CLK can be an N (N is a positive integer of 2 or more) - phase clock. For example, the shift clock CLK can be a two - phase clock CLK1, CLK2. The phases of the two - phase shift clocks CLK1, CLK2 are opposite to each other.

[0084] Each of the signal transmission units ST(1), …, ST(n - 2), ST(n - 1), ST(n) can output a first EM pulse EM2(n) via a first output node, output a second scan signal SCAN2(n) via a second output node, and output a third scan signal SCAN3(n) via a third output node while outputting.

[0085] FIG. 8 is a circuit diagram showing in detail a first EM driving unit according to an embodiment of the present invention, and FIG. 9 is a diagram showing the driving waveform of the first EM driving unit shown in FIG. 8.

[0086] Referring to FIGS. 8 to 9, the first EM driving unit according to the embodiment can output a first EM signal EM1(n) and can include a plurality of transistors T1 to T7.

[0087] When the shift clock CLK is at a high voltage (VGH2) that is equal to or higher than the gate-on voltage VEH, the first transistor T1 is turned on to supply the voltage of the carry signal C(n - 1) to the buffer node Qh. The first transistor T1 includes a first electrode connected to the (n - 1)-th carry signal line C(n - 1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0088] When the shift clock CLK is at a voltage (VGH2) that is equal to or higher than the gate-on voltage VEH, the second transistor T1A is turned on to supply the voltage of the buffer node Qh to the first control node Q(n) to charge the first control node. The second transistor T1A includes a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first control node Q(n).

[0089] The first and second transistors T1 and T1A are connected in series. The first and second transistors T1 and T1A are connected in series between the (n - 1)-th carry signal line C(n - 1) and the first control node Q(n).

[0090] When the first control node Q(n) is charged, the 3q-th transistor T3q is turned on to supply the second high potential voltage to the buffer node Qh via the second high potential voltage line GVDD1. The second high potential voltage GVDD1 is supplied to the buffer node Qh via the second high potential voltage line. The 3q-th transistor T3q includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first control node Q(n), and a second electrode connected to the buffer node Qh.

[0091] When the voltages of the 41st transistor T41 and the 41Ath transistor T41A are higher than or equal to the gate-on voltage VEH, the transistors are turned on to supply the second high-potential voltage GVDD1 to the first node 80 and charge the first node 80 to a voltage higher than or equal to the gate-on voltage VEH. The 41st transistor T41 includes a first electrode connected to the second high-potential voltage line GVDD1, a gate electrode connected to the second control node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1), and a second electrode connected to the first electrode of the 41Ath transistor T41A. The 41Ath transistor T41A includes a first electrode connected to the second electrode of the 41st transistor T41, a gate electrode connected to the second control node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1), and a second electrode connected to the first node 80.

[0092] When the voltage of the first node 80 is higher than or equal to the gate-on voltage VEH, the 4th transistor T4 and the 4Ath transistor T4A are turned on to connect the second high-potential voltage line GVDD1 to the second control node Qb(n), thereby charging the second control node Qb(n) to a voltage higher than or equal to the gate-on voltage VEH. The 4th transistor T4 includes a first electrode connected to the second high-potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the 4Ath transistor T4A. The 4Ath transistor T4A includes a first electrode connected to the second electrode of the 4th transistor T4, a gate electrode connected to the first node 80, and a second electrode connected to the second control node Qb(n). The first capacitor CF is connected between the gate electrode and the second electrode of the 4Ath transistor T4A. When the 4Ath transistor T4A is turned on by the first capacitor CF, the voltage of the first node 80 can be boosted.

[0093] The transistor T4q of the 4q turns on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, and connects the first node 80 to the second control node Qb(n). The transistor T4q of the 4q includes a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the second control node Qb(n).

[0094] The transistor T5q of the 5q turns on when the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, connects the second control node Qb(n) to the second low-potential voltage line GVSS1, and discharges the voltage of the second control node Qb(n) to the second low-potential voltage. The transistor T5q of the 5q includes a first electrode connected to the second control node Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low-potential voltage line GVSS1.

[0095] The first pull-up transistor T6 and the first pull-down transistor T7 charge and discharge the first output node according to the voltages of the first control node Q(n) and the second control node Qb(n), and output the first EM signal EM1(n). The first pull-up transistor T6 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the first high-potential voltage line to which the first high-potential voltage is applied, and a second electrode connected to the first output node. The first pull-down transistor T7 is connected to the first pull-up transistor T6 with the first output node interposed therebetween. The first pull-down transistor T7 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the first output node, and a second electrode connected to the first low-potential voltage line GVSS0 to which the first low-potential voltage is applied. The second capacitor CB is connected between the gate electrode and the second electrode of the first pull-up transistor T6. When the first pull-up transistor T6 is turned on by the second capacitor CB, the voltage of the first control node Q(n) can be boosted.

[0096] The second pull-up transistor T6cr and the second pull-down transistor T7cr charge and discharge the second output node according to the voltages of the first control node Q(n) and the second control node Qb(n), and output the carry signal EM1_C(n) of the first EM driving unit. The second pull-up transistor T6cr includes a gate electrode connected to the first control node Q(n), a first electrode connected to a second high potential voltage line GVDD1 to which a second high potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T7cr is connected to the second pull-up transistor T6cr with the second output node therebetween. The second pull-down transistor T7cr includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the second output node, and a second electrode connected to a second low potential voltage line GVSS1 to which a second low potential voltage is applied.

[0097] FIG. 10 is a circuit diagram showing in detail a gate driving unit according to an embodiment of the present invention.

[0098] Referring to FIG. 10, the gate driving unit according to the embodiment includes a first output circuit unit 71 that outputs a first gate signal, a second output circuit unit 72 that outputs a second gate signal, and a third output circuit unit 73 that outputs a third gate signal.

[0099] The first output circuit unit 71 can output a first gate signal, for example, a second EM signal EM2(n). Such a first output circuit unit 71 includes transistors T1 to T13 of 1-1 to 1-13.

[0100] The transistor T1 of 1-1 is turned on when the shift clock CLK is a high voltage (VGH2) equal to or higher than the gate-on voltage VEH, and supplies the voltage of the (n-1)th carry signal line C(n-1) of the previous signal transmission unit to the buffer node Qh. The transistor T1 of 1-1 includes a first electrode connected to the (n-1)th carry signal line C(n-1), a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the buffer node Qh.

[0101] The first to second transistors T2 turn on when the shift clock CLK is a voltage (VGH2) equal to or higher than the gate-on voltage VEH, and supply the voltage of the buffer node Qh to the first to first control node Q(n) to charge the first control node. The first to second transistors T2 include a first electrode connected to the buffer node Qh, a gate electrode to which the shift clock CLK is applied, and a second electrode connected to the first to first control node Q(n).

[0102] The first to first and first to second transistors T1 and T2 are connected in series. The first to first and first to second transistors T1 and T2 are connected in series between the (n - 1)-th carry signal line C(n - 1) and the first to first control node Q(n).

[0103] The first to third transistor T3 turns on when the first to first control node Q(n) is charged, and supplies the second high potential voltage to the buffer node Qh via the second high potential voltage line GVDD1. The second high potential voltage GVDD1 is supplied to the buffer node Qh via the second high potential voltage line GVDD1. The first to third transistor T3 includes a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first to first control node Q(n), and a second electrode connected to the buffer node Qh.

[0104] When the voltages of the first to fourth transistors T4 and the first to fifth transistors T5 are higher than or equal to the gate-on voltage VEH at the first and second control nodes Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), they are turned on to supply the second high potential voltage GVDD1 to the first node 80, charging the first node 80 to a voltage higher than or equal to the gate-on voltage VEH. The first to fourth transistors T4 include a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first and second control nodes Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first electrode of the first to fifth transistors T5. The first to fifth transistors T5 include a first electrode connected to the second electrode of the first to fourth transistors T4, a gate electrode connected to the first and second control nodes Qb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1), and a second electrode connected to the first node 80.

[0105] When the voltage of the first to sixth transistors T6 and the first to seventh transistors T7 is higher than or equal to the gate-on voltage VEH at the first node 80, they are turned on to connect the second high potential voltage line GVDD1 to the first and second control nodes Qb(n), charging the first and second control nodes Qb(n) to a voltage higher than or equal to the gate-on voltage VEH. The first to sixth transistors T6 include a first electrode connected to the second high potential voltage line GVDD1, a gate electrode connected to the first node 80, and a second electrode connected to the first electrode of the first to seventh transistors T7. The first to seventh transistors T7 include a first electrode connected to the second electrode of the first to sixth transistors T6, a gate electrode connected to the first node 80, and a second electrode connected to the first and second control nodes Qb(n). The first capacitor CF is connected between the gate electrode and the second electrode of the first to seventh transistors T7. When the first to seventh transistors T7 are turned on by the first capacitor CF, the voltage of the first node n1 can be boosted.

[0106] When the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, the first to eighth transistors T8 are turned on to connect the first node 80 to the first and second control nodes Qb(n). The first to eighth transistors T8 include a first electrode connected to the first node 80, a gate electrode connected to the buffer node Qh, and a second electrode connected to the first and second control nodes Qb(n).

[0107] When the voltage of the buffer node Qh is a high voltage equal to or higher than the gate-on voltage VEH, the first to ninth transistors T9 are turned on to connect the first and second control nodes Qb(n) to the second low-potential voltage line GVSS1, discharging the voltage of the first and second control nodes Qb(n) to the second low-potential voltage. The first to ninth transistors T9 include a first electrode connected to the first and second control nodes Qb(n), a gate electrode connected to the buffer node Qh, and a second electrode connected to the second low-potential voltage line GVSS1.

[0108] The first to tenth transistor or the first pull-up transistor T10 and the first to eleventh transistor or the first pull-down transistor T11 charge and discharge the first output node OUT1-1 according to the voltages of the first control node Q(n) and the first and second control nodes Qb(n), outputting a second gate signal, for example, the second EM signal EM2(n). The first pull-up transistor T10 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the first high-potential voltage line GVDD0 to which the first high potential voltage is applied, and a second electrode connected to the first output node OUT1-1. The first pull-down transistor T11 is connected to the first pull-up transistor T10 with the first output node OUT1-1 interposed therebetween. The first pull-down transistor T11 includes a gate electrode connected to the first and second control nodes Qb(n), a first electrode connected to the first output node OUT1-1, and a second electrode connected to the first low-potential voltage line GVSS0 to which the first low potential voltage is applied.

[0109] The 1st to 12th transistors or the 1st to 2nd pull-up transistors T12, and the 1st to 13th transistors or the 1st to 2nd pull-down transistors T13 charge and discharge the 1st to 2nd output node OUT1-2 according to the voltages of the 1st control node Q(n) and the 1st to 2nd control node Qb(n), and output a carry signal EM2_C(n). The 1st to 2nd pull-up transistor T12 includes a gate electrode connected to the 1st control node Q(n), a 1st electrode connected to a 2nd high potential voltage line GVDD1 to which a 2nd high potential voltage is applied, and a 2nd electrode connected to the 1st to 2nd output node OUT1-2. The 1st to 2nd pull-down transistor T13 is connected to the 1st to 2nd pull-up transistor T12 with the 1st to 2nd output node OUT1-2 therebetween. The 1st to 2nd pull-down transistor T13 includes a gate electrode connected to the 1st to 2nd control node Qb(n), a 1st electrode connected to the 1st to 2nd output node OUT1-2, and a 2nd electrode connected to a 2nd low potential voltage line GVSS1 to which a 2nd low potential voltage is applied.

[0110] The 2nd output circuit section 72 can output a 2nd gate signal, for example, a 2nd SCAN signal SCAN2(n). Such a 2nd output circuit section 72 includes transistors T21 to T29 of 2-1 to 2-9.

[0111] The 2-1st transistor T21 connects the 2nd low potential voltage line GVSS1 to the 2-1st node 81 according to the voltage of the carry signal line EM2_C(n) of the 1st output circuit section 71, and discharges it to the 2nd low potential voltage. The 2-1st transistor T21 includes a gate electrode connected to the carry signal line EM2_C(n), a 1st electrode connected to the 2nd low potential voltage line GVSS1, and a 2nd electrode connected to the 2-1st node 81.

[0112] The second - second transistor T22 connects the first - second control node Qb(n) of the first output circuit section 71 to the second - first control node Q’(n) according to the voltage of the second - first node 81. The second - second transistor T22 includes a gate electrode connected to the second - first node 81, a first electrode connected to the first - second control node Qb(n) of the first output circuit section 71, and a second electrode connected to the second - first control node Q’(n).

[0113] The second - third transistor T23 connects the carrier signal line EM1_C(n) of the first EM driving section to the second - first node 81 according to the voltage of the first - second control node Qb(n) of the first output circuit section 71. The second - third transistor T23 includes a gate electrode connected to the first - second control node Qb(n) of the first output circuit section 71, a first electrode connected to the carrier signal line EM1_C(n) of the first EM driving section, and a second electrode connected to the second - first node 81.

[0114] The second - fourth transistor T24 connects the first - first control node Q(n) of the first output circuit section 71 to the second - second control node Qb’(n) according to the voltage of the second - first node 81. The second - fourth transistor T24 includes a gate electrode connected to the second - first node 81, a first electrode connected to the first - first control node Q(n) of the first output circuit section 71, and a second electrode connected to the second - second control node Qb’(n).

[0115] The second - fifth transistor T25 connects the second control node Qb(n) of the first EM driving section to the second - second node 82 according to the voltage of the second control node Qb(n) of the first EM driving section. The second - fifth transistor T25 includes a gate electrode and a first electrode connected to the second control node Qb(n) of the first EM driving section, and a second electrode connected to the second - second node 82.

[0116] The transistors T26 of 2-6 discharge the control node Q'(n) of 2-1 to the second low potential voltage according to the voltage of the node 82 of 2-2. The transistor T26 of 2-6 includes a gate electrode connected to the node 82 of 2-2, a first electrode connected to the control node Q'(n) of 2-1, and a second electrode connected to the second low potential voltage line GVSS1.

[0117] The transistor T27 of 2-7 charges the control node Qb'(n) of 2-2 with the second high potential voltage GVDD1 according to the voltage of the node 82 of 2-2. The transistor T27 of 2-7 includes a gate electrode connected to the node 82 of 2-2, a first electrode connected to the control node Qb'(n) of 2-2, and a second electrode connected to the second high potential voltage line GVDD1.

[0118] The transistor T28 of 2-8 or the second pull-up transistor T28 and the transistor T29 of 2-9 or the second pull-down transistor T29 charge and discharge the second output node OUT2 according to the voltages of the control node Q'(n) of 2-1 and the control node Qb'(n) of 2-2, and output a second gate signal, for example, the second SCAN signal SCAN2(n). The second pull-up transistor T28 includes a gate electrode connected to the control node Q'(n) of 2-1, a first electrode connected to the first high potential voltage line GVDD0 to which the first high potential voltage is applied, and a second electrode connected to the second output node. The second pull-down transistor T29 is connected to the second pull-up transistor T28 with the second output node OUT2 interposed therebetween. The second pull-down transistor T29 includes a gate electrode connected to the control node Qb'(n) of 2-2, a first electrode connected to the second output node OUT2, and a second electrode connected to the first low potential voltage line GVSS0 to which the first low potential voltage is applied.

[0119] The third output circuit unit 73 can output a third gate signal, for example, the third SCAN signal SCAN3(n). Such a third output circuit unit 73 includes transistors T31 to T38 of 3-1 to 3-8.

[0120] The 3-1st transistor T31 connects the 1-2nd control node Qb(n) of the 1st output circuit section 71 to the 3-1st control node Q''(n) according to the voltage of the 1-2nd control node Qb(n-1) of the (n-1)th signal transmission section ST(n-1). The 3-1st transistor T31 includes a gate electrode connected to the 1-2nd control node Qb(n-1) of the (n-1)th signal transmission section ST(n-1), a 1st electrode connected to the 1-2nd control node Qb(n) of the 1st output circuit section 71, and a 2nd electrode connected to the 3-1st control node Q''(n).

[0121] The 3-2nd transistor T32 connects the 1-1st control node Q(n) to the 3-2nd control node Qb''(n) according to the voltage of the 1-2nd control node Qb(n-1) of the (n-1)th signal transmission section ST(n-1). The 3-2nd transistor T32 includes a gate electrode connected to the 1-2nd control node Qb(n-1) of the (n-1)th signal transmission section ST(n-1), a 1st electrode connected to the 1-1st control node Q(n), and a 2nd electrode connected to the 3-2nd control node Qb''(n).

[0122] The 3-3rd transistor T33 connects the 2-2nd node 82 to the 2-3rd node 83 according to the voltage of the carrier signal line EM1_C(n) of the 1st EM driving section. The 3-3rd transistor T33 includes a gate electrode connected to the carrier signal line EM1_C(n) of the 1st EM driving section, a 1st electrode connected to the 2-2nd node 82, and a 2nd electrode connected to the 2-3rd node 83.

[0123] The 3-4th transistor T34 connects the carrier signal line EM2_C(n) to the 2-3rd node 83 according to the voltage of the carrier signal line EM1_C(n) of the 1st EM driving section. The 3-4th transistor T34 includes a gate electrode connected to the carrier signal line EM1_C(n) of the 1st EM driving section, a 1st electrode connected to the carrier signal line EM2_C(n), and a 2nd electrode connected to the 2-3rd node 83.

[0124] The third to fifth transistors T35 discharge the third to first control node Q''(n) to the second low potential voltage according to the voltage of the second to third node 83. The third to fifth transistor T35 includes a gate electrode connected to the second to third node 83, a first electrode connected to the third to first control node Q''(n), and a second electrode connected to the second low potential voltage line GVSS1.

[0125] The third to sixth transistor T36 charges the third to second control node Qb''(n) with the second high potential voltage according to the voltage of the second to third node 83. The third to sixth transistor T36 includes a gate electrode connected to the second to third node 83, a first electrode connected to the third to second control node Qb''(n), and a second electrode connected to the second high potential voltage line GVDD1.

[0126] The third to seventh transistor or the third pull-up transistor T37 and the third to eighth transistor or the third pull-down transistor T38 charge and discharge the third output node OUT3 according to the voltages of the third to first control node Q''(n) and the third to second control node Qb''(n), and output a third gate signal, for example, the third SCAN signal SCAN3(n). The third pull-up transistor T37 includes a gate electrode connected to the third to first control node Q''(n), a first electrode connected to the first high potential voltage line GVDD0 to which the first high potential voltage is applied, and a second electrode connected to the third output node OUT3. The third pull-down transistor T38 is connected to the third pull-up transistor T37 with the third output node OUT3 interposed therebetween. The third pull-down transistor T38 includes a gate electrode connected to the third to second control node Qb''(n), a first electrode connected to the third output node OUT3, and a second electrode connected to the first low potential voltage line GVSS0 to which the first low potential voltage is applied.

[0127] FIG. 11 is a diagram showing the driving waveform of the gate driving unit shown in FIG. 10, and FIGS. 12 to 17 are diagrams for explaining the operating principle of the gate driving unit according to FIG. 11.

[0128] Referring to FIGS. 11 and 12, in interval (1), the first control node Q(n) of the first output circuit section becomes a high voltage, the second control node Qb(n) becomes a low voltage, and the first carry signal and the first gate signal output a high voltage.

[0129] The first control node Q’(n) of the second output circuit section becomes a low voltage, the second control node Qb’(n) becomes a high voltage, and the second gate signal outputs a low voltage.

[0130] The first control node Q’’(n) of the third output circuit section becomes a low voltage, the second control node Qb’’(n) becomes a high voltage, and the third gate signal outputs a low voltage.

[0131] Referring to FIGS. 11 and 13, in interval (2), the first control node Q(n) of the first output circuit section holds a high voltage, the second control node Qb(n) holds a low voltage, and the first carry signal and the first gate signal hold a high voltage.

[0132] The first control node Q’(n) of the second output circuit section becomes a low voltage, the second control node Qb’(n) becomes a high voltage, and the second gate signal holds a low voltage.

[0133] The first control node Q’’(n) of the third output circuit section becomes a low voltage, the second control node Qb’’(n) becomes a high voltage, and the third gate signal holds a low voltage.

[0134] Referring to FIGS. 11 and 14, in interval (3), the first control node Q(n) of the first output circuit section becomes a low voltage, the second control node Qb(n) becomes a high voltage, and the first carry signal and the first gate signal output a low voltage.

[0135] The first control node Q’(n) of the second output circuit section becomes a high voltage, the second control node Qb’(n) becomes a low voltage, and the second gate signal outputs a high voltage.

[0136] The 3-1 control node Q’’(n) of the third output circuit section becomes a high voltage, the 3-2 control node Qb’’(n) becomes a low voltage, and the third gate signal outputs a high voltage.

[0137] Referring to FIGS. 11 and 15, in interval (4), the 1-1 control node Q(n) of the first output circuit section holds a low voltage, the 1-2 control node Qb(n) holds a high voltage, and the 1-1 carry signal and the first gate signal hold a low voltage.

[0138] The 2-1 control node Q’(n) of the second output circuit section becomes a high voltage, the 2-2 control node Qb’(n) becomes a low voltage, and the second gate signal outputs a low voltage.

[0139] The 3-1 control node Q’’(n) of the third output circuit section becomes a high voltage, the 3-2 control node Qb’’(n) becomes a low voltage, and the third gate signal holds a high voltage.

[0140] Referring to FIGS. 11 and 16, in interval (5), the 1-1 control node Q(n) of the first output circuit section becomes a high voltage, the 1-2 control node Qb(n) becomes a low voltage, and the 1-1 carry signal and the first gate signal output a high voltage.

[0141] The 2-1 control node Q’(n) of the second output circuit section becomes a low voltage, the 2-2 control node Qb’(n) becomes a high voltage, and the second gate signal holds a low voltage.

[0142] The 3-1 control node Q’’(n) of the third output circuit section holds a high voltage, the 3-2 control node Qb’’(n) holds a low voltage, and the third gate signal holds a high voltage.

[0143] Referring to FIGS. 11 and 17, in section (6), the first control node Q(n) of the first output circuit section holds a high voltage, the first - 2 control node Qb(n) holds a low voltage, and the first - 1 carry signal and the first gate signal hold a high voltage.

[0144] The first control node Q’(n) of the second output circuit section becomes a low voltage, the second - 2 control node Qb’(n) becomes a high voltage, and the second gate signal holds a low voltage.

[0145] The first control node Q’’(n) of the third output circuit section becomes a low voltage, the third - 2 control node Qb’’(n) becomes a high voltage, and the third gate signal outputs a low voltage.

[0146] FIG. 18 is a diagram showing the simulation results of the gate driving section according to the embodiment.

[0147] Referring to FIG. 18, it shows the output waveforms of the first EM signal EM1(n), the second EM signal EM2(n), the second scan signal SCAN2(n), and the third scan signal SCAN3(n) of the first EM driving section, the second EM driving section, the second scan driving section, and the third scan driving section according to the embodiment.

[0148] As described above, the embodiments of the present invention have been described in more detail with reference to the accompanying drawings. However, the present invention is not necessarily limited to such embodiments, and various modifications can be made without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are for the purpose of explanation rather than for limiting the technical idea of the present invention, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary and non - limiting in all respects. The protection scope of the present invention should be interpreted according to the claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of the rights of the present invention.

Explanation of Reference Signs

[0149] 100: Panel 110: Data driving unit 120: Gate driving unit 130: Timing controller 400: Power supply unit

Claims

1. A plurality of signal transmission units connected in cascade via a carry line to which a carry signal is applied from a signal transmission unit in the previous stage, each of the plurality of signal transmission units, receives the carry signal from the signal transmission unit in the previous stage, and outputs the carry signal and a first gate signal according to voltages of a first - 1 control node and a first - 2 control node, a first output circuit unit; a second output circuit unit that outputs a second gate signal according to voltages of a second - 1 control node connected to the first - 2 control node and a second - 2 control node connected to the first - 1 control node; a gate driving unit including a third output circuit unit that outputs a third gate signal according to voltages of a third - 1 control node connected to the first - 2 control node and a third - 2 control node connected to the first - 1 control node.

2. The first output circuit unit, a first - 1 pull - up and a first - 1 pull - down transistor that output the first gate signal to a first - 1 output node according to voltages of the first - 1 and the first - 2 control nodes; a first - 2 pull - up and a first - 2 pull - down transistor that output the carry signal to a first - 2 output node according to voltages of the first - 1 and the first - 2 control nodes, the gate driving unit according to claim 1.

3. The second output circuit unit, including a second - 1 pull - up and a second - 1 pull - down transistor that output the second gate signal to a second output node according to voltages of the second - 1 and the second - 2 control nodes, the gate driving unit according to claim 2.

4. The second output circuit unit further includes a second - 1 transistor, a second - 2 transistor, a second - 3 transistor, and a second - 4 transistor, the second - 1 transistor includes a gate electrode connected to the first - 2 output node, a first electrode connected to a low - potential voltage line, and a second electrode connected to a second - 1 node; the second - 2 transistor includes a gate electrode connected to the second - 1 node, a first electrode connected to the first - 2 control node, and a second electrode connected to the second - 1 control node; The second to third transistors include a gate electrode connected to the first to second control nodes, a first electrode connected to the carrier signal line of the first EM driving unit, and a second electrode connected to the second to first nodes. The second to fourth transistors include a gate electrode connected to the second to first nodes, a first electrode connected to the first to first control nodes, and a second electrode connected to the second to second control nodes, according to the gate driving unit of claim 3.

5. The second output circuit unit further includes second to fifth to second to seventh transistors. The second to fifth transistors include a gate electrode and a first electrode connected to the first to second control nodes of the first EM driving unit, and a second electrode connected to the second to second nodes. The second to sixth transistors include a gate electrode connected to the second to second nodes, a first electrode connected to the second to first control nodes, and a second electrode connected to the low potential voltage line. The second to seventh transistors include a gate electrode connected to the second to second nodes, a first electrode connected to the second to second control nodes, and a second electrode connected to the high potential voltage line, according to the gate driving unit of claim 4.

6. The third output circuit unit According to the voltage of the third to first and third to second control nodes, it includes a third to first pull-up and a third to first pull-down transistor that output the third gate signal to the third output node, according to the gate driving unit of claim 3.

7. The third output circuit unit further includes third to first to third to second transistors. The third to first transistors include a gate electrode connected to the first to second control nodes of the n to first signal transmission unit, a first electrode connected to the first to second control nodes, and a second electrode connected to the third to first control nodes. The third to second transistors include a gate electrode connected to the first to second control nodes of the n to first signal transmission unit, a first electrode connected to the first to first control nodes, and a second electrode connected to the third to second control nodes, according to the gate driving unit of claim 6.

8. The third output circuit unit further includes third to third to third to sixth transistors. The 3-3 transistor includes a gate electrode connected to a carry signal line of the first EM driving unit, a first electrode connected to the 2-2 node, and a second electrode connected to the 2-3 node. The 3-4 transistor includes a gate electrode connected to a carry signal line of the first EM driving unit, a first electrode connected to the 1-2 output node, and a second electrode connected to the 2-3 node. The 3-5 transistor includes a gate electrode connected to the 2-3 node, a first electrode connected to the 3-1 control node, and a second electrode connected to a low potential voltage line. The 3-6 transistor includes a gate electrode connected to the 2-3 node, a first electrode connected to the 3-2 control node, and a second electrode connected to a high potential voltage line. The gate driving unit according to claim 7.

9. A display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels are arranged. A data driving unit that supplies a data voltage of pixel data to the data lines. A gate driving unit that supplies a gate signal to the gate lines. The gate driving unit includes a plurality of signal transmission units connected in cascade via a carry line to which a carry signal is applied from a signal transmission unit in a previous stage. Each of the plurality of signal transmission units. A first output circuit unit that receives the carry signal from the signal transmission unit in the previous stage and outputs the carry signal and a first gate signal according to voltages of a 1-1 control node and a 1-2 control node. A second output circuit unit that outputs a second gate signal according to voltages of a 2-1 control node connected to the 1-2 control node and a 2-2 control node connected to the 1-1 control node. A display device including a third output circuit unit that outputs a third gate signal according to voltages of a 3-1 control node connected to the 1-2 control node and a 3-2 control node connected to the 1-1 control node.

10. The first output circuit unit. A 1-1 pull-up and a 1-1 pull-down transistor that output the first gate signal to a 1-1 output node according to voltages of the 1-1 and 1-2 control nodes. The display device according to claim 9, comprising a first - 2 pull - up and a first - 2 pull - down transistor that output the carry signal to a first - 2 output node according to the voltages of the first - 1 and the first - 2 control nodes.

11. The second output circuit section The display device according to claim 10, comprising a second - 1 pull - up and a second - 1 pull - down transistor that output the second gate signal to a second output node according to the voltages of the second - 1 and the second - 2 control nodes.

12. The second output circuit section further includes a second - 1 transistor, a second - 2 transistor, a second - 3 transistor, and a second - 4 transistor, The second - 1 transistor includes a gate electrode connected to the first - 2 output node, a first electrode connected to a low - potential voltage line, and a second electrode connected to a second - 1 node. The second - 2 transistor includes a gate electrode connected to the second - 1 node, a first electrode connected to the first - 2 control node, and a second electrode connected to the second - 1 control node. The second - 3 transistor includes a gate electrode connected to the first - 2 control node, a first electrode connected to the carry signal line of the first EM driving section, and a second electrode connected to the second - 1 node. The display device according to claim 11, wherein the second - 4 transistor includes a gate electrode connected to the second - 1 node, a first electrode connected to the first - 1 control node, and a second electrode connected to the second - 2 control node.

13. The second output circuit section further includes a second - 5 transistor, a second - 6 transistor, and a second - 7 transistor, The second - 5 transistor includes a gate electrode and a first electrode connected to the first - 2 control node of the first EM driving section, and a second electrode connected to a second - 2 node. The second - 6 transistor includes a gate electrode connected to the second - 2 node, a first electrode connected to the second - 1 control node, and a second electrode connected to a low - potential voltage line. The display device according to claim 12, wherein the second - 7 transistor includes a gate electrode connected to the second - 2 node, a first electrode connected to the second - 2 control node, and a second electrode connected to a high - potential voltage line.

14. The third output circuit section The display device according to claim 11, comprising a 3-1 pull-up and a 3-1 pull-down transistor that output the third gate signal to a third output node according to the voltages of the 3-1 and 3-2 control nodes.

15. The third output circuit section further includes a 3-1 transistor, a 3-2 transistor, a 3-3 transistor, a 3-4 transistor, a 3-5 transistor, and a 3-6 transistor. The 3-1 transistor includes a gate electrode connected to a 1-2 control node of an n-1 signal transmission section, a first electrode connected to the 1-2 control node, and a second electrode connected to a 3-1 control node. The 3-2 transistor includes a gate electrode connected to a 1-2 control node of the n-1 signal transmission section, a first electrode connected to the 1-1 control node, and a second electrode connected to a 3-2 control node. The 3-3 transistor includes a gate electrode connected to a carry signal line of a first EM driving section, a first electrode connected to the 2-2 node, and a second electrode connected to a 2-3 node. The 3-4 transistor includes a gate electrode connected to a carry signal line of the first EM driving section, a first electrode connected to the 1-2 output node, and a second electrode connected to the 2-3 node. The 3-5 transistor includes a gate electrode connected to the 2-3 node, a first electrode connected to the 3-1 control node, and a second electrode connected to a low potential voltage line. The 3-6 transistor includes a gate electrode connected to the 2-3 node, a first electrode connected to the 3-2 control node, and a second electrode connected to a high potential voltage line, the display device according to claim 14.

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