Test and measurement system and communication method

Abstract

To simultaneously achieve high bandwidth and low latency at low cost.SOLUTION: A test and measurement system 100 includes a primary test and measurement instrument 102 and a secondary test and measurement instrument 104 coupled by a dual-band communication link DBCL. The dual-band communication link includes a high-bandwidth communication link HBCL having a first latency to transfer test data between the test and measurement instruments, and a low-latency communication link LLCL that is independent of the high-bandwidth communication link. The high-bandwidth communication link can be implemented at low cost by forming it using a standard high-speed bus standard. On the other hand, the low-latency communication link has a second latency that is less than the first latency, and can transmit control commands between the test and measurement instruments with low latency.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to communication with a test measurement device, and more specifically to a dual-band communication link including separate low-latency and high-bandwidth communication links for transmitting control commands and acquired test data between the test measurement device.

Background Art

[0002] A test measurement system may include a plurality of test measurement devices for acquiring test data from a device under test (DUT). In such a test measurement system, typically, one of these test measurement devices functions as a master or primary test measurement controller. Other test measurement devices are coupled to the primary test measurement device via a communication link and transfer the test data acquired from the DUT to the primary test measurement device. The primary test measurement device has a user interface, by which a user can analyze the acquired test data received from other test measurement devices via the communication link. Also, via the user interface, the user can supply control commands for controlling the operation of other test measurement devices via the communication link.

[0003] In such a test measurement system, the test data acquired by other test measurement devices corresponds to the acquired waveform data (hereinafter also simply referred to as "waveform") of one or more signals of the DUT. These acquired waveforms can be very large files, such as gigabyte-sized test data. Due to the large file size of the acquired waveforms, the communication link between other test measurement devices and the primary test measurement device needs to be a high-bandwidth communication link. This high bandwidth is necessary to transfer the acquired waveforms to the primary test measurement device in a timely manner.

[0004] The communication link needs to provide not only high bandwidth for transferring test data but also low-latency communication. Low latency is required so that the primary test measurement device can provide control commands to control the operation of other test measurement devices. For example, when a system includes multiple other test measurement devices and they cooperate to acquire multiple test signals of the DUT as a whole, low latency is required. Such a situation may occur when the DUT is tested as part of a production process. In this situation, the resetting or cooperative control of multiple other test measurement devices by the primary test measurement device is ideally performed as fast as possible to maximize the throughput of the test measurement system and the production volume of the production process.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0006]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] Latency and bandwidth are separate parameters of a communication link, and a high-bandwidth communication link may not be low-latency. The same can be said for low-latency communication links, which may not have a wide bandwidth. For example, a high-bandwidth communication link such as a PCIe (Peripheral Component Interconnect Express) bus uses a protocol that includes a relatively large header for the packets of data being communicated. These large packet headers result in a relatively long latency (response waiting time) for the PCIe bus. Therefore, in the use of test measurement systems, there is a need to improve communication links that can simultaneously achieve high bandwidth and low latency at low cost.

Means for Solving the Problems

[0008] Embodiments of the present disclosure relate to a test measurement system that communicates a large amount of acquired test data via a high-bandwidth communication link and communicates control commands for controlling a plurality of test measurement devices used within the test measurement system via a low-latency communication link, and has a dual-band communication link for this purpose. According to some embodiments of the present disclosure, the test measurement system includes a primary or first test measurement device and a secondary or second test measurement device. The dual-band communication link is coupled between the first test measurement device and the second test measurement device. This dual-band communication link includes a high-bandwidth communication link having a first latency time for transferring test data between the first and second test measurement devices. The dual-band communication link further includes a low-latency communication link separate from the high-bandwidth communication link. In the low-latency communication link, a second latency time in the transmission of control commands between the first and second test measurement devices is shorter than the first latency time.

[0009] The dual-band communication link provides the high bandwidth necessary to timely transmit a large amount of test data acquired by the second test measurement device to the first test measurement device. Further, the dual-band communication link enables the first test measurement device to timely reset the second test measurement device via an independent low-latency communication link. The test measurement system also includes additional test measurement devices, and the low-latency communication link enables timely resetting and coordinated control of these other test measurement devices by the first or primary test measurement device. This control is ideally performed as fast as possible to maximize the throughput of the test measurement system during testing of the device under test (DUT).

[0010] In a test measurement system according to an embodiment of the disclosed technology, instead of a test measurement device manufacturer (manufacturer) designing new and custom high-bandwidth communication links, a third party or off-the-shelf intellectual property (IP) core may be used. The core is a reusable logic circuit (logic) block or integrated circuit layout design that is designed by another party and may be licensed for use in a component or system under design. The IP of the core defines the function of the core, and the IP core is typically implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). For example, in an embodiment of the disclosed technology, the high-bandwidth communication link may be implemented by a third party IP core such as a PCIe bus core and a direct memory access (DMA) core.

[0011] By using a third party IP core in this way, the manufacturer of the test measurement device can reduce the time and cost for designing the required high-bandwidth communication link and the overall test measurement system. In an embodiment of the disclosed technology, the low-latency communication link may be a custom or proprietary communication link that reduces the latency of the link to achieve a low-overhead communication protocol. In another embodiment, the low-latency communication link may be a standard low-overhead protocol communication link such as a serial communication link such as a universal asynchronous receiver-transmitter (UART) or a serial peripheral interface (SPI).

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0013] FIG. 1 is a block diagram of a test measurement system 100 including a primary test measurement device 102 coupled to a secondary test measurement device 104 via a dual-band communication link DBCL (dual-band communication link) according to an embodiment of the present disclosure technology. The dual-band communication link DBCL provides high-bandwidth transfer of test data acquired by the secondary test measurement device 104 while enabling the primary test measurement device 102 to supply control commands to the secondary test measurement device 104 with low latency (LL: Low Latency). Note that the term "low latency" may be abbreviated as "LL" in this application and the accompanying figures. The primary device controller 106 of the primary test measurement device 102 and the secondary device controller 108 of the secondary test measurement device 104 perform communication via the dual-band communication link DBCL. The device controllers 106 and 108 are part of the dual-band communication link DBCL, and the structure and operation of these device controllers will be described in more detail below with reference to FIGS. 2 and 3.

[0014] The dual - band communication link DBCL has a high - bandwidth communication link HBCL (high - bandwidth communication link) for transferring test data acquired by the secondary test measurement device 104 to the primary test measurement device 102. The low - latency communication link LLCL (low - latency communication link) of the dual - band communication link DBCL provides low - latency communication of control commands from the primary test measurement device 102 to the secondary test measurement device 104, and resets or otherwise controls the operation of the secondary test measurement device 104. In the description of this application, each of the primary test measurement device 102 and the secondary test measurement device 104 may also be referred to as the first test measurement device 102 and the second test measurement device 104 instead of these names, or simply as device 102 or device 104.

[0015] The primary test measurement device 102 has one or more processors 110, which may be configured to execute instructions from the memory 112, and may also execute any method and related steps corresponding to such instructions. The user interface 114 is coupled to one or more processors 110 and may have, for example, a keyboard, a mouse, a touch screen, an output display, file storage, or any other operating device that is available for the user to interactively operate the primary test measurement device 102. In some embodiments, the user interface 114 may be connected to a remote interface (not shown) that is remote, or may be controlled by the remote interface, whereby the user may control the operation of the primary test measurement device 102 from a remote location physically separated from the primary test measurement device 102. The display portion of the user interface 114 may be a digital screen such as an LCD, an LED, or any other monitor for displaying waveforms, measurement values, and other data to the user. In some embodiments, the main output display of the user interface 114 may also be located at a location remote from the primary test measurement device 102.

[0016] The primary test measurement device 102 further includes one or more measurement units 116, which perform the function of measuring parameters and other characteristics of signals from the DUT being measured or tested by the primary test measurement device 102. Typical measurements include, in addition to measuring the voltage, current, and power of signals in the time domain, measuring the characteristics of signals in the frequency domain. The measurement unit 116 represents any measurement performed by the primary test measurement device 102, and the primary device controller 106 may be coupled or integrated with the measurement unit 116 or other components of the primary test measurement device 102. Similarly, the secondary test measurement device 104 includes a processor 118, a memory 120, a user interface 122, and a measurement unit 124, which function in the same manner as the corresponding components described above in relation to the primary test measurement device 102.

[0017] As described above, the size of the acquired test data may be very large, such as gigabyte-scale test data, and the high-bandwidth communication link HBCL has the bandwidth required to transfer this test data in a timely manner from the secondary test measurement device 104 to the primary test measurement device 102. For example, in some embodiments of the present disclosure, the high-bandwidth communication link HBCL is a PCIe bus, which provides a very wide bandwidth for transferring test data via the high-bandwidth communication link HBCL. The term "high-bandwidth" as used in the background of the present application means, for example, that the PCIe bus is PCIe version 6.0, the PCIe bus may have up to 32 lanes, and the communication on each lane may occur at a speed of 64 GT / s (Gigatransfers per second). In further embodiments of the test measurement system 100, the high-bandwidth communication link HBCL may be another type of high-bandwidth communication link implementing other protocols such as the Ethernet (registered trademark) protocol or the USB (Universal Serial Bus) protocol.

[0018] In addition to its high bandwidth characteristics, the high bandwidth communication link HBCL needs to communicate via a very efficient protocol, which means that most of each message segment transmitted is reserved in advance for the data transmitted between the secondary test measurement device 104 and the primary test measurement device 102.

[0019] While the high bandwidth communication link HBCL can utilize an efficient and high bandwidth communication protocol, the latency (Latency: response waiting time) between messages of the high bandwidth communication link HBCL may be too large to enable the desired control of the secondary test measurement device 104 by the primary test measurement device 102. Also, even if the latency of the high bandwidth communication link HBCL is small enough, transferring a large amount of acquired test data from the secondary test measurement device 104 using the high bandwidth communication link HBCL will either cause the high bandwidth communication link HBCL to become saturated (i.e., the high bandwidth communication link HBCL becomes 100% active while transferring the acquired test data), or the delay in the space where control commands in the data stream of the high bandwidth communication link HBCL are placed will tend to become very large.

[0020] One way to solve the problem of large latency in a high-bandwidth communication link in a test measurement system is to design a custom high-bandwidth communication link with reduced latency. However, manufacturers of test measurement devices in the test measurement industry may not have expertise in designing high-bandwidth communication links. Furthermore, reducing the time to market for new test measurement system features is becoming an increasingly important goal in the industry, and thus the time available to design new components of such systems independently is shrinking. Another approach to solving the problem of high latency time in a high-bandwidth communication link is to modify or customize the communication protocol implemented by a third-party IP core to reduce the latency time of the communication link implemented by that IP core. This approach is usually not a viable option. When using a third-party IP core such as the PCIe bus, the IP core is licensed from a third party under a license agreement, but the terms of that license agreement prohibit changing the IP core, so the IP core usually cannot be changed. Also, the software portion of the licensed third-party IP core is usually encrypted to prevent violation of the license terms for such changes.

[0021] The dual-band communication link DBCL overcomes these problems by providing a low-latency communication link LLCL independently and separately from the high-bandwidth communication link HBCL. Due to this independence, the primary test measurement device 102 can supply control commands to the secondary test measurement device 104 whenever necessary to control the desired operation of the secondary test measurement device 104. Thus, the dual-band communication link DBCL meets the needs of the test measurement system for both high-bandwidth communication for transferring large amounts of data and low latency for controlling the operation of test measurement devices within the system. Further, the dual-band communication link DBCL eliminates the need for a new custom-designed communication link. Instead, since third-party IP cores can be used for the high-bandwidth communication link HBCL, manufacturers of test measurement systems can combine IP cores from various vendors, integrate these IP cores at a higher level, and achieve the necessary time-to-market and scheduling goals while meeting the new system technical requirements. In embodiments of the disclosed technology, the low-latency communication link LLCL may be a custom-designed communication link that utilizes a custom low-overhead communication protocol to achieve the desired low latency for the communication link. Alternatively, the low-latency communication link LLCL may implement a standard low-overhead protocol communication link such as a serial communication link like UART (universal asynchronous receiver-transmitter) or SPI (serial peripheral interface).

[0022] Generally, during the operation of the dual-band communication link DBCL, the low-latency communication link LLCL does not continuously become active while the high-bandwidth communication link HBCL is active. The low-latency communication link LLCL enables the primary test measurement device 102 to issue control commands to the secondary test measurement device 104 or vice versa as required for a specific application. Such commands may be synchronized with the section and timing of the data transferred between the test measurement devices 102 and 104 via the high-bandwidth communication link HBCL, or may occur asynchronously with respect to the data. As long as these control commands can be issued as needed at all times, either device may transfer additional data via the low-latency communication link LLCL.

[0023] In some embodiments, each of the high - bandwidth communication link HBCL and the low - latency communication link LLCL provides two - way communication between the primary test measurement device 102 and the secondary test measurement device 104. Further, in some embodiments, test data is acquired by each of the primary test measurement device 102 and the secondary test measurement device 104 and may be communicated via the high - bandwidth communication link HBCL to the other of the primary test measurement device 102 and the secondary test measurement device 104. Similarly, control commands may be communicated from each of the primary test measurement device 102 and the secondary test measurement device 104 to the other of the primary test measurement device 102 and the secondary test measurement device 104 via the low - latency communication link LLCL. The two - way communication by each of the high - bandwidth communication link HBCL and the low - latency communication link LLCL enables two - way communication of test data and control commands via these communication links. This two - way communication also enables any necessary communication associated with the protocols implemented on each of the HBCL, LLCL communication links, such as communication related to hand - shakes, error correction, or other functions of the particular protocol being used. The low - latency communication link LLCL provides two - way communication between the primary test measurement device 102 and the secondary test measurement device 104 in a plurality of embodiments, where this two - way communication may include communication of status information and responses to control commands communicated from the secondary test measurement device 104 to the primary test measurement device 102.

[0024] The transfer rate, bit rate, or baud rate of the high-bandwidth communication link HBCL is significantly higher than the bandwidth of the low-latency communication link LLCL. In the low-latency communication link LLCL, the total time to transfer a packet such as a message or command is smaller compared to the total time to transfer a packet such as a message or command via the high-bandwidth communication link HBCL. This operation of the low-latency communication link LLCL may be achieved by small packets, a high transfer rate, or both. The "high transfer rate" of the low-latency communication link LLCL is a speed sufficient to achieve the low latency required for the low-latency communication link, but is significantly lower than the transfer rate of the high-bandwidth communication link HBCL as described above.

[0025] In a further embodiment of the present disclosure, the test measurement system 100 includes additional test measurement devices (not shown in FIG. 1) coupled to the dual-band communication link DBCL, and transfers test data obtained from each of these additional test measurement devices to the primary test measurement device 102. Embodiments including a plurality of additional test measurement devices will be described in further detail below with reference to FIG. 3. In yet another embodiment of the present disclosure, any of the test measurement devices coupled to the dual-band communication link DBCL may function as either the primary test measurement device or the secondary test measurement device. In yet another embodiment of the present disclosure, the device controller of a test measurement device may be coupled to the device controller of yet another test measurement device via an additional dual-band communication link. In short, the test measurement system 100 may have different connection forms (topologies) of components in a further embodiment of the present disclosure, and the test measurement devices in these different connection forms are interconnected through the dual-band communication link DBCL.

[0026] FIG. 2 is a block diagram showing in more detail a dual - band communication link 200 according to an embodiment of the disclosed technology. The dual - band communication link 200 corresponds to an embodiment of the dual - band communication link DBCL of FIG. 1. The dual - band communication link 200 includes a primary device controller 202 and a secondary device controller 204, each of which is included in a primary test measurement device and a secondary test measurement device (not shown in FIG. 2). Since some parts or components of each of the primary device controller 202 and the secondary device controller 204 are for realizing the dual - band communication link 200 as illustrated in FIG. 2, the primary device controller 202 and the secondary device controller 204 are described in this application's description as being part of or included in the dual - band communication link 200. However, in some embodiments of the disclosed technology, these device controllers 202 and 204 may be independent of and not included in the dual - band communication link 200, and there may be embodiments where this is the case. The dual - band communication link 200 includes a high - bandwidth communication link 206 and a low - latency communication link 208 coupled between the primary device controller 202 and the secondary device controller 204. The high - bandwidth communication link 206 and the low - latency communication link 208 each have a corresponding physical link PL - HB and PL - LL, each of which represents the physical communication medium of the corresponding communication link, for example, a wire or an optical cable. Note that PL means "physical link", HB means "high - bandwidth", and LL means "low - latency", respectively.

[0027] The high-bandwidth communication link 206 includes a high-bandwidth communication core 210, which is coupled to the first end of the physical link PL-HB and is configured to transmit and receive electrical signals via the physical link PL-HB for communicating test data. In the embodiment of FIG. 2, this high-bandwidth communication core 210 is a PCIe core. The high-bandwidth data transfer core 212 of the primary device controller 202 is coupled to the PCIe core 210, receives test data from the PCIe core, and stores this test data in a memory (not shown) included in the primary device controller 202. The high-bandwidth data transfer core 212 is, for example, a direct memory access (DMA) core, and each of the DMA core 212 and the PCIe core 210 is a third-party IP core in the embodiment of FIG. 2.

[0028] At the other end (second end) of the physical link PL-HB coupled to the secondary device controller 204 in the high-bandwidth communication link 206, there are corresponding IP core components. More specifically, the high-bandwidth communication link 206 further includes a high-bandwidth communication core 214, which is coupled to the second end of the physical link PL-HB and is configured to transmit and receive electrical signals via the physical link PL-HB for communicating test data. In the embodiment of FIG. 2, the high-bandwidth communication core 214 is a PCIe core and is coupled to the high-bandwidth data transfer core 216 of the secondary device controller 204. The high-bandwidth data transfer core 216 receives test data from a memory (not shown) included in a secondary test measurement device (not shown), supplies the received test data to the PCIe core 214, and then the PCIe core 214 generates an electrical signal for transmitting (communicating) the test data to the PCIe core 210 via the physical link PL-HB. Here too, the high-bandwidth data transfer core 216 is, for example, a direct memory access (DMA) core, and each of the DMA core 216 and the PCIe core 214 is a third-party IP core in the embodiment of FIG. 2. Each of the IP cores 210-216 may be implemented in the form of an FPGA or an ASIC (application-specific integrated circuit) in the embodiments of the disclosed technology.

[0029] The low-latency communication link 208 includes a low-latency (LL) communication core 218, which is coupled to the first end of the physical link PL-LL and is configured to transmit and receive electrical signals via the physical link PL-LL to communicate control commands for controlling the operation of a secondary test measurement device (not shown) including the secondary device controller 204. The low-latency communication core 218 is configured to receive control commands from the low-latency protocol core 220 and generate corresponding electrical signals for communicating the control commands to the secondary device controller 204 via the physical link PL-LL. The low-latency communication core 218 may be, for example, a custom communication core designed to implement a low-overhead communication protocol. The manufacturer of the test measurement device (not shown in FIG. 2) including the primary device controller 202 and the secondary device controller 204 may design the low-latency communication core 218 to implement a low-overhead communication protocol having the desired low latency required for the low-latency communication link 208.

[0030] In the embodiment of FIG. 2, this low-latency protocol core 220 is included in the primary device controller 202 and is configured to receive control command instructions and generate control commands for communicating via the physical link PL-LL of the low-latency communication link 208 from these control command instructions. The primary device controller 202 supplies control command instructions to the low-latency protocol core 220, and the low-latency protocol core generates control command packets using the low-overhead communication protocol of the low-latency communication link 208 in response to these control command instructions. The control command packets include control commands transmitted from the primary device controller 202 to the secondary device controller 204. The operation or settings of the secondary test measurement device (not shown in FIG. 2) including the secondary device controller 204 are adjusted by the applied control commands. In this way, the primary device controller 202 supplies control command instructions to the low-latency protocol core 220 to control the operation of the secondary test measurement device (not shown) including the secondary device controller 204.

[0031] The low-latency communication link 208 has a corresponding IP core component at the other end (the second end) of the physical link PL-LL coupled to the secondary device controller 204. More specifically, the low-latency communication link 208 further includes a low-latency communication core 222, which is coupled to the second end of the physical link PL-LL and the low-latency protocol core 224. The low-latency communication core 222 receives electrical signals corresponding to the control commands communicated via the physical link PL-LL and decodes these electrical signals into bits of the control commands. The low-latency communication core 222 supplies these decoded bits to the low-latency protocol core 224 included in the secondary device controller 204. The low-latency protocol core 224 generates corresponding control command packets from the received bits and supplies the corresponding control commands to the secondary device controller 204. In response to the control commands from the low-latency protocol core 224, the secondary device controller 204 then controls the operation or settings of a secondary test measurement device (not shown) including the secondary device controller. In the embodiment of the low-latency communication link 208 in FIG. 2, each of the low-latency communication cores 218 and 220 may be implemented in the form of an FPGA or an ASIC. Also, each of the low-latency protocol cores 220 and 224 may be implemented by an FPGA or an ASIC. Further, although the operation of the low-latency communication link 208 has been described as transmitting (communicating) control commands from the primary device controller 204 to the secondary device controller 204, in some embodiments of the present disclosure, other data or commands may be transmitted (communicated) via this link.

[0032] Through the dual - band communication link 200, the primary device controller 202 can identify or select whether to use the high - bandwidth communication link 206 or the low - latency communication link 208 for communication with the secondary device controller 204. In operation, the primary device controller 202 first determines whether to perform communication via the high - bandwidth communication link 206 or via the low - latency communication link 208. When a DMA transfer of test data is performed, the primary device controller 202 determines to use the high - bandwidth communication link 206 for communication. Thereafter, the DMA core 212, PCIe core 210 and DMA core 216, PCIe core 214 operate together to transfer the test data stored in the secondary device controller 204 via the high - bandwidth communication link 206 and store this test data in the memory of the primary test measurement device via the primary device controller 202. Conversely, when resetting the secondary device controller 204 or other control is required, the primary device controller 202 determines that it is necessary to send a control command to the secondary device controller 204 using the low - latency communication link 208. Then, the low - latency (LL) protocol core 220, LL communication core 218 and LL protocol core 224, LL communication core 222 operate together to apply the control command to the secondary device controller 204 via the low - latency communication link 208, whereby the secondary device controller 204 resets the secondary test measurement device or adjusts the control of the secondary test measurement device according to the control command.

[0033] In this way, the primary device controller 202 can use both communication links 206 and 208. In some embodiments of the present disclosure, the communication of test data and control commands can be performed in both directions on the dual-band communication link 200, that is, in the direction from the primary device controller 202 to the secondary device controller 204 and in the direction from the secondary device controller to the primary device controller. In such embodiments, each of the primary device controller 202 and the secondary device controller 204 can determine which of the communication links 206 and 208 within the dual-band communication link 200 to use for communication with the other device controller. Further, in embodiments of the present disclosure technology, both communication links 206 and 208 may operate simultaneously to communicate (transmit) test data and control commands between the device controllers 202 and 204.

[0034] FIG. 3 is a block diagram showing in more detail a dual - band communication link 300 according to a further embodiment of the present disclosure. The dual - band communication link 300 corresponds to an embodiment of the dual - band communication link DBCL of FIG. 1. The dual - band communication link 300 includes a primary device controller 302 coupled to a plurality of secondary device controllers 304A and 304B via the dual - band communication link 300. More specifically, the dual - band communication link 300 has a high - bandwidth communication link 306 and a low - latency communication link 308, each of which includes intermediate switches 322 and 336 for coupling the plurality of secondary device controllers 304A and 304B to the primary device controller 302. The high - bandwidth communication link 306 is, in the embodiment of FIG. 3, for example, a PCIe bus, and thus there are DMA cores and PCIe cores associated with each of the device controllers 302, 304A, and 304B. Accordingly, the high - bandwidth communication link 306 has a PCIe core 310 and a DMA core 312 at one end of the high - bandwidth communication link 306 coupled to the primary device controller 302, and at the other end of the high - bandwidth communication link 306, there are a PCIe core 314 and a DMA core 316 associated with the secondary device controller 304A and a PCIe core 318 and a DMA core 320 associated with the secondary device controller 304B.

[0035] The intermediate switch 322 is, in the embodiment of FIG. 3, a PCIe switch and is coupled to the primary device controller 302 via the first physical link PL - HB1 of the high - bandwidth communication link 306. Each of the secondary device controllers 304A and 304B is coupled to the PCIe switch 322 via their respective physical links PL - HB2, PL - HB3. An additional secondary device controller (not shown) may be coupled to the PCIe switch 322 via an additional physical link, but in the embodiment of FIG. 3, only two secondary device controllers 304A and 304B are shown by way of example.

[0036] In operation, the primary device controller 302 supplies commands to the PCIe switch 322 via the DMA core 312 and the PCIe core 310, and selects a desired one of the secondary device controllers 304A and 304B for communication. By this selection, a high-bandwidth communication link is effectively formed between the primary device controller 302 and the selected one of the secondary device controllers 304A and 304B. The high-bandwidth communication link between the primary device controller 302 and the selected one of the secondary device controllers 304A and 304B then operates as described above for the high-bandwidth communication link 206 in FIG. 2. Accordingly, the PCIe core 310 and the DMA core 312 and the PCIe core 314 and the DMA core 316 or the PCIe core 318 and the DMA core 320 associated with the selected one of the secondary device controllers 304A and 304B operate in the same manner as described above for the PCIe core 210, the DMA core 212, the PCIe core 214, and the DMA core 216 of the high-bandwidth communication link 206 in FIG. 2.

[0037] At one end of the low-latency communication link 308 coupled to the primary device controller 302, there are a low-latency (LL) communication core 324 and a low-latency protocol core 326. At the other end of the low-latency communication link 308, there are a low-latency (LL) communication core 328 and a low-latency protocol core 330 associated with the secondary device controller 304A, and a low-latency communication core 332 and a low-latency protocol core 334 associated with the secondary device controller 304B. The intermediate switch 336 is coupled to the primary device controller 302 via the first physical link PL-LL1 of the low-latency communication link 308. Each of the secondary device controllers 304A and 304B is coupled to the intermediate switch 336 via its respective physical links PL-LL2, PL-LL3. Here too, an additional secondary device controller (not shown) may be coupled to the intermediate switch 336 via an additional physical link, but in FIG. 3, only two secondary device controllers 304A and 304B are illustrated by way of example.

[0038] In operation, the primary device controller 302 supplies a command to the intermediate switch 336 for selecting either of the secondary device controllers 304A and 304B to be used for communication via the LL protocol core 326 and the LL communication core 324. As a result of this selection, a low-latency communication link is effectively formed between the primary device controller 302 and the selected one of the secondary device controllers 304A and 304B. Thereafter, the low-latency communication link between the primary device controller 302 and the selected one of the secondary device controllers 304A and 304B operates in the same manner as the operation described above with respect to the low-latency communication link 208 in FIG. 2. For this reason, either the LL protocol core 326 and the LL communication core 324, and the LL communication core 328 and the LL protocol core 330 associated with the secondary device controller 304A, or the LL communication core 332 and the LL protocol core 334 associated with the secondary device controller 304B, operates in the same manner as the operation described above for the LL communication core 218, the LL protocol core 220, the LL communication core 222, and the LL protocol core 224 of the low-latency communication link 208 in FIG. 2.

[0039] FIG. 4 is a diagram showing a software layer 400 implemented in a primary device controller 402 and a secondary device controller 404 coupled via a dual - band communication link DBCL according to an embodiment of the present disclosure technology. The primary device controller 402 corresponds to the primary device controller 202 or 302 in the embodiments of FIGS. 2 and 3, and the secondary device controller 404 corresponds to either the secondary device controller 204 in FIG. 2 or the secondary device controllers 304A and 304B in FIG. 3. The primary device controller 402 has a library software layer 406, which may be an application programming interface (API) in an embodiment of the present disclosure technology, and determines whether to use the high - bandwidth communication link HBCL or the low - latency communication link LLCL of the dual - band communication link DBCL for communication with the secondary device controller 404.

[0040] The library software layer 406 communicates with the upper layer of software (e.g., application programs, not shown in FIG. 4) executed on the primary device controller 402, and these software programs enable the dual-band communication link DBCL to be treated as a single communication link for providing communication with the secondary device controller 404. During operation, a software program (not shown) executed on the primary device controller provides instructions for communicating with the library software layer 406. These instructions include information that enables the library software layer 406 to determine whether to use the high-bandwidth communication link HBCL or the low-latency communication link LLCL for communication with the secondary device controller 404. The library software layer 406 then communicates with the high-bandwidth (HB) and low-latency (LL) layer 408, and this layer 408 then controls the communication via the communication link selected from among the high-bandwidth communication link HBCL and the low-latency communication link LLCL in the dual-band communication link DBCL. The HB and LL layer 408 communicates with the corresponding IP cores (e.g., the PCIe core 210 and the DMA core 212 or the LL communication core 218 and the LL protocol core 220 of FIG. 2) of the dual-band communication link DBCL and performs the desired communication via the communication link selected from among the high-bandwidth communication link HBCL and the low-latency communication link. The secondary device controller 404 has a library software layer 410 and an HB and LL layer 412, and these operate in a similar manner to facilitate communication with the primary device controller 402 via the dual-band communication link DBCL.

[0041] FIG. 5 is a flowchart of a process 500 that may be implemented in a test measurement system according to an embodiment of the present disclosure technology. This process 500 will be described with reference to FIG. 1. The process 500 starts from step 502, and in the primary test measurement device (or the first test measurement device) 102, or in the primary device controller 106, it is determined (decided) whether communication with the secondary test measurement device (or the second test measurement device) 104 is necessary. Next, the process 500 proceeds to step 504, and in the primary test measurement device 102 (or the primary device controller 106), an appropriate communication type (Type) is determined. Examples of the communication type include, for example, transfer of test data from the secondary test measurement device 104 to the primary test measurement device 102, and application of control commands to the secondary test measurement device 104. Next, the process 500 proceeds to step 506, and in the primary test measurement device 102 (or the primary device controller 106), either a high-bandwidth communication link HBCL or a low-latency communication link LLCL is selected. This selection is based on the communication type. The high-bandwidth communication link HBCL has a first delay time, and the low-latency communication link LLCL is independent of the high-bandwidth communication link HBCL and has a second delay time smaller than the first delay time.

[0042] Process 500 proceeds from step 506 to step 508, and the primary test measurement device 102 (or the primary device controller 106) communicates with the secondary test measurement device 104 via a communication link selected from the high bandwidth communication link HBCL and the low latency communication link LLCL. In an embodiment of process 500, when the type of communication is the transfer of test data from the secondary test measurement device 104 to the primary test measurement device 102, the primary test measurement device 102 (or the primary device controller 106) selects the high bandwidth communication link HBCL in step 506 and communicates with the secondary test measurement device 104 via the high bandwidth communication link in step 508. When the type of communication is the application of a control command to the secondary test measurement device 104, the primary test measurement device 102 (or the primary device controller 106) selects the low latency communication link LLCL in step 506 and communicates with the secondary test measurement device 104 via the low latency communication link LLCL in step 508.

[0043] Aspects of the disclosed technology can operate on a specially programmed general-purpose computer including specially created hardware, firmware, a digital signal processor, or a processor operating according to programmed instructions. The terms "controller" or "processor" in this application are intended to include microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology can be realized by computer-usable data and computer-executable instructions such as one or more program modules executed by one or more computers (including monitoring modules) and other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform a specific task or implement a specific abstract data type. The computer-executable instructions may be stored in a computer-readable storage medium such as a hard disk, optical disk, removable storage medium, solid-state memory, RAM, etc. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as necessary in various embodiments. Further, such functions may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, field-programmable gate arrays (FPGAs), etc. One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described in this application.

[0044] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may be implemented as instructions carried or stored by one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, a computer-readable media means any media that can be accessed by a computing device. By way of example, and not limitation, a computer-readable media may include computer storage media and communication media.

[0045] A computer storage media means any media that can be used to store computer-readable information. By way of example, and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disc storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other removable or non-removable media implemented by any technology. Computer storage media excludes signals per se and transient forms of signal transmission.

[0046] A communication media means any media that can be used to communicate computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other media suitable for communication of electrical, optical, radio frequency (RF), infrared, sound, or other forms of signals. Examples

[0047] Examples that are helpful for understanding the technology disclosed in the present application are presented below. Embodiments of this technology may include one or more of the examples described below and any combination thereof.

[0048] Example 1 is a test measurement system, comprising a first test measurement device, a second test measurement device, and a dual - band communication link coupled between the first test measurement device and the second test measurement device. The dual - band communication link has a high - bandwidth communication link having a first delay time for transferring test data between the first test measurement device and the second test measurement device, and a low - delay communication link independent of the high - bandwidth communication link having a second delay time shorter than the first delay time for transferring control commands between the first test measurement device and the second test measurement device.

[0049] Example 2 is the test measurement system of Example 1, comprising a first device controller in the first test measurement device, and a second device controller in the second test measurement device further. The first device controller is configured to identify or select either the high - bandwidth communication link or the low - delay communication link for communicating with the second test measurement device, and to initiate communication via the identified or selected communication link among the high - bandwidth communication link and the low - delay communication link. The second device controller is configured to identify or select either the high - bandwidth communication link or the low - delay communication link for communicating with the first test measurement device, and to initiate communication via the identified or selected communication link among the high - bandwidth communication link and the low - delay communication link.

[0050] Example 3 is the test measurement system of Example 2. When the first device controller transfers the test data acquired by the second test measurement device to the first test measurement device, it is configured to identify or select the high-bandwidth communication link for communicating with the second test measurement device. When the second device controller transfers the test data acquired by the first test measurement device to the second test measurement device, it is configured to identify or select the high-bandwidth communication link for communicating with the first test measurement device.

[0051] Example 4 is the test measurement system of Example 2. When the first device controller determines to transmit a control command to the second test measurement device, it is configured to identify or select the low-latency communication link for communicating with the second test measurement device.

[0052] Example 5 is the test measurement system of Example 2. The high-bandwidth communication link is any one of a PCIe communication link, a USB communication link, and an Ethernet (registered trademark) communication link.

[0053] Example 6 is the test measurement system of Example 5. The first device controller includes a direct memory access (DMA) core. The high-bandwidth communication link includes a PCIe core. The DMA core and the PCIe core are configured to communicate the test data acquired by the second test measurement device via the high-bandwidth communication link and operate jointly to store the test data in the first test measurement device.

[0054] Example 7 is the test measurement system of Example 2. The low-latency communication link is any one of serial communication links including a UART (universal asynchronous receiver-transmitter) or an SPI (serial peripheral interface).

[0055] Example 8 is the test measurement system of Example 2, wherein the first device controller includes a low-latency protocol core, the low-latency communication link includes a low-latency communication core, the low-latency protocol core and the low-latency communication core operate jointly, and are configured to transmit control commands to the second test measurement device via the low-latency communication link.

[0056] Example 9 is the test measurement system of Example 8, wherein the low-latency communication link includes either a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) configured to implement the low-latency communication core.

[0057] Example 10 is the test measurement system of Example 1, further comprising one or more additional test measurement devices coupled to the first test measurement device via the dual-band communication link.

[0058] Example 11 is the test measurement system of Example 10, wherein each of the high-bandwidth communication link and the low-latency communication link includes a switch configured to couple the second test measurement device and the one or more additional test measurement devices to the first test measurement device.

[0059] Example 12 is the test measurement system of Example 11, wherein the high-bandwidth communication link is a PCIe communication link, and the switch within the high-bandwidth communication link is a PCIe switch.

[0060] Example 13 is the test measurement system of Example 12, wherein the low-latency communication link is either a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) that implements the switch of the low-latency communication link.

[0061] Example 14 is the test measurement system of Example 1, wherein at least one of the first test measurement device and the second test measurement device is an oscilloscope.

[0062] Example 15 is a communication method, In the first test measurement device, a process of determining whether communication with the second test measurement device is necessary, In the first test measurement device, a process of determining the type of necessary communication, In the first test measurement device, based on the type of communication, a high-bandwidth communication link having a first delay time coupled between the first test measurement device and the second test measurement device, and also coupled between the first test measurement device and the second test measurement device, independent of the high-bandwidth communication link, and having a second delay time smaller than the first delay time with respect to communication with the second test measurement device. Selecting any one of the low-delay communication links, A process of communicating with the second test measurement device via the selected high-bandwidth communication link or the low-delay communication link is provided.

[0063] Example 16 is the communication method of Example 15, wherein the type of communication is either transfer of test data between the first test measurement device and the second test measurement device or communication of control commands between the first test measurement device and the second test measurement device.

[0064] Example 17 is the communication method of Example 16, wherein the selecting process includes a process of selecting the high-bandwidth communication link when the type of communication is transfer of test data between the first test measurement device and the second test measurement device, and a process of selecting the low-delay communication link when the type of communication is communication of control commands between the first test measurement device and the second test measurement device.

[0065] Example 18 is a test measurement system, A first test measurement device, A plurality of additional test measurement devices, A dual-band communication link coupled between the first test measurement device and each of the plurality of additional test measurement devices is provided, The dual - band communication link is configured to provide a high - bandwidth communication link having a first delay time for transferring test data between the first test measurement device and each of the plurality of additional test measurement devices, and is further configured to provide a low - delay communication link independent of the high - bandwidth communication link. The low - delay communication link has a second delay time smaller than the first delay time and communicates control commands between the first test measurement device and each of the plurality of additional test measurement devices.

[0066] Example 19 is the test measurement system of Example 18, wherein each of the high - bandwidth communication link and the low - delay communication link has an intermediate switch coupled between the first test measurement device and each of the plurality of additional test measurement devices.

[0067] Example 20 is the test measurement system of Example 18, wherein the first test measurement device and each of the plurality of additional test measurement devices are oscilloscopes.

[0068] The above - described versions of the subject matter of the present disclosure have many effects that have been described or will be apparent to those skilled in the art. Nevertheless, in all versions of the disclosed apparatus, system or method, not all of these effects or features are required.

[0069] In addition, the description of the present application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. When a particular feature is disclosed in relation to a particular aspect or embodiment, that feature can be used in relation to other aspects and embodiments as well, to the extent possible.

[0070] Also, in the present application, when referring to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the context excludes their possibility.

[0071] For the sake of explanation, specific embodiments of the present invention have been illustrated and described. However, it should be understood that various changes can be made without departing from the gist and scope of the present invention. Therefore, the present invention should not be limited except as defined by the appended claims.

Explanation of Reference Numerals

[0072] 100 Test Measurement System 102 Primary Test Measurement Device 104 Secondary Test Measurement Device 106 Primary Device Controller 108 Secondary Device Controller 110 One or More Processors 112 Memory 114 User Interface 116 One or More Measurement Units 118 One or More Processors 120 Memory 122 User Interface 124 One or More Measurement Units 200 Dual-Band Communication Link 202 Primary Device Controller 204 Secondary Device Controller 206 High-Bandwidth Communication Link 208 Low-Latency Communication Link 210 High-Bandwidth Communication Core (PCIe Core) 212 High-Bandwidth Data Transfer Core (DMA Core) 214 High-Bandwidth Communication Core (PCIe Core) 216 High-Bandwidth Data Transfer Core (DMA Core) 218 Low-Latency Communication Core 220 Low-Latency Protocol Core 222 Low-Latency Communication Core 224 Low-Latency Protocol Core 300 Dual-Band Communication Link 302 Primary Device Controller 304A First Secondary Device Controller 304B Secondary Device Controller 306 High-Bandwidth Communication Link 308 Low-Latency Communication Link 310 High-Bandwidth Communication Core (PCIe Core) 312 High-Bandwidth Data Transfer Core (DMA Core) 314 High-Bandwidth Communication Core (PCIe Core) 316 High-Bandwidth Data Transfer Core (DMA Core) 318 High-Bandwidth Communication Core (PCIe Core) 320 High-Bandwidth Data Transfer Core (DMA Core) 322 Intermediate Switch (PCIe Switch) 324 Low-Latency Communication Core 326 Low-Latency Protocol Core 328 Low-Latency Communication Core 330 Low-Latency Protocol Core 332 Low-Latency Communication Core 334 Low-Latency Protocol Core 336 Intermediate Switch 400 Software Layer 402 Primary Device Controller 404 Secondary Device Controller 406 Library Software Layer 408 HB and LL Layers 410 Library Software Layer 412 HB and LL Layers

Claims

1. A first test measurement device, a second test measurement device, and a dual - band communication link coupled between the first test measurement device and the second test measurement device comprising: The dual - band communication link includes a high - bandwidth communication link having a first delay time for transferring test data between the first test measurement device and the second test measurement device, and a low - delay communication link independent of the high - bandwidth communication link having a second delay time shorter than the first delay time for transferring control commands between the first test measurement device and the second test measurement device A test measurement system having the above.

2. further comprising a first device controller in the first test measurement device and a second device controller in the second test measurement device, wherein the first device controller is configured to identify either the high - bandwidth communication link or the low - delay communication link for communicating with the second test measurement device and initiate communication via the identified high - bandwidth communication link or low - delay communication link, and the second device controller is configured to identify either the high - bandwidth communication link or the low - delay communication link for communicating with the first test measurement device and initiate communication via the identified high - bandwidth communication link or low - delay communication link The test measurement system of Claim 1.

3. The first device controller is configured to identify the high - bandwidth communication link for communicating with the second test measurement device when transferring test data acquired by the second test measurement device to the first test measurement device, and the second device controller is configured to identify the high - bandwidth communication link for communicating with the first test measurement device when transferring test data acquired by the first test measurement device to the second test measurement device The test measurement system of Claim 2.

4. The first device controller is configured to identify the low - delay communication link for communicating with the second test measurement device when the first device controller determines to transmit a control command to the second test measurement device The test measurement system of Claim 2. The first device controller includes a low-latency protocol core, the low-latency communication link includes a low-latency communication core, the low-latency protocol core and the low-latency communication core operate jointly, and are configured to transmit control commands to the second test measurement device via the low-latency communication link. The test measurement system according to claim 2.

6. The test measurement system according to claim 1, wherein each of the high-bandwidth communication link and the low-latency communication link includes a switch configured to couple the second test measurement device and one or more additional test measurement devices to the first test measurement device.

7. In the first test measurement device, a process of determining whether communication with the second test measurement device is necessary, In the first test measurement device, a process of determining the type of necessary communication, In the first test measurement device, based on the type of communication, a high-bandwidth communication link having a first delay time coupled between the first test measurement device and the second test measurement device, and also coupled between the first test measurement device and the second test measurement device, independent of the high-bandwidth communication link, and having a second delay time smaller than the first delay time with respect to communication with the second test measurement device. A process of selecting either a low-latency communication link, A process of communicating with the second test measurement device via the selected high-bandwidth communication link or low-latency communication link A communication method comprising.

8. The process of selecting is When the type of communication is the transfer of test data between the first test measurement device and the second test measurement device, a process of selecting the high-bandwidth communication link, When the type of communication is the communication of control commands between the first test measurement device and the second test measurement device, a process of selecting the low-latency communication link The communication method according to claim 7 having.

9. A first test measurement device, A plurality of additional test measurement devices, A dual-band communication link coupled between the first test measurement device and the plurality of additional test measurement devices Comprising, The dual-band communication link is configured to provide a high-bandwidth communication link having a first delay time for transferring test data between the first test measurement device and each of the plurality of additional test measurement devices, and is further configured to provide a low-latency communication link independent of the high-bandwidth communication link. The low-latency communication link has a second latency time smaller than the first latency time, and is a test measurement system that communicates control commands between the first test measurement device and each of the plurality of additional test measurement devices.

10. The test measurement system according to claim 9, wherein each of the high-bandwidth communication link and the low-latency communication link has an intermediate switch coupled between the first test measurement device and each of the plurality of additional test measurement devices.

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