Display substrate and display device

Abstract

To narrow a frame.SOLUTION: A display substrate 12 includes: a first wiring line 21 located in a display region AA where an image is displayed; second wiring lines 27, 28 located in a non-display region NAA where the image is not displayed; a first circuit unit 18U located in the non-display region NAA and having a first output section GL connected to the first wiring line 21 and first input sections VSS, VDD connected to the second wiring lines 27, 28; and a second circuit unit 20U located in the non-display region NAA and connected to the second wiring lines 27, 28 but not connected to the first wiring line 21, wherein the second circuit unit 20U is located adjacent to the first circuit unit 18U along the second wiring lines 27, 28 in the non-display region NAA.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The technology disclosed in this specification relates to a display substrate and a display device.

Background Art

[0002] Conventionally, as an example of a circuit board provided in a display device, the one described in Patent Document 1 below is known. Patent Document 1 describes a semiconductor device as an example of a circuit board. The semiconductor device described in Patent Document 1 includes a plurality of semiconductor circuits on a substrate, wirings electrically connected to the plurality of semiconductor circuits, input terminals electrically connected to the wirings for supplying electrical signals, and a protection circuit connected to the wirings for protecting the wirings and the semiconductor circuits from static electricity and noise. Among the plurality of semiconductor circuits, at least one of the semiconductor circuits is arranged between the input terminal and the protection circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device described in Patent Document 1 above, the protection circuits are arranged in groups at the end portions on each terminal side and the opposite end portions with respect to the scanning line driving circuit which is a semiconductor circuit. Thus, since a space for arranging the protection circuits is required in the frame area of the active matrix substrate which is a semiconductor device, there is a problem that it is difficult to reduce the frame width of the active matrix substrate.

[0005] The technology described in this specification has been completed based on the above circumstances, and aims to reduce the frame width.

Means for Solving the Problems

[0006] (1) The display substrate related to the technology described in this specification includes a first wiring arranged in a display area where an image is displayed, a second wiring arranged in a non-display area where the image is non-displayed, a first output portion arranged in the non-display area and connected to the first wiring, and a first input portion connected to the second wiring, and a first circuit portion having these; and a second circuit portion arranged in the non-display area and connected to the second wiring but not connected to the first wiring. The second circuit portion is arranged side by side along the second wiring with respect to the first circuit portion in the non-display area.

[0007] (2) Further, in addition to the above (1), the second wiring of the display substrate has a linear portion that is linear along a first direction and a curved portion that is curved so as to intersect the first direction. The first wiring has at least two arranged side by side with a space therebetween in the first direction. The first circuit portion has at least two arranged side by side with a space therebetween along the curved portion. The second circuit portion may be arranged side by side along the curved portion with respect to the first circuit portion and be located between two of the first circuit portions.

[0008] (3) Further, in addition to the above (1), the second wiring of the display substrate has a linear portion that is linear along a first direction and an inclined linear portion that is inclined with respect to the first direction. The first wiring has at least two arranged side by side with a space therebetween in the first direction. The first circuit portion has at least two arranged side by side with a space therebetween along the inclined linear portion. The second circuit portion may be arranged side by side along the inclined linear portion with respect to the first circuit portion and be located between two of the first circuit portions.

[0009] (4) Further, in addition to any one of (1) to (3) above, in the display substrate, the first circuit portion is elongated in a direction intersecting the second wiring, and in the non-display region, a third wiring extending in parallel with the second wiring and located on one end side in the longitudinal direction of the first circuit portion, and a fourth wiring extending in parallel with the second wiring and located on the other end side in the longitudinal direction of the first circuit portion are provided, and the second circuit portion may be arranged within a range sandwiched between the third wiring and the fourth wiring.

[0010] (5) Further, in addition to any one of (1) to (3) above, in the display substrate, the first circuit portion is elongated in a direction intersecting the second wiring, and the second circuit portion may be elongated in parallel with the longitudinal direction of the first circuit portion and arranged within the range in the longitudinal direction of the first circuit portion.

[0011] (6) Further, in addition to any one of (1) to (5) above, in the display substrate, in the display region, a fifth wiring extending along a first direction intersecting the first wiring, a switching element connected to the first wiring and the fifth wiring, and a pixel electrode connected to the switching element are provided, and in the non-display region, a signal supply portion connected to the fifth wiring and supplying an image signal to the fifth wiring is provided, the first wiring and the first circuit portion are arranged side by side in plural along the first direction, and the plural first circuit portions may constitute a shift register circuit that sequentially supplies a scanning signal to the plural first wirings.

[0012] (7) Further, in addition to (6) above, in the display substrate, the second wiring is a power supply wiring, the second circuit portion is connected to the fifth wiring, and may constitute a first protection circuit that protects the fifth wiring and the switching element from electrostatic discharge.

[0013] (8) Further, in addition to the above (6), on the display substrate, in the non-display area, there is provided an inspection circuit that is located on the side opposite to the signal supply unit side with respect to the fifth wiring and is connected to the fifth wiring, and an inspection wiring that extends along the second wiring and is connected to the inspection circuit. The second wiring is a power supply wiring, and the second circuit unit may be connected to the inspection wiring and constitute a second protection circuit that protects the inspection wiring and the inspection circuit from electrostatic discharge.

[0014] (9) Further, in addition to the above (6), on the display substrate, in the non-display area, there is provided a charge removal wiring that extends along the second wiring and is set to a common potential or a ground potential. The second wiring is a first drive wiring that is connected to the signal supply unit and to which a first drive signal is supplied from the signal supply unit as the power-off sequence is executed. The second circuit unit has a second input unit connected to the fifth wiring and a second output unit connected to the charge removal wiring. As the first drive signal is supplied from the first drive wiring, a charge removal circuit that moves the charge of the pixel electrode to the charge removal wiring via the fifth wiring may be constituted.

[0015] (10) Further, in addition to the above (6), on the display substrate, in the display area, there are provided a position detection electrode and a position detection wiring that is connected to the position detection electrode and the signal supply unit and to which a position detection signal is supplied from the signal supply unit during a position detection period in which position detection is performed by the position detection electrode. In the non-display area, there is provided a common wiring that extends along the second wiring and is set to a common potential. The second wiring is a second drive wiring that is connected to the signal supply unit and to which a second drive signal is supplied from the signal supply unit during a display period in which an image is displayed. The second circuit unit has a third output unit connected to the position detection wiring and a third input unit connected to the common wiring. As the second drive signal is supplied from the second drive wiring, a common potential supply circuit that supplies a common potential to the position detection electrode via the position detection wiring may be constituted.

[0016] (11) Further, in addition to the above (10), on the display substrate, in the non-display area, a low-potential wiring connected to the signal supply unit and supplied with a low-potential signal from the signal supply unit is provided. The first circuit unit has an N-channel type transistor, the common potential supply circuit has a P-channel type transistor, the N-channel type transistor has a first gate electrode connected to the second wiring, a first source electrode connected to the low-potential wiring, and a first drain electrode connected to the first wiring, and the P-channel type transistor may have a second gate electrode connected to the second wiring, a second source electrode connected to the common wiring, and a second drain electrode connected to the position detection wiring.

[0017] (12) Further, in addition to any one of the above (1) to (5), on the display substrate, in the display area, a sixth wiring intersecting the first wiring, a switching element connected to the first wiring and the sixth wiring, and a pixel electrode connected to the switching element are provided. In the non-display area, a first signal supply unit connected to the first wiring and supplying an image signal to the first wiring, and a second signal supply unit connected to the sixth wiring and supplying a scanning signal to the sixth wiring are provided. A plurality of the first wirings are arranged side by side, the second wiring is arranged to intersect a plurality of the first wirings, the first circuit unit is connected to a plurality of the first wirings, is interposed between the first signal supply unit and the plurality of the first wirings, and may constitute a switch circuit that distributes the image signal supplied from the first signal supply unit to the plurality of the first wirings.

[0018] (13) Further, in addition to the above (12), on the display substrate, in the non-display area, a power supply wiring extending along the second wiring is provided. The second wiring is a switch wiring connected to the first circuit unit and supplying a switch signal for switching the first wiring that supplies the image signal. The second circuit unit may be connected to the switch wiring and the power supply wiring respectively, and constitute a third protection circuit that protects the switch circuit from electrostatic discharge.

[0019] (14) The display device related to the technology described in this specification includes the display substrate described in any one of (1) to (13) above, and a counter substrate arranged to face the display substrate.

Effect of the Invention

[0020] According to the technology described in this specification, it is possible to achieve a narrow bezel.

Brief Description of the Drawings

[0021]

Figure 1

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Figure 30

Mode for Carrying Out the Invention

[0022] <Embodiment 1> Embodiment 1 will be described with reference to FIGS. 1 to 7. In this embodiment, a liquid crystal panel (display device) 10 will be exemplified. Note that the X-axis, Y-axis, and Z-axis are shown in part of each drawing, and each axis direction is drawn so as to be the direction shown in each drawing.

[0023] As shown in FIG. 1, the liquid crystal panel 10 according to this embodiment has a substantially rectangular planar shape that is vertically long as a whole, and each of the four corner portions has a curved shape (arc shape) with rounded corners. In this liquid crystal panel 10, the short side direction coincides with the X-axis direction, the long side direction coincides with the Y-axis direction, and the plate thickness direction coincides with the Z-axis direction, respectively. The liquid crystal panel 10 is capable of displaying an image using illumination light irradiated from a backlight device (lighting device). In the liquid crystal panel 10, the central portion of the screen is a display area AA where an image is displayed, while the outer peripheral portion in a frame shape surrounding the display area AA on the screen is a non-display area NAA where an image is not displayed. The planar shape of the display area AA is in each case a shape following the outer shape seen in the plane of the liquid crystal panel 10, and is a curved display area AAR with a curved outer shape where each of the four corner portions has a rounded shape. Further, among the display area AA, the portion excluding the curved display area AAR is a linear display area AAL with a linear outer shape along the X-axis direction or the Y-axis direction. On the other hand, the non-display area NAA has an inner peripheral planar shape following the planar shape of the display area AA and an outer peripheral planar shape following the outer shape seen in the plane of the liquid crystal panel 10. Note that the range surrounded by the dashed-dotted line in FIG. 1 is the display area AA.

[0024] As shown in Fig. 2, the liquid crystal panel 10 is configured such that a liquid crystal layer 13 containing liquid crystal molecules, which are substances whose optical properties change with the application of an electric field, is sandwiched between a pair of substrates 11 and 12 made of glass that are substantially transparent and have excellent light transmittance. A seal portion 14 for sealing the liquid crystal layer 13 is provided between the outer peripheral ends of the pair of substrates 11 and 12 with an intervening space. The seal portion 14 is formed in a rectangular frame shape (endless loop shape) so as to surround the liquid crystal layer 13. Polarizing plates 15 are respectively attached to the outer surfaces of both substrates 11 and 12. Of the pair of substrates 11 and 12, the one arranged on the front side is the counter substrate 11, and the one arranged on the back side is the array substrate (display substrate, active matrix substrate) 12. Both the counter substrate 11 and the array substrate 12 are formed by laminating various films on the inner surface sides of glass substrates (substrate portions) 11GS and 12GS. Among these, the long side dimension of the array substrate 12 is made larger than the same dimension of the counter substrate 11. The counter substrate 11 is bonded to the array substrate 12 in such a manner that one end in the long side direction is aligned. Therefore, the other end of the array substrate 12 in the long side direction is an exposed portion 12A that protrudes laterally and is exposed with respect to the counter substrate 11. A driver (signal supply portion) 16 and a flexible substrate 17 are mounted on the exposed portion 12A. In the present embodiment, as shown in Fig. 1, the array substrate 12 has a curved outer shape portion 12R with a curved shape in which each of the four corners at the four corners is rounded. Also, among the array substrate 12, the portion excluding the curved outer shape portion 12R has a linear outer shape portion 12L with a linear shape along the X-axis direction or the Y-axis direction. Further, the counter substrate 11 has a curved shape with rounded corners at a pair of corners at the end in the long side direction opposite to the flexible substrate 17 side.

[0025] The driver 16 is composed of an LSI chip having a drive circuit inside. The driver 16 is COG (Chip On Glass) mounted on the exposed portion 12A of the array substrate 12. The driver 16 processes various signals transmitted by the flexible substrate 17. The driver 16 supplies various signals (such as an image signal, etc.) to various wirings (specifically, source wiring 22, etc., which will be described later) provided on the array substrate 12. The flexible substrate 17 is configured to have a plurality of wiring patterns formed on a base material made of a synthetic resin material (such as a polyimide-based resin, etc.) having insulation and flexibility. As shown in FIGS. 1 and 2, one end side of the flexible substrate 17 is connected to the exposed portion 12A of the array substrate 12, and the other end side is connected to an external circuit board (such as a control board, etc.). The flexible substrate 17 is connected to an end portion of the exposed portion 12A on the side opposite to the display region AA in the Y-axis direction with respect to the driver 16.

[0026] In the non-display region NAA of the glass substrate 12GS of the array substrate 12, as shown in FIG. 1, a gate drive circuit 18, a switch circuit 19, and a first protection circuit 20 are provided. A pair of gate drive circuits 18 are provided so as to sandwich the display region AA from both sides in the X-axis direction. The gate drive circuit 18 is provided in a vertically long strip-shaped range extending along the long side portion (Y-axis direction) of the non-display region NAA. The gate drive circuit 18 has a curved shape in which the planar shapes of both end side portions in the length direction (Y-axis direction) follow the curved display region AAR of the display region AA, respectively. The gate drive circuit 18 is for supplying a scanning signal to the gate wiring 21, which will be described later, and is monolithically provided on the glass substrate 12GS of the array substrate 12. The specific circuit configuration of the gate drive circuit 18 and the like will be described in detail later.

[0027] As shown in FIG. 1, the switch circuit 19 and the first protection circuit 20 are arranged at a position sandwiched between the display area AA and the driver 16 in the Y-axis direction within the non-display area NAA. The switch circuit 19 and the first protection circuit 20 are both provided in a horizontally long strip-shaped range extending along the short side portion (X-axis direction) of the non-display area NAA. The switch circuit 19 and the first protection circuit 20 both have a curved planar shape at both end portions in the length direction (X-axis direction) following the curved display area AAR of the display area AA, respectively. The switch circuit 19 is located closer to the display area AA (farther from the driver 16) than the first protection circuit 20 in the Y-axis direction. The switch circuit 19 has a switch function of distributing the image signal supplied from the driver 16 to the source wiring 22 described later. The first protection circuit 20 is located farther from the display area AA (closer to the driver 16) than the switch circuit 19 in the Y-axis direction. The first protection circuit 20 is for protecting the source wiring 22 and the like described later from electrostatic discharge. The both end portions in the length direction of the first protection circuit 20 are in a relationship of being superimposed on the both end portions in the length direction of the gate drive circuit 18 when viewed in a plane, respectively. Details of the specific circuit configurations of the switch circuit 19 and the first protection circuit 20 will be described later in detail.

[0028] On the inner surface side of the display area AA of the array substrate 12, as shown in FIG. 3, gate wirings (first wirings, scanning wirings) 21 and source wirings (fifth wirings, signal wirings, data wirings) 22 that intersect each other are provided. The gate wiring 21 extends along the X-axis direction (second direction) across the display area AA, and a plurality of them are arranged side by side at intervals in the Y-axis direction. The source wiring 22 extends along the Y-axis direction (first direction) across the display area AA, and a plurality of them are arranged side by side at intervals in the X-axis direction. On the inner surface side of the display area AA of the array substrate 12, a pixel TFT (switching element) 23 and a pixel electrode 24 are provided in a region surrounded by the gate wiring 21 and the source wiring 22. The pixel TFTs 23 and the pixel electrodes 24 are arranged regularly in the X-axis direction and the Y-axis direction in a matrix (row and column) pattern in a planar manner. The pixel TFT 23 includes a gate electrode 23A connected to the gate wiring 21, a source electrode 23B connected to the source wiring 22, a drain electrode 23C connected to the pixel electrode 24, and a semiconductor portion 23D connected to the source electrode 23B and the drain electrode 23C. The pixel TFT 23 is driven based on a scanning signal supplied to the gate wiring 21, and accordingly, a potential based on an image signal (data signal) supplied to the source wiring 22 is charged to the pixel electrode 24.

[0029] On the other hand, on the inner surface side of the display area AA of the counter substrate 11, there are provided color filters of three colors, red (R), green (G), and blue (B), arranged so as to overlap with each pixel electrode 24, a light-shielding portion (black matrix) that partitions between adjacent color filters, and the like. In this liquid crystal panel 10, the R, G, and B color filters arranged along the X-axis direction and the three pixel electrodes 24 facing each color filter constitute pixels of three colors. A pixel is a display unit in the display area AA, and a plurality of pixels are arranged at a predetermined arrangement pitch in the X-axis direction and the Y-axis direction, respectively. Further, as shown in FIG. 3, either the counter substrate 11 or the array substrate 12 is provided with a common electrode 25 made of the same transparent electrode material as the pixel electrode 24 and arranged to overlap with a space from the pixel electrode 24. The liquid crystal panel 10 can apply a predetermined electric field to the liquid crystal layer 13 based on the potential difference generated between the common electrode 25 and each pixel electrode 24, thereby enabling each pixel to perform a predetermined gradation display.

[0030] Next, the gate drive circuit 18, the switch circuit 19, and the first protection circuit 20 will be sequentially described in detail. The gate drive circuit 18 is a so-called shift register circuit. Specifically, as shown in FIG. 3, the gate drive circuit 18 has a plurality of unit gate circuit portions (first circuit portions) 18U arranged along its length direction (substantially the Y-axis direction). The unit gate circuit portion 18U has a gate output terminal (first output portion) GL connected to the gate wiring 21 to be connected. The plurality of unit gate circuit portions 18U include, in order from the upper stage side, a first unit gate circuit portion 18A (denoted as "GDm" in FIG. 3), a second unit gate circuit portion 18B (denoted as "GDm+1" in FIG. 3), a third unit gate circuit portion 18C (denoted as "GDm+2" in FIG. 3), and a fourth unit gate circuit portion 18D (denoted as "GDm+3" in FIG. 3). The gate drive circuit 18 is configured by repeating the arrangement of these four unit gate circuit portions 18A to 18D. The gate output terminal GL provided in the first unit gate circuit portion 18A is referred to as the "first gate output terminal GL1", the gate output terminal GL provided in the second unit gate circuit portion 18B is referred to as the "second gate output terminal GL2", the gate output terminal GL provided in the third unit gate circuit portion 18C is referred to as the "third gate output terminal GL3", and the gate output terminal GL provided in the fourth unit gate circuit portion 18D is referred to as the "fourth gate output terminal GL4". In the central portion of the gate drive circuit 18 in the length direction, a plurality of unit gate circuit portions 18U are arranged in a straight line along the outer shape (Y-axis direction) of the linear display area AAL. In the both end portions of the gate drive circuit 18 in the length direction, a plurality of unit gate circuit portions 18U are arranged in a curved line along the outer shape of the curved display area AAR. Among the plurality of gate wirings 21, the gate wiring 21 connected to the first unit gate circuit portion 18A is referred to as the "first gate wiring 21A", the gate wiring 21 connected to the second unit gate circuit portion 18B is referred to as the "second gate wiring 21B", the gate wiring 21 connected to the third unit gate circuit portion 18C is referred to as the "third gate wiring 21C", and the gate wiring 21 connected to the fourth unit gate circuit portion 18D is referred to as the "fourth gate wiring 21D". Each of the gate wirings 21A to 21D is provided in the same number as the number of sets of the unit gate circuit portions 18U.

[0031] Further, in the non-display area NAA of the array substrate 12, as shown in FIG. 3, a plurality of wirings are provided that extend along the length direction of the gate driving circuit 18 and are connected to the gate driving circuit 18. The plurality of wirings include a gate start pulse wiring 26 that transmits a gate start pulse signal GSP, a low potential power supply wiring (second wiring, low potential wiring) 27 that is always at a low potential power supply voltage, a high potential power supply wiring (second wiring) 28 that is always at a high potential power supply voltage, a first clock wiring 29 that transmits a clock signal GCK1, a second clock wiring 30 that transmits a clock signal GCK2, a third clock wiring 31 that transmits a clock signal GCK3, a fourth clock wiring 32 that transmits a clock signal GCK4, a first set wiring 33 that transmits a set signal, a second set wiring 34 that transmits a set signal, a third set wiring 35 that transmits a set signal, a fourth set wiring 36 that transmits a set signal, and a fifth set wiring 37 that transmits a set signal. These wirings 26 to 37 are all connected to the driver 16 and can receive supplies of various signals from the driver 16.

[0032] As shown in FIG. 3, the gate start pulse wiring 26 is connected to the first set terminal S1 of the first unit gate circuit section 18A of the uppermost set among the plurality of unit gate circuit sections 18U. The low potential power supply wiring 27 is connected to the power supply voltage terminal (first input section) VSS of all the unit gate circuit sections 18U. The high potential power supply wiring 28 is connected to the power supply voltage terminal (first input section) VDD of all the unit gate circuit sections 18U. The first clock wiring 29 is connected to the first input terminal GCKin of the first unit gate circuit section 18A and the second input terminal GCKin2 of the third unit gate circuit section 18C. The second clock wiring 30 is connected to the first input terminal GCKin of the second unit gate circuit section 18B and the second input terminal GCKin2 of the fourth unit gate circuit section 18D. The third clock wiring 31 is connected to the second input terminal GCKin2 of the first unit gate circuit section 18A and the first input terminal GCKin of the third unit gate circuit section 18C. The fourth clock wiring 32 is connected to the second input terminal GCKin2 of the second unit gate circuit section 18B and the first input terminal GCKin of the fourth unit gate circuit section 18D. The first set wiring 33 is connected to the first gate wiring 21A located at the uppermost stage among the plurality of gate wirings 21 and the first set terminal S1 of the second unit gate circuit section 18B of the uppermost set among the plurality of unit gate circuit sections 18U. The second set wiring 34 is connected to the second set terminal S2 of the first unit gate circuit section 18A, the first set terminal S1 of the third unit gate circuit section 18C, and the second gate wiring 21B. The third set wiring 35 is connected to the second set terminal S2 of the second unit gate circuit section 18B, the first set terminal S1 of the fourth unit gate circuit section 18D, and the third gate wiring 21C. The fourth set wiring 36 is connected to the second set terminal S2 of the third unit gate circuit section 18C, the first set terminal S1 of the first unit gate circuit section 18A of the next set (excluding the first unit gate circuit section 18A of the uppermost set among the plurality of first unit gate circuit sections 18A), and the fourth gate wiring 21D. The fifth set wiring 37 is connected to the second set terminal S2 of the fourth unit gate circuit section 18D, the first set terminal S1 of the second unit gate circuit section 18B of the next set, and the first gate wiring 21A of the next set.Each of the set wirings 34 to 37 except the first set wiring 33 is provided in the same number as the number of sets of the unit gate circuit portions 18U.

[0033] As shown in FIG. 4, the unit gate circuit portion 18U has a plurality of N-channel transistors NT1 to NT7 and a plurality of P-channel transistors PT1 to PT6. Each of the plurality of N-channel transistors NT1 to NT7 has a threshold voltage (Vgs) set to a high potential (H). On the other hand, each of the plurality of P-channel transistors PT1 to PT6 has a threshold voltage set to a low potential (L). The unit gate circuit portion 18U also has a first internal node VC and a second internal node VCB as connection wirings connecting predetermined transistors to each other.

[0034] As shown in FIG. 4, for the first P-channel transistor PT1, the gate electrode is connected to the second set wiring 34, the source electrode is connected to the power supply voltage terminal VDD, and the drain electrode is connected to the source electrode of the second P-channel transistor PT2. For the second P-channel transistor PT2, the gate electrode is connected to the first set wiring 33, the source electrode is connected to the drain electrode of the first P-channel transistor PT1, and the drain electrode is connected to the source electrode of the third P-channel transistor PT3. For the third P-channel transistor PT3, the gate electrode is connected to the first internal node VC, the source electrode is connected to the drain electrode of the second P-channel transistor PT2, and the drain electrode is connected to the second internal node VCB. For the fourth P-channel transistor PT4, the gate electrode is connected to the second input terminal GCKin2, the source electrode is connected to the power supply voltage terminal VDD, and the drain electrode is connected to the source electrode of the fifth P-channel transistor PT5. For the fifth P-channel transistor PT5, the gate electrode is connected to the second internal node VCB, the source electrode is connected to the drain electrode of the fourth P-channel transistor PT4, and the drain electrode is connected to the first internal node VC. For the sixth P-channel transistor PT6, the gate electrode is connected to the second internal node VCB, the source electrode is connected to the first input terminal GCKin, and the drain electrode is connected to the gate output terminal GL.

[0035] For the first N-channel transistor NT1, the gate electrode is connected to the second set terminal S2, the source electrode is connected to the second internal node VCB, and the drain electrode is connected to the power supply voltage terminal VSS. For the second N-channel transistor NT2, the gate electrode is connected to the first set terminal S1, the source electrode is connected to the second internal node VCB, and the drain electrode is connected to the power supply voltage terminal VSS. For the third N-channel transistor NT3, the gate electrode is connected to the first internal node VC, the source electrode is connected to the second internal node VCB, and the drain electrode is connected to the power supply voltage terminal VSS. For the fourth N-channel transistor NT4, the gate electrode is connected to the second input terminal GCKin2, the source electrode is connected to the first internal node VC, and the drain electrode is connected to the power supply voltage terminal VSS. For the fifth N-channel transistor NT5, the gate electrode is connected to the second internal node VCB, the source electrode is connected to the first internal node VC, and the drain electrode is connected to the power supply voltage terminal VSS. For the sixth N-channel transistor NT6, the gate electrode is connected to the first internal node VC, the source electrode is connected to the first input terminal GCKin, and the drain electrode is connected to the gate output terminal GL. For the seventh N-channel transistor NT7, the gate electrode is connected to the second internal node VCB, the source electrode is connected to the gate wiring 21, and the drain electrode is connected to the power supply voltage terminal VSS.

[0036] Next, the operation of the gate drive circuit 18 will be described with reference to FIG. 5. FIG. 5 is a timing chart related to the operation of the gate drive circuit 18. Prior to the description of the operation of the gate drive circuit 18, each signal and the potential of each terminal shown in FIG. 5 will be described. In FIG. 5, in order from the top, the gate start pulse signal GSP, the clock signals GCK1, GCK2, GCK3, GCK4, the power supply voltage terminal VSS, the power supply voltage terminal VDD, the first set terminal S1, the second set terminal S2, the first input terminal GCKin, the second input terminal GCKin2, the first internal node VC, the second internal node VCB, and the potentials of the gate output terminals GL1, GL2, GL3, GL4 ··· GLn are shown respectively. In the present embodiment, as shown in FIG. 5, the power supply voltage terminal VSS is always maintained at a low potential (denoted as "L" in FIG. 5), which is a constant low-level potential. The power supply voltage terminal VDD is always maintained at a high potential (denoted as "H" in FIG. 5), which is a constant high-level potential. The clock signals GCK1, GCK2, GCK3, GCK4 are all rectangular waves, and the low potential and the high potential are alternately repeated with a constant period. The gate start pulse signal GSP is a rectangular wave, which becomes high immediately before the first clock signal GCK1 in one frame display period becomes high, and is always low otherwise.

[0037] The potentials of the gate output terminals GL1, GL2, GL3, GL4 ··· GLn are all generally rectangular waves. The first gate output terminal GL1 is provided in the first unit gate circuit section 18A of the uppermost set, the second gate output terminal GL2 is provided in the second unit gate circuit section 18B of the uppermost set, the third gate output terminal GL3 is provided in the third unit gate circuit section 18C of the uppermost set, the fourth gate output terminal GL4 is provided in the fourth unit gate circuit section 18D of the uppermost set, and the nth gate output terminal GLn is provided in the nth unit gate circuit section 18U counted from the uppermost. The potential of the first gate output terminal GL1 is synchronized with the clock signal GCK1, the potential of the second gate output terminal GL2 is synchronized with the clock signal GCK2, the potential of the third gate output terminal GL3 is synchronized with the clock signal GCK3, and the potential of the fourth gate output terminal GL4 is synchronized with the clock signal GCK4. The potentials of the first set terminal S1, the second set terminal S2, the first input terminal GCKin, the second input terminal GCKin2, the first internal node VC, and the second internal node VCB described in FIG. 5 are the potentials of the respective terminals S1, S2, GCKin, GCKin2 and the respective internal nodes VC, VCB provided in the second unit gate circuit section 18B (denoted by parentheses as "GDm + 1" in FIG. 5).

[0038] The potential of the first set of terminals S1 is a rectangular wave and matches the potential of the gate output terminal GL provided in the unit gate circuit section 18U one stage before the unit gate circuit section 18U to which the first set of terminals S1 belongs (see FIG. 3). The potential of the second set of terminals S2 is a rectangular wave and matches the potential of the gate output terminal GL of the unit gate circuit section 18U one stage after the unit gate circuit section 18U to which the second set of terminals S2 belongs (see FIG. 3). The potential of the first input terminal GCKin is a rectangular wave and matches the clock signals GCK1 to GCK4 supplied by the clock wirings 29 to 32 connected to the first input terminal GCKin. The potential of the second input terminal GCKin2 is a rectangular wave and matches the clock signals GCK1 to GCK4 supplied by the clock wirings 29 to 32 connected to the second input terminal GCKin2. The potential of the first internal node VC is a rectangular wave. At the timing when a high potential is supplied to the first set of terminals S1, it changes from a low potential to a high potential, and then changes from a high potential to a low potential at the timing when a high potential is supplied to the second input terminal GCKin2. The potential of the second internal node VCB is a rectangular wave. At the timing when a high potential is supplied to the first set of terminals S1, it changes from a high potential to a low potential, and then changes from a low potential to a high potential at the timing when a high potential is supplied from the second input terminal GCKin2.

[0039] Regarding the operation of the gate drive circuit 18, the second unit gate circuit section 18B will be specifically described. First, immediately before TI1 shown in FIG. 5, the first internal node VC, the first set of terminals S1, and the second set of terminals S2 provided in the second unit gate circuit section 18B are at low potential, and the second internal node VCB and the second input terminal GCKin2 are at high potential. During this period, the N-channel transistors NT1, NT2, NT3, NT6 and the P-channel transistors PT4, PT5, PT6 are in the OFF state, and the N-channel transistors NT4, NT5, NT7 and the P-channel transistors PT1, PT2, PT3 are in the ON state.

[0040] At time TI1 shown in FIG. 5, the clock signal GCK1 is input to the first input terminal GCKin of the first unit gate circuit section 18A. Then, since a scan signal is output from the first gate output terminal GL1 of the first unit gate circuit section 18A to the first gate wiring 21A, the first set terminal S1 of the second unit gate circuit section 18B becomes a high potential. As a result, the second P-channel type transistor PT2 provided in the second unit gate circuit section 18B is turned off, and the second N-channel type transistor NT2 is turned on. Along with this, the second internal node VCB of the second unit gate circuit section 18B is maintained at a low potential. Also, the first internal node VC of the second unit gate circuit section 18B is maintained at a high potential.

[0041] When it reaches time TI2 shown in FIG. 5, the clock signal GCK2 is input to the first input terminal GCKin of the second unit gate circuit section 18B. At this time, because the first internal node VC of the second unit gate circuit section 18B is at a high potential, the sixth N-channel type transistor NT6 is turned on, and because the second internal node VCB is at a low potential, the sixth P-channel type transistor PT6 is turned on. Therefore, the clock signal GCK2 input to the input terminal GCKin is output as a scan signal from the second gate output terminal GL2 to the second gate wiring 21B via the sixth N-channel type transistor NT6 and the sixth P-channel type transistor PT6.

[0042] When it reaches time TI3 shown in FIG. 5, the clock signal GCK3 is input to the first input terminal GCKin of the third unit gate circuit section 18C. Then, since a scan signal is output from the third gate output terminal GL3 of the third unit gate circuit section 18C to the third gate wiring 21C, the second set terminal S2 of the second unit gate circuit section 18B becomes a high potential. As a result, the first P-channel type transistor PT1 provided in the second unit gate circuit section 18B is turned off, and the second N-channel type transistor NT2 is turned on. Along with this, the second internal node VCB of the second unit gate circuit section 18B is maintained at a low potential. Also, the first internal node VC of the second unit gate circuit section 18B is maintained at a high potential.

[0043] When it reaches the time point TI4 shown in FIG. 5, the clock signal GCK4 is input to the first input terminal GCKin of the fourth unit gate circuit section 18D. Then, a scan signal is output from the fourth gate output terminal GL4 of the fourth unit gate circuit section 18D to the fourth gate wiring 21D. On the other hand, the clock signal GCK4 is also input to the second input terminal GCKin2 of the second unit gate circuit section 18B. Then, the fourth P-channel type transistor PT4 provided in the second unit gate circuit section 18B is turned off, and the fourth N-channel type transistor NT4 is turned on. Along with this, the first internal node VC of the second unit gate circuit section 18B becomes a low potential, and the second internal node VCB of the second unit gate circuit section 18B becomes a high potential. As a result, the seventh N-channel type transistor NT7 provided in the second unit gate circuit section 18B is turned on, so that the second gate wiring 21B is short-circuited to the power supply voltage terminal VSS and becomes a low potential. As described above, by sequentially and repeatedly supplying the clock signals GCK1, GCK2, GCK3, and GCK4, scan signals are sequentially supplied to the plurality of gate wirings 21 from the upper stage side.

[0044] Next, the configuration of the switch circuit 19 will be described. The switch circuit 19 is a so-called SSD (Source Shared Driving) circuit. As shown in FIG. 3, the switch circuit 19 has a plurality of unit switch circuit portions 19U arranged along its length direction (substantially the X-axis direction). The number of installed unit switch circuit portions 19U is set to 1 / 3 of the number of installed source wirings 22. The unit switch circuit portion 19U has three switch wirings 38 to 40 through which a switch signal for the switch is transmitted, and three switch TFTs 41 to 43 connected to the switch wirings 38 to 40 and the source wiring 22 to control the supply of the image signal. The three switch wirings 38 to 40 are arranged at intervals in the Y-axis direction and all extend along the X-axis direction. The ends of the three switch wirings 38 to 40 extend toward the driver 16 side and are connected to the driver 16. The three switch wirings 38 to 40 are, in order from the upper side of FIG. 3, a red switch wiring 38, a green switch wiring 39, and a blue switch wiring 40. The three switch TFTs 41 to 43 are all N-channel type transistors. The three switch TFTs 41 to 43 are, in order from the left side of FIG. 3, a red switch TFT 41, a green switch TFT 42, and a blue switch TFT 43. The gate electrode of the red switch TFT 41 is connected to the red switch wiring 38, and the drain electrode is connected to the source wiring 22 that supplies an image signal to the pixel electrode 24 constituting the red pixel. The gate electrode of the green switch TFT 42 is connected to the green switch wiring 39, and the drain electrode is connected to the source wiring 22 that supplies an image signal to the pixel electrode 24 constituting the green pixel. The gate electrode of the blue switch TFT 43 is connected to the blue switch wiring 40, and the drain electrode is connected to the source wiring 22 that supplies an image signal to the pixel electrode 24 constituting the blue pixel. The source electrodes of the respective switch TFTs 41 to 43 are all connected to a source main wiring 44 provided in the non-display area NAA of the array substrate 12. One end side of the source main wiring 44 is connected to the driver 16, and the other end side is branched into three and connected to the source electrodes of the respective switch TFTs 41 to 43. The number of installed source main wirings 44 is set to 1 / 3 of the number of installed source wirings 22.In this way, the number of wirings (source trunk wiring 44) existing between the driver 16 and the switch circuit 19 can be reduced to 1 / 3 compared to the case where each source wiring is directly connected to the driver 16. As a result, even when the narrow bezel of the liquid crystal panel 10 progresses, the routing of the source trunk wiring 44 can be easily performed.

[0045] Red image signals for red pixels, green image signals for green pixels, and blue image signals for blue pixels are supplied to the source trunk wiring 44 from the driver 16 in a time-division manner. In synchronization with this, switch signals are supplied from the driver 16 to the three switch wirings 38 to 40. Specifically, at the timing when a red image signal is supplied from the driver 16 to the source trunk wiring 44, a switch signal is supplied from the driver 16 to the red switch wiring 38. As a result, the red switch TFT 41 among the three switch TFTs 41 to 43 is selectively turned on, so that the red image signal can be supplied to the selected source wiring 22 with respect to the pixel electrode 24 constituting the red pixel. At the timing when a green image signal is supplied from the driver 16 to the source trunk wiring 44, a switch signal is supplied from the driver 16 to the green switch wiring 39. As a result, the green switch TFT 42 among the three switch TFTs 41 to 43 is selectively turned on, so that the green image signal can be supplied to the selected source wiring 22 with respect to the pixel electrode 24 constituting the green pixel. At the timing when a blue image signal is supplied from the driver 16 to the source trunk wiring 44, a switch signal is supplied from the driver 16 to the blue switch wiring 40. As a result, the blue switch TFT 43 among the three switch TFTs 41 to 43 is selectively turned on, so that the blue image signal can be supplied to the selected source wiring 22 with respect to the pixel electrode 24 constituting the blue pixel. As described above, according to the switch circuit 19, the source wiring 22 connected to the source trunk wiring 44 can be switched in synchronization with the timing of supplying the image signal from the driver 16 to the source trunk wiring 44.

[0046] Next, the configuration of the first protection circuit 20 will be described. As shown in FIG. 3, the first protection circuit 20 has a plurality of first unit protection circuit portions (second circuit portions) 20U arranged along its length direction (substantially the X-axis direction). The number of installed first unit protection circuit portions 20U matches the number of installed source main wiring 44. The first unit protection circuit portion 20U includes the aforementioned low-potential power supply wiring 27 and high-potential power supply wiring 28, a first protection TFT 45 connected to the low-potential power supply wiring 27 and the source main wiring 44, and a second protection TFT 46 connected to the high-potential power supply wiring 28 and the source main wiring 44. These protection TFTs 45 and 46 are both N-channel type transistors. For the first protection TFT 45, the gate electrode and the drain electrode are connected to the low-potential power supply wiring 27, and the source electrode is connected to the source main wiring 44. For the second protection TFT 46, the gate electrode and the source electrode are connected to the source main wiring 44, and the drain electrode is connected to the high-potential power supply wiring 28. The threshold voltage of the second protection TFT 46 is lower than the maximum potential of the image signal supplied to the source main wiring 44. Therefore, even when an image signal is supplied from the driver 16 to the source main wiring 44, the first protection TFT 45 and the second protection TFT 46 do not turn on. The potential of the image signal supplied to the source main wiring 44 is equal to or higher than the low potential of the low-potential power supply wiring 27 and equal to or lower than the high potential of the high-potential power supply wiring 28. Here, when electrostatic discharge occurs and a surge outside the range from the low potential of the low-potential power supply wiring 27 to the high potential of the high-potential power supply wiring 28 is input to the source main wiring 44, either the first protection TFT 45 or the second protection TFT 46 turns on. As a result, the surge can be discharged to the low-potential power supply wiring 27 or the high-potential power supply wiring 28. Consequently, circuit components (driver 16) and circuit elements (source wiring 22, each switch TFT 41 - 43 of the switch circuit 19, and pixel TFT 23) connected to the source main wiring 44 can be protected from the surge.

[0047] As described above, as shown in FIG. 1, both end portions in the length direction of the first protection circuit 20 are in a relationship of overlapping each other with respect to both end portions in the length direction of the gate drive circuit 18 when viewed in a plane. The configuration of the overlapping portion between the gate drive circuit 18 and the first protection circuit 20 will be described with reference to FIG. 6. FIG. 6 shows a first unit gate circuit portion 18A and a second unit gate circuit portion 18B as unit gate circuit portions 18U constituting the gate drive circuit 18, and one first unit protection circuit portion 20U constituting the first protection circuit 20.

[0048] First, as shown in FIG. 6, each of the wirings 27 to 37 connected to the gate drive circuit 18 and the first protection circuit 20 forms a curved shape along the outer shape of the curved display region AAR in the overlapping portion between the first protection circuit 20 and the gate drive circuit 18. In particular, the low-potential power supply wiring 27 and the high-potential power supply wiring 28 have curved portions 27R and 28R that form a curved shape so as to intersect both in the Y-axis direction and the X-axis direction. The unit gate circuit portion 18U and the first unit protection circuit portion 20U are both longitudinally arranged in a plane with respect to the direction intersecting the curved portions 27R and 28R. And the unit gate circuit portion 18U and the first unit protection circuit portion 20U are arranged side by side along the above-described curved portions 27R and 28R. Specifically, the unit gate circuit portion 18U and the first unit protection circuit portion 20U are arranged in an alternating repeating sequence one by one along the curved portions 27R and 28R in the overlapping portion between the first protection circuit 20 and the gate drive circuit 18. Two unit gate circuit portions 18U are arranged side by side with an interval in the direction along the curved portions 27R and 28R, and one first unit protection circuit portion 20U is sandwiched between these two unit gate circuit portions 18U. Conversely, two first unit protection circuit portions 20U are arranged side by side with an interval in the direction along the curved portions 27R and 28R, and one unit gate circuit portion 18U is sandwiched between these two first unit protection circuit portions 20U. Note that the unit gate circuit portion 18U is connected to each of the gate wiring 21, the low-potential power supply wiring 27, the high-potential power supply wiring 28, etc. and constitutes the gate drive circuit 18, while the first unit protection circuit portion 20U is connected to the low-potential power supply wiring 27, the high-potential power supply wiring 28, etc., but is not connected to the gate wiring 21 and constitutes the first protection circuit 20. Therefore, it can be said that the unit gate circuit portion 18U and the first unit protection circuit portion 20U are functionally different circuit portions.

[0049] As described above, in the non-display area NAA, as shown in FIG. 6, the first unit protection circuit section 20U is arranged side by side along the low-potential power supply wiring 27 and the high-potential power supply wiring 28 with respect to the unit gate circuit section 18U which is a different circuit section. Therefore, if the first unit protection circuit section is arranged side by side along the direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28 with respect to the unit gate circuit section 18U, the arrangement space in the direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28 can be reduced as compared with the case where the first unit protection circuit section is arranged side by side along the direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28. As a result, the arrangement efficiency of the unit gate circuit section 18U and the first unit protection circuit section 20U in the non-display area NAA is improved, and thus the narrow border of the array substrate 12 can be achieved. In particular, in the present embodiment, the first unit protection circuit section 20U is arranged side by side along the curved portions 27R and 28R with respect to the unit gate circuit section 18U and is arranged between two unit gate circuit sections 18U. The interval between the two unit gate circuit sections 18U in the direction along the curved portions 27R and 28R is wider than the interval between the two unit gate circuit sections 18U in the Y-axis direction (the first direction). Therefore, a sufficient arrangement space for the first unit protection circuit section 20U arranged between the two unit gate circuit sections 18U can be secured. As described above, since the first unit protection circuit section 20U can be arranged so as to be side by side with respect to the unit gate circuit section 18U constituting the gate drive circuit (shift register circuit) 18, the first unit protection circuit section 20U can be provided side by side without increasing the arrangement space of the gate drive circuit (shift register circuit) 18. Also, the low potential and the high potential of the gate circuit 18 and the first protection circuit 20 supply the potential to each circuit from a common wiring. When the first unit protection circuit section 20U is arranged side by side along the direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28 with respect to the unit gate circuit section 18U, it is necessary to arrange the low-potential power supply wiring 27 and the high-potential power supply wiring 28 for the gate circuit 18 and the first protection circuit 20 respectively. However, in the present embodiment, since these wirings are made common, it is more advantageous for achieving a narrower border.

[0050] In addition, as shown in FIG. 3, each of the wirings 27 to 37 connected to the gate drive circuit 18 forms a straight line along the outer shape of the linear display region AAL in a portion that does not overlap with the first protection circuit 20 in the gate drive circuit 18. In particular, the low-potential power supply wiring 27 and the high-potential power supply wiring 28 have straight portions 27L and 28L that form a straight line along the Y-axis direction (first direction). Further, each of the wirings 27 and 28 connected to the first protection circuit 20 forms a straight line along the outer shape of the linear display region AAL in a portion that does not overlap with the gate drive circuit 18 in the first protection circuit 20, and extends substantially straight along the X-axis direction. Also, each of the wirings 38 to 40 connected to the switch circuit 19 forms a straight line along the outer shape of the linear display region AAL, and extends substantially straight along the X-axis direction.

[0051] A specific configuration of the overlapping portion between the gate drive circuit 18 and the first protection circuit 20 will be described. In the overlapping portion between the gate drive circuit 18 and the first protection circuit 20, as shown in FIG. 6, one low-potential power supply wiring 27 is arranged at the position closest to the display region AA (innermost peripheral position), and one high-potential power supply wiring 28 is arranged at the position farthest from the display region AA (outermost peripheral position). Between the low-potential power supply wiring 27 at the innermost peripheral position and the high-potential power supply wiring 28 at the outermost peripheral position, each of the transistors NT1 to NT7 and PT1 to PT6 constituting the unit gate circuit portion 18U, each of the protection TFTs 45 and 46 constituting the first unit protection circuit portion 20U, and a wiring group including each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27 are arranged. In this embodiment, two low-potential power supply wirings 27 are provided, one each at the innermost peripheral position and the intermediate position. Also, in FIG. 6, among each of the set wirings 33 to 37, the first set wiring 33, the second set wiring 34, the third set wiring 35, and the fifth set wiring 37 are shown.

[0052] The sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 that constitute the unit gate circuit section 18U are arranged to be sandwiched between the low-potential power supply wiring 27 at the innermost peripheral position and a wiring group including each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27. Each of the protection TFTs 45 and 46 that constitute the first unit protection circuit section 20U is arranged to be sandwiched between the low-potential power supply wiring 27 at the innermost peripheral position and a wiring group including each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27. That is, the sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 that constitute the unit gate circuit section 18U, and each of the protection TFTs 45 and 46 that constitute the first unit protection circuit section 20U are arranged side by side along the curved portions 27R and 28R and have substantially the same distance from the display area AA. The first N-channel transistor NT1 to the fifth N-channel transistor NT5 and the first P-channel transistor PT1 to the fifth P-channel transistor PT5 that constitute the unit gate circuit section 18U are arranged to be sandwiched between the high-potential power supply wiring 28 at the outermost peripheral position and a wiring group including each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27.

[0053] The cross-sectional configurations of the sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 that constitute the unit gate circuit section 18U, and each of the protection TFTs 45 and 46 that constitute the first unit protection circuit section 20U will be described with reference to FIG. 7. FIG. 7 shows each of the films that constitute the above-described transistors NT6, NT7, PT6 and each of the protection TFTs 45 and 46 among the various films laminated and formed on the inner surface side of the glass substrate 12GS that constitutes the array substrate 12. Specifically, FIG. 7 shows, in order from the lower layer side (the glass substrate 12GS side), a base coat film 47, a semiconductor film, a gate insulating film 48, a first metal film, an interlayer insulating film 49, and a second metal film.

[0054] The first metal film and the second metal film 34 are both made of a single-layer film composed of one type of metal material or a laminated film or alloy composed of different types of metal materials, thereby having conductivity. In the display area AA, the first metal film constitutes the gate wiring 21, the gate electrode 23A of the pixel TFT 23, etc. In the non-display area NAA, the first metal film constitutes the source main wiring 44, the gate electrodes of each of the transistors NT1 to NT7 and PT1 to PT6 constituting the unit gate circuit section 18U, and the gate electrodes of each of the protection TFTs 45 and 46 constituting the first unit protection circuit section 20U, etc. In the display area AA, the second metal film constitutes the source wiring 22, the source electrode 23B and the drain electrode 23C of the pixel TFT 23, etc. In the non-display area NAA, the second metal film constitutes each of the wirings 27 to 40, the source electrodes and the drain electrodes of each of the transistors NT1 to NT7 and PT1 to PT6 constituting the unit gate circuit section 18U, and the source electrodes and the drain electrodes of each of the protection TFTs 45 and 46 constituting the first unit protection circuit section 20U, etc.

[0055] The semiconductor film is made of a polycrystalline silicon semiconductor material (semiconductor material) having crystallinity created by a known method such as laser crystallization. The polycrystalline silicon semiconductor material of the semiconductor film has a higher electron mobility compared to an amorphous silicon semiconductor material or an oxide semiconductor material. In the display area AA, the semiconductor film constitutes the semiconductor part 23D of the pixel TFT 23, etc. In the non-display area NAA, the semiconductor film constitutes the semiconductor parts of each of the transistors NT1 to NT7 and PT1 to PT6 constituting the unit gate circuit section 18U, and the semiconductor parts of each of the protection TFTs 45 and 46 constituting the first unit protection circuit section 20U, etc. The base coat film 47, the gate insulating film 48, and the interlayer insulating film 49 are all made of a kind of inorganic material (inorganic resin material) such as SiO2 (silicon oxide, silicon dioxide) or SiN x (silicon nitride), etc. The base coat film 47 is located on the lower layer side of the semiconductor film. The gate insulating film 48 is interposed between the semiconductor film and the first metal film. The interlayer insulating film 49 is interposed between the first metal film and the second metal film. Although not shown in FIG. 7, the array substrate 12 is also provided with a transparent electrode film, etc. constituting the pixel electrode 24.

[0056] The structure of the sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 that make up the unit gate circuit section 18U, and each protection TFT 45, 46 that make up the first unit protection circuit section 20U will be described in detail. As shown in FIG. 7, the drain electrodes of the seventh N-channel transistor NT7 and the sixth P-channel transistor PT6 are shared, and they are connected to the semiconductor section through contact holes formed in the gate insulating film 48 and the interlayer insulating film 49. Similarly, the source electrodes of the sixth P-channel transistor PT6 and the sixth N-channel transistor NT6 are shared, and they are connected to the semiconductor section through contact holes formed in the gate insulating film 48 and the interlayer insulating film 49. Also, the source electrode of the seventh N-channel transistor NT7 is connected to the semiconductor section through a contact hole formed in the gate insulating film 48 and the interlayer insulating film 49. Similarly, the drain electrode of the sixth N-channel transistor NT6 is connected to the semiconductor section through a contact hole formed in the gate insulating film 48 and the interlayer insulating film 49. The gate electrodes of the sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 are superimposed on the respective semiconductor sections with the gate insulating film 48 interposed therebetween. Note that the cross-sectional structures of the first N-channel transistor NT1 to the fifth N-channel transistor NT5 and the first P-channel transistor PT1 to the fifth P-channel transistor PT5 that make up the unit gate circuit section 18U are also the same as the cross-sectional structures of the sixth N-channel transistor NT6, the seventh N-channel transistor NT7, and the sixth P-channel transistor PT6 described above.

[0057] As shown in FIG. 7, the first protection TFT 45 and the second protection TFT 46 have their source electrodes shared and are connected to the semiconductor portion through contact holes formed in the gate insulating film 48 and the interlayer insulating film 49. The drain electrode of the first protection TFT 45 is connected to the semiconductor portion through a contact hole formed in the gate insulating film 48 and the interlayer insulating film 49. The drain electrode of the second protection TFT 46 is connected to the semiconductor portion through a contact hole formed in the gate insulating film 48 and the interlayer insulating film 49. Each gate electrode of the protection TFTs 45 and 46 is superimposed on each semiconductor portion with the gate insulating film 48 interposed therebetween.

[0058] As shown in FIG. 6, the first internal node VC is connected to the gate electrode of the sixth N-channel transistor NT6. The first internal node VC is formed by connecting a portion made of the first metal film and a portion made of the second metal film through a contact hole formed in the interlayer insulating film 49. The portions of the first internal node VC made of the first metal film are all arranged to cross a wiring group including the clock wirings 29 to 32, the set wirings 33 to 37, and the low-potential power supply wiring 27 made of the second metal film. The portion of the first internal node VC made of the first metal film is directly connected to the gate electrode of the third N-channel transistor NT3 and the gate electrode of the third P-channel transistor PT3. Also, the portion of the first internal node VC made of the second metal film is directly connected to the drain electrode of the fifth P-channel transistor PT5 and the source electrode of the fourth N-channel transistor NT4.

[0059] As shown in FIG. 6, the second internal node VCB is connected to each gate electrode of the 7N-channel transistor NT7 and the 6P-channel transistor PT6. The second internal node VCB is formed by connecting a portion made of a first metal film and a portion made of a second metal film through a contact hole formed in the interlayer insulating film 49. The portions of the second internal node VCB made of the first metal film are all arranged so as to cross a wiring group including each clock wiring 29 to 32, each set wiring 33 to 37, and the low-potential power supply wiring 27 made of the second metal film. The portion of the second internal node VCB made of the second metal film is directly connected to the source electrode of the first N-channel transistor NT1, the source electrode of the second N-channel transistor NT2, the source electrode of the third N-channel transistor NT3, and the drain electrode of the third P-channel transistor PT3. Further, the portion of the second internal node VCB made of the second metal film is connected to the gate electrode of the fifth N-channel transistor NT5 and the gate electrode of the fifth P-channel transistor PT5 through the respective contact holes formed in the interlayer insulating film 49.

[0060] Also, as shown in FIG. 6, the first input terminal GCKin is made of a first metal film and is connected to the source electrodes of the sixth N-channel transistor NT6 and the sixth P-channel transistor PT6, and to the predetermined clock wirings GCK1 to GCK4 through the respective contact holes formed in the interlayer insulating film 49. Further, the second input terminal GCKin2 is made of a first metal film, is directly connected to the gate electrodes of the fourth N-channel transistor NT4 and the fourth P-channel transistor PT4, and is connected to the predetermined clock wirings GCK1 to GCK4 through the contact holes formed in the interlayer insulating film 49. The first set terminal S1 is made of a first metal film, is directly connected to the gate electrodes of the second N-channel transistor NT2 and the second P-channel transistor PT2, and is connected to the predetermined set wirings 33 to 37 through the contact holes formed in the interlayer insulating film 49. The second set terminal S2 is made of a first metal film, is directly connected to the gate electrodes of the first N-channel transistor NT1 and the first P-channel transistor PT1, and is connected to the predetermined set wirings 33 to 37 through the contact holes formed in the interlayer insulating film 49.

[0061] The source electrode of the first protection TFT 45, and the gate electrode and the source electrode of the second protection TFT 46 are connected to a source main wiring 44 as shown in FIG. 6. The source main wiring 44 is composed of two parts made of a first metal film and a part made of a second metal film. The part of the source main wiring 44 made of the second metal film is shared with the source electrodes of the first protection TFT 45 and the second protection TFT 46. One part of the source main wiring 44 made of the first metal film is connected to the part made of the second metal film through a contact hole formed in the interlayer insulating film 49 and is directly connected to the gate electrode of the second protection TFT 46. One part of the source main wiring 44 made of the first metal film is drawn out toward the display area AA side across the low-potential power supply wiring 27 located at the innermost periphery. The other part of the source main wiring 44 made of the first metal film is connected to the part made of the second metal film through a contact hole formed in the interlayer insulating film 49 and is drawn out toward the driver 16 side across a wiring group composed of each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27 and the high-potential power supply wiring 28 located at the outermost periphery.

[0062] As shown in FIG. 6, a power supply voltage terminal VDD is connected to the drain electrode of the second protection TFT 46. The power supply voltage terminal VDD is made of a first metal film and is arranged to cross a wiring group composed of each of the clock wirings 29 to 32, each of the set wirings 33 to 37, and the low-potential power supply wiring 27 made of the second metal film. The power supply voltage terminal VDD is connected to the drain electrode of the second protection TFT 46 and the high-potential power supply wiring 28 through a contact hole formed in the interlayer insulating film 49. A power supply voltage terminal VSS is connected to the gate electrode and the drain electrode of the first protection TFT 45. The power supply voltage terminal VSS is made of the second metal film and is directly connected to the drain electrode of the first protection TFT 45 and the low-potential power supply wiring 27 located at the innermost periphery, and is connected to the gate electrode of the first protection TFT 45 through a contact hole formed in the interlayer insulating film 49.

[0063] As described above, as shown in FIG. 6, the unit gate circuit section 18U according to the present embodiment has a longitudinal shape when viewed in a plane, and a low-potential power supply wiring (third wiring) 27 located on one end side (innermost circumference) in the longitudinal direction thereof, and a high-potential power supply wiring (fourth wiring) 28 located on the other end side (outermost circumference) in the longitudinal direction are arranged to be sandwiched therebetween. On the other hand, the first unit protection circuit section 20U is also arranged within a range sandwiched by the low-potential power supply wiring 27 located at the innermost circumference and the high-potential power supply wiring 28 located at the outermost circumference. In other words, the first unit protection circuit section 20U is arranged within the range in the longitudinal direction in the unit gate circuit section 18U. Thus, since the first unit protection circuit section 20U does not protrude from the unit gate circuit section 18U, the arrangement efficiency of the unit gate circuit section 18U and the first unit protection circuit section 20U is further improved.

[0064] As described above, the array substrate (display substrate) 12 of the present embodiment includes a gate wiring (first wiring) 21 arranged in a display area AA where an image is displayed, a low-potential power supply wiring 27 and a high-potential power supply wiring 28 which are second wirings arranged in a non-display area NAA where an image is not displayed, a gate output terminal (first output section) GL arranged in the non-display area NAA and connected to the gate wiring 21, and a power supply voltage terminal VSS and a power supply voltage terminal VDD which are first input sections connected to the low-potential power supply wiring 27 and the high-potential power supply wiring 28 which are second wirings, that is, a unit gate circuit section (first circuit section) 18U, and a first unit protection circuit section (second circuit section) 20U which is arranged in the non-display area NAA and connected to the low-potential power supply wiring 27 and the high-potential power supply wiring 28 which are second wirings but not connected to the gate wiring 21. The first unit protection circuit section 20U is arranged side by side along the low-potential power supply wiring 27 and the high-potential power supply wiring 28 which are second wirings with respect to the unit gate circuit section 18U in the non-display area NAA.

[0065] The unit gate circuit section 18U operates based on input signals such as those input from the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, to the power supply voltage terminal VSS and the power supply voltage terminal VDD, which are the first input sections, and outputs an output signal from the gate output terminal GL to the gate wiring 21 arranged in the display area AA. The first unit protection circuit section 20U is connected to the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, but is not connected to the gate wiring 21, so it is a circuit section different from the unit gate circuit section 18U. In the non-display area NAA, the first unit protection circuit section 20U is arranged side by side along the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, with respect to the unit gate circuit section 18U. Therefore, if the first unit protection circuit section 20U is arranged side by side along a direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, with respect to the unit gate circuit section 18U, compared to this case, the arrangement space in the direction intersecting the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, can be reduced. As a result, the arrangement efficiency of the unit gate circuit section 18U and the first unit protection circuit section 20U in the non-display area NAA is improved, so the narrow bezel of the array substrate 12 can be achieved.

[0066] Also, the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wirings, have straight linear portions 27L, 28L that are linear along the first direction and curved portions 27R, 28R that are curved so as to intersect the first direction. The gate wiring 21 has at least two arranged side by side with an interval in the first direction. The unit gate circuit section 18U has at least two arranged side by side with an interval along the curved portions 27R, 28R. The first unit protection circuit section 20U is arranged side by side along the curved portions 27R, 28R with respect to the unit gate circuit section 18U and is located between two unit gate circuit sections 18U. The interval between two unit gate circuit sections 18U in the direction along the curved portions 27R, 28R is wider than the interval between two unit gate circuit sections 18U in the first direction. Therefore, a sufficient arrangement space for the first unit protection circuit section 20U located between two unit gate circuit sections 18U can be secured.

[0067] Further, the unit gate circuit section 18U is elongated in a direction intersecting with the low potential power supply wiring 27 and the high potential power supply wiring 28 which are the second wirings. In the non-display area NAA, there are provided a low potential power supply wiring 27 which is a third wiring extending in parallel with the low potential power supply wiring 27 and the high potential power supply wiring 28 which are the second wirings and located at one end side in the longitudinal direction of the unit gate circuit section 18U, and a high potential power supply wiring 28 which is a fourth wiring extending in parallel with the low potential power supply wiring 27 and the high potential power supply wiring 28 which are the second wirings and located at the other end side in the longitudinal direction of the unit gate circuit section 18U. The first unit protection circuit section 20U is arranged within a range sandwiched between the low potential power supply wiring 27 which is the third wiring and the high potential power supply wiring 28 which is the fourth wiring. Thus, since the first unit protection circuit section 20U is not configured to protrude from the unit gate circuit section 18U, the arrangement efficiency of the unit gate circuit section 18U and the first unit protection circuit section 20U is further improved.

[0068] Further, the unit gate circuit section 18U is elongated in a direction intersecting with the low potential power supply wiring 27 and the high potential power supply wiring 28 which are the second wirings. The first unit protection circuit section 20U is elongated in a longitudinal shape parallel to the longitudinal direction of the unit gate circuit section 18U and is arranged within the range in the longitudinal direction of the unit gate circuit section 18U. Thus, since the first unit protection circuit section 20U is not configured to protrude from the unit gate circuit section 18U, the arrangement efficiency of the unit gate circuit section 18U and the first unit protection circuit section 20U is further improved.

[0069] Further, in the display area AA, a source wiring (fifth wiring) 22 extending along a first direction intersecting the gate wiring 21, a pixel TFT (switching element) 23 connected to the gate wiring 21 and the source wiring 22, and a pixel electrode 24 connected to the pixel TFT 23 are provided. In the non-display area NAA, a driver (signal supply unit) 16 connected to the source wiring 22 and supplying an image signal to the source wiring 22 is provided. The gate wiring 21 and the unit gate circuit portion 18U are arranged in plural side by side along the first direction, and the plurality of unit gate circuit portions 18U constitute a gate drive circuit (shift register circuit) 18 that sequentially supplies a scanning signal to the plurality of gate wirings 21. A plurality of scanning signals are sequentially supplied from the plurality of unit gate circuit portions 18U to the plurality of gate wirings 21. When the pixel TFT 23 connected to the gate wiring 21 to which the scanning signal is supplied is driven, the pixel electrode 24 connected to the pixel TFT 23 is charged to a potential based on the image signal supplied from the driver 16 to the source wiring 22. Since the first unit protection circuit portion 20U can be arranged so as to be aligned with the unit gate circuit portion 18U constituting the gate drive circuit (shift register circuit) 18, the first unit protection circuit portion 20U can be provided side by side without increasing the layout space of the gate drive circuit 18.

[0070] Further, the second wiring includes a low-potential power supply wiring 27 and a high-potential power supply wiring 28, and the first unit protection circuit portion 20U is connected to the source wiring 22 and constitutes a first protection circuit 20 that protects the source wiring 22 and the pixel TFT 23 from electrostatic discharge. Even when electrostatic discharge occurs, the first unit protection circuit portion 20U constituting the first protection circuit 20 can discharge the surge to the low-potential power supply wiring 27 and the high-potential power supply wiring 28, which are the second wiring. Thereby, the source wiring 22 connected to the first unit protection circuit portion 20U and the pixel TFT 23 connected to the source wiring 22 can be protected from electrostatic discharge.

[0071] Further, the liquid crystal panel (display device) 10 according to the present embodiment includes the above-described array substrate 12 and a counter substrate 11 arranged to face the array substrate 12. The narrow bezel of the liquid crystal panel 10 can be achieved.

[0072] <Embodiment 2> Embodiment 2 will be described with reference to FIGS. 8 to 14. In this Embodiment 2, the first protection circuit 20 described in Embodiment 1 is omitted, a charge extraction circuit 50 is added, and a case where the circuit configuration of the gate drive circuit 118 is changed is shown. Note that redundant descriptions of the same structures, operations, and effects as those in Embodiment 1 described above are omitted.

[0073] As shown in FIG. 8, the array substrate 112 according to this embodiment includes a charge extraction circuit 50 for extracting the charge of the pixel electrode 124. The charge extraction circuit 50 is disposed at a position in the non-display area NAA on the side opposite to the driver 116 and the switch circuit 119 side (the upper side in FIG. 8) with respect to the display area AA in the Y-axis direction. The charge extraction circuit 50 is provided in a horizontally long strip-shaped range along the short side portion (X-axis direction) of the non-display area NAA. The charge extraction circuit 50 has a curved shape in which the planar shapes of both end portions in the length direction (X-axis direction) follow the curved display area AAR of the display area AA, respectively. The charge extraction circuit 50 is arranged such that both end portions in the length direction are superimposed on both end portions in the length direction of the gate drive circuit 118 in a planar view. The circuit configuration of the charge extraction circuit 50 will be described later.

[0074] As shown in FIG. 9, in the non-display area NAA of the array substrate 112, in addition to the gate start pulse wiring 126, the low-potential power supply wiring 127, the high-potential power supply wiring 128, and the respective set wirings 133 to 137, two clock wirings 51 and 52 and three drive wirings 53 to 55 are provided. The two clock wirings 51 and 52 include a first clock wiring 51 that transmits a clock signal GCKA and a second clock wiring 52 that transmits a clock signal GCKB. The three drive wirings 53 to 55 include a first off-sequence drive wiring (first drive wiring, second wiring) 53 that transmits a first off-sequence drive signal (first drive signal), a second off-sequence drive wiring 54 that transmits a second off-sequence drive signal, and an on-sequence drive wiring 55 that transmits an on-sequence drive signal.

[0075] As shown in FIG. 9, the first clock wiring 51 is connected to the first input terminal GCK1 of the first unit gate circuit section 118A, the second input terminal GCK2 of the second unit gate circuit section 118B, the first input terminal GCK1 of the third unit gate circuit section 118C, and the second input terminal GCK2 of the fourth unit gate circuit section 118D. The second clock wiring 52 is connected to the second input terminal GCK2 of the first unit gate circuit section 118A, the first input terminal GCK1 of the second unit gate circuit section 118B, the second input terminal GCK2 of the third unit gate circuit section 118C, and the first input terminal GCK1 of the fourth unit gate circuit section 118D. The first off-sequence drive wiring 53 is connected to each of the first off-sequence input terminals AON of the unit gate circuit sections 118A to 118D. The second off-sequence drive wiring 54 is connected to each of the second off-sequence input terminals AONB of the unit gate circuit sections 118A to 118D. The on-sequence drive wiring 55 is connected to each of the on-sequence input terminals INIT of the unit gate circuit sections 118A to 118D.

[0076] The first set of wirings 133 is connected to the gate start pulse wiring 126 shown in FIG. 9 and the set terminal S of the first unit gate circuit section 118A of the uppermost set among the plurality of unit gate circuit sections 118U. The second set of wirings 134 is connected to the m-th gate wiring 121 (where "m" is an integer) counted from the upper side (for example, the first gate wiring 121A) and the set terminal S of the (m + 1)-th unit gate circuit section 118U (for example, the second unit gate circuit section 118B) counted from the upper side. The third set of wirings 135 is connected to the (m + 1)-th gate wiring 121 (for example, the second gate wiring 121B) counted from the upper side and the set terminal S of the (m + 2)-th unit gate circuit section 118U (for example, the third unit gate circuit section 118C) counted from the upper side. The fourth set of wirings 136 is connected to the (m + 2)-th gate wiring 121 (for example, the third gate wiring 121C) counted from the upper side and the set terminal S of the (m + 3)-th unit gate circuit section 118U (for example, the fourth unit gate circuit section 118D) counted from the upper side. The fifth set of wirings 135 is connected to the (m + 3)-th gate wiring 121 (for example, the fourth gate wiring 121D) counted from the upper side and the set terminal S of the 2m-th unit gate circuit section 118U (for example, the first unit gate circuit section 118A of the next stage). Similar to the above-described Embodiment 1, the low-potential power supply wiring 127 is connected to the power supply voltage terminal VSS of each unit gate circuit section 118U, and the high-potential power supply wiring 128 is connected to the power supply voltage terminal VDD of each unit gate circuit section 118U.

[0077] As shown in FIG. 10, the unit gate circuit section 118U includes transistors T1 to T12, a resistor R1, and a capacitor C1. The transistors T1 to T12 are all N-channel transistors, and all have a high potential (H) as the threshold voltage. The unit gate circuit section 118U also has a first internal node n1, a second internal node n2, and a third internal node n3 as connection wirings for connecting predetermined transistors to each other.

[0078] As shown in FIG. 10, for the first transistor T1, the gate electrode is connected to the first internal node n1, the source electrode is connected to the first input terminal GCK1, and the drain electrode is connected to the gate output terminal GL. For the second transistor T2, the gate electrode is connected to the second internal node n2, the source electrode is connected to the gate output terminal GL, and the drain electrode is connected to the power supply voltage terminal VSS. For the third transistor T3, the gate electrode is connected to the set terminal S, the source electrode is connected to the second off-sequence input terminal AONB, and the drain electrode is connected to the third internal node n3. For the fourth transistor T4, the gate electrode is connected to the second internal node n2, the source electrode is connected to the third internal node n3, and the drain electrode is connected to the power supply voltage terminal VSS. For the fifth transistor T5, the gate electrode is connected to the set terminal S, the source electrode is connected to the second internal node n2, and the drain electrode is connected to the power supply voltage terminal VSS. For the sixth transistor T6, the gate electrode is connected to the second input terminal GCK2, the source electrode is connected to the power supply voltage terminal VDD, and the drain electrode is connected to the second internal node n2. For the seventh transistor T7, the gate electrode is connected to the on-sequence input terminal INIT, the source electrode is connected to the power supply voltage terminal VDD, and the drain electrode is connected to the second internal node n2. For the eighth transistor T8, the gate electrode is connected to the gate output terminal GL, the source electrode is connected to the second internal node n2, and the drain electrode is connected to the power supply voltage terminal VSS. For the ninth transistor T9, the gate electrode is connected to the power supply voltage terminal VDD, the source electrode is connected to the third internal node n3, and the drain electrode is connected to the first internal node n1.

[0079] The 10th transistor T10 has its gate electrode connected to the first off-sequence input terminal AON, its source electrode connected to the third internal node n3, and its drain electrode connected to the power supply voltage terminal VSS. The 11th transistor T11 has its gate electrode connected to the first off-sequence input terminal AON, its source electrode connected to the second internal node n2, and its drain electrode connected to the power supply voltage terminal VSS. The 12th transistor T12 has both its gate electrode and source electrode connected to the first off-sequence input terminal AON, and its drain electrode connected to the gate output terminal GL. The resistor R1 is provided at the second internal node n2, with one end connected to the drain electrode of the 6th transistor T6 and the other end connected to the drain electrode of the 7th transistor T7. The capacitor C1 has one electrode connected to the first internal node n1 and the other electrode connected to the gate output terminal GL.

[0080] Next, the operation of the gate drive circuit 118 will be described with reference to FIG. 11. FIG. 11 is a timing chart related to the operation of the gate drive circuit 118. Prior to the description of the operation of the gate drive circuit 118, the potentials of each signal and each terminal shown in FIG. 11 will be described. In FIG. 11, in order from the top, the clock signals GCKA, GCKB, the power supply voltage terminal VSS, the power supply voltage terminal VDD, the first off-sequence input terminal AON, the second off-sequence input terminal AONB, the on-sequence input terminal INIT, the set terminal S(Gm + 1), the first internal node n1(Gm + 1), the second internal node n2(Gm + 1), the third internal node n3(Gm + 1), and the gate output terminals GLm, GL(Gm + 1) are respectively shown. Note that the set terminal S(Gm + 1), the first internal node n1(Gm + 1), the second internal node n2(Gm + 1), the third internal node n3(Gm + 1), and the gate output terminal GL(Gm + 1) are the set terminal S, the first internal node n1, the second internal node n2, the third internal node n3, and the gate output terminal GL provided in the (m + 1)-th unit gate circuit section 118U counted from the upper side. Also, the gate output terminal GLm is the gate output terminal GL provided in the m-th unit gate circuit section 118U counted from the upper side.

[0081] As shown in Fig. 11, both clock signals GCKA and GCKB are rectangular waves, in which a low potential (denoted as "L" in Fig. 11) and a high potential (denoted as "H" in Fig. 11) are alternately repeated at a constant period. The clock signal GCKA and the clock signal GCKB always have an inverse relationship between the low potential and the high potential. The first off-sequence input terminal AON and the on-sequence input terminal INIT are always maintained at a low potential, which is a constant low-level potential. The second off-sequence input terminal AONB is always maintained at a high potential, which is a constant high-level potential. The potential of the set terminal S(Gm + 1) is synchronized with the potential of the gate output terminal GLm. The potential of the gate output terminal GLm is synchronized with the clock signal GCKB. The potential of the gate output terminal GL(Gm + 1) is synchronized with the clock signal GCKA. The potentials of the first internal node n1(Gm + 1), the second internal node n2(Gm + 1), and the third internal node n3(Gm + 1) will be described in detail later. Similar to the above-described Embodiment 1, the power supply voltage terminal VSS is always maintained at a low potential, which is a constant low-level potential. The power supply voltage terminal VDD is always maintained at a high potential, which is a constant high-level potential.

[0082] Regarding the operation of the gate drive circuit 118, specifically, the (m + 1)-th unit gate circuit section 118U counted from the upper stage side will be taken up and described in detail. At the time point TI1 shown in FIG. 11, the high potential of the clock signal GCKA is input to the first input terminal GCK1 of the m-th unit gate circuit section 118A. Then, since a scan signal is output from the gate output terminal GLm to the connected gate wiring 121, the set terminal S(Gm + 1) of the (m + 1)-th unit gate circuit section 118U becomes high potential. When the set terminal S(Gm + 1) becomes high potential, both the third transistor T3 and the fifth transistor T5 of the (m + 1)-th unit gate circuit section 118U are turned on. Then, the first internal node n1(Gm + 1) and the third internal node n3(Gm + 1) of the (m + 1)-th unit gate circuit section 118U become the high potential of the second off-sequence input terminal AONB. When the first internal node n1(Gm + 1) and the third internal node n3(Gm + 1) become high potential, the capacitor C1 is charged. On the other hand, the high potential of the clock signal GCKA is also input to the second input terminal GCK2 of the (m + 1)-th unit gate circuit section 118U counted from the upper stage side, and although the sixth transistor T6 is turned on, a resistor R1 is connected to the drain electrode of the sixth transistor T6. For this reason, the potential of the second internal node n2(m + 1) becomes low potential through the fifth transistor T5 (the fifth transistor T5 has a switch size such that its driving ability is higher than that of the sixth transistor T6 connected via the resistor R1). Therefore, the fourth transistor T4 is turned off, and the second transistor T2 is turned off.

[0083] At time TI2 shown in FIG. 11, the high potential of the clock signal GCKB is input to the first input terminal GCK1 of the (m + 1)-th unit gate circuit section 118A. Then, the potential of the gate output terminal GL(Gm+1) of the (m + 1)-th unit gate circuit section 118A rises. At this time, since the capacitor C1 is provided between the first internal node n1(Gm+1) and the gate output terminal GL(Gm+1), the potential of the first internal node n1(Gm+1) also rises as the potential of the gate output terminal GL(Gm+1) rises. That is, the first internal node n1(Gm+1) is bootstrapped. As a result, the gate electrode of the first transistor T1 becomes a higher potential, so that the potential of the gate output terminal GL(Gm+1) becomes a high potential. Thereby, a scan signal is output to the (m + 1)-th gate wiring 121. When the potential of the gate output terminal GL(Gm+1) becomes a high potential, the eighth transistor T8 turns on, and the second internal node n2(Gm+1) is maintained at the low potential of the power supply voltage terminal VSS.

[0084] At time TI3 shown in FIG. 11, the high potential of the clock signal GCKA is input to the second input terminal GCK2 of the (m + 1)-th unit gate circuit section 118A. Then, as described above, the fourth transistor T4 is turned on, and the second transistor T2 is turned on. Along with this, the gate output terminal GL(Gm+1) becomes the low potential of the power supply voltage terminal VSS.

[0085] As shown in FIGS. 9 and 12, the charge extraction circuit 50 has a plurality of unit charge extraction circuit portions (second circuit portions) 50U arranged along its longitudinal direction (substantially the X-axis direction). The number of installed unit charge extraction circuit portions 50U is the same as the number of installed source wirings 122. The unit charge extraction circuit portion 50U includes the first off-sequence drive wiring 53 described above, a charge extraction wiring 56, and a charge extraction TFT 57. The charge extraction wiring 56 is connected to the driver 116 or the flexible substrate 117 and is always maintained at a common potential. The charge extraction TFT 57 is an N-channel transistor. The charge extraction TFT 57 has a gate electrode connected to the first off-sequence drive wiring 53, a source electrode connected to a source input terminal (second input portion) 58, and a drain electrode connected to a charge output terminal (second output portion) 59. The source input terminal 58 is connected to the source wiring 122. The charge output terminal 59 is connected to the charge extraction wiring 56. The charge extraction TFT 57 turns on as a first off-sequence drive signal is supplied from the driver 116 to the first off-sequence drive wiring 53.

[0086] Here, the operation of the charge extraction circuit 50 will be described with reference to FIGS. 9, 10, and 13. FIG. 13 is a timing chart related to the operation of the charge extraction circuit 50. In FIG. 13, in addition to the potential of the first off-sequence input terminal AON, the potentials of the second off-sequence input terminal AONB and the on-sequence input terminal INIT are shown. As shown in FIG. 13, the timing at which the first off-sequence drive signal is supplied from the driver 116 to the first off-sequence drive wiring 53 is synchronized with the timing at which the power-off sequence is started as the power supply of the liquid crystal panel 110 is turned off (the timing of switching from normal driving to the power-off sequence). As the power-off sequence is started, when the first off-sequence drive signal is supplied to the first off-sequence drive wiring 53, as shown in FIG. 9, all the charge extraction TFTs 57 provided in the charge extraction circuit 50 are turned on. At this time, as shown in FIG. 10, when each first off-sequence input terminal AON provided in all the unit gate circuit portions 118U becomes high potential, all the gate output terminals GL become high potential, and a scanning signal is supplied to all the gate wirings 121. Accordingly, since all the pixel TFTs 123 are turned on, charges are moved from each pixel electrode 124 to the charge extraction wiring 56 via each source wiring 122. Thereby, the charges of all the pixel electrodes 124 can be extracted. Note that while the power-off sequence is being performed, as shown in FIG. 13, the second off-sequence input terminal AONB is always set to a low potential.

[0087] When the power supply of the liquid crystal panel 110 is turned on and the power-on sequence is started, as shown in FIG. 13, each on-sequence input terminal INIT provided in all the unit gate circuit sections 118U becomes a high potential. Accordingly, as shown in FIG. 10, each seventh transistor T7 provided in all the unit gate circuit sections 118U is turned on, and the second internal node n2 becomes a high potential. Since the potential of the second internal node n2 is not divided by the resistor R1, it becomes equal to or higher than the threshold voltages of the fourth transistor T4 and the second transistor T2. As a result, both the fourth transistor T4 and the second transistor T2 are turned on, so that both the first internal node n1 and the third internal node n3 become low potentials, and the gate output terminal GL becomes a low potential.

[0088] As described above, as shown in FIG. 8, the charge extraction circuit 50 is configured such that both end portions in the length direction overlap the both end portions in the length direction of the gate drive circuit 118 in a planarly overlapping relationship. The configuration of the overlapping portion between the gate drive circuit 118 and the charge extraction circuit 50 will be described with reference to FIG. 14. FIG. 14 shows a first unit gate circuit section 118A and a second unit gate circuit section 118B as unit gate circuit sections 118U constituting the gate drive circuit 118, and one unit charge extraction circuit section 50U constituting the charge extraction circuit 50.

[0089] First, as shown in FIG. 14, each of the wirings 51 to 56, 127, 128, 133 to 137 connected to the gate drive circuit 118 and the charge extraction circuit 50 forms a curved shape along the outer shape of the curved display area AAR in the overlapping portion between the charge extraction circuit 50 and the gate drive circuit 118. In particular, the first off-sequence drive wiring 53 has a curved portion 53R that forms a curved shape so as to intersect both the Y-axis direction and the X-axis direction. The unit gate circuit portion 118U and the unit charge extraction circuit portion 50U are both longitudinally arranged in a plane in a direction intersecting the curved portion 53R. And the unit gate circuit portion 118U and the unit charge extraction circuit portion 50U are arranged side by side along the above-described curved portion 53R. Specifically, the unit gate circuit portion 118U and the unit charge extraction circuit portion 50U are arranged in an alternating array, one by one, along the curved portion 53R in the overlapping portion between the charge extraction circuit 50 and the gate drive circuit 118. Two unit gate circuit portions 118U are arranged side by side with an interval in the direction along the curved portion 53R, and one unit charge extraction circuit portion 50U is sandwiched between these two unit gate circuit portions 118U. Conversely, two unit charge extraction circuit portions 50U are arranged side by side with an interval in the direction along the curved portion 53R, and one unit gate circuit portion 118U is sandwiched between these two unit charge extraction circuit portions 50U. Note that the unit gate circuit portion 118U is connected to each of the gate wiring 121, the low-potential power supply wiring 127, the high-potential power supply wiring 128, the first off-sequence drive wiring 53, etc. and constitutes the gate drive circuit 118, while the unit charge extraction circuit portion 50U is connected to the first off-sequence drive wiring 53, the source wiring 122, and the charge extraction wiring 56, but is not connected to the gate wiring 121 and constitutes the charge extraction circuit 50. Therefore, it can be said that the unit gate circuit portion 118U and the unit charge extraction circuit portion 50U are functionally different circuit portions.

[0090] As described above, in the non-display area NAA, as shown in FIG. 14, the unit charge extraction circuit section 50U is arranged side by side along the first off-sequence drive wiring 53 with respect to the unit gate circuit section 118U, which is a different circuit section. Therefore, if the unit charge extraction circuits are arranged side by side along a direction intersecting the first off-sequence drive wiring 53 with respect to the unit gate circuit section 118U, the arrangement space in the direction intersecting the first off-sequence drive wiring 53 can be reduced compared to the case where they are arranged side by side. As a result, the arrangement efficiency of the unit gate circuit section 118U and the unit charge extraction circuit section 50U in the non-display area NAA is improved, and the narrow border of the array substrate 112 can be achieved. In particular, in the present embodiment, the unit charge extraction circuit section 50U is arranged side by side along the curved portion 53R with respect to the unit gate circuit section 118U and is located between two unit gate circuit sections 118U. The interval between the two unit gate circuit sections 118U along the direction of the curved portion 53R is wider than the interval between the two unit gate circuit sections 118U in the Y-axis direction (first direction). Therefore, a sufficient arrangement space for the unit charge extraction circuit section 50U located between the two unit gate circuit sections 118U can be secured. As described above, since the unit charge extraction circuit section 50U can be arranged side by side with respect to the unit gate circuit section 118U constituting the gate drive circuit 118, the unit charge extraction circuit section 50U can be provided without increasing the arrangement space of the gate drive circuit 118. Also, the first off-sequence drive signals of the gate circuit 118 and the charge extraction circuit 50 supply potentials to the respective circuits from a common wiring. When the charge extraction circuit 50 is arranged side by side along a direction intersecting the first off-sequence drive wiring 53 with respect to the unit gate circuit section 118U, it is necessary to arrange the first off-sequence drive wiring 53 for the charge extraction circuit 50 and the unit gate circuit section 118U, respectively. However, in the present embodiment, since this wiring is shared, it is more advantageous for achieving a narrower border.

[0091] The specific configuration of the overlapping portion between the gate drive circuit 118 and the charge extraction circuit 50 will be described. In the overlapping portion between the gate drive circuit 118 and the charge extraction circuit 50, as shown in FIG. 14, one charge extraction wiring 56 is arranged at the position closest to the display area AA (the innermost peripheral position), and each set of wirings 133 to 137 is arranged at the position farthest from the display area AA (the outermost peripheral position). On the outer peripheral side of the charge extraction wiring 56 at the innermost peripheral position, the second clock wiring 52, the first clock wiring 51, and the high-potential power supply wiring 128 are arranged at intervals in this order. Among this wiring group 51, 52, 56, 128, a low-potential power supply wiring 127 having a larger line width than the other wirings is arranged at a position spaced a predetermined interval from the high-potential power supply wiring 128 located on the outer peripheral side. Between the high-potential power supply wiring 128 located on the outer peripheral side and the wide low-potential power supply wiring 127 among the wiring group 51, 52, 56, 128, the first transistor T1, the second transistor T2, the sixth transistor T6, and the resistor R1 that constitute the unit gate circuit section 118U, and the charge extraction TFT 57 that constitutes the unit charge extraction circuit section 50U are arranged.

[0092] On one side, on the inner peripheral side of each of the set wirings 133 to 137 at the outermost peripheral position, as shown in FIG. 14, the low-potential power supply wiring 127, the on-sequence drive wiring 55, and the high-potential power supply wiring 128 are arranged at intervals in this order. Among this wiring group 55, 127, 128, 133 to 137, at a position with a predetermined interval on the inner peripheral side with respect to the high-potential power supply wiring 128 located on the inner peripheral side, the first off-sequence drive wiring 53 and the second off-sequence drive wiring 54 are arranged at intervals in this order. Between the high-potential power supply wiring 128 located on the inner peripheral side and the first off-sequence drive wiring 53 among the wiring group 55, 127, 128, 133 to 137, the seventh transistor T7, the eleventh transistor T11, etc. that constitute the unit gate circuit section 118U are arranged. A predetermined interval is provided between the second off-sequence drive wiring 54 and the above-mentioned low-potential power supply wiring 127 with a large width, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, etc. that constitute the unit gate circuit section 118U are arranged. In this embodiment, two low-potential power supply wirings 127 and two high-potential power supply wirings 128 are provided. Also, in FIG. 14, among the set wirings 133 to 137, the first set wiring 133, the second set wiring 134, and the third set wiring 135 are shown.

[0093] In this embodiment, for example, by selectively performing a low-resistance treatment on a semiconductor film, a part of the semiconductor film is made into a conductor with a low resistance. Specifically, among the semiconductor film, a portion that does not overlap with the configuration made of the first metal film is selectively subjected to a low-resistance treatment, and a portion that overlaps with the configuration made of the first metal film is not subjected to a low-resistance treatment. That is, the low-resistance treatment of the semiconductor film is performed using the configuration made of the first metal film as a mask. A part of the resistor R1 and the capacitor C1 (specifically, the electrode connected to the gate output terminal GL) that constitute the unit gate circuit section 118U is constituted by the low-resistance portion of the semiconductor film. Each of the wirings 51 to 55, 127, 128, 133 to 137 is made of a second metal film. Further, for each of the transistors T1 to T12, 57, each gate electrode is made of the first metal film, each source electrode and each drain electrode are made of the second metal film, and each semiconductor portion is made of a portion of the semiconductor film that is not low-resistance treated. Note that contact holes are formed by opening at the connection locations between the configuration made of the first metal film and the configuration made of the second metal film and at the connection locations between the configuration made of the second metal film and the configuration made of the semiconductor film in each of the insulating films 48, 49 (see FIG. 7).

[0094] The drain electrode of the first transistor T1 that constitutes the unit gate circuit section 118U and the drain electrode of the second transistor T2 are commoned as shown in FIG. 14 and are connected to the gate output terminal GL. The gate output terminal GL has two portions made of a first metal film and a portion made of a second metal film, and one portion made of the first metal film is connected to the drain electrodes of the transistors T1 and T2. One portion of the gate output terminal GL made of the first metal film extends toward the inner peripheral side at one end, crosses the wirings 51, 52, 56, and 128, and is connected to the gate wiring 121 within the display region AA. One portion of the gate output terminal GL made of the first metal film is drawn out to the side opposite to the first transistor T1 side with respect to the second transistor T2 at the other end, extends toward the outer peripheral side, is arranged across the wide low-potential power supply wiring 127, and is commoned with the gate electrode of the eighth transistor T8. A portion made of the second metal film is connected to the other end portion of one portion of the gate output terminal GL made of the first metal film. The portion of the gate output terminal GL made of the second metal film is connected to the drain electrode of the twelfth transistor T12 and is connected to the other portion of the gate output terminal GL made of the first metal film. The other portion of the gate output terminal GL made of the first metal film extends from the connection point with the portion made of the second metal film toward the outer peripheral side, is arranged across the wirings 53, 54, 55, 127, and 128, and is connected to the set wirings 133 to 137.

[0095] The source electrode of the first transistor T1 and one of the clock wirings 51 and 52 are connected by a first input terminal GCK1 made of a first metal film as shown in FIG. 14. The gate electrode of the first transistor T1 is directly connected to the electrode of the capacitor C1 made of the first metal film. The electrode of the capacitor C1 made of the first metal film is connected to the drain electrode of the ninth transistor T9. The capacitor C1 is configured such that an electrode made of the first metal film and an electrode made of a low-resistance portion of the semiconductor film overlap via a gate insulating film 48 (see FIG. 7). Note that the capacitor C1 is disposed so as to overlap with a wide low-power-supply potential wiring 127. The drain electrode of the second transistor T2 is directly connected to the low-potential power supply wiring 127. The gate electrode of the second transistor T2 extends across the wide low-potential power supply wiring 127 and is directly connected to the gate electrode of the fourth transistor T4 and is also connected to the second internal node n2.

[0096] As shown in FIG. 14, the second internal node n2 has a portion made of a first metal film and two portions made of a second metal film. The gate electrode of the fourth transistor T4 is connected to one of the portions made of the second metal film of the second internal node n2. One of the portions made of the second metal film of the second internal node n2 is routed so as to surround the eighth transistor T8, the ninth transistor T9, the third transistor T3, and the fifth transistor T5, and a portion made of the first metal film is connected to a part thereof. The portion made of the first metal film of the second internal node n2 extends across the wirings 53 and 54 toward the outer peripheral side and is connected to the other portion made of the second metal film of the second internal node n2. The other portion made of the second metal film of the second internal node n2 extends along the first off-sequence drive wiring 53.

[0097] As shown in FIG. 14, the gate electrode of the sixth transistor T6 is directly connected to a second input terminal GCK2 made of a first metal film. The second input terminal GCK2 is connected to one of the clock wirings 51 and 52. The source electrode of the sixth transistor T6 is shared with the power supply voltage terminal VDD and is connected to the high power potential wiring 128. The drain electrode of the sixth transistor T6 is connected to one end of the resistor R1. The resistor R1 extends from the high power potential wiring 128 side located on the inner peripheral side toward the wide low potential power supply wiring 127 side, and is connected to the source electrode of the fifth transistor T5 at a position crossing the wide low potential power supply wiring 127. The drain electrode of the fifth transistor T5 is connected to the wide low potential power supply wiring 127. The gate electrode of the fifth transistor T5 is directly connected to the gate electrode of the third transistor T3. The gate electrode of the third transistor T3 extends across the wirings 53 to 54, 127, and 128 toward the outer peripheral side and is connected to one of the set wirings 133 to 137. The source electrode of the third transistor T3 is connected to a second off-sequence input terminal AONB made of a first metal film. The second off-sequence input terminal AONB is connected to the second off-sequence drive wiring 54. The drain electrode of the third transistor T3 is connected to a third internal node n3 made of a second metal film.

[0098] As shown in FIG. 14, the source electrodes of the ninth transistor T9, the tenth transistor T10, and the fourth transistor T4 are connected to the third internal node n3. The gate electrode of the ninth transistor T9 is directly connected to the power supply voltage terminal VDD made of the first metal film. This power supply voltage terminal VDD extends from the gate electrode of the ninth transistor T9 toward the outer peripheral side and is connected to the high power supply potential wiring 128. The drain electrode of the ninth transistor T9 is connected to the electrode made of the first metal film of the capacitor C1. The gate electrode of the tenth transistor T10 is directly connected to the first off-sequence input terminal AON made of the first metal film. This first off-sequence input terminal AON extends from the gate electrode of the tenth transistor T10 toward the outer peripheral side and is connected to the first off-sequence drive wiring 53. The drain electrode of the tenth transistor T10 is shared with the power supply voltage terminal VSS and is connected to the low power supply potential wiring 127. The gate electrode of the fourth transistor T4 is connected to one part made of the second metal film among the second internal nodes n2. The drain electrode of the fourth transistor T4 is shared with the power supply voltage terminal VSS and is connected to the low power supply potential wiring 127.

[0099] As shown in FIG. 14, the source electrode of the eighth transistor T8 is connected to one part made of the second metal film among the second internal nodes n2. The drain electrode of the eighth transistor T8 is shared with the power supply voltage terminal VSS and is connected to the low power potential wiring 127. The gate electrode of the seventh transistor T7 is connected to the on-sequence input terminal INIT made of the first metal film. The on-sequence input terminal INIT is connected to the on-sequence drive wiring 55. The source electrode of the seventh transistor T7 is shared with the power supply voltage terminal VDD and is connected to the high power potential wiring 128. The drain electrode of the seventh transistor T7 is connected to the other part made of the second metal film among the second internal nodes n2. The gate electrode of the eleventh transistor T11 is directly connected to the first off-sequence input terminal AON made of the first metal film. This first off-sequence input terminal AON is connected to the first off-sequence drive wiring 53. The source electrode of the eleventh transistor T11 is connected to the other part made of the second metal film among the second internal nodes n2. The drain electrode of the eleventh transistor T11 is connected to the power supply voltage terminal VSS made of the first metal film. This power supply voltage terminal VSS is connected to the low power potential wiring 127. The gate electrode of the twelfth transistor T12 is directly connected to the first off-sequence input terminal AON made of the first metal film. This first off-sequence input terminal AON extends from the gate electrode of the twelfth transistor T12 toward the outer peripheral side and is connected to the first off-sequence drive wiring 53. The source electrode of the twelfth transistor T12 is connected to the gate electrode.

[0100] As shown in FIG. 14, the gate electrode of the charge extraction TFT 57 that constitutes the unit charge extraction circuit section 50U is directly connected to the first off-sequence input terminal AON made of the first metal film. The first off-sequence input terminal AON extends outward from the gate electrode of the charge extraction TFT 57 toward the outer peripheral side, is arranged across the wide low power supply potential wiring 127, and its end is connected to the first off-sequence drive wiring 53. The source electrode of the charge extraction TFT 57 is connected to the source input terminal 58 made of the first metal film. The source input terminal 58 extends inward from the connection point with the source electrode of the charge extraction TFT 57, crosses the respective wirings 51, 52, 56, 128, and is connected to the source wiring 122 within the display area AA. The drain electrode of the charge extraction TFT 57 is connected to the charge output terminal 59 made of the first metal film. The charge output terminal 59 extends inward from the connection point with the drain electrode of the charge extraction TFT 57, crosses the respective wirings 51, 52, 128, and is connected to the charge extraction wiring 56.

[0101] As described above, as shown in FIG. 14, the unit gate circuit section 118U according to the present embodiment is longitudinally shaped when viewed in plan, and the charge extraction wiring 56 (third wiring) 56 located at one end side (innermost circumference) in the longitudinal direction thereof and each set wiring (fourth wiring) 133 to 137 located at the other end side (outermost circumference) in the longitudinal direction are arranged to be sandwiched therebetween. On the other hand, the unit charge extraction circuit section 50U is also arranged within the range sandwiched by the charge extraction wiring 56 located at the innermost circumference and each set wiring 133 to 137 located at the outermost circumference. In other words, the unit charge extraction circuit section 50U is arranged within the range in the longitudinal direction in the unit gate circuit section 118U. Thus, since the unit charge extraction circuit section 50U does not protrude from the unit gate circuit section 118U, the arrangement efficiency of the unit gate circuit section 118U and the unit charge extraction circuit section 50U is further improved.

[0102] As described above, according to the present embodiment, the non-display area NAA is provided with a charge extraction wiring 56 that extends along the second wiring and has a common potential or a ground potential. The second wiring is a first off-sequence drive wiring (first drive wiring) 53 that is connected to the driver 116 and to which a first drive signal is supplied from the driver 116 as a power-off sequence is executed. The second circuit section has a source input terminal (second input section) 58 connected to the source wiring 122 and a charge output terminal (second output section) 59 connected to the charge extraction wiring 56. As the first drive signal is supplied from the first off-sequence drive wiring 53, a charge extraction circuit 50 is configured to move the charge of the pixel electrode 124 to the charge extraction wiring 56 via the source wiring 122. When the power-off sequence is executed, the first drive signal is supplied from the driver 116 to the second wiring, which is the first off-sequence drive wiring 53. Then, the unit charge extraction circuit section 50U, which is the second circuit section constituting the charge extraction circuit 50, receives the charge of the pixel electrode 124 via the source wiring 122 at the source input terminal 58 and outputs the input charge from the charge output terminal 59 to the charge extraction wiring 56. Thereby, the charge of the pixel electrode 124 can be moved to the charge extraction wiring 56.

[0103] <Embodiment 3> Embodiment 3 will be described with reference to FIGS. 15 to 20. In this Embodiment 3, a touch panel function is added to the liquid crystal panel 210, the first protection circuit 20 described in Embodiment 1 is omitted, a common potential supply circuit 60 is added, and a case where the circuit configuration of the gate drive circuit 218 is changed is shown. Note that redundant descriptions of the same structures, operations, and effects as those in Embodiment 1 described above are omitted.

[0104] As shown in FIG. 15, the liquid crystal panel 210 according to this embodiment has, in addition to a display function for displaying an image, a touch panel function (position input function) for detecting an input position by a user. In the liquid crystal panel 210, a touch panel pattern for exerting the touch panel function is integrated (formed in-cell). This touch panel pattern is of the so-called projected capacitance type, and its detection method is the self-capacitance method. The touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 61 arranged in a matrix within the main surface of the liquid crystal panel 110. The touch electrodes 61 are arranged in the display area AA of the liquid crystal panel 210. Therefore, the display area AA of the liquid crystal panel 210 substantially coincides with a touch area (position input area) where the input position can be detected, and the non-display area NAA substantially coincides with a non-touch area (non-position input area) where the input position cannot be detected. When the user tries to make a position input based on the image in the display area AA of the liquid crystal panel 210 that the user views and brings a finger (position input body), which is a conductor, close to the surface (display surface) of the liquid crystal panel 210, a capacitance is formed between the finger and the touch electrodes 61. As a result, the capacitance detected by the touch electrodes 61 near the finger changes as the finger approaches, becoming different from the touch electrodes 61 far from the finger, so that the input position can be detected based on this. In addition to the illustration in FIG. 26, the specific number of installed touch electrodes 61 can be appropriately changed. The touch electrodes 61 are substantially square in plan view, and the dimension of one side is about several millimeters. Therefore, the touch electrodes 61 are much larger in size in plan view than the pixels described later and are arranged in a range straddling a plurality of pixels in the X-axis direction and the Y-axis direction.

[0105] As shown in FIG. 16, a plurality of touch electrodes 61 are selectively connected to a plurality of touch wirings (position detection wirings) 62 provided on the liquid crystal panel 210. The touch wiring 62 extends generally along the Y-axis direction. One end side is connected to the driver 216 in the non-display area NAA, while the other end side is connected to a specific touch electrode 61 among the plurality of touch electrodes 61 arranged along the Y-axis direction in the display area AA. Further, the touch wiring 62 is connected to a detection circuit. The detection circuit may be provided in the driver 216 or may be provided outside the liquid crystal panel 210 via the flexible substrate 217.

[0106] As shown in FIG. 16, the above-described touch electrodes 61 and touch wirings 62 are both provided on the array substrate 212. Among these, the touch electrode 61 is formed by dividing the common electrode 225 provided on the array substrate 212. Specifically, the common electrode 225 arranged generally in a solid state within the main surface of the array substrate 212 is provided with grid-shaped partition openings, thereby forming a plurality of touch electrodes 61 arranged in a checkerboard pattern in both the X-axis direction and the Y-axis direction. To the touch wiring 62 connected to such a touch electrode 61, a common potential signal related to the image display function and a touch signal (position detection signal) related to the touch panel function are supplied in a time-division manner from the driver 216. The timing when the common potential signal is supplied from the driver 216 to the touch wiring 62 is the display period, and the timing when the touch signal is supplied from the driver 216 to the touch wiring 62 is the sensing period (position detection period). This common potential signal is transmitted to all the touch wirings 62 at the same timing (display period), so that all the touch electrodes 61 become a reference potential based on the common potential signal and function as the common electrode 225. The touch electrode 61 has a touch panel function and also serves as the above-described common electrode 225. During the display period, as described in paragraph 0027, the pixel electrode 24 is charged with a potential based on the image signal (see FIG. 3). During this display period, the touch electrode 61 functions as the common electrode 225.

[0107] As shown in FIG. 16, the array substrate 212 according to this embodiment is provided with a common potential supply circuit 60 for supplying a common potential signal to the touch wiring 62. The common potential supply circuit 60 is arranged at a position in the non-display area NAA on the side opposite to the driver 216 side (the upper side in FIG. 16) with respect to the display area AA in the Y-axis direction. The common potential supply circuit 60 is provided in a horizontally long strip-shaped range extending along the short side portion (X-axis direction) of the non-display area NAA. The planar shapes of both end portions of the common potential supply circuit 60 in the length direction (X-axis direction) are each in a curved shape following the curved display area AAR of the display area AA. The both end portions of the common potential supply circuit 60 in the length direction are in a relationship of being superimposed on the both end portions of the gate drive circuit 218 in the length direction when viewed in plan. The circuit configuration of the common potential supply circuit 60 will be described later again.

[0108] As shown in FIG. 16, in the non-display area NAA of the array substrate 212, in addition to the gate start pulse wiring 226, the low potential power supply wiring 227, the high potential power supply wiring 228, the clock wirings 229 to 232, and the respective set wirings 233 to 237, a common wiring 63 and a common potential circuit drive wiring (second drive wiring) 64 are provided. One end side of the common wiring 63 is connected to the driver 216 or the flexible substrate 217, and is routed so that the other end side is connected to the common potential supply circuit 60. The common potential circuit drive wiring 64 is routed so that one end side is connected to the driver 216 and the other end side is connected to the common potential supply circuit 60. An intermediate portion of the common potential circuit drive wiring 64 located between one end side and the other end side is arranged across the gate drive circuit 218 and is connected to each of the common input terminals VTP of the plurality of unit gate circuit portions 218U.

[0109] As shown in FIG. 17, the unit gate circuit section 218U includes the first to seventh N-channel transistors NT201 to NT207 and the first to sixth P-channel transistors PT201 to PT206, and further includes an eighth negative transistor NT8. For the eighth negative transistor NT8, a first gate electrode NT8G is connected to a common input terminal VTP, a first source electrode NT8S is connected to a gate output terminal GL, and a first drain electrode NT8D is connected to a power supply voltage terminal VSS.

[0110] As shown in FIGS. 16 and 18, the common potential supply circuit 60 includes a plurality of unit common potential supply circuit sections (second circuit sections) 60U arranged along its length direction (substantially the X-axis direction). The number of installed unit common potential supply circuit sections 60U is the same as the number of installed touch wirings 62. The unit common potential supply circuit section 60U includes the common potential circuit drive wiring 64, the common wiring 63, and the common TFT 65 described above. The common wiring 63 is connected to the driver 216 or the flexible substrate 217 and is always maintained at a common potential. The common TFT 65 is a P-channel transistor. For the common TFT 65, a second gate electrode 65G is connected to a common input terminal VTP, a second source electrode 65S is connected to a common potential input terminal (third input section) 66, and a second drain electrode 65D is connected to a common potential output terminal (third output section) 67. The common potential input terminal 66 is connected to the common wiring 63. The common potential output terminal 67 is connected to the touch wiring 62. The common TFT 65 turns on as a common drive signal (second drive signal) is supplied from the driver 216 to the common potential circuit drive wiring 64. Since the common TFT 65 is a P-channel transistor, the common drive signal is at a low potential.

[0111] Here, the operation of the common potential supply circuit 60 will be described with reference to FIGS. 16 to 19. FIG. 19 is a timing chart related to the operation of the common potential supply circuit 60. The potential of the common input terminal VTP is shown in FIG. 19. As shown in FIG. 19, the timing at which the common drive signal is supplied from the driver 216 to the common potential circuit drive wiring 64 is synchronized with the timing at which the display period starts (the timing at which the switching is made from the sensing period to the display period). That is, during the display period, the potential of the common input terminal VTP is set to a low potential. On the other hand, during the sensing period, the potential of the common input terminal VTP is set to a high potential. Specifically, during the display period, as shown in FIGS. 16 and 19, since the common drive signal is supplied from the driver 216 to the common potential circuit drive wiring 64 and the potential of the common input terminal VTP is set to a low potential, all the commoning TFTs 65 provided in the common potential supply circuit 60 are turned on. Then, the common potential of the common wiring 63 is input from the common potential output terminal 67 connected to the second drain electrode 65D of the commoning TFT 65 to the common potential input terminal 66 connected to the second source electrode 65S of the commoning TFT 65, and the input common potential is output from the common potential output terminal 67 to the touch wiring 62. As a result, all the touch electrodes 61 connected to each touch wiring 62 can be set to a common potential, the potential difference between the touch electrodes 61 is also reduced, the lattice-like unevenness for each touch electrode 61 is suppressed, and the display quality can be improved. Also, during the display period, as shown in FIG. 17, since each common input terminal VTP provided in all the unit gate circuit portions 218U is at a low potential, each eighth negative-type transistor NT8 is turned off.

[0112] On the other hand, during the sensing period, as shown in FIGS. 16 and 19, when the potential of the common input terminal VTP becomes high, all the common-mode TFTs 65 provided in the common potential supply circuit 60 are turned off. Therefore, during the sensing period, when a touch signal is supplied from the driver 216 to each touch wiring 62, each touch electrode 61 becomes a potential based on the touch signal. By detecting the potential of each touch electrode 61, touch detection can be performed. During the sensing period, as shown in FIG. 17, when the common input terminals VTP provided in all the unit gate circuit portions 218U become high, each eighth negative-type transistor NT8 is turned on. As a result, all the gate output terminals GL become the low potential of the power supply voltage terminal VSS, and all the pixel TFTs 223 are turned off.

[0113] As described above, as shown in FIG. 15, the common potential supply circuit 60 is configured such that both end portions in the length direction are in a relationship of being superimposed on both end portions in the length direction of the gate drive circuit 218 when viewed in a plane. The configuration of the overlapping portion between the gate drive circuit 218 and the common potential supply circuit 60 will be described with reference to FIG. 20. FIG. 20 shows a first unit gate circuit portion 218A and a second unit gate circuit portion 218B as unit gate circuit portions 218U constituting the gate drive circuit 218, and one unit common potential supply circuit portion 60U constituting the common potential supply circuit 60.

[0114] First, as shown in FIG. 20, each of the wirings 227 to 237, 63, and 64 connected to the gate drive circuit 218 and the common potential supply circuit 60 forms a curved shape along the outer shape of the curved display area AAR in the overlapping portion between the common potential supply circuit 60 and the gate drive circuit 218. In particular, the common potential circuit drive wiring 64 has a curved portion 64R that forms a curved shape so as to intersect both the Y-axis direction and the X-axis direction. The unit gate circuit portion 218U and the unit common potential supply circuit portion 60U are both longitudinally shaped in a plane with respect to the direction intersecting the curved portion 64R. Then, the unit gate circuit portion 218U and the unit common potential supply circuit portion 60U are arranged side by side along the above-described curved portion 64R. Specifically, the unit gate circuit portion 218U and the unit common potential supply circuit portion 60U are arranged in an alternating repeating array one by one along the curved portion 64R in the overlapping portion between the common potential supply circuit 60 and the gate drive circuit 218. Two unit gate circuit portions 218U are arranged side by side with an interval in the direction along the curved portion 64R, and one unit common potential supply circuit portion 60U is sandwiched between these two unit gate circuit portions 218U. Conversely, two unit common potential supply circuit portions 60U are arranged side by side with an interval in the direction along the curved portion 64R, and one unit gate circuit portion 218U is sandwiched between these two unit common potential supply circuit portions 60U. Note that the unit gate circuit portion 218U is connected to each of the gate wiring 221, the low-potential power supply wiring 227, the high-potential power supply wiring 228, etc. and constitutes the gate drive circuit 218, while the unit common potential supply circuit portion 60U is connected to the touch wiring 62, the common wiring 63, and the common potential circuit drive wiring 64, but is not connected to the gate wiring 221 and constitutes the common potential supply circuit 60. Therefore, it can be said that the unit gate circuit portion 218U and the unit common potential supply circuit portion 60U are functionally different circuit portions.

[0115] As described above, in the non-display area NAA, as shown in FIG. 20, the unit common potential supply circuit section 60U is arranged side by side along the common potential circuit drive wiring 64 with respect to the unit gate circuit section 218U which is a different circuit section. Therefore, compared with the case where the unit charge extraction circuits are arranged side by side along the direction intersecting the common potential circuit drive wiring 64 with respect to the unit gate circuit section 218U, the arrangement space in the direction intersecting the common potential circuit drive wiring 64 can be reduced. As a result, the arrangement efficiency of the unit gate circuit section 218U and the unit common potential supply circuit section 60U in the non-display area NAA is improved, and the narrow border of the array substrate 212 can be achieved. In particular, in the present embodiment, the unit common potential supply circuit section 60U is arranged side by side along the curved portion 64R with respect to the unit gate circuit section 218U and is located between two unit gate circuit sections 218U. The interval between the two unit gate circuit sections 218U along the direction of the curved portion 64R is wider than the interval between the two unit gate circuit sections 218U in the Y-axis direction (first direction). Therefore, a sufficient arrangement space for the unit common potential supply circuit section 60U located between the two unit gate circuit sections 218U can be secured. As described above, since the unit common potential supply circuit section 60U can be arranged so as to be aligned with the unit gate circuit section 218U constituting the gate drive circuit 218, the unit common potential supply circuit section 60U can be provided side by side without increasing the arrangement space of the gate drive circuit 218.

[0116] A specific configuration of the overlapping portion between the gate drive circuit 218 and the common potential supply circuit 60 will be described. In the overlapping portion between the gate drive circuit 218 and the common potential supply circuit 60, as shown in FIG. 20, one common wiring 63 is arranged at the position closest to the display area AA (the innermost peripheral position), and a common potential circuit drive wiring 64 is arranged at a position spaced apart from the outer peripheral side of the common wiring 63. A low potential power supply wiring 227 is arranged at a position spaced apart from the common potential circuit drive wiring 64 by a predetermined interval. An eighth N-channel transistor NT8 is arranged in a sandwiched manner between the common potential circuit drive wiring 64 and the low potential power supply wiring 227. The commonizing TFT 65 that constitutes the unit common potential supply circuit section 60U is arranged to be sandwiched between the low potential power supply wiring 227 adjacent to the common potential circuit drive wiring 64 and a wiring group including each clock wiring 229 to 232, each set wiring 233 to 237, and the low potential power supply wiring 227. That is, the sixth N-channel transistor NT206, the seventh N-channel transistor NT207, and the sixth P-channel transistor PT206 that constitute the unit gate circuit section 218U and the commonizing TFT 65 that constitutes the unit common potential supply circuit section 60U are arranged side by side along the curved portion 64R and have substantially the same distance from the display area AA. In addition, contact holes are formed at the connection points between the configurations made of the first metal film and the configurations made of the second metal film and at the connection points between the configurations made of the second metal film and the configurations made of the semiconductor film among the insulating films 48 and 49 (see FIG. 7).

[0117] As shown in FIG. 20, the first gate electrode NT8G of the eighth negative-type transistor NT8 that constitutes the unit gate circuit section 218U is directly connected to the common input terminal VTP made of the first metal film. The common input terminal VTP extends outward from the first gate electrode NT8G of the eighth negative-type transistor NT8 and is connected to the common potential circuit drive wiring 64. The first source electrode NT8S of the eighth negative-type transistor NT8 is directly connected to the portion made of the second metal film among the gate output terminals GL. The portion made of the second metal film among the gate output terminals GL extends toward the side opposite to the first semiconductor section side of the eighth negative-type transistor NT8 and is connected to the portion made of the first metal film among the gate output terminals GL. The first drain electrode NT8D of the eighth negative-type transistor NT8 is directly connected to the power supply voltage terminal VSS made of the second metal film. The power supply voltage terminal VSS is connected to the adjacent low-potential power supply wiring 227.

[0118] As shown in FIG. 20, the second gate electrode 65G of the common-mode TFT 65 that constitutes the unit common potential supply circuit section 60U is directly connected to the common input terminal VTP made of the first metal film. The common input terminal VTP extends inward from the second gate electrode 65G of the common-mode TFT 65, is arranged across the low-power supply potential wiring 227, and its end is connected to the common potential circuit drive wiring 64. The second source electrode 65S of the common-mode TFT 65 is connected to the common potential input terminal 66 made of the first metal film. The common potential input terminal 66 extends inward from the connection point with the second source electrode 65S of the common-mode TFT 65, crosses each of the wirings 64 and 227, and is connected to the common wiring 63. The second drain electrode 65D of the common-mode TFT 65 is connected to the common potential output terminal 67 made of the first metal film. The common potential output terminal 67 extends inward from the connection point with the second drain electrode 65D of the common-mode TFT 65, crosses each of the wirings 63, 64, and 227, and is connected to the touch wiring 62 within the display area AA.

[0119] As described above, according to the present embodiment, in the display area AA, there are provided a touch electrode (position detection electrode) 61 and a touch wiring (position detection wiring) 62 that is connected to the touch electrode 61 and the driver 216 and to which a position detection signal is supplied from the driver 216 during a position detection period in which position detection is performed by the touch electrode 61. In the non-display area NAA, a common wiring 63 that extends along the second wiring and has a common potential is provided. The second wiring is a common potential circuit drive wiring (second drive wiring) 64 to which a common drive signal (second drive signal) is supplied from the driver 216 during a display period in which an image is displayed and which is connected to the driver 216. The second circuit section has a common potential output terminal (third output section) 67 connected to the touch wiring 62 and a common potential input terminal (third input section) 66 connected to the common wiring 63, and constitutes a common potential supply circuit 60 that supplies a common potential to the touch electrode 61 via the touch wiring 62 as the common drive signal is supplied from the common potential circuit drive wiring 64. During the position detection period, position detection can be performed based on the potential of the touch electrode 61 by supplying a position detection signal from the driver 216 to the touch wiring 62. On the other hand, during the display period, a common drive signal is supplied from the driver 216 to the common potential circuit drive wiring 64, which is the second wiring. Then, the unit common potential supply circuit section 60U, which is the second circuit section constituting the common potential supply circuit 60, has a common potential input from the common wiring 63 to the common potential input terminal 66 and outputs the input common potential from the common potential output terminal 67 to the touch wiring 62. Thereby, the touch electrode 61 connected to the touch wiring 62 can be set to a common potential.

[0120] In addition, the non-display area NAA is provided with a low-potential power supply wiring (low-potential wiring) 227 connected to the driver 216 and supplied with a low-potential signal from the driver 216. The unit gate circuit section 218U has an eighth negative transistor (N-channel transistor) NT8, and the common potential supply circuit 60 has a common TFT 65 which is a P-channel transistor. The eighth negative transistor NT8 has a first gate electrode NT8G connected to the common potential circuit drive wiring 64 which is the second wiring, a first source electrode NT8S connected to the low-potential power supply wiring 227, and a first drain electrode NT8D connected to the gate wiring 221. The common TFT 65 which is a P-channel transistor has a second gate electrode 65G connected to the common potential circuit drive wiring 64 which is the second wiring, a second source electrode 65S connected to the common wiring 63, and a second drain electrode 65D connected to the touch wiring 62. During the display period, a low-potential signal is supplied as a common drive signal from the driver 216 to the common potential circuit drive wiring 64 which is the second wiring. Then, the eighth negative transistor NT8 of the unit gate circuit section 218U is turned off, and it is possible to avoid the low potential of the low-potential power supply wiring 227 from being supplied to the gate wiring 221. On the other hand, the common TFT 65 which is a P-channel transistor of the common potential supply circuit 60 is turned on, so that the common potential of the common wiring 63 is supplied to the touch electrode 61 via the touch wiring 62. On the other hand, during the position detection period, a high-potential signal is supplied from the driver 216 to the common potential circuit drive wiring 64 which is the second wiring. Then, the eighth negative transistor NT8 of the unit gate circuit section 218U is turned on, and the low potential of the low-potential power supply wiring 227 is supplied to the gate wiring 221. As a result, it is less likely that the pixel TFT 223 in the display area AA becomes in an ON state during the position detection period. On the other hand, the common TFT 65 which is a P-channel transistor of the common potential supply circuit 60 is turned off, and it is possible to avoid the common potential of the common wiring 63 from being supplied to the touch wiring 62.

[0121] <Embodiment 4> Embodiment 4 will be described with reference to FIGS. 21 to 23. In this Embodiment 4, a case where the configuration described in Embodiment 3 is combined with the configuration described in the above Embodiment 2 is shown. Note that redundant descriptions of the same structures, operations, and effects as those in the above Embodiments 2 and 3 are omitted.

[0122] As shown in FIG. 21, the liquid crystal panel 310 according to this embodiment has a touch panel function and includes touch electrodes 361 and touch wirings 362 for exerting the touch panel function. The configurations of the touch electrodes 361 and the touch wirings 362 are as described in Embodiment 3. An array substrate 312 constituting the liquid crystal panel 310 is provided with a charge extraction circuit 350 and a common potential supply circuit 360. The charge extraction circuit 350 and the common potential supply circuit 360 are arranged at positions on the non-display area NAA on the side opposite to the driver 316 side (the upper side in FIG. 21) with respect to the display area AA in the Y-axis direction. The charge extraction circuit 350 and the common potential supply circuit 360 are provided in a horizontally long strip-shaped range extending along the short side portion (X-axis direction) of the non-display area NAA. The charge extraction circuit 350 and the common potential supply circuit 360 have a curved shape that follows the curved display area AAR of the display area AA in the planar shape of both end portions in the length direction (X-axis direction). The charge extraction circuit 350 and the common potential supply circuit 360 are in a positional relationship where their formation ranges overlap almost entirely in a planar view. The both end portions of the charge extraction circuit 350 and the common potential supply circuit 360 in the length direction are in a relationship of overlapping the both end portions in the length direction of the gate drive circuit 318 in a planar view, respectively.

[0123] As shown in FIG. 21, in the non-display area NAA of the array substrate 312, in addition to the gate start pulse wiring 326, the low potential power supply wiring 327, the high potential power supply wiring 328, the respective set wirings 333 to 337, the clock wirings 351 and 352, the respective off-sequence drive wirings 353 and 354, the on-sequence drive wiring 355, and the charge extraction wiring 356, a common wiring 363 and a common potential circuit drive wiring 364 are provided.

[0124] As shown in FIG. 22, the unit gate circuit section 318U has a 13th transistor T13 in addition to the 1st to 12th transistors T1 to T12. The 13th transistor T13 is a negative-type transistor, and its configuration is the same as that of the 8th negative-type transistor NT8 described in Embodiment 3 (see FIG. 17). For the 13th transistor T13, a 1st gate electrode T13G is connected to a common input terminal VTP, a 1st source electrode T13S is connected to a gate output terminal GL, and a 1st drain electrode T13D is connected to a power supply voltage terminal VSS. Note that the operation of the 13th transistor T13 is the same as the operation of the 8th negative-type transistor NT8 described in Embodiment 3.

[0125] As described above, both end portions in the length direction of the charge extraction circuit 350 and the common potential supply circuit 360 are in a relationship of overlapping, when viewed in plan, with both end portions in the length direction of the gate drive circuit 318, respectively. The configuration of the overlapping portion of the gate drive circuit 318, the charge extraction circuit 350, and the common potential supply circuit 360 will be described. FIG. 23 shows a 1st unit gate circuit section 318A, a 2nd unit gate circuit section 318B, and a 3rd unit gate circuit section 318C as unit gate circuit sections 318U constituting the gate drive circuit 318, one unit charge extraction circuit section 350U constituting the charge extraction circuit 350, and one unit common potential supply circuit section 360U constituting the common potential supply circuit 360.

[0126] First, as shown in FIG. 23, each of the wirings 327, 328, 333 to 337, 351, 352, 353, 354, 355, 356, 363, 364 connected to the gate drive circuit 318, the charge extraction circuit 350, and the common potential supply circuit 360 forms a curve along the outer shape of the curved display region AAR in the overlapping portions of the charge extraction circuit 350 and the common potential supply circuit 360, and the gate drive circuit 318. In particular, the first off-sequence drive wiring 353 and the common potential circuit drive wiring 364 have curved portions 353R, 364R that are curved so as to intersect both in the Y-axis direction and the X-axis direction. The unit gate circuit portion 318U, the unit charge extraction circuit portion 350U, and the unit common potential supply circuit portion 360U are all longitudinally arranged in a plane in a direction intersecting the curved portions 353R, 364R. Then, the unit gate circuit portion 318U, the unit charge extraction circuit portion 350U, and the unit common potential supply circuit portion 360U are arranged side by side along the above-described curved portions 353R, 364R. Specifically, the unit gate circuit portion 318U, the unit charge extraction circuit portion 350U, and the unit common potential supply circuit portion 360U are arranged in an alternating repeating sequence one by one along the curved portions 353R, 364R in the overlapping portion of the charge extraction circuit 350 and the common potential supply circuit 360 and the gate drive circuit 318. Three unit gate circuit portions 318U are arranged at intervals in the direction along the curved portions 353R, 364R. One unit charge extraction circuit portion 350U is sandwiched between the first and second unit gate circuit portions 318U, and one unit common potential supply circuit portion 360U is sandwiched between the second and third unit gate circuit portions 318U.

[0127] Thus, in the non-display area NAA, the unit charge extraction circuit section 350U and the unit common potential supply circuit section 360U are arranged side by side along the first off-sequence drive wiring 353 and the common potential circuit drive wiring 364 with respect to the unit gate circuit section 318U, which is a different circuit section, as shown in FIG. 23. Therefore, if the unit charge extraction circuit section and the unit common potential supply circuit section are arranged side by side along a direction intersecting the first off-sequence drive wiring 353 and the common potential circuit drive wiring 364 with respect to the unit gate circuit section 318U, the arrangement space in the direction intersecting the first off-sequence drive wiring 353 and the common potential circuit drive wiring 364 can be reduced compared to the case where they are arranged in this way. As a result, the arrangement efficiency of the unit gate circuit section 318U, the unit charge extraction circuit section 350U, and the unit common potential supply circuit section 360U in the non-display area NAA is improved, so that the narrow border of the array substrate 312 can be achieved. In particular, in the present embodiment, the unit charge extraction circuit section 350U and the unit common potential supply circuit section 360U are arranged side by side along the curved portions 353R and 364R with respect to the unit gate circuit section 318U and are located between two unit gate circuit sections 318U. The interval between the two unit gate circuit sections 318U in the direction along the curved portions 353R and 364R is wider than the interval between the two unit gate circuit sections 318U in the Y-axis direction (the first direction). Therefore, sufficient arrangement space for the unit charge extraction circuit section 350U and the unit common potential supply circuit section 360U located between the two unit gate circuit sections 318U can be ensured. As described above, since the unit charge extraction circuit section 350U and the unit common potential supply circuit section 360U can be arranged side by side with respect to the unit gate circuit section 318U constituting the gate drive circuit 318, the unit charge extraction circuit section 350U and the unit common potential supply circuit section 360U can be provided side by side without increasing the arrangement space of the gate drive circuit 318. Also, the first off-sequence drive signal and the common potential circuit drive signal of the gate circuit 318, the charge extraction circuit 350, and the common potential supply circuit 360 supply potentials to the respective circuits from a common wiring.When the charge extraction circuit 350 or the common potential supply circuit 360 is arranged side by side along the direction intersecting with the first off-sequence drive wiring 353 and the common potential circuit drive wiring 364 with respect to the unit gate circuit section 318U, it is necessary to arrange the first off-sequence drive wiring 353 for the charge extraction circuit 350 and the unit gate circuit section 318U respectively, and to arrange the common potential circuit drive wiring 364 for the common potential supply circuit 360 and the unit gate circuit section 318U respectively. However, in this embodiment, since these wirings are shared, it is advantageous for making the frame narrower.

[0128] A specific configuration of the overlapping portion among the gate drive circuit 318, the charge extraction circuit 350, and the common potential supply circuit 360 will be described. In the overlapping portion among the gate drive circuit 318, the charge extraction circuit 350, and the common potential supply circuit 360, as shown in FIG. 23, one common potential circuit drive wiring 364 is arranged at the position closest to the display area AA (innermost peripheral position), and a common wiring 363 is arranged at a position spaced apart on the outer peripheral side of the common potential circuit drive wiring 364. A charge extraction wiring 356 is arranged at a position spaced apart from the common wiring 363 by a predetermined interval. A thirteenth transistor T13 is arranged in a sandwiched manner between the common potential circuit drive wiring 364 and the common wiring 363. Among the wiring groups 328, 351, 352, 356, 363, a charge extraction TFT 357 constituting the unit charge extraction circuit section 350U and a commonization TFT 365 constituting the unit common potential supply circuit section 360U are respectively arranged in a sandwiched manner between the high potential power supply wiring 328 located on the outer peripheral side and the low potential power supply wiring 327 having a large width. That is, the first transistor T1 and the second transistor T2 constituting the unit gate circuit section 318U, the charge extraction TFT 357 constituting the unit charge extraction circuit section 350U, and the commonization TFT 365 constituting the unit common potential supply circuit section 360U are arranged side by side along the curved portions 353R, 364R and are arranged such that the distances from the display area AA are substantially the same.

[0129] <Embodiment 5> Embodiment 5 will be described with reference to FIGS. 24 to 28. In this Embodiment 5, a case is shown where the outer shape of the liquid crystal panel 410 is changed from that of Embodiment 1 described above, the first protection circuit 20 is omitted, and an inspection circuit 70 and a second protection circuit 80 are added. Note that redundant descriptions of the same structure, operation, and effects as those of Embodiment 1 described above are omitted.

[0130] As shown in FIG. 24, the liquid crystal panel 410 according to this embodiment has a vertically long rectangular shape, and the corners at the four corners are not rounded. Accordingly, the display area AA has a vertically long rectangular shape where the corners at the four corners are not rounded. The gate driving circuit 418 is provided in a horizontally long strip-shaped range extending along the long side portion (Y-axis direction) of the non-display area NAA, and does not have a curved portion as in Embodiment 1. As shown in FIG. 25, the liquid crystal panel 410 is provided with an inspection circuit 70 for inspecting the source wiring 422 and the pixel TFT 423, and a second protection circuit 80 for protecting the inspection circuit 70 from electrostatic discharge. The inspection circuit 70 is disposed at a position on the opposite side (the upper side in FIGS. 24 and 25) of the driver 416 and the switch circuit 419 with respect to the display area AA in the Y-axis direction in the non-display area NAA. The inspection circuit 70 is provided in a horizontally long strip-shaped range extending along the short side portion (X-axis direction) of the non-display area NAA, and is arranged so as not to overlap with the gate driving circuit 418. On the other hand, the second protection circuit 80 is located in the long side portion of the non-display area NAA and is arranged to overlap with the range where the gate driving circuit 418 exists.

[0131] In the non-display area NAA of the array substrate 412, as shown in FIG. 25, in addition to the gate start pulse wiring 426, the low-potential power supply wiring 427, the high-potential power supply wiring 428, and the respective set wirings 433 to 437, four inspection image wirings 71 to 74 and three inspection drive wirings (inspection wirings) 75R, 75G, 75B are provided. The four inspection image wirings 71 to 74 include a first inspection image wiring 71, a second inspection image wiring 72, a third inspection image wiring 73, and a fourth inspection image wiring 74, and each transmits an image signal for inspection. The three inspection drive wirings 75R, 75G, 75B include a red inspection drive wiring 75R, a green inspection drive wiring 75G, and a blue inspection drive wiring 75B, and each transmits a scanning signal for inspection. These inspection image wirings 71 to 74 and inspection drive wirings 75R, 75G, 75B cross the inspection circuit 70 over the entire length and are routed so as to longitudinally cross the area outside (opposite to the display area AA side) of the gate drive circuit 418. Each end of these inspection image wirings 71 to 74 and inspection drive wirings 75R, 75G, 75B is connected to each inspection terminal portion provided at the end of the array substrate 412 on the side connected to the flexible substrate 417. An inspection device can be connected to each inspection terminal portion, and a scanning signal for inspection and an image signal for inspection can be input from the inspection device.

[0132] The inspection circuit 70 will be described. As shown in FIG. 25, the inspection circuit 70 includes the above-described inspection image wirings 71 to 74 and inspection drive wirings 75R, 75G, 75B, and inspection TFTs 76R, 76G, 76B. The inspection TFTs 76R, 76G, 76B include three types: a red inspection TFT 76R connected to the source wiring 422 for red pixels, a green inspection TFT 76G connected to the source wiring 422 for green pixels, and a blue inspection TFT 76B connected to the source wiring 422 for blue pixels. The three types of inspection TFTs 76R, 76G, 76B are all N-channel transistors. For each of the inspection TFTs 76R, 76G, 76B, the source electrode is connected to any one of the inspection image wirings 71 to 74. The gate electrode of the red inspection TFT 76R is connected to the red inspection drive wiring 75R, and the drain electrode is connected to the source wiring 422 that supplies an image signal to the pixel electrode 424 constituting the red pixel. The gate electrode of the green inspection TFT 76G is connected to the green inspection drive wiring 75G, and the drain electrode is connected to the source wiring 422 that supplies an image signal to the pixel electrode 424 constituting the green pixel. The gate electrode of the blue inspection TFT 76B is connected to the blue inspection drive wiring 75B, and the drain electrode is connected to the source wiring 422 that supplies an image signal to the pixel electrode 424 constituting the blue pixel.

[0133] The connection modes of the inspection image wirings 71 to 74 to the inspection TFTs 76R, 76G, and 76B will be described. For the first inspection image wiring 71, when "m" is an integer, it is connected to the source electrode of the (4m - 3)-th red inspection TFT 76R, the source electrode of the (4m - 3)-th blue inspection TFT 76B, and the source electrode of the (4m - 2)-th green inspection TFT 76G, counting from the left end. For the second inspection image wiring 72, when "m" is an integer, it is connected to the source electrode of the (4m - 3)-th green inspection TFT 76G, the source electrode of the (4m - 2)-th red inspection TFT 76R, and the source electrode of the (4m - 2)-th blue inspection TFT 76B, counting from the left end. For the third inspection image wiring 73, when "m" is an integer, it is connected to the source electrode of the (4m - 1)-th red inspection TFT 76R, the source electrode of the (4m - 1)-th blue inspection TFT 76B, and the source electrode of the 4m-th green inspection TFT 76G, counting from the left end. For the fourth inspection image wiring 74, when "m" is an integer, it is connected to the source electrode of the (4m - 1)-th green inspection TFT 76G, the source electrode of the 4m-th red inspection TFT 76R, and the source electrode of the 4m-th blue inspection TFT 76B, counting from the left end.

[0134] During the inspection, when an inspection scanning signal is input from the inspection device to each inspection driving wiring 75R, 75G, and 75B, the inspection TFTs 76R, 76G, and 76B connected to the inspection driving wiring 75R, 75G, and 75B to which the scanning signal is input become ON states. When an inspection image signal is input from the inspection device to each inspection image wiring 71 to 74 in synchronization with the input of the inspection scanning signal, the inspection image signal is supplied to the source wiring 422 connected to the ON-state inspection TFTs 76R, 76G, and 76B. On the other hand, the gate driving circuit 418 drives a scanning signal on the gate wiring 421 in synchronization with the input of the inspection scanning signal to each inspection driving wiring 75R, 75G, and 75B, turning on each pixel TFT 423. As a result, a predetermined pixel electrode 424 is charged to a potential based on the inspection image signal, so that an inspection image can be displayed. By visually inspecting the inspection image, it is possible to inspect the presence or absence of a disconnection in the source wiring 422, the presence or absence of a malfunction in the pixel TFT 423, and the like.

[0135] The second protection circuit 80 will be described. As shown in FIG. 25, the second protection circuit 80 has a plurality of second unit protection circuit parts (second circuit parts) 80U. The number of installed second unit protection circuit parts 80U is an integral multiple of the number of installed inspection drive wirings 75R, 75G, 75B. The second unit protection circuit part 80U includes a low-potential power supply wiring (second wiring) 427 and a high-potential power supply wiring (second wiring) 428, a first protection TFT 81 connected to either the low-potential power supply wiring 427 or one of the inspection drive wirings 75R, 75G, 75B, and a second protection TFT 82 connected to either the high-potential power supply wiring 428 or one of the inspection drive wirings 75R, 75G, 75B. These protection TFTs 81 and 82 are both N-channel type transistors. The first protection TFT 81 has its gate electrode and drain electrode connected to the low-potential power supply wiring 427, and its source electrode connected to one of the inspection drive wirings 75R, 75G, 75B. The second protection TFT 82 has its gate electrode and source electrode connected to one of the inspection drive wirings 75R, 75G, 75B, and its drain electrode connected to the high-potential power supply wiring 428. The threshold voltage of the second protection TFT 82 is higher than the potential of the inspection scanning signal supplied to the inspection drive wirings 75R, 75G, 75B. Therefore, even when an inspection scanning signal from an inspection device is supplied to the inspection drive wirings 75R, 75G, 75B, the first protection TFT 81 and the second protection TFT 82 do not turn on. The potential of the inspection scanning signal supplied to the inspection drive wirings 75R, 75G, 75B is equal to or higher than the low potential of the low-potential power supply wiring 427 and equal to or lower than the high potential of the high-potential power supply wiring 428. Here, when electrostatic discharge occurs and a surge outside the range from the low potential of the low-potential power supply wiring 427 to the high potential of the high-potential power supply wiring 428 is input to the inspection drive wirings 75R, 75G, 75B, either one of the first protection TFT 81 and the second protection TFT 82 turns on. As a result, the surge can be discharged to the low-potential power supply wiring 427 or the high-potential power supply wiring 428. Consequently, inspection TFTs 76R, 76G, 76B, etc. connected to the inspection drive wirings 75R, 75G, 75B can be protected from the surge.

[0136] Next, the relationship between the gate drive circuit 418 and the second protection circuit 80 will be described with reference to FIG. 26. FIG. 26 shows a first unit gate circuit section 418A and a second unit gate circuit section 418B as unit gate circuit sections 418U that make up the gate drive circuit 418, and one second unit protection circuit section 80U that makes up the second protection circuit 80. Also shown in FIG. 26 are the respective wirings 75R, 75G, 75B, 427 to 437 connected to the gate drive circuit 418 and the second protection circuit 80.

[0137] As shown in FIG. 26, each of the wirings 75R, 75G, 75B, 427 to 437 connected to the gate drive circuit 418 and the second protection circuit 80 is linear and extends along the Y-axis direction (first direction). The arrangement of the wirings 427 to 437 is as described in Embodiment 1. The blue inspection drive wiring 75B is arranged at a position spaced outward from the power supply voltage wiring 428 located on the outer peripheral side among the wirings 427 to 437. The green inspection drive wiring 75G is arranged at a position spaced outward from the blue inspection drive wiring 75B. The red inspection drive wiring 75R is arranged at a position spaced outward from the green inspection drive wiring 75G. The unit gate circuit section 418U and the second unit protection circuit section 80U are longitudinally shaped in a plane with respect to the X-axis direction (second direction) intersecting the respective wirings 75R, 75G, 75B, 427 to 437. And the unit gate circuit section 418U and the second unit protection circuit section 80U are arranged side by side along the above-described respective wirings 75R, 75G, 75B, 427 to 437. Specifically, the second unit protection circuit section 80U is arranged in a form sandwiched between two unit gate circuit sections 418U that are spaced apart in the Y-axis direction. Note that the unit gate circuit section 418U is connected to each of the gate wiring 421, the low-potential power supply wiring 427, the high-potential power supply wiring 428, etc. and constitutes the gate drive circuit 418, while the second unit protection circuit section 80U is connected to the low-potential power supply wiring 427, the high-potential power supply wiring 428, etc., but is not connected to the gate wiring 421 and constitutes the second protection circuit 80. Therefore, it can be said that the unit gate circuit section 418U and the second unit protection circuit section 80U are functionally different circuit sections.

[0138] Thus, in the non-display area NAA, as shown in FIG. 26, the second unit protection circuit section 80U is arranged side by side along the low-potential power supply wiring 427 and the high-potential power supply wiring 428 with respect to the unit gate circuit section 418U which is a different circuit section. Therefore, compared with the case where the second unit protection circuit section is arranged side by side along the direction intersecting the low-potential power supply wiring 427 and the high-potential power supply wiring 428 with respect to the unit gate circuit section 418U, the arrangement space in the direction intersecting the low-potential power supply wiring 427 and the high-potential power supply wiring 428 can be reduced. As a result, the arrangement efficiency of the unit gate circuit section 418U and the second unit protection circuit section 80U in the non-display area NAA is improved, and thus the narrow border of the array substrate 412 can be achieved. As described above, since the second unit protection circuit section 80U can be arranged side by side with respect to the unit gate circuit section 418U constituting the gate drive circuit 418, the second unit protection circuit section 80U can be provided without increasing the arrangement space of the gate drive circuit 418. Also, the low-potential and high-potential power supplies of the gate circuit 418 and the second protection circuit section 80 are each a common wiring. When the second protection circuit section 80 is arranged side by side along the direction intersecting the low-potential power supply wiring 427 and the high-potential power supply wiring 428 with respect to the unit gate circuit section 418U, it is necessary to arrange the low-potential power supply wiring 427 and the high-potential power supply wiring 428 for the second protection circuit section 80 and the unit gate circuit section 418U, respectively. However, in this embodiment, since this wiring is shared, it is more advantageous for narrowing the border.

[0139] Each protection TFTs 81 and 82 that make up the second unit protection circuit section 80U are arranged to be sandwiched between the low-potential power supply wiring 427 at the innermost peripheral position and the wiring group consisting of each clock wiring 429 to 432, each set wiring 433 to 437, and the low-potential power supply wiring 427, as shown in FIG. 26. That is, the sixth N-channel transistor NT406, the seventh N-channel transistor NT407, and the sixth P-channel transistor PT406 that make up the unit gate circuit section 418U, and each protection TFTs 81 and 82 that make up the second unit protection circuit section 80U are arranged side by side along the low-potential power supply wiring 427 and the high-potential power supply wiring 428, and the distances from the display area AA are substantially the same.

[0140] The source electrode of the first protection TFT 81 and the source electrode of the second protection TFT 82 are shared and connected to a connection terminal 83 made of a first metal film, as shown in FIG. 26. The connection terminal 83 extends outward from each source electrode of the protection TFTs 81 and 82, crosses the wiring group consisting of each clock wiring 429 to 432, each set wiring 433 to 437, and the low-potential power supply wiring 427, and is connected to any one of the inspection drive wirings 75R, 75G, and 75B. The gate electrode and the drain electrode of the first protection TFT 81 are connected to each other and connected to a power supply voltage terminal VSS made of a second metal film. The gate electrode and the source electrode of the second protection TFT 82 are connected to each other and connected to a power supply voltage terminal VDD made of a first metal film. The power supply voltage terminal VDD extends outward from the gate electrode and the source electrode of the second protection TFT 82, crosses the wiring group consisting of each clock wiring 429 to 432, each set wiring 433 to 437, and the low-potential power supply wiring 427, and is connected to the high-potential power supply wiring 428.

[0141] As described above, as shown in FIG. 26, the unit gate circuit section 418U according to this embodiment has a longitudinal shape when viewed in a plane, and is arranged between a low-potential power supply wiring (third wiring) 427 located on one end side (innermost circumference) in the longitudinal direction and a red inspection drive wiring (fourth wiring) 75R located on the other end side (outermost circumference) in the longitudinal direction. On the other hand, the second unit protection circuit section 80U is also arranged within a range sandwiched between the low-potential power supply wiring 427 located at the innermost circumference and the red inspection drive wiring 75R located at the outermost circumference. In other words, the second unit protection circuit section 80U is arranged within the range in the longitudinal direction in the unit gate circuit section 418U. In this way, since the second unit protection circuit section 80U does not protrude from the unit gate circuit section 418U, the arrangement efficiency of the unit gate circuit section 418U and the second unit protection circuit section 80U is further improved.

[0142] As described above, according to this embodiment, in the non-display area NAA, there are provided an inspection circuit 70 located on the side opposite to the driver 416 side with respect to the source wiring 422 and connected to the source wiring 422, and inspection drive wirings (inspection wirings) 75R, 75G, 75B that extend along the second wiring and are connected to the inspection circuit 70. The second wiring is the low-potential power supply wiring 427 and the high-potential power supply wiring 428. The second circuit section is connected to the inspection drive wirings 75R, 75G, 75B and constitutes a second protection circuit 80 that protects the inspection drive wirings 75R, 75G, 75B and the inspection circuit 70 from electrostatic discharge. Even when electrostatic discharge occurs, the second unit protection circuit section 80U, which is the second circuit section constituting the second protection circuit 80, can discharge the surge to the low-potential power supply wiring 427 and the high-potential power supply wiring 428, which are the second wiring. Thereby, the inspection drive wirings 75R, 75G, 75B connected to the second unit protection circuit section 80U, which is the second circuit section, and the inspection circuit 70 connected to the inspection drive wirings 75R, 75G, 75B can be protected from electrostatic discharge.

[0143] <Embodiment 6> Embodiment 6 will be described with reference to FIGS. 27 to 29. In this Embodiment 6, the inspection circuit 70 and the second protection circuit 80 are omitted from the above-described Embodiment 5, a third protection circuit 90 is added, and the case where the number of installed drivers 516 is changed is shown. Note that redundant descriptions of the same structures, operations, and effects as those of Embodiment 1 described above are omitted.

[0144] As shown in FIG. 27, the liquid crystal panel 510 according to this embodiment has two drivers 516. The two drivers 516 are arranged at positions spaced apart in the X-axis direction at a position between the flexible substrate 17 and the display area AA. The liquid crystal panel 510 includes a third protection circuit 90 for protecting the switch circuit 519. The third protection circuit 90 is located in the non-display area NAA at the short side portion on the driver 516 side with respect to the display area AA in the Y-axis direction, and is arranged so as to overlap the range where the switch circuit 519 exists. The liquid crystal panel 510 is provided with connection wirings 94 connected to each switch wiring (second wiring) 538 to 540 constituting the switch circuit 519 and the driver 516. The switch signal output from the driver 516 is supplied to each switch wiring 538 to 540 via the connection wiring 94. The number of installed connection wirings 94 is a value obtained by multiplying the number of installed each switch wiring 538 to 540 by the number of installed drivers 516. That is, each driver 516 is connected to each of the switch wirings 538 to 540 by each connection wiring 94.

[0145] Next, the configuration of the third protection circuit 90 will be described. As shown in FIG. 28, the third protection circuit 90 has a plurality of ninth unit protection circuit portions (second circuit portions) 90U arranged along its length direction (substantially the X-axis direction). The number of installed third unit protection circuit portions 90U matches the number of installed connection wirings 94. The third unit protection circuit portion 90U includes the aforementioned low-potential power supply wiring 527 and high-potential power supply wiring 528, a first protection TFT 91 connected to the low-potential power supply wiring 527 and the connection wiring 94, and a second protection TFT 92 connected to the high-potential power supply wiring 528 and the connection wiring 94. These protection TFTs 91 and 92 are both N-channel type transistors. The gate electrode and drain electrode of the first protection TFT 91 are connected to the low-potential power supply wiring 527, and the source electrode is connected to the connection wiring 94. The gate electrode and source electrode of the second protection TFT 92 are connected to the connection wiring 94, and the drain electrode is connected to the high-potential power supply wiring 528. The threshold voltage of the second protection TFT 92 is lower than the potential of the switch signal supplied to the connection wiring 94. Therefore, even when a switch signal is supplied from the driver 516 to the connection wiring 94, the first protection TFT 91 and the second protection TFT 92 do not turn on. The potential of the switch signal supplied to the connection wiring 94 is equal to or higher than the low potential of the low-potential power supply wiring 527 and equal to or lower than the high potential of the high-potential power supply wiring 528. Here, when electrostatic discharge occurs and a surge outside the range from the low potential of the low-potential power supply wiring 527 to the high potential of the high-potential power supply wiring 528 is input to the connection wiring 94, either the first protection TFT 91 or the second protection TFT 92 turns on. As a result, the surge can be discharged to the low-potential power supply wiring 527 or the high-potential power supply wiring 528. Consequently, the driver 516 and the like connected to the connection wiring 94 can be protected from the surge.

[0146] Next, the relationship between the switch circuit 519 and the third protection circuit 90 will be described with reference to FIG. 29. FIG. 29 shows four unit switch circuit portions 519U that constitute the switch circuit 519, and two third unit protection circuit portions 90U that constitute the third protection circuit 90. Further, FIG. 29 shows each wiring 94, 527, 528, 538 to 540 connected to the switch circuit 519 and the third protection circuit 90.

[0147] Each of the wirings 527, 528, 538 to 540 connected to the switch circuit 519 and the third protection circuit 90 is linear and extends along the X-axis direction (first direction) as shown in FIG. 29. The wirings 527, 528, 538 to 540 are arranged at intervals in the Y-axis direction, and in the order of the low-potential power supply wiring 527, the high-potential power supply wiring 528, the blue switch wiring 540, the green switch wiring 539, and the red switch wiring 538 from the side closer to the driver 516. These wirings 527, 528, 538 to 540 are all made of a second metal film. On the other hand, the connection wiring 94 is made of a first metal film, is linear and extends along the Y-axis direction (second direction), and is arranged across the above-described wirings 527, 528, 538 to 540. The unit switch circuit portion 519U and the third unit protection circuit portion 90U are longitudinally shaped in a plane in the Y-axis direction intersecting with each of the wirings 527, 528, 538 to 540. And the unit switch circuit portion 519U and the third unit protection circuit portion 90U are arranged side by side along each of the above-described wirings 527, 528, 538 to 540. Specifically, the third unit protection circuit portion 90U is arranged in a form sandwiched between two unit switch circuit portions 519U arranged at intervals in the X-axis direction. In the present embodiment, two third unit protection circuit portions 90U arranged at intervals in the X-axis direction are arranged to be sandwiched between two unit switch circuit portions 519U. Note that the unit switch circuit portion 519U is connected to each of the source wiring 522, the source main wiring 544, the low-potential power supply wiring 527, the high-potential power supply wiring 528, etc. and constitutes the switch circuit 519, while the third unit protection circuit portion 90U is connected to the low-potential power supply wiring 527, the high-potential power supply wiring 528, etc., but is not connected to the source wiring 522 and the source main wiring 544 and constitutes the third protection circuit 90. Therefore, it can be said that the unit switch circuit portion 519U and the third unit protection circuit portion 90U are functionally different circuit portions.

[0148] As described above, in the non-display area NAA, as shown in FIG. 29, the third unit protection circuit section 90U is arranged side by side along the low-potential power supply wiring 527 and the high-potential power supply wiring 528 with respect to the unit switch circuit section 519U which is a different circuit section. Therefore, if the third unit protection circuit section is arranged side by side along the direction intersecting the low-potential power supply wiring 527 and the high-potential power supply wiring 528 with respect to the unit switch circuit section 519U, the arrangement space in the direction intersecting the low-potential power supply wiring 527 and the high-potential power supply wiring 528 can be reduced as compared with the case where the third unit protection circuit section is arranged side by side along the direction intersecting the low-potential power supply wiring 527 and the high-potential power supply wiring 528. As a result, the arrangement efficiency of the unit switch circuit section 519U and the third unit protection circuit section 90U in the non-display area NAA is improved, and the narrow border of the array substrate 512 can be achieved. As described above, since the third unit protection circuit section 90U can be arranged side by side with respect to the unit switch circuit section 519U constituting the switch circuit 519, the third unit protection circuit section 90U can be provided without increasing the arrangement space of the switch circuit 519. Further, the red switch wiring 538 is a common wiring for the switch circuit 519 and the third protection circuit section 90. When the third protection circuit section 90 is arranged side by side along the direction intersecting the red switch wiring 538 with respect to the switch circuit 519, it is necessary to arrange the red switch wiring 538 for the third protection circuit section 90 and the switch circuit 519 respectively. However, in the present embodiment, since this wiring is shared, it is more advantageous for reducing the border.

[0149] As shown in FIG. 29, each of the switch TFTs 541 to 543 constituting the unit switch circuit section 519U is arranged to be sandwiched between the red switch wiring 538, which is the most distant from the driver 516 among the wirings 527, 528, 538 to 540, and the display area AA. Each of the protection TFTs 91 and 92 constituting the third unit protection circuit section 90U is arranged to be sandwiched between the red switch wiring 538, which is the most distant from the driver 516 among the wirings 527, 528, 538 to 540, and the display area AA. Therefore, each of the switch TFTs 541 to 543 constituting the unit switch circuit section 519U and each of the protection TFTs 81 and 82 constituting the third unit protection circuit section 90U are arranged side by side along the low-potential power supply wiring 527 and the high-potential power supply wiring 528, and are arranged at substantially the same distance from the display area AA.

[0150] As shown in FIG. 29, the source electrode of the first protection TFT 91 and the source electrode of the second protection TFT 92 are shared and connected to a connection terminal 93 made of a first metal film. The connection terminal 93 extends outward from each source electrode of the protection TFTs 91 and 92 and is connected to any one of the switch wirings 538 to 540. Further, the connection terminal 93 is directly connected to a connection wiring 94 made of the same first metal film. The gate electrode and the drain electrode of the first protection TFT 91 are connected to each other and are connected to a power supply voltage terminal VSS made of a first metal film. The power supply voltage terminal VSS made of a first metal film extends from the gate electrode and the drain electrode of the first protection TFT 91 toward the driver 516 side, crosses the wirings 528, 538 to 540, and is connected to the low-potential power supply wiring 527. The gate electrode and the source electrode of the second protection TFT 92 are connected to each other and are connected to a power supply voltage terminal VDD made of a first metal film. The power supply voltage terminal VDD extends outward from the gate electrode and the source electrode of the second protection TFT 92 and crosses the switch wirings 538 to 540 and is connected to the high-potential power supply wiring 528.

[0151] As described above, according to the present embodiment, in the display region AA, there are provided a gate wiring (sixth wiring) 521 that intersects a source wiring (first wiring) 522, a pixel TFT 523 connected to the source wiring 522 and the gate wiring 521, and a pixel electrode 524 connected to the pixel TFT 523. In the non-display region NAA, there are provided a driver (first signal supply unit) 516 connected to the source wiring 522 to supply an image signal to the source wiring 522, and a gate drive circuit (second signal supply unit) 518 connected to the gate wiring 521 to supply a scan signal to the gate wiring 521. A plurality of source wirings 522 are arranged side by side, and the second wiring is arranged to intersect the plurality of source wirings 522. The first circuit unit is connected to the plurality of source wirings 522, is interposed between the driver 516 and the plurality of source wirings 522, and constitutes a switch circuit 519 that distributes the image signal supplied from the driver 516 to the plurality of source wirings 522. When the pixel TFT 523 is driven as the scan signal is supplied from the gate drive circuit 518 to the gate wiring 521, the pixel electrode 524 connected to the pixel TFT 523 is charged to a potential based on the image signal supplied from the driver 516 to the source wiring 522 via the switch circuit 519. Since the third unit protection circuit unit 90U, which is the second circuit unit, can be arranged so as to be aligned with the unit switch circuit unit 519U, which is the first circuit unit constituting the switch circuit 519, the third unit protection circuit unit 90U, which is the second circuit unit, can be provided together without increasing the layout space of the switch circuit 519.

[0152] In addition, in the non-display area NAA, power supply voltage wirings (power supply wirings) 527 and 528 extending along the second wiring are provided. The second wiring is switch wirings 538 to 540 that are connected to the unit switch circuit 519U which is the first circuit section and supply a switch signal for switching a source wiring 522 that supplies an image signal. The second circuit section is connected to the switch wirings 538 to 540 and the power supply voltage wirings 527 and 528 respectively, and constitutes a third protection circuit 90 that protects the switch circuit 519 from electrostatic discharge. Even when electrostatic discharge occurs, a surge can be discharged to the power supply wiring by a third unit protection circuit section 90U which is the second circuit section constituting the third protection circuit 90. Thereby, the switch wirings 538 to 540 which are the second wiring connected to the third unit protection circuit section 90U which is the second circuit section, and the unit switch circuit 519U which is the first circuit section connected to the switch wirings 538 to 540 can be protected from electrostatic discharge.

[0153] <Embodiment 7> Embodiment 7 will be described with reference to FIG. 30. In this Embodiment 7, a case where the planar shape etc. of the display area AA in the above-described Embodiment 1 is changed is shown. Note that redundant descriptions of the same structures, operations, and effects as those in the above-described Embodiment 1 are omitted.

[0154] As shown in FIG. 30, the display area AA of the liquid crystal panel 610 according to the present embodiment has a substantially regular octagonal planar shape. The display area AA has a linear display area AAL having a linear outer shape along the X-axis direction or the Y-axis direction, and an inclined display area AAS that is inclined in a plane with respect to both the X-axis direction and the Y-axis direction. The planar shape of the display area AA is a shape following the outer shape viewed in the plane of the liquid crystal panel 610. In FIG. 30, the unit gate circuit section 618U constituting the gate drive circuit 618 and the first unit protection circuit section 620U constituting the first protection circuit 620 are illustrated in a simplified manner, and a low-potential power supply wiring 627 is illustrated as the second wiring. The specific configurations of the unit gate circuit section 618U and the first unit protection circuit section 620U are as described in Embodiment 1 (see FIG. 6).

[0155] The low-potential power supply wiring 627, which is the second wiring, has a linear portion 627L that forms a straight line along the Y-axis direction (the first direction) and an inclined linear portion 627S that is inclined in a plane with respect to both the Y-axis direction and the X-axis direction, as shown in FIG. 30. The inclined linear portion 627S is substantially parallel to the inclined display region AAS. The unit gate circuit portion 618U and the first unit protection circuit portion 620U are arranged side by side along the above-described inclined linear portion 627S. Specifically, the unit gate circuit portion 618U and the first unit protection circuit portion 620U are arranged in an alternating array, one by one, along the inclined linear portion 627S in the overlapping portion of the first protection circuit 620 and the gate drive circuit 618. Two unit gate circuit portions 618U are arranged side by side with an interval in the direction along the inclined linear portion 627S, and one first unit protection circuit portion 620U is sandwiched between these two unit gate circuit portions 618U. Conversely, two first unit protection circuit portions 620U are arranged side by side with an interval in the direction along the inclined linear portion 627S, and one unit gate circuit portion 618U is sandwiched between these two first unit protection circuit portions 620U.

[0156] As described above, in the present embodiment, as shown in FIG. 30, the first unit protection circuit section 620U is arranged side by side along the inclined linear section 627S with respect to the unit gate circuit section 618U and is disposed between two unit gate circuit sections 618U. The interval between two unit gate circuit sections 618U in the direction along the inclined linear section 627S is wider than the interval between two unit gate circuit sections 618U in the Y-axis direction (first direction). Therefore, it is possible to sufficiently secure the arrangement space for the first unit protection circuit section 620U disposed between two unit gate circuit sections 618U. As described above, since the first unit protection circuit section 620U can be arranged side by side with respect to the unit gate circuit section 618U constituting the gate drive circuit 618, the first unit protection circuit section 620U can be provided side by side without increasing the arrangement space of the gate drive circuit 618. Further, the gate drive circuit 618 and the first unit protection circuit section 620U share the low-potential wiring 627. When the first unit protection circuit section 620U is arranged side by side along the direction intersecting the low-potential wiring 627 with respect to the unit gate circuit section 618U, it is necessary to arrange the low-potential wiring 627 for the unit gate circuit section 618U and the first unit protection circuit section 620U, respectively. However, in the present embodiment, since this wiring is shared, it is advantageous for making the frame narrower.

[0157] As described above, according to the present embodiment, the low-potential power supply wiring 627, which is the second wiring, has a linear portion 627L that is linear along the first direction and an inclined linear portion 627S that is inclined with respect to the first direction. The gate wiring 21 has at least two arranged side by side with a space therebetween in the first direction. The unit gate circuit portions 618U are arranged with at least two spaced apart along the inclined linear portion 627S. The first unit protection circuit portion 620U is arranged side by side with the unit gate circuit portions 618U along the inclined linear portion 627S and is positioned between two unit gate circuit portions 618U. The space between two unit gate circuit portions 618U in the direction along the inclined linear portion 627S is wider than the space between two unit gate circuit portions 618U in the first direction. Therefore, it is possible to sufficiently secure the arrangement space for the first unit protection circuit portion 620U positioned between two unit gate circuit portions 618U.

[0158] <Other Embodiments> The technology disclosed in this specification is not limited to the embodiments described above and by the above description and drawings. For example, the following embodiments are also included in the technical scope.

[0159] (1) In the configuration described in Embodiment 1, an arrangement in which a plurality of unit gate circuit portions 18U and a plurality of first unit protection circuit portions 20U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit portions 18U and one first unit protection circuit portion 20U are arranged alternately may be used, or an arrangement in which one unit gate circuit portion 18U and a plurality of first unit protection circuit portions 20U are arranged alternately may be used.

[0160] (2) In the configuration described in Embodiment 2, an arrangement in which a plurality of unit gate circuit portions 118U and a plurality of unit charge extraction circuit portions 50U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit portions 118U and one unit charge extraction circuit portion 50U are arranged alternately may be used, or an arrangement in which one unit gate circuit portion 118U and a plurality of unit charge extraction circuit portions 50U are arranged alternately may be used.

[0161] (3) In the configuration described in Embodiment 3, an arrangement in which a plurality of unit gate circuit sections 218U and a plurality of unit common potential supply circuit sections 60U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit sections 218U and one unit common potential supply circuit section 60U are arranged alternately may be used, or an arrangement in which one unit gate circuit section 218U and a plurality of unit common potential supply circuit sections 60U are arranged alternately may be used.

[0162] (4) In the configuration described in Embodiment 4, an arrangement in which a plurality of unit gate circuit sections 318U, a plurality of unit charge extraction circuit sections 350U, and a plurality of unit common potential supply circuit sections 360U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit sections 318U, one unit charge extraction circuit section 350U, and one unit common potential supply circuit section 360U are arranged alternately may be used. Also, an arrangement in which a plurality of unit gate circuit sections 318U, a plurality of unit charge extraction circuit sections 350U, and one unit common potential supply circuit section 360U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit sections 318U, one unit charge extraction circuit section 350U, and a plurality of unit common potential supply circuit sections 360U are arranged alternately may be used. Also, an arrangement in which one unit gate circuit section 318U, a plurality of unit charge extraction circuit sections 350U, and one unit common potential supply circuit section 360U are arranged alternately may be used, or an arrangement in which one unit gate circuit section 318U, one unit charge extraction circuit section 350U, and a plurality of unit common potential supply circuit sections 360U are arranged alternately may be used.

[0163] (5) In the configuration described in Embodiment 5, an arrangement in which a plurality of unit gate circuit sections 418U and a plurality of second unit protection circuit sections 80U are arranged alternately may be used, or an arrangement in which a plurality of unit gate circuit sections 418U and one second unit protection circuit section 80U are arranged alternately may be used, or an arrangement in which one unit gate circuit section 418U and a plurality of second unit protection circuit sections 80U are arranged alternately may be used.

[0164] (6) In the configuration described in Embodiment 6, an arrangement in which a plurality of unit switch circuit portions 519U and one third unit protection circuit portion 90U are alternately arranged may be used, or an arrangement in which one unit switch circuit portion 519U and one third unit protection circuit portion 90U are alternately arranged may be used, or an arrangement in which one unit switch circuit portion 519U and a plurality of third unit protection circuit portions 90U are alternately arranged may be used.

[0165] (7) The number and arrangement of each wiring provided in the non-display area NAA of the array substrates 12, 112, 212, 312, 412, 512 can be appropriately changed other than as shown in the drawings.

[0166] (8) The material of the semiconductor film constituting the semiconductor portions of each of the TFTs 23, 41 to 43, 45, 46, 57, 65, 76B, 76G, 76R, 81, 82, 91, 92, 123, 223, 423, 523, 541 to 543, and each of the transistors NT1 to NT7, NT201 to NT207, NT406, NT407, PT1 to PT6, PT201 to PT206, PT406 may be an oxide semiconductor material, amorphous silicon, or the like.

[0167] (9) The configuration of each of the TFTs 23, 41 to 43, 45, 46, 57, 65, 76B, 76G, 76R, 81, 82, 91, 92, 123, 223, 423, 523, 541 to 543, and each of the transistors NT1 to NT7, NT201 to NT207, NT406, NT407, PT1 to PT6, PT201 to PT206, PT406 may be a bottom gate type, a double gate type, or the like, other than a top gate type.

[0168] (10) The specific circuit configuration of the unit gate circuit portions 18U, 118U, 218U, 318U, 418U, 518U, 618U constituting the gate drive circuits 18, 118, 218, 318, 418, 518, 618 can be appropriately changed other than as shown in the drawings.

[0169] (11) The drivers 16, 116, 216, 316, 416 may be implemented as COF (Chip On Film) on the flexible substrates 17, 117, 217, 417 which are FOG (Film On Glass) mounted on the array substrates 12, 112, 212, 312, 412, 512.

[0170] (12) The gate drive circuits 18, 118, 218, 318, 418, 518, 618 may be arranged on only one side in the X-axis direction with respect to the display area AA.

[0171] (13) The planar shape of the liquid crystal panels 10, 110, 210, 310, 410, 510, 610 may be a horizontally long rectangle, a square, a circle, a semi-circle, an oval, an ellipse, a trapezoid, etc.

[0172] (14) The number and arrangement of the unit switch circuit parts 19U, 519U can be appropriately changed other than as shown in the figure.

[0173] (15) The configurations of the unit switch circuits 19U, 519U, the first protection unit circuit 20U, the second protection unit circuit 80U, the third protection unit circuit 90U, the unit charge extraction circuit part 350U, the unit common potential supply circuit part 360U, and the inspection circuit 70 can be appropriately changed to NMOS (n-channel Metal-Oxide-Semiconductor), PMOS (p-channel Metal-Oxide-Semiconductor), CMOS (Complementary Metal Oxide Semiconductor), etc.

[0174] (16) In the configuration described in Embodiment 7, the planar shape of the display area AA may be an equilateral triangle, a non-equilateral triangle, a regular pentagon, a non-regular pentagon, a regular hexagon, a non-regular hexagon, a regular heptagon, a non-regular heptagon, a non-regular octagon, etc.

[0175] (17) The configuration described in Embodiment 7 may be combined with any of the configurations of Embodiments 2 to 6.

Description of Reference Numerals

[0176] 10, 110, 210, 310, 410, 510, 610… Liquid crystal panel (display device), 11… Opposite substrate, 12, 112, 212, 312, 412, 512… Array substrate (display substrate), 16, 116, 216, 316, 416… Driver (signal supply unit), 18, 118, 218, 318, 418, 618… Gate drive circuit (shift register circuit), 18U, 118U, 218U, 318U, 418U, 518U, 618U… Unit gate circuit section (first circuit section), 20, 620… First protection circuit, 20U, 620U… First unit protection circuit section (second circuit section), 21, 121, 221, 421… Gate wiring (first wiring), 22, 122, 422… Source wiring (fifth wiring), 23, 123, 223, 423, 523… Pixel TFT (switching element), 24, 124, 424, 524… Pixel electrode, 27, 127, 227, 327, 427, 527, 627… Low potential power supply wiring (second wiring, third wiring, low potential wiring), 27L, 627L… Linear part, 27R… Curved part, 28, 128, 228, 328, 428, 528… High potential power supply wiring (second wiring, fourth wiring), 28L… Linear part, 28R… Curved part, 50, 350… Charge extraction circuit, 50U, 350U… Unit charge extraction circuit section (second circuit section), 53, 353… First off-sequence drive wiring (second wiring, first drive wiring), 56, 356… Charge extraction wiring, 58… Source input terminal (second input part), 59… Charge output terminal (second output part), 60, 360… Common potential supply circuit, 60U, 360U… Unit common potential supply circuit section (second circuit section), 61, 361… Touch electrode (position detection electrode), 62, 362… Touch wiring (position detection wiring), 63, 363… Common wiring, 64, 364… Common potential circuit drive wiring (second wiring, second drive wiring), 65, 365… Commonization TFT (P-channel transistor), 65G… Second gate electrode, 65S… Second source electrode, 65D… Second drain electrode, 66… Common potential input terminal (third input part), 67… Common potential output terminal (third output part), 70… Inspection circuit, 75R, 75G,75B…Inspection drive wiring (inspection wiring), 80…Second protection circuit, 80U…Second unit protection circuit section (second circuit section), 90…Third protection circuit, 90U…Third unit protection circuit section (second circuit section), 516…Driver (first signal supply section), 518…Gate drive circuit (second signal supply section), 519…Switch circuit, 519U…Unit switch circuit section (first circuit section), 521…Gate wiring (sixth wiring), 522…Source wiring (first wiring), 538 - 540…Switch wiring (second wiring), 627S…Slanted linear section, AA…Display area, NAA…Non - display area, GL…Gate output terminal (first output section), NT8…Eighth negative - type transistor (N - channel transistor), NT8G…First gate electrode, NT8S…First source electrode, NT8D…First drain electrode, VSS…Power supply voltage terminal (first input section), VDD…Power supply voltage terminal (first input section),

Claims

1. a first wiring arranged in a display area where an image is displayed; a second wiring arranged in a non-display area where the image is not displayed; a first circuit unit arranged in the non-display area, having a first output unit connected to the first wiring and a first input unit connected to the second wiring; a second circuit unit arranged in the non-display area, connected to the second wiring but not connected to the first wiring; The second circuit unit is a display substrate arranged side by side along the second wiring with respect to the first circuit unit in the non-display area.

2. The second wiring has a linear portion that is linear along a first direction and a curved portion that is curved so as to intersect the first direction. At least two of the first wirings are arranged side by side with a space therebetween in the first direction. At least two of the first circuit units are arranged side by side with a space therebetween along the curved portion. The second circuit unit is arranged side by side along the curved portion with respect to the first circuit unit and is positioned between two of the first circuit units. The display substrate according to Claim 1.

3. The second wiring has a linear portion that is linear along a first direction and an inclined linear portion that is inclined with respect to the first direction. At least two of the first wirings are arranged side by side with a space therebetween in the first direction. At least two of the first circuit units are arranged side by side with a space therebetween along the inclined linear portion. The second circuit unit is arranged side by side along the inclined linear portion with respect to the first circuit unit and is positioned between two of the first circuit units. The display substrate according to Claim 1.

4. The first circuit unit is longitudinally shaped in a direction intersecting the second wiring. In the non-display area, a third wiring extending in parallel with the second wiring and located on one end side in the longitudinal direction of the first circuit unit, and a fourth wiring extending in parallel with the second wiring and located on the other end side in the longitudinal direction of the first circuit unit are provided. The second circuit unit is arranged within a range sandwiched between the third wiring and the fourth wiring. The display substrate according to any one of Claims 1 to 3.

5. The first circuit unit is longitudinally shaped in a direction intersecting the second wiring. The second circuit portion has a longitudinal shape parallel to the longitudinal direction of the first circuit portion and is arranged within the range in the longitudinal direction in the first circuit portion. The display substrate according to any one of claims 1 to 3.

6. In the display area, a fifth wiring extending along a first direction intersecting the first wiring, a switching element connected to the first wiring and the fifth wiring, and a pixel electrode connected to the switching element are provided. In the non-display area, a signal supply unit connected to the fifth wiring and supplying an image signal to the fifth wiring is provided. The first wiring and the first circuit portion are arranged side by side in plural along the first direction. The plurality of first circuit portions constitute a shift register circuit that sequentially supplies scanning signals to the plurality of first wirings. The display substrate according to any one of claims 1 to 3.

7. The second wiring is a power supply wiring. The second circuit portion is connected to the fifth wiring and constitutes a first protection circuit that protects the fifth wiring and the switching element from electrostatic discharge. The display substrate according to claim 6.

8. In the non-display area, an inspection circuit located on the side opposite to the signal supply unit side with respect to the fifth wiring and connected to the fifth wiring, and an inspection wiring extending along the second wiring and connected to the inspection circuit are provided. The second wiring is a power supply wiring. The second circuit portion is connected to the inspection wiring and constitutes a second protection circuit that protects the inspection wiring and the inspection circuit from electrostatic discharge. The display substrate according to claim 6.

9. In the non-display area, a charge removal wiring extending along the second wiring and having a common potential or a ground potential is provided. The second wiring is a first drive wiring connected to the signal supply unit and supplied with a first drive signal from the signal supply unit as a power-off sequence is executed. The second circuit portion has a second input portion connected to the fifth wiring and a second output portion connected to the charge removal wiring. As the first drive signal is supplied from the first drive wiring, a charge removal circuit that moves the charge of the pixel electrode to the charge removal wiring via the fifth wiring is constituted. The display substrate according to claim 6.

10. In the display area, a position detection electrode and a position detection wiring are provided. The position detection wiring is connected to the position detection electrode and the signal supply unit, and a position detection signal is supplied from the signal supply unit during a position detection period in which position detection is performed by the position detection electrode. In the non-display area, a common wiring that extends along the second wiring and has a common potential is provided. The second wiring is a second drive wiring that is connected to the signal supply unit and to which a second drive signal is supplied from the signal supply unit during a display period in which an image is displayed. The second circuit unit includes a third output unit connected to the position detection wiring and a third input unit connected to the common wiring. As the second drive signal is supplied from the second drive wiring, a common potential supply circuit that supplies a common potential to the position detection electrode via the position detection wiring is configured. The display substrate according to claim 6.

11. In the non-display area, a low-potential wiring that is connected to the signal supply unit and to which a low-potential signal is supplied from the signal supply unit is provided. The first circuit unit includes an N-channel type transistor. The common potential supply circuit includes a P-channel type transistor. The N-channel type transistor has a first gate electrode connected to the second wiring, a first source electrode connected to the low-potential wiring, and a first drain electrode connected to the first wiring. The P-channel type transistor has a second gate electrode connected to the second wiring, a second source electrode connected to the common wiring, and a second drain electrode connected to the position detection wiring. The display substrate according to claim 10.

12. In the display area, a sixth wiring that intersects the first wiring, a switching element connected to the first wiring and the sixth wiring, and a pixel electrode connected to the switching element are provided. In the non-display area, a first signal supply unit that is connected to the first wiring and supplies an image signal to the first wiring, and a second signal supply unit that is connected to the sixth wiring and supplies a scanning signal to the sixth wiring are provided. A plurality of the first wirings are arranged side by side, and the second wiring is arranged to intersect the plurality of the first wirings. The first circuit unit is connected to the plurality of first wirings, is interposed between the first signal supply unit and the plurality of first wirings, and distributes the image signal supplied from the first signal supply unit to the plurality of first wirings. The display substrate according to any one of claims 1 to 3, which constitutes a switch circuit.

13. A power supply wiring extending along the second wiring is provided in the non-display area. The second wiring is a switch wiring that is connected to the first circuit unit and supplies a switch signal for switching the first wiring that supplies the image signal. The second circuit unit is connected to the switch wiring and the power supply wiring respectively, and constitutes a third protection circuit that protects the switch circuit from electrostatic discharge. The display substrate according to claim 12.

14. A display device comprising the display substrate according to any one of claims 1 to 3, and a counter substrate arranged to face the display substrate.

Images