Residual and coefficient coding for video coding

Abstract

To provide a method, an apparatus, and a non-transitory computer-readable storage medium for improving and simplifying residual and coefficient coding in video coding.SOLUTION: A method includes signaling parameters for determining a coding bit depth value, signaling a first sequence parameter set (SPS) flag that is a transform skip enable flag, and setting a second SPS flag on the basis of the value of the first SPS flag and the coding bit depth value.SELECTED DRAWING: Figure 22

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority to Provisional Application No. 63 / 220,380, filed on July 9, 2021, and the entire content of the provisional application is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to video encoding and compression. More particularly, the present disclosure relates to improving and simplifying the encoding of residuals and coefficients for video encoding.

Background Art

[0003] To compress video data, various video encoding techniques may be used. Video encoding is performed according to one or more video encoding standards. For example, video encoding standards include Versatile Video Coding (VVC), Joint Exploration Test Model (JEM), High - Efficiency Video Coding (H.265 / HEVC), Advanced Video Coding (H.264 / AVC), Moving Picture Expert Group (MPEG) coding, or the like. Video encoding generally utilizes prediction methods (e.g., inter - prediction, intra - prediction, or the like) that exploit redundancy present in the moving image or sequence. An important goal of video encoding techniques is to compress video data into a form that uses a lower bit - rate while avoiding or minimizing degradation of video quality.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Examples of the present disclosure provide methods and apparatuses for video encoding.

Means for Solving the Problem

[0005] According to the present disclosure, a method for video decoding is provided. The method may include: determining, by a decoder, an encoded bit depth of at least one sample in a bitstream; determining, by the decoder, a value of a first SPS flag for the at least one sample; and determining, by the decoder, a second SPS flag for the at least one sample based on the value of the first SPS flag by combining the encoded bit depth of the at least one sample.

[0006] It should be understood that the above summary and the following detailed description are merely exemplary and explanatory and are not intended to limit the present disclosure.

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate examples in accordance with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Next, exemplary embodiments will be referred to in detail. Examples of those embodiments are shown in the accompanying drawings. The following description refers to the accompanying drawings, and unless otherwise specified, the same numbers in different drawings represent the same or similar elements. The implementation forms described in the following description of the exemplary embodiments do not represent all implementation forms in accordance with the present disclosure. Rather, those implementation forms are merely examples of devices and methods in accordance with aspects related to the present disclosure described in the appended claims.

[0010] The terms used in the present disclosure are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. The singular forms "a", "an", and "the" are intended to include the plural forms as well when used in the present disclosure and the appended claims, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used herein is intended to mean and include any and all possible combinations of one or more of the associated listed items.

[0011] In this specification, terms such as "first", "second", "third", etc. may be used to describe various information, but it should be understood that the information should not be limited by these terms. These terms are only used to distinguish one category of information from another. For example, without departing from the scope of the present disclosure, the first information may be referred to as the second information, and similarly, the second information may be referred to as the first information. The term "case" when used in this specification can be understood to mean "sometimes", "when", or "depending on the judgment" depending on the context.

[0012] FIG. 1 shows a schematic diagram of a block-based video encoder for VVC. Specifically, FIG. 1 shows a typical encoder 100. The encoder 100 has a video input 110, motion compensation 112, motion estimation 114, intra / inter mode decision 116, block predictor 140, adder 128, transform 130, quantization 132, prediction-related information 142, intra prediction 118, picture buffer 120, inverse quantization 134, inverse transform 136, adder 126, memory 124, in-loop filter 122, entropy coding 138, and bitstream 144.

[0013] In the encoder 100, a video frame is divided into a plurality of video blocks for processing. For each given video block, a prediction is formed based on either an inter prediction method or an intra prediction method.

[0014] The prediction residual, which represents the difference between the current video block that is part of the video input 110 and its predictor that is part of the block predictor 140, is sent from the adder 128 to the transform 130. Next, for entropy reduction, the transform coefficients are sent from the transform 130 to the quantization 132. Then, the quantized coefficients are supplied to the entropy coding 138 to generate a compressed video bitstream. As shown in FIG. 1, prediction-related information 142 from the intra / inter mode decision 116, such as video block partition information, motion vector (MV), reference picture index, and intra prediction mode, is also supplied through the entropy coding 138 and stored in the compressed bitstream 144. The compressed bitstream 144 includes the video bitstream.

[0015] In the encoder 100, decoder-related circuitry is also required to reconstruct pixels for prediction purposes. First, the prediction residual is reconstructed through the inverse quantization 134 and the inverse transform 136. This reconstructed prediction residual is combined with the block predictor 140 to generate the unfiltered reconstructed pixels of the current video block.

[0016] Spatial prediction (or "intra prediction") predicts the current video block using pixels from samples (referred to as reference samples) of already encoded adjacent blocks within the same video frame as the current video block.

[0017] Temporal prediction (also called "inter prediction") predicts the current video block using the reconstructed pixels from previously encoded video pictures. Temporal prediction reduces the temporal redundancy inherent in the video signal. The temporal prediction signal for a given coding unit (CU) or coding block is typically signaled by one or more motion vectors (MVs) indicating the amount and direction of motion between the current CU and its temporal reference. Additionally, one reference picture index is sent additionally to identify from which reference picture in the reference picture storage the temporal prediction signal is coming.

[0018] Motion estimation 114 fetches signals from video input 110 and picture buffer 120 and outputs a motion estimation signal to motion compensation 112. Motion compensation 112 fetches signals from video input 110, picture buffer 120, and the motion estimation signal from motion estimation 114 and outputs a motion compensation signal to intra / inter mode decision 116.

[0019] After spatial prediction and / or temporal prediction is performed, the intra / inter mode decision 116 within the encoder 100 selects the best prediction mode, for example, based on a rate distortion optimization method. Next, the block predictor 140 is subtracted from the current video block, and the resulting prediction residual is decorrelated using the transform 130 and quantization 132. The resulting quantized residual coefficients are inverse quantized by the inverse quantization 134 and inverse transformed by the inverse transform 136 to form a reconstructed residual, which is then added back to the prediction block to form the reconstructed signal of the CU. Before the reconstructed CU is placed in the reference picture storage of the picture buffer 120 and used to encode future video blocks, further in-loop filtering 122, such as a block deblocking filter, sample adaptive offset (SAO), and / or adaptive loop filter (ALF), may be applied to the reconstructed CU. To form the output video bitstream 144, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit 138, where they are further compressed and packed to form the bitstream.

[0020] Figure 1 shows a block diagram of a general block-based hybrid video coding system. The input video signal is processed block by block (referred to as a coding unit (CU)). In VTM-1.0, a CU may be up to 128×128 pixels. However, unlike HEVC which partitions blocks based only on quad-trees, in VVC, one coding tree unit (CTU) is decomposed into CUs to adapt to various local characteristics based on quad-trees / binary-trees / trinary-trees. By definition, a coding tree block (CTB) is a sample of an N×N block with a certain value N, and as a result, the division of components into CTBs is a partition. A CTU includes a CTB of luminance samples, two corresponding CTBs of chrominance samples of a picture having three sample arrays, or a CTB of samples of a picture encoded using a syntax structure used to encode a monochrome picture or three separate color planes and samples. Furthermore, the concept of multiple partition unit types in HEVC is excluded, that is, in VVC, the separation of CUs, prediction units (PUs), and transform units (TUs) no longer exists, and instead, each CU is always used as a basic unit for both prediction and transform without further partitioning. In a polymorphic tree structure, first, one CTU is partitioned by a quad-tree structure. Then, each quad-tree leaf node can be further partitioned by binary-tree and trinary-tree structures. As shown in FIGS. 3A, 3B, 3C, 3D, and 3E, there are five decomposition types: quad-partitioning, vertical binary-partitioning, horizontal binary-partitioning, horizontal trinary-partitioning, and vertical trinary-partitioning.

[0021] FIG. 3A shows a diagram illustrating block quad-partitioning in a polymorphic tree structure according to the present disclosure.

[0022] FIG. 3B shows a diagram illustrating block vertical binary-partitioning in a polymorphic tree structure according to the present disclosure.

[0023] FIG. 3C shows a diagram illustrating block horizontal binary-partitioning in a polymorphic tree structure according to the present disclosure.

[0024] FIG. 3D shows a diagram illustrating a block vertical three-way division in a polymorphic tree structure according to the present disclosure.

[0025] FIG. 3E shows a diagram illustrating a block horizontal three-way division in a polymorphic tree structure according to the present disclosure.

[0026] In FIG. 1, spatial prediction and / or temporal prediction may be performed. Spatial prediction (or "intra prediction") predicts the current video block using samples (referred to as reference samples) from already encoded adjacent blocks within the same video picture / slice. Spatial prediction reduces the spatial redundancy inherent in the video signal. Temporal prediction (also called "inter prediction" or "motion compensated prediction") predicts the current video block using reconstructed pixels from already encoded video pictures. Temporal prediction reduces the temporal redundancy inherent in the video signal. The temporal prediction signal for a given CU is typically signaled by one or more motion vectors (MVs) indicating the amount and direction of motion between the current CU and its temporal reference. Also, when multiple reference pictures are supported, an additional reference picture index is sent to identify from which reference picture in the reference picture store the temporal prediction signal is coming. After spatial prediction and / or temporal prediction, the mode decision block in the encoder selects the best prediction mode, for example, based on a rate distortion optimization method. Then, the prediction block is subtracted from the current video block, and the prediction residual is decorrelated and quantized using a transform. The quantized residual coefficients are inverse quantized and inverse transformed to form a reconstructed residual, and then the reconstructed residual is added back to the prediction block to form the reconstructed signal of the CU. Before the reconstructed CU is put into the reference picture store and used to encode future video blocks, further in-loop filtering such as block deblocking filter, sample adaptive offset (SAO), and adaptive loop filter (ALF) may be applied to the reconstructed CU. To form the output video bitstream, the encoding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit and further compressed and packed to form the bitstream.

[0027] Figure 2 shows a schematic block diagram of a video decoder for VVC. Specifically, Figure 2 shows a block diagram of a typical decoder 200. The decoder 200 includes a bitstream 210, entropy decoding 212, inverse quantization 214, inverse transform 216, adder 218, intra / inter mode selection 220, intra prediction 222, memory 230, in-loop filter 228, motion compensation 224, picture buffer 226, prediction-related information 234, and video output 232.

[0028] The decoder 200 is similar to the reconstruction-related section existing in the encoder 100 of Figure 1. In the decoder 200, first, the incoming input video bitstream 210 is decoded through entropy decoding 212 to derive the quantized coefficient levels and prediction-related information. Then, the quantized coefficient levels are processed through inverse quantization 214 and inverse transform 216 to obtain the reconstructed prediction residuals. The block predictor mechanism implemented in the intra / inter mode selector 220 is configured to execute either intra prediction 222 or motion compensation 224 based on the decoded prediction information. By summing the reconstructed prediction residuals from the inverse transform 216 and the prediction output generated by the block predictor mechanism using the adder 218, a set of non-filtered reconstructed pixels is obtained.

[0029] The reconstructed blocks may further pass through the in-loop filter 228 before being stored in the picture buffer 226, which functions as a reference picture store. The reconstructed video in the picture buffer 226 is sent to drive a display device and may also be used to predict future video blocks. In situations where the in-loop filter 228 is on, a filtering operation is performed on these reconstructed pixels to derive the final reconstructed video output 232.

[0030] FIG. 2 shows a schematic block diagram of a block-based video decoder. First, in an entropy decoding unit, a video bitstream is entropy decoded. Encoding mode and prediction information are sent to a spatial prediction unit (in the case of intra encoding) or a temporal prediction unit (in the case of inter encoding) to form a prediction block. Residual transform coefficients are sent to an inverse quantization unit and an inverse transform unit to reconstruct a residual block. Then, the prediction block and the residual block are added. The reconstructed block may further pass through in-loop filtering before being stored in a reference picture store. Next, the reconstructed video in the reference picture store is sent to drive a display device and is used to predict future video blocks.

[0031] Transform Coefficient Encoding in VVC In the conversion coefficient coding in VVC, first, the variable remBinsPass1 is set to the maximum number of context-coded bins (MCCB). In the coding process, the variable decreases by 1 each time a context-coded bin is signaled. While remBinsPass1 is 4 or more, the coefficient is first signaled through the syntax of sig_coeff_flag, abs_level_gt1_flag, par_level_flag, and abs_level_gt3_flag, all of which use context-coded bins in the first pass. The remaining part of the coefficient level information is coded using Golomb-Rice codes and bypass-coded bins in the second pass with the syntax element of abs_remainder. When remBinsPass1 becomes less than 4 while coding the first pass, the current coefficient is not coded in the first pass and is directly coded in the second pass using Golomb-Rice codes and bypass-coded bins with the syntax element of dec_abs_level. The Rice parameter derivation process of dec_abs_level[] is derived as specified in Table 1A. After coding all levels described above, finally, the sign (sign_flag) at all scan positions where sig_coeff_flag is equal to 1 is coded as a bypass bin. Such a process is depicted in Figure 4. remBinsPass1 is reset for each TB. The transition from the use of context-coded bins of sig_coeff_flag, abs_level_gt1_flag, par_level_flag, and abs_level_gt3_flag to the use of bypass-coded bins for the remaining coefficients occurs only once per TB at most. For a coefficient sub-block, if remBinsPass1 is less than 4 before coding the first coefficient, the entire coefficient sub-block is coded using bypass-coded bins.

[0032] Figure 4 shows a diagram of the residual coding structure of the conversion block. [Table 1]

Table 2

[0033] Residual Encoding of the Transform Skip Mode in VVC In the transform skip mode, the statistical characteristics of the residual signal are different from those of the transform coefficients, and no energy compression around the low-frequency components is observed. The residual encoding is modified considering various signal characteristics of the (spatial) transform skip residual.

[0034] FIG. 5 shows a diagram of the residual encoding structure of the transform skip block.

[0035] General Constraint Information The GCI structure includes several types of constraint syntax elements, including flags regarding general bitstream limitations indicating that only intra coding is used, all layers are independently coded, or the bitstream contains only one AU, fields constraining the bit depth and chroma format of the coded picture, flags indicating that a specific NAL unit type cannot exist in the bitstream, flags constraining how pictures can be partitioned into slices, tiles, and subpictures in the bitstream, flags constraining the size of the CTU, as well as the size and type of the partitioning tree, flags restricting the use of specific intra coding tools, flags restricting the use of specific inter coding tools, flags constraining the transform, quantization, and residual coding tools, and flags constraining the mode of the in-loop filter.

[0036] The purpose of the GCI syntax structure is to enable easy discovery of configuration information related to functions required for decoding a bitstream, and to enable signaling of interoperability points that impose restrictions beyond those specified by profiles, tiers, and levels (PTL) at a finer granularity than permitted by previous video coding standards. Similar to subprofiles, using the GCI syntax structure may enable defining interoperability for decoder implementations that address the needs of specific applications without supporting all the functions of a VVC profile. The decoder implementation may examine GCI syntax elements to determine how to configure the decoding process and to identify whether the bitstream is decodable by the decoder by checking whether the bitstream avoids using specific functions. A decoder implementation that supports all the functions of a VVC profile may be able to ignore the values of GCI syntax elements, and thus the decoder will be able to decode any bitstream that conforms to the specified PTL.

[0037] Residual coding of transform skip According to one or more examples of the present disclosure, it is proposed to use a variable set of binary codewords for encoding a specific syntax element, such as abs_remainder, in transform skip residual coding, and the selection result is determined according to specific encoded information of the current block, such as quantization parameters or encoded bit depth associated with TB / CB and / or slice / profile, and / or according to a new flag associated with TB / CB / slice / picture / sequence level, such as extended_precision_processing_flag. Various methods may be used to derive the variable set of binary codewords, and some exemplary methods are listed below.

[0038] First, to determine the sign word of abs_remainder, the same procedure as that currently used in VVC is employed, but a fixed Rice parameter (e.g., 2, 3, 4, 5, 6, 7, or 8) is always selected. The fixed value may vary under different conditions according to specific encoded information of the current block, such as the quantization parameter associated with the TB / CB and / or slice / profile, frame type (e.g., I, P, or B), component ID (e.g., luminance or chrominance), color format (e.g., 420, 422, or 444), or encoded bit depth, and / or according to syntax elements associated with the TB / CB / slice / picture / sequence level, such as the rice_parameter_value. A specific example is the case where TH1 to TH4 are predetermined thresholds satisfying (TH1 < TH2 < TH3 < TH4), and K0 to K4 are predetermined Rice parameters. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter from the BitDepth value of the current CU / sequence.

[0039] Second, it is fixed-length binarization.

[0040] Third, it is truncated Rice binarization.

[0041] Fourth, it is a truncated binary (TB) binarization process.

[0042] Fifth, it is a k-th exponential Golomb binarization process (EGk).

[0043] Sixth, it is limited k-th exponential Golomb binarization.

[0044] An example of the corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are shown in bold italic font in Table 1, and the deleted content is shown in italic font. It is worth noting that in reality, the same logic can be implemented in different ways. For example, a specific equation or lookup table may also be used to derive the same Rice parameter. [Table 3]

[0045] In another example, it is proposed that when a new flag, for example, extended_precision_processing_flag, is equal to 1, only one fixed value is used for the Rice parameter when encoding the syntax element of abs_remainder. The corresponding decoding process based on the VVC draft is shown below, with the changes shown in bold italic font and the deleted content shown in italic font. The changes to the VVC draft are shown in bold italic font in Table 2. [Table 4]

[0046] In yet another example, when a new flag, for example, extended_precision_processing_flag, is equal to 1, the Rice parameter cRiceParam is fixed as n, where n is a positive number (for example, 2, 3, 4, 5, 6, 7, or 8). The fixed value may be different under different conditions. An example of the corresponding decoding process based on the VVC draft is shown below, with the changes shown in bold italic font and the deleted content shown in italic font. The changes to the VVC draft are shown in bold italic font in Table 3. [Table 5]

[0047] In yet another example, when the BitDepth is greater than or equal to a predetermined threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), the Rice parameter cRiceParam is fixed to n, where n is a positive number, e.g., 4, 5, 6, 7, or 8. The fixed value may be different under different conditions. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), the changes are shown in bold italic font, and the deleted content is shown in italic font. The changes to the VVC draft are shown in bold italic font in Table 4.

Table 6

[0048] In yet another example, one control flag is signaled within the slice header to indicate whether signaling of the Rice parameters for the conversion skip block is effective or not. When the control flag is signaled as effective, one more syntax element is further signaled for each conversion skip slice to indicate the Rice parameter of that slice. When the control flag is signaled as ineffective (e.g., when set to be equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameter of the conversion skip slice, and a default Rice parameter (e.g., 1) is used for all conversion skip slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2), the changes are shown in bold italic font, and the deleted content is shown in italic font. The changes to the VVC draft are shown in bold italic font in Table 5. It is worth noting that sh_ts_residual_coding_rice_index can be coded in various ways and / or can have a maximum value. For example, for encoding / decoding the same syntax element, u(n), an unsigned integer using n bits, or f(n), a fixed pattern bit sequence using n bits with the left bit described first (from left to right), may also be used.

[0049] Slice header syntax

Table 7

[0050] That sh_ts_residual_coding_rice_flag is equal to 1 specifies that sh_ts_residual_coding_rice_index may exist within the current slice. That sh_ts_residual_coding_rice_flag is equal to 0 specifies that sh_ts_residual_coding_rice_index does not exist within the current slice. When sh_ts_residual_coding_rice_flag does not exist, the value of sh_ts_residual_coding_rice_flag is inferred to be equal to 0. sh_ts_residual_coding_rice_index specifies the Rice parameter used in the residual_ts_coding() syntax structure.

Table 8

[0051] In yet another example, one control flag is signaled within the sequence parameter set (or within the sequence parameter set range extension syntax) to indicate whether signaling of the Rice parameters for the conversion skip block is effective or not. When the control flag is signaled as effective, one more syntax element is further signaled for each conversion skip slice to indicate the Rice parameter of that slice. When the control flag is signaled as ineffective (e.g., when set to be equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the conversion skip slices, and default Rice parameters (e.g., 1) are used for all conversion skip slices. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). The changes to the VVC draft are shown in bold italics in Table 7, and the deleted content is shown in italics. Note that sh_ts_residual_coding_rice_idx can be coded in various ways and / or can have a maximum value. For example, to encode / decode the same syntax element, a unsigned integer u(n) using n bits, or a fixed pattern bit sequence f(n) using n bits with the left bit described first (from left to right) may also be used.

[0052] Sequence parameter set RBSP syntax [Table 9]

[0053] That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 1 specifies that sh_ts_residual_coding_rice_idx may exist in the SH syntax structure referring to the SPS. That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 0 specifies that sh_ts_residual_coding_rice_idx does not exist in the SH syntax structure referring to the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag does not exist, it is inferred that the value of sps_ts_residual_coding_rice_present_in_sh_flag is equal to 0.

[0054] Slice header syntax [Table 10]

[0055] sh_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. [Table 11]

[0056] In one or more examples of the present disclosure, when the transform skip is disabled, it is proposed to disable the existence of the Rice parameter for transform skip residual coding. In a specific example, in order to achieve such a design objective, it is proposed to use the sps_transform_skip_enabled_flag to condition the existence of sps_ts_residual_coding_rice_present_in_sh_flag. For example, when the flag sps_transform_skip_enabled_flag is equal to 0 (i.e., when transform skip is disabled in the current picture), sps_ts_residual_coding_rice_present_in_sh_flag is not signaled but is inferred to be 0. When the flag sps_transform_skip_enabled_flag is equal to 1, sps_ts_residual_coding_rice_present_in_sh_flag is further signaled. The changes to the current VVC working draft are shown in the following italic font.

Table 12

[0057] In another specific example, in order to achieve such a design objective, it is proposed to add bitstream compliance requirements related to sps_transform_skip_enabled_flag for sps_ts_residual_coding_rice_present_in_sh_flag. For example, when sps_transform_skip_enabled_flag is equal to 0, it is a bitstream compliance requirement that the value of sps_ts_residual_coding_rice_present_in_sh_flag be equal to 0. The changes to the current VVC working draft are shown in the following italic font.

[0058] Semantics of Sequence Parameter Set Range Extension That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 1 specifies that there may be sh_ts_residual_coding_rice_idx_minus1 within the slice_header() syntax structure that refers to the SPS. That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 0 specifies that there is no sh_ts_residual_coding_rice_idx_minus1 within the slice_header() syntax structure that refers to the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag does not exist, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0059] When sps_transform_skip_enabled_flag is equal to 0, it is a requirement for bitstream compliance that the value of sps_ts_residual_coding_rice_present_in_sh_flag be equal to 0.

[0060] In yet another example, when the transform skip flag (sps_transform_skip_enabled_flag) is signaled as enabled, one control flag is further signaled in the sequence parameter set (or in the sequence parameter set range extension syntax) to indicate whether signaling of the Rice parameters of the transform skip block is enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled for each transform skip slice to indicate the Rice parameter of that slice. When the control flag is signaled as disabled (e.g., when set to be equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the transform skip slices, and a default Rice parameter (e.g., 1) is used for all transform skip slices. An example of the corresponding decoding process based on the VVC draft is shown below. Changes to the VVC draft are shown in italic font.

[0061]

Table 13

[0062] That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in the SH syntax structure referring to the SPS. That sps_ts_residual_coding_rice_present_in_sh_flag is equal to 0 specifies that sh_ts_residual_coding_rice_idx_minus1 does not exist in the SH syntax structure referring to the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag does not exist, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0063]

Table 14

[0064] sh_ts_residual_coding_rice_idx_minus1 + 1 specifies the Rice parameter used in the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_idx_minus1 does not exist, the value of sh_ts_residual_coding_rice_idx_minus1 is inferred to be equal to 0.

[0065] 9.3.3.11 Binarization Process of abs_remainder[] The input to this process is a request for binarization of the syntax element abs_remainder[n], color component cIdx, current sub-block index i, luminance position (x0, y0) specifying the top-left sample of the current luminance transform block with respect to the top-left luminance sample of the picture, current coefficient scan position (xC, yC), binary logarithm log2TbWidth of the transform block width, and binary logarithm log2TbHeight of the transform block height.

[0066] The output of this process is the binarization of the syntax element.

[0067] The variables lastAbsRemainder and lastRiceParam are derived as follows.

[0068] - When this process is called for the first time for the current sub-block index i, both lastAbsRemainder and lastRiceParam are set to be equal to 0.

[0069] - Otherwise (if this process is not called for the first time for the current sub-block index i), lastAbsRemainder and lastRiceParam are set to be equal to the values of abs_remainder[n] and cRiceParam derived during the last call of the binarization process of the syntax element abs_remainder[n] specified in this section, respectively.

[0070] The Rice parameter cRiceParam is derived as follows.

[0071] - When transform_skip_flag[x0][y0][cIdx] is equal to 1 and sh_ts_residual_coding_disabled_flag is equal to 0, the Rice parameter cRiceParam is set to be equal to sh_ts_residual_coding_rice_idx_minus1 + 1.

[0072] - Otherwise, the Rice parameter cRiceParam is derived by calling the Rice parameter derivation process of abs_remainder[] as specified in Section 9.3.3.2, using as inputs the variable baseLevel set to be equal to 4, the color component index cIdx, the luminance position (x0, y0), the current coefficient scan position (xC, yC), the binary logarithm log2TbWidth of the transform block width, and the binary logarithm log2TbHeight of the transform block height.

[0073] In yet another example, one syntax element is signaled for each transform skip slice to indicate the Rice parameter of that slice. An example of the corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are indicated in Table 10 in bold italic font. It is worth noting that sh_ts_residual_coding_rice_idx can be coded in various ways and / or can have a maximum value. For example, for coding / decoding the same syntax element, u(n), an unsigned integer using n bits, or f(n), a fixed pattern bit sequence using n bits with the left bit described first (from left to right), may also be used.

[0074] Slice header syntax

Table 15

[0075] sh_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. If sh_ts_residual_coding_rice_idx does not exist, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

Table 16

[0076] In yet another example, one control flag is signaled within the picture parameter set range extension syntax to indicate whether signaling of the Rice parameters for the conversion skip block is effective or not. When the control flag is signaled as effective, one syntax element is further signaled to indicate the Rice parameters of that picture. When the control flag is signaled as ineffective (e.g., when set to be equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameters of the conversion skip slice, and default Rice parameters (e.g., 1) are used for all conversion skip slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). The changes to the VVC draft are shown in Table 12 in bold italic font. It is worth noting that pps_ts_residual_coding_rice_idx can be coded in various ways and / or can have a maximum value. For example, for coding / decoding the same syntax element, u(n), which is an unsigned integer using n bits, or f(n), which is a fixed pattern bit sequence using n bits with the left bit described first (from left to right), may also be used.

[0077] Picture parameter set range extension syntax [Table 17]

[0078] The fact that pps_ts_residual_coding_rice_flag is equal to 1 specifies that pps_ts_residual_coding_rice_index may exist within the current picture. The fact that pps_ts_residual_coding_rice_flag is equal to 0 specifies that pps_ts_residual_coding_rice_idx does not exist within the current picture. When pps_ts_residual_coding_rice_flag does not exist, it is inferred that the value of pps_ts_residual_coding_rice_flag is equal to 0.

[0079] pps_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure.

Table 18

[0080] In yet another example, it is proposed to use only variable Rice parameters for the coding of the syntax element abs_remainder. The value of the Rice parameter to be applied may be determined according to specific coded information of the current block, such as block size, quantization parameter, bit depth, transform type, etc. In a specific embodiment, it is proposed to adjust the Rice parameter based on the coding bit depth and the quantization parameter applied to one CU. The corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are shown in bold italic font in Table 14, and the deleted content is shown in italic font. It is worth noting that in practice the same logic may be implemented in different ways. For example, specific equations or look-up tables may also be used to derive the same Rice parameter.

Table 19

[0081] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 33 or 34). Changes to the VVC draft are shown in bold italic font in Table 15, with deleted content in italics. It is worth noting that in practice the same logic may be implemented in different ways. For example, specific equations or lookup tables may also be used to derive the same Rice parameters. [Table 20]

[0082] In yet another example, the corresponding decoding process based on the VVC draft is shown below, A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B = 33 or 34). Changes to the VVC draft are shown in bold italics in Table 16, with deletions in italics. It is worth noting that in practice the same logic can be implemented in different ways. For example, a specific equation or lookup table may also be used to derive the same Rice parameters. [Table 21]

[0083] In yet another example, it is proposed that when a new flag, for example, extended_precision_processing_flag is equal to 1, only a variable Rice parameter is used for encoding the syntax element of abs_remainder. The variable value may be determined according to specific encoded information of the current block, such as block size, quantization parameter, bit depth, transform type, etc. In a specific embodiment, it is proposed to adjust the Rice parameter based on the encoded bit depth and the quantization parameter applied to one CU. The corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are shown in bold italic font in Table 17. It is worth noting that in practice, the same logic may be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 22

[0084] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 18, 19). The changes to the VVC draft are shown in bold italic font in Table 18. It is worth noting that in practice, the same logic may be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 23

[0085] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH A and TH B are predetermined thresholds (e.g., TH A = 8, TH B= 18 or 19). The changes to the VVC draft are shown in bold italic font in Table 19. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 24

[0086] Figure 6 shows a method for video encoding. The method may be applied, for example, to an encoder. In step 1610, the encoder may receive a video input. The video input may be, for example, a live stream. In step 1612, the encoder may obtain a quantization parameter based on the video input. The quantization parameter may be calculated, for example, by a quantization unit within the encoder. In step 1614, the encoder may derive a Rice parameter based on at least one predetermined threshold, encoding bit depth, and quantization parameter. The Rice parameter is used, for example, to signal the syntax of abs_remainder and dec_abs_level. In step 1616, the encoder may entropy encode the video bit stream based on the Rice parameter. The video bit stream may be entropy encoded, for example, to generate a compressed video bit stream.

[0087] In yet another example, when BitDepth is greater than 10, it is proposed to use only fixed values (e.g., 2, 3, 4, 5, 6, 7, or 8) for the Rice parameter when encoding the abs_remainder syntax element. The fixed values may vary under different conditions according to certain encoded information of the current block, e.g., the quantization parameter. The corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 18, 19). The changes to the VVC draft are indicated in Table 20 in bold italic font. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 25

[0088] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH A and TH B are predetermined thresholds (e.g., TH A = 8, TH B = 18 or 19). The changes to the VVC draft are indicated in Table 21 in bold italic font. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 26

[0089] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 33 or 34). The changes to the VVC draft are indicated in Table 22 in bold italic font. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 27

[0090] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH A and TH B are predetermined thresholds (e.g., TH A = 8, TH B = 33 or 34). The changes to the VVC draft are shown in bold italic font in Table 23. It is worth noting that the same logic can actually be implemented in different ways. For example, specific equations or look-up tables may also be used to derive the same Rice parameter.

Table 28

[0091] It is worth mentioning that in the above illustration, the equations used to calculate the specific Rice parameter are only used as examples to illustrate the proposed concept. For those skilled in modern video coding techniques, other mapping functions (or equivalent mapping equations) are already applicable to the proposed concept (i.e., determining the Rice parameter of the transform skip mode based on the coded bits and the applied quantization parameter). On the other hand, it should also be mentioned that in the current VVC design, it is allowed that the value of the applied quantization parameter changes at the coded block group level. Therefore, the proposed Rice parameter adjustment method can provide flexible adaptation of the Rice parameter of the transform skip mode at the coded block group level.

[0092] Signaling information for normal residual coding and transform skip residual coding According to one or more examples of the present disclosure, signaling a Rice parameter of a binary codeword for encoding a particular syntax element, e.g., abs_remainder, in transform skip residual coding, a shift parameter and an offset parameter for deriving the Rice parameter used for abs_remainder / dec_abs_level in normal residual coding, and determining whether to signal, according to a quantization parameter or coding bit depth associated with a particular coded information of the current block, e.g., TB / CB and / or slice / profile, and / or according to a new flag associated with TB / CB / slice / picture / sequence level, e.g., sps_residual_coding_info_present_in_sh_flag, is proposed.

[0093] In one example, one control flag is signaled within the slice header to indicate whether signaling of the Rice parameter for the conversion skip block and / or signaling of the shift parameter and / or offset parameter for derivation of the Rice parameter in the conversion block is valid or invalid. When the control flag is signaled as valid, one syntax element is further signaled for each conversion skip slice to indicate the Rice parameter of that slice, and two syntax elements are further signaled for each conversion slice to indicate the shift parameter and / or offset parameter for derivation of the Rice parameter of that slice. When the control flag is signaled as invalid (e.g., when set to be equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameter of the conversion skip slice, a default Rice parameter (e.g., 1) is used for all conversion skip slices, no further syntax elements are signaled at a lower level to indicate the shift parameter and offset parameter for derivation of the Rice parameter of the conversion slice, and default shift and / or offset parameters (e.g., 0) are used for all conversion slices. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). The changes to the VVC draft are shown in Table 24 in bold italic font. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_index can be coded in various ways and / or may have a maximum value. For example, for coding / decoding the same syntax element, a unsigned integer u(n) using n bits or a fixed pattern bit sequence f(n) using n bits with the left bit described first (from left to right) may also be used.

[0094] Figure 7 shows a method for video decoding. The method may be applied to, for example, an encoder. In step 1710, the encoder may receive a video input. In step 1712, the encoder may signal a Rice parameter of a binary codeword for an encoded syntax element. The encoded syntax element may include an abs_remainder in transform skip residual coding. In step 1714, the encoder may entropy encode a video bitstream based on the Rice parameter and the video input.

[0095] Slice header syntax [Table 29]

[0096] That sh_residual_coding_rice_flag is equal to 1 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index may exist within the current slice. That sh_residual_coding_rice_flag is equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index do not exist within the current slice.

[0097] sh_residual_coding_rice_shift specifies a shift parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_shift does not exist, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0098] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process of abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0099] sh_ts_residual_coding_rice_index specifies the Rice parameter used in the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_index does not exist, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

Table 30

Table 31

[0100] In another example, one control flag is signaled within the sequence parameter set (or within the sequence parameter set range extension syntax) to indicate whether signaling of the Rice parameters for the conversion skip blocks and / or signaling of the shift and / or offset parameters for the derivation of the Rice parameters in the conversion blocks is enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled for each conversion skip slice to indicate the Rice parameter of that slice, and two syntax elements are further signaled for each conversion slice to indicate the shift and / or offset parameters for the derivation of the Rice parameter of that slice. When the control flag is signaled as disabled (e.g., when set equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameter of the conversion skip slices, a default Rice parameter (e.g., 1) is used for all conversion skip slices, no further syntax elements are signaled at a lower level to indicate the shift and / or offset parameters for the derivation of the Rice parameter of the conversion slices, and default shift and / or offset parameters (e.g., 0) are used for all conversion slices. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). The changes to the VVC draft are shown in Table 27 in bold italic font. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx can be coded in various ways and / or can have maximum values. For example, to code / decoder the same syntax element, a unsigned integer u(n) using n bits, or a fixed pattern bit sequence f(n) using n bits with the left bit described first (from left to right) may also be used.

[0101] Sequence parameter set RBSP syntax

Table 32

[0102] The fact that sps_residual_coding_info_present_in_sh_flag is equal to 1 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx may exist in the SH syntax structure referring to the SPS. The fact that sps_residual_coding_info_present_in_sh_flag is equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx do not exist in the SH syntax structure referring to the SPS. When sps_residual_coding_info_present_in_sh_flag does not exist, the value of sps_residual_coding_info_present_in_sh_flag is inferred to be equal to 0.

[0103] Slice header syntax

Table 33

[0104] sh_residual_coding_rice_shift specifies the shift parameter used in the Rice parameter derivation process of abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_shift does not exist, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0105] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0106] sh_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_index does not exist, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

Table 34

Table 35

[0107] In yet another example, one syntax element is signaled to indicate the Rice parameter of a slice for each conversion skip slice, and two syntax elements are signaled to indicate the shift parameter and / or offset parameter for the derivation of the Rice parameter of that slice for each conversion skip slice. An example of a corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are indicated in Table 31 in bold italic font. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx can be coded in various ways and / or may have maximum values. For example, for encoding / decoding the same syntax element, u(n), an unsigned integer using n bits, or f(n), a fixed pattern bit sequence using n bits with the left bit described first (from left to right), may also be used.

[0108] Slice header syntax

Table 36

[0109] sh_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. When sh_ts_residual_coding_rice_idx does not exist, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

[0110] sh_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process of abs_remainder[] and dec_abs_level[]. When sh_residual_coding_rice_offset does not exist, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0111] The sh_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. When the sh_ts_residual_coding_rice_index does not exist, the value of the sh_ts_residual_coding_rice_index is inferred to be equal to 0. [Table 37] [Table 38]

[0112] In yet another example, one control flag is signaled within the picture parameter set range extension syntax to indicate whether signaling of the Rice parameters for the transform skip block and / or signaling of the shift and / or offset parameters for derivation of the Rice parameters in the transform block is enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled to indicate the Rice parameter for transform skip residual coding of that picture, and two syntax elements are further signaled to indicate the shift and / or offset parameter for derivation of the Rice parameter of that picture for each normal residual coding. When the control flag is signaled as disabled (e.g., when set equal to "0"), no further syntax elements are signaled at a lower level to indicate the Rice parameter for transform skip residual coding, a default Rice parameter (e.g., 1) is used for all transform skip residual codings, no further syntax elements are signaled at a lower level to indicate the shift and / or offset parameter for derivation of the Rice parameter of normal residual coding, and default shift and / or offset parameters (e.g., 0) are used for all normal residual codings. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). The changes to the VVC draft are shown in Table 34 in bold italic font. It is worth noting that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx can be coded in various ways and / or may have maximum values. For example, for coding / decoding the same syntax element, a unsigned integer u(n) using n bits without a sign, or a fixed pattern bit sequence f(n) using n bits with the left bit described first (from left to right) may also be used.

[0113] Picture parameter set range extension syntax

Table 39

[0114] That pps_residual_coding_info_flag is equal to 1 specifies that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_index may exist within the current picture. That pps_residual_coding_info_flag is equal to 0 specifies that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx do not exist within the current picture. When pps_residual_coding_info_flag does not exist, the value of pps_residual_coding_info_flag is inferred to be equal to 0.

[0115] pps_residual_coding_rice_shift specifies the shift parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When pps_residual_coding_rice_shift does not exist, the value of pps_residual_coding_rice_shift is inferred to be equal to 0.

[0116] pps_residual_coding_rice_offset specifies the offset parameter used in the Rice parameter derivation process for abs_remainder[] and dec_abs_level[]. When pps_residual_coding_rice_offset does not exist, the value of pps_residual_coding_rice_offset is inferred to be equal to 0.

[0117] The pps_ts_residual_coding_rice_idx specifies the Rice parameter used in the residual_ts_coding() syntax structure. When the pps_ts_residual_coding_rice_index does not exist, the value of the pps_ts_residual_coding_rice_index is inferred to be equal to 0. [Table 40] [Table 41]

[0118] According to one or more examples of the present disclosure, in transform skip residual coding, different Rice parameters for encoding specific syntax elements, such as abs_remainder, and the use of shift parameters and offset parameters for deriving the Rice parameters used for abs_remainder / dec_abs_level in normal residual coding, and, depending on the quantization parameter or encoded bit depth associated with the specific encoded information of the current block, such as TB / CB and / or slice / profile, and / or according to a new flag associated with the TB / CB / slice / picture / sequence level, such as the sps_residual_coding_info_present_in_sh_flag, it is proposed to determine which one to use.

[0119] In one example, one control flag is signaled within the slice header to indicate whether the process of deriving the Rice parameter of the conversion skip block and the process of deriving the shift parameter and / or offset parameter of the Rice parameter in the conversion block are valid or invalid. When the control flag is signaled as valid, the Rice parameter may vary under different conditions according to the specific encoded information of the current block, such as quantization parameter and bit depth. Also, the shift parameter and / or offset parameter for deriving the Rice parameter in normal residual coding may vary under different conditions according to the specific encoded information of the current block, such as quantization parameter and bit depth. When the control flag is signaled as invalid (e.g., when set to be equal to "0"), a default Rice parameter (e.g., 1) is used for all conversion skip slices, and default shift parameter and / or offset parameter (e.g., 0) are used for all conversion slices. An example of the corresponding decoding process based on the VVC draft is shown below, TH A and TH B are predetermined thresholds (e.g., TH A = 8, TH B = 18 or 19). The changes to the VVC draft are shown in bold italic font in Table 37. It is worth noting that the same logic can actually be implemented in different ways. For example, specific equations or look-up tables may also be used to derive the same Rice parameter.

[0120] Slice header syntax

Table 42

[0121] That sh_residual_coding_rice_flag is equal to 1 specifies that the bit-depth-dependent Rice parameter derivation process is used for the current slice. That sh_residual_coding_rice_flag is equal to 0 specifies that the bit-depth-dependent Rice parameter derivation process is not used for the current slice.

Table 43

Table 44

[0122] In yet another example, the corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined threshold (e.g., 18, 19). The changes to the VVC draft are shown in bold italic font in Table 40. It is worth noting that the same logic can actually be implemented in different ways. For example, a specific equation or look-up table may also be used to derive the same Rice parameter.

Table 45

[0123] According to another aspect of the present disclosure, it is proposed to add a constraint that the values of these encoding tools flag to provide the same general constraint control as others within the general constraint information.

[0124] For example, sps_ts_residual_coding_rice_present_in_sh_flag being equal to 1 specifies that there may be a sh_ts_residual_coding_rice_idx within the SH syntax structure referring to the SPS. When sps_ts_residual_coding_rice_present_in_sh_flag is equal to 0, it specifies that there is no sh_ts_residual_coding_rice_idx within the SH syntax structure referring to the SPS. According to the present disclosure, in order to provide the same general constraint control as other flags, it is proposed to add a syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 46

Table 47

[0125] In another example, pps_ts_residual_coding_rice_flag being equal to 1 specifies that there may be a pps_ts_residual_coding_rice_index within the current picture. pps_ts_residual_coding_rice_flag being equal to 0 specifies that there is no pps_ts_residual_coding_rice_idx within the current picture. According to the present disclosure, in order to provide the same general constraint control as other flags, it is proposed to add a syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 48

Table 49

[0126] In yet another example, when sps_rice_adaptation_enabled_flag equals 1, it indicates that the Rice parameters for binarization of abs_remainder[] and dec_abs_level can be derived by an equation.

[0127] The equation may include RiceParam = RiceParam + shiftVal, and shiftVal = (localSumAbs < Tx[0])? Rx[0] : ((localSumAbs < Tx[1])? Rx[1] : ((localSumAbs < Tx[2])? Rx[2] : ((localSumAbs < Tx[3])? Rx[3] : Rx[4]))), where the lists Tx[] and Rx[] are specified as Tx[] = {32, 128, 512, 2048}>>(1523) Rx[] = {0, 2, 4, 6, 8}.

[0128] According to the present disclosure, in order to provide the same general constraint control as other flags, it is proposed to add the syntax element gci_no_rice_adaptation_constraint_flag into the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 50

Table 51

[0129] Since the proposed Rice parameter adaptation method is only used for transform skip residual coding (TSRC), the proposed method can bring effects when TSRC is effective. Correspondingly, in one or more embodiments of the present disclosure, when the transform skip mode is invalid at the general constraint information level, for example, when the value of gci_no_transform_skip_constraint_flag is set to 1, it is proposed to add a one-bit stream constraint that requires the value of gci_no_rice_adaptation_constraint_flag to be 1.

[0130] In yet another example, sps_range_extension_flag being equal to 1 specifies that the sps_range_extension() syntax structure exists within the SPS RBSP syntax structure. sps_range_extension_flag being equal to 0 specifies that this syntax structure does not exist. According to the present disclosure, it is proposed to add a syntax element gci_no_range_extension_constraint_flag within the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 52

Table 53

[0131] Figure 9 shows a method for video encoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 1902, the decoder may receive a sequence parameter set (SPS) range extension flag indicating whether a syntax structure sps_range_extension exists within the raw byte sequence payload (RBSP) syntax structure of a slice head (SH) based on the value of the SPS range extension flag.

[0132] In step 1904, the decoder may determine that sps_range_extension exists within the SH RBSP syntax structure in response to a determination that the value of the SPS range extension flag is equal to 1.

[0133] In step 1906, the decoder may determine that sps_range_extension does not exist within the SH RBSP syntax structure in response to a determination that the value of the range extension flag is equal to 0.

[0134] The sps_cabac_bypass_alignment_enabled_flag specifies that the value of ivlCurrRange can be aligned before bypass decoding of the syntax elements sb_coded_flag[][], abs_remainder[], dec_abs_level[n], and coeff_sign_flag[]. That the sps_cabac_bypass_alignment_enabled_flag is equal to 0 specifies that the value of ivlCurrRange is not aligned before bypass decoding. According to the present disclosure, it is proposed to add a syntax element gci_no_cabac_bypass_alignment_constraint_flag within the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are emphasized in italics.

Table 54

Table 55

[0135] Figure 10 shows a method for video encoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 2002, the decoder may receive a SPS alignment valid flag indicating whether the index ivlCurrRange is aligned before bypass decoding of the syntax elements sb_coded_flag, abs_remainder, dec_abs_level, and coeff_sign_flagn based on the value of the sequence parameter set (SPS) alignment valid.

[0136] In step 2004, the decoder may determine that ivlCurrRange is aligned before bypass decoding in response to a determination that the value of the SPS alignment valid flag is equal to 1.

[0137] In step 2006, the decoder may determine that ivlCurrRange is not aligned before bypass decoding in response to a determination that the value of the SPS alignment valid flag is equal to 0.

[0138] In yet another example, that the extended_precision_processing_flag is equal to 1 specifies that an extended dynamic range may be used for the transform coefficients and the transform process. That the extended_precision_processing_flag is equal to 0 specifies that the extended dynamic range is not used. According to the present disclosure, it is proposed to add a syntax element gci_no_extended_precision_processing_constraint_flag in the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 56

Table  57

[0139] Figure 11 shows a method for video encoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 2102, the decoder may include receiving a transform coefficient and an extended precision processing flag indicating whether an extended dynamic range is employed during the transform based on the value of the extended precision processing flag.

[0140] In step 2104, the decoder may determine that an extended dynamic range is employed for the transform coefficient and during the transform in response to a determination that the value of the extended precision processing flag is equal to 1.

[0141] In step 2106, the decoder may determine that an extended dynamic range is not employed for the transform coefficient or during the transform in response to a determination that the value of the extended precision processing flag is equal to 0.

[0142] In yet another example, the fact that the persistant_rice_adaptation_enabled_flag is equal to 1 specifies that at the start of each sub-block, the derivation of the Rice parameters for the binarization of abs_remainder[] and dec_abs_level can be initialized using the mode-dependent statistics accumulated from the previous sub-block. The fact that the persistant_rice_adaptation_enabled_flag is equal to 0 specifies that the previous sub-block state is not used in the Rice parameter derivation. According to the present disclosure, it is proposed to add a syntax element gci_no_persistent_rice_adaptation_constraint_flag within the general constraint information syntax to provide the same general constraint control as for the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics. [Table 58] [Table 59]

[0143] FIG. 12 shows a method for video coding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 2202, the decoder may receive a persistent Rice adaptation enable flag indicating whether the derivation of the Rice parameters for the binarization of abs_remainder and dec_abs_level is initialized at the start of each sub-block that employs the mode-dependent statistics accumulated from the previous sub-block, based on the value of the persistent Rice adaptation enable flag.

[0144] In step 2204, the decoder may determine that the derivation of the Rice parameters for binarization is initialized at the start of each sub-block that employs the mode-dependent statistics accumulated from the previous sub-block, in response to a determination that the value of the persistent Rice adaptation enable flag is equal to 1.

[0145] In step 2206, in response to determining that the value of the persistent Rice adaptation enable flag is equal to 0, the decoder may determine that the previous sub-block state is not adopted in Rice parameter derivation.

[0146] In yet another example, sps_rrc_rice_extension_flag being equal to 1 specifies that the extension of Rice parameter derivation for the binarization of abs_remainder[] and dec_abs_level[] is effective. sps_rrc_rice_extension_flag being equal to 0 specifies that the extension of Rice parameter derivation for the binarization of abs_remainder[] and dec_abs_level[] is ineffective. According to the present disclosure, it is proposed to add a syntax element gci_no_rrc_rice_extension_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changed parts for the VVC draft are highlighted. The added parts are shown in the following italic font. [Table 60] [Table 61]

[0147] FIG. 17 shows a method for video decoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 2702, the decoder may receive an SPS Rice extension flag indicating whether the extension of Rice parameter derivation for the binarization of abs_remainder and dec_abs_level is effective.

[0148] In step 2704, in response to determining that the value of the SPS Rice extension flag is equal to 1, the decoder may determine that the extension of Rice parameter derivation for binarization is effective.

[0149] In step 2706, the decoder may determine that the extension of the Rice parameter derivation for binarization is invalid in response to determining that the value of the SPS Rice extension flag is equal to 0.

[0150] In yet another example, sps_persistent_rice_adaptation_enabled_flag being equal to 1 specifies that the Rice parameter derivation for the binarization of abs_remainder[] and dec_abs_level[] is initialized at the start of each TU using the statistics accumulated from the previous TU. sps_persistent_rice_adaptation_enabled_flag being equal to 0 specifies that the previous TU state is not used in the Rice parameter derivation. According to the present disclosure, it is proposed to add a syntax element gci_no_persistent_rice_adaptation_enabled_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are shown in the following italic font. [Table 62] [Table 63]

[0151] FIG. 18 shows a method for video decoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 2802, the decoder may receive an SPS Rice adaptation enable flag indicating whether the Rice parameter derivation for the binarization of abs_remainder and dec_abs_level is initialized at the start of each transform unit using the statistics accumulated from the previous TU.

[0152] In step 2804, in response to determining that the value of the SPS Rice Adaptation Enable flag is equal to 1, the decoder may determine that the Rice parameter derivation for binarization is initialized at the start of each TU using the statistics accumulated from the previous TU.

[0153] In step 2806, in response to determining that the value of the SPS Rice Adaptation Enable flag is equal to 0, the decoder may determine that the previous TU state is not adopted in the Rice parameter derivation.

[0154] In yet another example, sps_reverse_last_sig_coeff_enabled_flag being equal to 1 specifies that sh_reverse_last_sig_coeff_flag exists within the slice_header() syntax structure that references the SPS. sps_reverse_last_sig_coeff_enabled_flag being equal to 0 specifies that sh_reverse_last_sig_coeff_flag does not exist within the slice_header() syntax structure that references the SPS. According to the present disclosure, it is proposed to add a syntax element gci_no_reverse_last_sig_coeff_enabled_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are emphasized in italics.

Table 64

Table 65

[0155] The fact that sh_reverse_last_sig_coeff_flag is equal to 1 specifies that the coordinates of the last significant coefficient are encoded with reference to ((Log2ZoTbWidth<<1)-1,(Log2ZoTbHeight<<1)-1) of each transform block of the current slice. The fact that sh_reverse_last_sig_coeff_flag is equal to 0 specifies that the coordinates of the last significant coefficient are encoded with reference to (0,0) of each transform block of the current slice. When it does not exist, the value of sh_reverse_last_sig_coeff_flag is inferred to be equal to 0.

[0156] FIG. 19 shows a method for video decoding according to an example of the present disclosure. The method may be applied, for example, to a decoder. In step 2902, the decoder may receive a reversed coordinate of a last significant coefficient enabled flag indicating whether the SH reversed coordinate of the last significant coefficient enabled flag exists within a slice header syntax structure referring to the SPS.

[0157] In step 2904, the decoder may determine that the SH reversed coordinate of the last significant coefficient enabled flag exists within a slice header syntax structure referring to the SPS in response to a determination that the value of the reversed coordinate of the last significant coefficient enabled flag is equal to 1.

[0158] In step 2906, the decoder may determine that the SH reversed coordinate of the last significant coefficient enabled flag does not exist within a slice header syntax structure referring to the SPS in response to a determination that the value of the reversed coordinate of the last significant coefficient enabled flag is equal to 0.

[0159] In yet another example, when the sps_transform_precision_adaptation_enabled_flag is equal to 1, it specifies that the downshift in the scaling process of the transform coefficients and the transform process of the scaled transform coefficients is adaptively assigned by examining the coefficient values during inverse quantization and inverse transformation. According to the present disclosure, in order to provide the same general constraint control as other flags, it is proposed to add a syntax element gci_no_transform_precision_adaptation_enabled_flag to the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics. [Table 66] [Table 67]

[0160] FIG. 20 shows a method for video decoding according to an example of the present disclosure. The method may be applied to a decoder, for example. In step 3002, the decoder may receive an SPS transform precision adaptation enable flag indicating whether the downshift in the scaling process of the transform coefficients and the transform process of the scaled transform coefficients is adaptively assigned by examining the coefficient values of inverse quantization and inverse transformation.

[0161] In step 3004, in response to a determination that the value of the SPS transform precision adaptation enable flag is equal to 1, the decoder may determine that the downshift in the scaling process of the transform coefficients and the transform process of the scaled transform coefficients is adaptively assigned by examining the coefficient values of inverse quantization and inverse transformation.

[0162] In yet another example, if the sps_high_throughput_flag is equal to 1, it may be determined that all syntax elements in the residual coding except for the position of the last valid coefficient in the RRC are encoded through the bypass mode, and only one alignment is required after the position of the last valid coefficient in the RRC and at the beginning of the TB of the TSRC. According to the present disclosure, in order to provide the same general constraint control as other flags, it is proposed to add a syntax element gci_no_high_throughput_flag to the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

Table 68

Table 69

[0163] FIG. 21 shows a method for video decoding according to an example of the present disclosure. The method may be applied to a decoder, for example. In step 3102, the decoder may receive an SPS high-throughput flag indicating whether the syntax elements in the residual coding are encoded through the bypass mode.

[0164] In step 3104, in response to a determination that the value of the SPS high-throughput flag is equal to 1, the decoder may determine that all syntax elements in the residual coding except for the position of the last valid coefficient in the regular residual coding (RRC) are encoded through the bypass mode, and alignment is performed after the position of the last valid coefficient and at the beginning of the transform block (TB) in the transform skip residual coding (TSRC).

[0165] The above method may be implemented using an apparatus including one or more circuits including, for a particular application, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. The apparatus may use the circuits in combination with other hardware components or software components to perform the methods described above. Each module, sub-module, unit, or sub-unit disclosed above may be implemented at least partially using one or more circuits.

[0166] Determination of Rice parameter On the encoder side, TSRC encoding may require multiple encoding paths to derive the best Rice parameter. This multi-path encoding may not be suitable for the design of an actual hardware encoder. To solve this problem, a low-latency TSRC encoding method is also proposed. According to one or more examples of the present disclosure, it is proposed to derive the Rice parameter according to specific encoded information of the current slice, for example, the quantization parameter and / or the encoded bit depth associated with the slice / picture / sequence, and / or according to the hash ratio associated with the level of the slice / picture / sequence. Various methods may be used to derive the Rice parameter, and some exemplary methods are listed below. It should be noted that the following methods may be applied alone or in combination.

[0167] 1. The Rice parameter described in the above embodiment may further depend on the video resolution including both the temporal resolution (e.g., frame rate) and the spatial resolution (e.g., width and height of the picture) of the video.

[0168] 2. The Rice parameter may vary at the sequence level, picture level, slice level, and / or any predetermined region. In a specific example, different Rice values are used for pictures having different temporal layer IDs (related to nuh_temporal_id_plus1 specified in the VVC specification). Alternatively, the Rice parameter may include a value determined based on the QP value used at the sequence level, picture level, slice level, and / or any predetermined region. For example, the Rice parameter = Clip3(1, 8, (TH - QP) / 6), where TH is a predetermined threshold (e.g., 18, 19).

[0169] 3. The Rice parameter may be set to a default value, e.g., 1, according to the change in the encoded information between the current slice and the previous slice. In a specific example, when the temporal layer ID has changed compared to the previous picture, the default Rice value is used for the picture. Alternatively, when ΔQ is greater than TH, the default Rice value is used for the picture, where ΔQ is calculated as abs(QPcurrent - QPprevious) and TH is a predetermined threshold. The Rice parameter (e.g., 0, 5). For example, when the hash ratio from the intra block copy mode of the current slice is greater than TH, the Rice parameter = 1, where TH is a predetermined threshold, e.g., Max(41 * (number of CTUs), 4200).

[0170] 4. The Rice parameter of each slice based on the value of abs_remainder encoded in its preceding slice according to the symbolization order. In a specific example, after one slice is encoded, the number of bins for the binarization of abs_remainder using different Rice parameters is calculated, and then that number is used to determine the Rice parameter of the subsequent slice. For example, the Rice parameter that achieves the minimum number of bins in the preceding slice is selected for the current slice. As another example, if the current slice and its preceding slice use the same QP, the Rice parameter that achieves the minimum number of bins in the preceding slice is selected for the current slice; otherwise, the number of bins generated using the default Rice parameter (i.e., 1) in the preceding slice is scaled by TH before being compared with other Rice parameters, and the Rice parameter that results in the minimum number of bins is selected for the current slice, where TH is a predetermined threshold, e.g., 0.9.

[0171] 5. It is the Rice parameter of each slice based on the value of abs_remainder encoded in its preceding slice according to the symbolization order, and the Rice parameter may be adjusted according to the change in the encoded information between the current slice and the previous slice. In a specific example, for example, the Rice parameter that achieves the minimum number of bins in the preceding slice is selected for the current slice. Also, when ΔQ is greater than TH, the Rice value may be adjusted, where ΔQ is calculated as abs(QPcurrent - QPprevious), and TH is a predetermined threshold. The Rice parameter (e.g., 0, 5). The adjustment may be adding a predetermined offset (e.g., +1, -1) or scaling by a predetermined value.

[0172] Bitstream Constraint In one or more examples of the present disclosure, it is proposed to disable the existence of Rice parameters for conversion skip residual coding and high bit-depth tools for low bit-depth coding. In a specific example, to achieve such an objective, it is proposed to add a bitstream compliance requirement indicating that such tools are disabled when the bit depth is 10 or less in a profile definition such as HEVC or its semantics.

[0173] For example, sps_ts_residual_coding_rice_present_in_sh_flag being equal to 1 specifies that sh_ts_residual_coding_rice_idx may exist within the SH syntax structure referring to the SPS. The changes to the current VVC working draft are as follows.

[0174] When BitDepth is 10 or less, it is a bitstream compliance requirement that the value of sps_ts_residual_coding_rice_present_in_sh_flag be equal to 0.

[0175] In another example, sps_rrc_rice_extension_flag being equal to 1 specifies that the extension of Rice parameter derivation for the binarization of abs_remaining[] and dec_abs_level[] is valid. sps_rrc_rice_extension_flag being equal to 0 specifies that the extension of Rice parameter derivation for the binarization of abs_remaining[] and dec_abs_level[] is invalid. According to the present disclosure, the changes to the current VVC working draft are as follows.

[0176] When BitDepth is 10 or less, it is a bitstream compliance requirement that the value of sps_rrc_rice_extension_flag be equal to 0.

[0177] In yet another example, sps_persistent_rice_adaptation_enabled_flag being equal to 1 specifies that the derivation of Rice parameters for the binarization of abs_remainder[] and dec_abs_level[] is initialized at the start of each TU using the statistics accumulated from the previous TU. sps_persistent_rice_adaptation_enabled_flag being equal to 0 specifies that the previous TU state is not used for the derivation of Rice parameters. According to the present disclosure, the changes to the current VVC working draft are as follows

[0178] When BitDepth is 10 or less, it is a bitstream compliance requirement that the value of sps_persistent_rice_adaptation_enabled_flag be equal to 0.

[0179] In yet another example, sps_reverse_last_sig_coeff_enabled_flag being equal to 1 specifies that sh_reverse_last_sig_coeff_flag exists within the slice_header() syntax structure that references the SPS. sps_reverse_last_sig_coeff_enabled_flag being equal to 0 specifies that sh_reverse_last_sig_coeff_flag does not exist within the slice_header() syntax structure that references the SPS. According to the present disclosure, the changes to the current VVC working draft are as follows

[0180] When BitDepth is 10 or less, it is a bitstream compliance requirement that the value of sps_reverse_last_sig_coeff_enabled_flag be equal to 0.

[0181] In yet another example, when sps_high_throughput_flag is equal to 1, it specifies that syntax elements in residual coding are encoded through the bypass mode. According to the present disclosure, the changes to the current VVC working draft are as follows.

[0182] When BitDepth is 10 or less, it is a bitstream compliance requirement that the value of sps_high_throughput_flag be equal to 0.

[0183] Furthermore, it is worth mentioning that the proposed bitstream compliance constraint sps_ts_residual_coding_rice_present_in_sh_flag regarding the encoded bit depth is orthogonal to the conditional signaling of the transform skip flag, i.e., the slice-level flag of sps_transform_skip_enabled_flag. In one embodiment, in such a combination, the flag sps_transform_skip_enabled_flag is used to condition the presence of sps_ts_residual_coding_rice_present_in_sh_flag. On the other hand, the compliant bitstream is also applied to require that sps_ts_residual_coding_rice_present_in_sh_flag can only be equal to 1 when the value of the encoded bit depth is greater than 10. The following shows the SPS syntax table and the semantic changes when such a method is applied.

Table 70

[0184] When sps_ts_residual_coding_rice_present_in_sh_flag is equal to 1, it specifies that there may be a sh_ts_residual_coding_rice_idx within the SH syntax structure that refers to the SPS. The changes to the current VVC working draft are as follows.

[0185] When the BitDepth is 10 or less, it is a requirement for bitstream compliance that the value of sps_ts_residual_coding_rice_present_in_sh_flag be equal to 0.

[0186] FIG. 22 shows a method for video decoding according to an example of the present disclosure. The method may be applied to, for example, a decoder. In step 3202, the decoder may determine the encoded bit depth of at least one sample in the bitstream. In step 3204, the decoder may determine the value of a first SPS flag for at least one sample. In step 3206, the decoder may determine a second SPS flag for at least one sample based on the value of the first SPS flag in combination with the encoded bit depth of at least one sample. In some examples, the decoder may determine the presence of the second SPS flag based on the first SPS flag, or may determine the value of the second SPS flag based on the encoded bit depth. In some examples, the decoder may determine the presence of the second SPS flag based on the first SPS flag and the encoded bit depth. In some examples, the decoder may determine the value of the second SPS flag based on the first SPS flag and the encoded bit depth. In some other examples, the decoder may determine the value of the second SPS flag based on the encoded bit depth regardless of the value of the first SPS flag.

[0187] In another embodiment, instead of applying bitstream compliance, it is proposed to conditionally signal the sps_ts_residual_coding_rice_present_in_sh_flag directly using the bit depth and the flag sps_transform_skip_enabled_flag. Specifically, by such a method, as shown below, the value of the sps_ts_residual_coding_rice_present_in_sh_flag is signaled only when the sps_transform_skip_enabled_flag is equal to 1 and the coded bit depth is greater than 10.

Table 71

[0188] FIG. 16 shows a flowchart of a low-delay transform skip residual coding (TSRC) method according to an example of the present disclosure. The method may be applied, for example, to an encoder. In step 2602, the encoder may derive a Rice parameter based on the encoded information of the current slice of the video. The encoded information may include one or more of the following parameters, namely, the quantization parameter or the coded bit depth associated with the slice, picture, or sequence of the video, or the hash ratio associated with the slice, picture, or sequence of the video.

[0189] It should be noted that the above encoder method may also be applied to the decoder side. In a specific example, it is not necessary to signal the Rice parameter to the decoder, and the encoder / decoder derives the Rice parameter using the same method.

[0190] FIG. 8 shows a computing environment 1810 coupled to a user interface 1860. The computing environment 1810 may be part of a data processing server. The computing environment 1810 includes a processor 1820, a memory 1840, and an I / O interface 1850.

[0191] Processor 1820 typically controls the overall operation of computing environment 1810, such as operations related to display, data acquisition, data communication, and image processing. Processor 1820 may include one or more processors for executing instructions to perform all or some of the steps in the above methods. Further, processor 1820 may include one or more modules to facilitate interaction between processor 1820 and other components. The processor may be a central processing unit (CPU), a microprocessor, a single-chip machine, a GPU, or the like.

[0192] Memory 1840 is configured to store various types of data to support the operation of computing environment 1810. Memory 1840 may include a predetermined software 1842. Examples of such data include instructions for any application or method operating on computing environment 1810, video data sets, image data, and the like. Memory 1840 may be implemented by using any type of volatile or non-volatile memory device, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk, or a combination thereof.

[0193] I / O interface 1850 provides an interface between processor 1820 and peripheral interface modules such as a keyboard, click wheel, buttons, and the like. The buttons may include, but are not limited to, a home button, a scan start button, and a scan stop button. I / O interface 1850 may be coupled to an encoder and a decoder.

[0194] In some embodiments, a non-transitory computer-readable storage medium is also provided that includes a plurality of programs, such as those included in memory 1840, executable by a processor 1820 within a computing environment 1810 for performing the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, or the like.

[0195] The non-transitory computer-readable storage medium stores a plurality of programs executable by a computing device having one or more processors, and the plurality of programs, when executed by one or more processors, cause the computing device to perform the above-described method for motion prediction.

[0196] In some embodiments, the computing environment 1810 may be implemented using one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), graphical processing units (GPUs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described method.

[0197] FIG. 13 is a block diagram illustrating an exemplary system 10 for encoding and decoding video blocks in parallel according to some implementations of the present disclosure. As shown in FIG. 13, system 10 includes a source device 12 that generates and encodes video data to be decoded later by a destination device 14. Source device 12 and destination device 14 may include any of a variety of electronic devices including a desktop or laptop computer, a tablet computer, a smartphone, a set-top box, a digital television, a camera, a display device, a digital media player, a video game console, a video streaming device, or the like. In some implementations, source device 12 and destination device 14 have wireless communication capabilities.

[0198] In some implementations, destination device 14 may receive the encoded video data to be decoded via link 16. Link 16 may include any type of communication medium or communication device capable of moving the encoded video data from source device 12 to destination device 14. In one example, link 16 may include a communication medium that enables source device 12 to directly transmit the encoded video data to destination device 14 in real time. The encoded video data may be modulated according to a communication standard such as a wireless communication protocol and transmitted to destination device 14. The communication medium may include any wireless communication medium or wired communication medium such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include a router, a switch, a base station, or any other device that may be useful in facilitating communication from source device 12 to destination device 14.

[0199] In some other implementations, the encoded video data may be sent from the output interface 22 to the storage device 32. Subsequently, the encoded video data within the storage device 32 may be accessed by the destination device 14 via the input interface 28. The storage device 32 may include any of a variety of data storage media that are either distributed or locally accessible, such as a hard drive, a Blu-ray disk, a digital versatile disk (DVD), a compact disk read-only memory (CD-ROM), a flash memory, a volatile or non-volatile memory, or any other suitable digital storage media for storing the encoded video data. In a further example, the storage device 32 may correspond to a file server or another intermediate storage device that can hold the encoded video data generated by the source device 12. The destination device 14 may access the stored video data from the storage device 32 via streaming or download. The file server may be any type of computer capable of storing the encoded video data and transmitting the encoded video data to the destination device 14. Exemplary file servers include a web server (e.g., for a website), a File Transfer Protocol (FTP) server, a Network Attached Storage (NAS) device, or a local disk drive. The destination device 14 may access the encoded video data through any standard data connection that includes both a wireless channel (e.g., a Wireless Fidelity (Wi-Fi) connection), a wired connection (e.g., a Digital Subscriber Line (DSL), a cable modem, etc.), or a combination of both suitable for accessing the encoded video data stored on the file server. The transmission of the encoded video data from the storage device 32 may be a streaming transmission, a download transmission, or a combination of both.

[0200] As shown in FIG. 13, the source device 12 includes a video source 18, a video encoder 20, and an output interface 22. The video source 18 may include a video capture device, such as a video camera, a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and / or a source such as a computer graphics system for generating computer graphics data as source video, or a combination of such sources. As an example, if the video source 18 is a video camera of a security monitoring system, the source device 12 and the destination device 14 may form a camera phone or a video phone. However, the implementations described in this application may generally be applicable to video encoding and may be applicable to wireless applications and / or wired applications.

[0201] The captured video, previously captured video, or computer-generated video may be encoded by the video encoder 20. The encoded video data may be transmitted directly to the destination device 14 via the output interface 22 of the source device 12. The encoded video data may also (or alternatively) be stored on the storage device 32 so that it can be accessed later by the destination device 14 or other devices for decoding and / or playback. The output interface 22 may further include a modem and / or a transmitter.

[0202] The destination device 14 includes an input interface 28, a video decoder 30, and a display device 34. The input interface 28 may include a receiver and / or a modem and may receive encoded video data via link 16. The encoded video data communicated on link 16 or provided on storage device 32 may include various syntax elements generated by video encoder 20 for use in decoding the video data by video decoder 30. Such syntax elements may be included within the encoded video data transmitted on a communication medium, stored on a storage medium, or stored on a file server.

[0203] In some implementations, the destination device 14 may include a display device 34, and the display device 34 may be an integrated display device and an external display device configured to communicate with the destination device 14. The display device 34 may display the decoded video data to the user and may include any of various display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0204] The video encoder 20 and the video decoder 30 may operate according to a proprietary or industry standard such as VVC, HEVC, MPEG-4, Part 10, AVC, or an extension of such a standard. It should be understood that the present application is not limited to a particular video encoding / decoding standard and is applicable to other video encoding / decoding standards as well. In general, it is contemplated that the video encoder 20 of the source device 12 may be configured to encode video data according to any of these current or future standards. Similarly, in general, it is also contemplated that the video decoder 30 of the destination device 14 may be configured to decode video data according to any of these current or future standards.

[0205] Video encoder 20 and video decoder 30 may each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. If the electronic device is implemented partially within software, instructions for the software may be stored on a suitable non-transitory computer-readable medium and the instructions may be executed within hardware using one or more processors to perform the video encoding / decoding operations disclosed in this disclosure. Each of video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, and either or both may be integrated as part of a combined encoder / decoder (CODEC) within their respective devices.

[0206] FIG. 14 is a block diagram illustrating an exemplary video encoder 20 according to some implementations described in this application. Video encoder 20 may perform intra prediction encoding and inter prediction encoding of video blocks within a video frame. Intra prediction encoding reduces or removes spatial redundancy of video data within a given video frame or picture depending on spatial prediction. Inter prediction encoding reduces or removes temporal redundancy of video data within adjacent video frames or pictures of a video sequence depending on temporal prediction. It should be noted that the term "frame" may be used synonymously with the terms "image" or "picture" in the field of video encoding.

[0207] As shown in FIG. 14, the video encoder 20 includes a video data memory 40, a prediction processing unit 41, a decoded picture buffer (DPB) 64, an adder 50, a conversion processing unit 52, a quantization unit 54, and an entropy encoding unit 56. The prediction processing unit 41 further includes a motion estimation unit 42, a motion compensation unit 44, a partitioning unit 45, an intra prediction processing unit 46, and an intra block copy (BC) unit 48. In some implementations, the video encoder 20 also includes an inverse quantization unit 58, an inverse conversion processing unit 60, and an adder 62 for video block reconstruction. In order to filter block boundaries and remove blocky artifacts from the reconstructed video, a loop filter 63 such as a deblocking filter may be arranged between the adder 62 and the DPB 64. In addition to the deblocking filter, another loop filter such as a sample adaptive offset (SAO) filter and / or an adaptive loop filter (ALF) may also be used to filter the output of the adder 62. In some examples, the loop filter may be omitted, and the decoded video blocks may be directly provided to the DPB 64 by the adder 62. The video encoder 20 may take the form of a fixed or programmable hardware unit, or may be divided into one or more of the illustrated fixed or programmable hardware units.

[0208] The video data memory 40 may store video data to be encoded by components of the video encoder 20. The video data in the video data memory 40 may be obtained, for example, from the video source 18 shown in FIG. 13. The DPB 64 is a buffer that stores reference video data (e.g., reference frames or reference pictures) for use when encoding video data by the video encoder 20 (e.g., in an intra prediction encoding mode or an inter prediction encoding mode). The video data memory 40 and the DPB 64 may be formed by any of various memory devices. In various examples, the video data memory 40 may be on-chip with other components of the video encoder 20 or may be off-chip with respect to those components.

[0209] As shown in FIG. 14, after receiving video data, the partitioning unit 45 in the prediction processing unit 41 partitions the video data into video blocks. This partitioning also includes partitioning the video frame into slices, tiles (e.g., a set of video blocks), or other larger coding units (CUs) according to a predefined decomposition structure such as a quad-tree (QT) structure associated with the video data. The video frame may be or may be regarded as a two-dimensional array or two-dimensional matrix of samples having sample values. Samples in the array may also be called pixels or pels. The number of samples in the horizontal and vertical directions (or axes) of the array or picture defines the size and / or resolution of the video frame. The video frame may be divided into a plurality of video blocks, for example, by using QT partitioning. A video block is also a two-dimensional array or two-dimensional matrix of samples having sample values, although it has a smaller dimension than the video frame, or may be regarded as such. The number of samples in the horizontal and vertical directions (or axes) of the video block defines the size of the video block. The video block may be further partitioned into one or more block partitions or sub-blocks (which may form blocks again) by repeatedly using, for example, QT partitioning, binary-tree (BT) partitioning, or triple-tree (TT) partitioning, or any combination thereof. It should be noted that the term "block" or "video block" as used herein can be a part of a frame or picture, specifically a rectangular (square or non-square) portion. For example, with respect to HEVC and VVC, a block or video block may be or correspond to a coding tree unit (CTU), CU, prediction unit (PU), or transform unit (TU), and / or a corresponding block, e.g., a coding tree block (CTB), coding block (CB), prediction block (PB), or transform block (TB), and / or a sub-block, or may correspond to them.

[0210] Based on the error results (e.g., the coding rate and the level of distortion), the prediction processing unit 41 may select one of a plurality of possible prediction coding modes for the current video block, such as one of a plurality of intra-prediction coding modes or one of a plurality of inter-prediction coding modes. The prediction processing unit 41 provides the resulting intra-prediction coded block or inter-prediction coded block to the adder 50 to generate a residual block, and also provides the resulting intra-prediction coded block or inter-prediction coded block to the adder 62 to reconstruct the coded block for use as part of a reference frame thereafter. Also, the prediction processing unit 41 provides syntax elements such as motion vectors, intra-mode indicators, partition information, and other such syntax information to the entropy coding unit 56.

[0211] To select an appropriate intra-prediction coding mode for the current video block, the intra-prediction processing unit 46 within the prediction processing unit 41 may perform intra-prediction coding of the current video block with respect to one or more adjacent blocks within the same frame as the current block to be coded, to provide spatial prediction. The motion estimation unit 42 and the motion compensation unit 44 within the prediction processing unit 41 perform inter-prediction coding of the current video block with respect to one or more prediction blocks within one or more reference frames to provide temporal prediction. The video encoder 20 may execute a plurality of coding paths, for example, to select an appropriate coding mode for each block of video data.

[0212] In some implementations, the motion estimation unit 42 determines an inter prediction mode for the current video frame by generating a motion vector indicating the displacement of a video block in the current video frame relative to a predicted block in a reference video frame according to a predetermined pattern within the sequence of video frames. The motion estimation performed by the motion estimation unit 42 is a process of generating a motion vector that estimates the motion of a video block. For example, the motion vector may indicate the displacement of a video block in the current video frame or picture relative to a predicted block in a reference frame with respect to the current block being encoded in the current frame. The predetermined pattern designates video frames within the sequence as P-frames or B-frames. The intra BC unit 48 may determine a vector for intra BC encoding, such as a block vector, in a manner similar to the determination of the motion vector by the motion estimation unit 42 for inter prediction, or may utilize the motion estimation unit 42 to determine the block vector.

[0213] The predicted block of a video block may be a block or reference block in a reference frame that is considered to exactly match the video block to be encoded in terms of pixel difference, or may correspond to those blocks, and those blocks may be determined by sum of absolute differences (SAD), sum of squared differences (SSD), or other difference metrics. In some implementations, the video encoder 20 may calculate values of sub-integer pixel positions of a reference frame stored in the DPB 64. For example, the video encoder 20 may interpolate values of quarter-pixel positions, eighth-pixel positions, or other fractional pixel positions of the reference frame. Thus, the motion estimation unit 42 may perform motion search for both full pixel positions and fractional pixel positions and output a motion vector with fractional pixel accuracy.

[0214] The motion estimation unit 42 calculates a motion vector of a video block in an inter-predicted coded frame by comparing the position of the video block with the position of a predicted block of a reference frame selected from a first reference frame list (list 0) or a second reference frame list (list 1) that respectively identifies one or more reference frames stored in the DPB 64. The motion estimation unit 42 sends the calculated motion vector to the motion compensation unit 44 and then to the entropy coding unit 56.

[0215] Motion compensation performed by the motion compensation unit 44 may include fetching or generating a predicted block based on the motion vector determined by the motion estimation unit 42. When receiving the motion vector of the current video block, the motion compensation unit 44 may identify the position of the predicted block pointed to by the motion vector in one of the reference frame lists, obtain the predicted block from the DPB 64, and transfer the predicted block to the adder 50. Next, the adder 50 forms a residual video block of pixel difference values by subtracting the pixel values of the predicted block provided by the motion compensation unit 44 from the pixel values of the currently encoded video block. The pixel difference values forming the residual video block may include a luminance difference component, a chrominance difference component, or both. The motion compensation unit 44 may also generate syntax elements associated with the video blocks of the video frame for use when decoding the video blocks of the video frame by the video decoder 30. The syntax elements may include, for example, syntax elements defining the motion vectors used to identify the predicted blocks, any flags indicating the prediction mode, or any other syntax information described herein. Note that the motion estimation unit 42 and the motion compensation unit 44 may be highly integrated, but are shown separately for the purpose of illustration.

[0216] In some implementations, the intra BC unit 48 can generate vectors and fetch prediction blocks in a manner similar to the manner described above in relation to the motion estimation unit 42 and the motion compensation unit 44, where the prediction blocks are in the same frame as the currently encoded block, and the vectors are called block vectors rather than motion vectors. Specifically, the intra BC unit 48 may determine an intra prediction mode to use for encoding the current block. In some examples, the intra BC unit 48 may encode the current block using various intra prediction modes, for example, during a separate encoding pass, and test their performance through rate-distortion analysis. Next, the intra BC unit 48 may select an appropriate intra prediction mode to use from among the various tested intra prediction modes and generate an intra mode indicator accordingly. For example, the intra BC unit 48 may calculate rate-distortion values using rate-distortion analysis for the various tested intra prediction modes and select the intra prediction mode having the best rate-distortion characteristics among the tested modes as the appropriate intra prediction mode to use. Rate-distortion analysis generally determines the amount of distortion (or error) between the encoded block and the original unencoded block that was encoded to create the encoded block, and the bit rate (i.e., the number of bits) used to create the encoded block. The intra BC unit 48 may calculate a ratio from the distortion and rate of the various encoded blocks to determine which intra prediction mode exhibits the best rate-distortion value for that block.

[0217] In other examples, the intra BC unit 48 may use all or part of the motion estimation unit 42 and the motion compensation unit 44 to perform such functions for intra BC prediction according to the implementations described herein. In any case, for intra block copy, the prediction block may be a block that is considered to exactly match the block to be encoded, which can be determined by SAD, SSD, or other difference metrics with respect to the pixel difference, and the identification of the prediction block may include the calculation of the values of sub-pixel positions.

[0218] Whether the prediction block is a block from the same frame according to intra prediction or a block from different frames according to inter prediction, the video encoder 20 may form a residual video block by subtracting the pixel values of the prediction block from the pixel values of the currently encoded video block to form a pixel difference value. The pixel difference value for forming the residual video block may include both the luminance component difference and the chrominance component difference.

[0219] As described above, the intra prediction processing unit 46 may perform intra prediction on the current video block as an alternative to inter prediction executed by the motion estimation unit 42 and the motion compensation unit 44, or as an alternative to intra block copy prediction executed by the intra BC unit 48. Specifically, the intra prediction processing unit 46 may determine an intra prediction mode to be used for encoding the current block. To do so, the intra prediction processing unit 46 may encode the current block using various intra prediction modes, for example, during a separate encoding pass, and the intra prediction processing unit 46 (or, in some examples, the mode selection unit) may select an appropriate intra prediction mode to use from among the tested intra prediction modes. The intra prediction processing unit 46 may provide information indicating the selected intra prediction mode for the block to the entropy encoding unit 56. The entropy encoding unit 56 may encode the information indicating the selected intra prediction mode into the bitstream.

[0220] After the prediction processing unit 41 determines the predicted block of the current video block by inter prediction or intra prediction, the adder 50 forms a residual video block by subtracting the predicted block from the current video block. The residual video data in the residual block may be included in one or more TUs and is provided to the transform processing unit 52. The transform processing unit 52 transforms the residual video data into residual transform coefficients using a transform such as a discrete cosine transform (DCT) or a conceptually similar transform.

[0221] The conversion processing unit 52 may send the resulting conversion coefficients to the quantization unit 54. The quantization unit 54 quantizes the conversion coefficients to further reduce the bit rate. The quantization process may also reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting the quantization parameter. In some examples, the quantization unit 54 may then perform a scan of the matrix containing the quantized conversion coefficients. Alternatively, the entropy coding unit 56 may perform the scan.

[0222] Following quantization, the entropy coding unit 56 entropy-codes the quantized conversion coefficients into a video bitstream using, for example, context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy coding methodology or technique. The encoded bitstream is then sent to the video decoder 30 as shown in FIG. 13, or may be archived in the storage device 32 as shown in FIG. 13 for later transmission to or retrieval by the video decoder 30. The entropy coding unit 56 may also entropy-code the motion vectors and other syntax elements of the currently encoded video frame.

[0223] The inverse quantization unit 58 and the inverse transform processing unit 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual video block in the pixel domain in order to generate a reference block for prediction of other video blocks. As described above, the motion compensation unit 44 may generate a motion-compensated prediction block from one or more reference blocks of the frames stored in the DPB 64. The motion compensation unit 44 may also apply one or more interpolation filters to the prediction block to calculate sub-pixel values for use in motion estimation.

[0224] The adder 62 may add the reconstructed residual block to the motion-compensated prediction block created by the motion compensation unit 44 to create a reference block for storage in the DPB 64. The reference block may then be used as a prediction block for inter-predicting another video block in a subsequent video frame by the intra BC unit 48, the motion estimation unit 42, and the motion compensation unit 44.

[0225] FIG. 15 is a block diagram showing an exemplary video decoder 30 according to some implementations of the present application. The video decoder 30 includes a video data memory 79, an entropy decoding unit 80, a prediction processing unit 81, an inverse quantization unit 86, an inverse transform processing unit 88, an adder 90, and a DPB 92. The prediction processing unit 81 further includes a motion compensation unit 82, an intra prediction unit 84, and an intra BC unit 85. The video decoder 30 may perform a decoding process that is substantially inverse to the encoding process described above with respect to the video encoder 20 in relation to FIG. 14. For example, the motion compensation unit 82 may generate prediction data based on the motion vectors received from the entropy decoding unit 80, while the intra prediction unit 84 may generate prediction data based on the intra prediction mode indicator received from the entropy decoding unit 80.

[0226] In some examples, tasks for executing the implementation forms of this application may be assigned to units of the video decoder 30. Also, in some examples, the implementation forms of this disclosure may be divided into one or more of the units of the video decoder 30. For example, the intra BC unit 85 may execute the implementation forms of this application alone or in combination with other units of the video decoder 30, such as the motion compensation unit 82, the intra prediction unit 84, and the entropy decoding unit 80. In some examples, the video decoder 30 may not include the intra BC unit 85, and the functions of the intra BC unit 85 may be executed by other components of the prediction processing unit 81, such as the motion compensation unit 82.

[0227] The video data memory 79 may store video data such as an encoded video bitstream that is decoded by other components of the video decoder 30. The video data stored in the video data memory 79 may be obtained, for example, from the storage device 32, from a local video source such as a camera, via wired network communication or wireless network communication of video data, or by accessing a physical data storage medium (e.g., a flash drive or a hard disk). The video data memory 79 may include a coded picture buffer (CPB) that stores encoded video data from the encoded video bitstream. The DPB 92 of the video decoder 30 stores reference video data for use when decoding video data by the video decoder 30 (e.g., in an intra prediction coding mode or an inter prediction coding mode). The video data memory 79 and the DPB 92 may be formed by any of various memory devices such as dynamic random access memory (DRAM) including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. In FIG. 15, for illustration purposes, the video data memory 79 and the DPB 92 are depicted as two separate components of the video decoder 30. However, it will be apparent to those skilled in the art that the video data memory 79 and the DPB 92 may be provided by the same memory device or separate memory devices. In some examples, the video data memory 79 may be on-chip with or off-chip from other components of the video decoder 30.

[0228] During the decoding process, video decoder 30 receives an encoded video bitstream representing video blocks of an encoded video frame and associated syntax elements. Video decoder 30 may receive syntax elements at the video frame level and / or at the video block level. The entropy decoding unit 80 of video decoder 30 entropy decodes the bitstream to generate quantized coefficients, motion vectors or intra prediction mode indicators, and other syntax elements. Next, the entropy decoding unit 80 transfers the motion vectors or intra prediction mode indicators and other syntax elements to the prediction processing unit 81.

[0229] When a video frame is encoded as an intra prediction encoded (I) frame or for an intra encoded prediction block in another type of frame, the intra prediction unit 84 of the prediction processing unit 81 may generate prediction data for a video block of the current video frame based on the signaled intra prediction mode and reference data from previously decoded blocks of the current frame.

[0230] When a video frame is encoded as an inter prediction encoded (i.e., B or P) frame, the motion compensation unit 82 of the prediction processing unit 81 may generate one or more prediction blocks for a video block of the current video frame based on the motion vectors and other syntax elements received from the entropy decoding unit 80. Each of the prediction blocks may be created from a reference frame in one of the reference frame lists. Video decoder 30 may construct list 0 and list 1, which are the reference frame lists, using a default construction technique based on the reference frames stored in DPB 92.

[0231] In some examples, when a video block is encoded according to the intra BC mode described herein, the intra BC unit 85 of the prediction processing unit 81 creates a prediction block of the current video block based on the block vector and other syntax elements received from the entropy decoding unit 80. The prediction block may be within the reconstructed area of the same picture as the current video block defined by the video encoder 20.

[0232] The motion compensation unit 82 and / or the intra BC unit 85 determine prediction information about the video blocks of the current video frame by analyzing the motion vectors and other syntax elements, and then use the prediction information to create a prediction block of the currently decoded video block. For example, the motion compensation unit 82 uses some of the received syntax elements to determine a prediction mode (e.g., intra prediction or inter prediction) used to encode the video blocks of the video frame, an inter prediction frame type (e.g., B or P), construction information about one or more of the reference frame lists of the frame, the motion vectors of each inter prediction encoded video block of the frame, the inter prediction status of each inter prediction encoded video block of the frame, and other information for decoding the video blocks within the current video frame.

[0233] Similarly, the intra BC unit 85 may determine, using some of the received syntax elements, such as a flag, that the current video block is predicted using the intra BC mode, construction information about which video blocks of the frame are within the reconstructed area and which video blocks should be stored in the DPB 92, the block vectors of each intra BC predicted video block of the frame, the intra BC prediction status of each intra BC predicted video block of the frame, and other information for decoding the video blocks within the current video frame.

[0234] The motion compensation unit 82 may also perform interpolation using an interpolation filter used by the video encoder 20 during the encoding of video blocks, and calculate interpolation values for sub-integer pixels of the reference blocks. In this case, the motion compensation unit 82 may determine the interpolation filter used by the video encoder 20 from the received syntax elements, and create a prediction block using the interpolation filter.

[0235] The inverse quantization unit 86 inverse quantizes the quantized transform coefficients provided in the bitstream and entropy decoded by the entropy decoding unit 80, using the same quantization parameter calculated by the video encoder 20 for each video block in the video frame to determine the degree of quantization. The inverse transform processing unit 88 applies an inverse transform, such as an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients to reconstruct the residual block in the pixel domain.

[0236] After the motion compensation unit 82 or the intra BC unit 85 generates a prediction block for the current video block based on vectors and other syntax elements, the adder 90 reconstructs the decoded video block of the current video block by adding the residual block from the inverse transform processing unit 88 and the corresponding prediction block generated by the motion compensation unit 82 and the intra BC unit 85. To further process the decoded video block, a loop filter 91, such as a deblocking filter, an SAO filter, and / or an ALF, may be arranged between the adder 90 and the DPB 92. In some examples, the loop filter 91 may be omitted, and the decoded video block may be directly provided to the DPB 92 by the adder 90. Then, the decoded video blocks within a given frame are stored in the DPB 92 that stores the reference frames used for subsequent motion compensation of the next video block. Also, the DPB 92, or a memory device separate from the DPB 92, may store the decoded video for later presentation on a display device, such as the display device 34 of FIG. 13.

[0237] The description of the present disclosure is presented for purposes of illustration and is not intended to be exhaustive or to limit the present disclosure. Many modifications, variations, and alternative implementations will be apparent to those skilled in the art who benefit from the teachings presented in the foregoing description and the associated drawings.

[0238] The examples are selected and described in order to explain the principles of the present disclosure and to enable those skilled in the art to understand the present disclosure with respect to various embodiments, and to make the most of the underlying principles and various implementations by making various modifications suitable for the particular applications contemplated. Accordingly, it is to be understood that the scope of the present disclosure is not limited to the specific examples of the disclosed implementations, and that modifications and other implementations are intended to be included within the scope of the present disclosure.

Claims

1. 1. A method for video decoding, comprising: determining, by a decoder, a coding bit depth of at least one sample in the bitstream; determining, by the decoder, a value of a first sequence parameter set (SPS) flag for the at least one sample; determining, by the decoder, a second SPS flag for the at least one sample based on the value of the first SPS flag in combination with a coded bit depth of the at least one sample; A method comprising:

2. determining the second SPS flag for the at least one sample based on the value of the first SPS flag in combination with the coding bit depth of the at least one sample; determining the presence of the second SPS flag based on the first SPS flag; or determining a value of the second SPS flag based on the coding bit depth; 10. The method for video decoding of claim 1, comprising at least one of:

3. determining the second SPS flag for the at least one sample based on the value of the first SPS flag in combination with the coding bit depth of the at least one sample; 2. The method for video decoding of claim 1, comprising: determining the presence of the second SPS flag based on the first SPS flag and the coded bit depth.

4. determining the second SPS flag for the at least one sample based on the value of the first SPS flag in combination with the coding bit depth of the at least one sample; 2. The method for video decoding of claim 1, comprising: determining a value of the second SPS flag based on the first SPS flag and the coded bit depth.

5. 2. The method for video decoding of claim 1, further comprising: determining, in response to determining that the coded bit depth value is greater than 10, that the value of the second SPS flag is equal to 1.

6. The method for video decoding according to claim 1, further comprising determining that there is a SH transform skip residual coding Rice index in a slice header (SH) syntax structure that references the SPS in response to a determination that the value of the second SPS flag is equal to 1.

7. The method for video decoding according to claim 1, further comprising determining that the value of the second SPS flag is equal to 0 in response to a determination that the value of the encoded bit depth is 10 or less.

8. The method for video decoding according to claim 1, further comprising determining that the second SPS flag is signaled in response to a determination that the value of the first SPS flag is equal to 1 and the encoded bit depth is greater than 10.

9. Determining the second SPS flag for the at least one sample based on the combined encoded bit depth of the at least one sample and the value of the first SPS flag, Determining the value of the second SPS flag based on the encoded bit depth, regardless of the value of the first SPS flag, the method for video decoding according to claim 1.

10. An apparatus for video decoding, comprising: One or more processors; A memory configured to store instructions executable by the one or more processors, and the apparatus, Wherein the one or more processors are configured to execute the method according to any one of claims 1 to 9 when executing the instructions.

11. A non-transitory computer-readable storage medium for video decoding, storing computer-executable instructions that cause one or more computer processors to execute the method according to any one of claims 1 to 9 when executed by the one or more computer processors.

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