Substrate inspection device

Abstract

To further improve the accuracy of defect detection in defect inspection based on a captured image of a substrate to be inspected.SOLUTION: A substrate inspection device for inspecting a substrate includes: an acquisition unit that acquires an estimated image of a substrate to be inspected after processing by a substrate processing device on the basis of an image estimating model created by machine learning using captured images before and after processing by the substrate processing device for each of a plurality of substrates, and a captured image of the substrate to be inspected before processing by the substrate processing device; and a determination unit that determines whether or not there is a defect in the substrate to be inspected on the basis of the captured image of the substrate to be inspected after processing by the substrate processing device and the estimated image.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a substrate inspection apparatus.

Background Art

[0002] Patent Document 1 discloses an inspection method for a wafer in a substrate processing system including a plurality of processing apparatuses that perform processing on the wafer. In this inspection method, the surface of the wafer before being processed by the processing apparatus is imaged to obtain a first substrate image, and feature amounts are extracted from the first substrate image. Next, a reference image corresponding to the feature amount extracted from the first substrate image is selected from a storage unit in which a plurality of reference images serving as criteria for defect inspection and set corresponding to feature amounts in different ranges are stored. Then, the surface of the substrate after being processed by the processing apparatus is imaged to obtain a second substrate image, and the presence or absence of defects on the wafer is determined based on the selected reference image and the second substrate image.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technology according to the present disclosure further improves the defect detection accuracy in defect inspection based on a captured image of a substrate to be inspected.

Means for Solving the Problems

[0005] One aspect of the present disclosure is a substrate inspection apparatus for inspecting a substrate, including an image estimation model created by machine learning using pre - processing captured images and post - processing captured images by a substrate processing apparatus for each of a plurality of substrates, and a captured image of a substrate to be inspected before processing by the substrate processing apparatus, and an acquisition unit that acquires an estimated image of the substrate to be inspected after processing by the substrate processing apparatus based on these, and a determination unit that determines whether there is a defect in the substrate to be inspected based on the captured image of the substrate to be inspected after processing by the substrate processing apparatus and the estimated image.

Advantages of the Invention

[0006] According to the present disclosure, it is possible to further improve the defect detection accuracy in defect inspection based on a captured image of a substrate to be inspected.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] In the manufacturing process of semiconductor devices and the like, a resist coating process of applying a resist solution onto a semiconductor wafer (hereinafter referred to as "wafer") to form a resist film, an exposure process of exposing the resist film, a development process of developing the exposed resist film, etc. are sequentially performed, and a resist pattern is formed on the wafer. Then, after the formation process of the resist pattern, etching of the etching target layer using this resist pattern as a mask is performed, and a predetermined pattern is formed on the etching target layer. Note that when forming the resist pattern, a film other than the resist film may be formed under the resist film.

[0009] In addition, when forming a resist pattern as described above or when etching using a resist pattern, a defect inspection may be performed on the wafer after various processes. In this defect inspection, for example, whether the resist pattern is properly formed, whether there is adhesion of foreign matter to the wafer, etc. are inspected. In recent years, in this defect inspection, an imaging image obtained by imaging the surface of the wafer to be inspected after processing may be used. In this case, the defect inspection is performed by comparing the imaging image of the wafer to be inspected with a reference image serving as a reference for the inspection.

[0010] However, the imaging image of the wafer to be inspected after processing is affected by the state of the surface of the wafer to be inspected before processing, that is, the state of the underlying surface of the wafer to be inspected, etc., and unevenness occurs. Further, since the processing environment is non-uniform among wafers, the state of the above-mentioned unevenness varies from wafer to wafer. For example, even if a resist film is normally formed on the antireflection film of the wafer under the same processing conditions, the unevenness occurring in the imaging image of the wafer after the resist film formation varies from wafer to wafer. It is necessary to prevent this unevenness from being misjudged as a defect.

[0011] Patent Document 1 discloses selecting a substrate image corresponding to a feature amount extracted from a first substrate image obtained by imaging the surface of a wafer before processing, from a plurality of substrate images that are set corresponding to feature amounts in different ranges and stored in a storage unit and serve as inspection criteria for a plurality of defects. In Patent Document 1, the presence or absence of defects on the wafer is determined based on the selected substrate image and a second substrate image obtained by imaging the surface of the substrate after processing.

[0012] In the case where there is such unevenness, higher defect detection accuracy may be required than in defect inspection using the substrate image selected as in Patent Document 1.

[0013] Therefore, the technology according to the present disclosure further improves the defect detection accuracy in defect inspection based on an imaging image obtained by imaging a substrate to be inspected.

[0014] Hereinafter, a substrate inspection apparatus, a substrate inspection system, and a substrate inspection method according to the present embodiment will be described with reference to the drawings. In the present specification and the drawings, elements having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

[0015] FIG. 1 is a diagram schematically showing an outline of the configuration of a substrate inspection system according to the present embodiment. As shown in the drawing, the substrate inspection system 1 includes a plurality of substrate processing systems 10 and an overall control device 20. Note that the number of substrate processing systems 10 included in the substrate inspection system 1 may be one.

[0016] Each substrate processing system 10 processes a wafer as a substrate. In this example, processing such as forming a resist pattern on the wafer is performed on the wafer.

[0017] FIG. 2 is a plan view schematically showing an outline of the configuration of each substrate processing system 10. FIGS. 3 and 4 are a front view and a rear view, respectively, schematically showing an outline of the internal configuration of each substrate processing system 10.

[0018] As shown in FIG. 2, each substrate processing system 10 includes a cassette station 100 where a cassette C containing a plurality of wafers W is loaded and unloaded, and a processing station 101 having a plurality of processing apparatuses for performing predetermined processes on the wafers W. Each substrate processing system 10 has a configuration in which an interface station 103 for transferring the wafer W between the cassette station 100, the processing station 101, and an exposure apparatus 102 adjacent to the processing station 101 is integrally connected.

[0019] The cassette station 100 is provided with a cassette mounting table 110. The cassette mounting table 110 is provided with a plurality of cassette mounting plates 111 for mounting the cassette C when loading and unloading the cassette C to and from the outside of the substrate processing system 10.

[0020] The cassette station 100 is provided with a wafer transfer apparatus 113 that is movable on a transfer path 112 extending in the X direction. The wafer transfer apparatus 113 is also movable in the vertical direction and around the vertical axis (θ direction), and can transfer the wafer W between the cassette C on each cassette mounting plate 111 and a transfer apparatus of a third block G3 of the processing station 101 described later.

[0021] The processing station 101 is provided with a plurality of, for example, four blocks, namely, a first block G1 to a fourth block G4, each equipped with various apparatuses. For example, the first block G1 is provided on the front side (the negative X direction side in FIG. 2) of the processing station 101, and the second block G2 is provided on the back side (the positive X direction side in FIG. 2, the upper side of the drawing) of the processing station 101. Further, the third block G3 is provided on the cassette station 100 side (the negative Y direction side in FIG. 2) of the processing station 101, and the fourth block G4 is provided on the interface station 103 side (the positive Y direction side in FIG. 2) of the processing station 101.

[0022] In the first block G1, liquid processing apparatuses for processing the wafer W using a processing liquid are arranged. Specifically, in the first block G1, as shown in FIG. 3, for example, a development processing apparatus 120, an underlayer film forming apparatus 121, an intermediate layer film forming apparatus 122, and a resist coating apparatus 123 are arranged in this order from the bottom.

[0023] The development processing apparatus 120 develops the wafer W. Specifically, the development processing apparatus 120 supplies a developing solution onto the resist film of the wafer W to form a resist pattern.

[0024] The underlayer film forming apparatus 121 forms an underlayer film, which is a base film for the resist film of the wafer W. Specifically, the underlayer film forming apparatus 121 applies an underlayer film material, which is a material for forming the underlayer film, onto the wafer W to form the underlayer film. The underlayer film is, for example, an SOC (spin-on carbon) film.

[0025] The intermediate layer film forming apparatus 122 forms an intermediate layer film at a position above the underlayer film of the wafer W and below the resist film. Specifically, the intermediate layer film forming apparatus 122 applies an intermediate layer film material, which is a material for forming the intermediate layer film, onto the underlayer film of the wafer W to form the intermediate layer film. The intermediate layer film is, for example, an SOG (spin-on glass) film.

[0026] The resist coating apparatus 123 applies a resist solution onto the wafer W to form a resist film. Specifically, the resist coating apparatus 123 applies the resist solution onto the intermediate layer film of the wafer W to form the resist film.

[0027] For example, three of each of the development processing apparatus 120, the underlayer film forming apparatus 121, the intermediate layer film forming apparatus 122, and the resist coating apparatus 123 are arranged side by side in the horizontal direction. Note that the number and arrangement of these development processing apparatus 120, underlayer film forming apparatus 121, intermediate layer film forming apparatus 122, and resist coating apparatus 123 can be arbitrarily selected.

[0028] In these developing processing apparatuses 120, lower layer film forming apparatuses 121, intermediate layer film forming apparatuses 122, and resist coating apparatuses 123, for example, a predetermined processing liquid is applied onto the wafer W by a spin coating method. In the spin coating method, for example, the processing liquid is discharged onto the wafer W from a coating nozzle, and at the same time, the wafer W is rotated to spread the processing liquid on the surface of the wafer W.

[0029] In the second block G2, heat treatment apparatuses 130, which are substrate processing apparatuses for performing heat treatment such as heating and cooling of the wafer W using a hot plate or a cooling plate on which the wafer W is placed, are provided side by side in the vertical direction and the horizontal direction. The number and arrangement of these heat treatment apparatuses 130 can be arbitrarily selected. Also, known apparatuses can be used for each of the heat treatment apparatuses 130.

[0030] In the third block G3, a plurality of transfer apparatuses 140, 141, 142, 143, 144 are provided in order from the bottom, and inspection imaging apparatuses 145, 146, 147 are provided in order from the bottom thereon. Also, in the fourth block G4, a plurality of transfer apparatuses 150, 151, 152 are provided in order from the bottom, and inspection imaging apparatuses 153, 154 are provided thereon.

[0031] Here, the configuration of the inspection imaging apparatus 145 will be described. FIG. 5 and FIG. 6 are a longitudinal sectional view and a transverse sectional view respectively showing the outline of the configuration of the inspection imaging apparatus 145. As shown in FIGS. 5 and 6, the inspection imaging apparatus 145 has a casing 200. Inside the casing 200, a mounting table 201 on which the wafer W is placed is provided. This mounting table 201 can be freely rotated and stopped by a rotation drive unit 202 such as a motor. On the bottom surface of the casing 200, a guide rail 203 extending from one end side (the negative X direction side in FIG. 6) to the other end side (the positive X direction side in FIG. 6) inside the casing 200 is provided. The mounting table 201 and the rotation drive unit 202 are provided on the guide rail 203 and can move along the guide rail 203 by a drive device 204.

[0032] On the side of the other end within the casing 200 (the positive X-direction side in FIG. 6), an imaging unit 210 is provided. For example, a wide-angle CCD camera is used for the imaging unit 210.

[0033] Near the center of the upper part of the casing 200, a half mirror 211 is provided. The half mirror 211 is provided at a position facing the imaging unit 210, with the mirror surface inclined 45 degrees upward in the direction of the imaging unit 210 from a state where it faces vertically downward. Above the half mirror 211, an illumination device 212 is provided. The half mirror 211 and the illumination device 212 are fixed to the upper surface inside the casing 200. The illumination from the illumination device 212 passes through the half mirror 211 and is directed downward. Therefore, the light reflected by an object below the illumination device 212 is further reflected by the half mirror 211 and captured by the imaging unit 210. That is, the imaging unit 210 can image an object in the irradiation area by the illumination device 212. And the imaging result by the imaging unit 210 is input to an imaging control device 251 described later.

[0034] Note that the configurations of the inspection imaging devices 146, 147, 153, and 154 are the same as the configuration of the above-described inspection imaging device 145.

[0035] Returning to the description of each substrate processing system 10 using FIGS. 2 to 4. As shown in FIG. 2, a wafer transfer area D is formed in the area surrounded by the first block G1 to the fourth block G4. In the wafer transfer area D, a plurality of wafer transfer devices 160 having a transfer arm 160a movable in, for example, the Y direction, X direction, θ direction, and vertical direction are arranged. The wafer transfer device 160 moves within the wafer transfer area D and can transfer the wafer W to a desired device within the surrounding first block G1, second block G2, third block G3, and fourth block G4.

[0036] Also, in the wafer transfer area D, as shown in FIG. 4, a shuttle transfer device 170 for linearly transferring the wafer W between the third block G3 and the fourth block G4 is provided.

[0037] The shuttle transfer device 170 is linearly movable, for example, in the Y direction in FIG. 4. The shuttle transfer device 170 moves in the Y direction while supporting the wafer W, and can transfer the wafer W between the transfer device 142 of the third block G3 and the transfer device 152 of the fourth block G4.

[0038] As shown in FIG. 2, a wafer transfer device 180 is provided adjacent to the positive X-direction side of the third block G3. The wafer transfer device 180 has a transfer arm 180a that is movable, for example, in the X direction, θ direction, and vertical direction. The wafer transfer device 180 moves vertically while supporting the wafer W, and can transfer the wafer W to each transfer device within the third block G3.

[0039] The interface station 103 is provided with a wafer transfer device 190 and a transfer device 191. The wafer transfer device 190 has a transfer arm 190a that is movable, for example, in the Y direction, θ direction, and vertical direction. The wafer transfer device 190 can support the wafer W on the transfer arm 190a, for example, and transfer the wafer W between each transfer device within the fourth block G4, the transfer device 191, and the exposure device 102.

[0040] Further, the substrate processing system 10 is provided with a transfer / process control device 250 and an imaging control device 251 as a substrate inspection device.

[0041] The transfer / process control device 250 (hereinafter sometimes referred to as the "main control device 250") is a computer equipped with, for example, a CPU, memory, etc., and has a program storage unit (not shown). A program for controlling the operations of the drive systems of the above-described various processing devices and transfer devices, etc., and performing various processes on the wafer W is stored in this program storage unit. Note that the above program may have been recorded on a computer-readable storage medium and installed from the storage medium into the main control device 250. Part or all of the program may be realized by dedicated hardware (circuit board).

[0042] Similar to the main control device 250, the imaging control device 251 is a computer equipped with, for example, a CPU, a memory, etc., and has a program storage unit (not shown). A program for controlling the operation of the imaging unit and the drive system of each inspection imaging device and controlling the processing related to the substrate inspection is stored in this program storage unit. Note that the above program may have been recorded on a computer-readable storage medium and installed in the imaging control device 251 from the storage medium. Part or all of the program may be realized by dedicated hardware (circuit board).

[0043] Return to the description of the substrate inspection system 1 using FIG. 1. As described above, the substrate inspection system 1 has the overall control device 20. The overall control device 20 is a computer equipped with, for example, a CPU, a memory, etc., and has a program storage unit (not shown). A program for creating the image estimation model described later is stored in this program storage unit. Note that the above program may have been recorded on a computer-readable storage medium and installed in the overall control device 20 from the storage medium. Part or all of the program may be realized by dedicated hardware (circuit board).

[0044] FIG. 7 is a block diagram schematically showing the outline of the configurations of the imaging control device 251 and the overall control device 20 related to the substrate inspection. As shown in the figure, the overall control device 20 has a storage unit 301 and a model creation unit 302.

[0045] The storage unit 301 stores various types of information. In this storage unit 301, the captured images of the wafer W obtained from the results of imaging the wafer W by the imaging unit 210 of the inspection imaging device in each substrate processing system 10 are stored. Hereinafter, for ease of understanding, unless otherwise specified, the captured images and the estimated images described later are assumed to be grayscale images. However, these images may be images of at least any one of the R component, G component, and B component. Each captured image is associated with identification information of the captured wafer W, identification information of the processing device used for processing the captured wafer W, and the like.

[0046] The model creation unit 302 uses the captured images before the desired processing in the substrate processing system 10 and the captured images after the above-mentioned desired processing (hereinafter sometimes referred to as the "set of captured images before and after processing in the substrate processing system 10") for each of the plurality of wafers W, and creates an image estimation model by machine learning. The image estimation model is a model that estimates the captured image of the inspection target wafer W after the desired processing in the substrate processing system 10 from the captured image of the inspection target wafer W before the desired processing in the substrate processing system 10. In other words, the image estimation model is a model that generates an estimated image of the inspection target wafer W after the above-mentioned processing from the captured image of the inspection target wafer W before the above-mentioned processing.

[0047] The machine learning used for creating the image estimation model is, for example, machine learning by a conditional adversarial generative network (Conditional GAN (Generative Adversarial Networks)), and more specifically, pix2pix. Also, the image estimation model is, for example, a generative network (Generator) that converts an input arbitrary image to generate a fake image in a conditional adversarial generative network or pix2pix.

[0048] In conditional adversarial generation networks and pix2pix, as neural networks, in addition to the above-mentioned generation network, a discriminator network is used. The discriminator network takes an arbitrary image and inputs either a real image corresponding to the arbitrary image or a fake image generated by the generation network based on the arbitrary image, and discriminates whether the image input together with the arbitrary image is a real image or a fake image. In machine learning using conditional adversarial generation networks and pix2pix, for the discriminator network, a discrimination method is learned so that the above-mentioned discrimination is accurately performed, and for the generation network, an image conversion method is learned so that a fake image is recognized as a real image in the discriminator network.

[0049] In the model creation unit 302, as an image set of the above-mentioned arbitrary image input to the discriminator network and the real image corresponding to the arbitrary image, an imaging image set before and after processing in the substrate processing system 10 is used. The image estimation model created by the model creation unit 302 is sent to the imaging control device 251 of the substrate processing system 10.

[0050] The imaging control device 251 includes a storage unit 311, an imaging image acquisition unit 312, an estimated image acquisition unit 313, and a determination unit 314.

[0051] The storage unit 311 stores various information. In this storage unit 311, for example, the image estimation model created by the model creation unit 302 of the overall control device 20 is stored.

[0052] The imaging image acquisition unit 312 acquires an imaging image of the wafer W based on the imaging results of the imaging units 210 of the inspection imaging devices 145, 146, 147, 153, and 154. Specifically, the imaging image acquisition unit 312 performs necessary image processing on the image captured by the imaging unit 210, thereby generating, as an imaging image of the wafer W, an image showing the state of the entire surface of the wafer W. This imaging image acquisition unit 312 acquires imaging images of the inspection target wafer W before and after the desired processing in the substrate processing system 10, and also acquires imaging images of the inspection target wafer W before and after the desired processing, which are used for creating the image estimation model.

[0053] Based on the imaging image of the inspection target wafer W before the desired processing in the substrate processing system 10 acquired by the imaging image acquisition unit 312 and the image estimation model stored in the storage unit 311, the estimated image acquisition unit 313 generates and acquires the estimated image of the inspection target wafer W after the desired processing. Note that the overall control device 20 may generate the estimated image of the inspection target wafer W after the desired processing using the image estimation model, and the estimated image acquisition unit 313 may acquire the generated estimated image.

[0054] Based on the imaging image of the inspection target wafer W after the desired processing in the substrate processing system 10 acquired by the imaging image acquisition unit 312, the determination unit 314 determines the presence or absence of defects on the inspection target wafer W. In particular, the determination unit 314 determines the presence or absence of defects on the inspection target wafer W based on the imaging image of the inspection target wafer W after the desired processing acquired by the imaging image acquisition unit 312 and the estimated image of the inspection target wafer W after the desired processing acquired by the estimated image acquisition unit 313. Specifically, the determination unit 314 compares the imaging image of the inspection target wafer W after the desired processing with the estimated image of the inspection target wafer W after the desired processing, and determines the presence or absence of defects on the inspection target wafer W based on the comparison result. More specifically, the determination unit 314 determines the presence or absence of defects on the inspection target wafer W based on the difference between the imaging image of the inspection target wafer W after the desired processing and the estimated image of the inspection target wafer W after the desired processing.

[0055] Next, a method for processing the wafer W and a method for inspecting the wafer W performed by each substrate processing system 10 configured as described above will be described. In the following description, the wafer W is imaged at three or more timings. However, the defect inspection based on the captured image of the wafer W is performed only on the captured image of the wafer W after the resist pattern is formed. Further, prior to the following processing of the wafer W and inspection of the wafer W, it is assumed that the machine learning of the image estimation model for the wafer W after the resist pattern is formed, which is used for the above defect inspection, is completed. The image estimation model is created, for example, based on the captured image of the wafer W after the resist film is formed (that is, before the resist pattern is formed) and the wafer W after the resist pattern is formed in each substrate processing system 10.

[0056] First, a cassette C containing a plurality of wafers W is carried into the cassette station 100. Then, under the control of the main control device 250, the wafer W in the cassette C is transported to the inspection imaging device 145 of the third block G3. Then, under the control of the imaging control device 251, imaging of the wafer W in the initial state, that is, before forming various films such as the lower layer film, is performed by the imaging unit 210 of the wafer W, and the imaging image of the wafer W in the initial state is acquired by the imaging image acquisition unit 312.

[0057] Next, under the control of the main control device 250, the wafer W is transported to the lower layer film forming device 121 of the first block G1, and a lower layer film is formed on the wafer W. Subsequently, the wafer W is transported to the heat treatment device 130 for the lower layer film of the second block G2, and the heat treatment of the lower layer film is performed. Thereafter, the wafer W is transported to the inspection imaging device 153. Then, under the control of the imaging control device 251, imaging of the wafer W after the lower layer film is formed is performed by the imaging unit 210, and the imaging image of the wafer W after the lower layer film is formed is acquired.

[0058] Next, under the control of the main control device 250, the wafer W is transported to the intermediate layer film forming device 122 of the first block G1, and an intermediate layer film is formed on the lower layer film of the wafer W. Subsequently, the wafer W is transported to the heat treatment apparatus 130 for the intermediate layer in the second block G2, and the heat treatment of the intermediate layer film is performed. Thereafter, the wafer W is transported to the imaging apparatus 146 for inspection. Then, under the control of the imaging control apparatus 251, the wafer W after the formation of the intermediate layer film is imaged by the imaging unit 210, and the imaging image acquisition unit 312 acquires the imaging image of the wafer W after the formation of the intermediate layer film.

[0059] Next, under the control of the main control apparatus 250, the wafer W is transported to the resist coating apparatus 123 in the first block G1, and a resist film is formed on the intermediate layer film of the wafer W. Subsequently, the wafer W is transported to the heat treatment apparatus 130 for PAB treatment in the second block G2, and the PAB treatment is performed. Thereafter, the wafer W is transported to the imaging apparatus 153 for inspection. Then, under the control of the imaging control apparatus 251, the wafer W after the formation of the resist film is imaged by the imaging unit 210, and the imaging image acquisition unit 312 acquires the imaging image of the wafer W after the formation of the resist film.

[0060] Next, the wafer W is transported to the exposure apparatus 102 under the control of the main control apparatus 250 and exposed to a desired pattern. Subsequently, the wafer W is transported to the heat treatment apparatus 130 for PEB treatment in the second block G2, and the PEB treatment is performed. Next, the wafer is transported to the development processing apparatus 120 in the first block G1, and the development process is performed, and a resist pattern is formed on the wafer W. Thereafter, the wafer W is transported to the imaging apparatus 147 for inspection. Then, under the control of the imaging control apparatus 251, the wafer W after the formation of the resist pattern is imaged by the imaging unit, and the imaging image acquisition unit 312 acquires the imaging image of the wafer W after the formation of the resist pattern.

[0061] Next, based on the captured image of the wafer W after the resist pattern is formed, which is acquired by the imaging image acquisition unit 312, the presence or absence of defects in the wafer after the resist pattern is formed is determined. Specifically, based on the captured image of the wafer W after the resist film is formed (i.e., before the resist pattern is formed) and the image estimation model for the wafer W after the resist pattern is formed, which is created in advance, the estimated image of the wafer W after the resist pattern is formed is generated by the estimated image acquisition unit 313. Then, based on the captured image of the wafer W after the resist pattern is formed and the above-mentioned estimated image, the determination unit 314 determines the presence or absence of defects in the wafer W after the resist pattern is formed (i.e., the wafer W to be inspected). In this determination of the presence or absence of defects, for example, for the wafer W after the resist pattern is formed, the captured image and the estimated image are compared. A portion where the difference in pixel values between the two images is greater than or equal to a threshold value is determined as a portion where a defect exists, and the other portions are determined as portions without defects.

[0062] Note that when making the above determination, if the creation of the image estimation model for the wafer W after the resist pattern is formed is not completed, the presence or absence of defects in the wafer W is determined in the same manner as in the prior art. Also, if the creation of the above-mentioned estimation model is not completed, the captured image after the resist film is formed and the captured image after the resist pattern is formed for the wafer W are input to the model creation unit 302 of the overall control device 20, and the machine learning of the above-mentioned model is advanced.

[0063] When the above determination is completed, that is, when the defect inspection is completed, the wafer W is returned to the cassette C under the control of the main control device 250, and the processing for the wafer W is completed. Then, the above-mentioned processing is also performed for other wafers W.

[0064] As described above, in the present embodiment, an image estimation model created by machine learning is used, which uses the captured images of each of the plurality of wafers W before the desired processing in the substrate processing system 10 and the captured images after the above-mentioned desired processing. This image estimation model is a model that creates an estimated image of the wafer W after the desired processing from the captured image of the wafer W before the desired processing in the substrate processing system 10. In the present embodiment, an estimated image of the inspection target wafer W after the desired processing is generated and acquired based on the above-mentioned image estimation model and the captured image of the inspection target wafer W before the desired processing. Then, based on the captured image actually acquired for the inspection target wafer W after the desired processing and the above-mentioned estimated image, it is determined whether there are defects in the inspection target wafer W. That is, for each inspection target wafer W, it is determined whether there are defects in the inspection target wafer based on a reference image that serves as a reference for defect inspection. Therefore, the defect detection accuracy can be improved. Specifically, since the reference image that serves as the reference for defect inspection is the estimated image generated based on the above-mentioned image estimation model, the unevenness between the captured image and the estimated image, that is, the reference image, for the inspection target wafer W after the desired processing becomes substantially the same. Therefore, since the possibility that the unevenness is detected as a defect is low, the defect detection accuracy can be improved. That is, when comparing the captured image and the estimated image for the inspection target wafer W after the desired processing as described above when determining whether there are defects, there is no possibility of erroneously detecting the unevenness as a defect, so the above-mentioned threshold value can be made smaller. Therefore, it is possible to detect defects that cannot be detected when the threshold value is large.

[0065] With reference to FIGS. 8 and 9, the effect of the defect inspection according to the present embodiment will be described more specifically. FIG. 8 is a conceptual diagram for explaining an example of a conventional defect inspection, and FIG. 9 is a conceptual diagram for explaining an example of the defect inspection according to the present embodiment. In FIGS. 8 and 9, the horizontal axis indicates the coordinates of each part along a certain direction on the wafer in that direction, and the vertical axis indicates values such as pixel values of each part. In FIG. 8(A), an example of the relationship between the captured image Ip of the wafer W to be inspected and the average image Ia described later is shown. In FIG. 8(B), the difference between the captured image Ip of the wafer W to be inspected and the average image Ia described later is shown. In FIG. 8(C), an example of a defect determination value Vc described later for the conventional defect inspection is shown. In FIG. 9(A), an example of the relationship between the captured image Ip of the wafer W to be inspected and the corresponding estimated image Ie is shown. In FIG. 9(B), an example of a defect determination value V according to the present embodiment is shown.

[0066] In the conventional defect inspection, for example, for a plurality of wafers W after a desired process, captured images are acquired, and an average image Ia and a standard deviation image Is are acquired from the captured images of the plurality of wafers W. The average image Ia is an image in which the average value of each pixel in the captured images of the plurality of wafers W is used as the pixel value of each pixel. For example, it has a relationship with the captured image Ip of the wafer W to be inspected as shown in FIG. 8(A). The standard deviation image Is is an image in which the standard deviation of each pixel in the captured images of the plurality of wafers W is used as the pixel value of each pixel.

[0067] Then, in the conventional defect inspection, the difference between the captured image Ip of the wafer W to be inspected and the average image Ia is calculated. In the part having a significant value in the difference, as shown in FIG. 8(B), not only the defective part but also the part caused by non-uniformity is included. Therefore, the standard deviation image Is is applied as a variation filter for removing non-uniformity, and a defect determination value Vc is generated. Specifically, for each pixel in which the absolute value of the pixel value of the difference exceeds the absolute value of the pixel value of the standard deviation image Is, the pixel value of the standard deviation image Is is subtracted from the pixel value of the difference for each pixel, and a defect determination value Vc as shown in FIG. 8(C) is generated. In the conventional defect inspection, in this defect determination value, the part exceeding the threshold value Tc is determined as a defect. However, the standard deviation image Is as the variation filter for removing non-uniformity is not unique to each wafer W and does not accurately represent non-uniformity. Therefore, as shown in FIG. 8(C), in the portion having a significant value in the defect determination value, not only the portions caused by the defects K1, K2, and K3 but also the portions caused by the non-uniformity U are included. In order to prevent this non-uniformity U portion from being detected as a defect, in the conventional defect inspection method, the threshold value Tc for the defect determination value is set large. That is, the detection sensitivity is set low. Therefore, only the defects K1 and K2 showing large values in the defect determination value Vc are detected, and the defect K3 to be detected, which shows a small value in the defect determination value Vc, may not be detected.

[0068] On the other hand, in the present embodiment, the captured image Ip of the inspection target wafer W after the desired process and the estimated image Ie serving as the reference image for defect inspection are in a relationship as shown in FIG. 9(A), for example. Then, for example, the difference at each pixel between the captured image Ip of the inspection target wafer W after the desired process and the estimated image Ie is taken as the defect determination value V, and in this defect determination value V, the portion exceeding the threshold value T is determined as a defect. The estimated image Ie used for defect determination in the present embodiment is created based on the image estimation model created by machine learning as described above, is unique to each wafer W, and reflects the state of the inspection target wafer W before the desired process. Therefore, in the captured image Ip and the estimated image Ie of the inspection target wafer W after the desired process, the non-uniformity is substantially the same. As shown in FIG. 9(B), in the portion showing a significant value in the defect determination value V, the portion caused by non-uniformity is not included, and only the portions caused by the defects K1, K2, and K3 are included. Therefore, even if the threshold value T for the defect determination value V is reduced, the non-uniformity portion is not detected as a defect. Therefore, the threshold value T is set small, that is, the detection sensitivity is set high, and the defect K3 showing a small value in the defect determination value V can also be accurately detected.

[0069] The inventors actually created an image estimation model by machine learning using the captured image of the wafer W after resist film formation and the captured image of the wafer W after resist pattern formation. Then, from the captured image of the inspection target wafer W after resist film formation and the created image estimation model, an estimated image of the inspection target wafer W after resist pattern formation was generated and compared with the actual captured image of the inspection target wafer W after resist pattern formation. The results are shown in FIGS. 10 and 11. FIGS. 10 and 11 are diagrams showing the relationship between the pixel values of the actual captured image and the pixel values of the estimated image for each part of the image. FIG. 10 shows the whole wafer, and FIG. 11 shows only the central part of the wafer. As shown in FIGS. 10 and 11, in each part of the image, the pixel values of the actual captured image and the pixel values of the estimated image showed close values. In particular, as shown in FIG. 11, at the central part of the wafer, the pixel values of the actual captured image and the pixel values of the estimated image were substantially the same. Note that FIGS. 10 and 11 show the pixel values of the R component, but the inventors have confirmed that the G component and the B component also show the same tendency as the R component.

[0070] In the above description, an image estimation model for the inspection target wafer W after resist pattern formation was created based on the captured image of the wafer W after resist film formation and the captured image of the wafer W after resist pattern formation. Instead of this, an image estimation model for the inspection target wafer W after resist pattern formation may be created based on the captured image of the wafer W in the initial state before lower layer film formation and the captured image of the wafer W after resist pattern formation. Then, based on the image estimation model and the captured image of the inspection target wafer W in the above initial state, an estimated image of the inspection target wafer W after resist pattern formation is estimated, and based on this estimated image, a defect inspection of the inspection target wafer W after resist pattern formation may be performed.

[0071] The inventors actually created an image estimation model by machine learning using the captured image of the wafer W in the above initial state and the captured image of the wafer W after resist pattern formation. Then, from the captured image of the inspection target wafer W in the above initial state and the created image estimation model, an estimated image after resist pattern formation of the inspection target wafer W was generated and compared with the actual captured image of the inspection target wafer W after resist pattern formation. The results are shown in FIGS. 12 and 13. FIGS. 12 and 13 are diagrams showing the relationship between the pixel values of the actual captured image and the pixel values of the estimated image for each part of the image. FIG. 12 shows the whole wafer, and FIG. 13 shows only the central part of the wafer. As shown in FIGS. 12 and 13, in each part of the image, the pixel values of the actual captured image and the pixel values of the estimated image showed close values. In particular, as shown in FIG. 13, at the central part of the wafer, the pixel values of the actual captured image and the pixel values of the estimated image were substantially the same. Note that FIGS. 12 and 13 are for the pixel values of the R component, but the inventors have confirmed that the G component and the B component also show the same tendency as the R component.

[0072] Further, an image estimation model for the inspection target wafer W after resist pattern formation may be created based on the captured image of the wafer W after lower layer film formation, the captured image of the wafer W after intermediate layer film formation, and the captured image of the wafer W after resist pattern formation. Then, based on the image estimation model, the captured image of the inspection target wafer W after lower layer film formation, and the wafer after intermediate layer film formation, an estimated image of the inspection target wafer W after resist pattern formation is estimated, and based on this estimated image, a defect inspection of the inspection target wafer W after resist pattern formation may be performed. That is, when n types of processes are performed and captured images of the inspection target wafer W are acquired before and after each type of process, for defect inspection and generation of an image estimation model for the inspection target wafer W after the m (m ≤ n)-th process, the following captured images may be used. That is, not only the captured image of the wafer W immediately before the m-th process (in other words, after the (m - 1)-th process), but also the captured image of the wafer W immediately before the (m - 1)-th process (in other words, after the (m - 2)-th process) may be used.

[0073] Furthermore, in the present embodiment, based on the results of FIGS. 11 and 13, defect inspection may be performed based on only the image of the center portion of the wafer in the captured image and the estimated image of the inspection target wafer W after the desired process in the substrate processing system 10. Thereby, the possibility of erroneously detecting non-uniformity as a defect can be further reduced, and defect detection can be performed more accurately. In this case, for example, an edge filter that excludes the peripheral portion of the wafer W is applied during defect inspection.

[0074] Note that, for the image estimation model, for example, a common one among the substrate processing systems is created using the captured images acquired by the plurality of substrate processing systems 10 included in the substrate inspection system 1. Alternatively, the image estimation model for a certain substrate processing system 10 may be created using only the captured images acquired by the substrate processing system. Thereby, an image estimation model reflecting the characteristics of the substrate processing system 10 can be created.

[0075] Further, from the captured images of the wafer W used for creating the image estimation model, the captured images of the wafer W determined to have defects in the defect inspection may be removed. Thereby, a more accurate image estimation model can be created.

[0076] Note that in the substrate processing system 10, a plurality of types of film formation processes (including the resist pattern formation process after the resist film formation process) are performed, but the substrate inspection method according to the present embodiment can also be applied when performing a single film formation process. Further, the substrate inspection method according to the present embodiment can also be applied when performing processes other than the film formation process (for example, etching process, etc.).

[0077] FIG. 14 is a block diagram showing an outline of another example of the overall control device, and shows a configuration related to substrate inspection. The overall control device 20a in FIG. 14 has a storage unit 301 and a model creation unit 302, similar to the overall control device 20 in FIG. 7. And the overall control device 20a further has a selection unit 400 that selects a plurality of captured image sets used for creating the image estimation model in the model creation unit 302, that is, the captured image sets for model creation, from among a large number of captured image sets. Note that the captured image set is an image set composed of a combination of a captured image before processing by the substrate processing system 10 and a captured image after processing for a certain wafer W.

[0078] The selection unit 400 determines the degree of abnormality for each captured image set, and selects the captured image set for model creation based on the degree of abnormality. The degree of abnormality is determined using the in-plane tendency of the pixel values in the captured image of the wafer W before the desired processing in the substrate processing system 10 (hereinafter sometimes referred to as "IN image") and the in-plane tendency of the pixel values in the captured image of the wafer W after processing in the substrate processing system 10 (hereinafter sometimes referred to as "OUT image").

[0079] The selection unit 400 has, for example, a candidate acquisition unit 401, a coefficient calculation unit 402, a distance calculation unit 403, and an extraction unit 404.

[0080] The candidate acquisition unit 401 acquires a plurality of imaging image sets from the storage unit 301 as candidates for the imaging image set for model creation.

[0081] For each imaging image of the wafer W included in the imaging image set acquired by the candidate acquisition unit 401, the coefficient calculation unit 402 decomposes the planar distribution of the pixel values in the imaging image into in-plane tendency components of a plurality of pixel values respectively using Zernike polynomials, and calculates the Zernike coefficients of each in-plane tendency component respectively.

[0082] Note that the imaging image of the wafer W is generally composed of three primary colors of RGB (Red, Green, Blue). Therefore, the in-plane tendency component Zi of the pixel values can be obtained for each of the primary colors R, G, and B, but there is no difference in the image processing methods among R, G, and B. Therefore, hereinafter, unless otherwise specified, it is assumed that the processing is performed in parallel for all the primary colors R, G, and B.

[0083] In the coefficient calculation unit 402, for each imaging image of the wafer W included in the imaging image set acquired by the candidate acquisition unit 401, first, the color of the imaging image is quantified as pixel values, for example, in pixel units over the entire surface of the wafer W. Thereby, the planar distribution of the pixel values in the wafer plane is obtained. Then, in the coefficient calculation unit 402, this planar distribution of the pixel values in the wafer plane is decomposed into in-plane tendency components Zi (i is an integer of 1 or more) of a plurality of pixel values. As shown in FIG. 15, these in-plane tendency components Zi of the plurality of pixel values are represented by decomposing the planar distribution Z of the pixel values in the wafer plane into a plurality of components using Zernike polynomials.

[0084] Here, the Zernike polynomial will be described. The Zernike polynomial is a complex function mainly used in the optical field and has two degrees (n, m). It is also a function on a unit circle with a radius of 1 and has polar coordinate arguments (r, θ). In the optical field, this Zernike polynomial is used, for example, to analyze the aberration components of a lens, and by decomposing the wavefront aberration using the Zernike polynomial, it is possible to know the aberration components based on independent wavefronts, for example, shapes such as mountain type and saddle type.

[0085] Next, regarding how to obtain the in-plane tendency component Zi of the pixel value using the Zernike polynomial in this embodiment, it will be described with reference to FIGS. 16 and 17. FIG. 16 shows the planar distribution Z of the pixel values of each pixel P in the plane of the wafer W, and the numerical values described inside each pixel P indicate the pixel values of the pixel P. For ease of explanation, in FIGS. 16 and 17, only a row of pixels P along the X-axis direction is described. When applying the Zernike polynomial to the planar distribution Z of the pixel values shown in FIG. 16, for example, as shown in FIG. 17, the pixel values of each pixel P are represented in the height direction (the positive Z direction in FIG. 17) on the wafer W surface. As a result, the planar distribution of the pixel values of each pixel P can be regarded as a curve of a predetermined shape drawn in three dimensions. Then, for the pixel values of all the pixels P in the plane of the wafer W, by similarly representing them in the height direction on the wafer W surface, the distribution of the pixel values in the plane of the wafer W can be regarded as a three-dimensional circular wave surface. By regarding it as such a three-dimensional wave surface, the Zernike polynomial can be applied, and the planar distribution Z of the pixel values in the wafer plane can be decomposed into in-plane tendency components Zi of a plurality of pixel values, such as inclination components in the up, down, left, and right directions in the wafer plane, and curvature components that curve convexly or concavely, using the Zernike polynomial. The magnitude of each in-plane tendency component Zi of the pixel value can be represented by the Zernike coefficient.

[0086] The Zernike coefficient representing the in-plane tendency component Zi of the pixel value can be specifically represented using the arguments (r, θ) of polar coordinates and the degree (n, m). An example of the Zernike coefficients from the first term to the ninth term is shown below. Z1, n = 0, m = 0 (1) Z2, n = 1, m = 1 (r·cosθ) Z3, n = 0, m = -1 (r·sinθ) Z4, n = 2, m = 0 (2r 2 -1) Z5, n = 2, m = 2 (r 2 ·cos2θ) Z6, n = 2, m = -2 (r 2 ·sin2θ) Z7, n = 3, m = 1 ((3r3 -2r)·cosθ) Z8,n = 3,m = -1 ((3r 3 -2r)·sinθ) Z9,n = 4,m = 0 (6r 4 -6r 2 +1) · · ·

[0087] For example, the Zernike coefficient Z1, which is the Zernike coefficient of item 1, represents the average value of the pixel values in the wafer plane. The second Zernike coefficient Z2 represents the horizontal tilt component of the pixel values in the wafer plane. The third Zernike coefficient Z3 represents the vertical tilt component of the pixel values in the wafer plane (the direction orthogonal to the tilt direction of the Zernike coefficient Z2). The fourth Zernike coefficient represents the curvature component of the pixel values that is uniform in the circumferential direction with the center of the wafer as the origin and gradually increases in the radial direction.

[0088] Return to the description of FIG. 14. The coefficient calculation unit 402 calculates the value of each in-plane tendency component Zi of the pixel values in the wafer plane obtained by decomposing the planar distribution Z of the pixel values in the wafer plane as described above. Specifically, since the magnitude of the in-plane tendency component Zi of the pixel values is represented by the Zernike coefficient as described above, the value of each in-plane tendency component Zi of the pixel values is calculated by obtaining the value of each Zernike coefficient.

[0089] The distance calculation unit 403 calculates the Mahalanobis distance for each imaging image set acquired by the candidate acquisition unit 401 for each term (each degree) in the Zernike polynomial based on the correlation distribution between the Zernike coefficient in the IN image and the Zernike coefficient in the OUT image. The distance calculation unit 403 calculates, for each imaging image set acquired by the candidate acquisition unit 401, the Mahalanobis distance MD (see FIG. 19 described later) between the point indicating the imaging image set and the correlation distribution in the space to which the correlation distribution belongs (that is, the distribution space consisting of the Zernike coefficient in the IN image and the Zernike coefficient in the OUT image) for each term in the Zernike polynomial.

[0090] The extraction unit 404 determines the degree of abnormality for each set of captured images acquired by the candidate acquisition unit 401 based on the Mahalanobis distance calculated by the distance calculation unit 403. Then, based on the determined degree of abnormality, the extraction unit 404 extracts and selects a set of captured images for model creation from the sets of captured images acquired by the candidate acquisition unit 401.

[0091] Next, the selection process of the set of captured images for model creation by the selection unit 400 will be described. FIG. 18 is a diagram showing the flow of the selection process of the set of captured images for model creation by the selection unit 400. FIG. 19 is a diagram for explaining the Mahalanobis distance. FIG. 20 is a diagram conceptually showing the method of calculating the degree of abnormality.

[0092] First, as shown in the figure, the candidate acquisition unit 401 of the selection unit 400 acquires a plurality of sets of captured images from the storage unit 301 as candidates for the set of captured images for model creation (step S1). At this time, the candidate acquisition unit 401 excludes the set of captured images for the wafer W determined to have "defects" in the defect inspection from the candidates for the set of captured images for model creation. The candidate acquisition unit 401 excludes the set of captured images for the wafer W determined to have "defects" when it is determined to have "defects" in the defect inspection based on the IN image, and also when it is determined to have "defects" in the defect inspection based on the OUT image.

[0093] Subsequently, the coefficient calculation unit 402 performs enhancement processing on each of the captured images (i.e., IN image and OUT image) included in the set of captured images acquired by the candidate acquisition unit 401 (step S2). The above enhancement processing is, for example, processing for enhancing the contrast in each captured image. Thereby, for a captured image of a wafer on which a coating film is formed, potential coating unevenness can be made apparent.

[0094] Next, for each captured image of the emphasized wafer W, the coefficient calculation unit 402 decomposes the planar distribution of the pixel values in the captured image into in-plane tendency components Zi of a plurality of pixel values using Zernike polynomials, and calculates the Zernike coefficients of each in-plane tendency component respectively (step S3). In other words, for each captured image of the emphasized wafer W (that is, for each of the emphasized IN image and OUT image), the coefficient calculation unit 402 approximates the planar distribution of the pixel values in the image using Zernike polynomials, and calculates the coefficients of each term in the approximation formula, that is, the Zernike coefficients, respectively. The coefficient calculation unit 402 calculates, for example, the Zernike coefficients from the first term to the 16th term in the Zernike polynomial. The calculation of the Zernike coefficients as described above by the coefficient calculation unit 402 is performed, for example, for each of RGB.

[0095] Next, for each set of captured images acquired by the candidate acquisition unit 401, the distance calculation unit 403 calculates the Mahalanobis distance MD for each term in the Zernike polynomial (step S4). As shown in FIG. 19, the Mahalanobis distance MD for each term in the Zernike polynomial calculated here is the Mahalanobis distance between the point P indicating the set of captured images to be calculated and the correlation distribution C between the Zernike coefficients in the IN image and the Zernike coefficients in the OUT image in the distribution space K of the Zernike coefficients between the IN image and the OUT image. Note that the Mahalanobis distance represents a measure between a sample point and a distribution. The Mahalanobis distance MD from the vector y to a distribution having the mean μ and the covariance Σ can be calculated by the following formula.

[0096]

Equation

[0097] The distance calculation unit 403 calculates the Mahalanobis distance MD for each set of captured images acquired by the candidate acquisition unit 401 for each term from the first term to the 16th term in the Zernike polynomial. Also, the calculation of the Mahalanobis distance for each term in the Zernike polynomial is performed, for example, for each of RGB. Furthermore, normalization processing may be performed by dividing the Mahalanobis distance calculated for each term in the Zernike polynomial by the average value in the corresponding term.

[0098] Subsequently, the extraction unit 404 determines the abnormality degree Ab of each imaging image set based on the Mahalanobis distance calculated for each term in the Zernike polynomial for each imaging image set by the distance calculation unit 403 (step S5). For example, the extraction unit 404 adds up the Mahalanobis distances MD calculated for each term in the Zernike polynomial by the distance calculation unit 403 for each imaging image set to determine the abnormality degree Ab.

[0099] More specifically, as shown in FIG. 20, for example, the extraction unit 404 adds up all the Mahalanobis distances MD for R calculated for each of the first to 16th terms in the Zernike polynomial by the distance calculation unit 403 for each imaging image set. Then, the extraction unit 404 determines the result of the addition (i.e., the sum of the above Mahalanobis distances MD) as the abnormality degree Ab for R of each imaging image set. r Similarly, the extraction unit 404 adds up all the Mahalanobis distances MD for G calculated for each of the first to 16th terms in the Zernike polynomial by the distance calculation unit 403 for each imaging image set, and determines the abnormality degree Ab for G of each imaging image set. g Also, the extraction unit 404 adds up all the Mahalanobis distances MD for B calculated for each of the first to 16th terms in the Zernike polynomial by the distance calculation unit 403 for each imaging image set, and determines the abnormality degree Ab for B of each imaging image set. b That is, the extraction unit 404 adds up all the Mahalanobis distances MD calculated for each of the first to 16th terms in the Zernike polynomial and for each of the RGB colors for each of the RGB colors and for each imaging image set.

[0100] In addition, when adding up the Mahalanobis distances MD calculated for each term in the Zernike polynomial for each imaging image set, weighting may be performed for each term in the Zernike polynomial. Also, when adding up the Mahalanobis distances calculated for each term in the Zernike polynomial and for each color of RGB for each imaging image set, weighting may be performed for each color.

[0101] Next, the extraction unit 404 sets an abnormality determination threshold Th for the abnormality degree Ab determined by the extraction unit 404 (step S6). For example, the extraction unit 404 calculates the threshold Th c based on the following formula. In the following formula, Ab Ave represents the average value of the abnormality degree Ab determined by the extraction unit 404, Ab Std represents the standard deviation of the abnormality degree Ab determined by the extraction unit 404, and c is an integer from 1 to 3, for example. Th c = Ab Ave + c × Ab Std The extraction unit 404 sets the calculated threshold Th c as the abnormality determination threshold Th. Note that if the calculated and set threshold Th c is too small, in the image capture image set extraction process for model creation in step S7 described later, more imaging image sets than necessary may be excluded from the imaging image sets for model creation. Therefore, a lower limit value for the abnormality determination threshold Th is provided, and when the threshold Th c calculated based on the above formula is below the lower limit value, the lower limit value may be used as the abnormality determination threshold Th. The calculation of the threshold Th c based on the above formula and the setting of the abnormality determination threshold Th are performed for each of RGB. Note that hereinafter, the abnormality determination thresholds Th for R, G, and B are denoted as Th r , Th g , and Th b .

[0102] Then, the extraction unit 404 extracts and selects an imaging image set for model creation based on the abnormality degree Ab of each imaging image set determined by the extraction unit 404 and the threshold Th set by the extraction unit 404 (step S7). Specifically, the extraction unit 404 extracts, as an imaging image set for model creation, those among the imaging image sets acquired by the candidate acquisition unit 401 whose total abnormality degree Ab obtained by adding the Mahalanobis distances MD does not exceed the abnormality determination threshold Th. More specifically, the extraction unit 404 extracts an imaging image set that satisfies all of the following conditions (x1) to (x3) for model creation. (x1) Abnormality degree Ab for R r ≥ Abnormality determination threshold Th for R r (x2) Abnormality degree Ab for G g ≥ Abnormality determination threshold Th for G g (x3) Abnormality degree Ab for B b ≥ Abnormality determination threshold Th for B b

[0103] As described above, by automatically selecting an image set optimal for learning the image estimation model from a large number of imaging image sets, the quality of the image estimation model can be ensured, and furthermore, the accuracy of defect detection using this image estimation model can be improved.

[0104] The method for extracting an imaging image set for model creation based on the Mahalanobis distance by the extraction unit 404 is not limited to the above example. For example, the following method may be used.

[0105] That is, for each imaging image set, the extraction unit 404 sets, for example, the Mahalanobis distance MD calculated by the distance calculation unit 403 for each term in the Zernike polynomial as the abnormality degree Ab. More specifically, for example, the extraction unit 404 sets the Mahalanobis distance MD for R calculated by the distance calculation unit 403 for each of the first to 16th terms in the Zernike polynomial as the abnormality degree Ab for R of each imaging image set r1 ~Ab r16Set it to. Similarly, the extraction unit 404, for example, sets the Mahalanobis distance MD for G calculated by the distance calculation unit 403 for each term from the first term to the 16th term in the Zernike polynomial to the abnormality degree Ab for G in each captured image set g1 ~Ab g16 Set it to. Also, the extraction unit 404, for example, sets the Mahalanobis distance MD for B calculated by the distance calculation unit 403 for each term from the first term to the 16th term in the Zernike polynomial to the abnormality degree Ab b1 ~Ab b16 Set it to.

[0106] Then, for each term in the Zernike polynomial, the extraction unit 404 sets an abnormality determination threshold Th for the abnormality degree Ab set by the extraction unit 404. For example, the extraction unit 404 calculates the threshold Th c For each of the first to 16th terms in the Zernike polynomial. In this case, for example, the same formula as described above can be used for the calculation formula.

[0107] The extraction unit 404 sets the calculated threshold Th c For each of the first to 16th terms in the Zernike polynomial as the abnormality determination threshold Th. Also in this example, a lower limit value of the abnormality determination threshold Th may be provided as described above. These thresholds Th c The calculation of and the setting of the abnormality determination threshold Th are performed for each of RGB. Hereinafter, for each of the first to 16th terms in the Zernike polynomial, the abnormality determination threshold Th for R is denoted as Th r1 ~Th r16 And the abnormality determination threshold Th for G is denoted as Th g1 ~Th g16 And the abnormality determination threshold Th for B is denoted as Th b1 ~Th b16 Let it be.

[0108] Then, the extraction unit 404 extracts, from the set of captured images acquired by the candidate acquisition unit 401, a set of captured images that do not have terms (orders) in the Zernike polynomial whose abnormality degree Ab exceeds the abnormality determination threshold Th as a set of captured images for model creation. More specifically, when n is an integer from 1 to 16, the extraction unit 404 extracts, for model creation, a set of captured images that satisfy all of the following conditions (y1) to (y3). (y1) For the n-th term in the Zernike polynomial, the abnormality degree Ab rn ≥ threshold Th rn is true. (y2) For the n-th term in the Zernike polynomial, the abnormality degree Ab gn ≥ threshold Th gn is true. (y3) For the n-th term in the Zernike polynomial, the abnormality degree Ab bn ≥ threshold Th bn is true.

[0109] In the above example, the Mahalanobis distance calculation etc. were performed for all colors and all terms in all Zernike polynomials, but for some colors and some terms, the Mahalanobis distance calculation etc. may be omitted. Information on the colors and the above terms for which the Mahalanobis distance calculation etc. are omitted is stored in the storage unit 301 in advance.

[0110] FIG. 21 is a diagram for explaining another example of a method for calculating the Mahalanobis distance. As shown in FIG. 21, the correlation distribution C between the Zernike coefficients in the IN image and the Zernike coefficients in the OUT image does not form a single cluster, making it impossible to calculate an appropriate Mahalanobis distance and possibly preventing the appropriate selection of a set of captured images for model creation. In this case, the correlation distribution C may be divided into a plurality of sub-correlation distributions. For example, the correlation distribution C may be divided into two sub-correlation distributions C1 and C2 as shown in FIG. 21. Then, when the distance calculation unit 403 calculates the Mahalanobis distance of a set of captured images, the Mahalanobis distance between the sub-correlation distribution to which the set of captured images belongs and the point indicating the set of captured images may be calculated.

[0111] The division unit of the correlation distribution C into sub-correlation distributions is, for example, for each lot of wafers W, for each apparatus, or for each transfer route, i.e., for each passing module.

[0112] It should be considered that all the embodiments disclosed this time are illustrative in all respects and not restrictive. The above embodiments may be omitted, replaced, or changed in various forms without departing from the scope and gist of the appended claims.

[0113] Note that the following configurations also belong to the technical scope of the present disclosure. (1) A substrate inspection apparatus for inspecting a substrate, an acquisition unit that acquires an estimated image of the inspection target substrate after being processed by the substrate processing apparatus, based on an image estimation model created by machine learning using pre-processing captured images and post-processing captured images for each of a plurality of substrates, and a captured image of the inspection target substrate before being processed by the substrate processing apparatus; a determination unit that determines whether or not there is a defect in the inspection target substrate, based on a captured image of the inspection target substrate after being processed by the substrate processing apparatus and the estimated image. In the above (1), an image estimation model created by machine learning using pre-processing and post-processing captured images for a plurality of substrates is used to generate a reference image that serves as a reference for defect inspection, and it is determined whether or not there is a defect in the inspection target substrate. Since the reference image that serves as a reference for defect inspection is an estimated image generated based on the above image estimation model, the unevenness between the captured image and the reference image for the inspection target substrate after being processed becomes substantially the same. Therefore, since the possibility of detecting the unevenness as a defect is low, the defect detection accuracy can be improved.

[0114] (2) The substrate inspection apparatus according to (1) above, wherein the acquisition unit generates an estimated image of the inspection target substrate after being processed by the substrate processing apparatus.

[0115] (3) The determination unit determines the presence or absence of defects on the substrate to be inspected based on the difference between the captured image of the substrate to be inspected after the processing by the substrate processing apparatus and the estimated image, in the substrate inspection apparatus according to the above (1) or (2).

[0116] (4) The determination unit determines the presence or absence of defects on the substrate to be inspected based on the captured image of the substrate to be inspected after the processing by the substrate processing apparatus and the image of the central portion of the substrate in the estimated image, in the substrate inspection apparatus according to any one of the above (1) to (3). According to the above (4), defect inspection can be performed more accurately.

[0117] (5) The image estimation model is a generation network in a conditional adversarial generation network that converts an input arbitrary image to generate a fake image. Regarding the discrimination network in the conditional adversarial generation network, in which an arbitrary image and the real image corresponding to the arbitrary image or the fake image generated based on the arbitrary image are input, and the discrimination network discriminates whether the image input together with the arbitrary image is the real image or the fake image, a discrimination method is machine-learned so that the discrimination is accurately performed. Regarding the generation network, a method for converting an image is machine-learned so that the fake image is recognized as the real image in the discrimination network, in the substrate inspection apparatus according to any one of the above (2) to (5).

[0118] (6) A substrate inspection system for inspecting a substrate, A substrate processing apparatus for processing a substrate, A control apparatus, and is provided with, The control apparatus, A creation unit that creates an image estimation model by machine learning using the captured images before and after the processing by the substrate processing apparatus for each of a plurality of substrates, A generation unit that generates an estimated image of the substrate to be inspected after the processing by the substrate processing apparatus based on the captured image of the substrate to be inspected before the processing by the substrate processing apparatus and the image estimation model. A substrate inspection system, comprising: a determination unit that determines whether there is a defect in the inspection target substrate based on a captured image of the inspection target substrate after processing by the substrate processing apparatus and the estimated image.

[0119] (7) The image estimation model is a generation network in a conditional adversarial generation network that converts an input arbitrary image to generate a fake image. In the conditional adversarial generation network, for an identification network that inputs an arbitrary image together with a real image corresponding to the arbitrary image or the fake image generated based on the arbitrary image, and identifies whether the image input together with the arbitrary image is the real image or the fake image, an identification method is machine-learned so that the identification is accurately performed. For the generation network, a method for converting an image is machine-learned so that the fake image is recognized as the real image in the identification network. The substrate inspection system according to (6).

[0120] (8) The substrate inspection system further includes a selection unit that selects an image set for model creation, which is an image set consisting of a combination of a captured image of the substrate before processing and a captured image of the substrate after processing. The selection unit selects the image set for model creation based on the degree of abnormality determined using the correlation distribution between the in-plane tendency of the pixel values in the captured image of the substrate before processing and the in-plane tendency of the pixel values in the captured image of the substrate after processing. The substrate inspection system according to (6) or (7).

[0121] (9) The selection unit a candidate acquisition unit that acquires a plurality of the image sets as candidates for the image set for model creation; For each captured image of the substrate included in the acquired image set for model creation, the planar distribution of the pixel values in the captured image is decomposed into in-plane tendency components of a plurality of pixel values using Zernike polynomials, and the Zernike coefficients of each in-plane tendency component are calculated respectively by a coefficient calculation unit. For each term in the Zernike polynomial, based on the correlation distribution between the Zernike coefficients in the captured image of the substrate before the processing and the Zernike coefficients in the captured image of the substrate after the processing, a distance calculation unit that calculates the Mahalanobis distance for each of the captured image sets; For each of the captured image sets, based on the Mahalanobis distance, determining an abnormality degree, and based on the abnormality degree, an extraction unit that extracts the captured image set for model creation from among the captured image sets acquired by the candidate acquisition unit, the substrate inspection system according to (8) above.

[0122] (10) The extraction unit For each of the captured image sets, adding up the Mahalanobis distances calculated by the distance calculation unit for each term in the Zernike polynomial to determine the abnormality degree, Of the captured image sets acquired by the acquisition unit, those for which the abnormality degree obtained by adding up the Mahalanobis distances does not exceed a threshold value are extracted as the captured image set for model creation, the substrate inspection system according to (9) above.

[0123] (11) The abnormality degree is the Mahalanobis distance calculated by the distance calculation unit for each term in the Zernike polynomial, The extraction unit extracts, as the captured image set for model creation, a captured image set that does not have a term in the Zernike polynomial for which the abnormality degree exceeds the threshold value from among the captured image sets, the substrate inspection system according to (9) above.

[0124] (12) A substrate inspection method for inspecting a substrate, A step of acquiring a captured image of a substrate to be inspected before processing by a substrate processing apparatus; A step of acquiring a captured image of the substrate to be inspected after processing by a substrate processing apparatus; A step of obtaining an estimated image of the inspection target substrate after being processed by the substrate processing apparatus, based on an image estimation model created by machine learning using the pre-processing captured images and the post-processing captured images for each of a plurality of substrates, and a captured image of the inspection target substrate before being processed by the substrate processing apparatus; A substrate inspection method, comprising: a step of determining whether or not there is a defect in the inspection target substrate, based on the captured image of the inspection target substrate after being processed by the substrate processing apparatus and the estimated image.

[0125] (13) The image estimation model is a generation network that converts an input arbitrary image to generate a fake image in a conditional adversarial generation network; In the conditional adversarial generation network, for a discrimination network that inputs an arbitrary image together with a real image corresponding to the arbitrary image or the fake image generated based on the arbitrary image, and discriminates whether the image input together with the arbitrary image is the real image or the fake image, a discrimination method is machine-learned so that the discrimination is accurately performed; The substrate inspection method according to (12), wherein for the generation network, a method of converting an image is machine-learned so that the fake image is recognized as the real image in the discrimination network.

[0126] (14) An estimation model of a captured image of a substrate, which is used when inspecting a substrate, The estimation model causes a computer to function so as to estimate a captured image of the inspection target substrate after being processed by the substrate processing apparatus from a captured image of the inspection target substrate before being processed by the substrate processing apparatus, and is created by machine learning using a conditional adversarial generation network, using the captured images before and after processing by the substrate processing apparatus for each of a plurality of substrates. In the conditional adversarial generation network, it is a generation network that converts an input arbitrary image to generate a fake image. ​In the machine learning by the conditional adversarial generation network, for an identification network that inputs an arbitrary image together with a genuine image corresponding to the arbitrary image or the fake image generated based on the arbitrary image, and identifies whether the image input together with the arbitrary image is the genuine image or the fake image, an identification method is learned so that the identification is accurately performed, and for the generation network, an image conversion method is learned so that the fake image is recognized as the genuine image in the identification network. This is an estimation model.

Explanation of Signs

[0127] 1 Substrate inspection system 20 Overall control device 120 Development processing device 121 Lower layer film forming device 122 Intermediate layer film forming device 123 Resist coating device 130 Heat treatment device 251 Imaging control device 302 Model creation unit 313 Estimated image acquisition unit 314 Judgment unit Ie Estimated image Ip Captured image K1, K2, K3 Defects W Wafer

Claims

1. A substrate inspection device for inspecting a substrate, an acquisition unit that acquires an estimated image of the inspection target substrate after processing by the substrate processing apparatus, the estimated image being generated based on an image estimation model created by machine learning; an inspection unit that inspects the inspection target substrate based on the difference between the estimated image and a captured image of the inspection target substrate after processing by the substrate processing apparatus.

2. A substrate inspection device as described in Claim 1, wherein the inspection unit determines whether or not the substrate to be inspected has a defect based on the difference between the captured image of the substrate to be inspected after processing by the substrate processing device and the estimated image.

3. A substrate inspection device as described in Claim 2, wherein the inspection unit determines whether or not there is a defect in the substrate to be inspected based on an image of the substrate to be inspected after processing by the substrate processing device and an image of the center of the substrate in the estimated image.

4. The estimated image reflects in-plane unevenness specific to each substrate, the inspection unit determines whether or not there is a defect in the inspection target substrate after removing influences due to unevenness between the substrates based on a difference between the captured image of the inspection target substrate after processing by the substrate processing apparatus and the estimated image.

4. The substrate inspection device according to claim 2 or 3.

5. The substrate processing apparatus includes a plurality of transport routes including different passing modules, the image estimation model is created individually for each of the transportation routes, the acquisition unit acquires a captured image of the inspection target substrate after processing by the substrate processing apparatus, the captured image being generated for each of the transport routes; The inspection unit performs an inspection for each of the transport routes. The substrate inspection device according to claim 1 .

6. A substrate inspection method for inspecting a substrate, comprising: an acquisition step of acquiring an estimated image of the inspection target substrate after processing by the substrate processing apparatus, which is generated based on the image estimation model created by machine learning; an inspection step of inspecting the inspection target substrate based on the difference between the estimated image and an image of the inspection target substrate after processing by the substrate processing apparatus.

7. A substrate inspection method as described in Claim 6, wherein the inspection process determines whether or not the substrate to be inspected has a defect based on the difference between the captured image of the substrate to be inspected after processing by the substrate processing apparatus and the estimated image.

8. A substrate inspection method as described in Claim 7, wherein the inspection process determines whether or not there is a defect in the substrate to be inspected based on an image of the substrate to be inspected after processing by the substrate processing apparatus and an image of the center of the substrate in the estimated image.

9. The estimated image reflects in-plane unevenness specific to each substrate, determining whether or not there is a defect in the inspection target substrate after removing influences due to unevenness between the substrates based on a difference between the captured image of the inspection target substrate after processing by the substrate processing apparatus and the estimated image; 9. The substrate inspection method according to claim 7 or 8.

10. The substrate processing apparatus includes a plurality of transport routes including different passing modules, the image estimation model is created individually for each of the transportation routes, the acquiring step acquires a captured image of the inspection target substrate after processing by the substrate processing apparatus, the captured image being generated for each of the transport routes; The inspection step inspects each of the transport routes.

7. The substrate inspection method according to claim 6.

11. A program that runs on a computer of a control unit that controls a substrate inspection device so as to cause the substrate inspection device to execute a substrate inspection method, The substrate inspection method includes: an acquisition step of acquiring an estimated image of the inspection target substrate after processing by the substrate processing apparatus, which is generated based on the image estimation model created by machine learning; an inspection step of inspecting the inspection target substrate based on a difference between a captured image of the inspection target substrate after processing by the substrate processing apparatus and the estimated image.

Images