Gate drive circuit, display board, display device, and gate drive method

Abstract

To solve the problem of a conventional gate drive circuit that display effects are not good, because frequencies at which PWM signals can be outputted are limited, and flickers not recognizable by naked eyes occur to organic light-emitting diodes due to PWM signals of relatively low frequencies.SOLUTION: The present invention includes a multiplication control circuit and an effective output circuit. The effective output circuit includes several first shift registers that are cascaded, and a first shift register located in the first stage of the effective output circuit is provided with a first signal input terminal and a second signal input terminal, with the first signal input terminal connected to an output control signal line and the second signal input terminal is coupled to the multiplication control circuit. The multiplication control circuit is arranged so to be coupled to the output control signal line, and to provide a multiplication control signal to the second signal input terminal a preset time after receiving an output control signal in accordance with control of the output control signal provided by the output control signal line. The first shift register located in the first stage outputs a scan signal in accordance with control of the output control signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to the display field, and more particularly to a gate driving circuit, a display substrate, a display device, and a gate driving method. [Background technology]

[0002] Currently, to achieve further control over pixel unit brightness, active-matrix organic light-emitting diode (AMOLED) panels generally use pulse width modulation (PWM) for dimming. Specifically, a light-emitting control transistor is installed in the pixel circuit of the pixel unit to control the time that drive current flows through the organic light-emitting diode (OLED), thereby precisely controlling the equivalent brightness of the pixel unit.

[0003] However, conventional gate drive circuits have limitations on the frequency at which they can output PWM signals, and relatively low-frequency PWM signals can cause flickering in organic light-emitting diodes that is visible to the naked eye, resulting in poor display results. Summary of the Invention [Means for solving the problem]

[0004] The present application aims to solve at least one technical problem existing in the prior art, and provides a gate driving circuit, a display substrate, a display device, and a gate driving method.

[0005] In a first aspect, the present application provides an embodiment comprising: The effective output circuit includes a multiplication control circuit and an effective output circuit, the effective output circuit includes several cascaded first shift registers, the first shift register located at a first stage in the effective output circuit has a first signal input terminal and a second signal input terminal, the first signal input terminal is coupled to an output control signal line, and the second signal input terminal is coupled to the multiplication control circuit, the other first shift registers in the effective output circuit other than the first shift register located at the first stage are all provided with first cascade connection signal input terminals, the first cascade connection signal input terminals of the other first shift registers are respectively coupled to the signal output terminals of the corresponding first shift registers in the previous stages, the multiplication control circuit is coupled to the output control signal line, and is configured to provide a multiplication control signal to the second signal input terminal after a predetermined time has elapsed since receiving the output control signal in response to control of the output control signal provided by the output control signal line; The first shift register located in the first stage is configured to output a scanning signal in response to control of the output control signal and to output a scanning signal in response to control of the multiplication control signal. A gate drive circuit is provided.

[0006] In some embodiments, the multiplication control circuit includes several cascaded second shift registers; a third signal input terminal is disposed in a first shift register located in a first stage of the multiplication control circuit, and the third signal input terminal is coupled to the output control signal line; In the multiplication control circuit, the other second shift registers other than the second shift register located at the first stage are all provided with second cascade connection signal input terminals, and the second cascade connection signal input terminals of the other second shift registers are respectively coupled to the signal output terminals of the corresponding second shift registers at the previous stages; The signal output terminal of the second shift register located at the final stage in the multiplication control circuit is coupled to the second signal input terminal.

[0007] In some embodiments, the second shift register in the multiplication control circuit includes a signal write circuit, a first control circuit, a second control circuit and a signal output circuit; the signal write circuit, the first control circuit, the second control circuit and the signal output circuit are coupled to a first node, the first control circuit and the second control circuit are both coupled to a second node, and the second control circuit and the signal output circuit are both coupled to a third node; the signal write circuit is coupled to a corresponding signal input terminal and a first clock signal terminal, and is configured to write a signal provided by the corresponding signal input terminal to the first node according to control of a first clock signal provided by the first clock signal terminal; the first control circuit is coupled to a first power supply terminal and the first clock signal terminal, and is configured to write a first operating voltage provided by the first power supply terminal to the second node in response to control of the first clock signal, and to write the first clock signal to the second node in response to control of a voltage at the first node; the second control circuit is coupled to the second power supply terminal and the second clock signal terminal, and is configured to write the second clock signal to the third node in response to controlling a voltage at the second node and a second clock signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the third node in response to controlling a voltage at the first node; The signal output circuit is coupled to the first power supply terminal and the second power supply terminal, and is configured to write the first operating voltage to the signal output terminal in response to controlling a voltage at the first node, and to write the second operating voltage to the signal output terminal in response to controlling a voltage at the third node.

[0008] In some embodiments, the signal write circuit includes a first transistor, the first control circuit includes a second transistor and a third transistor, the second control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, and the signal output circuit includes a seventh transistor, an eighth transistor and a second capacitor; a control pole of the first transistor is coupled to the first clock signal terminal, a first pole of the first transistor is coupled to the signal input terminal, and a second pole of the first transistor is coupled to the first node; a control pole of the second transistor is coupled to the first node, a first pole of the second transistor is coupled to the first clock signal terminal, and a second pole of the second transistor is coupled to the second node; a control pole of the third transistor is coupled to the first clock signal terminal, a first pole of the third transistor is coupled to the first power supply terminal, and a second pole of the third transistor is coupled to the second node; a control pole of the fourth transistor is coupled to the second node, a first pole of the fourth transistor is coupled to the second clock signal terminal, and a second pole of the fourth transistor is coupled to the first pole of the fifth transistor; a control pole of the fifth transistor is coupled to the second clock signal terminal, and a second pole of the fifth transistor is coupled to the third node; a control pole of the sixth transistor is coupled to the first node, a first pole of the sixth transistor is coupled to the second power supply terminal, and a second pole of the sixth transistor is coupled to the third node; a first end of the first capacitor coupled to the second node and a second end of the first capacitor coupled to a second pole of the fourth transistor; a control pole of the seventh transistor is coupled to the third node, a first pole of the seventh transistor is coupled to the second power supply terminal, and a second pole of the seventh transistor is coupled to the signal output terminal; a control pole of the eighth transistor is coupled to the first node, a first pole of the eighth transistor is coupled to the first power supply terminal, and a second pole of the eighth transistor is coupled to the signal output terminal; A first end of the second capacitor is coupled to the third node, and a second end of the third capacitor is coupled to the second power supply terminal.

[0009] In some embodiments, the second shift register further comprises a noise reduction circuit; The noise reduction circuit is coupled to the first node, the second node, the second power supply terminal, and the second clock signal terminal, and is configured to perform noise reduction on the voltage at the first node in response to control of the second clock signal and the voltage at the second node.

[0010] In some embodiments, the noise reduction circuit includes a ninth transistor, a tenth transistor, and a third capacitor; a control pole of the ninth transistor is coupled to the second node, a first pole of the ninth transistor is coupled to the second power supply terminal, and a second pole of the ninth transistor is coupled to a first pole of the tenth transistor; a control pole of the tenth transistor is coupled to the second clock signal terminal, and a second pole of the tenth transistor is coupled to the first node; A first end of the third capacitor is coupled to the first node, and a second end of the third capacitor is coupled to the second clock signal end.

[0011] In some embodiments, the first shift register in the valid output circuit has the same circuit structure as the second shift register in the multiplication control circuit.

[0012] In some embodiments, the first signal input terminal and the second signal input terminal of the first shift register located in the first stage of the valid output circuit are the same signal input terminal.

[0013] In some embodiments, the first signal input terminal and the second signal input terminal of the first shift register located in the first stage of the valid output circuit are different signal input terminals; A first shift register located in the first stage includes a second switch circuit and a third switch circuit, the second switch circuit is disposed between the signal write circuit and the first signal input terminal, is coupled to the second signal input terminal, and is configured to control ON / OFF between the signal write circuit and the first signal input terminal in response to control of a signal provided by the second signal input terminal; The third switch circuit is disposed between the signal write circuit and the second signal input terminal, is coupled to the first signal input terminal, and is configured to control on / off between the signal write circuit and the second signal input terminal according to control of a signal provided by the first signal input terminal.

[0014] In some embodiments, the second switch circuit includes a twelfth transistor, and the third switch circuit includes a thirteenth transistor; a control pole of the twelfth transistor is coupled to the second signal input terminal, a first pole of the twelfth transistor is coupled to the first signal input terminal, and a second pole of the twelfth transistor is coupled to the signal write circuit; A control pole of the thirteenth transistor is coupled to the first signal input terminal, a first pole of the thirteenth transistor is coupled to the second signal input terminal, and a second pole of the thirteenth transistor is coupled to the signal write circuit.

[0015] In some embodiments, a first switch circuit is disposed in a second shift register located in a first stage of the multiplication control circuit, and the first switch circuit is disposed between the signal output circuit and the second power supply terminal, coupled to a first switch control terminal, and configured to control on / off between the signal output circuit and the second power supply terminal according to control of a first switch control signal provided by the first switch control terminal.

[0016] In some embodiments, the first switch circuit includes an eleventh transistor; A control pole of the eleventh transistor is coupled to a first switch control terminal, a first pole of the eleventh transistor is coupled to the second power supply terminal, and a second pole of the eleventh transistor is coupled to the signal output circuit.

[0017] In some embodiments, a first switch circuit is disposed in a second shift register located in a first stage in the multiplication control circuit, and the first switch circuit is disposed between the second control circuit and the second clock signal terminal, and is configured to control on / off between the second control circuit and the second clock signal terminal according to the control of a first switch control signal provided by the first switch control terminal.

[0018] In some embodiments, the first switch circuit includes an eleventh transistor; The control pole of the eleventh transistor is coupled to the first switch control terminal, the first pole of the eleventh transistor is coupled to the second clock signal terminal, and the second pole of the eleventh transistor is coupled to the second control circuit.

[0019] In some embodiments, a first switch circuit is disposed in a second shift register located in a first stage of the multiplication control circuit, and the first switch circuit is disposed between the signal write circuit and the signal input terminal, coupled to a first switch control terminal, and configured to control on / off between the signal write circuit and the signal input terminal according to control of a first switch control signal provided by the first switch control terminal.

[0020] In some embodiments, the first switch circuit includes an eleventh transistor; The control pole of the eleventh transistor is coupled to the first switch control terminal, the first pole of the eleventh transistor is coupled to the signal input terminal, and the second pole of the eleventh transistor is coupled to the signal write circuit.

[0021] In some embodiments, a first power supply circuit is disposed in a second shift register located in a first stage of the multiplication control circuit; The first power supply circuit is coupled to the signal light circuit, the first switch circuit, the first power supply terminal and a second switch control terminal, and is configured to write the first operating voltage to the signal light circuit according to control of the second switch control signal provided by the second switch control terminal.

[0022] In some embodiments, the first power supply circuit includes a fourteenth transistor; A control pole of the fourteenth transistor is coupled to the second switch control terminal, a first pole of the fourteenth transistor is coupled to the first power supply terminal, and a second pole of the fourteenth transistor is coupled to the signal write circuit and the first switch circuit.

[0023] In some embodiments, a second power supply circuit is disposed in a second shift register located in a first stage of the multiplication control circuit; The second power supply circuit is coupled to the first power supply terminal, the signal output terminal of the second shift register located in the first stage, and a second switch control terminal, and is configured to write the first operating voltage to the signal output terminal of the second shift register according to control of the second switch control signal provided by the second switch control terminal.

[0024] In some embodiments, the second power supply circuit includes a fifteenth transistor; A control pole of the 15th transistor is coupled to the second switch control terminal, a first pole of the 15th transistor is coupled to the first power supply terminal, and a second pole of the 15th transistor is coupled to the signal output terminal of a second shift register located in a first stage.

[0025] In some embodiments, the input terminal of the inverter circuit is coupled to the first switch control terminal, and the output terminal of the inverter circuit is coupled to the second switch control terminal.

[0026] According to a second aspect, an embodiment of the present application includes a gate driving circuit provided by the first aspect and a plurality of gate lines located in a display area; The gate line is coupled to a signal output terminal of a corresponding first shift register in the gate driving circuit. A display substrate is also provided.

[0027] According to a third aspect, an embodiment of the present application further provides a display device provided by the first aspect, including a display substrate and an opposing substrate disposed opposite the display substrate.

[0028] According to a fourth aspect, an embodiment of the present application is based on the gate drive circuit provided in the first aspect, comprising: According to the output control signal, the shift registers of each stage in the effective output circuit sequentially output scanning signals, and the multiplication control circuit provides a multiplication control signal to the second signal input terminal of a first shift register located at a first stage in the effective output circuit after a preset time; a step of outputting a scanning signal in sequence from each stage of the shift register in the effective output circuit in response to the multiplication control signal; The present invention further provides a gate driving method including: [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a conceptual diagram of the circuit structure of a single gate driving circuit provided in an embodiment of the present application. [Figure 2a] FIG. 2a is a schematic circuit diagram of another gate driving circuit provided by an embodiment of the present application. [Figure 2b] FIG. 2b is an operation timing diagram of the gate drive circuit shown in FIG. 2a. [Figure 3] FIG. 3 is a conceptual diagram of the circuit structure of the second shift register provided in the embodiment of the present application. [Figure 4] FIG. 4 is a conceptual diagram of the circuit structure of the second shift register shown in FIG. [Figure 5] FIG. 5 is an operation timing diagram of the second shift register shown in FIG. [Figure 6a] FIG. 6a is a conceptual diagram of the circuit structure of the second shift register located in the first stage in the embodiment of the present application. [Figure 6b] FIG. 6b is a schematic diagram of an alternative circuit structure based on the second shift register located in the first stage shown in FIG. 6a. [Figure 7a]FIG. 7a is another schematic circuit diagram of the second shift register located in the first stage in the embodiment of the present application. [Figure 7b] FIG. 7b is a schematic diagram of an alternative circuit structure based on the second shift register located in the first stage shown in FIG. 7a. [Figure 8] FIG. 8 is another conceptual diagram of the circuit structure of the second shift register located in the first stage in the embodiment of the present application. [Figure 9] FIG. 9 is a conceptual diagram of yet another circuit structure of the second shift register located in the first stage in the embodiment of the present application. [Figure 10] FIG. 10 is a conceptual diagram of yet another circuit structure of the second shift register located in the first stage in the embodiment of the present application. [Figure 11] FIG. 11 is a conceptual diagram of yet another circuit structure of the second shift register located in the first stage in the embodiment of the present application. [Figure 12a] FIG. 12a is a conceptual diagram of the circuit structure of the first shift register located in the first stage in the embodiment of the present application. [Figure 12b] FIG. 12b is a schematic diagram of an alternative circuit structure based on the first shift register located in the first stage shown in FIG. 12a. [Figure 13] FIG. 13 is a flow chart of a gate driving method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present application, the following detailed description of the gate driving circuit, display substrate, display device and gate driving method provided by the present application will be given in conjunction with the accompanying drawings.

[0031] In the related art, a gate driver circuit is provided with one output control signal line (generally a frame start signal line for providing a frame start signal), which is coupled to a shift register located in the first stage of the gate driver circuit and controls the shift register located in the first stage to output a scanning signal, while the shift registers located in the other stages of the gate driver circuit output scanning signals in sequence. The frequency of the scanning signal output by each shift register in the gate driver circuit is equal to the frequency of the output control signal provided by the output control signal line. For example, if the frequency of the output control signal provided by the output control signal is k, the frequency of the scanning signal output by each shift register in the gate driver circuit of the related art is also k.

[0032] Because the external chip's ability to provide a signal to the output control signal line is limited, the frequency of the output control signal loaded on the output control signal line is limited, and furthermore, the frequency of the scanning signal output by each stage of the shift register in the gate driver circuit is limited. In some application scenarios that require a high-frequency PWM signal (for example, when displaying a static two-dimensional code, if the PWM signal is too low, it will cause obvious flickering and make the two-dimensional code difficult to accurately identify), the gate driver circuit of the related art cannot meet the high-frequency output demand.

[0033] In order to solve at least one of the technical problems existing in the related art, the technical solution of the present application provides a gate driving circuit, a display substrate, a display device and a gate driving method.

[0034] 1 is a conceptual diagram of the circuit structure of a gate driver circuit provided by an embodiment of the present application. As shown in FIG. 1, the gate driver circuit includes a multiplication control circuit 1 and an effective output circuit 2. The effective output circuit 2 includes several cascaded first shift registers A_1, A_2...A_n, where n is an integer. The first shift register A_1 located at the first stage in the effective output circuit 2 has a first signal input terminal INPUT and a second signal input terminal INPUT', the first signal input terminal INPUT is coupled to the output control signal line, and the second signal input terminal INPUT' is coupled to the multiplication control circuit 1. The other first shift registers A_2...A_n other than the first shift register located at the first stage in the effective output circuit 2 are all provided with first cascaded signal input terminals INPUT, and the first cascaded signal input terminals INPUT of the other first shift registers are respectively coupled to the signal output terminals OUT of the corresponding first shift registers at the previous stages. In addition, the signal output terminal OUT of each first shift register A_1, A_2...A_n is coupled to a corresponding gate line GATE_1, GATE_2...GATE_n in the display area, and provides scanning signals to the corresponding gate line GATE_1, GATE_2...GATE_n. In this embodiment, the first signal input terminal INPUT and the first cascade connection signal input terminal INPUT are not identical, but are both signal input terminals of the first shift register.

[0035] The multiplication control circuit 1 is coupled to the output control signal line and is configured to receive the output control signal and provide the multiplication control signal to the second signal input terminal INPUT' after a predetermined time period in response to the control of the output control signal provided by the output control signal line STV.

[0036] The first shift register A_1 located in the first stage is configured to output a scanning signal under the control of the output control signal and to output a scanning signal under the control of the multiplication control signal. The first shift registers of the other stages output their own scanning signals under the control of the shift register in the previous stage outputting a scanning signal. Regarding the entire effective output circuit 2, after the first signal input terminal INPUT or the second signal input terminal INPUT' of the first shift register A_1 in the first stage receives a pulse, the first shift registers A_1, A_2...A_n of each stage in the effective output circuit 2 output scanning signals in sequence.

[0037] In the embodiment of the present application, the output control signal line STV may be a frame start signal line, or may be other signal lines set according to actual needs. In the embodiment of the present application, the output control signal line STV is used as the frame start signal line for illustrative purposes. Two clock signal lines CLK and CLKB are set in the gate driving circuit to provide clock signals to the shift register in the gate driving circuit.

[0038] Taking the case where the output control signal provided by the output control signal line STV includes one pulse as an example, the operation process of the gate determination circuit provided in the embodiment of the present application is as follows: in response to the output control signal, the shift register of each stage in the effective output circuit 2 outputs a scanning signal in sequence, and each scanning signal includes one pulse, and the multiplication control circuit 1 provides a multiplication control signal to the second signal input terminal INPUT' of the first shift register A_1 located in the first stage in the effective output circuit 2 after a predetermined time, and the output control signal includes one pulse, and in response to the multiplication control signal, the first shift register A_1, A_2...A_n of each stage in the effective output circuit 2 outputs a scanning signal in sequence, and each scanning signal includes one pulse.

[0039] The length of the "preset time" can be designed according to actual needs. For example, for a first shift register in the valid output circuit 2, the delay between two pulses output from the first shift register is the "preset time."

[0040] As can be seen from the above, although the output control signal provides only one pulse, each stage of the shift register in the effective output circuit 2 outputs two pulses. Based on the same principle, if the output control signal provides K pulses, the first shift register in each stage of the gate drive circuit can output 2K pulses. From this, it can be seen that the gate drive circuit provided by the embodiment of the present application can realize multiplication output, that is, raise the upper limit of the scanning frequency output by the gate drive circuit, and effectively prevent the appearance of flicker visible to the naked eye on the OLED caused by the PWM signal frequency being too low.

[0041] In the embodiment of the present application, the multiplication control circuit 1 has a delay output function. The specific circuit structure of the multiplication control circuit 1 is not limited by the technical solution of the present application. The effective output circuit 2 in the embodiment of the present application may be equivalent to a gate driving circuit in the related art, which can provide scanning signals to gate lines in a display panel. The specific circuit structure of the effective output circuit 2 (and the first shift register) is also not limited by the technical solution of the present application.

[0042] 2a is a circuit diagram of another gate driving circuit provided by an embodiment of the present application, and FIG. 2b is an operation timing diagram of the gate driving circuit shown in FIG. As shown in Figures 2a and 2b, the gate driving circuit shown in Figure 2a is a more specific alternative embodiment based on the gate driving circuit shown in Figure 1, in which the multiplication control circuit 1 includes several cascaded second shift registers B_1, B_2 ... B_m, where m is an integer, and the second shift register located at the first stage in the multiplication control circuit 1 is provided with a third signal input terminal INPUT, which is coupled to the output control signal line STV, and the other second shift registers B_2 ... B_m other than the second shift register B_1 located at the first stage in the multiplication control circuit 1 are all provided with second cascaded signal input terminals INPUT, which are coupled to the signal output terminals OUT of the corresponding second shift registers in the previous stages, and the signal output terminal OUT of the second shift register B_m located at the last stage in the multiplication control circuit 1 is coupled to the second signal input terminal INPUT'.

[0043] In this case, the multiplication control circuit 1 is used as a dummy gate driving circuit. The second shift registers B_1, B_2...B_m in the gate driving circuit are cascaded, but do not provide scanning signals to the gate lines in the display area. The multiplication control circuit 1 delays and outputs the received output control signal (as a multiplication control signal) based on the signal transmission process of the cascaded second shift registers B_1, B_2...B_m in the gate driving circuit.

[0044] In practical applications, the number m of second shift registers included in the multiplication control circuit 1 can be designed based on the "preset time" and the time difference between when two adjacent second shift registers output pulse signals. For example, if the preset time is T and the time difference between when two adjacent second shift registers output pulse signals is t, then the number of second shift registers included in the multiplication control circuit 1 is T / t.

[0045] In the operation timing shown in FIG. 2b, OUT(B_m) represents the signal output terminal of the m-th stage second shift register B_m, and OUT(A_n) represents the signal output terminal of the n-th stage first shift register A_n.

[0046] The embodiment of the present application does not limit the circuit structure of the second shift register, and the second shift register can be a conventional shift register of any structure, and an exemplary description will be given below in conjunction with the drawings.

[0047] 3 is a conceptual diagram of the circuit structure of a second shift register provided in an embodiment of the present application. As shown in FIG. 3, the second shift register includes a signal write circuit 101, a first control circuit 102, a second control circuit 103, and a signal output circuit 104, wherein the signal write circuit 101, the first control circuit 102, the second control circuit 103, and the signal output circuit 104 are coupled to a first node N1, the first control circuit 102 and the second control circuit 103 are coupled to a second node N2, and the second control circuit 103 and the signal output circuit 104 are coupled to a third node N3.

[0048] The signal write circuit 101 is coupled to a corresponding signal input terminal INPUT and a first clock signal terminal CK, and writes the signal provided by the corresponding signal input terminal to a first node N1 according to the control of a first clock signal provided by the first clock signal terminal CK.

[0049] The first control circuit 102 is coupled to the first power supply terminal and the first clock signal terminal CK, and is configured to write the first operating voltage provided by the first power supply terminal to the second node N2 in response to the control of the first clock signal, and to write the first clock signal to the second node N2 in response to the control of the voltage at the first node N1.

[0050] The second control circuit 103 is coupled to the second power supply terminal and the second clock signal terminal CKB, and is configured to write a second clock signal to the third node N3 in response to controlling the voltage at the second node N2 and the second clock signal provided by the second clock signal terminal CKB, and to write a second operating voltage provided by the second power supply terminal to the third node N3 in response to controlling the voltage at the first node N1.

[0051] The signal output circuit 104 is coupled to the first power supply terminal and the second power supply terminal, and is configured to write a first operating voltage to the signal output terminal OUT in response to controlling the voltage at the first node N1, and to write a second operating voltage to the signal output terminal OUT in response to controlling the voltage at the third node N3.

[0052] In some embodiments, the second shift register further includes a noise reduction circuit coupled to the first node N1, the second node N2, the second power supply terminal, and the second clock signal terminal CKB, and configured to perform noise reduction processing on the voltage at the first node N1 in response to control of the second clock signal and the voltage at the second node N2.

[0053] 4 is a circuit diagram of the second shift register shown in FIG. 3. As shown in FIG. 4, the second shift register shown in FIG. 4 is an alternative embodiment based on the second shift register shown in FIG.

[0054] In some embodiments, the signal write circuit 101 includes a first transistor M1, the first control circuit 102 includes a second transistor M2 and a third transistor M3, the second control circuit 103 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1, and the signal output circuit 104 includes a seventh transistor M7, an eighth transistor M8 and a second capacitor C2.

[0055] A control pole of the first transistor M1 is coupled to the first clock signal terminal CK, a first pole of the first transistor M1 is coupled to the signal input terminal INPUT, and a second pole of the first transistor M1 is coupled to the first node N1.

[0056] The control pole of the second transistor M2 is coupled to the first node N1, the first pole of the second transistor M2 is coupled to the first clock signal terminal CK, and the second pole of the second transistor M2 is coupled to the second node N2.

[0057] The control electrode of the third transistor M3 is coupled to the first clock signal terminal CK, the first electrode of the third transistor M3 is coupled to the first power supply terminal, and the second electrode of the third transistor M3 is coupled to the second node N2.

[0058] The control pole of the fourth transistor M4 is coupled to the second node N2, the first pole of the fourth transistor M4 is coupled to the second clock signal terminal CKB, and the second pole of the fourth transistor M4 is coupled to the first pole of the fifth transistor M5.

[0059] The control pole of the fifth transistor M5 is coupled to the second clock signal terminal CKB, and the second pole of the fifth transistor M5 is coupled to the third node N3.

[0060] The control electrode of the sixth transistor M6 is coupled to the first node N1, the first electrode of the sixth transistor M6 is coupled to the second power supply terminal, and the second electrode of the sixth transistor M6 is coupled to the third node N3.

[0061] A first end of the first capacitor C1 is coupled to the second node N2, and a second end of the first capacitor C1 is coupled to the second pole of the fourth transistor M4.

[0062] A control electrode of the seventh transistor M7 is coupled to the third node N3, a first electrode of the seventh transistor M7 is coupled to the second power supply terminal, and a second electrode of the seventh transistor M7 is coupled to the signal output terminal OUT.

[0063] The control pole of the eighth transistor M8 is coupled to the first node N1, the first pole of the eighth transistor M8 is coupled to the first power supply terminal, and the second pole of the eighth transistor M8 is coupled to the signal output terminal OUT.

[0064] A first end of the second capacitor C2 is coupled to the third node, and a second end of the second capacitor C2 is coupled to the first power supply terminal.

[0065] In some embodiments, the noise reduction circuit includes a ninth transistor M9, a tenth transistor M10, and a third capacitor C3.

[0066] The control electrode of the ninth transistor M9 is coupled to the second node N2, the first electrode of the ninth transistor M9 is coupled to the second power supply terminal, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10.

[0067] The control pole of the tenth transistor M10 is coupled to the second clock signal terminal CKB, and the second pole of the tenth transistor M10 is coupled to the first node N1.

[0068] A first end of the third capacitor C3 is coupled to the first node N1, and a second end of the third capacitor C3 is coupled to the second clock signal terminal CKB.

[0069] In the embodiments of the present application, each transistor can be independently selected from one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. In the embodiments of the present application, the "control electrode" specifically refers to the gate of the transistor, the "first pole" specifically refers to the source of the transistor, and the corresponding "second pole" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first pole" and the "second pole" can be interchanged.

[0070] In addition, transistors can be divided into N-type transistors and P-type transistors. Each transistor in the present application can be independently selected from N-type transistors or P-type transistors. In the following embodiments, an example in which all transistors in the pixel unit are P-type transistors will be described. In this case, the transistors in the second shift register can be simultaneously manufactured using the same manufacturing process. Accordingly, the first operating voltage provided by the first power supply terminal is a low-level voltage VGL, and the second operating voltage provided by the second power supply terminal is a high-level voltage VGH. The operation process of the second shift register shown in FIG. 4 will be described in detail below in conjunction with FIG. 4.

[0071] Figure 5 is an operation timing diagram of the second shift register shown in Figure 4. As shown in Figure 5, the operation process of the second shift register includes the following steps:

[0072] First stage t1: the first clock signal provided by the first clock signal terminal CK is in a low level state, the second clock signal provided by the second clock signal terminal CKB is in a high level state, and the signal provided by the third signal input terminal INPUT is in a high level state. At this time, the first transistor M1, the third transistor M3, the fourth transistor M4, and the ninth transistor M9 are in a conducting state, and the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the tenth transistor M10 are in a non-conducting state.

[0073] Specifically, since the first clock signal is in a low state, the first transistor M1 and the third transistor M3 are both conductive, the signal provided by the third signal input terminal INPUT in a high state is written to the first node N1 by the first transistor M1, the first operating voltage VGL is written to the second node N2 by the third transistor M3, and the first node N1 is in a high state and the second node N2 is in a low state.

[0074] Since the first node N1 is in a high state, the sixth transistor M6 and the eighth transistor M8 are turned off. Since the second node N2 is in a low state, the fourth transistor M4 and the ninth transistor M9 are turned on, so that the second clock signal in a high state is written to the fourth node N4 by the fourth transistor M4, and the second operating voltage VGH is written to the fifth node N5 by the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low state, and the second terminal of the first capacitor C1 is in a high state.

[0075] Since the second clock signal is in a high state, the fifth transistor M5 and the tenth transistor M10 are turned off, and since the fifth transistor M5 and the sixth transistor M6 are both turned off, the third node N3 is in a floating state, the voltage at the third node N3 remains in its previous high state, and the seventh transistor M7 is turned off.

[0076] Since the seventh transistor M7 and the eighth transistor M8 are both turned off, the signal output terminal OUT is in a floating state, and the voltage at the signal output terminal OUT maintains its previous low level state.

[0077] Second stage t2: the first clock signal provided by the first clock signal terminal CK is in a high level state, the second clock signal provided by the second clock signal terminal CKB is in a low level state, and the signal provided by the third signal input terminal INPUT is in a low level state. At this time, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are in a conducting state, and the first transistor M1, the second transistor M2, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are in a non-conducting state.

[0078] Specifically, when the first clock signal is in a high state, the first transistor M1 and the third transistor M3 are both turned off. When the second clock signal is in a low state, the fifth transistor M5 and the tenth transistor M10 are turned on. At this time, the second operating voltage VGH is written to the first node N1 by the ninth transistor M9 and the tenth transistor M10, so that the first node N1 remains in a high state and noise reduction is achieved for the first node N1. The second transistor M2 and the eighth transistor M8 remain in a turned off state. At this time, the first terminal of the third capacitor C3 is in a high state, and the second terminal of the third capacitor C3 is in a low state.

[0079] At this time, the second clock signal in a low state is written to the fourth node N4 by the fourth transistor M4, the voltage at the fourth node N4 changes from a high state to a low state, and because the first end of the first capacitor C1 is in a floating state, under the bootstrap action of the first capacitor C1, the voltage at the second node N2 is pulled down to a lower state level.

[0080] Since the fifth transistor M5 is turned on, the second clock signal in a low level state is written to the third node N3 by the fourth transistor M4 and the fifth transistor M5, and the third node N3 is in a low level state. When the seventh transistor M7 is turned on, the second operating voltage VGH is written to the signal output terminal OUT by the seventh transistor M7, and the signal output terminal OUT outputs a high level signal.

[0081] Third stage t3: the first clock signal provided by the first clock signal terminal CK is in a low level state, the second clock signal provided by the second clock signal terminal CKB is in a high level state, and the signal provided by the third signal input terminal INPUT is in a low level state, at this time, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 are in a conducting state, and the fifth transistor M5, the seventh transistor M7, and the tenth transistor M10 are in a non-conducting state.

[0082] Specifically, since the first clock signal is in a low state, the first transistor M1 and the third transistor M3 are both conductive, the signal in a low state provided by the third signal input terminal INPUT is written to the first node N1 by the first transistor M1, the first operating voltage VGL is written to the second node N2 by the third transistor M3, the first node N1 is in a low state, the second node N2 is in a low state, the first end of the third capacitor C3 is in a low state, and the second end of the third capacitor C3 is in a high state.

[0083] Since the first node N1 is in a low state, the sixth transistor M6 and the eighth transistor M8 are conductive. Since the second node N2 is in a low state, the fourth transistor M4 and the ninth transistor M9 are conductive, the second clock signal in a high state is written to the fourth node N4 by the fourth transistor M4, and the second operating voltage VGH is written to the fifth node N5 by the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low state, and the second terminal of the first capacitor C1 is in a high state.

[0084] Since the second clock signal is in a high state, the fifth transistor M5 and the tenth transistor M10 are turned off, and since the fifth transistor M5 and the tenth transistor M10 are turned off, the second operating voltage VGH is written to the third node N3 by the sixth transistor M6, and the third node N3 is in a high state.

[0085] Since the first node N1 is in a low level state and the third node N3 is in a high level state, the seventh transistor M7 is turned off and the eighth transistor M8 is turned on, so that the first operating voltage VGL is written to the signal output terminal OUT by the eighth transistor M8, and the signal output terminal OUT outputs a low level signal.

[0086] Fourth stage t4: the first clock signal provided by the first clock signal terminal CK is in a high level state, the second clock signal provided by the second clock signal terminal CKB is in a low level state, and the signal provided by the third signal input terminal INPUT is in a low level state. At this time, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are in a conducting state, and the first transistor M1, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 are in a non-conducting state.

[0087] Specifically, when the first clock signal is in a high state, the first transistor M1 and the third transistor M3 are both turned off. With the first transistor M1 turned off, the first node N1 is in a floating state. When the second clock signal changes from a high state to a low state, the voltage at the first node N1 is pulled down to a lower level through the bootstrap function of the third capacitor C3, thereby providing noise reduction for the first node N1. At this time, the second transistor M2, the sixth transistor M6, and the eighth transistor M8 are all turned on. The second operating voltage VGH is written to the third node N3 by the sixth transistor M6.

[0088] Since the second transistor M2 is in a conducting state, the first clock signal in a high state is written to the second node N2 by the second transistor M2, the second node N2 is in a high state, and the fourth transistor M4 is cut off.

[0089] Since the second clock signal is in a low state, the fifth transistor M5 and the tenth transistor M10 are in a conductive state, and at this time, the voltage at the fourth node N4 is equal to the voltage at the third node N3, and the voltage at the fifth node N5 is equal to the voltage at the first node N1, that is, the voltage at the fourth node N4 is in a high state, and the voltage at the fifth node N5 is in a low state.

[0090] Since the first node N1 is in a low level state and the third node N3 is in a high level state, the seventh transistor M7 is turned off and the eighth transistor M8 is turned on, so that the first operating voltage VGL is written to the signal output terminal OUT by the eighth transistor M8, and the signal output terminal OUT outputs a low level signal.

[0091] Fifth stage t5: the first clock signal provided by the first clock signal terminal CK is in a low level state, the second clock signal provided by the second clock signal terminal CKB is in a high level state, and the signal provided by the third signal input terminal INPUT is in a low level state, at this time, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 are in a conducting state, and the fifth transistor M5, the seventh transistor M7, and the tenth transistor M10 are in a non-conducting state.

[0092] Specifically, since the first clock signal is in a low state, the first transistor M1 and the third transistor M3 are conductive, the signal in a low state provided by the third signal input terminal INPUT is written to the first node N1 by the first transistor M1, the first operating voltage VGL is written to the second node N2 by the third transistor M3, the first node N1 is in a low state, the second node N2 is in a low state, the first end of the third capacitor C3 is in a low state, and the second end of the third capacitor C3 is in a high state.

[0093] Since the first node N1 is in a low state, the sixth transistor M6 and the eighth transistor M8 are conductive. Since the second node N2 is in a low state, the fourth transistor M4 and the ninth transistor M9 are conductive, the second clock signal in a high state is written to the fourth node N4 by the fourth transistor M4, and the second operating voltage VGH is written to the fifth node N5 by the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low state, and the second terminal of the first capacitor C1 is in a high state.

[0094] Since the second clock signal is in a high state, the fifth transistor M5 and the tenth transistor M10 are turned off, and since the fifth transistor M5 and the tenth transistor M10 are turned off, the second operating voltage VGH is written to the third node N3 by the sixth transistor M6, and the third node N3 is in a high state.

[0095] Since the first node N1 is in a low level state and the third node N3 is in a high level state, the seventh transistor M7 is turned off and the eighth transistor M8 is turned on, so that the first operating voltage VGL is written to the signal output terminal OUT by the eighth transistor M8, and the signal output terminal OUT outputs a low level signal.

[0096] After this, the fourth stage t4 and the fifth stage t5 are alternately executed, and the signal output terminal OUT keeps outputting a low level signal until the signal provided by the third signal input terminal INPUT becomes a high level state, and the second shift register operates from the first stage t1 of the next period.

[0097] The circuit structure of the second shift register shown in Figure 4 is merely an example and does not limit the technical solution of the present application. The second shift register in the present application may have other circuit structures, and examples will not be provided here.

[0098] In some embodiments, the first shift register in the effective output circuit 2 has the same circuit structure as the second shift register in the multiplication control circuit 1. At this time, the overall circuit structure design of the gate driving circuit can be simplified.

[0099] For example, the first clock signal end CK of the first / second shift register located in the odd-numbered stage is coupled to the clock signal line CLK, and the second clock signal end CKB of the first / second shift register located in the even-numbered stage is coupled to the clock signal line CLKB.

[0100] 6a is a conceptual diagram of the circuit structure of the second shift register located in the first stage in the embodiment of the present application. As shown in FIG. 6a, the second shift register shown in FIG. 6a is an improvement based on the second shift register shown in FIG.

[0101] In some embodiments, in order to control the on / off of the "multiplication function" of the control gate driving circuit, a first switch circuit 106 is arranged in the second shift register B_1 located in the first stage in the multiplication control circuit 1, and the first switch circuit 106 is installed between the signal output circuit 104 in the second shift register located in the first stage and the second power supply terminal, and the first switch circuit 106 is for controlling the on / off between the signal output circuit 104 and the second power supply terminal.

[0102] Specifically, when the first switch circuit 106 is in a conductive state, the signal output circuit 104 in the second shift register located in the first stage is conductive to the second power supply terminal, allowing the second shift register located in the first stage to operate normally and turning on the "multiplication function" of the gate drive circuit; when the first switch circuit 106 is in a cut-off state, the signal output circuit 104 in the second shift register B_1 located in the first stage is cut off to the second power supply terminal, allowing the second shift register B_1 located in the first stage to operate normally and turning off the "multiplication function" of the gate drive circuit.

[0103] 6b is a conceptual diagram of a selectable circuit structure of the second shift register located in the first stage shown in FIG. 6a. As shown in FIG. 6b, the specific circuits of the signal write circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 in FIG. 6b can be those shown in FIG.

[0104] The situation shown in Figure 6b is for illustrative purposes only, and in the embodiments of the present application, the signal light circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 may adopt other circuit structures, which will not be listed here one by one.

[0105] 7a is another conceptual circuit diagram of the second shift register located at the first stage in the embodiment of the present application. As shown in FIG. 7a, the difference from the situation shown in FIG. 6a is that the first switch circuit 106 in FIG. 7a is installed between the second control circuit 103 and the second clock signal terminal CKB in the second shift register B_1 located at the first stage, and the first switch circuit 106 is used to control the on / off between the second control circuit 103 and the second clock signal terminal CKB.

[0106] Specifically, when the first switch circuit 106 is in a conductive state, the second control circuit 103 in the second shift register B_1 located at the first stage is conductive between the second clock signal terminal, so that the second shift register B_1 located at the first stage can operate normally and turn on the "multiplication function" of the gate drive circuit; when the first switch circuit 106 is in a cut-off state, the second control circuit 103 in the second shift register B_1 located at the first stage is cut off between the second clock signal terminal, so that the second shift register B_1 located at the first stage cannot operate normally and turn off the "multiplication function" of the gate drive circuit.

[0107] 7b is a conceptual diagram of a selectable circuit structure of the second shift register located in the first stage shown in FIG. 7a. As shown in FIG. 7b, the specific circuits of the signal write circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 in FIG. 7b can be those shown in FIG. 4.

[0108] The situation shown in Figure 7b is for illustrative purposes only, and in the embodiments of the present application, the signal light circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 may use other circuit structures, which will not be listed here one by one.

[0109] 6b and 7b, in some embodiments, the first switch circuit 106 includes an eleventh transistor M11. When the first switch circuit 106 is disposed between the signal output circuit 104 and the second power supply terminal, the control pole of the eleventh transistor M11 is coupled to the switch control terminal SC, the first pole of the eleventh transistor M11 is coupled to the second power supply terminal, and the second pole of the eleventh transistor M11 is coupled to the signal output circuit 104. When the first switch circuit 106 is disposed between the second control circuit 103 and the second clock signal terminal CKB, the control pole of the eleventh transistor M11 is coupled to the switch control terminal SC, the first pole of the eleventh transistor M11 is coupled to the second clock signal terminal CKB, and the second pole of the eleventh transistor M11 is coupled to the second control circuit 103.

[0110] 7b only exemplarily illustrates a situation in which the first switch circuit 106 (the eleventh transistor M11) is disposed between the second clock signal terminal and the first pole of the fourth transistor M4, but of course, the first switch circuit 106 (the eleventh transistor M11) may also be disposed between the second clock signal terminal and the control pole of the fifth transistor M5.

[0111] 8 is another conceptual circuit diagram of the second shift register located at the first stage in an embodiment of the present application. Different from the situation shown in FIGS. 6a to 7b, in the situation shown in FIG. 8, a first switch circuit 106 is disposed between the signal write circuit 101 and the signal input terminal INPUT, and the first switch circuit 106 is configured to control the on / off between the signal write circuit 101 and the signal input terminal INPUT according to the control of the first switch control signal provided by the first switch control terminal SC.

[0112] Specifically, when the first switch circuit 106 is in a conductive state, the signal write circuit 101 in the second shift register B_1 located in the first stage is conductive to the signal input terminal INPUT, allowing the second shift register B_1 located in the first stage to operate normally and turning on the "multiplication function" of the gate drive circuit; when the first switch circuit 106 is in a cut-off state, the signal write circuit 101 in the second shift register B_1 located in the first stage is cut off to the signal input terminal INPUT, allowing the second shift register B_1 located in the first stage to operate normally and turning off the "multiplication function" of the gate drive circuit.

[0113] In some embodiments, the first switch circuit 106 includes an eleventh transistor M11, a control pole of the eleventh transistor M11 is coupled to the first switch control terminal SC, a first pole of the eleventh transistor M11 is coupled to the signal input terminal INPUT, and a second pole of the eleventh transistor M11 is coupled to the signal write circuit 101.

[0114] When the signal write circuit 101 is disconnected from the signal input terminal INPUT, the terminal N6 in the signal write circuit 101 for connecting to the signal input terminal INPUT is in a floating state, which is prone to voltage deviation due to external interference. If the voltage at the terminal N6 in the signal write circuit 101 for connecting to the signal input terminal INPUT is biased to a high level, the second shift register in the first stage will generate an erroneous output, and the second shift registers in the subsequent stages will also generate erroneous outputs, causing the "multiplication function" of the gate drive circuit to be abnormally turned on.

[0115] In order to solve the technical problem of the abnormal activation of the "multiplication function" of the gate driver circuit, the embodiment of the present application provides a corresponding solution. Figure 9 is another conceptual circuit diagram of the second shift register located in the first stage in the embodiment of the present application. Unlike the situation shown in Figure 8, the second shift register located in the first stage in the multiplication control circuit in the situation shown in Figure 9 is provided with a first power supply circuit 107, which is coupled to the signal write circuit 101, the first switch circuit 106, the first power supply terminal, and the second switch control terminal SCB, and is configured to write a first operating voltage to the signal write circuit 101 according to the control of the second switch control signal provided by the second switch control terminal SCB.

[0116] In this embodiment, when the first switch circuit 106 controls the disconnection between the signal light circuit 101 and the signal input terminal INPUT, it can control the first power supply circuit 107 to operate according to the second switch control signal. Specifically, the first power supply circuit 107 writes the first operating voltage to the terminal N6 for coupling with the signal input terminal INPUT of the signal light circuit 101, thereby maintaining the voltage at this terminal stable and preventing the "multiplication function" of the gate driver circuit from being abnormally turned on.

[0117] As shown in FIG. 9, in some embodiments, the first power supply circuit 107 includes a fourteenth transistor M14, the control pole of which is coupled to the second switch control terminal SCB, the first pole of which is coupled to the first power supply terminal, and the second pole of which is coupled to the signal light circuit 101 and the first switch circuit 106.

[0118] Specific circuits of the signal write circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 in FIGS. 8 and 9 can be those shown in FIG.

[0119] 10 is a conceptual diagram of the circuit structure of another second shift register provided by an embodiment of the present application. As shown in FIG. 10, in some embodiments, the second shift register located in the first stage of the multiplication control circuit 1 is provided with a first switch circuit 106 and a second power supply circuit 109. The specific implementation of the first switch circuit can refer to the content of the previous embodiment (FIG. 10 only shows the first switch circuit 106 using the situation shown in FIG. 9), and will not be described again here. Only the second power supply circuit will be described in detail below.

[0120] The second power supply circuit 109 is coupled to the first power supply terminal, the signal output terminal OUT of the second shift register B_1 located in the first stage, and the second switch control terminal SCB, and the second power supply circuit 109 is configured to write a first operating voltage to the signal output terminal OUT of the second shift register B_1 located in the first stage according to the control of the second switch control signal provided by the second switch control terminal SCB.

[0121] When the first switch circuit 106 disconnects the signal output circuit from the second power supply terminal (the first switch circuit 106 shown in FIG. 6a is provided between the signal output circuit and the second power supply terminal), or disconnects the second control circuit 103 from the second clock signal terminal (the first switch circuit 106 shown in FIG. 7a is provided between the second control circuit 103 and the second clock signal terminal CKB), or disconnects the signal write circuit 101 from the signal input terminal INPUT (the first switch circuit 106 shown in FIG. 8 is provided between the signal write circuit 101 and the signal input terminal INPUT), the second power supply circuit 109 is controlled by the second switch control signal to write the first operating voltage to the signal output terminal OUT of the connected second shift register, thereby performing noise reduction processing on the signal output terminal OUT of the second shift register B_1 located in the first stage, and ultimately preventing the ``multiplication function'' of the gate drive circuit from being abnormally turned on.

[0122] In some embodiments, the second power supply circuit 109 includes a fifteenth transistor M15, a control pole of the fifteenth transistor M15 is coupled to the second switch control terminal SCB, a first pole of the fifteenth transistor M15 is coupled to the first power supply terminal, and a second pole of the fifteenth transistor M15 is coupled to the signal output terminal OUT of the second shift register B_1 located in the first stage.

[0123] 11 is another conceptual diagram of the circuit structure of the second shift register located in the first stage in the embodiment of the present application. As shown in FIG. 11, unlike the situation shown in FIGS. 9 and 10, the second shift register B_1 located in the first stage shown in FIG. 11 includes both a first power supply circuit 107 (including a fourteenth transistor M14) and a second power supply circuit 109 (including a fifteenth transistor M15).

[0124] In some embodiments, the gate driver circuit further includes an inverter circuit 108, the input terminal of which is coupled to the first switch control terminal SC, and the output terminal of which is coupled to the second switch control terminal SCB, and the inverter circuit 108 is configured to invert the signal at the input terminal. Specifically, the inverter circuit 108 inverts the first switch control signal provided by the first switch control terminal SC to obtain the second switch control signal. In this case, only one switch control signal needs to be provided by an external chip for the two different switch control terminals SC and SCB.

[0125] In some embodiments, the first signal input terminal INPUT and the second signal input terminal INPUT' of the first shift register A_1 located in the first stage in the valid output circuit 2 are the same signal input terminal, that is, the first shift register A_1 located in the first stage is provided with one signal input terminal, which is simultaneously coupled to the output control signal terminal and the signal output terminal OUT for the multiplication control circuit 1 to output the multiplication control signal.

[0126] 12A is a conceptual diagram of the circuit structure of a first shift register located at the first stage in an embodiment of the present application. As shown in FIG. 12A, in some embodiments, the first signal input terminal INPUT and the second signal input terminal INPUT' of the first shift register A_1 located at the first stage are different signal input terminals, and the first shift register A_1 located at the first stage further includes a second switch circuit 110 and a third switch circuit 111.

[0127] The second switch circuit 110 is disposed between the signal write circuit 101 and the first signal input terminal INPUT in the first shift register located in the first stage, and is coupled to the second signal input terminal INPUT', and is configured to control the on / off between the signal write circuit 101 and the first signal input terminal INPUT in response to control of the signal provided by the second signal input terminal INPUT'.

[0128] The third switch circuit 111 is disposed between the signal write circuit 101 and the second signal input terminal INPUT' in the first shift register A_1 located in the first stage, and is coupled to the first signal input terminal INPUT. The third switch circuit 111 is configured to control the on / off between the signal write circuit 101 and the second signal input terminal INPUT' in response to control of the signal provided by the first signal input terminal INPUT.

[0129] In some embodiments, the second switch circuit 110 includes a twelfth transistor M12, and the third switch circuit 111 includes a thirteenth transistor M13. A control pole of the twelfth transistor M12 is coupled to the second signal input terminal INPUT′, a first pole of the twelfth transistor M12 is coupled to the first signal input terminal INPUT, and a second pole of the twelfth transistor M12 is coupled to the signal write circuit 101. A control pole of the thirteenth transistor M13 is coupled to the first signal input terminal INPUT, a first pole of the thirteenth transistor M13 is coupled to the second signal input terminal INPUT′, and a second pole of the thirteenth transistor M13 is coupled to the signal write circuit 101.

[0130] 12b is a conceptual diagram of a selectable circuit structure based on the first shift register located in the first stage shown in FIG. 12a. As shown in FIG. 12b, the specific circuits of the signal write circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 in FIG. 12b can be those shown in FIG. 4.

[0131] The situation shown in Figure 12b is for illustrative purposes only, and in the embodiments of the present application, the signal light circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 may use other circuit structures, which will not be listed here one by one.

[0132] The present embodiment further provides a display substrate, which includes a gate driving circuit as provided in the above embodiment and a plurality of gate lines located in the display area, each gate line being coupled to a signal output terminal of a corresponding first shift register in the gate driving circuit. The details of the gate driving circuit can be referred to in the previous embodiment and will not be described again here.

[0133] The present invention further provides a display device including a display substrate provided by the above-described embodiment and an opposing substrate disposed opposite the display substrate, and the details of the display substrate can be referred to in the previous embodiment, and will not be described again here.

[0134] The display device may be any product or component having a display function, such as electronic paper, a liquid crystal display panel, an LED panel, an OLED panel, a mobile phone, a tablet PC, a television, a display, a notebook computer, a digital photo frame, or a navigation device.

[0135] 13 is a method flow diagram of the gate driving method provided by the embodiment of the present application. As shown in FIG. 13, the gate driving method is based on the gate driving circuit provided by the above embodiment, and includes the following steps:

[0136] Step S1: In response to the output control signal, the shift registers of each stage in the effective output circuit output the scanning signal in sequence, and the multiplication control circuit provides the multiplication control signal to the second signal input terminal of the first shift register located in the first stage in the effective output circuit after a preset time.

[0137] Step S2: In response to the multiplication control signal, the shift registers in each stage of the effective output circuit output the scanning signals in sequence.

[0138] For a specific description of steps S1 and S2, the corresponding contents in the previous embodiment can be referred to, and therefore a detailed description will not be given here.

[0139] The technical solution of the present application is to set up a multiplication control circuit based on the effective output circuit, and the multiplication control circuit provides a multiplication control signal to the second signal input terminal after a predetermined time has elapsed since receiving the output control signal, so that the effective output circuit realizes a multiplied output, that is, to raise the upper limit of the scanning frequency output by the gate driving circuit, and effectively prevent the appearance of flicker visible to the naked eye on the OLED caused by a PWM signal frequency that is too low.

[0140] The above-described embodiments are merely exemplary embodiments for explaining the principles of the present application, and the present application is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and scope of the present application, and such modifications and improvements are also considered to be included in the scope of the claims of the present application.

Claims

1. The effective output circuit includes a multiplication control circuit and an effective output circuit, the effective output circuit includes several cascaded first shift registers, the first shift register located at a first stage in the effective output circuit has a first signal input terminal and a second signal input terminal, the first signal input terminal is coupled to an output control signal line, and the second signal input terminal is coupled to the multiplication control circuit, the other first shift registers in the effective output circuit other than the first shift register located at the first stage are all provided with first cascade connection signal input terminals, the first cascade connection signal input terminals of the other first shift registers are respectively coupled to the signal output terminals of the corresponding first shift registers in the previous stages, the multiplication control circuit is coupled to the output control signal line, and is configured to provide a multiplication control signal to the second signal input terminal after a predetermined time has elapsed since receiving the output control signal in response to control of the output control signal provided by the output control signal line; a first shift register located in a first stage outputs a scanning signal in response to control of the output control signal, and a gate drive circuit is arranged to output a scanning signal in response to control of the multiplication control signal; a first switch circuit is disposed in a second shift register located at a first stage in the multiplication control circuit, the first switch circuit is disposed between the signal output circuit and the second power supply terminal, and is coupled to a first switch control terminal, and is configured to control on / off between the signal output circuit and the second power supply terminal according to the control of a first switch control signal provided by the first switch control terminal; or A first switch circuit is disposed in a second shift register located at a first stage in the multiplication control circuit, and the first switch circuit is disposed between the second control circuit and the second clock signal terminal, and is configured to control the on / off between the second control circuit and the second clock signal terminal according to the control of a first switch control signal provided by the first switch control terminal; or A first switch circuit is disposed in a second shift register located in a first stage of the multiplication control circuit, and the first switch circuit is disposed between the signal write circuit and the signal input terminal, coupled to a first switch control terminal, and configured to control on / off between the signal write circuit and the signal input terminal according to control of a first switch control signal provided by the first switch control terminal. Gate drive circuit.

2. the multiplication control circuit includes a number of cascaded second shift registers; a third signal input terminal is disposed in a second shift register located in a first stage of the multiplication control circuit, and the third signal input terminal is coupled to the output control signal line; In the multiplication control circuit, the other second shift registers other than the second shift register located at the first stage are all provided with second cascade connection signal input terminals, and the second cascade connection signal input terminals of the other second shift registers are respectively coupled to the signal output terminals of the corresponding second shift registers at the previous stages; The signal output terminal of the second shift register located at the final stage in the multiplication control circuit is coupled to the second signal input terminal.

2. The gate drive circuit of claim 1.

3. In the multiplication control circuit, the second shift register includes a signal write circuit, a first control circuit, a second control circuit, and a signal output circuit; the signal write circuit, the first control circuit, the second control circuit and the signal output circuit are coupled to a first node, the first control circuit and the second control circuit are both coupled to a second node, and the second control circuit and the signal output circuit are both coupled to a third node; the signal write circuit is coupled to a corresponding signal input terminal and a first clock signal terminal, and is configured to write a signal provided by the corresponding signal input terminal to the first node according to control of a first clock signal provided by the first clock signal terminal; the first control circuit is coupled to a first power supply terminal and the first clock signal terminal, and is configured to write a first operating voltage provided by the first power supply terminal to the second node in response to control of the first clock signal, and to write the first clock signal to the second node in response to control of a voltage at the first node; the second control circuit is coupled to a second power supply terminal and a second clock signal terminal, and is configured to write the second clock signal to the third node in response to controlling a voltage at the second node and a second clock signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the third node in response to controlling a voltage at the first node; the signal output circuit is coupled to the first power supply terminal and the second power supply terminal, and is configured to write the first operating voltage to the signal output terminal in response to controlling a voltage at the first node, and to write the second operating voltage to the signal output terminal in response to controlling a voltage at the third node; 2. The gate drive circuit of claim 1.

4. the signal write circuit includes a first transistor, the first control circuit includes a second transistor and a third transistor, the second control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor, and the signal output circuit includes a seventh transistor, an eighth transistor, and a second capacitor; a control pole of the first transistor is coupled to the first clock signal terminal, a first pole of the first transistor is coupled to the signal input terminal, and a second pole of the first transistor is coupled to the first node; a control pole of the second transistor is coupled to the first node, a first pole of the second transistor is coupled to the first clock signal terminal, and a second pole of the second transistor is coupled to the second node; a control pole of the third transistor is coupled to the first clock signal terminal, a first pole of the third transistor is coupled to the first power supply terminal, and a second pole of the third transistor is coupled to the second node; a control pole of the fourth transistor is coupled to the second node, a first pole of the fourth transistor is coupled to the second clock signal terminal, and a second pole of the fourth transistor is coupled to the first pole of the fifth transistor; a control pole of the fifth transistor is coupled to the second clock signal terminal, and a second pole of the fifth transistor is coupled to the third node; a control pole of the sixth transistor is coupled to the first node, a first pole of the sixth transistor is coupled to the second power supply terminal, and a second pole of the sixth transistor is coupled to the third node; a first end of the first capacitor coupled to the second node and a second end of the first capacitor coupled to a second pole of the fourth transistor; a control pole of the seventh transistor is coupled to the third node, a first pole of the seventh transistor is coupled to the second power supply terminal, and a second pole of the seventh transistor is coupled to the signal output terminal; a control pole of the eighth transistor is coupled to the first node, a first pole of the eighth transistor is coupled to the first power supply terminal, and a second pole of the eighth transistor is coupled to the signal output terminal; A first end of the second capacitor is coupled to the third node, and a second end of the third capacitor is coupled to the second power supply terminal.

4. The gate drive circuit of claim 3.

5. the second shift register further includes a noise reduction circuit; The noise reduction circuit is coupled to the first node, the second node, the second power supply terminal, and the second clock signal terminal, and is configured to perform noise reduction on the voltage at the first node in response to control of the second clock signal and the voltage at the second node.

4. The gate drive circuit of claim 3.

6. the noise reduction circuit includes a ninth transistor, a tenth transistor, and a third capacitor; a control pole of the ninth transistor is coupled to the second node, a first pole of the ninth transistor is coupled to the second power supply terminal, and a second pole of the ninth transistor is coupled to a first pole of the tenth transistor; a control pole of the tenth transistor is coupled to the second clock signal terminal, and a second pole of the tenth transistor is coupled to the first node; A first end of the third capacitor is coupled to the first node, and a second end of the third capacitor is coupled to the second clock signal end.

6. The gate drive circuit of claim 5.

7. The first shift register in the effective output circuit has the same circuit structure as the second shift register in the multiplication control circuit. The gate drive circuit according to any one of claims 3 to 6.

8. The first signal input terminal and the second signal input terminal of the first shift register located in the first stage of the effective output circuit are the same signal input terminal.

8. The gate drive circuit of claim 7.

9. the first signal input terminal and the second signal input terminal of the first shift register located in the first stage of the valid output circuit are different signal input terminals; A first shift register located in the first stage includes a second switch circuit and a third switch circuit, the second switch circuit is disposed between the signal write circuit and the first signal input terminal, is coupled to the second signal input terminal, and is configured to control ON / OFF between the signal write circuit and the first signal input terminal in response to control of a signal provided by the second signal input terminal; The third switch circuit is disposed between the signal write circuit and the second signal input terminal, is coupled to the first signal input terminal, and is configured to control on / off between the signal write circuit and the second signal input terminal according to the control of a signal provided by the first signal input terminal.

8. The gate drive circuit of claim 7.

10. the second switch circuit includes a twelfth transistor, and the third switch circuit includes a thirteenth transistor; a control pole of the twelfth transistor is coupled to the second signal input terminal, a first pole of the twelfth transistor is coupled to the first signal input terminal, and a second pole of the twelfth transistor is coupled to the signal write circuit; A control pole of the thirteenth transistor is coupled to the first signal input terminal, a first pole of the thirteenth transistor is coupled to the second signal input terminal, and a second pole of the thirteenth transistor is coupled to the signal write circuit.

10. The gate drive circuit of claim 9.

11. the first switch circuit includes an eleventh transistor; A control pole of the eleventh transistor is coupled to a first switch control terminal, a first pole of the eleventh transistor is coupled to the second power supply terminal, and a second pole of the eleventh transistor is coupled to the signal output circuit.

2. The gate drive circuit of claim 1.

12. the first switch circuit includes an eleventh transistor; A control pole of the eleventh transistor is coupled to a first switch control terminal, a first pole of the eleventh transistor is coupled to the second clock signal terminal, and a second pole of the eleventh transistor is coupled to the second control circuit.

2. The gate drive circuit of claim 1.

13. the first switch circuit includes an eleventh transistor; A control pole of the eleventh transistor is coupled to a first switch control terminal, a first pole of the eleventh transistor is coupled to the signal input terminal, and a second pole of the eleventh transistor is coupled to the signal write circuit.

2. The gate drive circuit of claim 1.

14. a first power supply circuit is disposed in a second shift register located in a first stage of the multiplication control circuit; the first power supply circuit is coupled to the signal light circuit, the first switch circuit, the first power supply terminal and the second switch control terminal, and is configured to write the first operating voltage to the signal light circuit according to control of the second switch control signal provided by the second switch control terminal; 14. The gate drive circuit of claim 13.

15. the first power supply circuit includes a fourteenth transistor; A control pole of the fourteenth transistor is coupled to the second switch control terminal, a first pole of the fourteenth transistor is coupled to the first power supply terminal, and a second pole of the fourteenth transistor is coupled to the signal write circuit and the first switch circuit.

15. The gate drive circuit of claim 14.

16. a second power supply circuit is disposed in a second shift register located in a first stage of the multiplication control circuit; The second power supply circuit is coupled to the first power supply terminal, the signal output terminal of the second shift register located in the first stage, and a second switch control terminal, and is configured to write the first operating voltage to the signal output terminal of the second shift register according to control of the second switch control signal provided by the second switch control terminal.

16. The gate drive circuit according to claim 11.

17. the second power supply circuit includes a fifteenth transistor; A control pole of the 15th transistor is coupled to the second switch control terminal, a first pole of the 15th transistor is coupled to the first power supply terminal, and a second pole of the 15th transistor is coupled to the signal output terminal of a second shift register located in a first stage.

17. The gate drive circuit of claim 16.

18. The inverter further includes an inverter circuit, the input terminal of which is coupled to the first switch control terminal, and the output terminal of which is coupled to the second switch control terminal.

15. The gate drive circuit of claim 14.

19. The gate driving circuit according to any one of claims 1 to 18 and a plurality of gate lines located within a display area, The gate line is coupled to a signal output terminal of a corresponding first shift register in the gate driving circuit. Display board.

20. a display substrate according to claim 19 and an opposing substrate disposed opposite to the display substrate; Display device.

21. Based on the gate drive circuit according to any one of claims 1 to 18, According to the output control signal, the shift registers of each stage in the effective output circuit sequentially output scanning signals, and the multiplication control circuit provides a multiplication control signal to the second signal input terminal of a first shift register located at a first stage in the effective output circuit after a preset time; a step of outputting a scanning signal in sequence from each stage of the shift register in the effective output circuit in response to the multiplication control signal; A gate driving method including:

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