Semiconductor device

Abstract

To provide a reliable semiconductor device.SOLUTION: A semiconductor device includes first to third transistors and a capacitor. In a first transistor, one of a source or a drain is provided with a first signal, the other is connected to a gate of a second transistor and one electrode of the capacitor, and the gate is provided with a second pulse signal. In the second transistor, one of a source or a drain is provided with a first pulse signal, and the other is connected to the other electrode of the capacitor and one of a source or a drain of a third transistor. In the third transistor, the other of the source or the drain is provided with a first potential, and a gate is provided with a second signal obtained by inverting the first signal. The first pulse signal is a clock signal, and the second pulse signal is a signal having a duty ratio of 55% or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. TECHNICAL FIELD One embodiment of the present invention relates to a drive circuit for a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and the like. , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof Semiconductor devices function by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Display devices include a variety of devices, including mobile information terminals such as smartphones and television sets. In recent years, there has been a demand for an improvement in the screen occupancy rate of devices that use display devices. Therefore, the display device has to narrow the area other than the display area (narrow the frame). In addition, it is required to fabricate a part or all of the driver circuit on the same substrate as the pixel portion. A system-on-panel is effective in meeting the above requirements. The transistors provided in the driver circuit and the transistors provided in the pixel portion are formed in the same process. It is desirable to manufacture the panel by this method, since it reduces the cost required for manufacturing the panel. In Patent Document 1 and Patent Document 2, an inverter and a shift register used in a drive circuit of a display device are The technology for configuring various circuits, such as transistors, with unipolar transistors has been disclosed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-325798 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-277652 Summary of the Invention [Problem to be solved by the invention]

[0005] A sequential circuit that outputs a pulse signal and is used in a driving circuit of a display device comprises a sequential circuit. If the electrical characteristics of the transistors, particularly the threshold voltage, change, the desired signal may not be transmitted. As a result, the image may not be displayed. There is a problem.

[0006] One embodiment of the present invention is to provide a highly reliable semiconductor device, a highly reliable display device, or an electronic device. One embodiment of the present invention is a semiconductor device that can realize a narrower frame of a display device, It is an object of the present invention to provide a display device or an electronic device. To provide a semiconductor device, a display device, or an electronic device that has high performance and can be manufactured at low cost. One embodiment of the present invention is a semiconductor device, a display device, or a semiconductor device having a novel structure. It is an object of the present invention to provide an electronic device that can reduce the problems of the prior art. One of the goals is to mitigate at least one of these issues.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including first to third transistors, a first capacitor, and first to fifth wirings. The first transistor has one of a source and a drain thereof. The other of the source and drain is electrically connected to the gate of the second transistor. and a gate electrically connected to one electrode of the first capacitor and a third wiring. One of the source and the drain of the second transistor is electrically connected to the fourth wiring. The other of the source and the drain is connected to the other electrode of the first capacitor and the other of the third transistor. The third transistor is electrically connected to one of the source and drain. The other end of the drain is electrically connected to the fifth wiring, and the gate is electrically connected to the second wiring. A first signal is applied to the first wiring, and a second signal, which is the inverse of the first signal, is applied to the second wiring. The second signal is applied to the fourth wire. The first pulse signal is applied to the fifth wire. A first potential is applied to the first wiring. A second pulse signal is applied to the third wiring. The pulse signal is a clock signal, and the second pulse signal has a duty ratio of 55% or less. It's a signal.

[0009] Another embodiment of the present invention is a semiconductor device including a control circuit, first to third transistors, and a first capacitor. The semiconductor device has a first transistor and first to fifth wirings. One of the source and the drain is electrically connected to a first wiring, and the other of the source and the drain is electrically connected to a second wiring. The gate of the second transistor is electrically connected to one electrode of the first capacitor, and the gate is The second transistor is electrically connected to a third wiring. the other of the source and drain is electrically connected to the fourth wiring, and the other of the source and drain is the other electrode of the first capacitor; and electrically connected to one of the source and drain of the third transistor. The other of the source and drain of the transistor is electrically connected to the fifth wiring, and the gate is connected to the second wiring. The control circuit outputs a first signal to the first wiring and The second signal, which is the inverse of the first signal, is output to the second wire. The fourth wire is the first pulse A signal is applied to the fifth wiring. A first potential is applied to the third wiring. Pulse signals are provided. The first pulse signal is a clock signal, and the second pulse signal is a is a signal with a duty cycle of 55% or less.

[0010] In the above, it is preferable to have a signal generating circuit that outputs a second pulse signal. At this time, it is preferable that a third pulse signal is given to the signal generating circuit and the control circuit. Furthermore, it is preferable that the third pulse signal has a duty ratio of 1% or less. It's nice.

[0011] In the above, the second pulse signal has a duty ratio of 1% or less. is preferred.

[0012] In the above, the signal generating circuit includes a fourth transistor, a fifth transistor, and In this case, the fourth transistor preferably has a source and a second capacitor. A second potential higher than the first potential is applied to one of the source and drain. The other is connected to the third wiring, one of the source and drain of the fifth transistor, and the second capacitor. The fifth transistor has a source and a drain electrically connected to one electrode thereof. The other electrode of the second capacitor is applied with a first potential. Furthermore, a third pulse signal is applied to the gate of the fourth transistor, and a fifth pulse signal is applied to the gate of the fifth transistor. A fourth pulse signal is applied to the gate of the transistor. The signal preferably has a duty ratio of 1% or less.

[0013] In the above, the second pulse signal is given to the third wiring and the control circuit. is preferred.

[0014] In the above, the first transistor includes a first semiconductor layer and a second semiconductor layer. It is preferable that the first gate and the second gate are overlapped with each other. The first gate and the second gate are preferably electrically connected.

[0015] In the above, the third transistor includes a second semiconductor layer and a second semiconductor layer. It is preferable that the third gate and the fourth gate are overlapped with each other. One of the third gate and the fourth gate is electrically connected to the second wiring, and the third gate and The other of the first and fourth gates is preferably electrically connected to a fifth wiring.

[0016] In the above, the fourth gate is preferably located below the second semiconductor layer. At this time, the third gate is electrically connected to the second wiring, and the fourth gate is It is preferable that the fifth wiring is electrically connected.

[0017] Another embodiment of the present invention is a display device including any of the above semiconductor devices and a pixel. The pixel includes a display element and a sixth transistor. The first transistor, the second transistor, and the third transistor are provided on the same plane. It is preferable that

[0018] In the above, the display element is preferably a liquid crystal element or a light-emitting element.

[0019] Another embodiment of the present invention is a display device including any of the above display devices, an antenna, a battery, a housing, and a At least one of a camera, a speaker, a microphone, a touch sensor, and an operation button; It is an electronic device. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a highly reliable semiconductor device, a display device, or an electronic device is provided. Alternatively, a semiconductor device, a display device, or an electronic device that can realize a narrower frame of a display device can be provided. Alternatively, a semiconductor device, a display device, or the like that is highly reliable and can be manufactured at low cost can be provided. Alternatively, a semiconductor device, a display device, or an electronic device having a novel structure can be provided. It is possible to provide an electronic device that at least alleviates at least one of the problems of the prior art. can.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a sequential circuit. [Figure 2] 2A is a diagram illustrating an example of the configuration of a sequential circuit, and FIG. 2B is a timing chart. [Figure 3] 3A to 3C are diagrams showing configuration examples of sequential circuits. [Figure 4] 4A and 4B are diagrams illustrating configuration examples of sequential circuits. [Figure 5] 5A and 5B are diagrams illustrating configuration examples of sequential circuits. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a sequential circuit. [Figure 7] FIG. 7 is a timing chart. [Figure 8] Fig. 8A is a diagram showing an example of the configuration of a sequential circuit, Fig. 8B is a circuit diagram of a shift register, and Fig. 8C is a timing chart. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a signal generating circuit. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a sequential circuit. [Figure 11] FIG. 11 is a timing chart. [Figure 12] Fig. 12A is a diagram showing an example of the configuration of a sequential circuit, Fig. 12B is a circuit diagram of a shift register, and Fig. 12C is a timing chart. [Figure 13] 13A to 13C are diagrams showing examples of the configuration of a transistor. [Figure 14] 14A to 14C are diagrams showing examples of the configuration of a transistor. [Figure 15] 15A to 15C are diagrams showing configuration examples of transistors and capacitors. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of a transistor and a capacitor. [Figure 17] 17A to 17F illustrate a method for manufacturing a transistor. [Figure 18] 18A to 18D illustrate a method for manufacturing a transistor. [Figure 19] 19A to 19C are diagrams showing examples of the configuration of a transistor. [Figure 20]Fig. 20A is a block diagram of a display device, and Fig. 20B and Fig. 20C are circuit diagrams of pixel circuits. [Figure 21] Figures 21A, 21C, and 21D are circuit diagrams of pixel circuits, and Figure 21B is a timing chart. [Figure 22] 22A and 22B are diagrams showing configuration examples of a display module. [Figure 23] 23A and 23B are diagrams showing configuration examples of electronic devices. [Figure 24] 24A to 24E are diagrams showing configuration examples of electronic devices. [Figure 25] 25A to 25G are diagrams showing configuration examples of electronic devices. [Figure 26] 26A to 26D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0025] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area The figures may be exaggerated for clarity and are not necessarily limited to that scale. I can't.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0027] A transistor is a type of semiconductor device that has the function of amplifying current or voltage and conducting electricity. Alternatively, a switching operation for controlling non-conduction can be realized. The transistor is an IGFET (Insulated Gate Field Effect Transistor). ct Transistor) and thin film transistor (TFT) Transistor).

[0028] In addition, the functions of "source" and "drain" can be different when using transistors with different polarities. , or may be swapped when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. It shall be possible to do so.

[0029] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "something that has some kind of electrical action" includes electrodes, wiring, and transistors. It has various functions such as switching elements such as resistors, coils, and capacitors. This includes elements, etc.

[0030] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0031] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packet ge) or a connector such as COG (Chip On Ground) is attached to the board. The IC mounted on the display panel module is called a display module. It may also be called a display panel or simply a display panel.

[0032] (Embodiment 1) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described.

[0033] [Configuration example 1] [Configuration Example 1-1] FIG. 1 shows a configuration example of a sequential circuit 10 of one embodiment of the present invention. The sequential circuit 10 includes a circuit 11 and The circuit 11 and the circuit 12 are electrically connected to each other through wirings 15a and 15b. The circuit 12 can also be called a control circuit.

[0034] In the following, unless otherwise specified, among the signals and potentials given to the sequential circuit 10, high The potential may be described as potential VDD, and the low potential as potential VSS.

[0035] The circuit 12 supplies the first potential to the wiring 15a in accordance with the potentials of the signals LIN and RIN. The first signal is output to the wiring 15b, and the second signal is output to the wiring 15c. The second signal is the inverse of the first signal. When the signals have two types of potentials, high potential and low potential, the signals are input from the circuit 12 to the wiring 15a. When a high potential is output, a low potential is output to the wiring 15b, and a low potential is output to the wiring 15a. When this is done, a high potential is output to the wiring 15b.

[0036] The circuit 11 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor C1. The transistor 21, the transistor 22, and the transistor 23 each have n The transistors 21, 22, and As the semiconductor in which the channel is formed, a metal oxide ( Hereinafter, a semiconductor material other than the oxide semiconductor can be preferably used. silicon (monocrystalline silicon, polycrystalline silicon, or amorphous silicon), germanium A semiconductor such as silicon or a compound semiconductor may be used.

[0037] The transistor 23 has a gate electrically connected to a wiring to which a signal BDG is applied, and a source One of the source and the drain is electrically connected to the wiring 15a, and the other of the source and the drain is connected to the transistor 15b. The gate of the transistor 22 is electrically connected to one electrode of the capacitor C1. The capacitor 22 has one of its source and drain electrically connected to a wiring to which a signal CLK is applied. The other of the source and drain is the other electrode of the capacitor C1, and the source and drain of the transistor 21. The gate of the transistor 21 is electrically connected to one of the wirings 15b. The other of the source and drain is connected to a potential VSS (also referred to as a first potential). The source and drain of the transistor 21 are electrically connected to a wiring. The other of the source and drain of the transistor 22 and the other electrode of the capacitor C1 are connected to the output terminal O The output terminal OUT is electrically connected to the output terminal UT. The part to be covered may be a part of the wiring or a part of the electrode.

[0038] The clock signal CLK is input to one of the source and drain of the transistor 22. The clock signal has a duty ratio (the number of high-side and low-side clocks in one period of the signal). A signal with a level potential (proportion of the period when the potential is high) of 45% or more and 55% or less is preferably used. More preferably, a clock signal with a duty ratio of 50% can be used. The duty ratio of the clock signal is not limited to the above, and This can be changed as appropriate depending on the operation method.

[0039] In this specification, a clock signal is a signal that alternates between high and low potentials, and , the interval between the rising edge of the potential and the rising edge of the next potential, or the interval between the falling edge of the potential and the falling edge of the next potential In this specification, a pulse signal is a signal in which the interval between the rising and falling edges is constant. A pulse signal is a signal whose potential changes periodically. These include signals that vary in frequency. For example, pulse signals include square waves, triangle waves, sawtooth waves, and sine waves. The clock signal includes signals whose potential changes periodically, such as waves. It can also be said to be one aspect of the number.

[0040] The signal CLK is a signal that is alternately given high and low potentials. It is preferable that the low potential of K is the same as the potential VSS. A high potential (for example, potential VDD) is applied to one of the source and drain of transistor 22. It may also be configured as follows.

[0041] The signal BDG given to the gate of the transistor 23 is a periodic pulse signal. At this time, it is preferable that the duty ratio of the signal BDG is low. G has a duty ratio of 60% or less, preferably 55% or less, and more preferably 50% or less. More preferably, it is 10% or less, even more preferably, it is 5% or less, even more preferably, it is 1% or less. A pulse signal can be used. The lower limit of the duty cycle of the signal BDG is The smaller the better, and the greater the value, the better.

[0042] A pulse signal with a small duty ratio is applied to the gate of the transistor 23. This makes it possible to suppress fluctuations in the threshold voltage of the transistor 23. For example, a constant potential (i.e., a duty ratio of 10) that is always high is applied to the gate of the transistor 23. 0% (which can be said to be a signal of 0%), the threshold of transistor 23 Since the low voltage is easily shifted to the positive side, the expected signal cannot be output from the sequential circuit 10. On the other hand, in one aspect of the present invention, the gate of the transistor 23 is Since the signal BDG having a small duty ratio is given, the fluctuation of the electrical characteristics of the transistor 23 As a result, a highly reliable sequential circuit 10 can be realized.

[0043] Here, the signal BDG is a signal generated using a signal for driving the circuit 12. Alternatively, the signal BDG may also serve as a signal for driving the circuit 12. This is preferable because a circuit for generating the signal BDG is provided outside the sequential circuit 10. Since this is not necessary, the configuration of the device to which the sequential circuit 10 is applied can be simplified.

[0044] The operation of the sequential circuit 10 will be described. A high potential is applied to the wiring 15a, and a low potential is applied to the wiring 15b. When a low potential is applied and the signal BDG becomes a high potential, the transistors 23 and 2 2 is in a conductive state (ON state), and transistor 21 is in a non-conductive state (OFF state). At this time, the output terminal OUT and the wiring to which the signal CLK is applied are brought into a conductive state.

[0045] In the circuit 11, the output terminal OUT and the gate of the transistor 22 are connected via a capacitor C1. Therefore, the potential of the output terminal OUT rises due to the bootstrap effect. As the voltage rises, the potential of the gate of the transistor 22 rises. If not, the potential is lower than the high potential of the signal CLK by the threshold voltage of the transistor 22. However, by having the capacitance C1, The potential of the gate of the transistor 22 is close to twice the potential VDD (for example, the potential VDD and the potential Since the threshold voltage of transistor 22 rises to a potential close to twice the difference between the VSS and VSS levels, The output terminal OUT is not affected by the high potential of the signal CLK (for example, the potential VDD This allows the output performance to be improved without increasing the number of power supply potentials. A highly efficient sequential circuit 10 can be realized.

[0046] Furthermore, a high potential is applied as the signal BDG, and the transistor 23 is in an on state. When a high potential is applied to the wiring 15a, the gate of the transistor 22 is connected to the transistor 23. At this time, a high potential is applied to the wiring 15a and a high potential of the signal BDG. When the potentials are equal (for example, both are at the potential VDD), the gate of transistor 22 A potential lower than the potential VDD by the threshold voltage of the transistor 23 is applied to the gate. When the signal CLK goes from a low potential to a high potential, the transistor 22 The potential of the gate of the transistor 23 (the potential of the other of the source and drain of the transistor 23) rises. Therefore, when the potential of the other of the source and drain of the transistor 23 exceeds the potential VDD, Since the transistor 23 is turned off, the gate of the transistor 22 and the wiring 15a are electrically connected. The gate of transistor 22 is electrically isolated from the In addition, the potential of the wiring 15a does not rise above the output potential (VDD) of the circuit 12. Therefore, a potential higher than the output potential is applied to the transistors and the like in the circuit 12 via the wiring 15a. This can improve the reliability of the sequential circuit 10. do.

[0047] On the other hand, when a low potential is applied to the wiring 15a and a high potential is applied to the wiring 15b, the transistor A low potential is applied to the gate of transistor 22 via transistor 23, turning transistor 22 on. In addition, the transistor 21 is turned on. At this time, the output terminal OUT The wiring to which the potential VSS is applied becomes conductive, and the potential VSS is output to the output terminal OUT. After that, the signal BDG is changed from a high potential to a low potential, and the transistor 23 is turned off. It is preferable to adopt this form.

[0048] FIG. 2A shows a more detailed configuration example of the sequential circuit 10 illustrated in FIG. The circuit 12 includes a transistor 31, a transistor 32, a transistor 33, and a transistor The transistors 31 to 34 have the above-mentioned n-channel In particular, it is preferable to apply a type of transistor to a semiconductor in which a channel is formed. It is preferable to use a transistor using a compound semiconductor.

[0049] The transistors 31 and 34 are turned on or off according to the potential of the signal LIN. The transistors 33 and 32 are turned on and off according to the potential of the signal RIN. Alternatively, non-conduction is selected.

[0050] When the signal LIN is at a high potential and the signal RIN is at a low potential, the transistor 31 is in an on state. The transistor 33 is turned off, and the wiring to which the potential VDD is applied and the wiring 15a are electrically connected. Also, transistor 34 is in the ON state and transistor 32 is in the OFF state. The wiring to which the potential VSS is applied is electrically connected to the wiring 15b. When LIN is at a low potential and signal RIN is at a high potential, transistor 31 is in an off state. The resistor 33 is turned on, and the wiring to which the potential VSS is applied and the wiring 15a are electrically connected. Also, transistor 34 is turned off and transistor 32 is turned on. The wiring to which the potential VDD is applied is electrically connected to the wiring 15b.

[0051] In the sequential circuit 10, when the signal LIN is at a high potential and the signal RIN is at a low potential, the wiring 15a The potential of the signal CLK is output to the output terminal OUT. On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the wiring 15a is at a low potential and the wiring The line 15b is at a high potential, and the output terminal OUT is electrically connected to the line to which the potential VSS is applied. To be continued.

[0052] The potentials of the signals LIN and RIN input to the sequential circuit 10 are alternately set to high and low potentials. By changing the signal CLK and the signal LIN, the output terminal OUT A pulse-shaped output signal is output to the output terminal OUT of the sequential circuit 10. By supplying an output signal to wiring (e.g., scanning lines) connected to multiple pixels, The circuit 10 can be used as part of a gate driver circuit.

[0053] FIG. 2B is a timing chart showing an example of a method for driving the sequential circuit 10 shown in FIG. 2A. FIG. 2B shows the signals LIN, RIN, BDG, CLK, node N, and the output The graph shows the time variation of the potential at the output terminal OUT. This corresponds to the node to which the gate of transistor 22 is connected (see FIG. 2A).

[0054] At time T1, the signals LIN and BDG are at a high potential, and the signals RIN and CLK are at a low potential. During the period T1 to T2, a high potential is output from the circuit 12 to the wiring 15a. Since the transistor 23 is on, the potential of the node N is changed from the potential of the wiring 15a to the potential of the transistor 23. The potential rises to a potential that is lowered by the threshold voltage of the transistor 23.

[0055] Subsequently, at time T2, the signal LIN goes to a low potential, and the signal CLK goes to a high potential. At this time, the transistors 31 to 34 in the circuit 12 are all turned off. Therefore, during the period T2-T3, the wiring 15a is in an electrically floating state. When the signal CLK goes high, the potential of the node N rises. The difference between the gate potential of transistor 23 and the potential of node N reaches the threshold voltage of transistor 23. Then, the transistor 23 is turned off, and the node N is brought into a floating state. As the potential of the gate of the transistor 23 rises, the high level of the signal CLK is output to the output terminal OUT. A potential is applied.

[0056] Subsequently, at time T3, the signal RIN goes to a high potential, and the signal CLK goes to a low potential. In the period T3 to T4, a high potential is output from the circuit 12 to the wiring 15b, and the transistor 2 On the other hand, a low potential is output to the wiring 15a, and the transistor 23 is turned on. Since the transistor 22 is in the OFF state, the output terminal OUT The potential VSS is applied.

[0057] Then, at time T4, the signal BDG becomes low potential, and the transistor 23 is turned off. become.

[0058] The above is a description of an example of the operation method of the sequential circuit 10.

[0059] Here, the voltage stress applied to the transistor 23 will be explained. Therefore, the high potential will be referred to as potential VDD and the low potential as potential VSS.

[0060] At time T1, a potential VDD is applied to the gate of the transistor 23, and the potential Vdd is applied to the wiring 15a side. When a potential VDD is applied to the electrode on the node N side, the transistor 23 is connected to the source. Subsequently, at time T2, the signal CLK changes from the potential VSS to the potential VDD, and Suppose the potential of node N rises to a potential VDD- and twice the potential VSS. Since the line 15a is floating and remains at the potential VDD, the transistor 23 In this case, the source and drain are switched, and the electrode connected to the wiring 15a becomes the source. At time T3, the potential VSS is applied to the wiring 15a, and the potential of the node N also decreases. In the transistor 23, the electrode on the wiring 15a side functions as the source. A transistor whose source and drain functions are interchanged during operation is called a bidirectional transistor (b The transistor can be called an i-direction transistor.

[0061] During the period T1-T2, the voltage (potential difference) applied between the gate and source of the transistor 23 is However, as the potential of node N rises, the transistor The voltage applied between the source and drain of the transistor 23 drops suddenly, so the voltage stress is immediately During the period T2-T3, the gate-source voltage of the transistor 23 is During the period T3-T4, the gate of the transistor 23 is turned on. The voltage between the gate and source of the transistor becomes VDD-VSS. Therefore, no voltage stress occurs between the gate and source of the transistor 23. The stress is applied to the wiring 15a when a low potential is applied to the wiring 15a and the signal BDG is at a high potential. Therefore, during the period when a low potential is applied to the wiring 15a, , the period during which the signal BDG is at a high potential is made as short as possible, so that the voltage of the transistor 23 This reduces stress and suppresses fluctuations in threshold voltage.

[0062] Here, the sequential circuit 10 can be used as a driving circuit for a display device. In this case, the output terminal OUT is connected to the line driver circuit of the display device. When connecting scanning lines connected to a plurality of pixels, the sequential circuit 10 outputs to the output terminal OUT. The duty ratio of the output signal is significantly smaller than that of the signal CLK. The potential input to 5a has a significantly longer period of low potential than high potential. Therefore, if a high constant potential is applied to the gate of the transistor 23, The period during which voltage stress is applied between the gate and source of transistor 23 becomes significantly longer, The threshold voltage of the transistor 23 is likely to fluctuate. , the gate of the transistor 23 is not supplied with a constant potential but with a pulse signal having a small duty ratio. Since the signal BDG is applied, the fluctuation of the threshold voltage of the transistor 23 is suitably suppressed. In particular, the signal BDG is used to cause the sequential circuit 10 to output a signal to the output terminal OUT. The potential is high only during the operation period (for example, the period T1-T4 in FIG. 2B), and during other periods It is preferable to apply a pulse signal that is always at a low potential. This allows the duplex of the signal BDG to be Reduce the ratio to 1% or less, preferably 0.5% or less, and more preferably 0.1% or less. The sequential circuit 10, and further, a semiconductor device, a display device, and an electronic device using the sequential circuit 10 This provides the device with extremely high reliability.

[0063] In addition, when the sequential circuit 10 is used as a driving circuit for a display device, the Transistors and transistors constituting the sequential circuit 10 (transistor 21, transistor It is preferable to provide the transistors 22 and 23 on the same substrate. The transistors provided in the element and the transistors constituting the sequential circuit 10 are fabricated in the same process. It is preferable to make it more

[0064] [Configuration Example 1-2] FIG. 3A shows an example of a sequential circuit 10a having a circuit 11 with a partially different configuration from that shown in FIG. 2A. Shows.

[0065] The transistor 21 included in the circuit 11 has a pair of gates (hereinafter referred to as a first gate and a second gate) The first gate of the transistor 21 is electrically connected to the wiring 15b. The second gate is connected to the other of its source and drain, and the potential VSS is applied. The source and drain of the transistor 22 are electrically connected to the wiring. The other end of the drain is electrically connected to the other electrode of the capacitor C1.

[0066] Here, when the sequential circuit 10a is used in a drive circuit of a display device, as described above, The duty ratio of the output signal output from the circuit 10a to the output terminal OUT is determined by the signal CLK etc. At this time, the transistor 21 is in a state where the period of time during which the transistor 21 is in an off state is significantly smaller than that during which the transistor 21 is in an off state. The period of time that the transistor 21 is in the on state is significantly longer. The period during which the high potential is applied is significantly longer than the period during which the low potential is applied. The threshold voltage of the transistor 21 is more likely to fluctuate than that of the transistor 22. Specifically, the threshold voltage of the transistor 21 is more positive than that of the transistor 22. It is easy to shift to

[0067] Therefore, one embodiment of the present invention is a transistor 21 in which a semiconductor layer is sandwiched between two adjacent transistors. A pair of gates is provided. One of the gates is connected to a wiring (voltage In other words, the transistor is electrically connected to the The transistor 21 can also be said to have a configuration in which one of the gates and the source are electrically connected to each other. By adopting such a configuration, the threshold voltage of the transistor 21 is shifted in the positive direction. Therefore, the sequential circuit 10a and the sequential circuit 10 The reliability of semiconductor devices, display devices, electronic devices, and the like using the compound a can be improved.

[0068] In addition, the transistor 21 is configured such that one of the gates is electrically connected to the source. This can also suitably prevent the threshold voltage from becoming a negative value. This makes it easy to make the transistor 21 normally-off. When the transistor 21 has a polarity-on characteristic, the voltage between the other gate and source of the transistor 21 is 0 When V is applied, leakage current occurs between the source and drain, and the potential of the output terminal OUT cannot be maintained. Therefore, in order to turn off the transistor 21, The other gate must be supplied with a potential lower than VSS, which requires multiple power supplies. On the other hand, the transistor 21 according to one embodiment of the present invention can stably achieve normally-off characteristics. Therefore, a sequential circuit 10a with high output performance can be realized without increasing the number of types of power supply potential. It is possible.

[0069] The transistor 21 has one gate and one source electrically connected to each other. This also has the effect of enhancing saturation. This makes it easier to design the circuit 11. 11 can be made into a circuit that can operate stably.

[0070] In this way, in the sequential circuit 10a, the period during which voltage stress is applied is significantly long. The transistor 21 is a bidirectional transistor in which one gate and one source are connected. The gate of the transistor 23, which functions as a resistor, is supplied with a pulse signal having a small duty ratio. As a result, in all three transistors constituting the circuit 11, As a result, it is possible to suppress the fluctuation of the threshold voltage. A sequential circuit 10a that is both reliable and reliable can be realized.

[0071] [Configuration Example 1-3] FIG. 3B shows an example of the configuration of a sequential circuit 10b. In the sequential circuit 10b, the circuit 12 is The transistor 33 has a pair of gates, one of which is connected to the source. A transistor is applied.

[0072] The transistor 33, like the transistor 21 of the circuit 11, Therefore, transistor 33 is a transistor that is in an on state for a significantly long period of time. By using the same structure as the transistor 21, fluctuations in the threshold voltage are suppressed, and the sequential circuit 1 This can improve the reliability of 0b.

[0073] [Configuration Example 1-4] FIG. 3C shows an example of the configuration of the sequential circuit 10c.

[0074] The sequential circuit 10c has not only the transistor 33 but also the transistor 34 included in the circuit 12. In the above case, a transistor having a pair of gates, one of which is connected to a source, is applied. are.

[0075] Compared to the transistor 33, the transistor 34 is turned on when the sequential circuit 10c is in operation. Although the period in which this state occurs is short, long-term operation can cause fluctuations in the threshold voltage. Therefore, by configuring the transistor 34 in the same manner as the transistor 33, Fluctuations in the low voltage are suppressed, and the reliability of the sequential circuit 10c can be improved.

[0076] In the sequential circuit 10c, the transistor 31, the transistor 32, and the transistor 22 , and the transistor 23 is a transistor having a pair of gates.

[0077] In a transistor having a pair of gates via a semiconductor layer, the pair of gates are electrically connected. By connecting the Compared to when a constant potential is applied to one side of the gate, the area where a channel is formed increases, and the source- The current that can flow between the drains (also called the on-state current) can be increased. Since the size of the transistor can be reduced while suppressing the decrease in the on-state current, the sequential circuit 10c, In this case, the area of the driving circuit using the sequential circuit 10c can be reduced. The transistor 22 and the transistor 23 have a larger current than the transistors provided in the circuit 12. Since a current supply capability is required, the transistors 22 and 23 are The application of transistors is extremely effective in reducing the area.

[0078] In addition, by using a transistor in which a pair of gates are electrically connected, it is possible to Compared to conventional transistors, it is easier to achieve normally-off electrical characteristics and has improved saturation. This provides the advantage of realizing a highly reliable sequential circuit 10c. It is possible.

[0079] Also, transistor 31, transistor 32, transistor 22, and transistor 2 3, by applying a transistor with high current supply capability, the operating frequency of the sequential circuit 10c It can also be increased.

[0080] In FIG. 3C, the transistors 31, 32, 22, and An example in which a pair of gates are electrically connected to each other is used as the transistor 23. However, the present invention is not limited to this, and the above transistor may be applied to one or more transistors. In particular, the transistors 22 and 23 included in the circuit 11 have a pair of gates. It is preferable to use a transistor in which the

[0081] [Configuration example 2] A sequential circuit having a different configuration from the above configuration example 1 will be described below.

[0082] [Configuration Example 2-1] FIG. 4A shows an example of the configuration of a sequential circuit 20. The sequential circuit 20 includes a circuit 11 and a circuit 13. The circuit 11 and the circuit 13 are electrically connected by a wiring 15a and a wiring 15b. The configuration of the circuit 11 can be based on the configuration example 1.

[0083] The signal BDG and the signal CLK1 are input to the circuit 11. The output terminal SROUT The signal BDG is input to the gate of the transistor 23. The signal CLK 1 is input to one of the source and drain of transistor 22 .

[0084] The circuit 13 includes transistors 41 to 47 and a capacitor C2. The signals LIN, CLK2, CLK3, RIN, and RES are input to The transistors 41 to 47 are the n-channel transistors described above. In particular, it is preferable to use an oxide semiconductor as the semiconductor in which the channel is formed. It is preferable to use a transistor having a

[0085] The circuit 13 outputs a first signal to the wiring 15a and a second signal to the wiring 15b in accordance with various input signals. The first signal is inverted to produce a second signal, which is then output.

[0086] The circuit 11 and the circuit 13 are connected to a potential VDD, which is a high potential, and a potential VS, which is a low potential. S is supplied.

[0087] Specifically, the transistor 41 has a gate connected to a line to which a signal LIN is applied, and a source connected to a line to which a signal LIN is applied. One of the source and drain of the transistor 46 is connected to the wiring 15a, and the other of the source and drain of the transistor 46 is connected to the wiring 15b. The other end is electrically connected to a wiring to which a potential VDD is applied. 42 is a wiring to which the signal CLK3 is applied at the gate, and one of the source and drain is a transistor. One of the source and drain of the resistor 43 is connected to a wiring to which a potential VDD is applied, and the other is connected to a wiring to which a potential VDD is applied. The transistor 43 has a gate to which a signal CLK2 is applied. The other of the source and drain is connected to the wiring 15b, one electrode of the capacitor C2, and the transistor The gates of the transistors 44 and 46 are electrically connected to each other. A wiring to which a signal RIN is applied, one of the source and drain is a wiring 15b, and the other is a potential The transistor 45 is electrically connected to a wiring to which VDD is applied. The port is a wiring to which a signal RES is applied, one of the source and drain is a wiring 15b, and the other is a wiring 15c. The transistors 46 are electrically connected to wirings to which a potential VDD is applied. The other of the source and drain is electrically connected to a wiring to which a potential VSS is applied. The transistor 47 has a gate connected to a wiring to which a signal LIN is applied, and a source and a drain connected to a wiring. One end is electrically connected to the wiring 15b, and the other end is electrically connected to the wiring to which the potential VSS is applied. The other electrode of the capacitor C2 is electrically connected to the wiring to which the potential VSS is applied. There are.

[0088] In the circuit 13 shown in FIG. 4A, the transistor 46 is a transistor having a pair of gates. The transistor 46 has a pair of gates, one of which is connected to a potential VS S is electrically connected to the wire.

[0089] The transistors 41 to 45, the transistor 47, and the transistor 22 At least one of the transistors 23 has a pair of electrically connected gates. In FIG. 4B, all of the transistors have a pair of An example is shown in which a transistor having an electrically connected gate is applied.

[0090] [Configuration Example 2-2] FIG. 5A shows an example of the configuration of a sequential circuit 30 having two output terminals. 1 has a configuration in which the circuit 11 in the sequential circuit 20 is replaced with a circuit 11a.

[0091] The circuit 11a receives the signals BDG, CLK1, and PWC. The path 11a is connected to the output terminal SROUT and the output terminal GOUT.

[0092] The circuit 11a has a configuration in which two circuits 11 are connected in parallel. 1, a transistor 22, a transistor 23, and a capacitor C1 constitute one circuit 11. However, the transistors 24, 25, and 26, and the capacitor C3 also The other circuit 11 is formed by the transistors 24 to 26 and the capacitor C3. The connection configuration is the same as that of the circuit 11 described above.

[0093] One of the source and drain of the transistor 25 is electrically connected to a wiring to which a signal PWC is applied. Also, one of the source and drain of the transistor 24 is connected to the transistor The other of the source and drain of the capacitor 25 and the other electrode of the capacitor C3 are connected to the output terminal GOUT. The gate of the transistor 26 is electrically connected to a wiring to which a signal BDG is applied. are actively connected.

[0094] In the circuit 11a, when a high potential is applied to the wiring 15a and a low potential is applied to the wiring 15b, The terminal SROUT has the potential of the signal CLK1, the output terminal GOUT has the potential of the signal PWC, On the other hand, when a low potential is applied to the wiring 15a and a high potential is applied to the wiring 15b, The output terminals SROUT and GOUT are both connected to the wiring to which the potential VSS is applied. electrically connected.

[0095] Here, when the sequential circuit 30 is used as a part of a gate driver circuit of a display device, The input terminal GOUT is used as the terminal to which the scanning line is connected, and the output terminal SROUT is used as the terminal to which the scanning line is connected. It can be used as a terminal to which the wiring input to the input circuit 30 is connected. The transistors 24 and 25 have a higher current than the transistors 21 and 22. It is preferable to use a transistor with a high current supply capacity. A large transistor can be applied to transistor 24 and transistor 25.

[0096] Here, the signal CLK1 and the signal PWC can be synchronized signals. In practice, a signal in which the high potential period and the low potential period coincide can be used. At this time, the high potential of the signal CLK1 and the signal PWC is the potential VDD, and the low potential is the potential If a signal that is VSS is used, it is necessary to increase the number of types of power supply potentials for driving the sequential circuit 30. This is preferable because it does not require

[0097] Furthermore, the signal CLK1 and the signal PWC may have different amplitudes. For example, A signal having a larger amplitude than the signal CLK1 can be used as the signal PWC. The signal PWC is a signal whose low potential is the potential VSS and whose high potential is a potential higher than the potential VDD. It is preferable to use a high potential signal. This makes it possible to output a high potential to the output terminal GOUT. In addition, the amplitude of the signal CLK1 can be reduced and the potential difference between the potential VDD and the potential VSS can be reduced. By reducing the voltage stress on the transistors that make up the sequential circuit 30, This suppresses fluctuations in the electrical characteristics of the transistor, including the threshold voltage. This can improve the reliability of the sequential circuit 30. The potential applied to the gate of the transistor 25 is a bootstrap effect due to the capacitance C3. Therefore, the potential of the transistor 25 can be set to a potential that is sufficiently higher than the potential VDD. The high potential of the signal PWC is output to the output terminal GOUT without being affected by the threshold voltage. You can exert your power.

[0098] The transistors 41 to 45, the transistor 47, and the transistor 22 , at least one of transistor 23, transistor 25, and transistor 26 A transistor having a pair of electrically connected gates may be applied to the above-mentioned circuit. All of the transistors have a pair of electrically connected gates. In particular, the transistor 22 and the transistor 25 are provided with a pair of It is preferable to use a transistor having an electrically connected gate and high current driving capability. I wish.

[0099] [Driver circuit configuration example] Below, we will explain a circuit that is composed of multiple stages of sequential circuits and functions as a shift register. An example of a driving circuit will be described.

[0100] [Driver circuit configuration example 1] First, an example of the configuration of a sequential circuit that can be used in a driver circuit will be described. The circuit diagram of the sequential circuit 30a is shown. The sequential circuit 30a is composed of the circuit 13, the circuit 11a, and the signal generation circuit. The signal generating circuit 14a generates the signal BDG.

[0101] The circuit 13 and the circuit 11a can be configured in accordance with the second example. The signal RIN illustrated in the configuration example 2 is set as the signal RIN1. The node to which the gate of the transistor 22 is connected is the node N1, and the gate of the transistor 25 is the node N2. The node to which is connected is assumed to be node N2.

[0102] The signal generating circuit 14a includes a transistor 51, a transistor 52, and a capacitor C4. The signal generating circuit 14a also receives the signal LIN and the signal RIN2.

[0103] The transistor 51 has a gate connected to a wiring to which a signal LIN is input, and a source and a drain connected to a wiring. One is a wiring to which a potential VDD is applied, and the other is a wiring for the source and drain of the transistor 52. The transistor 52 is electrically connected to one electrode of the capacitor C1 and one electrode of the capacitor C2. The gate is a wiring to which a signal RIN2 is input, and the other of the source and drain is a wiring to which a potential VSS is input. The capacitor C4 has its other electrode connected to the potential VSS The signal is electrically connected to a wiring to which a signal is applied.

[0104] In the signal generating circuit 14a, the other of the source and drain of the transistor 51 is connected to The signal BDG is output to the wiring connected to the gate of the transistor 23 in the circuit 11a. and the gate of transistor 26, respectively.

[0105] When the signal LIN is at a high potential and the signal RIN2 is at a low potential, the transistor 51 is in an on state. The transistor 52 is turned off, and the signal BDG output from the signal generating circuit 14a is a high voltage signal. On the other hand, when the signal LIN is at a low potential and the signal RIN2 is at a high potential, the transistor 51 is turned off, the transistor 52 is turned on, and the signal BDG is at a low potential.

[0106] Furthermore, a capacitor C4 is connected to the line through which the signal BDG is output. LIN and signal RIN2 are both at a low potential, and transistors 51 and 52 When both are in the OFF state, the wiring that outputs the signal BDG is electrically floating. Even when the signal generation is interrupted, the potential of the wiring can be maintained. It is not necessary for the generating circuit 14a to continuously output a high potential or a low potential as the signal BDG. Even if signals with a small duty ratio are used for signal LIN and signal RIN2, the potential of the wiring Specifically, the state in which the signal BDG is at a low potential can be maintained for a long period of time. Since the signal BDG can be maintained for a long period of time, it is possible to use a signal with an extremely small duty ratio. Furthermore, by providing the capacitor C4, the wiring through which the signal BDG is output can be This prevents the potential from fluctuating due to electrical noise. Since there is no need to turn on transistor 52 during the period when the potential is This reduces the voltage stress on MOSFET 2, thereby suppressing fluctuations in the threshold voltage.

[0107] By using such a signal generating circuit 14a, the signal BDG can be generated at a duty ratio of 5% or more. preferably 3% or less, more preferably 1% or less, even more preferably 0.5% or less, More preferably, it can be a pulse signal with a frequency of 0.1% or less. The sequential circuit 30a, and in turn, the semiconductor device, display device, and electronic device using the sequential circuit 30a, Extremely high reliability can be achieved.

[0108] In FIG. 6, a pair of transistors 51 and 52 included in the signal generating circuit 14a are This example shows an example in which a transistor having a gate electrically connected to the gate of the transistor is used. The transistors 51 and 52 are transistors each having one gate. In addition, one of the pair of gates of the transistor 52 is connected to the potential VSS. A transistor electrically connected to a wiring to which a voltage is applied may be used.

[0109] FIG. 7 shows a timing chart of an example of a method for driving the sequential circuit 30a. Then, the signal CLK1 (signal PWC), the signal CLK2, the signal CLK3, the signal RES, and the signal L IN, signal RIN1, signal RIN2, signal BDG, node N1 (node N2), and output 10A and 10B show schematic diagrams of the change in potential over time at the terminal SROUT (output terminal GOUT). Note that the signals CLK1 and PWC have the same waveform, so they are shown together. In addition, the time-varying potentials of the nodes N1 and N2 are roughly the same. Therefore, they are shown together. Also, the signals CLK1, CLK2, and CLK3 are The clock signals used are shifted by 1 / 4 cycle in this order.

[0110] At time T11, the signal LIN goes high and the signal RIN2 goes low, Subsequently, at time T12, the signal CLK1 and the signal PWC are set to high potential. As a result, the potentials of the nodes N1 and N2 rise. During period T14, a high potential is output to the output terminal SROUT and the output terminal GOUT. In this case, when the signal LIN is at a low potential and the signal RIN1 is at a high potential, the output terminal S A low potential is output to ROUT and the output terminal GOUT. Then, at time T15, When the signal RIN2 goes high, the signal BDG goes low. Even after the signal RIN2 becomes low potential, the signal BDG remains low potential.

[0111] Next, a driving circuit configured by connecting the above-mentioned sequential circuits 30a in multiple stages will be described. Reveal.

[0112] 8A is a diagram illustrating the input / output terminals of the sequential circuit 30a. The terminals are signal LIN, signal RIN1, signal RIN2, signal CLK1, signal CLK2, The signals CLK3, PWC, and RES are input and output terminals, respectively. The output terminal SROUT and the output terminal GOUT are also included.

[0113] 8B shows an example of the configuration of the driving circuit 40a. The driving circuit 40a is made up of a plurality of sequential circuits. FIG. 8B shows sequential circuits 30a_1 to 30a_6, and the following sequential circuits 30a_1 to 30a_6 are shown. The sequential circuits 30a_1 and 30a_2 are the same as the sequential circuit 30a illustrated in FIG. In the following, the n-th order from the side closest to the input of the driving circuit 40a will be The circuit will be expressed as a sequential circuit 30a_n (n is an integer equal to or greater than 1).

[0114] The sequential circuit 30a_n receives the signals CLK1, CLK2, and CLK3, and the signal C Any three of signals K1 to CK4 are used. As the PWC, any one of the signals PWC1 to PWC4 is used. The combination of signals CK1 to CK4 and signals PWC1 to PWC4 is the same for every four stages. That is, the sequential circuit 30a_n and the sequential circuit 30a_n+4 receive the signal CL The same signal is input as K1, signal CLK2, signal CLK3, and signal PWC.

[0115] The output terminal GOUT of the sequential circuit 30a_n is connected to a wiring OUTn (see FIG. 8B shows wiring OUT1 to wiring OUT6.

[0116] The sequential circuit 30a_1 receives the signal SP as the signal LIN. The sequential circuit 30a_n is connected to the output terminal of the sequential circuit 30a_n-1 as a signal LIN. The sequential circuit 30a_n receives the signal SROUT as input. The signal from the output terminal SROUT of the sequential circuit 30a_n+2 is input. The signal RIN2 is input to the sequential circuit 30a_n+3. The signal RIN2 is input to the sequential circuit 30a_n+3. is entered.

[0117] Specifically, the sequential circuit 30a_1 receives signals CK1, CK2, CK3, and PW. C1, signal RES, signal SP, the output signal of the sequential circuit 30a_3, and the output signal of the sequential circuit 30a_4 The sequential circuit 30a receives the output signals from the first and second sequential circuits 30a and 30b, respectively, and outputs an output signal to the wiring OUT1. _2 is a signal CK2, a signal CK3, a signal CK4, a signal PWC2, a signal RES, a sequential circuit 3 The output signal of the sequential circuit 30a_1, the output signal of the sequential circuit 30a_4, and the output signal of the sequential circuit 30a_5 The sequential circuit 30a_3 receives a signal CK3 and outputs an output signal to the wiring OUT2. , signal CK4, signal CK1, signal PWC3, signal RES, and the output signal of the sequential circuit 30a_2 , an output signal of the sequential circuit 30a_5 and an output signal of the sequential circuit 30a_6 are input, and The sequential circuit 30a_4 outputs an output signal to OUT3. CK2, signal PWC4, signal RES, the output signal of the sequential circuit 30a_3, the sequential circuit 30a_ 6 and an output signal of a sequential circuit 30a_7 (not shown), and The sequential circuit 30a_5 outputs an output signal to T4. 3, signal PWC1, signal RES, output signal of sequential circuit 30a_4, sequential circuit 30a_7( The output signal of the sequential circuit 30a_8 (not shown) and the output signal of the sequential circuit 30a_9 (not shown) are input to the , and outputs an output signal to the wiring OUT5. The sequential circuit 30a_6 outputs the signals CK2, CK3 , signal CK4, signal PWC2, signal RES, output signal of sequential circuit 30a_5, sequential circuit 3 0a_8 (not shown) and the output signal of the sequential circuit 30a_9 (not shown) is input, and an output signal is output to wiring OUT6.

[0118] 8C shows a timing chart relating to the driving method of the driving circuit 40a. In C, from the top, there are signals RES, SP, CK1 to CK4, and wiring OUT1 to OUT4. The transition of the potential change is shown for each of the lines OUT6. The signal PWC4 has the same phase and period as the signals CK1 to CK4. Since a clock signal is used, it is also shown.

[0119] Before time T0 shown in FIG. 8C, the signal SP is at a high potential, and the signal CK1 is at a low potential. At this time, a low potential is output to the wirings OUT1 to OUT6.

[0120] At time T0, the signal CK1 (signal PWC1) changes from low potential to high potential, A high potential is output from the circuit 30a_1 to the wiring OUT1. By K4 and signals PWC1 to PWC4, high voltage is sequentially applied to the wirings after the wiring OUT2. The digits are output.

[0121] The signals CK1 to CK4 are signals that are shifted by a quarter period in order. Similarly, the signals PWC1 to PWC4 are also signals that are shifted by a quarter period in order. Therefore, as shown in FIG. 8C, the wirings OUT1 to OUT6 are connected to the signals CK1, etc. The signals are output in the order of a quarter period.

[0122] In addition, during a period in which a high potential is output to the wirings OUT1 to OUT6, etc., The period is half a cycle. That is, there is a period when the wiring OUTn is at a high potential and a period when the wiring The period when OUTn+1 is at a high potential overlaps with the period when OUTn+2 is at a high potential. This allows for a longer period of time, so it is suitable for situations where the wiring load is heavy. In other words, it is preferable to use the driving circuit 40a for a display device with a large number of pixels or When the scanning line driving circuit is used for a display device with a large screen size, such a driving method is used. By using this, the charge / discharge period of the scanning line can be extended, which is preferable. 1 to CL4 are four-phase clock signals shifted by a quarter period, and the wiring OUT By setting the period during which n is at a high potential (selected) to a half period of the signal CK1, etc. In the above configuration, a period is provided in which two adjacent wirings are simultaneously selected, but the present invention is not limited to this. For example, by changing the clock signal period or duty ratio, three adjacent The above wirings may be selected simultaneously.

[0123] [Driver circuit configuration example 2] Hereinafter, a signal generating circuit having a configuration that is partially different from the signal generating circuit 14a illustrated in FIG. 6 will be described. An example of the path configuration will be described.

[0124] 9 shows a circuit diagram of the signal generating circuit 14b. The signal generating circuit 14b generates the signal BDG. The signal generating circuit 14b is a circuit that generates the signal R Since the configuration does not use IN2, the number of wires can be reduced.

[0125] The signal generating circuit 14b includes transistors 60 to 69, a transistor 71, and transistor 72.

[0126] The transistor 60 receives a signal LIN at its gate and has a voltage applied to one of its source and drain. The other end is electrically connected to the gate of transistor 71. The gate of the transistor 61 is supplied with a signal CLK3, and one of the source and drain is connected to a potential VDD. and the other is electrically connected to the gate of transistor 71. In this case, a signal RIN1 is applied to the gate, and a potential VDD is applied to one of the source and drain. The other end is electrically connected to the gate of transistor 71. A signal CLK1 is applied to the gate of the transistor 71. the other is electrically connected to one of the source and drain of the transistor 64 The transistor 64 has a gate to which a signal CLK2 is applied, and a source and a drain The other terminal is supplied with the potential VSS. The transistor 65 receives the signal CLK2 at its gate. , a potential VDD is applied to one of the source and drain of the transistor 66, and the other is applied to the source of the transistor 66. The transistor 66 receives a signal CLK1 at its gate and is electrically connected to one of its drains. is applied, and the other of the source and drain is electrically connected to the gate of transistor 72. The transistor 67 has a gate to which a signal LIN is applied and one of its source and drain is connected. The other terminal of the transistor 71 is electrically connected to the gate of the transistor 72, and the potential VSS is applied to the other terminal of the transistor 72. The transistor 68 has a gate to which a signal CLK3 is applied, and one of the source and drain of the transistor The other end of the transistor 6 is electrically connected to the gate of the transistor 72, and the other end of the transistor 6 is supplied with the potential VSS. 9 has a gate to which a signal RIN1 is applied and one of the source and drain of the transistor 72 The other end of the transistor 71 is electrically connected to the gate of the transistor 72, and the other end of the transistor 72 is applied with a potential VSS. A potential VDD is applied to one of the source and drain of transistor 72. One of the drains is electrically connected to a wiring to which a signal BDG is output. In the transistor 72, the potential VSS is applied to the other of the source and drain.

[0127] The signal generating circuit 14b has a duty ratio of 45% or more and 55% or less, preferably A signal BDG having a ratio of 45% to 51%, typically 50% to 51% is generated. Therefore, compared to when the potential VDD is used instead of the signal BDG, High reliability can be achieved.

[0128] By configuring the signal generating circuit 14b in this way, the signal to be supplied to the circuit 13 and the circuit 11a can be Therefore, the signal BDG can be generated using only the signals.

[0129] [Driver circuit configuration example 3] An example of the configuration of a drive circuit that does not use a signal generating circuit will be described below.

[0130] 10 shows a circuit diagram of the sequential circuit 30b. The sequential circuit 30b includes the signal generating circuit 14a. The main difference from the sequential circuit 30a is that it does not have a delay time.

[0131] The sequential circuit 30b is configured to use the signal CLK3 as the signal BDG. In comparison with the sequential circuit 30a, the signal RIN2 and the signal generating circuit 14a can be used. Therefore, the configuration can be simplified.

[0132] FIG. 11 shows a timing chart of an example of a method for driving the sequential circuit 30b. In 11, the signal CLK1 (signal PWC), the signal CLK2, the signal CLK3, the signal RES, the signal Signal LIN, signal RIN1, signal BDG, node N1 (node N2), and output terminal SRO 10A and 10B show a schematic diagram of the change in potential over time at UT (output terminal GOUT).

[0133] As shown in FIG. 11, the signal BDG and the signal CLK3 are the same signal.

[0134] At time T21, the signal BDG is at a high potential and the signal LIN becomes a high potential. The nodes N1 and N2 are at high potential. Then, at time T22, the signal CLK1 When the signal PWC goes high, the potentials of the nodes N1 and N2 rise. In addition, during the period T22-T24, a high potential is output to the output terminal SROUT and the output terminal GOUT. At this time, the signal BDG becomes low potential, and the transistor 23 and the transistor 26 is turned off, the nodes N1 and N2 are electrically floating. Subsequently, at time T24, the signal LIN is at a low potential, the signal RIN1 is at a high potential, The signal BDG becomes high potential, and the transistors 23 and 26 are turned on again. Therefore, the potentials of the nodes N1 and N2 drop to a low potential. A low potential is output to the output terminal ROUT and the output terminal GOUT. Then, at time T26, the signal BD G becomes low potential. After that, high potential and low potential are repeatedly input as the signal BDG. , since the signal LIN and the signal RIN1 are both at a low potential, the output terminal SROUT and the output terminal GOUT is maintained at a low potential.

[0135] Since the sequential circuit 30b is configured to use a clock signal as the signal BDG, the signal BD G has a duty ratio of 45% or more and 55% or less, preferably a duty ratio of 45% or more. A pulse signal with a frequency of 51% or less, typically 50%, can be used. Higher reliability can be achieved compared to when using the potential VDD instead of BDG. .

[0136] FIG. 12A is a diagram illustrating the input and output terminals of the sequential circuit 30b. The difference from the sequential circuit 30a is that it does not have a terminal to which the signal RIN2 is input. do.

[0137] FIG. 12B shows an example of the configuration of a drive circuit 40b using a sequential circuit 30b. The driving circuit 40b receives the signal RIN2 from the sequential circuit 30a_n in the driving circuit 40a. It has the same configuration except that it does not have wiring that connects to the input terminal.

[0138] FIG. 12C shows a timing chart relating to the driving method of the driving circuit 40b. As shown in FIG. 12C, the same output signal can be obtained by the same driving method as the driving circuit 40a. It is possible.

[0139] The driving circuit shown here is a shift register that sequentially supplies pulse signals to multiple wirings. Therefore, it can be suitably used in the gate driver circuit (scanning line driving circuit) of a display device. The shift register circuit can be applied not only to display devices but also to storage devices and the like. It can be suitably used in a variety of devices.

[0140] The above is a description of an example of the configuration of the drive circuit.

[0141] [Transistor configuration example] The following describes an example of the configuration of a transistor that can be used in the sequential circuit illustrated above. I will explain.

[0142] The transistors exemplified below have a pair of gates sandwiching a semiconductor layer, and one of the gates The gate is electrically connected to one of the source and drain. The transistor may be applied to the transistor 21 in the sequential circuit exemplified above. can be done.

[0143] Note that the connections of the gate, source, and drain of the transistors exemplified below can be changed. As a result, other transistors such as transistor 22 and transistor 23 in the sequential circuit exemplified above For example, a pair of gate electrodes can be fabricated. A transistor with two gates electrically connected to each other or a transistor with only one gate is called a By changing the connection part of the conductive layer and the shape (pattern) of the conductive layer, It can be prepared in the same way as a diaster.

[0144] [Configuration example 1] FIG. 13A shows a schematic top view of the transistor 100. FIG. 13B shows the transistor 100 shown in FIG. 13A. FIG. 13C corresponds to a cross-sectional view of the cut surface taken along the dashed line A1-A2 in FIG. It corresponds to a cross-sectional view taken along the dashed line A3-A2. Some of the components of the gate insulating layer 100 are omitted in the figure. The direction of the line A1-A2 includes the channel length direction of the transistor 100, and the dashed line A3-A2 The direction includes the channel width direction of the transistor 100. In the following drawings, some of the components will be omitted as in FIG. 13A. Let's say.

[0145] The transistor 100 is provided on a substrate 102, and includes a conductive layer 106a, an insulating layer 103, a semiconductor layer 104, and a gate insulating layer 106b. The conductive layer 106a is formed on the substrate 10. The conductive layer 106a is formed on the insulating layer 110. 2. The insulating layer 103 is provided to cover the substrate 102, the conductive layer 106a, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103 and is located in a region overlapping with the conductive layer 106a. The insulating layer 110 is provided to cover the semiconductor layer 108 and the insulating layer 103. The layer 112a is provided over the insulating layer 110 and overlaps with the semiconductor layer 108 and the conductive layer 106a. It has an area.

[0146] In addition, an insulating layer 118 is provided to cover the conductive layer 112a and the insulating layer 110.

[0147] In the transistor 100, a part of the conductive layer 112a is a first gate electrode (top gate A part of the conductive layer 106a functions as a second gate electrode ( A part of the insulating layer 110 functions as a first gate electrode. A part of the insulating layer 103 functions as a first gate insulating layer, and a part of the insulating layer 103 functions as a second gate insulating layer. do.

[0148] The semiconductor layer 108 preferably contains a metal oxide. For example, a metal oxide containing indium and M (M are gallium, aluminum, silicon, boron, yttrium, tin, copper, and vanadium. , beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Titanium, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium It is preferable that M is one or more selected from the group consisting of aluminum and zinc. One or more elements selected from aluminum, gallium, yttrium, and tin In particular, the semiconductor layer 108 is preferably an oxide containing indium, gallium, and zinc. It is preferable to use an indium tin and zinc oxide (IGZO). It is preferable to use an oxide containing indium, gallium, tin, and zinc. It is preferable to use an oxide containing

[0149] The semiconductor layer 108 has a region 108i that functions as a channel formation region and a region 108i that functions as a channel formation region. The pair of low resistance regions 108n are provided on either side of each other. One serves as the source region of transistor 100 and the other serves as the drain region. The region 108i overlaps with at least one of the conductive layer 112a and the conductive layer 106a. In FIG. 13B, the portion of the semiconductor layer 108 overlapping with the conductive layer 112a is defined as a channel formation region. Although the functional region 108i is shown, it does not actually overlap with the conductive layer 112a. When a channel is also formed in the portion overlapping with 106a (portion including low-resistance region 108n) There are also.

[0150] The low resistance region 108n is a region having a lower resistance and a higher carrier concentration than the channel formation region. High oxygen vacancy density regions, high impurity concentration regions, or n-type regions. It can be said that.

[0151] The low-resistance region 108n of the semiconductor layer 108 may be a region containing an impurity element. The impurity elements include, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and arsenic. Examples of rare gases include aluminum and rare gases such as helium. , neon, argon, krypton, and xenon. In particular, those containing boron or phosphorus It is also possible to contain two or more of these elements.

[0152] The process of adding impurities to the low resistance region 108n is carried out by using the conductive layer 112a as a mask. This can be done through layer 110.

[0153] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×1 0 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5x 10 22 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 End , 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0154] The concentration of impurities contained in the low resistance region 108n can be measured by, for example, secondary ion mass spectrometry (SIM) S: Secondary Ion Mass Spectrometry), or X-ray Photoelectron spectroscopy (XPS:X-ray Photoelectron Spectrosc) When XPS analysis is used, the surface side Or ion sputtering from the backside and analysis such as SIMS analysis or XPS analysis By combining this method with other methods, it is possible to determine the concentration distribution in the depth direction.

[0155] In particular, when hydrogen is used as an impurity element, an analytical method using neutron beams is used. It is good.

[0156] In addition, in the low resistance region 108n, the impurity element is present in an oxidized state. For example, boron, phosphorus, magnesium, aluminum, and silicon are used as impurity elements. It is preferable to use an element that is easily oxidized, such as silicon. Since the oxidized state of the fluorine-containing compound can be stably present by bonding with oxygen in the semiconductor layer 108, it can be easily oxidized in the subsequent process. When exposed to high temperatures (for example, above 400°C, above 600°C, or above 800°C) Even if there is an impurity element, the desorption is suppressed. As a result, many oxygen vacancies are generated in the low resistance region 108n. The low resistance region 108n has an extremely low resistance. It becomes an anti-state.

[0157] For example, when boron is used as the impurity element, the boron contained in the low resistance region 108n This is evident from the XPS analysis, where the B2O3 bond is This can be confirmed by observing the spectral peaks caused by the SiO2. Spectral peaks due to the existence of elemental boron are not observed or are not measurable. The peak intensity is so low that it is buried in the background noise observed near the lower limit of the and becomes smaller.

[0158] The region of the insulating layer 110 that overlaps with the low-resistance region 108n contains the above-described impurity element. At this time, the impurity elements in the insulating layer 110 may be present in the same manner as in the low-resistance region 108n. It is preferable that such easily oxidized elements exist in a state bonded with oxygen. Since it can bond with oxygen in the layer 110 and exist stably in an oxidized state, it can be easily used in a later process at high temperatures. In particular, the insulating layer 110 is prevented from being desorbed even when heated. When oxygen that can be separated (also called excess oxygen) is contained, the excess oxygen and the impurity element Oxygen is supplied from the insulating layer 110 to the low resistance region 108n to bond and stabilize it. In addition, the part of the insulating layer 110 containing the impurity element in an oxidized state can be suppressed. Since the portion is in a state where oxygen is difficult to diffuse, the insulating layer 110 is Oxygen is prevented from being supplied to the low resistance region 108n via the low resistance region 108n. It is also possible to prevent the resistance of the capacitor from increasing.

[0159] The insulating layer 103 is formed by stacking an insulating film 103a and an insulating film 103b from the substrate 102 side. At this time, the insulating film 103a located on the conductive layer 106a side has a laminated structure. It is preferable to use an insulating film that does not easily diffuse the metal elements contained in 106a. Inorganic insulating films such as silicon film, silicon nitride oxide film, aluminum oxide film, and hafnium oxide film In addition, the insulating film 103b in contact with the semiconductor layer 108 is preferably an oxygen insulating film. For example, a silicon oxide film or a silicon oxynitride film is preferably used. It is preferable to use a membrane or the like.

[0160] The insulating layer 103 may have a single layer structure or a laminated structure of three or more layers. 13B and 13C, the insulating layer 110 is shown as a single layer structure. However, it may have a laminated structure in which two or more layers are laminated.

[0161] 13B and 13C, an insulating layer 110 is provided to cover the edge of the semiconductor layer 108. For example, the insulating layer 110 may be formed on the conductive layer 112. The upper surface of the semiconductor layer 108 may be processed so as to roughly match the upper surface of the semiconductor layer 108. The upper surface of the low-resistance region 108n is in contact with the insulating layer 118.

[0162] In this specification, the term "top surface shapes are roughly the same" means that there is a slight difference between the two stacked layers. For example, the upper and lower layers are made of the same mask pattern. This includes cases where the entire surface or part of the surface is processed using the same mask pattern. The contours do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case, it is also said that the top surface shapes are roughly the same.

[0163] Furthermore, a layer functioning as a barrier film may be provided between the conductive layer 112a and the insulating layer 110. For example, a metal film, an alloy film, or a metal oxide film may be used as the conductive layer 112a and the insulating layer 110. The layer functioning as a barrier film may be at least an insulating layer 1. It is preferable to use a material that is less permeable to either oxygen or hydrogen, preferably both. This is preferable because oxygen diffuses from the semiconductor layer 108 to the conductive layer 112a side. This can prevent hydrogen from diffusing from the conductive layer 112a to the semiconductor layer 108. Therefore, the carrier density of the region 108i that functions as a channel formation region of the semiconductor layer 108 is The layer that can function as a barrier film can be made extremely low. Examples of the metal oxide film include an aluminum oxide film, a hafnium oxide film, and a hafnium aluminate film. oxide insulating films such as indium oxide, indium tin oxide, silicon A conductive oxide film such as an indium tin oxide film containing Zn can be used.

[0164] Alternatively, the metal oxide film functioning as a barrier film may contain the same element as the semiconductor layer 108. Preferably, the same sputtering target as that for the semiconductor layer 108 is used. It is preferable to use a metal oxide film formed by sputtering. When forming a metal oxide film, the metal oxide film is formed in an atmosphere containing oxygen gas, so that the insulating layer 110 Oxygen can be suitably added to the semiconductor layer 108 or the like. When the insulating layer 110 or the semiconductor layer 108 is formed for the purpose of supplying oxygen thereto, the metal The metal oxide film may be removed after it is formed.

[0165] 13A and 13B, the transistor 100 is formed on the insulating layer 118. The conductive layer 120a and the conductive layer 120b are provided. The conductive layer 120a serves as a source electrode and a drain electrode. The conductive layer 120b functions as one of the source and drain electrodes. The conductive layer 120a and the conductive layer 120b are formed on the insulating layer 118 and the insulating layer 110, respectively. In the opening 141a or the opening 141b, the low resistance region of the semiconductor layer 108 The area 108n is electrically connected to the area 108a.

[0166] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxynitride, silicon nitride, and silicon nitride oxide. , aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium An inorganic insulating material such as ammonium aluminate can be used.

[0167] 13A and 13C, in the channel width direction, the conductive layer 112a It is also preferable that the conductive layer 106a extends beyond the edge of the semiconductor layer 108. At this time, as shown in FIG. 13C, the entire semiconductor layer 108 in the channel width direction is covered with the insulating layer 110 and the insulating layer 103, and is covered with the conductive layer 112a and the conductive layer 106a. .

[0168] The transistor 100 includes a conductive layer 106a serving as a back gate, a source electrode, and a and the conductive layer 120b functioning as the other of the drain electrodes are electrically connected to each other. Specifically, the conductive layer 106a and the conductive layer 120b are electrically connected via the conductive layer 112b. are actively connected.

[0169] The conductive layer 112b is located on the same plane as the conductive layer 112a of the transistor 100 and has the same The conductive layer 112b and the conductive layer 106a are layers formed by processing a conductive film. 10 and an opening 143 formed in the insulating layer 103. The conductive layer 120b and the conductive layer 112b are formed in an opening 144 in the insulating layer 118. As a result, the source and drain of the transistor 100 One of the two is electrically connected to the back gate. Openings are formed in the insulating layer 118, the insulating layer 110, and the insulating layer 103, and the conductive layer 120b and the conductive layer 120c are formed. The conductive layer 112b is electrically connected to the conductive layer 106a via the conductive layer 112b, rather than directly connecting the conductive layer 106a. This allows the depth of the opening to be shallow, so that the step at the opening is low. This increases the step coverage of the conductive film that covers the opening, and the step is not completely covered by the conductive film. This can prevent problems such as the data being split.

[0170] 13A and 13C, the conductive layer 112a functioning as the top gate is formed by wiring. The conductive layer 112a and the conductive layer 106b are electrically connected to each other. 6b is an opening 142 formed in the insulating layer 110 and the insulating layer 103, and is electrically The conductive layer 106b is located on the same plane as the conductive layer 106a and is connected to the conductive layer 106a. It is preferable that the layer be formed by processing a conductive film.

[0171] For example, the transistor 100 may be connected to the transistor 21 in the sequential circuit 30 illustrated in FIG. 5A. When applied to the transistor 24, the conductive layer 106b is electrically connected to the wiring 15b. The conductive layer 120a corresponds to the wiring, and is electrically connected to the output terminal GOUT or the output terminal SROUT. The conductive layer 120b corresponds to a wiring to which the potential VSS is applied.

[0172] Here, an oxide film is used for the insulating film 103b of the insulating layer 103 that is in contact with the semiconductor layer 108. In particular, a silicon oxide film or a silicon oxynitride film capable of releasing oxygen by heating is preferable. It is preferable to use a silicon film, which can prevent the transistor 100 from being damaged during the manufacturing process. Oxygen released from the insulating layer 103 by the heat or the like is supplied to the semiconductor layer 108, and the semiconductor Since the oxygen vacancies in the semiconductor layer 108 can be reduced, the transistor 100 can be made more reliable. This can be achieved.

[0173] At this time, after the insulating film 103b is formed and before the semiconductor layer 108 is formed, the insulating film It is preferable to perform treatment to supply oxygen into the insulating film 103b. The treatment may be a plasma treatment or a heat treatment in an oxygen-containing atmosphere. Alternatively, the insulating film 1 is formed by ion doping or ion implantation. Alternatively, oxygen may be supplied to the insulating film 103b. The metal oxide film is formed by sputtering in an atmosphere containing Alternatively, oxygen may be supplied to the semiconductor layer 108, and then the metal oxide film may be removed. The semiconductor layer 108 is formed by sputtering in an atmosphere containing oxygen. The step of supplying oxygen to the insulating film 103b can be combined with the step of oxidizing the insulating film 103b.

[0174] When the insulating film 103b contains excess oxygen, the semiconductor layer 108 and the insulating film 103b In some cases, defect levels are easily generated at or near the interface with the second gate. When a high potential is applied to the conductive layer 106a functioning as a gate electrode, carriers are introduced into the defect level. There is a risk that electrons, which are atoms, are trapped and the threshold voltage of the transistor 100 is shifted to the positive side. However, in the transistor 100, the insulating layer 103 is provided between the first and second electrodes. A source potential (for example, a potential VSS) is applied to the conductive layer 106a, which functions as a second gate electrode. Therefore, carriers are generated at or near the interface between the semiconductor layer 108 and the insulating film 103b. As a result, even if the defect level exists, electrons are not trapped. Since the gate insulating film is less susceptible to leakage, a positive shift in the threshold voltage can be suitably suppressed. Therefore, the transistor 100 can be said to be an extremely reliable transistor.

[0175] [Configuration example 2] FIG. 14A shows a transistor 100A having a different configuration from the transistor 100. 14A is a schematic top view of the cross section taken along the dashed line B1-B2 in FIG. 14C is a cross-sectional view taken along the dashed line B3-B2 in FIG. 14A. is equivalent to

[0176] The transistor 100A includes a conductive layer 112a functioning as a top gate and a conductive layer 12 0b are electrically connected. The following mainly describes the differences and omits the explanation of the differences.

[0177] The conductive layer 120b and the conductive layer 112a are electrically connected to each other through an opening 144 formed in the insulating layer 118. are electrically connected.

[0178] Furthermore, a part of the conductive layer 106a functions as a wiring.

[0179] For example, the transistor 100A is replaced with the transistor 21 in the sequential circuit 30 illustrated in FIG. 5A. When applied to the transistor 24, the conductive layer 106a is electrically connected to the wiring 15b. The conductive layer 120a corresponds to the wiring to be connected to the output terminal GOUT or the output terminal SROUT. The conductive layer 120b corresponds to a wiring to which the potential VSS is applied. .

[0180] In the transistor 100A, the insulating layer 110 is made of an oxide that can release oxygen when heated. It is preferable to apply a film thereto. This prevents the film from being damaged during the manufacturing process of the transistor 100A. Oxygen released from the insulating layer 110 by heat or the like is supplied to the semiconductor layer 108, Since the oxygen vacancies in the 108 can be reduced, a highly reliable transistor 100A can be produced. It can be achieved.

[0181] At this time, after the insulating layer 110 is formed and before the conductive layer 112a and the like are formed, It is preferable to perform a process for supplying oxygen into the insulating layer 110. Examples of the treatment include plasma treatment and heat treatment in an oxygen-containing atmosphere. The insulating layer 110 is doped with an oxide film by ion doping or ion implantation. Alternatively, as described above, a source material may be supplied onto the insulating layer 110 in an atmosphere containing oxygen. By forming a metal oxide film by sputtering, oxygen is supplied into the insulating layer 110. The metal oxide film may be removed after the film formation, or may be removed by removing the conductive layer 112a and the insulating layer 112b. It may remain between 10 and 20.

[0182] If the insulating layer 110 contains excess oxygen, the semiconductor layer 108 and the insulating layer 110 may be damaged. Defect levels may be easily generated at or near the interface. When a high potential is applied to the transistor 100A, the threshold voltage of the transistor 100A shifts to the positive side. However, in the transistor 100A, the first gate electrode The active conductive layer 112a is supplied with a source potential (for example, potential VSS), so that the semiconductor layer Even if a defect level exists at or near the interface between the semiconductor layer 108 and the insulating layer 110, the transistor Therefore, the positive shift of the threshold voltage of the transistor 100A can be suppressed. The Transistor 100A is an extremely reliable transistor.

[0183] [Configuration Example 3] An example of a configuration having two transistors and a capacitor will be described below.

[0184] FIG. 15A shows a circuit in which a transistor 100, a transistor 150, and a capacitor 160 are connected. 15A. Also, FIG. 15B shows a schematic top view of the configuration of the device. 15C corresponds to a cross-sectional view of the cross section taken along the dashed line C3-C4 in FIG. 15A. FIG. 15B is a cross-sectional view of the transistor 150 in the channel length direction and the capacitance 15C includes a cross section of transistor 150 in the channel width direction.

[0185] 16 shows a top view of the device shown in FIG. 15A, excluding the conductive layers 120a to 120c. In FIG. 16, only the outlines of the conductive layers 120a to 120c are shown by dashed lines. is shown.

[0186] The transistor 100 has a second gate electrode (bottom gate electrode) located on the substrate 102 side. ) and one of the source and drain are electrically connected, and The configuration exemplified in 3A etc. can be used.

[0187] The transistor 150 is located on the same surface as the transistor 100 and is fabricated through the same process. The transistor 150 is a transistor having a pair of gates electrically connected to each other. It has the following configuration.

[0188] The capacitor 160 is fabricated through the same process as the transistor 100 and the transistor 150. It is possible.

[0189] The transistor 150 includes a conductive layer 106c, a part of which functions as a second gate electrode, and a A part of the insulating layer 103 functions as a second gate insulating layer, a part of the semiconductor layer 108a functions as a first gate insulating layer, and an insulating layer 110 which functions as a first gate insulating layer; The semiconductor layer 108a functions as a channel formation region. A region 108ai and a pair of low resistance regions 108an functioning as a source and a drain are provided. Has.

[0190] The transistor 150 is electrically connected to one of the pair of low-resistance regions 108an. The conductive layer 120c is electrically connected to the other conductive layer 120a. a is electrically connected to the low resistance region 108n (not shown) of the transistor 100. The conductive layer 120a and the conductive layer 120c are provided on the insulating layer 118 and the insulating layer 110, respectively. The opening 141d or the opening 141c is electrically connected to the low resistance region 108an. It has been done.

[0191] As shown in FIGS. 15A and 15C, the conductive layer 112c and the conductive layer 106c are In the opening 145 provided in the insulating layer 110 and the insulating layer 103, That is, the transistor 150 is formed by a pair of gate electrodes sandwiching a semiconductor layer 108a. The gate electrodes are electrically connected to each other.

[0192] With this configuration, the semiconductor layer 108a is electrically connected to the pair of gate electrodes. In this case, the conductive layer 106c and the conductive layer 112c are electrically surrounded by the field. The same potential is applied to the semiconductor layer 108a. Since an electric field can be effectively applied, the on-current of the transistor 150 can be increased. Therefore, it is possible to miniaturize the transistor 150.

[0193] The conductive layer 112c and the conductive layer 106c may not be connected to each other. A constant potential is applied to one of the pair of gate electrodes, and a signal for driving the transistor 150 is applied to the other. At this time, the potential applied to one of the gate electrodes of the transistor 15 It is also possible to control the threshold voltage when driving 0 with the other gate electrode.

[0194] The capacitor 160 is formed by a part of the semiconductor layer 108a (a part of the low resistance region 108an) and the insulating layer 1 The capacitor 160 is made up of a part of the insulating layer 103 and a part of the conductive layer 106c. The conductive layer 106c and the semiconductor layer 108a are paired. It functions as an electrode.

[0195] In addition, in the region where the low resistance region 108an and the conductive layer 106c overlap, the insulating layer 118 A plurality of openings 141e are provided in the insulating layer 110, and the conductive layer 141e is The conductive layer 120a and the low resistance region 108an are electrically connected. 20a serves as either the source or drain electrode of transistor 150. The conductive layer 120a functions as an auxiliary wiring (auxiliary electrode) of the capacitor 160. By contacting the resistive region 108an at multiple points, the contact resistance can be reduced. This is preferable because it can reduce the parasitic resistance of the capacitor 160. In addition, a configuration using the conductive layer 106c and the conductive layer 112c, or a configuration using the conductive layer 106c and the conductive layer The configuration using the conductive layer 106c and the low-resistance region 108an is different from the configuration using the conductive layer 106c and the low-resistance region 108an. By doing so, the thickness of the insulating layer that functions as the dielectric layer can be reduced, and the capacitance can be increased. can be done.

[0196] As shown in FIGS. 15A and 16, the conductive layer 120a is connected to the source of the transistor 100. one of the source and drain electrodes of the transistor 150; The island-shaped semiconductor layer 108a can also serve as one electrode of the capacitor 160. can serve as both a part of the transistor 150 and a part of the capacitor 160. By adopting such a configuration, the area occupied by the circuits shown in FIGS. 15A and 16 can be reduced. .

[0197] The configuration shown in FIG. 15A etc. can be applied to a part of the above sequential circuit. For example, When applied to the sequential circuit 30 illustrated in B, the transistor 21 or the transistor 24 Transistor 100 is connected to transistor 22 or transistor 25 and transistor 150. and capacitance 160 can be applied to capacitance C1 or capacitance C3. The conductive layer 106b corresponds to a wiring electrically connected to the wiring 15b, and the conductive layer 120a corresponds to an output wiring. The conductive layer 1 corresponds to the wiring electrically connected to the input terminal GOUT or the output terminal SROUT. The conductive layer 106c corresponds to the wiring to which the potential VSS is applied, and the conductive layer 106b corresponds to the transistor 23 or corresponds to the wiring electrically connected to the wiring 15a via the transistor 26, and the conductive layer 12 0c corresponds to the wiring to which the signal CLK1 or the signal PWC is applied.

[0198] The above is a description of an example of the configuration of a transistor.

[0199] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. 13A to 13C. The transistor 100 will be used as an example.

[0200] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method The CVD method can be a plasma chemical vapor deposition (PE CVD (Plasma Enhanced CVD) method, or thermal CVD method. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). anic CVD) method.

[0201] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coating, roll coating, curtain coating, knife coating It can be formed by the following methods.

[0202] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. The thin film may be processed by a method such as a masking method. The island-shaped thin film may be directly formed by the film method.

[0203] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0204] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Extreme ultraviolet (EUV) light or X-rays Also, instead of light used for exposure, an electron beam can be used. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, Masks are not required.

[0205] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0206] 17A to 18D are cross-sectional views illustrating steps in a manufacturing process of the transistor 100. 17A to 18D, the transistor 100 is shown to the left of the dashed line. A cross section in the channel length direction is shown on the right, and a cross section in the channel width direction is shown on the right.

[0207] [Formation of Conductive Layer 106a] A conductive film is formed on the substrate 102 and processed by etching to form a second gate electrode. A conductive layer 106a is formed to function as a conductive layer (FIG. 17A).

[0208] At this time, as shown in FIG. 17A, the edge of the conductive layer 106a is pressed so as to have a tapered shape. This improves the step coverage of the insulating layer 103 to be formed next. This can be done.

[0209] Furthermore, by using a conductive film containing copper as the conductive film that becomes the conductive layer 106a, the wiring resistance For example, it is possible to reduce the size of a large display device or a high-resolution display device. When the transistor 100 is used, a conductive film containing copper is used for the conductive layer 106a. Even when a conductive film containing copper is used for the conductive layer 106a, it is preferable that the insulating layer 1 Since the copper element is prevented from diffusing into the semiconductor layer 108 by the presence of the copper element 03, a highly reliable A transistor can be realized.

[0210] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106a (FIG. 17B The insulating layer 103 is formed by using a PECVD method, an ALD method, a sputtering method, or the like. It is possible.

[0211] Here, the insulating layer 103 is formed by laminating an insulating film 103a and an insulating film 103b. In particular, it is preferable that each insulating film constituting the insulating layer 103 be formed by the PECVD method. It's nice.

[0212] The insulating film 103a may be, for example, a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film. In particular, an insulating film containing nitrogen, such as a hafnium film or a hafnium nitride film, can be used. As 103a, a dense silicon nitride film formed using a PECVD apparatus is used. By using such an insulating film containing nitrogen, even if the thickness is thin, This can effectively prevent impurities from diffusing from the surface on which the film is formed.

[0213] In addition, by using an insulating film containing nitrogen as the insulating film 103a, Oxygen diffuses into the conductive layer 106a and the like, and the amount of oxygen contained in the insulating film 103b decreases. In addition, oxidation of the conductive layer 106a and the like can be suppressed.

[0214] In this specification, the term "oxynitride" refers to a compound having a higher oxygen content than nitrogen content. Nitride oxide refers to a material that contains more nitrogen than oxygen in its composition. For example, when it is written as silicon oxynitride, it means that the composition contains more oxygen than nitrogen. It refers to a material with a high content of silicon dioxide, and when it is written as silicon nitride oxide, it means that the composition contains more silicon dioxide than oxygen. This refers to materials with a higher nitrogen content than steel.

[0215] In addition, in this specification, oxynitrides and nitride oxides each containing the same element are described. When the oxide nitride is used, the oxygen content is higher than that of the nitride oxide. The materials include those that satisfy either one or both of the following conditions: In addition, the nitride oxide has a lower oxygen content than the oxynitride, and the nitrogen content The material includes materials that satisfy either one or both of the above. For example, oxynitride When silicon and silicon oxynitride are mentioned, silicon oxynitride includes silicon oxynitride. It includes materials that have a higher oxygen content and a lower nitrogen content than silicon. Silicon nitride oxide has a lower oxygen content than silicon oxynitride, and Contains high content materials.

[0216] The insulating film 103b in contact with the semiconductor layer 108 is formed of an insulating film containing oxide. It is particularly preferable to use an oxide film for the insulating film 103b. In addition, the insulating film 103b is a dense insulating film whose surface is resistant to adsorption of impurities such as water. It is also preferable to use a material with as few defects as possible and without impurities such as water or hydrogen. It is preferable to use a reduced insulating film.

[0217] The insulating film 103b may be, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. Silicon film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film um oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, oxide An insulating film containing at least one of a cerium film and a neodymium oxide film can be used. It is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating film 103b. .

[0218] The insulating film 103b preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating film 103b is an insulating material that can release oxygen when heated. For example, the insulating film 103b is formed in an oxygen atmosphere. The insulating film 103b after deposition is subjected to a heat treatment in an oxygen atmosphere, and the insulating film 103b After the film formation, a plasma treatment or the like is performed in an oxygen atmosphere, or an oxygen atmosphere is applied to the insulating film 103b. Oxygen can be supplied to the insulating film 103b by forming an oxide film under atmospheric conditions. In each of the above-mentioned treatments in which oxygen is supplied, it is possible to use a gas such as HCl instead of or in addition to oxygen. Alternatively, an oxidizing gas (such as nitrous oxide or ozone) may be used. An insulating film capable of releasing oxygen when heated is formed on the insulating film 103b, and then heat treatment is performed. By performing this, oxygen may be supplied from the insulating film into the insulating film 103b. Oxygen is supplied to the insulating film 103b by a method such as a doping method or an ion implantation method. That's fine.

[0219] Here, it is preferable that the insulating film 103b is formed thicker than the insulating film 103a. As a result, the amount of oxygen that can be released from the insulating film 103b by heating increases, and the amount of oxygen that can be released from the insulating film 103a increases. Therefore, the amount of hydrogen released from the semiconductor layer 108 is reduced. This allows for the supply of a large amount of oxygen while suppressing the generation of oxygen, resulting in the realization of highly reliable transistors. The thickness of the insulating film 103b is between 2 and 50 times that of the insulating film 103a, and preferably 3 times or more and 30 times or less, more preferably 5 times or more and 20 times or less, and even more preferably 7 times or more and 10 times or less. The thickness is preferably 5 times or less, typically about 10 times.

[0220] In addition, a metal oxide film that will become the semiconductor layer 108 is formed by sputtering in an atmosphere containing oxygen. When the insulating film 103b is formed by the above method, oxygen can be supplied to the insulating film 103b. After forming the metal oxide film to be the layer, heat treatment may be performed. The oxygen in the insulating film 103b can be effectively supplied to the metal oxide film, and the oxygen in the metal oxide film Defects can be reduced.

[0221] [Formation of Semiconductor Layer 108] Subsequently, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 17C).

[0222] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0223] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. In addition, the metal oxide film 108f has high purity and contains as few impurities as possible, such as hydrogen or water. In particular, the metal oxide film 108f is preferably a crystalline metal oxide film. It is preferable to use a nitride film.

[0224] In addition, when forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helix) are used. It is also possible to mix the metal oxide with other gases such as ammonium gas, argon gas, and xenon gas. The ratio of oxygen gas to the total deposition gas when depositing a film (hereinafter referred to as the oxygen flow ratio) is The higher the crystallinity of the metal oxide film, the more reliable the transistor will be. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate.

[0225] When forming the metal oxide film 108f, the higher the substrate temperature, the higher the crystallinity and the denser the metal oxide film 108f. On the other hand, the lower the substrate temperature, the lower the crystallinity and the lower the electrical conductivity. It is possible to form a high-quality metal oxide film.

[0226] The metal oxide film 108f is formed under the following conditions: the substrate temperature is preferably from room temperature to 250° C. The substrate temperature is preferably from room temperature to 200°C, more preferably from room temperature to 140°C. For example, if the substrate temperature is set to a temperature above room temperature and below 140°C, productivity will be increased, which is preferable. In addition, the metal oxide film is formed at room temperature or without intentional heating of the substrate. This makes it possible to reduce the crystallinity.

[0227] Here, the metal oxide film 108f is formed in an atmosphere containing oxygen, so that the metal oxide When the film 108f is formed, oxygen can be supplied to the insulating layer 103. In particular, the metal oxide film It is preferable that 108f is formed by sputtering in an atmosphere containing oxygen.

[0228] When forming the metal oxide film 108f, the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The amount of oxygen supplied to the metal oxide film 108f can be increased. The oxygen flow rate ratio or oxygen partial pressure affects the crystallinity of the metal oxide film 108f or the transistor current. This also affects the electrical characteristics, so it must be determined based on the required electrical characteristics of the transistor. For example, the oxygen flow rate ratio or oxygen partial pressure during the formation of the metal oxide film 108f can be The ratio is determined appropriately within the range of 10% or more and 100% or less, preferably 20% or more and 100% or less. That's fine.

[0229] Further, the metal oxide film 108f is formed by sputtering in an atmosphere containing oxygen. At this time, the surface of the insulating layer 103 is covered with the metal oxide film 108f in the process of being formed. As a result, part of the oxygen supplied to the insulating layer 103 during the formation of the metal oxide film 108f is transferred to the insulating layer 103. As a result, a large amount of the insulating layer 103 can be prevented from being desorbed to the outside. It can trap oxygen.

[0230] In addition, before the metal oxide film 108f is formed, water and hydrogen adsorbed on the surface of the insulating layer 103 are removed. Alternatively, a treatment for removing organic substances and a treatment for supplying oxygen into the insulating layer 103 may be performed. For example, it is preferable to carry out at least one of the above steps. The heat treatment can be performed at a temperature of 0.1° C. or less. It can be performed in a film forming apparatus. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, the heating may be carried out in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). Oxygen may be supplied to the insulating layer 103 by plasma treatment. When the plasma treatment is performed, organic substances on the surface of the insulating layer 103 are suitably removed while oxygen is supplied. After such a treatment, the surface of the insulating layer 103 can be continuously heated without being exposed to the atmosphere. It is preferable to subsequently deposit a metal oxide film 108f.

[0231] In addition, when the semiconductor layer 108 has a stacked structure in which a plurality of metal oxide films are stacked, After forming the metal oxide film, the surface is continuously formed without being exposed to the atmosphere. It is preferable to deposit the following metal oxide film.

[0232] When stacking multiple metal oxide films, sputtering targets with different compositions are used. Alternatively, a laminated film can be formed by laminating metal oxide films of different compositions. It is also possible to stack metal oxide films by using a targeting target and varying the film formation conditions. The film formation conditions include the type of film formation gas, the flow rate of the film formation gas, the flow rate ratio of the film formation gas, the size of the film formation chamber, and the like. These include pressure, substrate temperature (stage temperature), and power.

[0233] Here, when forming a metal oxide film by sputtering, the higher the power, the faster the film formation rate. In addition, the lower the power, the lower the film formation speed, and the film thickness and This reduces the in-plane variations in quality, etc. The metal oxide film was formed under high power conditions using a ion beam and the metal oxide film was formed under lower power conditions. By stacking the deposited metal oxide films, the film deposition rate is increased while reducing in-plane variations. It is possible.

[0234] For example, a metal oxide film is first formed on the insulating layer 103 at low power, and then a higher power is applied. Alternatively, a metal oxide film can be formed first at high power. Then, a metal oxide film can be deposited at a lower power. The deposition with high power and the deposition with low power may be repeated.

[0235] The higher the power during film formation, the denser (more dense) the metal oxide film formed. The lower the power during deposition, the lower the density of the metal oxide film obtained. During deposition, oxide films can supply more oxygen to the layers below them. It has the following characteristics:

[0236] For example, the semiconductor layer 108 may be a metal oxide film formed from the insulating layer 103 side with low power. In this way, the insulating layer 1 can be formed as a laminated structure of metal oxide films formed at high power. In addition, the semiconductor layer 108 can have a high density on the upper side. Therefore, the semiconductor layer 108 is etched when the openings 141a and 141b are formed later. Since chipping is less likely to occur, the manufacturing yield can be increased.

[0237] The semiconductor layer 108 is a metal oxide film formed from the insulating layer 103 side with high power. It is also possible to form a laminated structure of metal oxide films formed at low power. Therefore, it is possible to prevent impurities remaining in the film formation chamber from being mixed into the metal oxide film. In particular, by using high power at the beginning of the film formation process, impurities in the film can be reduced more effectively. Therefore, the metal oxide film formed at high power on the insulating layer 103 side can be formed. It is preferable to use an oxide film. When a metal oxide film is formed using electricity, the second layer of metal oxide film also tends to become dense. When a dense and highly crystalline film is formed in the first layer, the crystallinity of the second layer is reflected. In addition, by forming a metal oxide film on the second layer at low power, the Since oxygen can be directly supplied to the metal oxide film, the film This can reduce oxygen deficiency in the glass.

[0238] Subsequently, a part of the metal oxide film 108f is etched to form the island-shaped semiconductor layer 1 Form 08 (Figure 17D).

[0239] The metal oxide film 108f can be processed by wet etching or dry etching. In this case, the insulating layer 106 that does not overlap with the semiconductor layer 108 may be used. A part of the insulating layer 103 may be etched and thinned. In some cases, the insulating film 103b is removed by etching, and the surface of the insulating film 103a is exposed. .

[0240] Here, after the metal oxide film 108f is formed, or after the metal oxide film 108f is formed on the semiconductor layer 10 It is preferable to perform a heat treatment after processing into the metal oxide film 10. Remove hydrogen or water contained in 8f or semiconductor layer 108 or adsorbed on the surface. Furthermore, the metal oxide film 108f or the semiconductor layer 108 can be formed by the heat treatment. The quality may be improved (e.g., fewer defects, improved crystallinity, etc.).

[0241] Furthermore, the heat treatment removes the acid supplied to the insulating layer 103 during the formation of the metal oxide film 108f. The element can be diffused throughout the insulating layer 103. For example, the metal oxide film 108f can be Immediately after the film formation, the supplied oxygen is present in large amounts in the upper part of the insulating layer 103, and the oxygen is easily desorbed. In this case, in the process of forming the insulating layer 110 described later, There is a risk that a large amount of oxygen will be desorbed from the exposed surface of the insulating layer 103. By diffusing oxygen throughout the insulating layer 103 by heat treatment, the insulating layer 110 Even in this case, a state in which a large amount of oxygen is confined in the insulating layer 103 can be maintained.

[0242] Furthermore, the metal oxide film 108f or the semiconductor layer 103 is removed by the heat treatment. Oxygen can be supplied to the semiconductor layer 8. In this case, heat treatment is performed before processing into the semiconductor layer 108. By performing this, oxygen desorbed from the insulating layer 103 can be efficiently supplied to the metal oxide film 108f. Therefore, it is more preferable.

[0243] Furthermore, water, hydrogen, or the like can be released from the insulating layer 103 by the heat treatment. At this time, when heat treatment is performed after processing into the semiconductor layer 108, the insulating layer 103 is exposed. The water or hydrogen is easily desorbed from the insulating layer 103. and the like can be prevented from being supplied into the semiconductor layer 108. When the content of water or hydrogen is large, heat treatment is performed after processing into the semiconductor layer 108. It is preferable to do so.

[0244] The temperature of the heat treatment is typically 150°C or higher but lower than the distortion point of the substrate, or 200°C or higher but lower than the distortion point of the substrate. 00℃ or less, or 250℃ to 450℃ or 300℃ to 450℃ It is possible.

[0245] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in an atmosphere containing oxygen, the material may be heated in a dry air atmosphere. It is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is preferably carried out in an electric furnace or an RTA (Rapid Thermal Annealing) furnace. By using an RTA device, the heating time can be shortened. It is possible.

[0246] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0247] [Formation of insulating layer 110] Subsequently, the insulating layer 110 is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 17). E).

[0248] The insulating film that constitutes the insulating layer 110 is preferably formed by the PECVD method.

[0249] The insulating layer 110 may be, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film aluminum film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, ceramic oxide film For example, an insulating layer containing at least one of a lithium oxide film and a neodymium oxide film can be used.

[0250] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films. The insulating layer 110 may have a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is preferably an insulating film capable of releasing oxygen. It is preferable to have

[0251] Here, as the insulating layer 110, a laminated film in which three insulating films formed under different film forming conditions are laminated is used. In this case, it is particularly preferable to use a silicon oxide film or a silicon nitride film for all three insulating films. It is preferable to use a silicon oxynitride film.

[0252] The first insulating film is formed on the semiconductor layer 108, so it is necessary to keep the first insulating film as close to the semiconductor layer 108 as possible. It is preferable that the film is formed under conditions that do not cause damage. For example, compared to other films, Film formation can be performed under conditions where the film formation speed (also called film formation rate) is sufficiently low. For example, When forming a silicon oxynitride film as the insulating film of the first layer by the plasma CVD method, The deposition gas containing silicon, such as silane or disilane, is used in the film formation under the conditions of high pressure. The film formation rate is reduced by reducing the flow rate of the gas, and the damage to the semiconductor layer 108 is reduced. The image can be made extremely small.

[0253] The second insulating film is formed under conditions of a higher film formation rate than the first insulating film. This makes it possible to improve productivity.

[0254] The third insulating layer has reduced surface defects and absorbs impurities such as water from the air. It is preferable that the insulating film is extremely dense and difficult to adhere. For example, like the first insulating film, The film can be formed under conditions where the film formation rate is sufficiently low.

[0255] Furthermore, before the insulating layer 110 is formed, the surface of the semiconductor layer 108 is subjected to plasma treatment. By the plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 are removed. Therefore, the impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced. Since the impurities in the semiconductor layer 1 can be reduced, a highly reliable transistor can be realized. The surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. In some cases, plasma treatment is suitable. For example, oxygen, ozone, nitrogen, nitrous oxide, The plasma treatment can be carried out in an atmosphere containing one or more of the following: The deposition of the insulating layer 110 is preferably carried out successively without exposure to the atmosphere.

[0256] Here, it is preferable to perform heat treatment after the insulating layer 110 is formed. This makes it possible to remove hydrogen or water contained in the insulating layer 110 or adsorbed on the surface. In addition, defects in the insulating layer 110 can be reduced.

[0257] Furthermore, oxygen contained in the insulating layer 103 is released by the heat treatment, and the semiconductor layer 108 For example, when the insulating layer 110 is formed, the semiconductor layer 108 may be damaged. This may result in defects such as oxygen vacancies in the semiconductor layer 108. Therefore, by performing heat treatment after the insulating layer 110 is formed, oxygen supplied from the insulating layer 103 can be easily removed. This reduces oxygen vacancies in the semiconductor layer 108, and enables the realization of a highly reliable transistor. do.

[0258] The conditions for the heat treatment may be as described above.

[0259] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0260] [Formation of opening 143] Subsequently, the insulating layer 110 and the insulating layer 103 are partially etched to form the conductive layer 106. An opening 143 reaching a is formed.

[0261] [Formation of Conductive Layer 112a and Conductive Layer 112b] Next, a conductive film is formed on the insulating layer 110 so as to cover the opening 143. By processing into a desired shape, conductive layers 112a and 112b are formed (FIG. 17F ).

[0262] The conductive layers 112a and 112b are preferably made of a low-resistance metal or alloy material. In addition, the conductive layers 112a and 112b are preferably made of a material that does not easily release hydrogen. It is preferable to use a material that is easy to disperse hydrogen. The conductive layer 112b is preferably formed using a material that is not easily oxidized.

[0263] For example, the conductive layer 112a and the conductive layer 112b are formed by sputtering a metal or alloy. It is preferable to form the film by sputtering using a target.

[0264] For example, the conductive layers 112a and 112b may be made of a material that is resistant to oxidation and hydrogen diffusion. It is preferable to use a laminated film in which a low-resistance conductive film and a low-resistance conductive film are laminated.

[0265] In this way, the top and side surfaces of the semiconductor layer 108 and the insulating layer 110 are removed without etching. By forming a structure in which the insulating layer 103 is covered with the insulating layer 110, the conductive layers 112a and the like can be formed. During etching of the film, a part of the semiconductor layer 108 or the insulating layer 103 is etched. , it is possible to prevent the film from becoming thin.

[0266] When the conductive layers 112a and 112b are processed, a part of the insulating layer 110 is etched. It may be etched and thinned.

[0267] When forming the opening 143 shown in FIGS. 13A to 13C, the conductive layer 112a Before forming the conductive film that will become the conductive layer 112b, the insulating layer 110 and a part of the insulating layer 103 are The conductive layer 106a is then etched to form an opening 143 that reaches the conductive layer 106a. 3, a conductive film to be the conductive layer 112a and the conductive layer 112b is formed on the insulating layer 110. The conductive film is then processed to form conductive layers 112a and 112b. As a result, the conductive layer 112b electrically connected to the conductive layer 106a in the opening 143 can be formed.

[0268] [Fueling of impurity elements] Next, using the conductive layer 112a as a mask, impurities are applied to the semiconductor layer 108 through the insulating layer 110. A process of supplying (adding or injecting) a material element is performed (Figure 18A). A low resistance region 108n is formed in the region of the semiconductor layer 108 that is not covered with the conductive layer 112a. At this time, the impurity element is introduced into the region of the semiconductor layer 108 that overlaps with the conductive layer 112a. To minimize the supply, the material or thickness of the conductive layer 112a or the like that serves as the mask should be adjusted. It is preferable to determine the conditions for the supplying process of the impurity element taking this into consideration. A channel having a sufficiently reduced impurity concentration is formed in the region of the layer 108 that overlaps with the conductive layer 112a. A region can be formed.

[0269] The supplying process of the impurity element is performed by plasma in an atmosphere containing the impurity element to be supplied. For example, plating in an atmosphere containing hydrogen gas or ammonia gas is By performing the Zuma treatment, hydrogen is supplied to the semiconductor layer 108 through the insulating layer 110. In particular, it is preferable to perform plasma treatment in an atmosphere containing hydrogen gas.

[0270] In FIG. 18A, the semiconductor layer 10 is exposed to plasma 140 through the insulating layer 110. 8.

[0271] The plasma 140 can be generated by a dry etching device, an up A CVD apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, etc. can be used.

[0272] After the plasma treatment, the insulating layer 118 is formed without exposure to the atmosphere. At this time, it is preferable to deposit the insulating layer 118 in the same deposition chamber of the deposition apparatus. Therefore, it is preferable to perform the plasma treatment and the film formation treatment successively. A processing gas containing a nitrogen gas is supplied to perform plasma processing, and then a film formation gas is supplied into the film formation chamber. The insulating layer 118 can be formed by supplying the plasma treatment and the film formation treatment. It is preferable that the temperature of the substrate (the temperature of the stage that holds the substrate) is the same.

[0273] In one embodiment of the present invention, an impurity element is supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, the impurity element can be The damage to the semiconductor layer 108 during supply is reduced, and the crystallinity is not impaired. Therefore, in cases where the electrical resistance increases due to a decrease in crystallinity, It is suitable.

[0274] Alternatively, the impurity element may be supplied by plasma ion doping or ion implantation. These methods can be used to obtain a concentration profile in the depth direction by The plasma ions can be controlled with high precision by adjusting the acceleration voltage and dose. By using the doping method, productivity can be increased. By using the ion implantation method, the purity of the supplied impurity element can be increased.

[0275] In the supplying process of the impurity element, the interface between the semiconductor layer 108 and the insulating layer 110 or the semiconductor The portion of the dielectric layer 108 near the interface or the portion of the insulating layer 110 near the interface is the most It is preferable to control the treatment conditions so that the concentration is as high as possible. This allows the impurity elements to be supplied to both the semiconductor layer 108 and the insulating layer 110 at optimum concentrations. Cut.

[0276] Impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Examples of rare gases include ammonium, magnesium, silicon, and rare gases. Examples include helium, neon, argon, krypton, and xenon. Preferably, boron, phosphorus, aluminum, magnesium, or silicon is used.

[0277] As the source gas of the impurity element, a gas containing the above impurity element can be used. When supplying uran, B2H6 gas or BF3 gas can be typically used. When supplying phosphorus, PH3 gas can be typically used. A mixed gas obtained by diluting these source gases with a rare gas may also be used.

[0278] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and a solid or liquid vaporized by heating can also be used. That's fine.

[0279] The addition of impurity elements is determined in consideration of the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. The amount of irradiation can be controlled by setting conditions such as the acceleration voltage or the dose.

[0280] [Formation of insulating layer 118] Next, the insulating layer 110, the conductive layer 112a, the conductive layer 112b, etc. are covered with the insulating layer 111. Form 8 (Figure 18B).

[0281] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the low resistance The impurities contained in the region 108n etc. are introduced into the peripheral region including the channel forming region of the semiconductor layer 108. There is a risk of diffusion or an increase in the electrical resistance of the low resistance region 108n. Therefore, the temperature at which the insulating layer 118 is formed should be determined taking these factors into consideration. .

[0282] For example, the temperature at which the insulating layer 118 is formed is preferably 150° C. or higher and 550° C. or lower. Preferably, the temperature is 160°C or higher and 500°C or lower, more preferably 180°C or higher and 450°C or lower, and even more preferably The insulating layer 118 is formed at a low temperature, preferably at a temperature of 250° C. or higher and 400° C. or lower. This allows good electrical characteristics to be imparted even to transistors with short channel lengths. can be done.

[0283] After the insulating layer 118 is formed, heat treatment may be performed. In some cases, the region 108n can be made more stable and have a lower resistance. By performing heat treatment, the impurity elements are diffused appropriately and locally homogenized, resulting in an ideal impurity A low resistance region 108n having a concentration gradient of the pure element can be formed. If the temperature is too high (for example, 500°C or higher), the impurity elements will diffuse into the channel formation region, This may result in deterioration of the electrical characteristics or reliability of the transistor.

[0284] The conditions for the heat treatment may be as described above.

[0285] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In the case where there is a step (for example, a film formation step) in the process, the step may be combined with the heat treatment.

[0286] [Formation of Openings 141a, 141b, and 144] Subsequently, a portion of the insulating layer 118 is etched to form an opening that reaches the conductive layer 112b. The opening 144 is formed. Also, a part of the insulating layer 118 and the insulating layer 110 is etched. As a result, openings 141a and 141b reaching the low resistance region 108n are formed ( Figure 18C).

[0287] The opening 144 and the openings 141a and 141b may be formed simultaneously. If they are performed simultaneously, the bottom of the opening 144 is The openings 141a and 141b are formed under conditions that make it difficult for the conductive layer 112b to be etched. It is preferable to etch the insulating layer 110 located at the top.

[0288] Next, the insulating layer 1 is formed so as to cover the openings 141a, 141b, and 144. A conductive film is formed on the conductive layer 18 and processed into a desired shape, thereby forming the conductive layer 120a and Then, a conductive layer 120b is formed (FIG. 18D).

[0289] Through the above steps, the transistor 100 can be manufactured. When the photodiode 100 is applied to a pixel or a driving circuit of a display device, a protective insulating layer is subsequently formed. , a step of forming one or more of a planarization layer, a pixel electrode, and a wiring may be added.

[0290] The above is a description of an example of the manufacturing method.

[0291] In the case of manufacturing the transistor 100A illustrated in Configuration Example 2, the conductive layer 112a The conductive layer 106a can be formed in different patterns.

[0292] In addition, when the structure shown in FIG. 15A and the like is manufactured, the conductive layer 106b and the conductive layer 106c The conductive layer 106a is formed by processing the same conductive film as the conductive layer 106b, and the semiconductor layer 108a is formed by processing the same conductive film as the semiconductor layer 106b. The conductive layer 112c is formed by processing the same metal oxide film as that of the conductive layer 112a. The conductive layer 120c is formed by processing the same conductive film as the conductive layer 112b. The openings 142 and the opening 143 may be formed by processing the same conductive film as the conductive layer 120b. The opening 145 is formed in the same manner as the opening 143, and the openings 141c, 141d, and The opening 141e may be formed in the same manner as the opening 141a. The transistor 100, the transistor 150, and the capacitor are formed on the same substrate without increasing the number of processes. A quantity 160 can be formed.

[0293] [Modification of the Example of the Fabrication Method] [Variation 1] In the above-described manufacturing method example, when the conductive layer 112a and the conductive layer 112b are processed, The insulating layer 110 in the area not overlapping with the conductive layer 112a and the conductive layer 112b is removed by etching. A cross-sectional view of a transistor manufactured in this manner is shown in FIG. Shown in 19A.

[0294] The transistor shown in FIG. 19A includes a low-resistance region 108n of a semiconductor layer 108 and an insulating layer 11 8 is in contact with the insulating layer 118. By using an insulating film having such a structure, hydrogen is suitably introduced into the low resistance region 108n during the process of forming the insulating layer 118. Alternatively, heat treatment can be performed after the insulating layer 118 is formed. In a later step, hydrogen is supplied from the insulating layer 118 to the low resistance region 108n by heat. In this case, the insulating layer 118 is made of a silicon nitride film or a silicon oxynitride film. An insulating film containing nitrogen, such as a nitrogen film, can be suitably used. The film has both the function of releasing hydrogen and the function of acting as a barrier film against water or hydrogen. This can be done.

[0295] The insulating layer 118 is formed in contact with a part of the semiconductor layer 108 that becomes the low resistance region 108n. If the resistance of the part of the semiconductor layer 108 can be sufficiently reduced by this, In this case, it is not necessary to use an insulating film that can release hydrogen when heated. The insulating film 118 may be an oxygen-containing insulating film such as a silicon oxide film or a silicon oxynitride film. A velum can be used.

[0296] Alternatively, after the insulating layer 118 is formed, the impurity element is supplied. The impurity element may be supplied to the low resistance region 108n through the insulating layer 118. The insulating film does not necessarily have to be one that can release hydrogen when heated.

[0297] [Variation 2] By using the above-described manufacturing method example, transistors each having only one gate can be simultaneously manufactured. A schematic cross-sectional view of a transistor fabricated in this manner is shown in Figure 19B.

[0298] The transistor shown in FIG. 19B has a conductive layer 106a that functions as a bottom gate. The conductive layer 112b does not have the opening 143 and the opening 144. The main difference from the transistor 100 is that it does not have

[0299] 19C, similarly to the first modification, the insulating layer 110 is connected to the conductive layer 112a in a top view. 1 shows a cross-sectional schematic diagram of a transistor that has been processed to have a roughly matching shape.

[0300] The above is a description of the modified example.

[0301] The above-described transistors can be used not only in sequential circuits but also in transistors provided in pixels of a display device. This can also be applied to transistors. and a transistor provided in a pixel of a display device are manufactured on the same substrate through the same process. This makes it possible to manufacture a highly reliable display device at low cost. This becomes possible.

[0302] [Components of semiconductor device] The components included in the semiconductor device of this embodiment will be described below.

[0303] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, silicon or silicon carbide is used as the material. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, The substrate 102 may be an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, the substrate on which the semiconductor element is provided may be referred to as the substrate 10. It may also be used as 2.

[0304] In addition, a flexible substrate is used as the substrate 102, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the semiconductor device. After a semiconductor device is partially or entirely completed on the substrate, it is separated from the substrate 102 and placed on another substrate. In this case, the semiconductor device is mounted on a substrate having poor heat resistance, or It can also be transferred to flexible substrates.

[0305] [Conductive film] In addition to the gate, source, and drain of a transistor, various wiring that makes up semiconductor devices Materials that can be used for conductive layers such as electrodes include aluminum, titanium, and quartz. Chromium, nickel, copper, yttrium, zirconium, molybdenum, gold, silver, zinc, tantalum metals such as zinc, manganese, iron, niobium, cobalt, or tungsten, or In addition, films containing these materials can be used as single layers or as laminated structures. It can be used as:

[0306] For example, a single layer structure of aluminum film containing silicon, or an aluminum film stacked on a titanium film Two-layer structure with an aluminum film on a tungsten film, two-layer structure with an aluminum film on a tungsten film, copper-magnesium Two-layer structure in which a copper film is laminated on a titanium-aluminum alloy film, and two-layer structure in which a copper film is laminated on a titanium film. a two-layer structure in which a copper film is laminated on a tungsten film; a titanium film or a titanium nitride film; An aluminum film or copper film is laminated on top of that, and then a titanium film or nitride film is laminated on top of that. Three-layer structure forming a titanium film, a molybdenum film or a molybdenum nitride film, and a An aluminum film or copper film is laminated, and then a molybdenum film or molybdenum nitride film is further laminated on top of that. There are three-layer structures that form a film. Also, when copper containing manganese is used, the shape can be easily controlled by etching. This is preferable because it increases

[0307] In addition, the conductive layers constituting the semiconductor device include In-Sn oxide, In-W oxide, In- W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In - Uses oxide conductors such as Sn-Si oxide, In-Ga-Zn oxide, or metal oxides You can also do this.

[0308] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. As a result, a donor level is formed near the conduction band. As a result, the metal oxide has high conductivity. The metal oxide that has become a conductor can be called an oxide conductor.

[0309] In addition, a conductive layer constituting a semiconductor device may be formed using a conductive material containing the oxide conductor (metal oxide). The conductive film may have a laminated structure of a conductive film containing a metal or an alloy. By using a conductive film, the wiring resistance can be reduced. It is preferable to use a conductive film containing an oxide conductor on the side in contact with the insulating layer that functions as a conductive film.

[0310] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The atomic ratio of the metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1 :3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 :1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. In the above, when the element M contains two or more elements, the atomic ratio The ratio of M corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0311] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 can be easily formed with crystallinity. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. The ratio of the number of atoms may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], film formation The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. This may be the case.

[0312] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, it means In When Ga is 4, this includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or in the vicinity, When n is 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is greater than or equal to 5 and less than or equal to 7. It also includes cases where the atomic ratio is In:Ga:Zn=1:1:1 or in the vicinity. When mounting, when In is 1, Ga is greater than 0.1 and not more than 2, and Zn is 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0313] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0314] The semiconductor layer 108 preferably has a non-single-crystal structure. This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure, which will be described later. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0315] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0316] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with a CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0317] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has no clear grain boundaries, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. Crystallinity may be reduced by the inclusion of impurities or the generation of defects. -OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of oxide semiconductors containing AAC-OS are stable. Oxide semiconductors containing S are heat-resistant and highly reliable.

[0318] In crystallography, the three axes that make up the unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the layer structure. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis intersecting the layers is the The c-axis is generally defined as the plane of the crystal. Graphite is classified as a hexagonal crystal, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The crystal of InGaZnO4 can be classified as a hexagonal system, and the a-axis and The a and b axes are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0319] An oxide semiconductor film having a microcrystalline structure (a microcrystalline oxide semiconductor film) was observed under a transmission electron microscope ( TEM (Transmission Electron Microscope) In the observation image, crystal parts may not be clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film is called a film. For example, in a TEM image, the grain boundaries are clearly visible. It may not be possible to confirm.

[0320] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, X-ray diffraction using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis was performed using an X-ray diffraction (XRD) device, In the out-of-plane analysis, no peaks indicating crystal planes are detected. For the nc-OS film, an electron beam with a probe diameter larger than the crystalline part (for example, 50 nm or more) is used. When electron diffraction (also called selected area electron diffraction) is performed, a halo pattern like On the other hand, for the nc-OS film, the size of the crystals is close to that of the crystals. Electron diffraction ( When nanobeam electron diffraction is performed, a bright ring-shaped area appears in a circular pattern. is observed, and multiple spots may be observed within the ring-shaped region.

[0321] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to the OS film, the carrier density is higher and the electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0322] The nc-OS film can be formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the substrate is not heated. Since it can be used to form films on large glass substrates or resin substrates, it is suitable for such applications. This allows for increased productivity.

[0323] An example of the crystal structure of a metal oxide is described below. The substrate temperature was set at 100°C or higher. The metal oxide formed by sputtering is nc (nano c) crystal structure) or CAAC structure, or a mixture of these. On the other hand, metal oxides formed at room temperature (RT) tend to have a structure similar to that shown in Fig. The NC crystal structure is easily formed. Includes temperatures when no heating is used.

[0324] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0325] CAAC (c-axis aligned crystal) is an example of a crystal structure. CAC (Cloud-Aligned Composite) represents the functionality or material An example of the composition of the fee is shown below.

[0326] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconducting properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. The function of activating the CAC-OS or CAC-metal oxide can be added. In CAC-OS or CAC-metal oxide, each function is separated. By combining these, the functions of both can be maximized.

[0327] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0328] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0329] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0330] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0331] The above is the explanation of the configuration of the metal oxide.

[0332] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly can be combined with other configuration examples or drawings as appropriate.

[0333] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0334] (Embodiment 2) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. The description will be made with reference to FIGS.

[0335] The display device shown in FIG. 20A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 506. , and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0336] The transistor included in the pixel portion 502, the driver circuit portion 504, or the like is The protection circuit 506 can also be a transistor according to one embodiment of the present invention. A transistor may also be applied.

[0337] The pixel section 502 is made up of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element. .

[0338] The driver circuit unit 504 is a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. A data driver 504a supplies data signals to the data lines DL_1 through DL_Y. The gate driver 504a includes at least one driver circuit, such as a source driver 504b. The source driver 504b may also have a shift register. It is also constructed using a shift register etc. The switch driver 504b may be configured as a

[0339] The sequential circuit of one embodiment of the present invention can be applied to the gate driver 504a. The sequential circuit of one embodiment of the present invention may also be applied to the source driver 504b.

[0340] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for connecting the power supply to the power source are provided.

[0341] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 The protection circuit 506 shown in FIG. 20A is a circuit that connects a wiring to another wiring. For example, the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, or the It is connected to various wirings such as the data line DL which is the wiring between the pixel driver 504b and the pixel circuit 501. In FIG. 20A, the protection circuit 506 is shown as a separate circuit to distinguish it from the pixel circuit 501. The circuit 506 is hatched.

[0342] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) plate) by COG or TAB (Tape Automated Bonding) Therefore, the LED may be mounted on the substrate on which the pixel portion 502 is provided.

[0343] 20B and 20C show examples of pixel circuit configurations that can be applied to the pixel circuit 501. 20B and 20C show examples of the mth row and nth column (m is a natural number between 1 and X, and n is 1 This shows the pixel circuit (a natural number between Y and Y).

[0344] The pixel circuit 501 shown in FIG. 20B includes a liquid crystal element 570, a transistor 550, and a capacitor element. The pixel circuit 501 also includes a data line DL_n, a gate line GL_m, and a , potential supply line VL, etc. are connected to the terminals.

[0345] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0346] The pixel circuit 501 shown in FIG. 20C includes a transistor 552 and a transistor 554. The pixel circuit 501 includes a data The line DL_n, the gate line GL_m, the potential supply line VL_a, and the potential supply line VL_b are connected to each other. It has been done.

[0347] One of the potential supply lines VL_a and VL_b is connected to a potential supply line VL_b, which is a high power supply potential. The other side is supplied with a potential VSS, which is a low power supply potential. The current flowing through the light emitting element 572 is controlled according to the potential applied to the gate of the light emitting element 554. In this way, the brightness of light emitted from the light emitting element 572 is controlled.

[0348] Transistor 550 shown in FIG. 20B or transistor 552 shown in FIG. 20C The transistor 554 is formed on the same substrate as the transistor included in the gate driver 504a. It is preferably provided on the

[0349] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0350] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0351] (Embodiment 3) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0352] [Circuit configuration] 21A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M1, The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0353] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, and The other terminal is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring. G2, one of the source and drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1, and 401 and 402, respectively.

[0354] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) EMS) elements, etc. can be applied.

[0355] The node connecting the transistor M1 and the capacitor C1 is connected to the node N1, and the transistor M2 is connected to the node N2. The node connecting to the path 401 is node N2.

[0356] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. Furthermore, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via capacitor M1, capacitive coupling via capacitor C1 This allows the potential of the node N2 to be changed in accordance with the amount of change in the potential of the node N1. .

[0357] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, as exemplified in 1, can be used. Therefore, the potential of the node N1 or N2 is maintained for a long period of time due to the extremely low off-state current. In addition, when the period for which the potential of each node is held is short (specifically, when In cases where the frequency is 30 Hz or more, transistors using semiconductors such as silicon A star may also be used.

[0358] [Driving method example] Next, an example of an operation method of the pixel circuit 400 will be described with reference to FIG. 1 is a timing chart relating to the operation of the pixel circuit 400. Therefore, various resistances such as wiring resistance, parasitic capacitance of transistors or wiring, and The influence of the threshold voltage of the transistor is not taken into consideration.

[0359] In the operation shown in FIG. 21B, one frame period is divided into periods T1 and T2. Period T1 is a period during which a potential is written to the node N2, and period T2 is a period during which a potential is written to the node N1. is.

[0360] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supply.

[0361] The node N1 is connected to the line S1 via the transistor M1. ref is given. The node N2 is supplied with a first data potential V w is given Therefore, the potential difference V w -V ref is maintained.

[0362] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1. A potential that turns off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may be in a locking state.

[0363] The node N1 receives a second data potential V data but At this time, the second data potential V data In response In other words, the circuit 401 stores the first data Potential V w The potential obtained by adding the potential dV to the potential dV is input. Although the second data potential is shown as being a positive value, it may also be a negative value. V data is the potential V ref It may be lower.

[0364] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is Data potential V data The potential is close to

[0365] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential supplied to the line 401 can be generated, the gradation can be corrected in the pixel circuit 400. It will be possible to do this.

[0366] The pixel circuit 400 can also be supplied with a source driver connected to the wiring S1 and the wiring S2. For example, when a light emitting element is used, it is possible to generate a potential that exceeds the maximum potential. It is possible to display high dynamic range (HDR) images. In this case, overdrive driving or the like can be realized.

[0367] [Application example] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 21C includes a circuit 401LC. It has a liquid crystal element LC and a capacitor C2.

[0368] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitor C2, and the other electrode connected to the Potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0369] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0370] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Overdrive operation allows for high-speed display, and liquid crystal materials with high drive voltage are used. In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected in accordance with the operating temperature or the deterioration state of the liquid crystal element LC.

[0371] [Example using light-emitting element] The pixel circuit 400EL shown in Figure 21D includes a circuit 401EL. The device includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0372] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the node N2 and one electrode of the capacitor C2. One of the rains is at potential V H The other is one electrode of the light-emitting element EL, and The capacitor C2 is connected to the other electrode at a potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0373] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0374] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0375] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 or It is also possible to correct variations in the electrical characteristics of the light-emitting element EL and the like.

[0376] The circuit is not limited to the circuits illustrated in FIGS. 21C and 21D, and may include a separate transistor or capacitor. It may also be configured to add the above.

[0377] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0378] (Fourth embodiment) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. and explain.

[0379] The display module 6000 shown in FIG. 22A includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a print It has a substrate 6010 and a battery 6011 .

[0380] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0381] The upper cover 6001 and the lower cover 6002 are designed to fit the size of the display device 6006. The shape, dimensions, etc. can be changed as appropriate.

[0382] The display device 6006 may have a function as a touch panel.

[0383] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0384] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0385] FIG. 22B is a cross-sectional view of a display module 6000 when an optical touch sensor is provided. This is a schematic diagram.

[0386] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is enclosed by an upper cover 6001 and a lower cover 6002. The region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0387] The display device 6006 is mounted on a printed circuit board 6010 or a backplane via a frame 6009. The display device 6006 and the frame 6009 are provided overlapping with the terry 6011. It is fixed to the light guide portion 6017a and the light guide portion 6017b.

[0388] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 600 by the light guiding unit 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a sensing object such as a stylus. It is possible.

[0389] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information about the position where the touch operation was performed.

[0390] The light emitting unit 6015 can use a light source such as an LED element, and in particular, can emit infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0391] The light emitting unit 60 15 and the light receiving section 6016 can be disposed below the display device 6006, and external light is received by the light receiving section 6016 and cause the touch sensor to malfunction. If a resin that transmits infrared rays is used, malfunction of the touch sensor can be more effectively suppressed.

[0392] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0393] (Embodiment 5) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0394] The electronic device 6500 shown in FIG. 23A is a portable information device that can be used as a smartphone. It is a news terminal.

[0395] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, and a 504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0396] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0397] FIG. 23B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0398] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. The space surrounded by the protective member 6510 is provided with a display panel 6511, an optical member 6512, a tab The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0399] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The flannel 6513 is fixed by an adhesive layer (not shown).

[0400] In addition, in the area outside the display portion 6502, a part of the display panel 6511 is folded back. In addition, the FPC6515 is connected to the folded part. The 6515 is mounted with IC6516. The FPC6515 is a printed circuit board 6 517.

[0401] A flexible display panel according to one embodiment of the present invention is applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. 1 is extremely thin, so it can accommodate a large-capacity battery 6518 while keeping the thickness of the electronic device small. It is also possible to fold back a part of the display panel 6511 and attach an FPC to the back of the pixel area. By arranging the connection part with 6515, it is possible to realize electronic devices with narrow bezels.

[0402] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0403] (Sixth embodiment) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described. and explain.

[0404] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0405] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0406] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0407] The electronic device to which one aspect of the present invention is applied is suitable for use in an interior or exterior wall of a house or building, an automobile, etc. The device can be installed along a flat or curved surface of the interior or exterior of the vehicle.

[0408] FIG. 24A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached. is.

[0409] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0410] The camera 8000 may have the lens 8006 and the housing integrated together.

[0411] The camera 8000 can be operated by pressing the shutter button 8004 or by using the touch panel. An image can be captured by touching the display portion 8002.

[0412] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as

[0413] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0414] The housing 8101 is configured to mount the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 is attached to the camera 8000. It can be displayed on the display unit 8102.

[0415] The button 8103 has a function such as a power button.

[0416] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device of one embodiment of the present invention can be applied. It may also be La 8000.

[0417] FIG. 24B is a diagram showing the appearance of the head mounted display 8200.

[0418] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0419] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movement of the user's eyeballs or eyelids. It can be used as a force means.

[0420] In addition, the attachment part 8201 has a flow sensor that moves in accordance with the movement of the user's eyeball at a position where it comes into contact with the user. A plurality of electrodes capable of detecting the current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse of the user by measuring the current flowing through the electrodes. The mounting part 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, or the user's head It may have a function to change the image displayed on the display unit 8204 according to the movement of the good.

[0421] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0422] 24C, 24D, and 24E show the appearance of the head mounted display 8300. The head-mounted display 8300 includes a housing 8301 and a display unit 830. 2, a band-shaped fixture 8304, and a pair of lenses 8305.

[0423] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The configuration is not limited to one display unit 8302, but two display units 8302 may be provided, and one of the display units may be One display unit may be arranged for each eye.

[0424] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the lens 8305 is used to enlarge the image, the pixels are not visible to the user, and the image is more visible. It is possible to display highly realistic images.

[0425] The electronic device shown in FIGS. 25A to 25G includes a housing 9000, a display unit 9001, a speaker 9002, and a 003, operation keys 9005 (including a power switch or an operation switch), connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, Magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity (including functions to measure degree, gradient, vibration, smell or infrared rays), microphone 900 8, etc.

[0426] The electronic devices shown in FIGS. 25A to 25G have various functions. For example, Still images, videos, text images, etc.) on the display, touch panel function, calendar Functions that display date, time, etc., and various software (programs) Functions for controlling processing, wireless communication functions, programs or data recorded on recording media The functions of the electronic device are not limited to these. The electronic device may have multiple display units. It is also possible to provide a camera or the like in the electronic device to take still or moving images and store them on a recording medium (external or It has functions such as saving the captured image to a memory card or built into the camera, and displaying the captured image on the display. It's fine.

[0427] The electronic devices shown in FIGS. 25A to 25G will be described in detail below.

[0428] 25A is a perspective view showing a television device 9100. 0 is equipped with a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more. It is possible to incorporate this.

[0429] FIG. 25B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 is, for example, For example, the portable information terminal 9101 can be used as a smartphone. A connector 9003, a connection terminal 9006, a sensor 9007, etc. may also be provided. 9101 can display text or image information on multiple surfaces. An example of displaying three icons 9050 is shown in the figure. 051 can also be displayed on another surface of the display unit 9001. An example of the information 9051 is , notifications of incoming calls, such as emails, SNS, and phone calls, the subject of emails or SNS, The information includes the name of the follower, the date and time, the remaining battery level, and the strength of the antenna reception. An icon 9050 or the like may be displayed at the position where 9051 is displayed.

[0430] FIG. 25C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a display. The display unit 9001 has a function of displaying information on three or more surfaces. 9053 and information 9054 are displayed on different surfaces. , with the mobile information terminal 9102 stored in the breast pocket of the clothes, The user can also check the information 9053 displayed in a position that can be observed from above. The display can be checked without taking the mobile information terminal 9102 out of the pocket, and for example, a call can be answered. It is possible to determine whether or not

[0431] FIG. 25D is a perspective view showing a wristwatch-type mobile information terminal 9200. 01 has a curved display surface, and can display information along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. This allows hands-free conversation. The connection terminal 9006 allows data transmission to and from other information terminals or charging. The charging operation may be performed by wireless power supply.

[0432] 25E, 25F, and 25G are oblique views showing a foldable mobile information terminal 9201. 25E shows the mobile information terminal 9201 in an unfolded state, and FIG. 25G shows the mobile information terminal 9201 in a folded state. 25F is a perspective view of a state in which the state shown in FIG. 25E and FIG. 25G is changing to the other state. The portable information terminal 9201 is highly portable when folded and is unfolded. The seamless, wide display area provides excellent visibility of the display. The display unit 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less. Cut.

[0433] An example of a television device is shown in FIG. 26A. The television device 7100 includes a housing 710 A display unit 7500 is built into the housing 710. This shows a configuration that supports 1.

[0434] The television device 7100 shown in FIG. 26A is operated by an operation switch provided on the housing 7101. This can be done by a separate remote control 7111. A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control device 7111 may have a display unit in addition to the operation buttons.

[0435] The television device 7100 may be a television broadcast receiver or a network-connected The device may have a communication device for the purpose.

[0436] FIG. 26B shows a notebook personal computer 7200. The computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and a 213, an external connection port 7214, etc. A display unit 7500 is incorporated in the housing 7211. It is being eaten.

[0437] 26C and 26D show examples of digital signage. An example of a digital sign is shown below.

[0438] The digital signage 7300 shown in FIG. 26C includes a housing 7301, a display unit 7500, and It also has a speaker 7303, etc., and an LED lamp, an operation key (power switch, or It can have a control switch, connection terminals, various sensors, a microphone, etc. .

[0439] FIG. 26D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 75 provided along the curved surface of a pillar 7401. 00.

[0440] The larger the display 7500, the more information can be displayed at once, and the closer it is to the human eye. It is easy to attach to the surface, which has the effect of increasing the advertising effectiveness of advertisements, for example.

[0441] It is preferable that the display unit 7500 be configured as a touch panel so that a user can operate it. This allows for not only advertising purposes, but also route information, traffic information, and commercial facility guidance information. It can also be used to provide information that a user desires.

[0442] Also, as shown in FIGS. 26C and 26D, a digital signage 7300 or a digital The Tal Signage 7400 is connected to an information terminal 7311 such as a smartphone carried by the user. It is preferable that the communication is possible via wireless communication. The information of the notice is displayed on the screen of the information terminal 7311, or the information terminal 7311 is operated. By operating the buttons, the display on the display unit 7500 can be switched.

[0443] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0444] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. 26A to 26D. It is possible.

[0445] Although the electronic device of this embodiment has a display unit, the present invention can also be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above.

[0446] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0447] LIN: Signal: RIN: Signal: BDG: Signal: CLK: Signal: OUT: Output terminal: GOU T: Output terminal: SROUT: Output terminal: PWC: Signal: RES: Signal: SP: Signal: C1 C4 to C4: Capacity: CK1 to CK4: Signal: CLK1 to CLK3: Signal: N, N1, N 2: Node: OUT to OUT6: Wiring: PWC1 to PWC4: Signal: RIN1, RI N2: Signal: 10, 10a, 10b, 10c: Sequential circuit: 11, 11a, 12, 13: times Route: 14a, 14b: Signal generation circuit: 15a, 15b: Wiring: 20: Sequential circuit: 21 to 26: Transistor: 30, 30a, 30a_n: Sequential circuit: 30b: Sequential circuit: 31 34: Transistors: 40a, 40b: Driver circuits: 41 to 47, 51, 52, 60 To 69, 71, 72: Transistor

Claims

1. an oxide semiconductor layer, a first conductive layer, and a second conductive layer; the oxide semiconductor layer has a region that functions as a channel formation region of a transistor, the first conductive layer has a region that functions as a gate electrode of the transistor, the second conductive layer has a region functioning as a source electrode or a drain electrode of the transistor, In a plan view, a channel length direction of the transistor is a direction along a first direction, In a plan view, the oxide semiconductor layer has a first region extending in a second direction intersecting the first direction, the first region is a region having a lower resistance than the channel formation region, In a plan view, the first conductive layer has a second region extending in the second direction to overlap the first region, In a plan view, the second conductive layer has a third region extending in the second direction to overlap with the first region, In a plan view, the third region contacts the first region in each of a plurality of contact holes aligned in the second direction.

2. an oxide semiconductor layer, a first conductive layer, and a second conductive layer; the oxide semiconductor layer has a region that functions as a channel formation region of a transistor, the first conductive layer has a region that functions as a gate electrode of the transistor, the second conductive layer has a region functioning as a source electrode or a drain electrode of the transistor, In a plan view, a channel length direction of the transistor is a direction along a first direction, In a plan view, a channel width direction of the transistor is a direction along the second direction, the oxide semiconductor layer has a first region extending in the second direction in a plan view, the first region is a region having a lower resistance than the channel formation region, In a plan view, the first conductive layer has a second region extending in the second direction to overlap the first region, In a plan view, the second conductive layer has a third region extending in the second direction to overlap with the first region, In a plan view, the third region contacts the first region in each of a plurality of contact holes aligned in the second direction.

Images