Display device

Abstract

To provide a display device capable of performing image processing.SOLUTION: A memory circuit is provided in each pixel, and desired correction data is held in the memory circuit. The correction data is calculated by an external device and written in each pixel. The correction data is added to image data by capacitive coupling and supplied to a display element. Thus, the corrected image can be displayed in the display element. By such correction, the image can be up-converted or the image quality, which deteriorates due to characteristic variation of transistors in the pixel, can be corrected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing a transistor using a metal oxide formed on a substrate has been attracting attention. For example, a transistor using zinc oxide or In-Ga-Zn oxide is used for the display of a display device. The technology used for the basic switching elements is disclosed in Patent Document 1 and Patent Document 2. .

[0005] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0007] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware capable of displaying at higher resolutions is being developed. Since the amount of image data at high resolution is enormous, in order to popularize high-resolution display devices, It is also necessary to prepare peripheral technologies such as imaging devices, storage devices, and communication devices.

[0008] Up-conversion is one of the techniques for generating high-resolution image data. By converting the image, you can convert a low-resolution image into a pseudo-high-resolution image. Since upconversion is performed on a peripheral device of the display device, the image before upconversion is Conventional technology can be used for the equipment that handles the data.

[0009] However, devices that perform upconversion analyze huge amounts of image data to generate new image data. However, since the data is generated, the circuit scale and power consumption are large. The processing may not be able to keep up, resulting in display delays.

[0010] Up-conversion has such problems, but for example, By distributing the functions across multiple devices, it may be possible to mitigate issues such as power consumption and latency. do.

[0011] In addition, in display devices that have EL (Electro Luminescence) elements, etc. In this case, variations in the characteristics of the transistors in the pixels are one of the factors that cause degradation of display quality. One way to correct for variations in transistor characteristics is to use a circuit that stores image data in the pixel. Internal correction is performed by acquiring the correction value for each pixel, and supplying the corrected image data to the pixel. There is an external correction.

[0012] Internal correction can be performed on a frame-by-frame basis, but on high-resolution displays, horizontal selection is required. Since the selection period is short, it becomes difficult to secure the correction period. This is effective for various display devices, but it requires correction of all image data. This places a heavy load on external devices. Ideally, high-resolution displays should operate without correction. However, suppressing the variation in transistor characteristics is extremely difficult, so new A means of correction is desired.

[0013] Therefore, one aspect of the present invention is to provide a display device capable of image processing. Another object is to provide a display device capable of up-conversion. One of the objects is to provide a display device capable of correcting image data. One of the objectives is to

[0014] Another object is to provide a display device with low power consumption. One of the purposes is to provide a new display device. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0016] One embodiment of the present invention relates to a display device capable of performing image processing. The present invention relates to a display device capable of correcting the above.

[0017] One embodiment of the present invention is a display device including a pixel provided with a display element and a memory circuit. The memory circuit has a function of storing the first data. The display element has a function of generating third data by adding the second data to the third data. It is a display device that has the function of displaying information based on the data.

[0018] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a transistor, a fourth transistor, a first capacitor, a second capacitor, and a display element; and one of the source and drain of the first transistor is connected to one of the first capacitance elements. One electrode of the first capacitor is electrically connected to the source electrode of the second transistor. the source or drain of the second transistor. One of the inputs is electrically connected to the gate of the third transistor. The gate is electrically connected to one electrode of the second capacitor element and the other electrode of the second capacitor element. The electrode is electrically connected to one of the source and drain of the third transistor. One of the source or drain of the transistor is connected to the source or drain of a fourth transistor. The other of the source and drain of the fourth transistor is electrically connected to the surface. The display device is electrically connected to one electrode of the display element.

[0019] The display element can be an organic EL element.

[0020] At least the second transistor has a metal oxide in a channel formation region, and the metal oxide , In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or It is preferred that the composition has Hf.

[0021] The first circuit may have the function of supplying a constant potential or reading a current value. The function may include generating correction data.

[0022] Another aspect of the present invention is a display having a first pixel, a second pixel, and a third pixel. A display device, wherein a first pixel and a second pixel are adjacent to each other in a first direction, and the first pixel and a third pixel are adjacent to each other in a first direction. The pixels are adjacent to each other in a direction perpendicular to the first direction, and the first to third pixels are adjacent to each other in a direction perpendicular to the first direction. The first pixel has three sub-pixels, and the first wiring electrically connected to the first sub-pixel of the first pixel is a third wiring. The first sub-pixel is electrically connected to one terminal of the first switch and the second sub-pixel is electrically connected to the first terminal of the second switch. The second wiring connected to the first pixel is electrically connected to the other terminal of the first switch. The third wiring electrically connected to the second sub-pixel is electrically connected to one terminal of the second switch. The fourth wiring electrically connected to the second sub-pixel of the second pixel is connected to the second switch. a fifth sub-pixel electrically connected to the other terminal and electrically connected to the third sub-pixel of the first pixel; The wiring is electrically connected to one terminal of the third switch, and is electrically connected to the third subpixel of the second pixel. The sixth wire is electrically connected to the other terminal of the third switch, and the first The seventh wiring electrically connected to the first to third subpixels of the pixel is connected to one of the fourth switches. an eighth sub-pixel electrically connected to the terminal and electrically connected to the first to third sub-pixels of the third pixel; The wiring is a display device that is electrically connected to the other terminal of the fourth switch.

[0023] The first to sixth wirings function as signal lines for supplying image data, and the seventh and eighth wirings The lines can have the function of signal lines for selecting pixels.

[0024] The first to third sub-pixels can have the function of emitting light of different colors, respectively. [Effects of the Invention]

[0025] By using one embodiment of the present invention, a display device capable of image processing can be provided. Alternatively, a display device capable of up-conversion can be provided. It is possible to provide a display device capable of correcting image data.

[0026] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. Furthermore, a method for driving the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 2] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 3] FIG. 1 is a diagram illustrating up-conversion. [Figure 4] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 5] FIG. 1 is a block diagram illustrating a display device. [Figure 6] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 7] FIG. 1 is a block diagram illustrating a display device. [Figure 8] FIG. 2 is a diagram illustrating a pixel array. [Figure 9] 1A and 1B are diagrams illustrating a display device. [Figure 10] FIG. 2 is a diagram illustrating a touch panel. [Figure 11] 1A and 1B are diagrams illustrating a display device. [Figure 12] 1A and 1B are diagrams illustrating a transistor. [Figure 13] 1A and 1B are diagrams illustrating a transistor. [Figure 14] FIG. 1 is a cross-sectional view showing an example of the configuration of a DOSRAM. [Figure 15] FIG. 1 is a diagram illustrating an example of the configuration of a neural network. [Figure 16] 1A to 1C illustrate a structural example of a semiconductor device. [Figure 17] 1A and 1B are diagrams illustrating an example of the configuration of a memory cell. [Figure 18] FIG. 2 is a diagram illustrating a configuration example of an offset circuit. [Figure 19] 1 is a timing chart illustrating an operation of a semiconductor device. [Figure 20] 1A to 1C illustrate electronic devices. [Figure 21] FIG. 10 is a graph showing ID-VG characteristics of a transistor. [Figure 22] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 23] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 24] FIG. 10 is a diagram illustrating a simulation result. [Figure 25] FIG. [Figure 26] FIG. 10 is a graph showing ID-VG characteristics of a transistor. [Figure 27] FIG. 1 is a diagram illustrating the interface between an external correction circuit and an EL panel. [Figure 28] FIG. 1 is a diagram illustrating the interface between an external correction circuit and an EL panel. [Figure 29] FIG. 2 is a diagram illustrating a pixel layout. [Figure 30] FIG. 2 is a block diagram illustrating the configuration of a pixel and a source driver. [Figure 31] 10A and 10B are diagrams illustrating the results of measuring the current of a driving transistor. [Figure 32] 10A and 10B are diagrams illustrating a display in which an image has been corrected using an external correction system. [Figure 33] FIG. 10 is a diagram illustrating the results of measuring luminance unevenness using a two-dimensional luminance colorimeter. [Figure 34] 10A and 10B are diagrams illustrating display photographs and measurement results using a two-dimensional color luminance meter. [Figure 35] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0029] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0030] One aspect of the present invention is a display device having a function for adding correction data to image data. Each pixel is provided with a memory circuit, and the desired correction data is stored in the memory circuit. The correction data is generated by an external device and written to each pixel.

[0031] The correction data is added to the image data by capacitive coupling and supplied to the display element. Therefore, the display device can display a corrected image. Alternatively, the characteristics of the transistors in the pixels can be varied. It is possible to correct the deterioration of image quality caused by the staining.

[0032] FIG. 1 illustrates a pixel 10a that can be used in a display device of one embodiment of the present invention. The pixel 10a includes a transistor 101, a transistor 102, and a transistor 111. , a transistor 112, a capacitor 103, a capacitor 113, and an EL element 104. do.

[0033] One of the source and drain of the transistor 101 is connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the source or One of the source and drain of the transistor 111 is electrically connected to the The other end is electrically connected to the gate of the transistor 112. is electrically connected to one electrode of the capacitor 103. The other electrode of the capacitor 103 is , electrically connected to one of the source and drain of the transistor 112. One of the source or drain of transistor 112 is connected to the source or drain of transistor 102. The other of the source and drain of the transistor 102 is electrically connected to E It is electrically connected to one electrode of the L element 104 .

[0034] Here, the other electrode of the capacitor 113 and one of the source and drain of the transistor 111 are On the other hand, a wiring to which the gate of the transistor 112 and one electrode of the capacitor 103 are connected is The other of the source and drain of the transistor 102 and the EL The wiring to which one electrode of the element 104 is connected is referred to as a node NA.

[0035] The gate of the transistor 101 is electrically connected to the wiring 122. The gate of the transistor 111 is electrically connected to a wiring 126. The other of the source and the drain of the transistor 101 is electrically connected to the wiring 21. The other of the source and drain of the transistor 111 is electrically connected to the transistor 125. It is electrically connected to the line 124 .

[0036] The other of the source and drain of the transistor 112 is electrically connected to the power supply line 128 (high potential). The other electrode of the EL element 104 is electrically connected to a common wiring 129. Note that any potential can be supplied to the common wiring 129.

[0037] The wirings 121, 122, and 126 function as signal lines for controlling the operation of the transistors. The wiring 125 has a function as a signal line for supplying image data. The wiring 124 can also be used to write data to a memory circuit MEM, which will be described next. The signal line can function as a signal line for inputting the signal.

[0038] The transistor 111, the transistor 112, and the capacitor 113 constitute a memory circuit MEM. The node NM is a storage node, and by making the transistor 111 conductive, Data provided on line 124 can be written to node NM. By using a transistor with extremely low off-state current, the potential of the node NM can be held for a long time. In the transistor, for example, a metal oxide is used in a channel formation region. A transistor having such a structure (hereinafter referred to as an OS transistor) can be used.

[0039] In addition to the transistor 111, other transistors constituting the pixel are also OS transistors. Alternatively, the transistor 111 may have Si in a channel formation region. Alternatively, an OS transistor may be used. It is also possible to use both a silicon transistor and a silicon transistor. Amorphous silicon transistors, crystalline silicon (typically low-temperature poly Examples include transistors using silicon (silicon, single crystal silicon).

[0040] When an EL element is used as the display element, a silicon substrate can be used, and a Si transistor The OS transistor can be formed to have an overlapping region. Even if the number of transistors is relatively large, the pixel density can be improved.

[0041] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0042] OS transistors have a large energy gap and therefore exhibit extremely low off-state current. In addition, OS transistors have the following drawbacks: impact ionization, avalanche breakdown, and short-channel It has characteristics different from Si transistors, such as no effects, and can form highly reliable circuits. It can be achieved.

[0043] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0044] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0045] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or The oxide semiconductor is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and It can be said that this is an oxide semiconductor with stable characteristics.

[0046] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0047] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0048] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0049] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0050] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor, or C-Axis Aligne d and AB-plane Anchored Crystalline Oxi Semiconductor), including polycrystalline, microcrystalline, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density. The defect level density is also low.

[0051] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0052] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0053] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This article explains the structure of the .NET composite OS.

[0054] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0055] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0056] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0057] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0058] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0059] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0060] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0061] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0062] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0063] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will In the region, nanoparticles containing the metal element as the main component are observed, and in a part, In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0064] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set it to 0% or more and 10% or less.

[0065] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0066] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped region with high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS is nc(nan It can be seen that the crystalline structure is o-crystal.

[0067] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0068] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0069] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0070] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0071] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0072] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0073] In the pixel 10a, the data written to the node NM is supplied from the line 125. The image data is capacitively coupled to the transistor 10 and can be output to the node NA. The transistor 102 can select the EL element 10. 4 can function as a switch for controlling the light emission.

[0074] For example, the voltage of the data written to the node NM from the wiring 124 is Threshold voltage (V th ), transistor 1 is Therefore, the transistor 102 is not provided. After the potential of the node NM is determined, the transistor 102 is turned on, and the EL element 104 It is preferable to emit light.

[0075] That is, if desired correction data is stored in the node NM, the corresponding correction data can be added to the supplied image data. Correction data can be added. Note that the correction data may be attenuated by factors on the transmission path. Therefore, it is preferable to generate the signal taking this attenuation into consideration.

[0076] In addition, in the distribution, coupling or loss of potential, the circuit configuration and operation timing, etc. The detailed changes due to the capacitive coupling are not taken into account. However, for clarity, the capacitance values of the nodes NM and NA are is assumed to be sufficiently small.

[0077] The operation of the pixel 10a will be described in detail using the timing charts shown in FIGS. 2(A) and 2(B). The correction data (Vp) supplied to the wiring 124 can be any positive or negative potential. However, here we will explain the case where a positive potential is supplied. In this case, high potential is represented by "H" and low potential by "L".

[0078] First, the operation of writing the correction data (Vp) to the node NM will be described with reference to FIG. In addition, in an operation for the purpose of up-conversion, the operation is usually performed for each frame. is preferred.

[0079] At time T1, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 125 is set to When the potential of the wiring 126 is set to "L", the transistor 101 is turned on, and the capacitor 1 The potential of the other electrode of 13 becomes "L".

[0080] This operation is a reset operation for performing a subsequent capacitive coupling operation. The EL element 104 is still emitting light in the previous frame, but the reset operation As a result, the potential of the node NM changes, and the current flowing through the EL element 104 changes. It is preferable to make the EL element 104 non-conductive and stop the EL element 104 from emitting light.

[0081] At time T2, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "H", and the potential of the wiring 125 is set to "H". When the potential of the wiring 126 is set to "L", the transistor 111 is turned on, and the potential of the wiring 124 is turned on. The potential (correction data (Vp)) is written to the node NM.

[0082] At time T3, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 125 is set to When the potential of the wiring 126 is set to "L", the transistor 111 is turned off. The correction data (Vp) is stored in the node NM.

[0083] At time T4, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 125 is set to "L". When the potential of the wiring 126 is set to "L", the transistor 101 is turned off. The data (Vp) write operation is completed.

[0084] Next, the image data (Vs) is corrected and the EL element 104 is made to emit light, using FIG. 2(B). The operation will be explained below.

[0085] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 124 is set to "H". When the potential of the wiring 126 is set to "L", the transistor 101 is turned on, and the capacitor The potential of the wiring 125 is added to the potential of the node NM by the capacitive coupling of 113. That is, The node NM has a potential (Vs+Vp) where the correction data (Vp) is added to the image data (Vs). )

[0086] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 126 is set to "L", the transistor 101 is turned off. The potential of the node NM is determined to be Vs+Vp.

[0087] At time T13, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 124 is set to "L". When the potential of the wiring 126 is set to "H", the transistor 102 is turned on, and the potential of the node N The potential of A becomes Vs+Vp, and the EL element 104 emits light. The potential is changed from Vs+Vp to the threshold voltage of the transistor 112 (V th ) is lower than the However, here we will use V th is set to a value that is small enough to be ignored.

[0088] The above is the operation of correcting the image data (Vs) and the operation of making the EL element 104 emit light. The write operation of the correction data (Vp) and the input operation of the image data (Vs) are as follows: It may be performed continuously, but it is recommended to write the correction data (Vp) to all pixels before writing the image data. As will be described in detail later, in one embodiment of the present invention, Since the same image data can be supplied to multiple pixels simultaneously, the correction data is first sent to all pixels. The operating speed can be improved by writing data (Vp).

[0089] The configuration and operation of the pixel 10a described above is useful for up-converting an image. The up-conversion using the above will be explained with reference to FIGS.

[0090] For example, the number of pixels on an 8K4K display device is 3840 x 2100 pixels on a 4K2K display device. 60) is four times the image data displayed on one pixel of a 4K2K display device. If you try to display the same image data on an 8K / 4K display device, it will be displayed using four pixels. become.

[0091] FIG. 3A is a diagram for explaining an image displayed on four pixels in the horizontal and vertical directions, assuming the above. As shown in FIG. 3(A), before up-conversion, image data S1 is displayed in all four pixels. After up-conversion, the image data S0 to S1 are displayed in each pixel. 2 can be applied to improve the resolution.

[0092] FIG. 3B is a diagram illustrating the up-conversion operation in the pixel 10a. In a, as mentioned above, any correction data can be added to the image data. Therefore, the original image data S1 is supplied to each pixel as is.

[0093] Furthermore, W1 to W3 are supplied to each pixel as correction data. The method of generating the correction data is not limited. The correction data can be generated in real time using an external device. Alternatively, the correction data stored in the recording medium may be read out and synchronized with the image data S1. It is also acceptable to do so.

[0094] Then, by performing the operation of the pixel 10a described above, each correction data is added to each image data. The new image data S0 to S2 are generated. It is possible to display the converted image.

[0095] Conventional up-conversion using external correction generates new image data itself. On the other hand, in one aspect of the present invention, the image data to be supplied is The external data is not changed, and new image data is generated using the pixels to which the correction data is supplied. This reduces the burden on the device. Also, the new image data can be generated by pixels. The operation can be performed in a few steps, and it is compatible with display devices with a large number of pixels and a short horizontal period. It is possible.

[0096] The pixel of one embodiment of the present invention can also have the structure of a pixel 10b shown in FIG. The pixel 10b has a configuration in which the transistor 102 is omitted from the pixel 10a.

[0097] As described above, the transistor 102 is turned on when the voltage of the data written to the node NM is applied to the transistor. The threshold voltage of the capacitor 112 (V th ) or more. However, if the data written to node NM is V th If limited to a lower value For example, transistor 102 can be omitted.

[0098] The pixel of one embodiment of the present invention can also have the structure of a pixel 10c shown in FIG. 4B. The pixel 10c has a configuration in which a back gate is provided for each transistor. The back gate is electrically connected to the front gate, which has the effect of increasing the on-current. Also, a constant potential different from that of the front gate may be supplied to the back gate. With this structure, the threshold voltage of the transistor can be controlled. 4(B) shows a configuration in which all transistors are provided with back gates. Alternatively, the semiconductor device may have a transistor that does not have a back gate. The configuration having a back gate is also effective for other pixel circuits in this embodiment.

[0099] FIG. 5 is an example of a block diagram of a display device according to one embodiment of the present invention. A pixel array in which 0 are arranged in a matrix, a row driver 12, and a column driver 13 and a circuit 14. The pixel 10 may be any one of the pixels 10a to 10c described above. Either one can be applied.

[0100] The row driver 12 and the column driver 13 may be implemented using, for example, a shift register circuit. The circuit 14 has a function of generating correction data. It can also be considered an external device for generating data.

[0101] The image data S1 in the explanation of FIGS. 3(A) and 3(B) is input to the circuit 14, and the image data The data S1 and correction data W are generated and output to the column driver 13. The image data S1 input to the camera driver 13 may be input without going through the circuit 14.

[0102] The circuit 14 may also include a neural network. By using deep neural networks trained with training data, highly accurate Correction data W can be generated.

[0103] Up to now, we have mainly explained the up-conversion operation in pixels having a memory circuit MEM. However, in this pixel, it is also possible to perform an operation to correct the characteristic variations of the transistor. In a pixel using an EL element, the threshold voltage of the driving transistor that supplies current to the EL element is The voltage fluctuations have a large effect on the display quality. Improved display quality by storing data to correct the threshold voltage and adding it to image data It can be done.

[0104] FIG. 6 shows the threshold voltage (V th ) 1 is a diagram showing the configuration of a pixel 10d that can perform an operation to correct the pixel The element 10a has a configuration in which a transistor 105 and a wiring 130 are added. The above-mentioned up-conversion operation may be performed using a pixel circuit having a threshold voltage. Both voltage correction and up-conversion operations may be performed.

[0105] One of the source or drain of transistor 105 is connected to the source or drain of transistor 112. is electrically connected to one of the source and drain of the transistor 105. The other end is electrically connected to a wiring 130. The gate of the transistor 105 is electrically connected to a wiring 122. and electrically connected to each other.

[0106] The wiring 130 functions as a monitor line for acquiring the electrical characteristics of the transistor 111. In addition, the wiring 130 is connected to the source of the transistor 112 via the transistor 105. Alternatively, by supplying a specific potential to one of the drains, the writing of image data can be stabilized. It can also be made into

[0107] In the pixel 10d, an external correction operation is performed as an initial operation, but the generated correction data is not stored in memory. Therefore, after the correction data is stored in the memory circuit MEM, In this case, pixel 10d operates like an internal correction.

[0108] The generation of correction data and storage in the memory circuit MEM are shown in the circuit diagram of FIG. 6 and FIG. 7(A). The display device will be described using a block diagram of the display device. a pixel array provided in the row driver 12, a column driver 13, and a column driver It has a bus 15 and a circuit 16.

[0109] The column driver 15 can be, for example, a shift register circuit. The column driver 15 sequentially selects the wiring 130. The output value can be input to the circuit 16.

[0110] First, the transistor 111 is turned on, and the standard voltage at which the transistor 112 is turned on is applied to the node NM. The current output from the transistor 112 is input to the circuit via the transistor 105. This operation is performed for all pixels, and the standard potential is applied to the gate. The current value output by the transistor 112 at this time is obtained.

[0111] The circuit 16 reads and analyzes the current value and selects the transistor whose current value is the average or median value. The correction data W stored in each pixel is based on the Vth The correction data W Vt h is input to the column driver 13 and stored in the memory circuit MEM of each pixel. The circuit 16 has a function of reading the current value and outputs the correction data W Vth The function to generate other circuits may have.

[0112] After that, the display operation is performed by adding correction data to the image data in the same way as the up-conversion operation. The threshold voltage of a transistor may vary significantly over a long period of time. However, the fluctuations over a short period are extremely small. Therefore, the generation of correction data and memory recovery The operation of storing data in the ROM does not need to be performed for each frame, but rather when the power is turned on or turned off. Alternatively, the operating time of the display device can be recorded and used in units of days, weeks, months, years, etc. It may be carried out at regular intervals.

[0113] In addition, when both the threshold voltage correction and up-conversion are performed, the block diagram of FIG. As shown in the block diagram, a circuit 14 (see FIG. 5) for generating correction data for up-conversion is provided. In this case, the correction data W generated by the circuit 14 may be Vth is circuit 1 6, and the threshold voltage correction data for up-conversion is output from the circuit 16. Correction data for W Vth The correction data W' to which the value W is added is input to the column driver 13. do.

[0114] In the above, the current value output by the transistor 112 is actually measured and the correction data W Vth to produce However, there are other ways to create the correction data W. Vth For example, , a grayscale display is performed, and the brightness of the display is read using a luminance meter. Correction data W based on the data read from the photo Vth The correction data may be generated. W Vth It is preferable to use inference using a neural network for generating the above.

[0115] The display device of one embodiment of the present invention has an up-converting structure in the pixel as described in FIGS. Therefore, the image data supplied to the pixels is This is low-resolution image data, and the same image data is supplied to multiple pixels. (Figure 3) In the examples shown in (A) and (B), the same image data is supplied to four pixels in the horizontal and vertical directions. In this case, the same image data may be supplied to each of the signal lines connected to each pixel. By electrically connecting the signal lines that supply image data, the image data writing operation can be made faster.

[0116] FIG. 8 shows a part of a pixel array of a display device capable of displaying color. The signal lines supplying the data can be electrically connected to each other via a switch. Generally, the pixels of a display device that can display color are R (red), G (green), and B (blue). In Figure 8, the sub-pixels that emit the R, G, and B colors are arranged horizontally. These three sub-pixels make up one pixel, representing four pixels in the horizontal and vertical directions. .

[0117] As explained in Fig. 3(A) and (B), the same image data is stored in four pixels in the horizontal and vertical directions. In FIG. 8, the same image data is input to pixels R1 to R4. For example, the wiring 1 connected to each of the pixels R1 to R4 and functioning as a signal line The same image data is supplied to 25[1] and 125[4], and the wiring 122 functions as a scanning line. By inputting signals sequentially to [1], 122[2], the same image data is input to all pixels. However, in this method, when the same image data is supplied to multiple pixels, That's a lot of waste.

[0118] In one aspect of the present invention, two signal lines are connected to each other by a switch provided between the signal lines. By connecting two scanning lines with a switch provided between the scanning lines, This allows for simultaneous writing of four pixels.

[0119] As shown in FIG. 8, a switch 141 is provided between the wirings 125[1] and 125[4]. By turning on the line 125[1] or 125[4], the image data supplied to either line 125[1] or 125[4] is Data can be written to pixels R1 and R2 simultaneously. By keeping the switch 144 connected to the wiring 122[2] conductive, the pixel R3 and pixel R4 can also be written at the same time. In other words, simultaneous writing of four pixels is possible. This becomes:

[0120] Similarly, a switch 142 provided between the wiring 125[2] and 125[5], and a wiring The switch 143 provided between 125[3] and 125[6] is turned on as needed. By doing so, simultaneous writing to four pixels is possible in other pixels as well. The element 144 can be, for example, a transistor.

[0121] By being able to write to four pixels simultaneously, the writing time can be shortened, and the frame The wave number can also be increased.

[0122] This embodiment mode may be implemented by appropriately combining with the configurations described in other embodiment modes or examples. It is possible to implement this.

[0123] (Embodiment 2) In this embodiment, a configuration example of a display device using an EL element will be described. In this embodiment, the description of the operations and functions relating to the correction described in the first embodiment will be omitted. do.

[0124] 9A to 9C illustrate the structure of a display device that can use one embodiment of the present invention. is.

[0125] In FIG. 9A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is attached to the sealant 4005 and the second substrate 40 It is sealed by 06.

[0126] The display portion 215 is provided with a pixel array having the pixels described in Embodiment 1.

[0127] In FIG. 9A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 2 32a and the common line driving circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a are formed of a conductor. The scanning line driving circuit 221a has the function of the column driver shown in the first embodiment. The common line driver circuit 241a has the function of the row driver shown in the first embodiment. The common wiring has a function of supplying a specified potential to the common wiring shown in FIG.

[0128] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal Various signals and potentials are applied to the signal line driver circuit 232a via a flexible printed circuit (FPC). The power supply is supplied via a 4018 printed circuit.

[0129] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 included in the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area from the area where it is installed.

[0130] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0131] FIG. 9B shows the integrated circuits included in the signal line driver circuit 231a and the signal line driver circuit 232a. In this example, the circuit 4042 is mounted by the COG method. can be formed integrally on the same substrate as the display unit 215 to form a system-on-panel. do.

[0132] In FIG. 9B, the scanning line driving circuit 221a and the common line driving circuit 241a are connected to the display unit 21. 5 is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts in a single piece, the number of parts can be reduced, thereby increasing productivity. Cut.

[0133] In FIG. 9B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided so as to surround the circuit 221a and the common line driver circuit 241a. In addition, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 221b are provided. The second substrate 4006 is provided on the display unit 215 and the scanning line driver 41a. The circuit 221a and the common line driver circuit 241a are formed on the first substrate 4001 and the sealing material 400. 5 and the second substrate 4006, sealing the display element together.

[0134] In addition, in FIG. 9B, the signal line driver circuit 231a and the signal line driver circuit 232a are separately formed. 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. Alternatively, a part of the driving circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a may be formed on the same substrate as the display unit 215. good.

[0135] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0136] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be used as the transistor. can be done.

[0137] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit may be the same or different. They may have the same structure, or two or more types of structures may be used in combination. The transistors in the pixel circuit may all have the same structure, or may have two or more types of structures. may also be used in combination.

[0138] An input device 4200 can be provided on the second substrate 4006. A display device provided with an input device 4200 can function as a touch panel.

[0139] There is no limitation on the detection elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0140] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or the like.

[0141] In this embodiment, a touch panel having a capacitance type detection element will be described as an example. .

[0142] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0143] The touch panel of one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is formed on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0144] 10(A) and (B) show examples of touch panels. FIG. 10(A) shows a touch panel 4 10(B) is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0145] The touch panel 4210 is made by bonding a display device and a sensing element that are separately manufactured. be.

[0146] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0147] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b can be provided.

[0148] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In this case, in addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. may be applied.

[0149] FIG. 11 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. 9(B). The display device has an electrode 4015, which is different from the terminal of the FPC 4018. 11, the electrodes 401 are electrically connected via the isotropic conductive layer 4019. 5 is an insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 in an opening formed therein. The wiring 4014 is electrically connected to the wiring 4014 .

[0150] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0151] The display portion 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are In FIG. 11, the display unit 215 includes a transistor 401. 0 and a transistor 4011 included in the scanning line driver circuit 221a. In FIG. 11, the transistors 4010 and 4011 are bottom gate Although a top-gate transistor is shown as an example, a top-gate transistor may also be used.

[0152] In FIG. 11, an insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. In addition, a partition wall 4510 is formed over the insulating layer 4112.

[0153] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The electrode 4017 is formed on the semiconductor substrate 401. The electrode 4017 functions as a back gate electrode. It is possible.

[0154] The display device shown in FIG. 11 further includes a capacitor 4020. The electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and the source electrode and These electrodes are formed by the same process as the insulating layer 41. Overlapping through 03.

[0155] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0156] The transistor 4010 provided in the display portion 215 is electrically connected to a display element.

[0157] 11 also includes an insulating layer 4111 and an insulating layer 4104. The insulating layer 411 and the insulating layer 4104 are formed using an insulating layer that is not easily permeated by impurity elements. The semiconductor layer of the transistor is sandwiched between the insulating layer 4104 and the insulating layer 4105, which prevents impurities from entering from the outside. It can be prevented.

[0158] As a display element included in the display device, a light-emitting element (E An EL element can be applied. An EL element contains a light-emitting compound between a pair of electrodes. A layer (also called an "EL layer") having a voltage higher than the threshold voltage of the EL element is provided between a pair of electrodes. When a small potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, causing the luminescent material contained in the EL layer to emit light. It glows.

[0159] EL elements are also classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0160] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer, and then the carriers (electrons and holes) recombine. By this, the light-emitting organic compound forms an excited state, and the excited state returns to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element. It is called a child.

[0161] In addition to the light-emitting compound, the EL layer may contain a material having a high hole injection property and a material having a high hole transport property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The layer may contain a highly functional substance (a substance having high electron-transporting and hole-transporting properties).

[0162] The EL layer can be formed by a variety of methods, including vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0163] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0164] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission structure, which emits light from the top surface, and bottom emission structure, which emits light from the surface of the substrate. (bottom emission) structure and double-sided emission (dual emission) structure There are light emitting elements with a light-emitting structure, and any light emitting element with an emission structure can be applied.

[0165] FIG. 11 shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is a transistor provided in the display portion 215. The light-emitting element 4513 is electrically connected to the first electrode layer. 4030, a light-emitting layer 4511, and a second electrode layer 4031. The direction of the light emitting element 4513 is adjusted according to the direction of the light extracted from the light emitting element 4513. The configuration can be changed as appropriate.

[0166] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is It is preferable to form the inclined surface with a curvature.

[0167] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked. Either way is fine.

[0168] The light emitting element 4513 emits light in a variety of colors, including white, red, green, and blue, depending on the material that makes up the light emitting layer 4511. , cyan, magenta, or yellow, etc.

[0169] To achieve color display, a white light-emitting element 4513 is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light emitting element 4513 with a different luminescent color for each pixel. The first method has higher productivity than the latter method. However, the latter method is less productive than the former method because it requires separate production. In addition to the latter method, it is possible to obtain an emission color with higher color purity than the former method. By adding a microcavity structure to the element 4513, color purity can be further improved. can be done.

[0170] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. By using the child dots in the light-emitting layer, they can also function as a light-emitting material.

[0171] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (laminating film) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. Desirable.

[0172] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or Ethylene vinyl acetate (EVA) can also be used. may contain a desiccant.

[0173] The sealing material 4005 is made of glass materials such as glass frit, or ordinary materials such as two-component mixed resin. Resin materials such as heat-curable resin, photo-curable resin, and thermosetting resin can be used. The sealing material 4005 may also contain a desiccant.

[0174] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0175] In addition, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves the visibility of the displayed image.

[0176] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0177] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0178] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or its alloy, or metal nitride thereof. .

[0179] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or Its derivatives are also included.

[0180] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0181] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0182] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0183] The display device of one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a transistor having a MOSFET. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0184] [Bottom-gate transistor] FIG. 12(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 12A1 is a cross-sectional view of a transistor 810. In FIG. The transistor 810 is formed on a substrate 771 with an insulating layer 772 interposed therebetween. An electrode 746 is provided on the semiconductor layer 742. The semiconductor layer 742 is provided on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer. It can function.

[0185] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0186] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This prevents the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0187] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0188] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, forming an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0189] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0190] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0191] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0192] The transistor 811 shown in FIG. 12A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0193] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0194] Both the electrode 746 and the electrode 723 can function as gate electrodes. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate electrode. That's fine.

[0195] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0196] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0197] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0198] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0199] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0200] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0201] Figure 12(B1) shows a channel protection transistor, which is one of the bottom gate transistors. 8 shows a cross-sectional view of transistor 820. Transistor 820 has a similar structure to transistor 810. The structure is different in that an insulating layer 741 covers the edge of the semiconductor layer 742. In addition, in an opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer 742, The semiconductor layer 742 and the electrode 744a are electrically connected to each other. In another opening formed by selectively removing a part of the insulating layer 741, the semiconductor layer 7 The insulating layer 741 is electrically connected to the electrode 744b. The region can function as a channel protection layer.

[0202] The transistor 821 shown in FIG. 12B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0203] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0204] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 is In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0205] The transistor 825 shown in FIG. 12C1 is a bottom-gate transistor. The transistor 825 is a channel-etched transistor having an insulating layer 741. Electrodes 744a and 744b are formed without using the When forming the electrode 744b, a part of the semiconductor layer 742 that is exposed may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0206] The transistor 826 shown in FIG. 12C2 has a back gate electrode over the insulating layer 729. It differs from transistor 825 in that it has a functioning electrode 723 .

[0207] [Top-gate transistor] The transistor 842 illustrated in FIG. 13A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed on the insulating layer 728 and the insulating layer 729. The insulating film 742 is electrically connected to the semiconductor layer 742 in the opening.

[0208] Also, as shown in FIG. 13(A3), a part of the insulating layer 726 that does not overlap with the electrode 746 is removed. Then, the electrode 746 and the remaining insulating layer 726 are used as a mask to inject impurities 755 into the semiconductor layer 74. 2, the impurity region is self-aligned in the semiconductor layer 742. The transistor 842 has an insulating layer 726 that covers an edge of the electrode 746. When the impurity 755 is introduced into the semiconductor layer 742, the semiconductor layer The impurity concentration in the region where the impurity 755 is introduced through the insulating layer 726 of 742 is 26. Therefore, the area of the semiconductor layer 74 2 is a lightly doped drain (LDD) in an area that does not overlap with the electrode 746. ) region is formed.

[0209] The transistor 843 shown in FIG. 13A2 has the electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0210] In addition, the transistor 844 shown in FIG. 13B1 and the transistor 845 shown in FIG. 13B2 As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 13C1 and the transistor 846 shown in FIG. 13C2 The insulating layer 726 may remain, as may the insulating layer 847.

[0211] The transistors 842 to 847 are also formed with the electrode 746. As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. Furthermore, according to one aspect of the present invention, a transistor with good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0212] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0213] (Fourth embodiment) In this embodiment, the row driver 12, the column driver 13, The semiconductor device applicable to the circuits 14 and 16 will be described below. The conductor device can function as a memory device.

[0214] In this embodiment, a DOSRAM (registered trademark) is used as an example of a memory device including an oxide semiconductor. The name "DOSRAM" stands for Dynamic Oxide Derived from Semiconductor Random Access Memory DOSRAM is a memory cell that is a 1T1C (one transistor, one capacitor) type cell. In addition, the write transistor is a transistor to which an oxide semiconductor is applied. And so.

[0215] An example of the stacked structure of the DOSRAM1000 will be described with reference to FIG. 000 is a circuit diagram of a sense amplifier unit 1002 that reads data and a cell amplifier unit 1003 that stores data. The layer portion 1003 is laminated.

[0216] As shown in FIG. 14, the sense amplifier unit 1002 includes a bit line BL, a Si transistor T The Si transistors Ta10 and Ta11 are single crystal silicon. The silicon wafer has a semiconductor layer. Si transistors Ta10 and Ta11 are sense amplifiers. and is electrically connected to the bit line BL.

[0217] The cell array section 1003 has a plurality of memory cells 1001. The cell array section 1003 has two transistors Tw1 and a capacitance element C1. The transistor Tw1 shares the semiconductor layer. The semiconductor layer and the bit line BL are connected by a conductor (not shown). are electrically connected by

[0218] The stacked structure shown in FIG. 14 is constructed by stacking multiple circuits each having a group of transistors. It can be applied to various semiconductor devices.

[0219] The metal oxides, insulators, conductors, etc. in FIG. 14 may be single-layer or multi-layered. , sputtering method, molecular beam epitaxy method (MBE method), pulsed laser ablation Various film formation methods such as PLA method, CVD method, and atomic layer deposition method (ALD method) can be used. There are various CVD methods, such as plasma CVD, thermal CVD, and metal organic CVD. There are some.

[0220] Here, the semiconductor layer of the transistor Tw1 is made of metal oxide (oxide semiconductor). Here, an example is shown in which the semiconductor layer is composed of three metal oxide layers. The dielectric layer is preferably composed of a metal oxide containing In, Ga, and Zn.

[0221] Here, the metal oxide is formed by adding an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. For example, when a metal oxide is used, the carrier density increases and the resistance decreases. By selectively lowering the resistance of the semiconductor layer used, a source region or a drain region can be formed in the semiconductor layer. A region can be established.

[0222] Representative elements that reduce the resistance of metal oxides include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. Representative examples of rare gas elements include helium, neon, argon, krypton, and The concentration of the element is measured by Secondary Ion Mass Spectroscopy (SIMS). It can be measured using methods such as ion mass spectrometry (MMS). Cut.

[0223] In particular, boron and phosphorus are essential for the production of amorphous silicon or low-temperature polysilicon. This is preferable because existing equipment can be used. Capital investment can be reduced.

[0224] A transistor having a semiconductor layer selectively reduced in resistance uses, for example, a dummy gate. Specifically, a dummy gate is provided on the semiconductor layer, and the dummy gate is The gate is used as a mask to add an element that reduces the resistance of the semiconductor layer. The element is added to the region of the semiconductor layer that does not overlap with the dummy gate, and the resistance is reduced. The element is added by adding an ionized source gas to the Ion implantation method in which mass separation is performed before addition, and ionized source gas is added without mass separation. Ion doping, plasma immersion ion implantation, etc. It is possible.

[0225] The conductive material used for the conductor is polycrystalline silicon doped with impurity elements such as phosphorus. Semiconductors such as nickel silicide, molybdenum, titanium, tungsten Metals such as aluminum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitrides containing the above-mentioned metals (tantalum nitride, titanium nitride, molybdenum nitride) In addition, indium tin oxide, indium tin oxide containing tungsten oxide, etc. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide doped with silicon can be used.

[0226] The insulating materials used for the insulator include aluminum nitride, aluminum oxide, and aluminum nitride oxide. Aluminum, aluminum oxide nitride, magnesium oxide, silicon nitride, silicon oxide, nitrogen Silicon oxide nitride, silicon oxide, gallium oxide, germanium oxide, yttrium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, In this specification, the term "oxynitride" refers to a compound containing oxygen. Nitrogen oxides are compounds in which the nitrogen content is higher than the oxygen content. This refers to compounds that are

[0227] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0228] (Embodiment 5) In this embodiment, a neural network that can be used in the circuit 14 described in the first embodiment is used. An example of the configuration of a semiconductor device that functions as a network will be described.

[0229] As shown in Figure 15(A), the neural network NN consists of an input layer IL, an output layer OL, and a middle layer OL. It can be composed of an input layer IL, an output layer OL, and an intermediate layer H Each L has one or more neurons (units). It may be a single layer or two or more layers. The network can also be called a DNN (deep neural network), and Learning using neural networks can also be called deep learning.

[0230] Input data is input to each neuron in the input layer IL, and previous data is input to each neuron in the hidden layer HL. The output signal of the neurons in the layer OL or the subsequent layer is input, and each neuron in the output layer OL receives the signal of the neurons in the previous layer. The output signal of each neuron is input. Each neuron is connected to all the neurons in the previous and next layers. It may be connected to all neurons (fully connected) or to a portion of neurons.

[0231] Figure 15(B) shows an example of a computation by a neuron. Here, we consider a neuron N and a neuron B. The figure shows two neurons in the front layer that output signals to neuron N. Neuron N has a The output x1 of the neuron in the previous layer and the output x2 of the neuron in the previous layer are input. In Ron N, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum of the calculation results (x2w2) x1w1+x2w2 is calculated, the bias b is applied as needed. are added to obtain the value a=x1w1+x2w2+b. The value a is then applied to the activation function h Thus, the neuron N outputs the output signal y=h(a).

[0232] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. When the multiply-and-accumulate operation is performed by hardware, a multiply-and-accumulate circuit can be used. This product-sum operation circuit may be a digital circuit or an analog circuit. Good too.

[0233] In one embodiment of the present invention, an analog circuit is used for the sum-of-products circuit. The reduction of circuit scale or the reduction of memory access times improves processing speed and Power consumption can be reduced.

[0234] The sum-of-products operation circuit may be configured using Si transistors or OS transistors. In particular, since the off-state current of an OS transistor is extremely small, it is possible to It is suitable as a transistor for composing an analog memory of a circuit. A multiply-accumulate circuit may be configured using both an OS transistor and an OS transistor. A configuration example of a semiconductor device having the above functions will be described.

[0235] <Configuration example of semiconductor device> FIG. 16 shows an example of the configuration of a semiconductor device MAC having a function for performing neural network calculations. The semiconductor device MAC stores first data corresponding to the connection strength (weight) between neurons. The first data has a function of performing a multiplication and accumulation operation on the second data corresponding to the input data. The first data and the second data are analog data or multi-valued data (discrete data). The semiconductor device MAC can be configured as a data (data) obtained by the multiplication and accumulation operation. It has the function of transforming by an activation function.

[0236] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, and a circuit WDD, circuit WLD, circuit CLD, offset circuit OFST, and activation function circuit AC Has a TV.

[0237] The cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. FIG. 16 shows a cell array CA having memory cells MC (M C[1,1] to [m,n]), and m memory cells MCref (MCref[1] to The memory cell MC has a function of storing first data. The memory cell MCref stores reference data used in the multiply-and-accumulate operation. The reference data can be analog data or multi-valued data. do.

[0238] The memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is It is connected to line WL[i], wiring RW[i], wiring WD[j], and wiring BL[j]. The memory cell MCref[i] is connected to the wiring WL[i], the wiring RW[i], and the wiring WD ref and the wiring BLref. Here, the memory cell MC[i,j] and the wiring B The current flowing between L[j] is I MC[i,j] and the memory cell MCref[i] is The current flowing between the lines BLref is I MCref[i] It is written as follows.

[0239] A specific example of the configuration of the memory cell MC and the memory cell MCref is shown in FIG. As representative examples, memory cells MC[1,1], [2,1] and memory cell MCref[ 1] and [2] are shown, but the same applies to other memory cells MC and memory cells MCref. The memory cell MC and the memory cell MCref can be configured as follows: The transistors Tr11 and Tr12 and the capacitance element C11 are included. This section explains the case where r11 and transistor Tr12 are n-channel transistors. Reveal.

[0240] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, and the source Alternatively, one of the drains is connected to the gate of the transistor Tr12 and the first terminal of the capacitance element C11. The other of the source and drain is connected to the wiring WD. Either the source or the drain of transistor Tr12 is connected to wiring BL. The other electrode of the capacitor C11 is connected to the wiring VR. The second electrode of the capacitor C11 is connected to the wiring RW. The wiring VR is a wiring that has a function of supplying a predetermined potential. Next, a case where a low power supply potential (ground potential, etc.) is supplied from the wiring VR will be described.

[0241] One of the source and drain of the transistor Tr11, the gate of the transistor Tr12, The node connected to the first electrode of the capacitance element C11 is referred to as a node NM. The nodes NM of Moricells MC[1,1] and MC[2,1] are respectively called nodes NM[1,1] and NM[2,1]. It is written as [2,1].

[0242] The memory cell MCref has the same configuration as the memory cell MC. Cref is connected to the wiring WDref instead of the wiring WD, and the wiring BL is connected to the wiring BL ref. Also, in memory cells MCref[1] and [2], one of the source or drain of transistor Tr11, the gate of transistor Tr12, and The nodes connected to the first electrodes of the capacitance elements C11 are referred to as nodes NMref[1] and NMref[2], respectively. This is written as [2].

[0243] The node NM and the node NMref are the storage nodes of the memory cell MC and the memory cell MCref, respectively. The node NM holds the first data, and the node NMref holds the second data. The reference data is stored in the memory cell MC[1,1], [2] from the wiring BL[1]. ,1], the current I MC[1,1] , I MC[2,1] Also, the transistors of the memory cells MCref[1] and [2] are connected to the wiring BLref. The current I MCref[1] , I MCref[2] is playing.

[0244] The transistor Tr11 has the function of maintaining the potential of the node NM or the node NMref. Therefore, it is preferable that the off-state current of the transistor Tr11 is small. It is preferable to use an OS transistor with extremely low off-state current as the transistor Tr11. This makes it possible to suppress fluctuations in the potential of the node NM or the node NMref, The calculation accuracy can be improved. This makes it possible to reduce the frequency of refreshing operations, thereby reducing power consumption. Cut.

[0245] The transistor Tr12 is not particularly limited and may be, for example, a Si transistor or an OS transistor. When an OS transistor is used as the transistor Tr12, The transistor Tr12 can be manufactured using the same manufacturing equipment as the transistor Tr11. This makes it possible to reduce manufacturing costs. It may be either a p-channel type or a n-channel type.

[0246] The current source circuit CS is connected to the wirings BL[1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL[1] to [n] and the wiring BLref. Note that the current values supplied to the wirings BL[1] to BL[n] and the current value supplied to the wiring BLref are The supplied current value may be different. Here, the current source circuit CS is connected to the wiring BL[1]. The current supplied to [n] is I C , the current supplied from the current source circuit CS to the wiring BLref I Cref It is written as follows.

[0247] The current mirror circuit CM has wirings IL[1] to IL[n] and wiring ILref. The wirings IL[1] to IL[n] are connected to the wirings BL[1] to BL[n], respectively, and the wirings ILr ef is connected to the wiring BLref. Here, the wirings IL[1] to IL[n] and the wiring The connection points of BL[1] to [n] are expressed as nodes NP[1] to [n]. The connection point between ILref and wiring BLref is denoted as node NPref.

[0248] The current mirror circuit CM generates a current I according to the potential of the node NPref. CM Wiring ILre f and this current I CM It also has the function of sending the signal to the wiring IL[1] to [n]. 16, the current I CM is discharged, and wiring BL[1] A current I flows from the wiring IL[1] to [n]. CM This shows an example of the discharge of In addition, current flows from the current mirror circuit CM to the cell array CA via the wiring BL[1] to [n]. The current that flows is I B The current mirror circuit CM is connected to the The current flowing through the cell array CA via BLref is I Bref It is written as follows.

[0249] The circuit WDD is connected to the wirings WD[1] to WD[n] and the wiring WDref. The WDD supplies a potential corresponding to the first data stored in the memory cell MC to the wiring WD[1] The circuit WDD has a function of supplying the data stored in the memory cell MCref to the The circuit WL has a function of supplying a potential corresponding to the reference data to the wiring WDref. D is connected to the wirings WL[1] to WL[m]. A signal for selecting the memory cell MC or memory cell MCref to be used is transmitted through a wiring WL[1 The circuit CLD is connected to the wirings RW[1] to RW[m]. The circuit CLD supplies a potential corresponding to the second data to the wirings RW[1] to RW[m]. It has the function of supplying

[0250] The offset circuit OFST includes wirings BL[1] to [n] and wirings OL[1] to [n]. The offset circuit OFST is connected to the offset line from the wiring BL[1] to [n]. The amount of current flowing through the offset circuit OFST and / or the offset from the wiring BL[1] to [n] It has the function of detecting the amount of change in the current flowing through the offset circuit OFST. OFST has the function of outputting the detection results to wiring OL[1] to [n]. The set circuit OFST may output a current corresponding to the detection result to the wiring OL, or may The current corresponding to the result may be converted into a voltage and output to the wiring OL. The current flowing between the gate circuit OFST is I α These are written as [1] to [n].

[0251] An example of the configuration of the offset circuit OFST is shown in Fig. 18. has circuits OC[1] to OC[n]. Each of the circuits OC[1] to OC[n] has the following: Transistor Tr21, transistor Tr22, transistor Tr23, and capacitor C21 The connection relationship of each element is as shown in FIG. A node connected to the first electrode of the capacitance element C21 and the first terminal of the resistance element R1 is referred to as a node The second electrode of the capacitance element C21, the source or The node connected to one of the drains and the gate of the transistor Tr22 is called the node Let Nb.

[0252] The wiring VrefL has a function of supplying a potential Vref, and the wiring VaL supplies a potential Va. The wiring VbL has a function of supplying a potential Vb. The wiring VSSL has a function of supplying a potential VSS. Now, let's consider the case where the potential VDD is the high power supply potential and the potential VSS is the low power supply potential. The wiring RST supplies a potential for controlling the conduction state of the transistor Tr21. Transistor Tr22, transistor Tr23, wiring VDDL, wiring The line VSSL and the wiring VbL form a source follower circuit.

[0253] Next, an example of the operation of the circuits OC[1] to [n] will be described. An example of the operation of OC[1] will be explained, but circuits OC[2] to [n] can also be operated in the same way. First, when a first current flows through the wiring BL[1], the potential of the node Na becomes equal to the first current. The potential is determined by the current and the resistance value of the resistor element R1. The transistor Tr21 is in the ON state, and the potential Va is supplied to the node Nb. It will be in the off state.

[0254] Next, when a second current flows through the wiring BL[1], the potential of the node Na increases depending on the second current and the resistance The potential changes according to the resistance value of the element R1. At this time, the transistor Tr21 is in the off state. Since the node Nb is in a floating state, the potential of the node Na changes. The potential of the node Nb changes due to capacitive coupling. Here, the change in the potential of the node Na is expressed as Δ V Na If the capacitance coupling coefficient is 1, the potential of node Nb is Va+ΔV Na It becomes. Then, the threshold voltage of transistor Tr22 is V th Then, the potential from the wiring OL[1] Va+ΔV Na -V th is output, where Va=V th By doing so, the wiring L[1] to potential ΔV Na can be output.

[0255] Potential ΔV Na is the change amount from the first current to the second current, the resistance value of the resistive element R1, and The resistance value of the resistor R1 and the potential Vref are known. Therefore, the potential ΔV Na From this, the amount of change in the current flowing through the wiring BL can be obtained.

[0256] The amount of current detected by the offset circuit OFST as described above and / or the The signal corresponding to the change amount is sent to the activation function circuit ACTV via wiring OL[1] to [n]. is entered.

[0257] The activation function circuit ACTV includes wirings OL[1] to OL[n] and wirings NIL[1] to NIL[n]. The activation function circuit ACTV receives input from the offset circuit OFST. A function that performs operations to transform the received signal according to a predefined activation function. The activation function can be, for example, a sigmoid function, a tanh function, a softma x function, ReLU function, threshold function, etc. can be used. Activation function circuit ACT The signal converted by V is output to the wiring NIL[1] to [n] as output data. do.

[0258] <Example of semiconductor device operation> The semiconductor device MAC can be used to perform a multiplication and accumulation operation on first data and second data. An example of the operation of the semiconductor device MAC when performing a product-sum operation will be described below.

[0259] FIG. 19 shows a timing chart of an example of the operation of the semiconductor device MAC. In the wiring WL[1], wiring WL[2], wiring WD[1], wiring WDref, node NM [1,1], node NM[2,1], node NMref[1], node NMref[2] , the transition of the potential of wire RW[1] and wire RW[2], and the current I B [1]-I α [1] , and current I Bref The graph shows the transition of the value of the current I B [1]-I α [1] is the wiring This corresponds to the sum of the currents flowing from BL[1] to memory cells MC[1,1] and [2,1].

[0260] As a representative example, memory cells MC[1,1], [2,1] and The operation will be explained focusing on memory cells MCref[1] and [2], but other memory cells MC The memory cell MCref can also be operated in the same manner.

[0261] [Storage of first data] First, at time T01-T02, the potential of the wiring WL[1] becomes high level, and the potential of the wiring W The potential of D[1] is V higher than the ground potential (GND). PR -V W[1,1] It becomes a large potential, The potential of the wiring WDref is V higher than the ground potential. PR The potential is large. Also, the wiring RW[1] , and the potential of the wiring RW[2] is the reference potential (REFP).W[1,1 ] is a potential corresponding to the first data stored in the memory cell MC[1,1]. Potential V PR is the potential corresponding to the reference data. The transistor Tr11 of the memory cell MCref[1] is turned on, and The potential of node NM[1,1] is V PR -V W[1,1] , the potential of node NMref[1] is V PR This becomes:

[0262] At this time, a current flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. The current I MC[1,1],0 can be expressed as follows: where k is the number of transistors The constant is determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of Tr12. Also, V th is the threshold voltage of transistor Tr12.

[0263] I MC[1,1],0 =k(V PR -V W[1,1] -V th ) 2 (E1)

[0264] Also, the current flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. current I MCref[1],0 can be expressed by the following formula:

[0265] I MCref[1],0 =k(V PR -V th ) 2 (E2)

[0266] Next, at time T02-T03, the potential of the wiring WL[1] becomes low level. Therefore, the transistors of the memory cell MC[1,1] and the memory cell MCref[1] The transistor Tr11 is turned off, and the voltages of the nodes NM[1,1] and NMref[1] are The position is maintained.

[0267] As described above, it is preferable to use an OS transistor as the transistor Tr11. This makes it possible to suppress the leakage current of the transistor Tr11, and the node NM[ 1,1] and the potential of node NMref[1] can be accurately maintained.

[0268] Next, at time T03-T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring W The potential of D[1] is V higher than the ground potential. PR -V W[2,1] This results in a large potential, and the wiring WDr The potential of ef is V higher than the ground potential. PR The potential V W[2,1] Ha Memo This potential corresponds to the first data stored in the memory cell MC[2,1]. The transistor Tr1 included in the memory cell MC[2,1] and the memory cell MCref[2] 1 is turned on, and the potential of node NM[2,1] becomes V PR -V W[2,1] , node N The potential of Mref[2] is V PR This becomes:

[0269] At this time, a current flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. The current I MC[2,1],0 can be expressed by the following formula:

[0270] I MC[2,1],0 =k(V PR -V W[2,1] -V th ) 2 (E3)

[0271] Also, the current flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. current I MCref[2],0 can be expressed by the following formula:

[0272] I MCref[2],0 =k(V PR -V th ) 2 (E4)

[0273] Next, at time T04-T05, the potential of the wiring WL[2] becomes low level. Therefore, the transistors of the memory cell MC[2,1] and the memory cell MCref[2] The transistor Tr11 is turned off, and the voltages of the nodes NM[2,1] and NMref[2] are The position is maintained.

[0274] By the above operation, the first data is stored in the memory cells MC[1,1] and MC[2,1]. Reference data is stored in memory cells MCref[1] and MCref[2].

[0275] Here, at time T04-T05, the current flowing through the wiring BL[1] and the wiring BLref The current is supplied to the wiring BLref from the current source circuit CS. The current flowing through Lref is calculated by the current mirror circuit CM and the memory cells MCref[1], [2 The current supplied from the current source circuit CS to the wiring BLref is I Cref , distribution The current flowing from the line BLref to the current mirror circuit CM is I CM,0 Then, the following The formula holds.

[0276] I Cref -I CM,0 =I MCref[1],0 +I MCref[2],0 (E5)

[0277] The wire BL[1] is supplied with current from the current source circuit CS. The current flows through the current mirror circuit CM and is discharged to the memory cells MC[1,1] and MC[2,1]. In addition, current flows from the wiring BL[1] to the offset circuit OFST. The current supplied from CS to wire BL[1] is I C,0 , offset from wiring BL[1] The current flowing through the OFST is I α,0 Then, the following formula holds:

[0278] I C -I CM,0 =I MC[1,1],0 +I MC[2,1],0 +I α,0 (E6)

[0279] [Multiply and add operations on the first and second data] Next, at time T05-T06, the potential of the wiring RW[1] becomes V X[1] At this time, the memory cell MC[1,1] and the memory cell MCref Each capacitance element C11 in [1] has a potential V X[1] is supplied, and the transistor is The potential of the gate of transistor Tr12 rises. X[1] is the memory cell MC[ 1,1] and a potential corresponding to the second data supplied to the memory cell MCref[1]. be.

[0280] The change in the potential of the gate of the transistor Tr12 is proportional to the change in the potential of the wiring RW. The capacitance coupling coefficient is determined by the capacitance element C1. 1, the gate capacitance of transistor Tr12, and the parasitic capacitance. For the sake of convenience, the amount of change in the potential of the wiring RW and the amount of change in the potential of the gate of the transistor Tr12 are assumed below. In this explanation, we will assume that the capacitance coupling coefficient is 1. Considering the potential V X It is sufficient to determine the following.

[0281] The potential V X[1] When is supplied, the potentials of the nodes NM[1,1] and NMref[1] are V respectively X[1] Rise.

[0282] Here, at time T05-T06, the line BL[1] to the memory cell MC[1,1] Current I flowing through transistor Tr12 MC[1,1],1 can be expressed as follows: .

[0283] I MC[1,1],1 =k(V PR -V W[1,1] +V X[1] -V th ) 2 (E7)

[0284] That is, the potential V X[1] By supplying The current flowing through the transistor Tr12 of the memory cell MC[1,1] is ΔI MC[1,1] =I MC[1,1],1 -I MC[1,1],0 Increase.

[0285] Also, at time T05-T06, the line BLref is connected to the memory cell MCref[1]. Current I flowing through transistor Tr12 MCref[1],1 can be expressed as follows: do.

[0286] IMCref[1],1 =k(V PR +V X[1] -V th ) 2 (E8)

[0287] That is, the potential V X[1] By supplying The current flowing through the transistor Tr12 of the memory cell MCref[1] is ΔI MCref[ 1] =I MCref[1],1 -I MCref[1],0 Increase.

[0288] Next, consider the current flowing through the wiring BL[1] and the wiring BLref. f is the current I from the current source circuit CS Cref Also, the current flows through the wiring BLref. The current is discharged to the current mirror circuit CM and the memory cells MCref[1] and MCref[2]. The current flowing from the wiring BLref to the current mirror circuit CM is I CM,1 Then, The following equation holds:

[0289] I Cref -I CM,1 =I MCref[1],1 +I MCref[2],1 (E9)

[0290] The wire BL[1] carries the current I from the current source circuit CS. C Also, wiring BL[1] The current flowing through the current mirror circuit CM is discharged to the memory cells MC[1,1] and MC[2,1]. Furthermore, current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from BL[1] to the offset circuit OFST is I α,1 Then, the following equation is obtained: stand.

[0291] IC -I CM,1 =I MC[1,1],1 +I MC[2,1],1 +I α,1 (E10)

[0292] Then, from equations (E1) to (E10), the current I α,0 and current I α,1 Difference (Differential Current ΔI α ) can be expressed as follows:

[0293] ΔI α =I α,1 -I α,0 =2kV W[1,1] V X[1] (E11)

[0294] In this way, the differential current ΔI α is the potential V W[1,1] and V X[1] The value depends on the product of .

[0295] After that, at time T06-T07, the potential of the wiring RW[1] becomes the reference potential, and the node The potentials of NM[1,1] and node NMref[1] are the same as those at times T04-T05. .

[0296] Next, at time T07-T08, the potential of the wiring RW[1] becomes V X[1] The potential of the wiring RW[2] becomes V higher than the reference potential. X[2] It becomes a large potential As a result, the memory cells MC[1,1] and MCref[1] are The potential V X[1] is supplied, and the node NM[1,1] is connected by capacitive coupling. and the potential of node NMref[1] are V X[1] Also, the memory cell A potential is applied to the capacitance element C11 of each of the memory cells MC[2,1] and MCref[2]. V X[2] is supplied, and the nodes NM[2,1] and NMref[ 2] are V X[2] Rise.

[0297] Here, at time T07-T08, the line BL[1] to the memory cell MC[2,1] Current I flowing through transistor Tr12 MC[2,1],1 can be expressed as follows: .

[0298] I MC[2,1],1 =k(V PR -V W[2,1] +V X[2] -V th ) 2 (E12)

[0299] That is, the potential V X[2] By supplying The current flowing through the transistor Tr12 of the memory cell MC[2,1] is ΔI MC[2,1] =I MC[2,1],1 -I MC[2,1],0 Increase.

[0300] Also, at time T07-T08, the line BLref is connected to the memory cell MCref[2]. Current I flowing through transistor Tr12 MCref[2],1 can be expressed as the following formula: do.

[0301] I MCref[2],1 =k(V PR +V X[2] -V th ) 2 (E13)

[0302] That is, the potential V X[2] By supplying The current flowing through the transistor Tr12 of the memory cell MCref[2] is ΔIMCref[ 2] =I MCref[2],1 -I MCref[2],0 Increase.

[0303] Next, consider the current flowing through the wiring BL[1] and the wiring BLref. f is the current I from the current source circuit CS Cref Also, the current flows through the wiring BLref. The current is discharged to the current mirror circuit CM and the memory cells MCref[1] and MCref[2]. The current flowing from the wiring BLref to the current mirror circuit CM is I CM,2 Then, The following equation holds:

[0304] I Cref -I CM,2 =I MCref[1],1 +I MCref[2],1 (E14)

[0305] The wire BL[1] carries the current I from the current source circuit CS. C Also, wiring BL[1] The current flowing through the current mirror circuit CM is discharged to the memory cells MC[1,1] and MC[2,1]. Furthermore, current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from BL[1] to the offset circuit OFST is I α,2 Then, the following equation is obtained: stand.

[0306] I C -I CM,2 =I MC[1,1],1 +I MC[2,1],1 +I α,2 (E15)

[0307] Then, from the equations (E1) to (E8) and the equations (E12) to (E15), the current I α,0 and current I α,2Difference in current (ΔI α ) can be expressed as follows:

[0308] ΔI α =I α,2 -I α,0 =2k(V W[1,1] V X[1] +V W[2,1] V X[ 2] ) (E16)

[0309] In this way, the differential current ΔI α is the potential V W[1,1] and potential V X[1] and the potential V W [2,1] and potential V X[2] The value is determined by adding the product of and .

[0310] After that, at time T08-T09, the potential of the wiring RW[1] and [2] becomes the reference potential. The potentials of the nodes NM[1,1], [2,1] and NMref[1], [2] are It will be the same as time T04-T05.

[0311] As shown in equations (E11) and (E16), the input to the offset circuit OFST is The differential current ΔI α is the potential V corresponding to the first data (weight) W and the second data (input (data) X It can be calculated from an equation with product terms, i.e. Differential current ΔI α By measuring the offset signal using the offset circuit OFST, the first data and the second data are The result of the multiplication and accumulation of data can be obtained.

[0312] In the above, memory cells MC[1,1], [2,1] and memory cell MCref Although we focused on [1] and [2], the number of memory cells MC and memory cells MCref can be arbitrarily set. The number m of rows of memory cells MC and memory cells MCref can be set to any number. The differential current ΔIα when i is used can be expressed by the following equation:

[0313] ΔI α =2kΣ i V W[i,1] V X[i] (E17)

[0314] In addition, by increasing the number n of columns of memory cells MC and memory cells MCref, This allows for an increased number of multiply-add operations to be performed.

[0315] As described above, by using the semiconductor device MAC, the product of the first data and the second data can be obtained. The memory cell MC and the memory cell MCref are shown in FIG. By using the configuration shown in 17, it is possible to configure a product-sum operation circuit with a small number of transistors. Therefore, it is possible to reduce the circuit scale of the semiconductor device MAC.

[0316] When the semiconductor device MAC is used for calculations in a neural network, the memory cell MC The number of rows m corresponds to the number of input data supplied to one neuron, and the number of memory cells MC The number of columns n can be made to correspond to the number of neurons. For example, the hidden layer shown in Figure 15(A) Consider a case where a multiply-and-accumulate operation is performed using a semiconductor device MAC in HL. The number of rows m of the cell MC is the number of input data supplied from the input layer IL (the number of neurons in the input layer IL). The number of columns n of memory cells MC is set to the number of neurons in the hidden layer HL. It is possible.

[0317] The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC uses convolutional neural networks (CNNs), recurrent neural networks (RNs), and Neural Networks (RNN), Autoencoders, Boltzmann Machines (Restricted Boltzmann Machines) It can also be used for other purposes, such as

[0318] As described above, by using the semiconductor device MAC, it is possible to Furthermore, the cell array CA includes the memory cells MC and MC shown in FIG. By using the memory cell MCref, it is possible to improve the calculation accuracy, reduce the power consumption, or It is possible to provide an integrated circuit that can be reduced in scale.

[0319] This embodiment mode may be implemented by appropriately combining with the configurations described in other embodiment modes or examples. It is possible to implement this.

[0320] (Embodiment 6) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 20.

[0321] FIG. 20A shows a television set, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 975. The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using the above, it is possible to perform a display with high display quality.

[0322] FIG. 20B shows an information processing terminal, which includes a housing 901, a display portion 902, a display portion 903, a sensor The display unit 902 and the display unit 903 are each made up of a single display panel, and are flexible. The housing 901 is also flexible and can be folded as shown in the figure. It can also be used in a flat form like a tablet device. 4 can sense the shape of the housing 901, for example, when the housing is bent, the display 9 The display of the display unit 902 and the display unit 903 can be switched. By using the display device of one embodiment of the present invention in 3, high-quality display can be achieved. do.

[0323] FIG. 20C shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 69 and the like. By using the display device of one embodiment of the present invention for the display portion 965, the display quality can be improved. High display is possible.

[0324] FIG. 20(D) shows a digital signage having a large display unit 922. For example, When the display device of one embodiment of the present invention is used for the display portion 922, A high-quality display can be achieved.

[0325] FIG. 20E shows a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, and an external The mobile phone has a connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The telephone has a touch sensor on the display 952. All operations such as the above can be performed by touching the display unit 952 with a finger or a stylus. The housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, A high-quality display can be achieved.

[0326] FIG. 20F shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera, and a camera body. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, the display quality can be improved. High display is possible.

[0327] This embodiment mode may be implemented by appropriately combining with the configurations described in other embodiment modes or examples. It is possible to implement this. [Example]

[0328] In this example, a result of fabricating a display device according to one embodiment of the present invention will be described.

[0329] Figure 21 shows an OS transistor (CAAC-IGZO) fabricated using the same process as the display device. FET, W / L=3μm / 3μm) D -V G Characteristics (Vds=0.1V, 5.1V) The transistor characteristics are normally off, and the off-current is below the lower limit of the measurement equipment. was the value.

[0330] The pixel circuit diagram is shown in Figure 22. The pixel circuit consists of five transistors, two capacitors, and The display element is an OLED. All transistors have a front gate and a A back gate is provided for electrical connection. The driving method is explained below. The period for writing the display data (corresponding to image data) is different from the period for writing the display data (corresponding to image data). It was the right timing.

[0331] <Writing weights (correction data)> The timing chart for writing weights to storage nodes is shown in FIG. 23(A). When writing, there is no need to make the display element OLED emit light, so transistor M5 is non-conductive. Then, transistors M1, M3, and M4 are turned on, and the reference voltage V r , fixed potential V0, The potential of the weight (V w ) were supplied, respectively.

[0332] <Writing display data (image data)> The timing chart for writing display data is shown in FIG. Since no rewriting is required, M4 is turned off and M1 is turned on to display data (V data )of The gate voltage V of the transistor M2 that drives the display element OLED is g is expressed as equation (1) where the capacitance element C w and the capacitance element C s The capacitance value of C w >>C s Relationship If so, the gate voltage V g is the value expressed by equation (2). In other words, the display data (V da ta ) with weight (V w -V r) will be added.

[0333]

number

number

[0334] <Simulation results> FIG. 24 shows the gate voltage V of transistor M2 when the weight value is changed. g Changes in the circuit This is the result calculated using simulation software (SPICE). By increasing the weight value, Gate voltage V g The results also showed an increase in

[0335] <Wide dynamic range display> The gate voltage V of transistor M2 g is the potential of the display data (V data ) and the weight potential ( V w ) can be expressed as the sum of the source driver (corresponding to the column driver) This means that a voltage equal to or greater than the output voltage of the transistor M2 can be applied to the gate of the transistor M2. This is useful when high brightness is required for display. w and the capacitance element C s The capacitance ratio of V is 4:1. r When =V0=0V, the transistor The voltage V applied to the gate of M2 g can be expressed by equation (3).

[0336]

number

[0337] If the maximum voltage that the source driver can output is 5V, the gate voltage of transistor M2 is Pressure V g The gate voltage V of transistor M2 reaches an ideal value of 9V. g to 4.5 If you want to set the voltage to V, you can output 2.5V from the source driver. The weight (V w ) and display data (V data ) alternately, the operating frequency must be increased, but the voltage is lowered. This will result in an overall reduction in power consumption.

[0338] <Panel specifications> The specifications of the prototype display device (panel) are shown in Table 1. ) is an OS transistor (CAAC-IGZO) element on the same substrate as the pixel circuit. The display element OLED is a tandem type that emits white light and is combined with a color filter. This is a colorization method that combines the two.

[0339] [Table 1]

[0340] <Result> Figure 25(A) is a photograph showing only the image data of the balloon that was input as a weight. 5(B) is a photograph showing only the image data of a zebra that was input as display data. Figure 25(C) shows the results of applying the image data of the balloon input as weights to the simulation data input as display data. This is a photo of the image of the mauma added to it. This is because the weights are not properly stored in the pixel memory nodes. This indicates that

[0341] Next, write the data that displays all white as the weight, and use the same all white data as the display data. As shown in Table 2, the brightness was improved. In this way, a voltage higher than the output voltage of the source driver is applied to the gate of transistor M2. It was confirmed that this allows for the application of a voltage to the LCD panel, thereby enabling the display of higher brightness.

[0342] [Table 2]

[0343] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments. is. [Example]

[0344] Example 1 In this example, an example in which an external correction circuit is provided in a display device according to one embodiment of the present invention will be described. do.

[0345] In display devices with EL elements, variations in the characteristics and deterioration of the driving transistors have a significant effect on the display. Therefore, it is necessary to provide a circuit to correct the current variations of the drive transistor. is preferred.

[0346] In this example, an EL display device having an external correction circuit with improved current readout accuracy was fabricated. The external correction circuit is used to connect the source driver to a differential or two-differential It is equipped with an integrating circuit that uses the input method.

[0347] Figure 26 shows an OS transistor (CAAC-IGZO) fabricated using the same process as the display device. FET, W / L=4μm / 6μm) D -VG Characteristics (Vds=0.1V, 10V) The transistor characteristics are normally off, and the off-current is below the lower limit of the measurement equipment. It was.

[0348] To improve the accuracy of the external compensation circuit, it is necessary to accurately measure the current of the drive transistor. However, if the external correction circuit is used, When affected by common mode noise, the accuracy of current measurement decreases. To cancel out the noise, for example, in the sensing circuit of a touch sensor, A dynamic input type integrator circuit is used.

[0349] Figures 27 and 28 are diagrams explaining the interface between the external correction circuit and the EL panel. The external correction circuit is composed of an integrating circuit, an ADC (A / D converter), and an image processing circuit. The integrator circuit and ADC are built into the source driver IC chip. The external correction circuit measures the current of the driving transistor of the pixel connected to the wiring MONI[N]. Before connecting the MONI[N-1], MONI[N], and MONI [N+1] etc. to V REF Set to.

[0350] The integrator circuit shown in Figure 27 has a differential input, while the integrator circuit shown in Figure 28 has two differential inputs. Both of these can cancel common mode noise. The transistor on the panel side is an OS transistor with extremely low off-state current, so It does not require a storage capacitor or power supply control, and maintains the reference potential during current measurement. It is possible to do this.

[0351] A pixel layout in which one power line is shared by two pixels (sub-pixels) as shown in Figure 29 is used. When using it, use the two-differential method shown in Figure 28 to accurately cancel noise. can be done.

[0352] FIG. 30 is a block diagram illustrating the configuration of a pixel and a source driver. The standard drive circuit is equipped with a memory to store voltage data that corrects for characteristic variations. The memory has an OS transistor and is connected to the OS memory. In this pixel, the current value of the driving transistor is read out from the wire Monitor and measured. The measured current value is used to correct the characteristic variations of the drive transistor. Create voltage data and weight (V w ) as image data (V data ) to This can reduce display unevenness caused by variations in transistor characteristics.

[0353] Next, we will explain how to drive pixels. w ) writing, image data (V da ta ) and the current are written in different periods. Mi(V w ) and image data (V data ) when writing, the Monitor wiring is set to a fixed potential. (V0) is input.

[0354] <Weight(V w )'s post> Weight (V w ) is a transistor included in the driving circuit of the EL element and a transistor included in the memory. Gate signals (G1, G2) that turn on the transistors, and reference voltage (V r ), fixed potential (V0) and write it to memory.

[0355] <Image data (V data )'s post> Display data (V data ) is a gate that turns on the transistor in the driving circuit of the EL element. At this time, the drive signal (G1) of the EL element is supplied to the drive circuit. The voltage V applied to the gate of the transistor g If the memory capacity is large enough, w - V r " to "V data " is added to the image data (V data ) to “ V w -V r " weights are added, so the voltage data that corrects for characteristic variations is Weight (V w ) to enable correction.

[0356] <Current readout> The current reading is performed by first reading the transistors in the driving circuit of the EL element and the The drive transistor is made conductive by supplying a constant gate signal to the transistor. When the current flows from the drive transistor to the wire Monitor, it is sourced via the selection circuit. It can be read out by a current monitor circuit in the driver IC chip.

[0357] <System wide> First, the pixel current is measured using a current monitor circuit. Then, correction data is calculated from the measured current value. The correction data is written to the OS memory in the pixel, and the image data is added. The memory only needs to be refreshed every few seconds, allowing external calculations to run at a lower frequency. Therefore, the data measured by the current monitor circuit is converted into corrected data through software processing. It can be converted and written to the OS memory in the pixel from the data driver unit once every few seconds. The data driver section includes, for example, an input section, a latch, a level shifter, a D / A converter, an amplifier, and a It can be configured with various circuits such as a pixel amplifier and is electrically connected to the pixel circuit via a selection circuit. The system is cost-effective because it requires slow computation and no dedicated peripheral circuits. This can reduce the amount of work required.

[0358] Figure 31 (A), (B), and (C) show the red light near the center of the screen of a separately manufactured high-definition panel. The current of the driving transistor was measured for the color display sub-pixel (160 x 360). The X and Y coordinates are the coordinates of the pixel where the current was measured, and the color intensity is the measured current as an AD The converted tone values are shown.

[0359] Figure 31(A) shows the results when a single-ended method is used for the input of the integrator circuit. The effect of noise in the direction of the differential line is strong. Figure 31(C) shows the results when using the two-differential method. The noise is cancelled, but when compared by Fourier transform, the two-differential method is It was confirmed that the formula can reduce noise by about 0.5%.

[0360] The specifications of the display device (EL panel) prototyped this time are the same as those in Table 1 shown in Example 1. The can driver is an OS transistor (CAAC-IGZO) mounted on the same substrate as the pixel circuit. The source driver implemented with COG has the external correction circuit mentioned above. The display element OLED is a tandem type that emits white light, and a color filter is used. This is a colorization method that combines these.

[0361] Figure 32(A) and (B) show the results of image correction using the new external correction system. Figure 32(A) shows a gray display when external correction is not performed. There is a large display unevenness. Black is written as the weight. Figure 32(B) shows the result without external correction. This is the gray display when the weight is set to 0. The display irregularities have disappeared and the display is uniform. The corrected image created from the current measurement results is written in the image.

[0362] Figure 33(A) and (B) show the luminance measured with a two-dimensional color luminance meter (Konica Minolta CA-2500). The results of measuring unevenness are shown in Figure 33(A) and Figure 33(B). This result shows that external correction can be used to achieve uniform brightness. We were able to confirm this.

[0363] Figure 34 shows the display images when displayed in LOW GRAY, GRAY, and WHITE. The results of measurements using a 2D colorimeter are compared with and without correction. The correction data was the same for both displays. With correction, the image was relatively bright regardless of the brightness. It can be seen that the display unevenness has been reduced.

[0364] Figures 35(A), (B), and (C) show examples of display applications that utilize memory within pixels. (V w ) and write the text data (Figure 35(A)) as the display data. When the image data of Jack (Fig. 35(B)) is written and displayed, it will look like Fig. 35(C). The two images are displayed overlapping each other. Even if the display data is changed, the weight (V w ) and it was confirmed that the characters written as weights (V w ) is retained.

[0365] As a result, in the external correction circuit of the prototype display device, the driving transistor of the EL element It was confirmed that the current can be measured with high accuracy. , and the voltage is weighted (V w ) stored in the pixel, which reduces the variation in the characteristics of the driving transistor. It was confirmed that it was possible to correct

[0366] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments. is. [Explanation of symbols]

[0367] 10 pixels 10a pixels 10b pixels 10c pixels 10d pixels 12 Low Driver 13 Column Driver 14 circuits 15 Column Driver 16 circuits 101 Transistor 102 transistor 103 Capacitor element 104 EL element 105 transistors 111 Transistor 112 transistors 113 Capacitor element 121 Wiring 122 Wiring 124 Wiring 125 Wiring 126 Wiring 128 Power line 129 Common Wiring 130 Wiring 141 Switch 142 Switch 143 Switch 144 Switch 215 Display section 221a Scanning line driving circuit 231a Signal line driver circuit 232a Signal line driver circuit 241a Common line driver circuit 723 Electrode 726 Insulation Layer 728 Insulation Layer 729 Insulation Layer 741 Insulation Layer 742 Semiconductor layer 744a electrode 744b electrode 746 Electrode 755 Impurities 771 Circuit Board 772 Insulation Layer 810 Transistor 811 Transistor 820 transistors 821 Transistor 825 transistors 826 Transistor 842 transistors 843 Transistor 844 transistors 845 transistors 846 transistors 847 Transistor 901 Case 902 Display section 903 Display section 904 Sensors 911 chassis 912 Display section 913 Speaker 919 Camera 921 Pillar 922 Display section 951 Case 952 Display section 953 Operation Button 954 External connection port 955 Speaker 956 Mike 957 Camera 961 Case 962 Shutter button 963 Mike 965 Display section 966 Operation Key 967 Speaker 968 Zoom Lever 969 Lens 971 Case 973 Display section 974 Operation Key 975 Speaker 976 Communication connection terminal 977 Optical Sensor 1000 DOSRAM 1001 memory cells 1002 Sense amplifier section 1003 Cell array section 4001 board 4005 Sealing material 4006 board 4010 transistor 4011 transistor 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Capacitor 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4041 Printed Circuit Board 4042 Integrated Circuits 4102 Insulation layer 4103 Insulation layer 4104 Insulation layer 4110 Insulation layer 4111 Insulation layer 4112 Insulation layer 4200 input device 4210 Touch Panel 4227 Electrode 4228 Electrode 4237 Wiring 4238 Wiring 4239 Wiring 4263 Circuit Board 4272b FPC 4273b IC 4510 Bulkhead 4511 Light-emitting layer 4513 Light-emitting element 4514 Filling material

Claims

[Claim 1] The pixel array includes pixels arranged in a matrix, a row driver, a column driver, and a circuit. the row driver and the column driver are electrically connected to the pixel array; the circuit is electrically connected to the column driver; The circuit has a function of generating correction data from image data input to the circuit and outputting the image data and the correction data to the column driver.

Images