Coding of residual and coefficient for video coding

Abstract

To provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding.SOLUTION: A decoder receives an enabling flag for a last significant coefficient of a sequence parameter set (SPS) indicating whether the enabling flag for an inverted coordinate of a last significant coefficient of a slice header (SH) is present in a slice header syntax structure referring to the SPS. In order to provide the same general constraint control as other flags, to general constraint information (GCI) syntax, the enabling flag for the inverted coordinate of the last significant coefficient of the GCI can be added.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Provisional Application No. 63 / 215,961, filed June 28, 2021, the entire contents of which are incorporated herein by reference for all purposes.

[0002] This disclosure relates to video coding and compression. More particularly, this disclosure relates to improving and simplifying residual and coefficient coding for video coding. [Background technology]

[0003]

[0003] Various video coding techniques may be used to compress video data. Video coding is performed according to one or more video coding standards. For example, video coding standards include Versatile Video Coding (VVC), Joint Search and Test Model (JEM), High Efficiency Video Coding (H.265 / HEVC), Advanced Video Coding (H.264 / AVC), Moving Picture Experts Group (MPEG) coding, etc. Video coding generally utilizes prediction methods (e.g., inter-prediction, intra-prediction, etc.) that exploit redundancy present in a video image or sequence. An important goal of video coding techniques is to compress video data into a format that uses a lower bitrate while avoiding or minimizing degradation of video quality. Summary of the Invention

[0004]

[0004] Examples of this disclosure provide methods and apparatus for video coding.

[0005] According to a first aspect of the present disclosure, there is provided a method for video decoding, the method including receiving, by a decoder, a slice header (SH) coefficient enable flag indicating whether an SPS coefficient enable flag is present in a slice header syntax structure that references a sequence parameter set (SPS).

[0006] According to a second aspect of the present disclosure, there is provided a method for video decoding, the method including receiving, by a decoder, a sequence parameter set (SPS) transform precision adaptation enable flag indicating whether a scaling process of transform coefficients and a downshift in a transformation process of scaled transform coefficients are adaptively assigned by examining coefficient values of inverse quantization and inverse transform.

[0007] According to a third aspect of the present disclosure, there is provided a method for video decoding, the method including: receiving, by a decoder, a sequence parameter set (SPS) high-throughput flag indicating whether syntax elements in residual coding are coded through a bypass mode; and determining, in response to determining that the value of the SPS high-throughput flag is equal to 1, by the decoder, that all syntax elements in the residual coding are coded through the bypass mode except for a last significant coefficient position in normal residual coding (RRC), and that alignment is performed after the last significant coefficient position in RRC and at the beginning of a transform block (TB) in transform-skip residual coding (TSRC).

[0008]

[0008] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to be restrictive of the present disclosure.

[0009]

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate examples consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram of an encoder according to an example of the present disclosure. [Figure 2]

[0011] FIG. 2 is a block diagram of a decoder according to an example of the present disclosure. [Figure 3A]

[0012] FIG. 10 illustrates block division in a multi-tree structure according to an example of the present disclosure. [Figure 3B]

[0013] FIG. 10 illustrates block division in a multi-tree structure according to an example of the present disclosure. [Figure 3C]

[0014] FIG. 10 illustrates block division in a multi-tree structure according to an example of the present disclosure. [Figure 3D]

[0015] FIG. 10 illustrates block division in a multi-tree structure according to an example of the present disclosure. [Figure 3E]

[0016] FIG. 10 illustrates block division in a multi-tree structure according to an example of the present disclosure. [Figure 4]

[0017] FIG. 1 illustrates a residual coding structure for a transform block according to an example of the present disclosure. [Figure 5]

[0018] FIG. 10 illustrates a residual coding structure for a transform skip block according to an example of the present disclosure. [Figure 6]

[0019] FIG. 1 is a diagram of a method for encoding a video signal according to an example of the present disclosure. [Figure 7]

[0020] FIG. 1 is a diagram of a method for encoding a video signal according to an example of the present disclosure. [Figure 8]

[0021] FIG. 1 illustrates a computing environment coupled with a user interface according to an example of the present disclosure. [Figure 9]

[0022] FIG. 1 illustrates a method for video coding according to an example of the present disclosure. [Figure 10]

[0023] FIG. 1 illustrates a method for video coding according to an example of the present disclosure. [Figure 11]

[0024] FIG. 1 illustrates a method for video coding according to an example of the present disclosure. [Figure 12]

[0025] FIG. 1 illustrates a method for video encoding according to an example of the present disclosure. [Figure 13]

[0026] FIG. 1 is a block diagram illustrating an exemplary system for encoding and decoding video blocks, according to one example of this disclosure. [Figure 14]

[0027] FIG. 2 is a block diagram illustrating an exemplary video encoder according to one example of this disclosure. [Figure 15]

[0028] FIG. 2 is a block diagram illustrating an exemplary video decoder according to one example of this disclosure. [Figure 16]

[0029] FIG. 1 illustrates a low-delay transform skip residual coding (TSRC) method according to an example of the present disclosure. [Figure 17]

[0030] FIG. 1 illustrates a method for video decoding according to an example of the present disclosure. [Figure 18]

[0031] FIG. 1 illustrates a method for video decoding according to an example of the present disclosure. [Figure 19]

[0032] FIG. 1 illustrates a method for video decoding according to an example of the present disclosure. [Figure 20]

[0033] FIG. 1 illustrates a method for video decoding according to an example of the present disclosure. [Figure 21]

[0034] FIG. 1 illustrates a method for video decoding according to an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0035] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise stated. The implementations described in the following description of exemplary embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects related to the present disclosure as set forth in the appended claims.

[0012]

[0036] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is also to be understood that the term "and / or," as used herein, means and is intended to mean and include any and all possible combinations of one or more of the associated listed items.

[0013]

[0037] Terms such as "first," "second," and "third" may be used herein to describe various pieces of information, but it should be understood that the information should not be limited by these terms. These terms are used only to distinguish one category of information from another. For example, first information could also be referred to as second information without departing from the scope of this disclosure. Similarly, second information could also be referred to as first information. The term "when" as used herein may be understood to mean "when," "in the event of," or "at the discretion of," depending on the context.

[0014]

[0038] Figure 1 shows a general diagram of a block-based video encoder for VVC. Specifically, Figure 1 shows a typical encoder 100. The encoder 100 includes a video input 110, a motion compensation unit 112, a motion estimation unit 114, an intra / inter mode decision unit 116, a block predictor 140, an adder 128, a transform unit 130, a quantization unit 132, prediction-related information 142, an intra prediction unit 118, a picture buffer 120, an inverse quantization unit 134, an inverse transform unit 136, an adder 126, a memory 124, an in-loop filter 122, an entropy coding unit 138, and a bitstream 144.

[0015]

[0039] In encoder 100, a video frame is divided into video blocks for processing. For a given video block, a prediction is formed based on either an inter-prediction approach or an intra-prediction approach.

[0016]

[0040] A prediction residual, which represents the difference between a current video block, which is part of the video input 110, and its predictor, which is part of the block predictor 140, is sent from the summer 128 to the transform unit 130. The transform coefficients are then sent from the transform unit 130 to the quantizer 132 for entropy reduction. The quantized coefficients are then provided to the entropy encoder 138 to generate a compressed video bitstream. As shown in FIG. 1 , prediction-related information 142 from the intra / inter mode decision unit 116, such as video block partition information, motion vectors (MVs), reference picture indices, and intra prediction modes, is also provided through the entropy encoder 138 and stored in the compressed bitstream 144. The compressed bitstream 144 comprises the video bitstream.

[0017]

[0041] Encoder 100 also requires decoder-related circuitry to reconstruct pixels for prediction purposes. A prediction residual is reconstructed through an inverse quantizer 134 and an inverse transformer 136. This reconstructed prediction residual is combined with a block predictor 140 to generate unfiltered reconstructed pixels for the current video block.

[0018]

[0042] Spatial prediction (or "intra prediction") predicts the current video block using pixels from samples (called reference samples) of already coded neighboring blocks in the same video frame as the current video block.

[0019]

[0043] Temporal prediction (also called "inter-prediction") uses pixels reconstructed from an already coded video picture to predict the current video block. Temporal prediction reduces the temporal redundancy inherent in a video signal. The temporal prediction signal for a particular coding unit (CU) or coding block typically indicates the amount and direction of motion between the current CU and its temporal reference. Furthermore, if multiple reference pictures are supported, one reference picture index is additionally transmitted, which is used to identify which reference picture in the reference picture storage the temporal prediction signal comes from.

[0020]

[0044] The motion estimation unit 114 receives signals from the video input 110 and the picture buffer 120, and outputs a motion estimation signal to the motion compensation unit 112. The motion compensation unit 112 receives signals from the video input 110, the picture buffer 120, and the motion estimation signal from the motion estimation unit 114, and outputs a motion compensation signal to the intra / inter mode decision unit 116.

[0021]

[0045] After spatial and / or temporal prediction is performed, an intra / inter mode decision unit 116 within encoder 100 selects the best prediction mode based, for example, on a nominal distortion optimization method. Block predictor 140 is then subtracted from the current video block, and the resulting prediction residual is decorrelated using transform unit 130 and quantizer 132. The resulting quantized residual coefficients are inverse quantized by inverse quantizer 134 and inverse transformed by inverse transform unit 136 to form a reconstructed residual, which is then added back to the prediction block to form a reconstructed signal for the CU. Further in-loop filtering 122, such as a deblocking filter, sample adaptive offset (SAO), and / or adaptive in-loop filter (ALF), can be applied to the reconstructed CU before it is placed into reference picture storage in picture buffer 120 and used to encode future video blocks. To form the output video bitstream 144, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit 138, which further compresses and packs them to form the bitstream.

[0022]

[0046] Figure 1 shows a block diagram of a typical block-based hybrid video coding system. The input video signal is processed in blocks (called coding units (CUs)). In VTM-1.0, a CU can be up to 128 x 128 pixels in size. However, unlike HEVC, which partitions blocks solely based on a quaternary tree, VVC partitions a single coding tree unit (CTU) into CUs based on quaternary, binary, and ternary trees to accommodate various local characteristics. By definition, a coding tree block (CTB) is an N x N block of samples for some value of N, where the partitioning of components into CTBs constitutes a partition. A CTU contains a CTB for luma samples, two corresponding CTBs for chroma samples in a picture with a three-sample array, or a CTB for samples in a picture coded using three separate color planes and a syntax structure used for monochrome pictures or sample coding. Furthermore, the concept of multiple partition unit types in HEVC is eliminated. That is, the separation of CUs, prediction units (PUs), and transform units (TUs) no longer exists in VVC. Instead, each CU is always used as the basic unit for both prediction and transformation without further division. In the multi-tree structure, one CTU is first divided into quaternary tree structures. Then, each quaternary tree leaf node can be further divided into binary tree and ternary tree structures. As shown in Figures 3A, 3B, 3C, 3D, and 3E, there are five division types: 4-way division, horizontal 2-way division, vertical 2-way division, horizontal 3-way division, and vertical 3-way division.

[0023]

[0047] FIG. 3A shows a diagram illustrating a quadrant of a block in a multi-tree structure according to the present disclosure.

[0024]

[0048] FIG. 3B shows a diagram illustrating block vertical bisection in a multi-tree structure according to the present disclosure.

[0025]

[0049] FIG. 3C shows a diagram illustrating horizontal bisection of blocks in a multi-tree structure according to the present disclosure.

[0026]

[0050] FIG. 3D shows a diagram illustrating a vertical 3-division of blocks in a multi-tree structure according to the present disclosure.

[0027]

[0051] FIG. 3E shows a diagram illustrating a horizontal 3-partitioning of blocks in a multi-tree structure according to the present disclosure.

[0028]

[0052] In FIG. 1, spatial prediction and / or temporal prediction can be performed. Spatial prediction (or "intra prediction") predicts the current video block using pixels from samples (called reference samples) of previously coded neighboring blocks in the same video picture / slice. Spatial prediction mitigates spatial redundancy inherent in video signals. Temporal prediction (also called "inter prediction" or "motion-compensated prediction") predicts the current video block using pixels reconstructed from previously coded video pictures. Temporal prediction mitigates temporal redundancy inherent in video signals. The temporal prediction signal for a particular CU is typically conveyed by one or more motion vectors (MVs), which indicate the amount and direction of motion between the current CU and its temporal reference. If multiple reference pictures are supported, an additional reference picture index is transmitted, which is used to identify which reference picture in the reference picture store the temporal prediction signal comes from. After spatial and / or temporal prediction, a mode decision block in the encoder selects the optimal prediction mode, for example, based on a nominal distortion optimization method. The predicted block is then subtracted from the current video block. The prediction residual is decorrelated and quantized using a transform. The quantized residual coefficients are inverse quantized and inverse transformed to form a reconstructed residual, which is then added back to the prediction block to form the reconstructed signal for the CU. Further in-loop filtering, such as a deblocking filter, sample adaptive offset (SAO), and adaptive in-loop filtering (ALF), can be applied to the reconstructed CU before it is placed in the reference picture store and used to encode future video blocks. To form the output video bitstream, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to an entropy coding unit for further compression and packing to form the bitstream.

[0029]

[0053] 2 shows a general block diagram of a video decoder for VVC. Specifically, FIG. 2 shows a block diagram of an exemplary decoder 200. The decoder 200 includes a bitstream 210, an entropy decoding unit 212, an inverse quantization unit 214, an inverse transform unit 216, an adder 218, an intra / inter mode selection unit 220, an intra prediction unit 222, a memory 230, an in-loop filter 228, a motion compensation unit 224, a picture buffer 226, prediction-related information 234, and a video output 232.

[0030]

[0054] The decoder 200 is similar to the reconstruction-related section present in the encoder 100 of FIG. 1. In the decoder 200, an input video bitstream 210 is first decoded through an entropy decoding unit 212 to derive quantized coefficient levels and prediction-related information. The quantized coefficient levels are then processed through an inverse quantization unit 214 and an inverse transform unit 216 to obtain a reconstructed prediction residual. The block prediction mechanism implemented in the intra / inter mode selector 220 is configured to perform either an intra prediction unit 222 or a motion compensation unit 224 based on the decoded prediction information. A set of unfiltered reconstructed pixels is obtained by summing the reconstructed prediction residual from the inverse transform unit 216 and the prediction output generated by the block prediction mechanism using an adder 218.

[0031]

[0055] The reconstructed blocks are stored in a picture buffer that acts as a reference picture store. 226. The reconstructed video in picture buffer 226 may be further passed through an in-loop filter 228. The reconstructed video in picture buffer 226 may not only be transmitted to drive a display device, but may also be used to predict future video blocks. In situations where in-loop filter 228 is turned on, a filtering operation is performed on these reconstructed pixels to derive the final reconstructed video output 232.

[0032]

[0056] Figure 2 shows a general block diagram of a block-based video decoder. The video bitstream is first entropy decoded in an entropy decoding unit. The coding mode and prediction information are sent to a spatial prediction unit (for intra-coding) or a temporal prediction unit (for inter-coding) to form a prediction block. The residual transform coefficients are sent to an inverse quantization unit and an inverse transform unit to reconstruct a residual block. The prediction block and the residual block are then added together. The reconstructed block may undergo further in-loop filtering before being stored in a reference picture store. The reconstructed video in the reference picture store is used to predict future video blocks as well as to drive a display device.

[0033]

[0057] Transform coefficient coding in VVC.

[0034]

[0058] In transform coefficient coding in VVC, the variable remBinsPassl is initially set to the maximum number of allowed context coding bins (MCCBs). During the coding process, the variable is decremented by one each time a context coding bin is transmitted. While remBinsPassl is 4 or greater, coefficients are first transmitted through the sig_coeff_flag, abs_level_gtl_flag, par_level_flag, and abs_level_gt3_flag syntax elements, all using context coding bins in the first pass. The remaining level information for the coefficients is coded using Golomb-Rice coding and bypass coding bins in the second pass with the abs_remainder syntax element. If remBinsPass1 becomes less than 4 during first-pass coding, the current coefficient is not coded in the first pass but is directly coded in the second pass with the dec_abs_level syntax element using Golomb-Rice coding and bypass coding bins. Rice parameters for dec_abs_level[ ] The derivation process is as specified in Table 1A. After all the above level coding, the codes (sign flags) of all scan positions where sig_coeff_flag is equal to 1 are finally coded as bypass bins. This process is shown in Figure 4. remBinsPass1 is reset for each TB. The transition from using context coding bins for sig_coeff_flag, abs_level_gtl_flag, par_level_flag, and abs_level_gt3_flag to using bypass coding bins for the remaining coefficients occurs at most once per TB. For a coefficient sub-block, if remBinsPass1 is less than 4 before coding the first coefficient, the entire coefficient sub-block is coded using bypass coding bins.

[0035]

[0059] FIG. 4 shows the residual coding structure of a transform block.

[0036] [Table 1]

[0037] [Table 2]

[0038]

[0060] Transform skip mode residual coding in VVC.

[0039]

[0061] In transform skip mode, the statistical properties of the residual signal differ from those of the transform coefficients, and no energy compaction around low-frequency components is observed. The residual coding is modified to take into account the different signal properties of the (spatial) transform skip residual.

[0040]

[0062] FIG. 5 shows the residual coding structure of a transform skip block.

[0041]

[0063] General Constraint Information

[0042]

[0064] The GCI structure contains several types of constraint syntax elements, including flags for general bitstream restrictions, such as indicating that only intra-coding is used, that all layers are coded independently, or that the bitstream contains only one AU; fields that constrain the bit depth and chroma format of coded pictures; flags that indicate that certain NAL unit types cannot be present in the bitstream; flags that constrain how pictures can be partitioned in the bitstream into slices, tiles, and subpictures; flags that restrict the size of CTUs and the size and type of partition trees; flags that restrict the use of certain intra-coding tools; flags that restrict the use of certain inter-coding tools; flags that constrain transform, quantization, and residual coding tools; and flags that constrain aspects of in-loop filters.

[0043]

[0065] The purpose of the GCI syntax structure is to allow easy discovery of configuration information about features required for decoding a bitstream, to impose restrictions beyond those specified in a profile, tier, and level (PTL), and to enable signaling of interoperability points that impose restrictions at a finer granularity than allowed by previous video coding standards. Similar to subprofiles, the GCI syntax structure allows interoperability to be defined for decoder implementations that do not support all the features of a VVC profile but address the needs of a specific application. A decoder implementation may inspect the GCI syntax elements to determine whether a bitstream avoids the use of certain features to determine how to configure the decoding process and to identify whether the bitstream is decodable by the decoder. A decoder implementation that supports all the features of a VVC profile can ignore the values of the GCI syntax elements, since such a decoder can decode any bitstream that conforms to the specified PTL.

[0044]

[0066] Residual coding for transform skipping

[0045]

[0067] According to one or more examples of the present disclosure, in order to encode a particular syntax element, a variable set of binary codewords, e.g., abs_remainder, is proposed to be used in transform skip residual coding. The selection is made according to specific coding information of the current block, e.g., quantization parameters or coding bit depth associated with TB / CB and / or slice / profile, and / or according to a new flag associated with TB / CB / slice / picture / sequence level, e.g., extended_precision_processing_flag. Various methods can be used to derive a variable set of binary codewords. Some exemplary methods are shown below.

[0046]

[0068] First, the same procedure as that used in the current VVC for determining the codeword of abs_remainder is used, but a fixed Rice parameter (e.g., 2, 3, 4, 5, 6, 7, or 8) is always selected. The fixed value may vary under different conditions according to specific coding information of the current block, e.g., quantization parameter, frame type (e.g., I, P, or B), component ID (e.g., luminance or chrominance), color format (e.g., 420, 422, or 444), or coding bit depth associated with TB / CB and / or slice / profile, and / or according to a syntax element associated with TB / CB / slice / picture / sequence level, e.g., rice_parameter value. A specific example is the case where TH1 to TH4 are predetermined thresholds satisfying (TH1 < TH2 < TH3 < TH4), and K0 to K4 are predetermined Rice parameters. In fact, it is worth noting that the same logic can be implemented in different ways. For example, the same Rice parameter can also be derived from the BitDepth value of the current CU / sequence using a specific equation or look-up table.

[0047]

[0069] Second, fixed-length binarization.

[0048]

[0070] Third, truncated Rice binarization.

[0049]

[0071] Fourth, the truncated binary (TB) binarization process.

[0050]

[0072] Fifth, the kth-order Exp-Golomb binarization process (EGk).

[0051]

[0073] Sixth, limited k-th order Exp-Golomb binarization

[0052]

[0074] An example of the corresponding decoding process based on the VVC draft is shown below. Changes to the VVC draft are shown in bold italics in Table 1, and removed content is shown in italics. Note that in practice, the same logic may be implemented in different ways. For example, the same Rice parameters may be derived using a specific equation or lookup table.

[0053] [Table 3]

[0054]

[0075] In another example, when a new flag, e.g., extended_precision_processing_flag, is equal to 1, it is proposed to use only one fixed value for the Rice parameter when encoding the abs_remainder syntax element. The corresponding decoding process based on the WC draft is shown below. Changes are in bold italics, and deleted content is in italics. Changes to the VVC draft are shown in bold italics in Table 2.

[0055] [Table 4]

[0056]

[0076] In yet another example, if a new flag, e.g., extended_precision_processing_flag, is equal to 1, the rice parameter cRiceParam is fixed to n, where n is a positive number (e.g., 2, 3, 4, 5, 6, 7, or 8). The fixed value may be different depending on conditions. An example of the corresponding decoding process based on the VVC draft is shown below. Changes are in bold italics, and deleted content is in italics. Changes to the VVC draft are shown in bold italics in Table 3.

[0057] [Table 5]

[0058]

[0077] In yet another example, if BitDepth is greater than or equal to a predetermined threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), the Rice parameter cRiceParam is fixed to n, where n is a positive number, e.g., 4, 5, 6, 7, or 8. The fixed value may vary depending on conditions. An example of the corresponding decoding process based on the VVC draft is shown below, where TH is a preset threshold (e.g., 10, 11, 12, 13, 14, 15, or 16), changes are shown in bold italics, and removed content is shown in italics. The changes to the VVC draft are shown in bold italics in Table 4.

[0059] [Table 6]

[0060]

[0078] In yet another example, one control flag is transmitted in the slice header to indicate whether transmission of the Rice parameter for the transform skip block is enabled or disabled. When the control flag is transmitted as enabled, one syntax element is further transmitted for each transform skip slice to indicate the Rice parameter for that slice. When the control flag is transmitted as disabled (e.g., set to "0"), no further syntax elements are transmitted at lower levels to indicate the Rice parameter for the transform skip slice, and a default Rice parameter (e.g., 1) is used for all transform skip slices. An example of a corresponding decoding process based on the VVC draft is shown below. Here, TH is a predetermined value (e.g., 0, 1, 2), changes are indicated in bold and italic font, and deleted content is indicated in italic font. Changes to the VVC draft are shown in bold and italic font in Table 5. It is worth noting that sh_ts_residual_coding_rice_index can be coded in various ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to encode / decode the same syntax element.

[0061]

[0079] Slice Header Syntax [Table 7]

[0062]

[0080] sh_ts_residual_coding_rice_flag equal to 1 specifies that sh_ts_residual_coding_rice_index may be present in the current slice. sh_ts_residual_coding_rice_flag equal to 0 specifies that sh_ts_residual_coding_rice_index is not present in the current slice. If sh_ts_residual_coding_rice_flag is not present, the value of sh_ts_residual_coding_rice_flag is inferred to be equal to 0. sh_ts_residual_coding_rice_index specifies the rice parameter used in the residual_ts_coding() syntax structure.

[0063] [Table 8]

[0064]

[0081] In yet another example, one control flag is transmitted within the sequence parameter set (or sequence parameter set range extension syntax) to indicate whether transmission of Rice parameters for transform skip blocks is enabled or disabled. When the control flag is transmitted as enabled, one syntax element is further transmitted for each transform skip slice to indicate the Rice parameter for that slice. When the control flag is transmitted as disabled (e.g., set to “0”), no further syntax elements are transmitted at lower levels to indicate Rice parameters for transform skip slices, and a default Rice parameter (e.g., 1) is used for all transform skip slices. An example of a corresponding decoding process based on the VVC draft is shown below, where TH is a predetermined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 7, and deleted content is shown in italic font. It is worth noting that sh_ts_residual_coding_rice_idx can be coded in various ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to encode / decode the same syntax element.

[0065]

[0082] Sequence Parameter Set RBSP Syntax [Table 9]

[0066]

[0083] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in SH syntax structures that reference an SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx is not present in SH syntax structures that reference an SPS. If sps_ts_residual_coding_rice_present_in_sh_flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0067]

[0084] Slice Header Syntax [Table 10]

[0068]

[0085] sh_ts_residual_coding_rice_idx specifies the rice parameter used in the residual_ts_coding() syntax structure.

[0069] [Table 11]

[0070]

[0086] In one or more examples of the present disclosure, it is proposed to disable the presence of the Rice parameter for transform skip residual coding when transform skip is disabled. In one particular example, to meet such design objective, it is proposed to use sps_transform_skip_enabled_flag to condition the presence of sps_ts_residual_coding_rice_present_in_sh_flag. For example, when the flag sps_transform_skip_enabled_flag is equal to 0 (i.e., transform skip is disabled in the current picture), sps_ts_residual_coding_rice_present_in_sh_flag is not signaled and is inferred to be 0. When the flag sps_transform_skip_enabled_flag is equal to 1, sps_ts_residual_coding_rice_present_in_sh_flag is further signaled. Changes to the current VVC working draft are indicated in italics below.

[0071] [Table 12]

[0072]

[0087] In another specific example, to meet such design objectives, it is proposed to add a bitstream conformance requirement relating to the sps_transform_skip_enabled_flag to the sps_ts_residual_coding_rice_present_in_sh flag. For example, it is a bitstream conformance requirement that if sps_transform_skip_enabled_flag is equal to 0, then the value of sps_ts_residual_coding_rice_present_in_sh_flag must be equal to 0. Changes to the current VVC working draft are shown in italics below.

[0073]

[0088] Sequence parameter set range extension semantics

[0074]

[0089] sps_ts_residual_coding_rice_present_in_sh_flag equal to 1 specifies that sh_ts_residual_coding_rice_idx_minus1 may be present in the slice_header() syntax structure referencing the SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx_minus1 is not present in the slice_header() syntax structure referencing the SPS. If sps_ts_residual_coding_rice_present_in_sh_flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0075]

[0090] It is a bitstream conformance requirement that if sps_transform_skip_enabled_flag is equal to 0, the value of sps_ts_residual_coding_rice_present_in_sh_flag must be equal to 0.

[0076]

[0091] In yet another example, when the flag for transform skip (sps_transform_skip_enabled_flag) is signaled as enabled, one control flag is further signaled in the sequence parameter set (or sequence parameter set range extension syntax) to indicate whether signaling of Rice parameters for transform skip blocks is enabled or disabled. When the control flag is signaled as enabled, one syntax element is further signaled for each transform skip slice to indicate the Rice parameters for that slice. When the control flag is signaled as disabled (e.g., set equal to "0"), no further syntax elements are signaled at lower levels to indicate Rice parameters for transform skip slices, and default Rice parameters (e.g., 1) are used for all transform skip slices. An example of a corresponding decoding process based on the VVC draft is shown below. Changes to the VVC draft are italicized.

[0077]

[0092] Sequence Parameter Set RBSP Syntax [Table 13]

[0078]

[0093] sps_ts_residual_coding_rice_present_in_sh flag equal to 1 specifies that sh_ts_residual_coding_rice_idx may be present in SH syntax structures that reference an SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx_minus1 is not present in SH syntax structures that reference an SPS. If the sps_ts_residual_coding_rice_present_in_sh flag is not present, the value of sps_ts_residual_coding_rice_present_in_sh_flag is inferred to be equal to 0.

[0079]

[0094] Slice Header Syntax [Table 14]

[0080]

[0095] sh_ts_residual_coding_rice_idx_minus1 plus 1 specifies the rice parameter used in the residual_ts_coding() syntax structure. If sh_ts_residual_coding_rice_idx_minus1 is not present, the value of sh_ts_residual_coding_rice_idx_minus1 is inferred to be equal to 0.

[0081]

[0096] 9.3.3.11 abs_remainder[ ] thresholding process

[0082]

[0097] The input to this process is the syntax element abs_remainder[n] , color component cIdx, current sub-block index i, and luminance position (xO, yO) specifying the top-left sample of the current luminance transformation block relative to the top-left luminance sample of the picture, current coefficient scan position (xC, yC), binary logarithm of the transformation block width log2Tbwidth, and binary logarithm of the transformation block height log2TbHeight.

[0083]

[0098] The output of this process is a binarization of the syntax elements.

[0084]

[0099] The variables lastAbsRemainder and lastRiceParam are derived as follows:

[0085]

[0100] - This is the first time this process is called for the current subblock index i. If issued, lastAbsRemainder and lastRiceParam are both set equal to 0.

[0086]

[0101] - Otherwise (this process is done for the current subblock index i) If this clause is not called for the first time for a given syntax element (abs_remainder[n] or cRiceParam), then lastAbsRemainder and lastRiceParam are set equal to the values of abs_remainder[n] and cRiceParam, respectively, that were derived during the last invocation of the binarization process for the syntax element abs_remainder[n] specified in this clause.

[0087]

[0102] The rice parameter cRiceParam is derived as follows:

[0088]

[0103] - transform_skip_flag[x0][y0][cIdx ] is equal to 1 and the sh_ts_residual_coding disable flag is equal to 0, then the rice parameter cRiceParam is set equal to sh_ts_residual_coding_rice_idx_minus1+1.

[0089]

[0104] - Otherwise, the rice parameter cRiceParam is set to 9.3. As specified in Section 3.2, the rice parameter of abs_remainder[ ] It is derived by invoking the data derivation process, setting the variable baseLevel equal to 4, and using as input the color component index cIdx, the luma position (x0, y0), the current coefficient scan position (xC, yC), the binary logarithm of the transform block width log2Tbwidth, and the binary logarithm of the transform block height log2TbHeight.

[0090]

[0105] In yet another example, one syntax element for each transform skip slice: is signaled to indicate the Rice parameters for that slice. An example of the corresponding decoding process based on the VVC draft is shown below. Changes to the VVC draft are shown in bold italics in Table 10. Note that sh_ts_residual_coding_rice_idx can be coded in different ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to encode / decode the same syntax element.

[0091]

[0106] Slice Header Syntax [Table 15]

[0092]

[0107] sh_ts_residual_coding_rice_idx is res Specifies the rice parameter used for the residual_ts_coding() syntax structure. If sh_ts_residual_coding_rice_idx is not present, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

[0093] [Table 16]

[0094]

[0108] In yet another example, whether transmission of Rice parameters in transform skip blocks is valid or not. A control flag is transmitted in the picture parameter set range extension syntax to indicate whether the picture parameter set range is disabled. If the control flag is transmitted as enabled, the picture parameter set range is disabled. One additional syntax element is transmitted to indicate the Rice parameter. When the control flag is transmitted as disabled (e.g., set to "0"), no further syntax elements are transmitted at lower levels to indicate the Rice parameter for the transform skip slice, and the default Rice parameter (e.g., 1) is used for all transform skip slices. An example of the corresponding decoding process based on the VVC draft is shown below. Here, TH is a pre-defined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 12. It is worth noting that pps_ts_residual_coding_rice_idx can be coded in various ways and / or may have a maximum value. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to encode / decode the same syntax element.

[0095]

[0109] Picture Parameter Set Range Extension Syntax

[0096] [Table 17]

[0097]

[0110] pps_ts_residual_coding_rice_fl equal to 1 ag specifies that pps_ts_residual_coding_rice_index may be present in the current picture. pps_ts_residual_coding_rice_flag equal to 0 specifies that pps_ts_residual_coding_rice_idx is not present in the current picture. If pps_ts_residual_coding_rice_flag is not present, the value of pps_ts_residual_coding_rice_flag is inferred to be equal to 0.

[0098]

[0111] pps_ts_residual_coding_rice_idx is re Specifies the Rice parameters used in the sidual_ts_coding() syntax construct.

[0099] [Table 18]

[0100]

[0112] As another example, the syntax element abs_remainder is encoded as It is proposed to use only variable Rice parameters. The value of the applied Rice parameter may be determined according to the specific coding information of the current block, such as the block size, quantization parameter, bit depth, transform type, etc. In one specific embodiment, it is proposed to adjust the Rice parameter based on the coding bit depth and the quantization parameter applied to one CU. The corresponding decoding process based on the VVC draft is shown below. Changes to the VVC draft are shown in bold and italic font in Table 14, and deleted content is shown in italic font. It is worth noting that in practice, the same logic can be implemented in different ways. For example, the same Rice parameter can be derived using a specific equation or lookup table.

[0101] [Table 19-1] [Table 19-2]

[0102]

[0113] In yet another example, the corresponding decoding process based on the VVC draft is as follows: where TH is a predetermined threshold (e.g., 33 or 34). Changes to the VVC draft are shown in bold and italic font in Table 15, and deleted content is shown in italic font. Note that in practice, the same logic may be implemented in different ways. For example, the same Rice parameters may be derived using a specific equation or lookup table.

[0103] [Table 20]

[0104]

[0114] In yet another example, the corresponding decoding process based on the VVC draft is as follows: As shown, TH A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B = 33 or 34). Changes to the VVC draft are shown in bold and italic font in Table 16, while deleted content is shown in italic font. It is worth noting that in practice, the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using a specific equation or lookup table.

[0105] [Table 21]

[0106]

[0115] In yet another example, new flags, such as extended_precision When on_processing_flag is equal to 1, it is proposed to use only variable Rice parameters for encoding the abs_remainder syntax element. The varying value may be determined according to the specific encoding information of the current block, such as the block size, quantization parameter, bit depth, transform type, etc. In one specific embodiment, it is proposed to adjust the Rice parameters based on the encoding bit depth and the quantization parameter applied to one CU. The corresponding decoding process based on the VVC draft is shown below. The changes to the VVC draft are shown in bold and italic font in Table 17. It is worth noting that in practice, the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using a specific equation or lookup table.

[0107] [Table 22]

[0108]

[0116] In yet another example, the corresponding decoding process based on the VVC draft is as follows: where TH is a predetermined threshold (e.g., 18, 19). Changes to the VVC draft are shown in bold and italic font in Table 18. In practice, the same It is worth noting that the same logic can be implemented in different ways, for example, using a specific equation or lookup table to derive the same Rice parameters.

[0109] [Table 23]

[0110]

[0117] In yet another example, the corresponding decoding process based on the VVC draft is as follows: As shown, TH A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B= 18 or 19). Changes to the VVC draft are shown in bold and italic font in Table 19. It is worth noting that in practice the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using specific equations or lookup tables.

[0111] [Table 24]

[0112]

[0118] Figure 6 shows a video coding method, which is applied to, for example, an encoder. At step 1610, the encoder may receive a video input. For example, the video input may be a live stream. At step 1612, the encoder may obtain a quantization parameter based on the video input. The quantization parameter may be calculated, for example, by a quantization unit within the encoder. At step 1614, the encoder may derive a Rice parameter based on at least one predetermined threshold, the coding bit depth, and the quantization parameter. For example, the Rice parameter is used to transmit the abs_remainder and dec_abs_level syntaxes. At step 1616, the encoder may entropy encode the video bitstream based on the Rice parameter. For example, the video bitstream may be entropy encoded to generate a compressed video bitstream.

[0113]

[0119] In yet another example, if BitDepth is greater than 10, abs_rem It is proposed to use only fixed values (e.g., 2, 3, 4, 5, 6, 7, or 8) for the Rice parameter when encoding the ⎯ ...

[0114] [Table 25]

[0115]

[0120] In yet another example, the corresponding decoding process based on the VVC draft is as follows: As shown, TH A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B = 18 or 19). Changes to the VVC draft are shown in bold and italic font in Table 21. It is worth noting that in practice the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using specific equations or lookup tables.

[0116] [Table 26]

[0117]

[0121] In yet another example, the corresponding decoding process based on the VVC draft is as follows: where TH is a predetermined threshold (e.g., 33 or 34). Changes to the VVC draft are shown in bold and italic font in Table 22. It is worth noting that in practice, the same logic can be implemented in different ways. For example, the same Rice parameters could be derived using a specific equation or lookup table.

[0118] [Table 27]

[0119]

[0122] In yet another example, the corresponding decoding process based on the VVC draft is as follows: As shown, TH A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B = 33 or 34). Changes to the VVC draft are shown in bold and italic font in Table 23. It is worth noting that in practice the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using specific equations or lookup tables.

[0120] [Table 28]

[0121]

[0123] In the diagram above, the equation used to calculate a particular Rice parameter is It is worth mentioning that the above mapping function (or equivalent mapping equation) is used only as an example to explain the proposed idea. For those skilled in the art of modern video coding technology, other mapping functions (or equivalent mapping equations) can already be applied to the proposed idea (i.e., determining the Rice parameter for the transform skip mode based on the coded bits and the applied quantization parameter). Meanwhile, it should also be mentioned that in the current VVC design, the value of the applied quantization parameter can be changed at the coded block group level. Therefore, the proposed Rice parameter adjustment scheme can provide flexible adaptation of the Rice parameter for the transform skip mode at the coded block group level.

[0122]

[0124] Transmission information for regular residual coding and transform-skip residual coding Information

[0123]

[0125] According to one or more examples of this disclosure, in regular residual coding, It is proposed to transmit the Rice parameters of a binary codeword to encode certain syntax elements, e.g., abs_remainder for transform skip residual coding, shift and offset parameters for deriving the Rice parameters used for abs_remainder / dec_abs_level, and to decide whether to transmit them according to specific coding information of the current block, e.g., quantization parameters or coding bit depth associated with TB / CB and / or slice / profile, and / or according to a new flag associated with TB / CB / slice / picture / sequence level, e.g., sps_residual_coding_info_present_in_sh_flag.

[0124]

[0126] In one example, one control flag is the Rice parameter of the transform skip block. The control flag is transmitted in the slice header to indicate whether the transmission of the Rice parameter for the transform block and the shift and / or offset parameters for deriving the Rice parameter for the transform block are enabled or disabled. When the control flag is transmitted as enabled, one syntax element is further transmitted for each transform skip slice to indicate the Rice parameter for that slice, and two syntax elements are further transmitted for each transform slice to indicate the shift and / or offset parameters for deriving the Rice parameter for that slice. When the control flag is transmitted as disabled (e.g., set to "0"), no further syntax elements are transmitted at lower levels to indicate the Rice parameter for the transform skip slice, and a default Rice parameter (e.g., 1) is used for all transform skip slices; no further syntax elements are signaled at lower levels to indicate the shift and offset parameters for deriving the Rice parameter for the transform slice, and a default shift and / or offset parameter (e.g., 0) is used for all transform slices. An example of a corresponding decoding process based on the VVC draft is shown below. Here, TH is a predetermined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 24. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_index can be coded differently and / or have maximum values. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used and will encode / decode the same syntax element.

[0125]

[0127] Figure 7 shows a method for video decoding, which can be applied to, for example, an encoder. At step 1710, the encoder may receive a video input. At step 1712, the encoder may transmit Rice parameters of a binary codeword for encoding a syntax element. The encoding syntax element may include abs_remainder for transform skip residual coding. At step 1714, the encoder may entropy encode a video bitstream based on the Rice parameters and the video input.

[0126]

[0128] Slice Header Syntax [Table 29]

[0127]

[0129] sh_residual_coding_rice_flag equal to 1 means Specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index may be present in the current slice, and sh_residual_coding_rice_flag equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_residual_coding_rice_index are not present in the current slice.

[0128]

[0130] sh_residual_coding_rice_shift is abs_ Specifies the shift parameter used in the Rice parameter derivation process for readinder[ ] and dec_abs_level[ ]. If sh_residual_coding_rice_shift is not present, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0129]

[0131] sh_residual_coding_rice_offset is abs Specifies the offset parameter used in the Rice parameter derivation process for _remainder[ ] and dec_abs_level[ ]. If sh_residual_coding_rice_offset is not present, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0130]

[0132] sh_ts_residual_coding_rice_index is r Rice parameters used in the esidual_ts_coding() syntax structure. If sh_ts_residual_coding_rice_index is not present, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0131] [Table 30]

[0132] [Table 31-1] [Table 31-2]

[0133] In another example, one control flag may be used to set the sequence parameter set (or sequence parameter set). The control flag is transmitted in the Transform Parameter Set Range Extension Syntax (see section 1.1.1.1) to indicate whether transmission of Rice parameters for transform skip blocks and transmission of shift parameters and / or offset parameters for deriving Rice parameters within transform blocks are enabled or disabled. When the control flag is transmitted as enabled, one syntax element is further transmitted for each transform skip slice to indicate the Rice parameters for that slice, and two syntax elements are further transmitted for each transform slice to indicate the shift parameters and / or offset parameters for deriving the Rice parameters for that slice. When the control flag is transmitted as disabled (e.g., set to “0”), no further syntax elements are transmitted at lower levels to indicate Rice parameters for transform skip slices, and default Rice parameters (e.g., 1) are used for all transform skip slices; no further syntax elements are signaled at lower levels to indicate shift parameters and / or offset parameters for deriving Rice parameters for transform slices, and default shift parameters and / or offset parameters (e.g., 0) are used for all transform slices. An example of a corresponding decoding process based on the VVC draft is shown below. where TH is a predetermined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 27. It is worth noting that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx can be coded differently and / or have maximum values. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to code / decode the same syntax elements.

[0134]

[0134] Sequence Parameter Set RBSP Syntax [Table 32]

[0135] sps_residual_coding_info_prese equal to 1 nt_in_sh_flag specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx may be present in SH syntax structures that reference an SPS. sps_residual_coding_info_present_in_sh_flag equal to 0 specifies that sh_residual_coding_rice_shift, sh_residual_coding_rice_offset, and sh_ts_residual_coding_rice_idx are not present in SH syntax structures that reference an SPS. If sps_residual_coding_info_present_in_sh_flag is not present, the value of sps_residual_coding_info_present_in_sh_flag is inferred to be equal to 0.

[0136] Slice Header Syntax [Table 33]

[0137]

[0137] sh_residual_coding_rice_shift is abs_ Specifies the shift parameter used in the Rice parameter derivation process for remainder[ ] and dec_abs_level[ ]. If sh_residual_coding_rice_shift is not present, the value of sh_residual_coding_rice_shift is inferred to be equal to 0.

[0138]

[0138] sh_residual_coding_rice_offset is abs Specifies the offset parameter used in the Rice parameter derivation process for _remainder[ ] and dec_abs_level[ ]. If sh_residual_coding_rice_offset is not present, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0139]

[0139] sh_ts_residual_coding_rice_idx is res Specifies the rice parameter used in the residual_ts_coding() syntax construct. If sh_ts_residual_coding_rice_index is not present, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0140] [Table 34]

[0141] [Table 35-1] [Table 35-2]

[0142]

[0140] In yet another example, one syntax element is provided for each transform skip slice. sh_ts_residual_coding_rice_idx is signaled as sh_residual_coding_rice_shift to indicate the Rice parameter for that slice, and two syntax elements are signaled for each transformed slice to indicate the shift and / or offset parameters for deriving the Rice parameter for that slice. An example of the corresponding decoding process based on the VVC draft is shown below. Changes to the WC draft are shown in bold italics in Table 31. Note that sh_ts_residual_coding_rice_idx can be coded differently and / or have maximum values. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits written left bit first (left to right), can also be used to encode / decode the same syntax elements.

[0143] Slice Header Syntax [Table 36]

[0144]

[0142] sh_ts_residual_coding_rice_idx is res Specifies the rice parameter used for the residual_ts_coding() syntax structure. If sh_ts_residual_coding_rice_idx is not present, the value of sh_ts_residual_coding_rice_idx is inferred to be equal to 0.

[0145]

[0143] sh_residual_coding_rice_offset is abs Specifies the offset parameter used in the Rice parameter derivation process for _remainder[ ] and dec_abs_Level[ ]. If sh_residual_coding_rice_offset is not present, the value of sh_residual_coding_rice_offset is inferred to be equal to 0.

[0146]

[0144] sh_ts_residual_coding_rice_idx is res Specifies the rice parameter used in the residual_ts_coding() syntax construct. If sh_ts_residual_coding_rice_index is not present, the value of sh_ts_residual_coding_rice_index is inferred to be equal to 0.

[0147] [Table 37]

[0148] [Table 38-1] [Table 38-2]

[0149]

[0145] In yet another example, one control flag may be used to control the expansion of picture parameter set ranges. The control flag is transmitted in the extended syntax to indicate whether transmission of Rice parameters for transform skip blocks and transmission of shift parameters and / or offset parameters for deriving Rice parameters within transform blocks are enabled or disabled. When the control flag is transmitted as enabled, one syntax element is further transmitted to indicate Rice parameters for transform skip residual coding of the picture, and two syntax elements are further transmitted for regular residual coding to indicate shift parameters and / or offset parameters for deriving Rice parameters for the picture. When the control flag is transmitted as disabled (e.g., set to "0"), no further syntax elements are transmitted at lower levels to indicate Rice parameters for transform skip residual coding, and default Rice parameters (e.g., 1) are used for all transform skip residual coding; no further syntax elements are transmitted at lower levels to indicate shift parameters and / or offset parameters for deriving Rice parameters for regular residual coding, and default shift parameters and / or offset parameters (e.g., 0) are used for all regular residual coding. An example of a corresponding decoding process based on the VVC draft is shown below. where TH is a predetermined value (e.g., 0, 1, 2). Changes to the VVC draft are shown in bold and italic font in Table 34. It is worth noting that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx can be coded differently and / or have maximum values. For example, u(n), an unsigned integer using n bits, or f(n), a fixed-pattern bit string using n bits and written left-to-right, can also be used to code / decode the same syntax element.

[0150]

[0146] Picture parameter set range extension syntax [Table 39]

[0151]

[0147] pps_residual_coding_info_flag equal to 1 , pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_index may be present in the current picture. pps_residual_coding_info_flag equal to 0 specifies that pps_residual_coding_rice_shift, pps_residual_coding_rice_offset, and pps_ts_residual_coding_rice_idx are not present in the current picture. If pps_residual_coding_info_flag is not present, the value of pps_residual_coding_info_flag is inferred to be equal to 0.

[0152]

[0148] pps_residual_coding_rice_shift is abs Specifies the shift parameter used in the Rice parameter derivation process for _remainder[ ] and dec_abs_level[ ]. If pps_residual_coding_rice_shift is not present, the value of pps_residual_coding_rice_shift is inferred to be equal to 0.

[0153]

[0149] pps_residual_coding_rice_offset is ab Specifies the offset parameter used in the Rice parameter derivation process for s_remainder[ ] and dec_abs_level[ ]. If pps_residual_coding_rice_offset is not present, the value of pps_residual_coding_rice_offset is inferred to be equal to 0.

[0154]

[0150] pps_ts_residual_coding_rice_idx is re Specifies the rice parameter used in the residual_ts_coding() syntax structure. If pps_ts_residual_coding_rice_index is not present, the value of pps_ts_residual_coding_rice_index is inferred to be equal to 0.

[0155] [Table 40]

[0156] [Table 41-1] [Table 41-2]

[0157]

[0151] According to one or more examples of this disclosure, encoding a particular syntax element It is proposed to use different Rice parameters for transform skip residual coding, e.g., abs_remainder for transform skip residual coding, shift and offset the parameters to derive the Rice parameters used for abs_remainder / dec_abs_level in regular residual coding, and decide which one to use according to specific coding information of the current block, e.g., quantization parameters or coding bit depth associated with TB / CB and / or slice / profile, and / or according to a new flag associated with TB / CB / slice / picture / sequence level, e.g., sps_residual_coding_info_present_in_sh_flag.

[0158]

[0152] In one example, one control flag is transmitted in the slice header and The control flag indicates whether the derivation process of the Rice parameter of the block and the derivation process of the shift parameter and / or offset parameter of the Rice parameter of the transform block are enabled or disabled. When the control flag is transmitted as enabled, the Rice parameter may vary under different conditions according to the specific coding information of the current block, such as the quantization parameter and bit depth. And the shift parameter and / or offset parameter for Rice parameter derivation in regular residual coding may vary under different conditions according to the specific coding information of the current block, such as the quantization parameter and bit depth. When the control flag is transmitted as disabled (e.g., set to "0"), the default Rice parameter (e.g., 1) is used for all transform skip slices, and the default shift parameter and / or offset parameter (e.g., 0) is used for all transform slices. An example of a corresponding decoding process based on the VVC draft is shown below. Here, TH A and T.H. B is a predetermined threshold (e.g., TH A =8,TH B = 18 or 19). Changes to the VVC draft are shown in bold and italic font in Table 37. It is worth noting that in practice the same logic can be implemented in different ways. For example, the same Rice parameters can be derived using specific equations or lookup tables.

[0159] Slice Header Syntax [Table 42]

[0160] sh_residual_coding_rice_flag equal to 1 means Specifies that the bit-depth-aware Rice parameter derivation process is used for the current slice. sh_residual_coding_rice_flag equal to 0 specifies that the bit-depth-aware Rice parameter derivation process is not used for the current slice.

[0161] [Table 43]

[0162] [Table 44-1] [Table 44-2]

[0163]

[0155] In yet another example, the corresponding decoding process based on the VVC draft is as follows: where TH is a predetermined threshold (e.g., 18, 19). Changes to the VVC draft are shown in bold and italic font in Table 40. It is worth noting that in practice, the same logic can be implemented in different ways. For example, the same Rice parameters could be derived using a specific equation or lookup table.

[0164] [Table 45-1] [Table 45-2]

[0165]

[0156] According to another aspect of the present disclosure, the values of these above coding tools are generally The same general constraint control as the others in the constraint information It is proposed to add a constraint that flags the 'provides information'.

[0166] For example, sps_ts_residual_coding_ric equal to 1 sps_ts_residual_coding_rice_present_in_sh_flag specifies that sh_ts_residual_coding_rice_idx may be present in SH syntax structures that reference an SPS. sps_ts_residual_coding_rice_present_in_sh_flag equal to 0 specifies that sh_ts_residual_coding_rice_idx is not present in SH syntax structures that reference an SPS. According to this disclosure, it is proposed to add the syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0167] [Table 46]

[0168] [Table 47]

[0169]

[0158] In another example, pps_ts_residual_coding_rice_f When lag is equal to 1, it is specified that pps_ts_residual_coding_rice_index may exist in the current picture. When pps_ts_residual_coding_rice_flag is equal to 0, it is specified that pps_ts_residual_coding_rice_idx does not exist in the current picture. According to this disclosure, in order to provide the same general constraint control as other flags, it is proposed to add the syntax element gci_no_ts_residual_coding_rice_constraint_flag to the general constraint information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

[0170]

Table 48

[0171]

Table 49

[0172]

[0159] In yet another example, the sps_rice_adaptation_e nabled_flag equal to 1 indicates that the Rice parameter for the binarization of abs_remainder[ ] and dec_abs_ level can be derived by an expression.

[0173]

[0160] The expression may include RiceParam = RiceParam + shiftVal and shiftVal=(localSumAbs<Tx[0])?Rx[0]:((localSumAbs<Tx[1])?Rx[1]:((localSumAbs<Tx[2])?Rx[2]:((localSumAbs<Tx[3])?Rx[3]:Rx[4])))), and the lists Tx[ ] and Rx[ ] are specified as follows: Tx ]={32,128,512,2048}>>(1523)Rx[ ]={0, 2, 4, 6, 8}

[0174]

[0161] According to the present disclosure, the general constraint flag is used to provide the same general constraint control as other flags. It is proposed to add the syntax element gci_no_rice_adaptation_constraint_flag to the information syntax. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0175] [Table 50]

[0176] [Table 51]

[0177] The proposed Rice parameter adaptation method is based on transform skip residual coding (TS RC), the proposed method may only be effective when TSRC is enabled. Similarly, one or more embodiments of the present disclosure propose to add one bti stream constraint that requires the value of gci_no_rice_adaptation_constraint_flag to be 1 when transform skip mode is disabled from the general constraint information level, e.g., when the value of gci_no_transform_skip_constraint_flag is set to 1.

[0178] In yet another example, sps_range_extension_f equal to 1 lag specifies that the sps_range_extension() syntax structure is present in the SPSRBSP syntax structure. sps_range_extension_flag equal to 0 specifies that this syntax structure is not present. According to this disclosure, it is proposed to add the syntax element gci_no_range_extension_constraint_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0179] [Table 52]

[0180] [Table 53]

[0181]

[0164] Figure 9 illustrates a video encoding method according to an example of the present disclosure. In step 1902, the decoder can receive a sequence parameter set (SPS) range extension flag, which indicates whether a syntax structure sps_range_extension is present in a slice head (SH) raw byte sequence payload (RBSP) syntax structure based on the value of the SPS range extension flag.

[0182] In step 1904, in response to determining that the value of the SPS range extension flag is equal to 1, In response, the decoder can determine that sps_range_extension is present in the SHRBSP syntax structure.

[0183] In step 1906, in response to determining that the value of the range extension flag is equal to 0, The decoder can then determine that sps_range_extension is not present in the SHRBSP syntax structure.

[0184] In yet another example, sps_cabac_bypass_alig equal to 1 nment_enabled_flag is a syntax element of sb_coded_flag[ ][ ], abs_remainder[ ], dec_abs_Level[n] and aligned before bypass decoding of coeff_sign_flag[ ] sps_cabac_bypass_alignment_enabled_flag equal to 0 specifies that the value of ivlCurrRange is not aligned before bypass decoding. According to this disclosure, it is proposed to add the syntax element gci_no_cabac_bypass_alignment_constraint_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0185] [Table 54]

[0186] [Table 55]

[0187]

[0168] Figure 10 illustrates a video encoding method according to an example of the present disclosure. , can be applied to the decoder. In step 2002, the decoder can receive a sequence parameter set (SPS) alignment enable flag, which indicates whether the index ivlCurrRange is aligned before bypass decoding of syntax elements sb_coded_flag, abs_remainder, dec_abs_level, and coeff_sign_flagn based on a valid SPS alignment value.

[0188] In step 2004, if the value of the SPS alignment enable flag is equal to 1, In response to determining that the ivlCurrRange is aligned, the decoder may determine that the ivlCurrRange is aligned before bypass decoding.

[0189]

[0170] In step 2006, if the value of the SPS alignment enable flag is equal to 0, In response to determining , the decoder may determine that the ivlCurrRange is not aligned before bypass decoding.

[0190] In yet another example, extended_precision_pr equal to 1 The processing_flag specifies that extended dynamic range can be used for the transform coefficients, and a transform processing extended_precision_processing_flag equal to 0 specifies that extended dynamic range is not used. According to this disclosure, it is proposed to add a syntax element gci_no_extended_precision_processing_constraint_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0191] [Table 56]

[0192] [Table 57]

[0193]

[0172] Figure 11 illustrates a video encoding method according to an example of the present disclosure. , can be applied to the decoder. In step 2102, the decoder can receive an extended precision processing flag that indicates whether extended dynamic range is employed for the transform coefficients during the transform process based on the value of the extended precision processing flag.

[0194]

[0173] In step 2104, upon determining that the value of the extended precision processing flag is equal to 1, In response, the decoder may determine that an extended dynamic range is to be employed during the transform process and for the transform coefficients.

[0195] In step 2106, in response to determining that the value of the extended precision processing flag is 0, In response, the decoder may determine that extended dynamic range is not employed during the transform process or for the transform coefficients.

[0196] In yet another example, persistent_rice_adapt equal to 1 ation_enabled_flag is abs_remainder[ ] and dec Specifies that the Rice parameter derivation for _abs_level binarization can be initialized at the beginning of each sub-block using mode-dependent statistics accumulated from previous sub-blocks. A persistent_rice_adaptation_enabled_flag equal to 0 specifies that previous sub-block state is not used for Rice parameter derivation. According to this disclosure, it is proposed to add the syntax element gci_no_persistent_rice_adaptation_constraint_flag to the general constraint information syntax to provide the same general constraint control as other flags. An example of the decoding process for the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

[0197] [Table 58]

[0198] [Table 59]

[0199]

[0176] Figure 12 illustrates a video encoding method according to an example of the present disclosure. , can be applied to the decoder. In step 2202, the decoder can receive a persistent Rice adaptation enable flag that indicates whether the Rice parameter derivation for binarization of abs_remainder and dec_abs_level is initialized at the beginning of each sub-block employing mode-dependent statistics accumulated from previous sub-blocks based on the value of persistent_rice_adaptation_enabled_flag.

[0200] In step 2204, persistent_rice_adapta In response to determining that the value of tion_enabled_flag is equal to 1, the decoder may determine that the Rice parameter derivation for binarization is initialized at the beginning of each sub-block, employing mode-dependent statistics accumulated from previous sub-blocks.

[0201] In step 2206, if the value of the persistent Rice adaptation enable flag is 0, In response to determining , the decoder may determine that the previous sub-block state is not employed in the Rice parameter derivation.

[0202] In yet another example, sps_rrc_rice_extension equal to 1 n_flag is abs_remainder[ ] and dec_abs_Level Specifies that the extension of the Rice parameter derivation for binarization of [ ] is enabled. An equal sps_rrc_rice_extension_flag specifies that the extension of the Rice parameter derivation for binarization of abs_remainder[ ] and dec_abs_Level[ ] is disabled. According to this disclosure, it is proposed to add the syntax element gci_no_rrc_rice_extension_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are shown in italics below.

[0203] [Table 60]

[0204] [Table 61]

[0205]

[0180] Figure 17 illustrates a method for video decoding according to an example of this disclosure. For example, it can be applied to a decoder. In step 2702, the decoder can receive an SPS Rice extension flag that indicates whether extension of the Rice parameter derivation for binarization of abs_remainder and dec_abs_level is enabled.

[0206] In step 2704, if the value of the SPS Rice Extension Flag is determined to be equal to 1, In response to the determination, the decoder may determine that an extension of the Rice parameter derivation for binarization is valid.

[0207]

[0182] In step 2706, if it is determined that the value of the SPS Rice Extension Flag is equal to 0, In response to the determination, the decoder may determine that the extension of the Rice parameter derivation for binarization is invalid.

[0208]

[0183] In yet another example, sps_persistent_rice_a equal to 1 daptation_enabled_flag is abs_remainder[ ] The Rice parameter derivation for binarization of dec_abs_level[ ] and dec_abs_level[ ] is as follows: Specifies that the Rice parameter is initialized at the beginning of each TU using statistics accumulated from the previous TU. When sps_persistent_rice_adaptation_enabled_flag is equal to 0, it specifies that the previous TU state is not used to derive the Rice parameters. According to this disclosure, it is proposed to add the syntax element gci_no_persistent_rice_adaptation_enabled_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are shown in italics below.

[0209] [Table 62]

[0210] [Table 63]

[0211]

[0184] Figure 18 illustrates a method for video decoding according to an example of this disclosure. For example, it can be applied to a decoder. In step 2802, the decoder can receive an SPS Rice adaptation enable flag that indicates whether the Rice parameter derivation for binarization of abs_remainder and dec_abs_level is initialized at the start of each transform unit using statistics accumulated from previous TUs.

[0212] In step 2804, the value of the SPS Rice Adaptation Enable flag is equal to 1. In response to determining that, the decoder may determine that the Rice parameter derivation for binarization is initialized at the start of each TU using statistics accumulated from previous TUs.

[0213] In step 2806, the value of the SPS Rice Adaptation Enable flag is equal to 0. In response to determining that, the decoder may determine that the previous TU state is not employed in the Rice parameter derivation.

[0214] In yet another example, sps_reverse_last_sig_coeff _enabled_flag equal to 1 specifies that sps_reverse_last_sig_coeff_enabled_flag is present in the slice_header() syntax structure that references the SPS. sps_reverse_last_sig_coeff_enabled_flag equal to 0 specifies that sps_reverse_last_sig_coeff_enabled_flag is not present in the slice_header() syntax structure that references the SPS. According to this disclosure, it is proposed to add the syntax element gci_no_reverse_last_sig_coeff_enabled_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The additions are highlighted in italics.

[0215] [Table 64]

[0216] [Table 65]

[0217]

[0188] When sh_reverse_last_sig_coeff_flag is equal to 1, it specifies that the coordinates of the last significant coefficient are coded relative to ((Log2ZoTbwidth<<1)-1, (Log2ZoTbHeight<<1)-1) of each transform block of the current slice. When sh_reverse_last_sig_coeff_flag is equal to 0, it specifies that the coordinates of the last significant coefficient are coded relative to (0,0) of each transform block of the current slice. If not present, the value of sh_reverse_last_sig_coeff_flag is inferred to be equal to 0.

[0218]

[0189] Figure 19 shows a method for video decoding according to an example of the present disclosure. This method can be applied to, for example, a decoder. In step 2902, the decoder can receive an enable flag of the last significant coefficient of the SPS, which indicates whether an enable flag of the inverted coordinate of the last significant coefficient of the SH is present in a slice header syntax structure referencing the SPS.

[0219]

[0190] In step 2904, in response to determining that the value of the enable flag of the inverted coordinate of the last significant coefficient of the SPS is equal to 1, the decoder can determine that the enable flag of the last significant coefficient of the SH is present in the slice header syntax structure that references the SPS.

[0220]

[0191] In step 2906, in response to determining that the value of the enable flag of the inverted coordinate of the last significant coefficient of the SPS is equal to 0, the decoder can determine that the enable flag of the last significant coefficient of the SH is not present in the slice header syntax structure that references the SPS.

[0221] In yet another example, sps_transform_precision equal to 1 The on_adaptation_enabled_flag specifies that the scaling process of transform coefficients and the downshifting in the transformation process of scaled transform coefficients are adaptively assigned by examining the coefficient values during inverse quantization and inverse transformation. According to this disclosure, it is proposed to add a syntax element gci_no_transform_precision_adaptation_enabled_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

[0222] [Table 66]

[0223] [Table 67]

[0224]

[0193] Figure 20 illustrates a method for video decoding according to an example of this disclosure. For example, it can be applied to a decoder. In step 3002, the decoder can receive an SPS transform precision adaptation enable flag, which indicates whether the scaling process of transform coefficients and the downshifting in the transformation process of scaled transform coefficients are adaptively assigned by examining the coefficient values of inverse quantization and inverse transformation.

[0225]

[0194] In step 3004, if the value of the SPS conversion precision adaptation enable flag is equal to 1, In response to determining that the scaling process of the transform coefficients and the downshifting in the transformation process of the scaled transform coefficients are adaptively assigned by examining the coefficient values of the inverse quantization and inverse transformation.

[0226]

[0195] In yet another example, sps_high_throughput_flag equal to 1 specifies that all residual coding syntax elements are coded in bypass mode except for the last significant coefficient position of RRC, and that alignment is required only once after the last significant coefficient position of RRC and at the beginning of the TB of TSRC. According to this disclosure, it is proposed to add a syntax element gci_no_high_throughput_flag to the general constraint information syntax to provide the same general constraint control as the other flags. An example of the decoding process of the VVC draft is shown below. The changes to the VVC draft are highlighted. The added parts are highlighted in italics.

[0227] [Table 68]

[0228] [Table 69]

[0229]

[0196] Figure 21 illustrates a method for video decoding according to an example of this disclosure. For example, it can be applied to a decoder. In step 3102, the decoder can receive an SPS high throughput flag that indicates whether a syntax element in the residual coding is coded through a bypass mode.

[0230] In step 3104, in response to determining that the value of the SPS high-throughput flag is equal to 1, the decoder may determine that all syntax elements of the residual coding are coded through the bypass mode, except for the last significant coefficient position in normal residual coding (RRC). Alignment is performed after the last significant coefficient position in RRC and at the beginning of the transform block (TB) in transform-skip residual coding (TSRC).

[0231]

[0198] The above method can be implemented using an apparatus that includes one or more circuits. This may include an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. The apparatus may use circuitry in combination with other hardware or software components to perform the methods described above. Each module, sub-module, unit, or sub-unit disclosed above may be at least partially implemented using one or more circuits.

[0232] Determination of Rice Parameters

[0233]

[0200] On the encoder side, TSRC coding uses a set of approximations to derive the best Rice parameters. To achieve this, multiple coding passes may be required. This multi-pass coding may not be suitable for practical hardware encoder designs. To solve this problem, a low-delay TSRC coding scheme has also been proposed. According to one or more examples of the present disclosure, it is proposed to derive the Rice parameter according to specific coding information of the current slice, such as a quantization parameter and / or a coding bit depth associated with the slice / picture / sequence, and / or a hash ratio associated with the slice / picture / sequence level. Various methods can be used to derive the Rice parameter. Some exemplary methods are listed below. It should be noted that the following methods can be applied independently or in combination.

[0234]

[0201] 1. The Rice parameters mentioned in the above embodiment are related to the time resolution of the video (e.g. It may further depend on the video resolution, which includes both the video quality (e.g., frame rate) and spatial resolution (e.g., picture width and height).

[0235]

[0202] 2. Rice parameters are available at the sequence level, picture level, and slice level. The Rice parameter may vary across different slice levels, and / or any preset region. In one particular example, different Rice values are used for pictures with different temporal layer IDs (related to nuh_temporal_id_plusl specified in the VVC specification). Alternatively, the Rice parameter may include a value determined based on the QP value used at the sequence level, picture level, slice level, and / or any preset region. For example, the Rice parameter = Clip3(1, 8, (TH-QP) / 6), where TH is a preset threshold (e.g., 18, 19).

[0236] 3. The Rice parameter is the coding information between the current slice and the previous slice. The Rice parameter may be set as a default value, e.g., 1, according to changes in information. In one specific example, if the temporal layer ID is changed compared to the previous picture, the default Rice value is used for the picture. Alternatively, if AQ is greater than TH, the default Rice value is used for the picture. Here, AQ is calculated as abs(QPcurrent-QPprevious), and TH is a preset threshold. Rice parameter (e.g., 0, 5). For example, if the hash ratio from the intra block copy mode of the current slice is greater than TH, the Rice parameter = 1. Here, TH is a preset threshold, e.g., Max(41*(number of CTUs), 4200).

[0237]

[0204] 4. abs_remaind coded in the previous slice according to the coding order The Rice parameter for each slice is based on the value of er. In one specific example, after one slice is coded, the number of bins for binarization of abs_remainder using different Rice parameters is calculated and then used to determine the Rice parameter for the next slice. For example, the Rice parameter that achieved the smallest number of bins in the previous slice is selected for the current slice. As another example, if the current slice and its previous slice use the same QP, the Rice parameter that achieved the smallest number of bins in the previous slice is selected for the current slice. Otherwise, the number of bins generated in the previous slice using the default Rice parameter (i.e., 1) is scaled by TH before being compared with other Rice parameters, and the Rice parameter that results in the smallest number of bins is selected for the current slice. TH is a preset threshold, for example, 0.9.

[0238]

[0205] 5. abs_remain coded in the previous slice according to the coding order The Rice parameter and Rice parameter for each slice based on the value of der are The Rice parameter may be adjusted according to changes in the coding information between the current slice and the previous slice. In one specific example, the Rice parameter that achieves the smallest number of bins in the previous slice is selected for the current slice. Also, if AQ is greater than TH, the Rice value can be adjusted, where AQ is calculated as abs(QPcurrent-QPprevious), and TH is a preset threshold value for the Rice parameter (e.g., 0, 5). The adjustment can be adding a preset offset (e.g., +1, -1) or scaling by a preset value.

[0239]

[0206] FIG. 16 illustrates a low-delay transform skip residual coding (TSRC) method according to an example of the present disclosure. 26 shows a flowchart of a method for deriving a Rice parameter based on coding information for a current slice of video. The method may be applied to, for example, an encoder. In step 2602, the encoder may derive a Rice parameter based on coding information for a current slice of video. The coding information may include one or more of the following parameters: a quantization parameter or coding bit depth associated with the slice, picture, or sequence of video, or a hash ratio associated with the slice, picture, or sequence of video.

[0240]

[0207] Note that the above encoder method can be applied to the decoder side. In certain instances, the Rice parameters do not need to be signaled to the decoder; the encoder / decoder use the same method to derive the Rice parameters.

[0241] FIG. 8 illustrates a computing environment coupled with a user interface 1860. 18 illustrates a computing environment 1810. The computing environment 1810 may be part of a data processing server. The computing environment 1810 includes a processor 1820, a memory 1840, and an I / O interface 1850.

[0242]

[0209] The processor 1820 typically handles display, data acquisition, data communication, and image processing. The processor 1820 controls the overall operation of the computing environment 1810, such as operations related to the processing of the data. The processor 1820 may include one or more processors that execute instructions to perform all or a portion of the steps in the methods described above. Additionally, the processor 1820 may include one or more modules that facilitate interaction between the processor 1820 and other components. The processor may be a central processing unit (CPU), a microprocessor, a single-chip machine, a GPU, etc.

[0243]

[0210] Memory 1840 is used to support the operation of computing environment 1810. The memory 1840 is configured to store various types of data for purposes of storing the various types of data. The memory 1840 may include predetermined software 1842. Examples of such data include instructions for any application or method operating on the computing environment 1810, video data sets, image data, etc. The memory 1840 may be implemented by using any type of volatile or non-volatile memory device, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk, or a combination thereof.

[0244]

[0211] The I / O interface 1850 connects the processor 1820 to the keyboard, The I / O interface 1850 provides an interface between the peripheral interface module and peripheral devices such as a click wheel, buttons, etc. The buttons include, but are not limited to, a home button, a start scan button, and a stop scan button. The I / O interface 1850 can be coupled to an encoder and a decoder.

[0245] In some embodiments, a computing device for performing the above method is provided. A non-transitory computer-readable storage medium containing a plurality of programs, such as contained in memory 1840, executable by processor 1820 in environment 1810 is also provided. For example, the non-transitory computer-readable storage medium may be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0246]

[0213] A non-transitory computer-readable storage medium having one or more processors The computer-implemented method further includes storing a plurality of programs for execution by a computing device, the plurality of programs, when executed by the one or more processors, causing the computing device to perform the motion estimation method described above.

[0247] In some embodiments, the computing environment 1810 performs the above method. It may be implemented using one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), graphics processing units (GPUs), controllers, microcontrollers, microprocessors, or other electronic components to execute.

[0248] FIG. 13 illustrates a method for encoding video blocks in parallel, in accordance with some implementations of this disclosure. 13 is a block diagram illustrating an exemplary system 10 for encoding and decoding video data. As shown in FIG. 13, system 10 includes a source device 12 that generates and encodes video data that is subsequently decoded by a destination device 14. Source device 12 and destination device 14 can include any of a wide variety of electronic devices, including desktop or laptop computers, tablet computers, smartphones, set-top boxes, digital televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc. In some implementations, source device 12 and destination device 14 are equipped with wireless communication capabilities.

[0249] In some implementations, the destination device 14 receives the decoded Link 16 may receive encoded video data to be transmitted from source device 12 to destination device 14. Link 16 may comprise any type of communication medium or device capable of moving encoded video data from source device 12 to destination device 14. In one example, link 16 may comprise a communication medium that enables source device 12 to transmit encoded video data directly to destination device 14 in real time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 14. The communication medium may include any wireless or wired communication medium, such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment useful for facilitating communication from source device 12 to destination device 14.

[0250] In some other implementations, the encoded video data is transmitted to the output interface 22 The encoded video data may be transmitted from the storage device 32 to the storage device 32. The encoded video data in the storage device 32 may then be accessed by the destination device 14 via the input interface 28. The storage device 32 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a digital versatile disc (DVD), a read-only compact disc memory (CD-ROM), flash memory, volatile or non-volatile memory, or other suitable digital storage media for storing the encoded video data. In a further example, the storage device 32 may include a source The destination device 14 may correspond to a file server or another intermediate storage device capable of holding the encoded video data generated by the storage device 12. The destination device 14 can access the stored video data from the storage device 32 via streaming or download. The file server may be any type of computer capable of storing encoded video data and transmitting the encoded video data to the destination device 14. Examples of file servers include a web server (e.g., a website), a file transfer protocol (FTP) server, a network-attached storage (NAS) device, or a local disk drive. The destination device 14 can access the encoded video data through any standard data connection, including a wireless channel (e.g., a wireless fidelity (Wi-Fi) connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on a file server. The transmission of the encoded video data from the storage device 32 may be a streaming transmission, a download transmission, or a combination of both.

[0251]

[0218] As shown in Figure 13, the source device 12 is a video source. 18, a video encoder 20, and an output interface 22. Video source 18 may include sources such as video imaging devices, e.g., a video camera, a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and / or a computer graphics system that generates computer graphics data as the source video, or a combination of such sources. As an example, if video source 18 is a video camera in a security surveillance system, source device 12 and destination device 14 may form a camera phone or video phone. However, the implementations described herein are applicable to video encoding generally and to wireless and / or wired applications.

[0252]

[0219] Captured, pre-captured, or computer-generated video The video may be encoded by video encoder 20. The encoded video data may be transmitted directly to destination device 14 via output interface 22 of source device 12. The encoded video data may also (or alternatively) be stored in storage device 32 for later access by destination device 14 or other devices for decoding and / or playback. Output interface 22 may further include a modem and / or a transmitter.

[0253]

[0220] The destination device 14 includes an input interface 28, a video decoder 30, and and display device 34. Input interface 28 may include a receiver and / or modem and may receive encoded video data over link 16. The encoded video data communicated over link 16 or provided on storage device 32 may include various syntax elements generated by video encoder 20 for use by video decoder 30 in decoding the video data. Such syntax elements may be included within the encoded video data transmitted over a communications medium, stored on a storage medium, or stored on a file server.

[0254]

[0221] In some implementations, the destination device 14 may include an integrated display device and and destination device 14. Display device 34 displays the decoded video data to a user and may comprise any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0255]

[0222] The video encoder 20 and the video decoder 30 are compatible with VVC, HEVC, MP4, It may operate in accordance with proprietary or industry standards, such as EG-4, Part 10, AVC, or extensions to such standards. It should be understood that the present application is not limited to a particular video encoding / decoding standard and may be applicable to other video encoding / decoding standards. It is generally contemplated that video encoder 20 of source device 12 may be configured to encode video data in accordance with any of these current or future standards. Similarly, it is generally contemplated that video decoder 30 of destination device 14 may be configured to decode video data in accordance with any of these current or future standards.

[0256]

[0223] The video encoder 20 and the video decoder 30 may each include various suitable The video encoder 20 and video decoder 30 may be implemented as either a single encoder and / or decoder circuit, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. If implemented partially in software, the electronic device may store the software instructions on a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the video encoding / decoding operations disclosed in this disclosure. Each of the video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (CODEC) within the respective device.

[0257]

[0224] Figure 14 illustrates an example video encoding process according to some implementations described in this application. 1 is a block diagram illustrating a video encoder 20. Video encoder 20 can perform intra-predictive and inter-predictive coding of video blocks within a video frame. Intra-predictive coding reduces or removes spatial redundancy in video data within a particular video frame or picture depending on spatial prediction. Inter-predictive coding reduces or removes temporal redundancy in video data within adjacent video frames or pictures of a video sequence depending on temporal prediction. It should be noted that the term "frame" may be used synonymously with the terms "image" or "picture" in the field of video coding.

[0258]

[0225] As shown in Figure 14, the video encoder 20 includes a video data memory 40, The video encoder 20 includes a prediction processing unit 41, a decoded picture buffer (DPB) 64, an adder 50, a transform processing unit 52, a quantization unit 54, and an entropy coding unit 56. The prediction processing unit 41 further includes a motion estimation unit 42, a motion compensation unit 44, a partitioning unit 45, an intra-prediction processing unit 46, and an intra-block copy (BC) unit 48. In some implementations, the video encoder 20 also includes an inverse quantization unit 58, an inverse transform processing unit 60, and an adder 62 for video block reconstruction. An in-loop filter 63, such as a deblocking filter, may be disposed between the adder 62 and the DPB 64 to filter block boundaries and remove blocky artifacts from the reconstructed video. In addition to the deblocking filter, another in-loop filter, such as a sample adaptive offset (SAO) filter and / or an adaptive in-loop filter (ALF), may also be used to filter the output of the adder 62. In some examples, the in-loop filter may be omitted, and the decoded video blocks may be provided directly to DPB 64 by summer 62. Video encoder 20 may take the form of a fixed or programmable hardware unit, or may be divided into one or more of the illustrated fixed or programmable hardware units.

[0259]

[0226] The video data memory 40 is encoded by components of the video encoder 20. The video data in the video data memory 40 can be stored. 13. DPB 64 is a buffer that stores reference video data (e.g., reference frames or pictures) for use in encoding video data by video encoder 20 (e.g., in intra- or inter-predictive coding modes). Video data memory 40 and DPB 64 may be formed by any of a variety of memory devices. In various examples, video data memory 40 may be on-chip with other components of video encoder 20 or may be off-chip relative to those components.

[0260]

[0227] As shown in Figure 14, the division unit 45 in the prediction processing unit 41 divides the video Upon receiving the data, the video data is divided into video blocks. This division may include dividing the video frame into slices, tiles (e.g., sets of video blocks), or other larger coding units (CUs) according to a pre-defined division structure, such as a quad-tree (QT) structure associated with the video data. A video frame is, or can be viewed as, a two-dimensional array or matrix of samples with sample values. The samples in the array are sometimes referred to as pixels or pels. The number of samples in the horizontal and vertical directions (or axes) of the array or image defines the size and / or resolution of the video frame. The video frame may be divided into multiple video blocks, for example, by using QT division. A video block may also be, or can be viewed as, a two-dimensional array or matrix of samples with sample values, albeit with smaller dimensions than a video frame. The number of samples in the horizontal and vertical directions (or axes) of a video block defines the size of the video block. A video block may be further divided into one or more block divisions or sub-blocks (potentially forming blocks again). For example, QT division, binary-tree (BT) division, triple-tree (TT) division, or any combination thereof may be used repeatedly. It should be noted that the term "block" or "video block" as used herein may refer to a portion of a frame or picture, particularly a rectangular (square or non-square) portion. For example, with reference to HEVC and VVC, a block or video block may be or correspond to a coding tree unit (CTU), a CU, a prediction unit (PU), or a transform unit (TU), and / or may be or correspond to a corresponding block, e.g., a coding tree block (CTB), a coding block (CB), a prediction block (PB), or a transform block (TB), and / or a sub-block.

[0261]

[0228] The prediction processing unit 41 determines the error results (e.g., the coding rate and distortion level) ), for the current video block, prediction processing unit 41 may select one of a plurality of possible predictive coding modes, such as one of a plurality of intra-predictive coding modes or one of a plurality of inter-predictive coding modes. Prediction processing unit 41 provides the resulting intra- or inter-predictive coded block to summer 50 to generate a residual block, which is then provided to summer 62 to reconstruct a coded block for later use as part of a reference frame. Prediction processing unit 41 also provides syntax elements, such as motion vectors, intra-mode indicators, syntax information such as partition information, etc., to entropy coding unit 56.

[0262]

[0229] To select an appropriate intra-prediction coding mode for the current video block, Intra-prediction processing unit 46 within prediction processing unit 41 may perform intra-predictive coding of the current video block relative to one or more neighboring blocks in the same frame as the current block to be coded to provide spatial prediction. Motion estimation unit 42 and motion compensation unit 44 within prediction processing unit 41 perform inter-predictive coding of the current video block relative to one or more predictive blocks in one or more reference frames to provide temporal prediction. Video encoder 20 may perform multiple coding passes, e.g., to select an appropriate coding mode for each block of video data. Cut.

[0263]

[0230] In some implementations, the motion estimation unit 42 generates motion vectors. The intra BC unit 48 determines an inter-prediction mode for the current video frame by, which indicates the displacement of a video block in the current video frame relative to a predictive block in a reference video frame according to a predetermined pattern within the sequence of video frames. Motion estimation performed by motion estimation unit 42 is the process of generating motion vectors that estimate the motion of video blocks. For example, the motion vector may indicate the displacement of a video block in the current video frame or picture relative to a predictive block in a reference frame relative to the current block being coded in the current frame. The predetermined pattern may designate a video frame in the sequence as a P-frame or a B-frame. Intra BC unit 48 may determine vectors, e.g., block vectors, for intra BC coding in a manner similar to the determination of motion vectors by motion estimation unit 42 for inter prediction, or may utilize motion estimation unit 42 to determine the block vectors.

[0264]

[0231] A prediction block of a video block is a video block that is coded in terms of pixel differences. The reference frame may be a block or reference block that is deemed to closely match or correspond to the reference frame, which may be determined by sum of absolute differences (SAD), sum of squared differences (SSD), or other difference metric. In some implementations, video encoder 20 may calculate values for sub-integer pixel locations of the reference frame stored in DPB 64. For example, video encoder 20 may interpolate values for quarter-pixel locations, eighth-pixel locations, or other fractional-pixel locations of the reference frame. Thus, motion estimation unit 42 may perform motion searches for whole-pixel and fractional-pixel locations and output motion vectors with fractional-pixel accuracy.

[0265]

[0232] Motion estimation unit 42 calculates the location of the video block relative to the first reference frame list. Motion estimation unit 42 calculates motion vectors for video blocks in inter-predictively coded frames by comparing the positions of predictive blocks of reference frames selected from either the first reference frame list (List 0) or the second reference frame list (List 1), each identifying one or more reference frames stored in DPB 64. Motion estimation unit 42 sends the calculated motion vectors to motion compensation unit 44 and then to entropy coding unit 56.

[0266] The motion compensation performed by the motion compensation unit 44 is The motion vector for the current video block may include fetching or generating a predictive block based on the motion vector determined by motion vector estimation unit 42. Upon receiving the motion vector for the current video block, motion compensation unit 44 may identify the predictive block to which the motion vector points in one of the reference frame lists, obtain the predictive block from DPB 64, and forward the predictive block to summer 50. Summer 50 then forms a residual video block of pixel difference values by subtracting pixel values of the predictive block provided by motion compensation unit 44 from pixel values of the current video block being coded. The pixel difference values forming the residual video block may include luma difference components, chroma difference components, or both. Motion compensation unit 44 may also generate syntax elements associated with the video blocks of the video frame that are used by video decoder 30 in decoding the video blocks of the video frame. The syntax elements may include, for example, syntax elements that define the motion vector used to identify the predictive block, any flags indicating a prediction mode, or any other syntax information described herein. Note that motion estimation unit 42 and motion compensation unit 44 may be highly integrated, but are shown separately for conceptual purposes.

[0267]

[0234] In some implementations, the intra BC unit 48 includes the motion estimation unit 42 and The vectors may be generated and the predictive block may be fetched in a manner similar to that described above in connection with the motion compensation unit 44, except that the predictive block is in the same frame as the current block being coded, and the vectors are referred to as block vectors rather than motion vectors. In particular, the intra BC unit 48 may determine an intra prediction mode to use to code the current block. In some examples, the intra BC unit 48 may encode the current block using various intra prediction modes, e.g., during separate coding passes, and test their performance through rate-distortion analysis. The intra BC unit 48 may then select an appropriate intra prediction mode to use from among the various tested intra prediction modes and generate an intra mode indicator accordingly. For example, the intra BC unit 48 may calculate rate-distortion values using rate-distortion analysis for the various tested intra prediction modes, and may select the intra prediction mode with the best rate-distortion characteristics among the test modes as the appropriate intra prediction mode to use. The rate-distortion analysis generally determines the amount of distortion (or error) between the coded block and the original uncoded block coded to generate the coded block, as well as the bit rate (i.e., number of bits) used to generate the coded block. Intra BC unit 48 may calculate ratios from the distortions and rates of various coded blocks to determine which intra prediction mode exhibits the best rate-distortion value for that block.

[0268]

[0235] In another example, the intra BC unit 48 is Compensation unit 44 may be used in whole or in part to perform such functions for intra BC prediction according to the implementations described herein. In either case, for intra block copying, the predictive block may be a block that is deemed to closely match the block to be coded in terms of pixel difference, which may be determined by SAD, SSD, or other difference metric, and identification of the predictive block may include calculating values for sub-integer pixel positions.

[0269]

[0236] Whether the predicted blocks are from the same frame according to intra prediction or If the predicted block is from a different frame according to a target prediction, video encoder 20 may form a residual video block by subtracting pixel values of the predictive block from pixel values of the current video block being encoded to form pixel difference values. The pixel difference values forming the residual video block may include both luma component differences and chroma component differences.

[0270]

[0237] The intra-prediction processing unit 46 performs the motion estimation and the intra-prediction processing as described above. As an alternative to inter prediction performed by motion compensation unit 44 or intra block copy prediction performed by intra BC unit 48, the current video block may be intra predicted. In particular, intra prediction processing unit 46 may determine the intra prediction mode to use to encode the current block. To do so, intra prediction processing unit 46 may encode the current block using various intra prediction modes, e.g., during separate encoding passes, and intra prediction processing unit 46 (or, in some examples, a mode selection unit) may select an appropriate intra prediction mode to use from the tested intra prediction modes. Intra prediction processing unit 46 may provide information indicating the selected intra prediction mode for the block to entropy coding unit 56. Entropy coding unit 56 may encode the information indicating the selected intra prediction mode into the bitstream.

[0271]

[0238] The prediction processing unit 41 performs inter-prediction or intra-prediction on the current video. After determining the predicted block of the oblique video block, adder 50 calculates the predicted block from the current video block. A residual video block is formed by subtracting the blocks. The residual video data in the residual block, which may be included in one or more TUs, is provided to transform processing unit 52. Transform processing unit 52 converts the residual video data into residual transform coefficients using a transform, such as a discrete cosine transform (DCT) or a conceptually similar transform.

[0272]

[0239] The transform processing unit 52 passes the resulting transform coefficients to the quantization unit 54. The quantization unit 54 may quantize the transform coefficients to further reduce the bit rate. The quantization process may reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be varied by adjusting a quantization parameter. In some examples, the quantization unit 54 may perform a scan of a matrix containing the quantized transform coefficients. Alternatively, the entropy coding unit 56 may perform the scan.

[0273] Following quantization, entropy coding unit 56 generates the quantizer using: The entropy coding unit 56 entropy codes the encoded transform coefficients into a video bitstream, for example, using context-adaptive variable length coding (CAVLC), context-adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques. The encoded bitstream may then be transmitted to video decoder 30 as shown in FIG. 13, or archived in storage device 32 as shown in FIG. 13 for later transmission to or retrieval by video decoder 30. Entropy coding unit 56 may also entropy code motion vectors and other syntax elements of the current video frame being coded.

[0274]

[0241] The inverse quantization unit 58 and the inverse transform processing unit 60 perform inverse quantization and Motion compensation unit 44 applies a transform and an inverse transform to reconstruct the residual video block in the pixel domain to generate reference blocks for prediction of other video blocks. As described above, motion compensation unit 44 may generate motion-compensated prediction blocks from one or more reference blocks of frames stored in DPB 64. Motion compensation unit 44 may also apply one or more interpolation filters to the prediction block to calculate sub-integer pixel values for use in motion estimation.

[0275]

[0242] Adder 62 receives the reconstructed residual block produced by motion compensation unit 44. The resulting motion compensated prediction block may be added to the resulting motion compensated prediction block to generate a reference block for storage in DPB 64. The reference block may then be used by intra BC unit 48, motion estimation unit 42, and motion compensation unit 44 as a prediction block to inter predict another video block in a subsequent video frame.

[0276]

[0243] Figure 15 illustrates an exemplary video decoder 30 according to some implementations of the present application. 14. The video decoder 30 includes a video data memory 79, an entropy decoding unit 80, a prediction processing unit 81, an inverse quantization unit 86, an inverse transform processing unit 88, an adder 90, and a DPB 92. The prediction processing unit 81 further includes a motion compensation unit 82, an intra prediction unit 84, and an intra BC unit 85. The video decoder 30 may perform a decoding process that is generally the reverse of the encoding process described above for the video encoder 20 in connection with FIG. 14. For example, the motion compensation unit 82 may generate prediction data based on a motion vector received from the entropy decoding unit 80, while the intra prediction unit 84 may generate prediction data based on an intra prediction mode indicator received from the entropy decoding unit 80.

[0277]

[0244] In some examples, the units of the video decoder 30 may perform implementations of the present application. Also, in some examples, implementations of the present disclosure may be divided among one or more of the units of video decoder 30. For example, intra BC unit 85 may perform implementations of the present application alone or in combination with other units of video decoder 30, such as motion compensation unit 82, intra prediction unit 84, and entropy decoding unit 80. In some examples, video decoder 30 may not include intra BC unit 85, and the functions of intra BC unit 85 may be performed by other components of prediction processing unit 81, such as motion compensation unit 82.

[0278]

[0245] Video data memory 79 is used to store data decoded by other components of video decoder 30. The video data memory 79 may store video data, such as an encoded video bitstream, to be decoded. The video data stored in the video data memory 79 may be obtained, for example, from storage device 32, from a local video source such as a camera, via wired or wireless network communication of the video data, or by accessing a physical data storage medium (e.g., a flash drive or hard disk). The video data memory 79 may include a coded picture buffer (CPB) that stores coded video data from the coded video bitstream. The DPB 92 of the video decoder 30 stores reference video data for use in decoding the video data by the video decoder 30 (e.g., in intra- or inter-prediction coding mode). The video data memory 79 and the DPB 92 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. For illustrative purposes, the video data memory 79 and the DPB 92 are shown in FIG. 15 as two separate components of the video decoder 30. However, it will be apparent to those skilled in the art that video data memory 79 and DPB 92 may be provided by the same memory device or separate memory devices. In some examples, video data memory 79 may be on-chip with other components of video decoder 30 or off-chip with respect to those components.

[0279]

[0246] During the decoding process, video decoder 30 decodes the video blocks of the encoded video frames. Video decoder 30 receives an encoded video bitstream representing a block and associated syntax elements. Video decoder 30 may receive the syntax elements at the video frame level and / or the video block level. Entropy decoding unit 80 of video decoder 30 entropy decodes the bitstream to generate quantized coefficients, motion vectors or intra-prediction mode indicators, and other syntax elements. Entropy decoding unit 80 then forwards the motion vectors or intra-prediction mode indicators and other syntax elements to prediction processing unit 81.

[0280]

[0247] When a video frame is coded as an intra-predictive (I) frame or other time If the video block is encoded as an intra-coded predictive block of the current frame, intra prediction unit 84 of prediction processing unit 81 may generate predictive data for the video block of the current video frame based on the signaled intra prediction mode and reference data from previously decoded blocks of the current frame.

[0281]

[0248] If a video frame is coded as an inter-predictive (i.e., B or P) frame, When encoded, motion compensation unit 82 of prediction processing unit 81 generates one or more prediction blocks for a video block of a current video frame based on the motion vectors and other syntax elements received from entropy decoding unit 80. Each of the prediction blocks may be generated from a reference frame in one of the reference frame lists. Video decoder 30 generates a differential prediction block based on the reference frames stored in DPB 92. The reference frame lists, List0 and List1, may be constructed using the default construction technique.

[0282]

[0249] In some examples, the video block may be in intra-BC mode as described herein. When a video block is encoded according to the ENCODE code, intra BC unit 85 of prediction processing unit 81 generates a predictive block for the current video block based on the block vectors and other syntax elements received from entropy decoding unit 80. The predictive block may be within the same reconstructed region of the picture as the current video block established by video encoder 20.

[0283]

[0250] The motion compensation unit 82 and / or the intra BC unit 85 The motion compensation unit 82 determines prediction information for video blocks of the current video frame by parsing the received syntax elements and other syntax elements, and then uses the prediction information to generate a predictive block for the current video block being decoded. For example, motion compensation unit 82 uses some of the received syntax elements to determine the prediction mode (e.g., intra-prediction or inter-prediction) used to encode the video blocks of the video frame, the inter-prediction frame type (e.g., B or P), structural information for one or more reference frame lists for the frame, the motion vectors for each inter-predictively coded video block of the frame, the inter-prediction status for each inter-predictively coded video block of the frame, and other information for decoding video blocks in the current video frame.

[0284] Similarly, the intra BC unit 85 may receive some of the syntax elements, e.g. For example, a flag may be used to determine that the current video block was predicted using intra BC mode, and configuration information of the video blocks of the frame is in the reconstruction domain and should be stored in DPB92, block vectors of each intra BC predicted video block of the frame, intra BC prediction status of each intra BC predicted video block of the frame, and other information for decoding video blocks in the current video frame.

[0285]

[0252] Motion compensation unit 82 also performs the following functions on the video encoder during the encoding of a video block: The motion compensation unit 82 may also perform the interpolation using an interpolation filter used by video encoder 20 to calculate interpolated values for sub-integer pixels of the reference block. In this case, motion compensation unit 82 may determine the interpolation filter used by video encoder 20 from the received syntax elements and use that interpolation filter to generate the predictive block.

[0286]

[0253] Inverse quantization unit 86 performs inverse quantization on the video frames to determine the degree of quantization. 1. Inverse transform processing unit 88 applies an inverse transform, e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients in order to reconstruct the residual block in the pixel domain.

[0287]

[0254] The motion compensation unit 82 or the intra BC unit 85 processes vectors and other After generating the predictive block for the current video block based on the syntax elements, summer 90 reconstructs a decoded video block for the current video block by adding the residual block from inverse transform processing unit 88 and the corresponding predictive block generated by motion compensation unit 82 and intra BC unit 85. An in-loop filter 91, such as a deblocking filter, an SAO filter, and / or an ALF, may be disposed between summer 90 and DPB 92 to further process the decoded video block. In some examples, in-loop filter 91 may be omitted, and the decoded video block may be provided directly to DPB 92 by summer 90. The decoded video block in a given frame may then be further processed by summer 90. The decoded video blocks are stored in DPB 92, which stores reference frames used for subsequent motion compensation of the next video block. DPB 92, or a memory device separate from DPB 92, may also store decoded video for later display on a display device, such as display device 34 of FIG. 13.

[0288]

[0255] The description in this disclosure is presented for illustrative purposes only and is not intended to be exhaustive. It is not intended to be limiting or limiting to the present disclosure. Many modifications, variations and alternative implementations will become apparent to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

[0289]

[0256] The examples illustrate the principles of the present disclosure and allow others skilled in the art to readily understand the principles of the present disclosure in various implementations. The underlying principles and various implementations have been chosen and described to best utilize them with various modifications as suited to the particular use contemplated, to facilitate understanding of the present disclosure. Therefore, it should be understood that the scope of the disclosure is not limited to the particular examples of implementations disclosed, and that modifications and other implementations are also intended to be included within the scope of the disclosure.

Claims

1. 1. A method for video decoding, comprising: A method comprising receiving, by a decoder, an enable flag for the inverted coordinate of the last significant coefficient of a sequence parameter set (SPS), the enable flag indicating whether the enable flag for the inverted coordinate of the last significant coefficient of the slice header (SH) is present in a slice header syntax structure that references the SPS.

2. In response to determining that a value of an enable flag for a flipped coordinate of a last significant coefficient of the SPS is equal to 1, determining by the decoder that an enable flag for a flipped coordinate of a last significant coefficient of the SH is present in the slice header syntax structure referencing the SPS; 2. The method for video decoding of claim 1, further comprising: in response to determining that the value of an enable flag for a flipped coordinate of a last significant coefficient of the SPS is equal to 0, determining, by the decoder, that an enable flag for a flipped coordinate of a last significant coefficient of the SH is not present in a slice header syntax structure that references the SPS.

3. 2. The method for video decoding of claim 1, further comprising adding, by the decoder, an enable flag of the flip coordinate of the last significant coefficient to a general constraint information syntax to provide general control of the enable flag of the flip coordinate of the last significant coefficient of the SPS.

4. 4. The method for video decoding of claim 3, further comprising: determining, in response to determining that a value of an enable flag of a flipped coordinate of a final significant coefficient of the SPS is equal to 1, that a value of an enable flag of a flipped coordinate of a final significant coefficient of the SPS is equal to 0.

5. 1. A method for video decoding, comprising receiving, by a decoder, a sequence parameter set (SPS) transform precision adaptation enable flag that indicates whether scaling of transform coefficients and downshifting in a transformation process of scaled transform coefficients are adaptively assigned by examining coefficient values of inverse quantization and inverse transformation.

6. 6. The method for video decoding of claim 5, further comprising: determining, by the decoder, in response to determining that a value of the SPS transform precision adaptation enable flag is equal to 1, that the downshift in the scaling process of the transform coefficients and the transformation process of the scaled transform coefficients is adaptively assigned by examining the coefficient values of inverse quantization and inverse transform.

7. 6. The method for video decoding of claim 5, further comprising adding, by the decoder, a transform precision adaptation enable flag to a general constraint information syntax to provide general control of the SPS transform precision adaptation enable flag.

8. 8. The method for video decoding of claim 7, further comprising: in response to determining that the value of the transform precision adaptation enable flag is equal to one, determining that the value of the SPS transform precision adaptation enable flag is equal to zero.

9. 1. A method for video decoding, comprising: receiving, by the decoder, a sequence parameter set (SPS) high throughput flag indicating whether a syntax element in the residual coding is coded via bypass mode; determining, by the decoder, in response to determining that the value of the SPS high-throughput flag is equal to one, that all syntax elements in the residual coding are coded in the bypass mode except for a last significant coefficient position in normal residual coding (RRC), and that alignment is performed after the last significant coefficient position in RRC and at the beginning of a transform block (TB) in transform-skip residual coding (TSRC); A method comprising:

10. 10. The method for video decoding of claim 9, further comprising adding, by the decoder, a high-throughput flag to a general constraint information syntax to provide general control of the SPS high-throughput flag.

11. 11. The method for video decoding of claim 10, further comprising the step of determining, in response to determining that the value of the high throughput flag is equal to one, that the value of the SPS high throughput flag is equal to zero.

12. one or more processors; a memory configured to store instructions executable by the one or more processors; 12. An apparatus for video decoding, wherein the one or more processors are configured, upon execution of the instructions, to perform the method of any one of claims 1 to 11.

13. 1. A non-transitory computer-readable storage medium for video decoding that stores computer-executable instructions, comprising:

12. A non-transitory computer-readable storage medium, the instructions, when executed by one or more computer processors, causing the one or more computer processors to perform the method of any one of claims 1 to 11.

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