Exposure head

Abstract

To form a driving circuit by a semiconductor process of a low withstand voltage, and reduce a chip size, while securing a forward voltage of a light-emitting element, in such a structure that the light-emitting element and the driving circuit are formed in one chip.SOLUTION: An exposure head 106 includes: a printed circuit board 202; a plurality of light-emitting element array chips 400-1 to 400-20 which include a plurality of light-emitting elements 602 for emitting light, and an analog part 801 for driving the light-emitting elements 602, are arranged on the printed circuit board 202 and have strip shapes; and a rod lens array 203 for condensing the light from the light-emitting elements 602 on a photosensitive drum 102. The analog part 801 is operated between a first potential and a second potential, and the light-emitting element 602 is operated between a third potential and a fourth potential. A potential difference between the third potential and the fourth potential is equal to or more than a potential difference between the first potential and the second potential.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to an exposure head that exposes a photosensitive drum and an image forming apparatus equipped with the same. [Background technology]

[0002] Conventionally, electrophotographic printers generally employ an exposure head that uses LEDs or organic electroluminescence (EL) to expose a photosensitive drum to light to form a latent image. Such an exposure head is composed of a row of light-emitting elements arranged in the longitudinal direction of the photosensitive drum and a rod lens array that focuses light from the row of light-emitting elements onto the photosensitive drum. The LEDs or organic EL elements are light-emitting element arrays in which the direction of light emitted from the light-emitting surface is parallel to the optical axis of the rod lens array.

[0003] In the exposure head, the length of the light-emitting element array is determined by the width of the image formation area on the photosensitive drum, and the spacing between the light-emitting elements is determined by the image resolution of the printer. For example, in a 1200 dpi printer, the pixel spacing is 21.16 μm (omitted from the third decimal point), so the spacing between the light-emitting elements is also 21.16 μm. Printers using such exposure heads use fewer parts than laser scanning printers that deflect and scan a laser beam using a polygon motor, making it easier to make the device smaller and less expensive.

[0004] Recently, a technology has been developed to reduce the size of devices by mounting light-emitting elements and drive circuits on the same chip. For example, an exposure head is known in which a drive integrated circuit and electrodes are formed on a silicon substrate, and an organic electroluminescent (EL) film is vapor-deposited thereon, thereby integrating the light-emitting elements and drive circuit into a single chip. Patent Document 1 discloses an exposure head in which a TFT circuit and an organic EL are mounted on a transparent glass substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-112856 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in conventional exposure heads that integrate the light emitting elements and the drive circuitry into a single chip, it is necessary to form the integrated circuit using a semiconductor process with a relatively high withstand voltage in order to ensure the forward voltage of the light emitting elements and obtain a predetermined amount of light emission. When the drive circuitry is formed using such a semiconductor process with a high withstand voltage, the size of the transistors becomes large, which results in an increase in the chip size.

[0007] An object of the present invention is to provide an exposure head in which a light-emitting element and a drive circuit are formed on a single chip, in which the drive circuit can be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element, thereby enabling the chip size to be reduced. [Means for solving the problem]

[0008] The exposure head of the present invention is an exposure head that exposes a photosensitive drum, and comprises a substrate, a plurality of light-emitting elements that emit light, and a drive circuit that drives the light-emitting elements, and is characterized in that it has a plurality of strip-shaped semiconductor chips arranged on the substrate, and a lens array that focuses light from the light-emitting elements onto the photosensitive drum, the drive circuit operates between a first potential and a second potential, the light-emitting elements operate between a third potential and a fourth potential, and the potential difference between the third potential and the fourth potential is greater than or equal to the potential difference between the first potential and the second potential. [Effects of the Invention]

[0009] According to the present invention, in a configuration in which a light-emitting element and a drive circuit are formed on a single chip, the drive circuit can be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light-emitting element, thereby making it possible to reduce the chip size. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of an image forming apparatus according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram of an exposure head and a photosensitive drum according to the first embodiment of the present invention. [Figure 3] 1 is a schematic diagram showing the configuration of an exposure head according to a first embodiment of the present invention. [Figure 4] 2 is a schematic diagram of a light-emitting element array chip of the exposure head according to the first embodiment of the present invention. FIG. [Figure 5] 5 is a cross-sectional view taken along the line AA in FIG. 4. [Figure 6] 2 is a schematic diagram showing the arrangement of light-emitting elements in a light-emitting element array chip of the exposure head according to the first embodiment of the present invention. FIG. [Figure 7] 5A and 5B are schematic diagrams showing modified examples of the arrangement of light-emitting elements in the light-emitting element array chip of the exposure head according to the first embodiment of the present invention. [Figure 8] 2 is a plan view showing the positional relationship between the light-emitting units and rod lenses of the exposure head according to the first embodiment of the present invention. FIG. [Figure 9] 1 is a block diagram showing a configuration of an exposure head according to a first embodiment of the present invention. [Figure 10] 1 is a block diagram showing the configuration of a light-emitting element array chip of an exposure head according to a first embodiment of the present invention. [Figure 11] 3 is a circuit configuration diagram of a data holding unit of the light-emitting element array chip of the exposure head according to the first embodiment of the present invention. FIG. [Figure 12] FIG. 2 is a block diagram showing the configuration of an analog section of the exposure head according to the first embodiment of the present invention. [Figure 13] 3 is a block diagram showing the configuration of a power supply section that supplies power to an exposure head according to the first embodiment of the present invention. FIG. [Figure 14] FIG. 4 is a flowchart of the operation of the exposure head according to the first embodiment of the present invention. [Figure 15]4 is a timing chart of the power supply voltage supplied to the light-emitting element array chip of the exposure head according to the first embodiment of the present invention. [Figure 16] 4 is a timing chart of the light emitting element array chip of the exposure head according to the first embodiment of the present invention. [Figure 17] FIG. 10 is a block diagram showing the configuration of a light-emitting element array chip of an exposure head according to a second embodiment of the present invention. [Figure 18] FIG. 10 is a block diagram showing the configuration of an analog section of an exposure head according to a second embodiment of the present invention. [Figure 19] FIG. 10 is a block diagram showing the configuration of a power supply section that supplies power to an exposure head according to a second embodiment of the present invention. [Figure 20] FIG. 10 is a flowchart showing the operation of the exposure head according to the second embodiment of the present invention. [Figure 21] 10 is a timing chart of the power supply voltage supplied to the light emitting element array chip of the exposure head according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0012] (Embodiment 1) <Configuration of image forming device> The configuration of an image forming apparatus 1 according to the first embodiment of the present invention will be described in detail with reference to FIG.

[0013] The image forming apparatus 1 includes a scanner unit 100, an image creating unit 103, a fixing unit 104, a paper feeding / conveying unit 105, and a registration roller 110.

[0014] The scanner unit 100 illuminates a document placed on a document table, optically reads the image of the document, converts the read image into an electrical signal, and creates image data. The scanner unit 100 outputs the created image data to a printer control unit (not shown).

[0015] The image forming unit 103 operates under the control of the printer control unit, forms an image on a sheet conveyed by the registration rollers 110, and conveys the sheet with the image formed to the fixing unit 104. The image forming unit 103 has four image forming units that perform a series of electrophotographic processes including charging, exposure, development, and transfer. The image forming unit 103 forms a full-color image on the sheet using the four image forming units arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K). Each of the four image forming units sequentially performs magenta, yellow, and black image forming operations after a predetermined time has elapsed since the start of cyan image formation.

[0016] Specifically, the image forming unit 103 includes a photosensitive drum 102 , an exposure head 106 , a charger 107 , a developing unit 108 , a transfer belt 111 , and an optical sensor 113 .

[0017] A photosensitive drum 102 serving as an image carrier is attached to the image forming apparatus 1 by a mounting member (not shown) and is driven to rotate.

[0018] The exposure head 106 is attached to the image forming apparatus 1 by an attachment member (not shown). The exposure head 106 is composed of four exposure heads 106a, 106b, 106c, and 106d corresponding to the four imaging units. The exposure head 106 forms a latent image (electrostatic latent image) on the photosensitive drum 102 by concentrating and exposing the photosensitive drum 102 with light emitted in accordance with image data. The configuration of the exposure head 106 will be described in detail later.

[0019] The charger 107 charges the photosensitive drum 102 .

[0020] The developing device 108 supplies toner to the latent image formed on the photosensitive drum 102 to develop it, thereby forming a toner image (developer image) on the photosensitive drum 102.

[0021] The transfer belt 111 transports the sheet transported by the registration rollers 110 to the fixing unit 104. A toner image developed by the developing unit 108 is transferred onto the sheet transported by the transfer belt 111.

[0022] An optical sensor 113 is provided opposite the transfer belt 111 and detects the position of a test chart printed on the transfer belt 111 in order to derive the amount of color misregistration between each of the imaging units. The optical sensor 113 outputs the detection result of the test chart position to an image controller (not shown). Based on the detection result of the test chart position input from the optical sensor 113, the image controller derives the amount of color misregistration between each of the imaging units of the image forming unit 103 and performs control to correct the image position of each color. This control allows a full-color toner image without color misregistration to be transferred onto the sheet.

[0023] Fixing unit 104 is made up of a combination of rollers and has a built-in heat source such as a halogen heater (not shown). Fixing unit 104 melts and fixes the toner on the sheet onto which the toner image has been transferred by imaging unit 103 using heat and pressure, and discharges the sheet with the fixed toner outside image forming apparatus 1 using paper discharge rollers 112.

[0024] The paper feed / transport section 105 includes an internal paper feed unit 109a, an internal paper feed unit 109b, an external paper feed unit 109c, and a manual paper feed unit 109d, and feeds a sheet from a pre-specified paper feed unit and transports it to the registration rollers 110.

[0025] The registration rollers 110 convey the sheet conveyed by the paper feed / conveyance unit 105 to the transfer belt 111 at the timing when the toner image formed in the image creation unit 103 is transferred onto the sheet.

[0026] The printer control unit controls the operations of scanner unit 100, image creating unit 103, fixing unit 104, and paper feed / transport unit 105. The printer control unit communicates with an MFP control unit that controls the entire MFP (entire image forming apparatus 1), and controls the operations while managing the states of scanner unit 100, image creating unit 103, fixing unit 104, and paper feed / transport unit 105 in accordance with instructions from the MFP control unit.

[0027] <Exposure head configuration> The configuration of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIGS.

[0028] Figure 2(a) shows the arrangement of the exposure head 106 relative to the photosensitive drum 102, and Figure 2(b) shows how light emitted from the light-emitting element group 201 is focused on the photosensitive drum 102 by the rod lens array 203.

[0029] Fig. 3(a) shows the surface of the printed circuit board 202 opposite to the surface on which the light-emitting element group 201 is mounted (hereinafter referred to as the "light-emitting element non-mounted surface"), and Fig. 3(b) shows the surface on which the light-emitting element group 201 is mounted (hereinafter referred to as the "light-emitting element mounted surface"). Fig. 3(c) shows the state of the boundary between the light-emitting element array chips 400-m (m is an integer of 1 to 19).

[0030] The exposure head 106 includes a group of light-emitting elements 201 , a printed circuit board 202 , a rod lens array 203 , and a housing 204 .

[0031] The light emitting element group 201 is mounted on the light emitting element mounting surface of the printed circuit board 202, and has a configuration in which 20 strip-shaped light emitting element array chips 400-1 to 400-20 are arranged in two staggered rows. The light emitting element array chips 400-1 to 400-20 in each row are arranged along the longitudinal direction of the printed circuit board 202.

[0032] In the light emitting element array chips 400-1 to 400-20 serving as semiconductor chips, light emitting elements 602 are arranged at a predetermined pitch along the longitudinal direction (main scanning direction) and lateral direction (sub-scanning direction) of the light emitting element array chips 400-1 to 400-20. In each of the light emitting element array chips 400-1 to 400-20, 748 light emitting elements 602 are arranged at a predetermined image resolution pitch in the X direction, which is the longitudinal direction. In this example, the image resolution pitch is 1200 dpi (approximately 21.16 μm). In this example, the distance from one end to the other of the 748 light emitting elements 602 in each of the light emitting element array chips 400-1 to 400-20 is approximately 15.8 mm.

[0033] The light emitting element group 201 has 20 light emitting element array chips 400-1 to 400-20 arranged in the longitudinal direction, so that the number of light emitting elements capable of exposure is 14960 elements, enabling image formation corresponding to an image width of approximately 316 mm.

[0034] In this example, the image resolution pitch between the light emitting elements 602-n and 602-1 located at the boundary of the light emitting element array chips 400-1 to 400-20 shown in FIG. 3(c) is also 1200 dpi (approximately 21.16 μm). The distance S between the light emitting elements 602-n and 602-1 in the short direction is approximately 127 μm (equivalent to six pixels at 1200 dpi and four pixels at 800 dpi). The distance L between the light emitting elements 602-n and 602-1 in the long direction is approximately 21.16 μm (equivalent to one pixel at 1200 dpi). The distances S and L between the light emitting elements 602-n and 602-1 are not limited to the values described above.

[0035] As shown in Fig. 3(a), the printed circuit board 202 serving as a substrate is provided with a connector 305 on a surface on which light-emitting elements are not mounted and a driver IC (not shown) for driving the light-emitting element group 201. As shown in Fig. 3(b), the printed circuit board 202 has the light-emitting element group 201 mounted on a light-emitting element mounting surface serving as a front surface.

[0036] The connector 305 is connected to a driver IC and a power supply (not shown) provided on the surface of the printed circuit board 202 where no light emitting elements are mounted, via signal lines (not shown), and is also connected to the light emitting element group 201 .

[0037] The rod lens array 203 is arranged so that the distance between it and the light-emitting element group 201 is a predetermined distance, and is also arranged so that the distance between it and the photosensitive drum 102 is a predetermined distance, and the light emitted from the light-emitting element group 201 is imaged on the photosensitive drum 102.

[0038] A rod lens array 203 and a printed circuit board 202 are attached to the housing 204 .

[0039] The exposure head 106 having the above configuration is assembled individually in a factory, and is subjected to focus adjustment, which adjusts the spot at the light-condensing position to a predetermined size, and light intensity adjustment. Here, focus adjustment involves adjusting the mounting position of the rod lens array 203 so that the distance between the rod lens array 203 and the light-emitting element group 201 is the desired distance. Furthermore, light intensity adjustment involves sequentially causing each light-emitting element 602 in the light-emitting element group 201 to emit light individually, and adjusting the drive current of each light-emitting element 602 so that the light condensed on the photosensitive drum 102 via the rod lens array 203 has a predetermined light intensity.

[0040] <Configuration of light-emitting element array chip> The configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIG.

[0041] The light-emitting element array chip 400 is a chip configured by providing light-emitting elements 602 on a Si substrate, and includes a light-emitting substrate 402, a light-emitting section 404, a circuit section 406, and wire bonding pads (WB pads) 408.

[0042] The light emitting substrate 402 is a Si substrate, and is provided with a light emitting section 404 and wire bonding pads 408. The light emitting substrate 402 has a built-in circuit section 406 for controlling the light emitting section 404. Here, Si substrates have been developed with advanced process technology for forming integrated circuits, and are already used as substrates for various integrated circuits. Therefore, they have the advantage of being able to form high-speed, highly functional circuits at high density, and being inexpensively available due to the availability of large-diameter wafers.

[0043] The light emitting section 404 includes a light emitting element 602. The configuration of the light emitting section 404 will be described in detail later.

[0044] The circuit section 406 has a circuit configuration including an analog drive circuit, a digital control circuit, or both an analog drive circuit and a digital drive circuit, and controls the light emitting section 404 .

[0045] The wire bonding pads 408 supply power to the circuit section 406 and input and output signals between the light emitting element array chip 400 and the outside.

[0046] <Configuration of the light-emitting unit> The configuration of the light emitting units 404 of the light emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIG.

[0047] The light-emitting section 404 is the portion where the light-emitting substrate 402 and the upper electrode 508 face each other, and the light-emitting layer 506 in the facing portion, and is configured by stacking multiple lower electrodes 504, light-emitting layers 506, and upper electrodes 508 in this order on the light-emitting substrate 402.

[0048] The lower electrode 504 is an independent electrode and is formed on the light emitting substrate 402. The lower electrode 504 has a width W in the X direction, and a plurality of lower electrodes 504 are formed with a predetermined distance d between adjacent lower electrodes 504 in the X direction. The lower electrodes 504 are formed together with the circuit section 406 using Si integrated circuit processing technology with a high precision processing rule of about 0.2 μm, and are connected to a drive section (not shown) of the circuit section 406. This allows the lower electrodes 504 to be arranged with high precision and high density, and since the light emitting portions of the light emitting elements 602 are substantially the same as the lower electrodes 504, it is possible to arrange the light emitting elements 602 with high density.

[0049] The lower electrode 504 is preferably formed from a metal having a high reflectivity at the wavelength of light emitted from the light emitting layer 506, such as silver (Ag), aluminum (Al), or an alloy of silver and aluminum.

[0050] The light-emitting layer 506 is formed on the lower electrode 504 and is, for example, an organic EL film or an inorganic EL film. When the light-emitting layer 506 is an organic EL film, it is a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer as necessary.

[0051] When the light-emitting layer 506 is formed of a material that is susceptible to moisture, such as an organic EL layer or an inorganic EL layer, it is desirable that the light-emitting layer 506 be sealed to prevent moisture from entering the light-emitting section 404. The light-emitting layer 506 is prevented from entering the light-emitting section 404 by a sealing film formed, for example, of a single thin film of silicon oxide, silicon nitride, aluminum oxide, or the like, or by laminating thin films of silicon oxide, silicon nitride, and aluminum oxide, or the like. A method that is excellent in covering structures such as steps is preferable as a method for forming the sealing film, and for example, atomic layer deposition (ALD) or the like can be used.

[0052] The light-emitting layer 506 may be formed continuously or may be divided into pieces of approximately the same size as the lower electrode 504. The material, configuration, and formation method of the sealing film described above are merely examples, and are not limited to the above examples, and any suitable material may be selected as appropriate.

[0053] The upper electrode 508 is a common electrode and is formed on the light-emitting layer 506. The upper electrode 508 is preferably transparent to the emission wavelength of the light-emitting layer 506, and a transparent electrode such as indium tin oxide (ITO) can be used.

[0054] The light-emitting unit 404 having the above configuration applies a current to the light-emitting layer 506 through a selected lower electrode 504 from the plurality of lower electrodes 504 and the upper electrode 508, thereby causing the light-emitting layer 506 to emit light at a location corresponding to the selected lower electrode 504. As a result, the light-emitting unit 404 emits light through the upper electrode 508 on the side of the light-emitting layer 506 opposite the light-emitting substrate 402.

[0055] By using a transparent electrode such as indium tin oxide for the upper electrode 508, the aperture ratio can be made substantially 100%, and light emitted from the light-emitting layer 506 can be used as emitted light as is. Furthermore, by forming the lower electrodes 504 using high-precision Si integrated circuit processing technology, the lower electrodes 504 can be arranged at high density, which allows almost the entire area of the light-emitting portion 404 to emit light, thereby improving the utilization efficiency of the light-emitting portion 404. Here, the area of the light-emitting portion 404 is the total area of the plurality of lower electrodes 504 and the total area of the plurality of intervals d.

[0056] <Arrangement of light-emitting elements in the light-emitting section> The arrangement of the light emitting elements 602 of the light emitting section 404 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIGS.

[0057] 6, Fig. 6(a) is an example in which a plurality of light-emitting elements 602 are arranged in a row, and Fig. 6(b) is a schematic cross-sectional view of a light-emitting element row 604. Fig. 7 is an example in which a light-emitting unit 404 is configured by arranging a plurality of light-emitting element rows 604 in the Y direction of the figure.

[0058] 6(a) and 6(b), W1 is the width of the light-emitting element 602 in the X direction, and d1 is the distance between adjacent light-emitting elements 602 in the X direction. Also, in Fig. 7, W2 is the width of the light-emitting element 602 in the Y direction, and d2 is the distance between adjacent light-emitting elements 602 in the Y direction.

[0059] In FIG. 6(b), for example, the light emitting element 602-3 is the part surrounded by the dashed line.

[0060] The light emitting element row 604 is configured by arranging a plurality of light emitting elements 602 at a predetermined interval (pitch) along the X direction. For example, the predetermined interval is 21.16 μm when the image resolution in the Y direction is 1200 dpi. In addition, W1 is exemplified as 19.8 μm, and d1 is exemplified as 0.68 μm.

[0061] Here, if the light-emitting layer 506 is sufficiently thin, the light-emitting location of the light-emitting element 602 is substantially the same as the lower electrode 504, and W1 can be regarded as W in FIG. 5, and d1 as d in FIG.

[0062] The light emitting element row 604 is not limited to a single row in which the light emitting elements 602 are arranged in the X direction as shown in Fig. 6(a), but may also be multiple rows in which the light emitting elements 602 are arranged in the Y direction as shown in Fig. 7. Fig. 7 illustrates a case in which 748 light emitting elements 602 (602-1 to 4_1 to 748) are arranged in the X direction and four rows (604-1 to 4) are arranged in a matrix in the Y direction, which is different from the X direction. W2 is illustrated as 19.8 µm, the same as W1. d2 is illustrated as 0.68 µm, the same as d1, and the light emitting elements are arranged at a pitch of 21.16 µm (1200 dpi) in the Y direction.

[0063] The rod lens array 203 focuses light emitted from the light-emitting element group 201 onto the photosensitive drum 102. The number of light-emitting element rows 604 in the Y direction is shown as four in this example. The pitch of the light-emitting elements 602 in the X direction is shown as 21.16 μm in this example, as shown in FIG. 8. The pitch of the light-emitting elements 602 in the Y direction is shown as 21.16 μm in this example, as shown in FIG. 8. The diameter of the rod lens array 203 is shown as 290 μm in this example, as shown in FIG. 8. In this example, one rod lens array 203 focuses light emitted from a plurality of light-emitting elements 602.

[0064] <Exposure head circuit configuration> The circuit configuration of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIG.

[0065] 9, for the sake of simplicity, the circuit configuration of one single-color exposure head 106 will be described, but in reality, each of the four exposure heads 106 for four colors has the same circuit configuration. Furthermore, these four exposure heads 106 perform parallel processing simultaneously.

[0066] The exposure head 106 has an image controller unit 700 that transmits signals or data for controlling the printed circuit board 202 to the printed circuit board 202 and performs processing on image data and processing on exposure timing. The signals and data transmitted from the image controller unit 700 to the printed circuit board 202 are a clock signal, image data, a signal indicating the start of image data capture (hereinafter referred to as a "line synchronization signal"), and a communication signal.

[0067] Specifically, the image controller unit 700 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a -5V generation circuit 711, and a switch (SW) 714.

[0068] The image controller unit 700 and the printed circuit board 202 are connected by a clock signal line 705 , a line synchronization signal line 706 , an image data signal line 707 , a communication signal line 708 , a +5V power line 712 and a −5V power line 713 .

[0069] The clock signal line 705 connects the chip data conversion unit 702 to each of the light-emitting element array chips 400-1 to 400-20.

[0070] The line synchronization signal line 706 connects only the chip data conversion unit 702 and the light-emitting element array chip 400-1.

[0071] The image data signal lines 707 connect the chip data converter 702 to each of the light emitting element array chips 400-1 to 400-20. The number of image data signal lines 707 is shown as four, which is the same as the number of light emitting element columns 604.

[0072] A communication signal line 708 connects the CPU 703 to each of the light-emitting element array chips 400-1 to 400-20.

[0073] The +5V power supply line 712 connects the +5V generation circuit 710 to each of the light-emitting element array chips 400-1 to 400-20.

[0074] The −5V power supply line 713 connects the switch (SW) 714 to each of the light-emitting element array chips 400-1 to 400-20.

[0075] The image data generation unit 701 performs dithering processing at an image resolution instructed by the CPU 703 on image data input from the scanner unit 100 or received from outside the image forming apparatus 1 to generate image data for print output. The image data generation unit 701 performs dithering processing at an image resolution of 1200 dpi in each of the main scanning direction and the sub-scanning direction, for example, to generate image data of 1 line x 4 columns (number of light emitting element columns). The image data generation unit 701 outputs the generated image data to the chip data conversion unit 702.

[0076] The chip data conversion unit 702 divides the image data input from the image data generation unit 701 for each of the light-emitting element array chips 400-1 to 400-20 in synchronization with a line synchronization signal input from a synchronization signal generation unit 704. The chip data conversion unit 702 outputs the divided image data to each of the light-emitting element array chips 400-1 to 400-20 via an image data signal line 707. At the same time, the chip data conversion unit 702 outputs a line synchronization signal to the light-emitting element array chip 400-1 via a line synchronization signal line 706, and outputs a clock signal to the light-emitting element array chips 400-1 to 400-20 via a clock signal line 705.

[0077] The CPU 703 defines one line period as a period during which the surface of the photosensitive drum 102 moves by a predetermined pixel size in the rotation direction at a predetermined rotation speed of the photosensitive drum 102, and instructs the synchronization signal generating unit 704 on the time interval of the signal period.

[0078] For example, the CPU 703 defines one line period as the period during which the surface of the photosensitive drum 102 moves a pixel size of 1200 dpi (approximately 21.16 μm) in the rotation direction at a predetermined rotation speed of the photosensitive drum 102. When exposure is performed at a speed of 200 mm / sec in the transport direction, the CPU 703 specifies the time interval of the signal period as 105.8 μsec (two decimal points and below omitted) for one line period to the synchronization signal generator 704. At this time, the CPU 703 calculates the speed in the transport direction using a setting value (fixed value) of the printing speed set in a speed controller (not shown) that controls the speed of the photosensitive drum 102.

[0079] The CPU 703 instructs the image resolution to the image data generation unit 701. The CPU 703 outputs a power control signal to the switch 714 to turn on the switch 714. The CPU 703 transmits and receives communication signals to and from each of the light-emitting element array chips 400-1 to 400-20 via a communication signal line 708. The CPU 703 sets a setting value in the communication signal based on head information, etc., which will be described later, stored in a head information storage unit 709, and outputs the communication signal with the setting value set to the light-emitting element array chips 400-1 to 400-20 via the communication signal line 708.

[0080] The synchronization signal generation unit 704 generates a line synchronization signal based on the time interval of the signal cycle instructed by the CPU 703 , and outputs the generated line synchronization signal to the chip data conversion unit 702 .

[0081] The +5V generation circuit 710 converts the +12V power supply voltage applied from the +12V power supply into a +5V voltage and supplies it to each of the light-emitting element array chips 400-1 to 400-20 via a +5V power supply line 712. A general switching regulator circuit can be used as the +5V generation circuit 710.

[0082] The −5V generation circuit 711 converts the +12V power supply voltage applied from the +12V power supply into a −5V voltage and supplies it to the switch 714. As the −5V generation circuit 711, a general switching regulator circuit can be used.

[0083] A switch 714 as a switching element is turned on or off depending on whether a power supply control signal is input from the CPU 703, thereby switching whether or not a voltage of −5 V is supplied to the light-emitting element array chips 400. The switch 714 is turned on when a power supply control signal is input from the CPU 703, and supplies a voltage of −5 V to each of the light-emitting element array chips 400-1 to 400-20 via a −5 V power supply line 713. The −5 V power supply line 713 is in a floating state when the switch 714 is turned off and the voltage of −5 V is not supplied to the light-emitting element array chips 400-1 to 400-20.

[0084] The printed circuit board 202 includes light-emitting element array chips 400-1 to 400-20 and a head information storage unit 709.

[0085] The light-emitting element array chip 400-1 and the light-emitting element array chip 400-2 are connected by a signal line 708-1. The light-emitting element array chip 400-2 and the light-emitting element array chip 400-3 are connected by a signal line 708-2. Similarly, the light-emitting element array chips 400-3, etc. are connected in a daisy chain by signal lines 708-3, etc.

[0086] Each of the light-emitting element array chips 400-1 to 400-20 generates a line synchronization signal for the next chip based on the input line synchronization signal and outputs it to the next light-emitting element array chip 400-1 to 400-20 via signal lines 708-1, .... Each of the light-emitting element array chips 400-1 to 400-20 causes the light-emitting element 602 to emit light based on the setting values set in the input clock signal, line synchronization signal, image data, and communication signal.

[0087] The head information storage unit 709 is connected to the CPU 703 via a communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the light emission amount and mounting position information of the light emitting element array chips 400-1 to 400-20.

[0088] <Circuit configuration of light-emitting element array chip> The circuit configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIGS.

[0089] Since the light-emitting element array chips 400-1 to 400-20 have the same circuit configuration, only the circuit configuration of the light-emitting element array chip 400-1 will be described, and descriptions of the circuit configurations of the light-emitting element array chips 400-2 to 400-20 will be omitted. Also, since the clock signal is input to all blocks of the digital unit 800, the clock signal line 705 is connected to all blocks of the digital unit 800, but this is not shown in FIG.

[0090] The light emitting element array chip 400-1 includes a light emitting section 404 and a circuit section 406. The circuit section 406 includes a digital section 800 and an analog section 801.

[0091] The digital unit 800 receives a clock signal, an image data signal, and a line synchronization signal from the chip data conversion unit 702, and also receives a communication signal from the CPU 703. The digital unit 800 generates a drive signal (pulse signal) for causing the light emitting element 602 to emit light based on the setting value set in the communication signal, the image data signal, and the line synchronization signal, in synchronization with the clock signal, and outputs the generated drive signal to the analog unit 801. The digital unit 800 generates a line synchronization signal for the next chip based on the line synchronization signal, and outputs the generated line synchronization signal for the next chip to the light emitting element array chip 400-2, which is the next chip, via a signal line 708-1.

[0092] Specifically, the digital section 800 includes a communication IF section 802, a register section 803, a line synchronization signal generation section 804, a capture signal generation section 805, and data holding sections 806-001 to 806-748.

[0093] The communication IF unit 802 is connected to the CPU 703 via a communication signal line 708 .

[0094] The register unit 803 writes a setting value set in a communication signal input from the CPU 703 via the communication IF unit 802. The register unit 803 reads the setting value written by the CPU 703, and outputs the read setting value to the analog unit 801 as drive current information and also outputs it as delay time information to the capture signal generation unit 805. Here, the drive current information is information on the current setting value of the drive current to be passed through the light emitting unit 404 and is a digital value. Moreover, the delay time information is information on the delay time for delaying the output of the data latch signal and is a digital value.

[0095] The line synchronization signal generation unit 804 delays the line synchronization signal input from the line synchronization signal line 706 by a predetermined time, generates a line synchronization signal for the next chip, and outputs it to the light-emitting element array chip 400-2 via a signal line 708-1.

[0096] Based on the line synchronization signal input from the line synchronization signal line 706, the capture signal generation unit 805 outputs a data latch signal we001 to the data holding unit 806-001 at a timing delayed by the delay time of the delay time information input from the register unit 803.

[0097] A clock signal and a data latch signal wen (n=1 to 748) are input to each of the data holding units 806-001 to 748, and image data 1 to 4 for four columns are input at the timing when the data latch signal wen is input.

[0098] 11, the data holding units 806-001 to 748 include four flip-flop circuits 807 and four gate circuits 808 that latch input image data 1 to 4, generate drive signals 1 to 4, and output them to the analog unit 801. Each of the data holding units 806-001 to 748 includes one flip-flop circuit 809 that delays the input data latch signal wen by one clock and outputs the delayed data latch signal we(n+1) to the next data holding unit 806-001 to 748.

[0099] The analog unit 801 controls the driving of the light emitting unit 404 based on the drive current information input from the register unit 803 and the drive signals input from the data holding units 806-001 to 806-748.

[0100] Specifically, the analog section 801 includes a drive circuit 900 that includes a current setting DAC 901, a current control MOSFET 902, and a switching MOSFET 903, as shown in FIG.

[0101] The drive circuits 900 are connected one-to-one to each light-emitting element 602, and are provided in the same number as the number of light-emitting elements 602. In this embodiment, 748 drive circuits x 4 columns = 2992 drive circuits 900 are provided for each light-emitting element array chip 400-1 to 400-20. Note that all drive circuits 900 have the same configuration, and therefore, for simplicity of explanation, only the configuration of one drive circuit 900 will be described.

[0102] The current setting DAC 901 converts the digital value of the drive current to be passed through the light emitting unit 404, which is indicated by the drive current information input from the register unit 803 of the digital unit 800, into an analog voltage and outputs it to the gate terminal G of the current control MOSFET 902.

[0103] The current control MOSFET 902 is a Pch MOSFET, with a source terminal S connected to a power supply voltage VDD, a gate terminal G connected to the output terminal of the DAC 901, and a drain terminal D connected to the source terminal S of the switching MOSFET 903. The current control MOSFET 902 is configured so that the drive current of the light emitting element 602 flowing from the source terminal S to the drain terminal D increases as the analog voltage input from the current setting DAC 901 increases.

[0104] The switching MOSFET 903 is a Pch MOSFET. The switching MOSFET 903 has a source terminal S connected to a drain terminal D of the current control MOSFET 902, a gate terminal G connected to an output terminal of the data holding unit 806, and a drain terminal D connected to an anode terminal A of the light emitting element 602 of the light emitting unit 404. The gate terminal G of the switching MOSFET 903 receives binary drive signals 1 to 4 of Hi level or Low level from the data holding units 806-001 to 806-748.

[0105] The switching MOSFET 903 is turned ON when a Hi-level drive signal is input to the gate terminal G, and is turned OFF when a Low-level drive signal is input to the gate terminal G. When a Hi-level drive signal is input to the gate terminal G and the switching MOSFET 903 is turned ON, a current flows from the source terminal S to the drain terminal D, which serves as a drive current for the light emitting element 602 controlled by the current control MOSFET 902.

[0106] Next, the power supply configuration for each of the digital section 800, the analog section 801, and the light emitting element 602 will be described in detail with reference to FIG.

[0107] In FIG. 13, for the sake of simplicity, the internal blocks of the digital section 800 are not shown, and only one drive circuit 900 and one light emitting element 602 are shown in the analog section 801.

[0108] A voltage of +5V is supplied to the digital section 800 from the +5V power supply line 712 as a power supply voltage. The digital section 800 is connected to GND (0V) as a reference potential. As a result, each block of the digital section 800 operates at a voltage between +5V and 0V. A voltage in the range of 0V to 5V is applied to the gate terminal of the switching MOSFET 903.

[0109] A voltage of +5V is supplied as a power supply voltage from the +5V power supply line 712 to the current setting DAC 901 of the analog section 801. The current setting DAC 901 is connected to GND (0V) as a reference potential. As a result, a voltage in the range of 0V to 5V is applied to the gate terminal of the current control MOSFET 902. In addition, a voltage of +5V is supplied as a power supply voltage from the +5V power supply line 712 to the source terminal of the current control MOSFET 902.

[0110] The light emitting element 602 is, for example, an organic EL element, and has an anode terminal A connected to the drain terminal of the switching MOSFET 903 and a cathode terminal K connected to the -5V power supply line 713. A voltage of -5V is supplied to the cathode terminal K of the light emitting element 602 from the -5V power supply line 713. A forward voltage of about 6V is generally generated in the light emitting element 602 by a drive current of several μA. In this case, the potential of the anode terminal A of the light emitting element 602 becomes about +1V, which is -5V plus +6V.

[0111] Since the drain-source voltages of the current control MOSFET 902 and the switching MOSFET 903 are each about 1.5 V, adding the drain-source voltage of 1.5 V × 2 = 3 V to the forward voltage of the light emitting element 602 of 6 V results in about 9 V. Therefore, the light emitting element array chips 400-1 to 400-20 require a voltage of about 9 V or more to cause the light emitting element 602 to emit light. The light emitting element array chips 400-1 to 400-20 can drive the light emitting element 602 in a 10 V range between +5 V and −5 V, and can therefore cause the light emitting element 602 to emit light.

[0112] In a conventional configuration in which an EL film is laminated on a circuit section by vapor deposition or the like, it was necessary to form a light-emitting element array chip using a semiconductor process of 9V or more, taking into consideration the drain-source voltage of the MOSFET, in order to ensure a forward voltage of 6V for the light-emitting element. In contrast, in this embodiment, +5V and -5V are supplied as power supply voltages to drive the light-emitting element 602 in the 10V range, and the digital section 800 and analog section 801 are configured using a semiconductor process from GND to +5V. As a result, in this embodiment, the sizes of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip sizes of the light-emitting element array chips 400-1 to 400-20 can be reduced.

[0113] <Exposure head operation> The operation of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIGS.

[0114] The exposure head 106 starts operating when the main power supply of the image forming apparatus 1 is turned on.

[0115] First, the CPU 703 determines whether or not a print job has been requested by the user (S1).

[0116] If a print job has not been requested by the user (S1: No), the CPU 703 repeats the operation of step S1.

[0117] On the other hand, when a print job is requested by the user (S1: Yes), the CPU 703 writes setting values into the register sections 803 of the light-emitting element array chips 400-1 to 400-20 to perform register setting (S2).

[0118] Next, the CPU 703 outputs a power supply control signal to the switch 714 to supply a voltage of −5 V to the cathode electrodes of the light emitting elements 602 of the light emitting element array chips 400-1 to 400-20 (−5 V ON) (S3).

[0119] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 400-1 to 400-20 at a predetermined timing, thereby exposing the photosensitive drum 102 (S4).

[0120] Next, the CPU 703 determines whether the print job is completed (S5).

[0121] If the print job is not completed (S5: No), the CPU 703 repeats the operation of step S5.

[0122] On the other hand, when the print job is completed (S5: Yes), the CPU 703 stops sending the power control signal to the switch 714, thereby putting the potential of the cathode electrode of the light emitting element 602 into a floating state and ending the operation.

[0123] Next, the operation of the exposure head 106 will be described in more detail with reference to FIG.

[0124] 15, at time t=t0, the power supply of image forming apparatus 1 is turned on, and a power supply voltage of +12V is supplied to +5V generation circuit 710 and -5V generation circuit 711. As a result, the voltage of +5V power supply line 712 becomes +5V after time t=t1 has elapsed. At this time, switch 714 is turned off, so -5V power supply line 713 is in a floating state (0V in FIG. 15).

[0125] At time t=t1, upon receiving a job request from the user, the CPU 703 outputs a power control signal to the switch 714, which sets the potential of the −5V power line 713 to −5V, thereby enabling the light emitting element 602 to be driven.

[0126] At time t=t2, the job ends, and the CPU 703 stops outputting the power control signal to the switch 714, turns off the switch 714, and sets the −5V power line 713 to a floating state (0V in FIG. 15).

[0127] <Operation of light-emitting element array chip> The operation of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail with reference to FIG.

[0128] Four columns of image data (D1[1] to D1[4]) are input simultaneously to the data holding unit 806-001. The data holding unit 806-001 latches the image data (D1[1] to D1[4]) when the data latch signal we001 is input from the capture signal generation unit 805, and generates drive signals (P001[1] to P001[4]).

[0129] Furthermore, the data holding unit 806-001 outputs the data latch signal we002, which is the input data latch signal we001 delayed by one clock, to the next data holding unit 806-002.

[0130] Like the data holding unit 806-001, the data holding unit 806-002 simultaneously receives four columns of image data (D2[1] to D2[4]). The data holding unit 806-002 latches the image data (D2[1] to D2[4]) when the data latch signal we002 is input from the data holding unit 806-001, and generates drive signals (P002[1] to P002[4]).

[0131] Furthermore, the data holding unit 806-002 outputs the data latch signal we003, which is the input data latch signal we002 delayed by one clock, to the next data holding unit 806-003.

[0132] In this way, the data holding units 806-001 to 748 sequentially latch the image data while sequentially outputting the data latch signals.

[0133] The data holding units 806-001 to 748 latch image data and output the latched signals as drive signals to the analog unit 801. The data holding units 806-001 to 748 latch image data for four columns with one data latch signal, and therefore output drive signals for four columns (four pixels) simultaneously.

[0134] In this configuration in which the light emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (-5V) lower than the voltage (+5V and reference potential (GND)) supplied to the analog unit 801 is supplied to the cathode electrode of the light emitting element 602. This allows the analog unit 801 to be formed using a semiconductor process with a relatively low withstand voltage, thereby reducing the size of the analog unit 801 and the chip size.

[0135] Furthermore, during non-exposure, the potential of the cathode electrode connected to the -5V power supply line 713 of the light emitting element 602 is set to a floating state, thereby suppressing leakage current from the current control MOSFET 902 and the switching MOSFET 903 to the light emitting element 602, which would otherwise generate leakage current even when the elements are off during non-exposure, and reducing power consumption.

[0136] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light emitting element 602 operates between a third potential of +1V and a fourth potential of −5V. The potential difference between the third potential +1V and the fourth potential −5V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. As a result, in a configuration in which the light emitting element 602 and the analog unit 801 are formed on a single chip, the analog unit 801 can be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light emitting element 602, and the chip size can be reduced.

[0137] In this embodiment, the third potential +1V is lower than the first potential +5V, and the fourth potential −5V is lower than the second potential 0V. The potential difference between the second potential 0V and the fourth potential −5V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. The second potential 0V is ground potential, the first potential +5V is positive relative to ground potential, and the fourth potential −5V is negative relative to ground potential.

[0138] In addition, in this embodiment, when the switch 714 is switched so that no current is supplied to the light-emitting element 602, the potential of the cathode terminal K of the light-emitting element 602 becomes a fifth potential of 0 V, which is higher than at least the fourth potential of −5 V. The fifth potential of 0 V is equal to the second potential of 0 V.

[0139] Furthermore, in this embodiment, the fourth potential -5V is lower than the first potential +5V. The second potential 0V is the ground potential. The third potential +1V is higher than the second potential 0V.

[0140] In this embodiment, the voltages are not limited to +5V and −5V, and any voltage other than +5V and −5V can be supplied as long as it can drive the light emitting element 602. For example, instead of securing a 10V voltage range from +5V to −5V, a 10V voltage range from +4V to −6V may be secured.

[0141] In addition, in this embodiment, 20 light emitting element array chips 400-1 to 400-20 are provided on the printed circuit board 202, but this is not limitative, and any number of light emitting element array chips can be provided on the printed circuit board 202 as needed.

[0142] (Embodiment 2) The configuration of the image forming apparatus according to the second embodiment of the present invention is the same as that of the image forming apparatus 1 shown in Fig. 1, and therefore a description thereof will be omitted. Also, the configuration of the exposure head according to this embodiment is the same as that shown in Figs. 3 to 8, except for the circuit configuration of the exposure head, and therefore a description thereof will be omitted.

[0143] The first embodiment has a configuration in which the cathode electrode of the plurality of light emitting elements 602 is common, but the present embodiment has a configuration in which the anode electrode of the plurality of light emitting elements 602 is common.

[0144] <Exposure head circuit configuration> The circuit configuration of the exposure head according to the second embodiment of the present invention will be described in detail with reference to FIG.

[0145] In FIG. 17, parts having the same configuration as those in FIG. 9 are given the same reference numerals, and the description thereof will be omitted.

[0146] The exposure head according to this embodiment has an image controller unit 1301 that transmits signals or data for controlling the printed circuit board 1302 to the printed circuit board 1302 and performs processing on image data and processing on exposure timing. The signals and data transmitted from the image controller unit 1301 to the printed circuit board 1302 are clock signals, image data, line synchronization signals, and communication signals.

[0147] Specifically, the image controller unit 1301 includes an image data generation unit 701, a chip data conversion unit 702, a CPU 703, a synchronization signal generation unit 704, a +5V generation circuit 710, a switch 714, and a +10V generation circuit 1303.

[0148] The image controller unit 1301 and the printed circuit board 1302 are connected by a clock signal line 705 , a line synchronization signal line 706 , an image data signal line 707 , a communication signal line 708 , a +5V power line 712 and a +10V power line 1304 .

[0149] The +10V power supply line 1304 connects the switch 714 to each of the light-emitting element array chips 1400-1 to 1400-20.

[0150] The +10V generation circuit 1303 converts the +12V power supply voltage applied from an external +12V power supply into a +10V voltage and supplies it to the switch 714. As the -5V generation circuit 711, a general switching regulator circuit can be applied.

[0151] The switch 714 switches whether or not a voltage of +10 V is supplied to the light-emitting element array chip 1400 by turning on or off depending on whether or not a power control signal is input from the CPU 703. The switch 714 turns on when a power control signal is input from the CPU 703, and supplies a voltage of +10 V to each of the light-emitting element array chips 1400-1 to 1400-20 via the +10 V power line 1304. The +10 V power line 1304 is in a floating state when the switch 714 is turned off and no voltage of +10 V is supplied to the light-emitting element array chips 1400-1 to 1400-20.

[0152] The printed circuit board 1302 includes a head information storage unit 709 and light-emitting element array chips 1400-1 to 1400-20. The layout and arrangement of the light-emitting element array chips 1400-1 to 1400-20 on the printed circuit board 1302 are the same as the layout and arrangement of the light-emitting element array chips 400-1 to 400-20 on the printed circuit board 302.

[0153] The light-emitting element array chip 1400-1 and the light-emitting element array chip 1400-2 are connected by a signal line 708-1. The light-emitting element array chip 1400-2 and the light-emitting element array chip 1400-3 are connected by a signal line 708-2. Similarly, the light-emitting element array chips 1400-3, etc. are connected in a daisy chain by signal lines 708-3, etc.

[0154] Each of the light-emitting element array chips 1400-1 to 1400-20 generates a line synchronization signal for the next chip and outputs it to the next light-emitting element array chip 1400-2 to 1400-20 via signal lines 708-1, .... Each of the light-emitting element array chips 1400-1 to 1400-20 causes the light-emitting element 602 to emit light based on the setting values set in the input clock signal, line synchronization signal, image data, and communication signal.

[0155] The head information storage unit 709 is connected to the CPU 703 via a communication signal line 708. The head information storage unit 709 is a storage device that stores head information such as the light emission amount and mounting position information of the light emitting element array chips 1400-1 to 1400-20.

[0156] The light emitting portions of the light emitting element array chips 1400-1 to 1400-20 have the same configuration as the light emitting portion 404 shown in FIG. 5, and therefore the description thereof will be omitted.

[0157] <Circuit configuration of light-emitting element array chip> The circuit configuration of the light emitting element array chips 1400-1 to 1400-20 of the exposure head according to the second embodiment of the present invention will be described in detail with reference to FIG.

[0158] Since the light-emitting element array chips 1400-1 to 1400-20 have the same circuit configuration, only the circuit configuration of the light-emitting element array chip 1400-1 will be described, and descriptions of the circuit configurations of the light-emitting element array chips 1400-2 to 1400-20 will be omitted. Also, in Fig. 18, parts having the same configuration as in Fig. 12 will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0159] The light emitting element array chip 1400-1 includes a light emitting section 404 and a circuit section 406. The circuit section 406 includes a digital section 800 and an analog section 801.

[0160] In this embodiment, 748×4 columns=2992 drive circuits 900 are provided for each of the light-emitting element array chips 1400-1 to 1400-20. Since all the drive circuits 900 have the same configuration, only the configuration of one drive circuit 900 will be described for simplicity.

[0161] The current control MOSFET 902 is a Pch MOSFET. The current control MOSFET 902 has a source terminal connected to the cathode of the light emitting element 602, a gate terminal connected to the output terminal of the current setting DAC 901, and a drain terminal connected to the source terminal of the switching MOSFET 903. The current control MOSFET 902 is configured so that the current flowing from the source terminal to the drain terminal increases as the analog voltage input from the current setting DAC 901 increases.

[0162] The switching MOSFET 903 is a Pch MOSFET, and has a source terminal connected to the drain terminal of the current control MOSFET 902, a gate terminal connected to the output terminal of the data holding unit 806, and a drain terminal connected to GND. The gate terminal of the switching MOSFET 903 receives binary drive signals 1 to 4 of Hi level or Low level from the data holding units 806-001 to 806-748.

[0163] The switching MOSFET 903 is turned ON when a Hi-level drive signal is input to its gate terminal, and is turned OFF when a Low-level drive signal is input to its gate terminal. When the switching MOSFET 903 is turned ON by inputting a Hi-level drive signal to its gate terminal, a current that serves as the drive current for the light-emitting element 602 controlled by the current control MOSFET 902 flows from the source terminal to the drain terminal.

[0164] Next, the power supply configuration for each of the digital section 800, the analog section 801, and the light emitting element 602 will be described in detail with reference to FIG.

[0165] 19, parts having the same configuration as those in Fig. 11 are denoted by the same reference numerals, and their description will be omitted. Also, in Fig. 19, for the sake of simplicity, the description of the internal blocks of the digital unit 800 is omitted, and only one drive circuit 900 and one light-emitting element 602 are shown in the analog unit 801.

[0166] A voltage of +10V is supplied to the anode terminal A of the light emitting element 602 from the +10V power supply line 1304, and the cathode terminal is connected to the source terminal of the current control MOSFET 902. The light emitting element 602 is, for example, an organic EL, and generally generates a forward voltage of about 6V with a drive current of several μA. In other words, the potential of the cathode terminal K of the light emitting element 602 is about +4V, which is +10V minus 6V.

[0167] Since the drain-source voltages of the current control MOSFET 902 and the switching MOSFET 903 are each about 1.5 V, adding the drain-source voltage of 1.5 V × 2 = 3 V to the forward voltage of the light emitting element 602 of 6 V results in about 9 V. Therefore, the light emitting element array chips 1400-1 to 1400-20 require a voltage of about 9 V or more to cause the light emitting element 602 to emit light. The light emitting element array chips 1400-1 to 1400-20 can drive the light emitting element 602 in a 10 V range between GND (0 V) and +10 V, and can therefore cause the light emitting element 602 to emit light.

[0168] In a conventional configuration in which an EL film is laminated on a circuit section by vapor deposition or the like, it was necessary to form a light-emitting element array chip using a semiconductor process of 9V or more, taking into consideration the drain-source voltage of the MOSFET, in order to ensure a forward voltage of 6V for the light-emitting element. In contrast, in this embodiment, GND and +10V are supplied as power supply voltages to drive the light-emitting element 602 in the 10V range, and the digital section 800 and analog section 801 are configured using a semiconductor process of GND to +5V. As a result, in this embodiment, the sizes of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip sizes of the light-emitting element array chips 1400-1 to 1400-20 can be reduced.

[0169] <Exposure head operation> The operation of the exposure head 106 according to the second embodiment of the present invention will be described in detail with reference to FIGS.

[0170] The exposure head 106 starts operating when the main power supply of the image forming apparatus 1 is turned on.

[0171] First, the CPU 703 determines whether or not a print job has been requested by the user (S11).

[0172] If a print job has not been requested by the user (S11: No), the CPU 703 repeats the operation of step S11.

[0173] On the other hand, when a print job is requested by the user (S11: Yes), the CPU 703 writes setting values into the register sections 803 of the light-emitting element array chips 1400-1 to 1400-20 to perform register setting (S12).

[0174] Next, the CPU 703 outputs a power supply control signal to the switch 714 to supply a voltage of +10V to the anode electrodes of the light emitting elements 602 of the light emitting element array chips 1400-1 to 1400-20 (+10V ON) (S13).

[0175] Next, the CPU 703 starts outputting image data to the light-emitting element array chips 1400-1 to 1400-20 at a predetermined timing, thereby exposing the photosensitive drum 102 (S14).

[0176] Next, the CPU 703 determines whether the print job is completed (S15).

[0177] If the print job is not completed (S15: No), the CPU 703 repeats the operation of step S15.

[0178] On the other hand, when the print job is completed (S15: Yes), the CPU 703 stops sending the power control signal to the switch 714, thereby putting the potential of the anode electrode of the light emitting element 602 into a floating state and ending the operation.

[0179] Next, the operation of the exposure head 106 will be described in more detail with reference to FIG.

[0180] 21, at time t=t10, the power supply of the image forming apparatus 1 is turned on, and a power supply voltage of +12V is supplied to the +5V generation circuit 710 and the +10V generation circuit 1303. As a result, the voltage of the +5V power supply line 712 becomes +5V after time t=t10 has elapsed. At this time, the potential of the +10V power supply line 1304 is floating (0V in FIG. 21) because the switch 714 is turned off.

[0181] At time t=t11, upon receiving a JOB request from the user, the CPU 703 outputs a power control signal to the switch 714, which causes the potential of the +10V power line 1304 to become +10V, thereby enabling the light emitting element 602 to be driven.

[0182] At time t=t12, the job ends, and the CPU 703 stops outputting the power control signal to the switch 714, turns off the switch 714, and sets the potential of the +10V power line 1304 to a floating state (0V in FIG. 21).

[0183] In this configuration in which the light emitting element 602 and the analog unit 801 are formed on the same chip, a voltage (+10 V) higher than the voltage (+5 V and reference potential (GND)) supplied to the analog unit 801 is supplied to the anode electrode of the light emitting element 602. This allows the analog unit 801 to be formed using a semiconductor process with a relatively low withstand voltage, thereby reducing the size of the analog unit 801 and the chip size.

[0184] During non-exposure, the potential of the anode electrode connected to the +10V power supply line 1304 of the light emitting element 602 is set to a floating state, thereby suppressing leakage current from the current control MOSFET 902 and the switching MOSFET 903 to GND, which would otherwise occur even when they are off during non-exposure, and reducing power consumption.

[0185] In this embodiment, the analog unit 801 operates between a first potential of +5V and a second potential of 0V, and the light emitting element 602 operates between a third potential of +10V and a fourth potential of +4V. The potential difference between the third potential of +10V and the fourth potential of +4V is equal to or greater than the potential difference between the first potential of +5V and the second potential of 0V. As a result, in a configuration in which the light emitting element 602 and the analog unit 801 are formed on a single chip, the analog unit 801 can be formed using a low-voltage semiconductor process while ensuring the forward voltage of the light emitting element 602, thereby reducing the chip size.

[0186] In this embodiment, the third potential +10 V is higher than the first potential +5 V, and the fourth potential +4 V is higher than the second potential 0 V. The potential difference between the first potential +5 V and the third potential +10 V is equal to or greater than the potential difference between the first potential +5 V and the second potential 0 V.

[0187] In this embodiment, when the switch 714 is switched so as not to supply current to the light-emitting element 602, the fifth potential becomes 0 V, which is lower than at least the first potential +5 V. The fifth potential 0 V is equal to the second potential 0 V.

[0188] Furthermore, in this embodiment, the fourth potential +4V is lower than the first potential +5V. The second potential 0V is the ground potential. The third potential +10V is higher than the second potential 0V.

[0189] In this embodiment, the voltages are not limited to +5V and +10V, and may be any voltage other than 5V and 10V as long as the voltage can drive the light emitting element 602.

[0190] In this embodiment, 20 light emitting element array chips 1400-1 to 1400-20 are provided on the printed circuit board 1302, but the present invention is not limited to this and any number of light emitting element array chips can be provided on the printed circuit board 1302 as needed.

[0191] The present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0192] 1. Image forming device 102 Photosensitive drum 103 Image creation section 104 Fixing section 105 Conveyor 106 Exposure head 107 Charger 108 Developer 110 Register Roller 111 Transfer belt 112 Paper ejection roller 113 Optical Sensor 201 Light emitting element group 202 Printed Circuit Board 203 Rod Lens Array 204 Housing 305 Connector 400-1 to 400-20 Light-emitting element array chip 402 Light-emitting substrate 404 Light-emitting part 406 Circuit section 408 Wire bonding pad 504 Lower electrode 506 Light-emitting layer 508 Upper electrode 602 Light-emitting element 604 Light-emitting element array

Claims

1. An exposure head that exposes a photosensitive drum, A substrate; a plurality of strip-shaped semiconductor chips arranged on the substrate, each of the semiconductor chips comprising a plurality of light-emitting elements that emit light and a drive circuit that drives the light-emitting elements; a lens array that focuses light from the light-emitting element onto the photosensitive drum; and The drive circuit operating between a first potential and a second potential; The light-emitting element is operating between a third potential and a fourth potential; a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential; An exposure head characterized by:

2. The light-emitting element is an anode terminal connected to the third potential and a cathode terminal connected to the fourth potential; The third potential is a potential lower than the first potential, The fourth potential is a potential lower than the second potential; 2. The exposure head according to claim 1.

3. The potential difference between the second potential and the fourth potential is the potential difference between the first potential and the second potential is equal to or greater than the potential difference between the first potential and the second potential; 3. The exposure head according to claim 1 or 2.

4. The second potential is is the ground potential, The first potential is a positive potential relative to the ground potential, The fourth potential is a negative potential relative to the ground potential; 4. The exposure head according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

5. The drive circuit a switching element disposed between the first potential and the light-emitting element, for switching whether or not a current is supplied to the light-emitting element; 5. The exposure head according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

6. The potential of the cathode terminal of the light emitting element is When the switching element is switched so as not to supply current to the light-emitting element, a fifth potential is set that is higher than at least the fourth potential.

6. The exposure head according to claim 5.

7. The fifth potential is equal to the second potential, 7. The exposure head according to claim 6.

8. The light-emitting element is an anode terminal connected to the third potential and a cathode terminal connected to the fourth potential; The third potential is a potential higher than the first potential, The fourth potential is a potential higher than the second potential; 2. The exposure head according to claim 1.

9. The potential difference between the first potential and the third potential is the potential difference between the first potential and the second potential is equal to or greater than the potential difference between the first potential and the second potential; 9. The exposure head according to claim 8.

10. The drive circuit a switching element disposed between the third potential and the light-emitting element, for switching whether or not a current is supplied to the light-emitting element; 10. The exposure head according to claim 8 or claim 9.

11. The potential of the anode terminal of the light emitting element is When the switching element is switched so as not to supply current to the light-emitting element, the potential becomes a fifth potential that is lower than at least the first potential.

11. The exposure head according to claim 10.

12. The fifth potential is equal to the second potential, 12. The exposure head according to claim 11.

13. The fourth potential is a potential lower than the first potential; 13. The exposure head according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

14. The second potential is is the ground potential, 14. The exposure head according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

15. The third potential is a potential higher than the second potential; 15. The exposure head according to claim 1.

16. The light-emitting element is Consists of an organic EL film.

16. The exposure head according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

17. The organic EL film is formed on the upper part of the driving circuit, 17. The exposure head according to claim 16.

18. a charger that charges the photosensitive drum; an exposure head according to any one of claims 1 to 17, wherein the photosensitive drum charged by the charger is exposed to light to form an electrostatic latent image on the photosensitive drum; a developing unit that develops the electrostatic latent image to form a developer image on the photosensitive drum; An image forming apparatus comprising:

Images