Communication system and image forming apparatus

Abstract

To flexibly switch between transmission of individual setting information and transmission of common setting information to a plurality of devices.SOLUTION: A communication system is provided comprising: a plurality of devices; a communication interface that is connected to the plurality of devices; a first storage unit that stores a plurality of pieces of individual setting information for the plurality of devices and common setting information; a second storage unit that stores control information for indicating the operation mode for the communication interface; and a control unit that controls the operation of the communication interface by writing the control information in the second storage unit. When the control information in the second storage unit indicates a first operation mode, the communication interface transmits the plurality of pieces of individual setting information in the first storage unit to the plurality of devices, and when the control information in the second storage unit indicates a second operation mode, transmits the common setting information in the first storage unit to the plurality of devices.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a communication system and an image forming apparatus. [Background technology]

[0002] Electrophotographic image forming devices form an image by exposing a rotating photoreceptor to light to form an electrostatic latent image on the photoreceptor, and then developing the electrostatic latent image with toner. Among these, solid-state exposure devices that use light from an array of light-emitting elements are attracting attention because they are easier to make smaller, quieter, and less expensive than laser scanning exposure devices.

[0003] Patent Document 1 discloses an example of a solid-state exposure type exposure apparatus. In the exposure apparatus of Patent Document 1, multiple light-emitting chips, each having an array of light-emitting elements, are connected to a communication interface via multiple signal lines, and each light-emitting chip has an internal register for storing operational setting values.

[0004] Patent Document 2 discloses a communication system for communicating with multiple devices in an image forming apparatus. The communication system of Patent Document 2 can switch between sending common setting values ​​to multiple devices collectively or sending individual setting values ​​to multiple devices individually, depending on a mode designated in advance by an administrator via a user interface (UI). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-35765 [Patent Document 2] Patent No. 4193148 Summary of the Invention [Problem to be solved by the invention]

[0006] Even in a solid-state exposure type exposure apparatus, if it were possible to flexibly switch between sending individual setting information to multiple light-emitting chips and sending common setting information, the communication load for setting those light-emitting chips would be reduced and communication time would be shortened, which would be beneficial in terms of productivity. However, the method described in Patent Document 2, in which a mode is specified in advance via a UI, is inconvenient for real-time operation, and is particularly not suitable for controlling operation during job execution in an image forming apparatus.

[0007] In view of the above, the present invention aims to provide improved communication control that allows for flexible switching between sending individual setting information to multiple devices and sending common setting information. [Means for solving the problem]

[0008] According to a first aspect, there is provided a communication system comprising: a plurality of devices; a communication interface connected to the plurality of devices via a plurality of signal lines; a first storage unit that stores setting information to be transmitted from the communication interface to the plurality of devices; a second storage unit that stores control information indicating an operating mode of the communication interface; and a control unit that controls operation of the communication interface by writing the control information to the second storage unit, wherein the first storage unit stores a plurality of pieces of individual setting information to be applied individually to the plurality of devices and common setting information to be applied commonly to the plurality of devices, and the communication interface reads out the plurality of pieces of individual setting information from the first storage unit and transmits the read out plurality of pieces of individual setting information to the plurality of devices when the control information written to the second storage unit includes a first value indicating a first operating mode, and reads out the common setting information from the first storage unit and transmits the read out common setting information to the plurality of devices when the control information written to the second storage unit includes a second value indicating a second operating mode.

[0009] According to a second aspect, there is provided an image forming apparatus for forming an image on a sheet, comprising a photosensitive member and an exposure device for exposing the photosensitive member, the exposure device including a communication system according to the first aspect, and each of the plurality of devices being a light-emitting chip having an array of light-emitting elements used to expose the photosensitive member. [Effects of the Invention]

[0010] According to the present invention, it is possible to flexibly switch between transmitting individual setting information to a plurality of devices and transmitting common setting information. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a schematic configuration of an image forming apparatus according to an embodiment. [Figure 2] FIG. 2 is an explanatory diagram of the configuration of a photosensitive member and an exposure head according to an embodiment. [Figure 3] FIG. 2 is an explanatory diagram illustrating the configuration of a printed circuit board of an exposure head according to an embodiment. [Figure 4] 1A and 1B are explanatory diagrams of a light-emitting chip and a light-emitting element array in the light-emitting chip according to an embodiment. [Figure 5] FIG. 1 is a plan view showing a schematic configuration of a light-emitting chip according to an embodiment. [Figure 6] 1 is a cross-sectional view showing a schematic configuration of a light-emitting device according to an embodiment. [Figure 7] FIG. 1 is a block diagram showing an example of the configuration of a communication system that can be installed in an exposure apparatus according to an embodiment. [Figure 8] FIG. 2 is a block diagram showing an example of a detailed configuration of a light-emitting chip according to an embodiment. [Figure 9] FIG. 3 is a circuit diagram showing a partial configuration of a current driver corresponding to one light-emitting element. [Figure 10] 10 is a timing chart of transmission of image data to a plurality of light-emitting chips. [Figure 11A] 10 is a timing chart of transmission of setting data to a plurality of light-emitting chips. [Figure 11B]10 is a timing chart of receiving setting data from a plurality of light-emitting chips. [Figure 12] 10 is a timing chart illustrating the transmission of disabling data to a plurality of light-emitting chips. [Figure 13] FIG. 10 is a state transition diagram showing constraints on transitions of the operating states of the interface circuit of the light-emitting chip. [Figure 14] 10 is a timing diagram of data communication in a scenario in which misinterpretation of identification information occurs during transmission of image data. [Figure 15] 10 is a table showing an example of a configuration of a register of an image controller according to an embodiment. [Figure 16A] 10 is a timing chart of transmission of setting data in the individual setting mode. [Figure 16B] 10 is a timing chart of transmission of setting data in the common setting mode. [Figure 17] 10 is a flowchart showing an example of the flow of a tip setting process according to an embodiment. [Figure 18] 10 is a flowchart showing an example of the flow of a job control process according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0013] 1. General Configuration of Image Forming Apparatus 1 shows an example of a schematic configuration of an image forming apparatus 1 according to an embodiment. The image forming apparatus 1 includes a reading unit 100, an image creating unit 103, a fixing unit 104, a conveying unit 105, and a control unit (not shown) capable of communicating with these units. The reading unit 100 optically reads an original placed on a platen and generates read image data. The image creating unit 103 forms an image on a sheet, for example, based on the read image data generated by the reading unit 100 or based on print image data received from an external device via a network.

[0014] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration and are collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the drawing during image formation. The charger 107 charges the photoconductor 102. The exposure head 106 exposes the photoconductor 102 to light to form an electrostatic latent image on the surface of the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner to form a toner image. The toner image formed on the surface of the photoreceptor 102 is transferred onto a sheet transported on a transfer belt 111. By transferring the toner images of the four photoreceptors 102 onto the sheet in an overlapping manner, a color image containing four color components, namely black, yellow, magenta, and cyan, can be formed.

[0015] The conveying unit 105 controls the feeding and transport of sheets. Specifically, the conveying unit 105 feeds a sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to a transport path of the image forming apparatus 1. The fed sheet is transported to the registration rollers 110. The registration rollers 110 transport the sheet onto the transfer belt 111 at an appropriate timing so that the toner images on the photoconductors 102 are transferred to the sheet. As described above, the toner image is transferred to the sheet while the sheet is transported on the transfer belt 111. The fixing unit 104 fixes the toner image to the sheet by applying heat and pressure to the sheet to which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus 1 by the discharge rollers 112. An optical sensor 113 is disposed opposite the transfer belt 111. The optical sensor 113 optically reads the test chart formed on the transfer belt 111 by the image forming unit 101. If an error (e.g., color misalignment) in the image formation range is detected for the test chart read by the optical sensor 113, the CPU 701 (described later) performs control to compensate for the error when the subsequent job is executed.

[0016] Although an example has been described here in which a toner image is directly transferred from each photoconductor 102 to a sheet on the transfer belt 111, the toner image may also be indirectly transferred from each photoconductor 102 to a sheet via an intermediate transfer body. Also, although an example has been described here in which a color image is formed using toners of multiple colors, the technology according to the present disclosure is also applicable to an image forming apparatus that forms a monochrome image using toner of a single color.

[0017] 1 manages the states of the reading unit 100, the image forming unit 103, the fixing unit 104, and the conveying unit 105, and controls the operations of these units so that the print job is executed smoothly. A multifunction peripheral (MFP) control unit that controls the operation of the entire device, and a print control unit that controls the image forming operation may be provided, and the execution of the print job may be controlled by these control units cooperating with each other.

[0018] <2. Basic structure of the exposure head> 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 includes a light-emitting element array 201, a printed circuit board 202 on which the light-emitting element array 201 is mounted, a rod lens array 203, and a housing 204 that supports the printed circuit board 202 and the rod lens array 203. The photoconductor 102 has a cylindrical shape. The exposure head 106 is disposed such that its longitudinal direction is parallel to an axial direction D1 corresponding to the rotation axis of the photoconductor 102, and the surface on which the rod lens array 203 is attached faces the surface of the photoconductor 102. While the photoconductor 102 rotates in the circumferential direction D2, the light-emitting element array 201 of the exposure head 106 emits light, and the rod lens array 203 focuses the light on the surface of the photoconductor 102.

[0019] 3(A) and 3(B) show an example of the configuration of the printed circuit board 202. Note that Fig. 3(A) shows the surface on which the connector 305 is mounted, and Fig. 3(B) shows the surface on which the light-emitting element array 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). Fig. 4 schematically shows the light-emitting chip 400 and the arrangement of light-emitting elements 602 in the light-emitting chip 400.

[0020] In this embodiment, the light-emitting element array 201 includes a plurality of light-emitting elements arranged two-dimensionally. The light-emitting element array 201 includes, as a whole, N columns of light-emitting elements in the axial direction D1 of the photoconductor and M rows of light-emitting elements in the circumferential direction D2, where M and N are integers. In the example shown in FIG. 3B, the light-emitting element array 201 is divided into 20 light-emitting chips 400-1 to 400-20, each including a subset of the entire plurality of light-emitting elements, and the light-emitting chips 400-1 to 400-20 are arranged in a staggered pattern along the axial direction D1. The light-emitting chips 400-1 to 400-20 are also collectively referred to as light-emitting chips 400. As shown in FIG. 3B, the area occupied by all of the light-emitting elements of the 20 light-emitting chips in the axial direction D1 is wider than the area occupied by the maximum width W0 of the input image data. Therefore, some light-emitting elements located at both ends of the axial direction D1 may not be used to expose the photoconductor 102 unless an error in the image formation area is detected. Each light-emitting chip 400 on the printed circuit board 202 is connected to the image controller 710 (FIG. 7) via a connector 305. For convenience of explanation, the side with the smaller branch number of the light-emitting chips 400-1 to 400-20 arranged along the axial direction D1 may be referred to as the "left" and the side with the larger branch number as the "right." For example, the light-emitting chip 400-1 is the leftmost light-emitting chip 400, and the light-emitting chip 400-20 is the rightmost light-emitting chip.

[0021] The number J (J=N / 20) of light-emitting elements 602 arranged in each row of one light-emitting chip 400 may be equal to, for example, 748 (J=748, N=14960). Meanwhile, the number M of light-emitting elements 602 arranged in each column of one light-emitting chip 400 may be equal to, for example, 4 (M=4). That is, in the exemplary embodiment, each light-emitting chip 400 has a total of 2992 (=748×4) light-emitting elements 602, with 748 in the axial direction D1 and 4 in the circumferential direction D2. The interval P between the center points of the light-emitting elements 602 adjacent to each other in the circumferential direction D2 is Cmay be, for example, approximately 21.16 μm, corresponding to a resolution of 1200 dpi. The distance between the center points of adjacent light-emitting elements 602 in the axial direction D1 may also be approximately 21.16 μm, in which case 748 light-emitting elements 602 occupy a length of approximately 15.8 mm in the axial direction D1, which corresponds to the width in the axial direction D1 of the light-emitting element array of one light-emitting chip 400. The width in the axial direction D1 of the light-emitting element array of 20 light-emitting chips 400-1 to 400-20 is approximately 316 mm.

[0022] In one embodiment, M>1, and as shown in FIG. 4, in each light-emitting chip 400, the light-emitting elements 602 may be completely arranged in a grid pattern. In another embodiment, M=1, and in each light-emitting chip 400, the light-emitting elements 602 form a simple one-dimensional array. In yet another embodiment, M>1, and in each light-emitting chip 400, the M light-emitting elements 602 in each column may be arranged in a stepped pattern (i.e., offset from each other by 1 / M of the pixel pitch in the axial direction) or a partially stepped pattern. When the number of rows M of the light-emitting element array is greater than 1, pixel areas (also called spots) corresponding to each pixel of each line on the surface of the photoconductor 102 are exposed multiple times by the M light-emitting elements 602. This increases the amount of light for exposure, allowing for the formation of a high-density image.

[0023] 5 is a plan view showing a schematic configuration of the light-emitting chip 400. The plurality of light-emitting elements 602 of each light-emitting chip 400 are formed on a light-emitting substrate 402, which is, for example, a silicon substrate. A circuit unit 406 for driving the plurality of light-emitting elements 602 is provided on the light-emitting substrate 402. Signal lines for communicating with the image controller 710, power lines for connecting to a power source, and ground lines for connecting to ground are connected to the pads 408-1 to 408-8. The signal lines, power lines, and ground lines may be wires made of, for example, gold.

[0024] FIG. 6 shows a portion of the cross section taken along line AA in FIG. 5. A plurality of lower electrodes 504 are formed on the light-emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light-emitting layer 506 is provided on the lower electrodes 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504. When a voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. Therefore, one lower electrode 504 and a partial region of the light-emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 constitute one light-emitting element 602. That is, in this embodiment, the light-emitting substrate 402 includes a plurality of light-emitting elements 602.

[0025] The light-emitting layer 506 may be, for example, an organic EL film. The upper electrode 508 is made of a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. In this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that a partial region through which light from each light-emitting element 602 passes transmits the emission wavelength.

[0026] 6 shows that one continuous light-emitting layer 506 is formed, but multiple light-emitting layers 506 each having a width equivalent to the width W of the lower electrode 504 may be formed on the lower electrode 504. Also, in FIG. 6, the upper electrode 508 is formed as a single common electrode for the multiple lower electrodes 504, but multiple upper electrodes 508 each having a width equivalent to the width W of the lower electrode 504 may be formed corresponding to each lower electrode 504. Also, among the lower electrodes 504 of each light-emitting chip 400, a first plurality of lower electrodes 504 may be covered with a first light-emitting layer 506, and a second plurality of lower electrodes 504 may be covered with a second light-emitting layer 506. Similarly, among the lower electrodes 504 of each light-emitting chip 400, a first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504, and a second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. In such a configuration, one lower electrode 504 and the region of the light-emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 constitute one light-emitting element 602 .

[0027] <3. Communication system configuration> This section describes an example of the configuration of a communication system involved in the communication of data for controlling light emission in the exposure head 106. For simplicity of explanation, only the configuration for a single color component will be described here, but similar configurations may exist for multiple color components, and some of the configurations described may be common to multiple color components.

[0028] Fig. 7 is a block diagram showing an example of the configuration of a communication system 200 that can be mounted on the exposure head 106. Referring to Fig. 7, the communication system 200 includes a CPU 701, an image controller 710, and a plurality of (20 in the illustrated embodiment) light-emitting chips 400-1 to 400-20. In the communication system 200, each light-emitting chip 400 is a slave device that passively participates in communication.

[0029] The CPU 701 is a processor that controls the operation of the exposure head 106. In this embodiment, the image controller 710 is mounted on a printed circuit board (first board) 202 together with the light emitting chips 400-1 to 400-20, and the CPU 701 is mounted on a control board (second board) 210 that is different from the printed circuit board. The printed circuit board 202 and the control board 210 are connected to each other via a communication line 211. The communication line 211 may be a serial communication line (for example, a serial communication cable). As will be described in detail later, the CPU 701 writes information to a register 712 of the image controller 710 via the serial communication line 211. For example, the CPU 701 controls the operation of the communication interface 715 by writing control information to the register 712.

[0030] The image controller 710 includes a clock generation unit 711, a register 712, an image data generation unit 713, a setting data processing unit 714, and a communication interface (I / F) 715. The communication I / F 715 is connected to the plurality of light-emitting chips 400 via a plurality of signal lines. For example, the signal lines between the communication I / F 715 and the n-th light-emitting chip 400-n include a data signal line DATAn, a data signal line READn, a clock signal line CLK, and a synchronization signal line SYNC. The data signal line DATAn is a signal line used to transmit data to the light-emitting chip 400-n. The data signal line READn is a signal line used to read data from the light-emitting chip 400-n. The clock signal line CLK is a signal line that carries a clock signal generated by the communication I / F 715 based on a reference clock signal from the clock generation unit 711. The synchronization signal line SYNC is a signal line that carries a line synchronization signal that indicates the periodic exposure timing of each line on the photoconductor 102.

[0031] The clock generating unit 711 generates a reference clock signal having a preset frequency, and outputs the generated reference clock signal to the communication I / F 715 .

[0032] The register 712 stores information related to communication between the communication I / F 715 and the plurality of light-emitting chips 400. Although the register 712 is illustrated in Fig. 7 as an element separate from the setting data processing unit 714 and the communication I / F 715, the setting data processing unit 714 and the communication I / F 715 may be an integrated control chip, and the register 712 may be part of such a control chip. As illustrated, the register 712 has a first memory area (first memory unit) 721 and a second memory area (second memory unit) 722 different from the first memory area 721.

[0033] The first storage area 721 stores setting information to be transmitted from the communication I / F 715 to the plurality of light-emitting chips 400. The setting information may include, for example, at least one of control parameters indicating the following setting values: - Adjustment value of the light intensity of the light-emitting element array - Power saving mode on / off -Instruction to stop driving light emitting elements The adjustment value of the light intensity of the light-emitting element array may indicate, for example, an offset relative to a reference value of the drive current to be supplied to the light-emitting element. Typically, the adjustment value of the light intensity is determined individually during post-manufacture inspection of the light-emitting chip to eliminate uneven light intensity. The adjustment value may also be determined for each light-emitting element group within the light-emitting chip. The power-saving mode refers to a mode in which the application of a steady voltage to the drive circuit of the light-emitting element array in each light-emitting chip 400 is stopped. When the power-saving mode is set to ON, the light-emitting chip 400 reduces power consumption by stopping the application of voltage to the drive circuit of the light-emitting element array. When the power-saving mode is set to OFF, voltage is applied to the drive circuit of the light-emitting element array, and the light-emitting element 602 emits light in response to the input of a drive signal indicating light emission ON. The light-emitting element drive stop instruction is an instruction to simultaneously stop the emission of all light-emitting elements 602 in the light-emitting element array of each light-emitting chip 400.

[0034] The second storage area 722 stores control information that instructs the operation mode of the communication I / F 715. Control of communication based on the control information stored in the second storage area 722 will be described in detail later.

[0035] The image data generation unit 713 performs image processing on image data received from the reading unit 100 or an external device to generate binary bitmap image data for controlling the on / off of light emission of the light-emitting elements 602 of the multiple light-emitting chips 400. The image processing here may include, for example, raster conversion, tone correction, color conversion, and halftone processing. The image data generation unit 713 outputs the generated image data to the communication I / F 715 as input image data.

[0036] The setting data processing unit 714 reads out the setting information written in the first storage area 721 of the register 712, and outputs setting data including the read setting information and corresponding address information to the communication I / F 715. The address information here indicates the address in the register of the light-emitting chip 400 to which the setting information is written. In addition, the setting data processing unit 714 receives the setting information read out from the register of each light-emitting chip 400 via the communication I / F 715, and outputs the received setting information to the CPU 701.

[0037] The communication I / F 715 is an interface that mediates communication between the image controller 710 and the light-emitting chips 400-1 to 400-20. For example, the communication I / F 715 divides input image data input from the image data generation unit 713 into 20 segments and transmits signal sequences corresponding to the segments in parallel to the light-emitting chips 400-1 to 400-20. At this time, the signal sequence of the i-th segment is assigned predetermined identification information in accordance with a signal format described later, and is transmitted to the light-emitting chip 400-i via the data signal line DATAi.

[0038] The communication I / F 715 also transmits a signal sequence corresponding to the setting data input from the setting data processing unit 714 to the light-emitting chips 400-1 to 400-20. At this time, the signal sequence of the setting data for the light-emitting chip 400-i is assigned with predetermined identification information and access control information in accordance with a signal format described later, and is transmitted to the light-emitting chip 400-i via the data signal line DATAi. The access control information here is information instructing writing of the setting information to a register of the light-emitting chip 400-i. The communication I / F 715 is also capable of reading the setting information from the register of the light-emitting chip 400-i. For example, the communication I / F 715 transmits a signal sequence including access control information instructing reading of the setting information and address information specifying an address to the light-emitting chip 400-i via the data signal line DATAi. Then, the light-emitting chip 400-i reads the setting information written at the specified address and returns the read setting information to the communication I / F 715 via the data signal line READi.

[0039] FIG. 8 is a block diagram showing an example of a detailed configuration of one light-emitting chip 400 (the nth light-emitting chip 400-n) as a slave device. Referring to FIG. 8, the light-emitting chip 400 includes a circuit unit 406, a light-emitting element array 1005, and eight pads 408-1 to 408-8, which are also shown in FIG. 5. The circuit unit 406 includes an interface (I / F) circuit 1001, a register 1002, a data holding unit 1003, and a current driving unit 1004. The I / F circuit 1001, the register 1002, and the data holding unit 1003 are digital circuits, and the current driving unit 1004 is an analog circuit. The light-emitting element array 1005 is a one-dimensional or two-dimensional array of light-emitting elements 602 used to form an image. The pads 408-1 and 408-2 are connected to a power supply voltage VCC via a power supply line. Power is supplied from this power supply voltage VCC to each circuit of the circuit unit 406 of the light-emitting chip 400. Pads 408-3 and 408-4 are connected to ground by ground lines. Each circuit of the circuit section 406 and the upper electrode 508 are connected to ground via pads 408-3 and 408-4. Signal lines CLK, SYNC, DATAn, and READn are connected to the I / F circuit 1001 via pads 408-5, 408-6, 408-7, and 408-8, respectively.

[0040] The I / F circuit 1001 is an interface that mediates communication between each light-emitting chip 400 and the image controller 710. The register 1002 is a storage unit (e.g., a semiconductor memory) that stores setting information for setting the operation of the light-emitting element array 1005. The data holding unit 1003 includes a set of latch circuits that hold J×M signal values ​​of image data received from the communication I / F 715 via the I / F circuit 1001. The data holding unit 1003 outputs drive signals indicating each signal value in parallel to the current driving unit 1004 at the timing indicated by the line synchronization signal. The current driving unit 1004 drives the light-emitting elements 602 that make up the light-emitting element array 1005 in accordance with the drive signals input from the data holding unit 1003. The light-emitting element array 1005 is an array of light-emitting elements 602 used to expose the photosensitive member 102.

[0041] In addition to the drive signal, the current driver 1004 is supplied with a light emission intensity (light amount) value indicated by the setting information stored in the register 1002. FIG. 9 shows an example of a partial configuration of the current driver 1004, which is a driver circuit corresponding to one light emitting element 602. Referring to FIG. 9, the current driver 1004 includes a digital-to-analog converter (DAC) 1101, a first transistor 1102, and a second transistor 1103. The DAC 1101 performs digital-to-analog conversion on the digital value (current setting value) of the light emission intensity stored in the register 1002 and outputs a corresponding analog signal to the gate of the first transistor 1102. The first transistor 1102 is a current amplifier circuit and may be, for example, a P-channel MOSFET. The source of the first transistor 1102 is connected to a power supply voltage VCC. The drain of the first transistor 1102 is connected to the source of the second transistor 1103. The first transistor 1102 draws from its source a current whose magnitude depends on the current amount of an analog signal input to its gate and outputs it to its drain. The second transistor 1103 is a switching circuit and may be, for example, a P-channel MOSFET. A drive signal (indicating whether light emission is on or off) from the data storage unit 1003 is input to the gate of the second transistor 1103. The drain of the second transistor 1103 is connected to the lower electrode 504 of the light-emitting element 602. When the drive signal input to its gate indicates that light emission is on (e.g., high level), the second transistor 1103 outputs the current input to its source to the light-emitting element 602 via its drain. Therefore, during the period when the drive signal indicates that light emission is on, a current whose magnitude corresponds to the setting value stored in the register 1002 is supplied to the light-emitting element 602, causing each light-emitting element 602 to emit light at a specified light intensity.

[0042] 9 shows only a portion corresponding to one light-emitting element 602, the current driver 1004 may actually have the same number of similar circuits as the number of light-emitting elements 602 (for example, 748×4=2992). However, the DAC 1101 may be shared by multiple light-emitting elements 602. Furthermore, when a power-saving mode is adopted in the light-emitting chip 400, the circuit unit 406 may further include a switch capable of allowing and stopping application of the power supply voltage VCC to the current driver 1004.

[0043] In this embodiment, the I / F circuit 1001 can receive the following types of data from the communication I / F 715: Image data Setting data Disabling Data As described above, the image data is a sequence of signal values ​​indicating the on or off state of the drive signal output to each light-emitting element. The setting data indicates at least one setting value to be written to the register 1002 and the address of the corresponding register. The invalidation data is data transmitted from the communication I / F 715 to the I / F circuit 1001 to switch the operating state of the I / F circuit 1001. Both types of data are transmitted serially on the data signal line DATAn in synchronization with the clock indicated by the clock signal.

[0044] The I / F circuit 1001 determines the type of data received from the communication I / F 715 based on the identification information attached to the beginning of each data. The identification information may be composed of, for example, two clock bits from the rising edge of the synchronization signal. Table 1 below shows an example of the correspondence between the signal levels of the two bits (also called identification bits) of the identification information and the data type.

[0045] [Table 1]

[0046] According to the example of Table 1, if the first bit of the identification information is at a high level and the second bit is also at a high level, image data is transmitted after the identification information. If the first bit of the identification information is at a high level and the second bit is at a low level, setting data is transmitted after the identification information. If the first bit of the identification information is at a low level, invalidation data is transmitted after the identification information regardless of the signal level of the second bit. Note that the correspondence between the signal level of the identification information and the data type is not limited to the example of Table 1. For example, a correspondence in which the high level and the low level are interchanged may be adopted.

[0047] The I / F circuit 1001 switches the output destination of the subsequent data between the register 1002 and the data holding unit 1003 according to the data type determined based on the above-mentioned identification information. For example, when the identification information indicates image data, the I / F circuit 1001 outputs the subsequent data (together with a clock signal and a line synchronization signal) to the data holding unit 1003. When the identification information indicates setting data, the I / F circuit 1001 outputs the subsequent data (together with a clock signal and a line synchronization signal) to the register 1002 (and writes the value of the control parameter to a specified address in the register 1002). When the identification information indicates invalid data, the I / F circuit 1001 may ignore the subsequent data.

[0048] When the identification information indicates setting data, the I / F circuit 1001 switches between writing data to the register 1002 and reading data from the register 1002 in accordance with access control information received following the identification information. The access control information may be configured by one clock's worth of bits (also referred to as an access control bit) following the identification information. For example, the access control bit may indicate a data write instruction when at a low level and a data read instruction when at a high level, or vice versa.

[0049] 10 is a timing chart when image data is transmitted from the communication I / F 715 to the light-emitting chips 400-1 to 400-20. From the top to the bottom, the diagram shows changes in signal level along the time axis of a clock signal (CLK), a line synchronization signal (SYNC), and data signals on signal lines DATA1, DATA2, ..., DATA19, and DATA20. The clock signal and the line synchronization signal are signals common to the multiple light-emitting chips 400.

[0050] The clock signal (CLK) provides a clock for distinguishing each bit of the signal. The frequency of the clock signal may be, for example, 30 MHz. The communication I / F 715 can generate a clock signal of a desired frequency by frequency-converting the reference clock generated by the clock generation unit 711.

[0051] The line synchronization signal (SYNC) indicates the start timing of each line cycle in which the photoconductor 102 rotates by an angle equivalent to one pixel in the circumferential direction D2 by a rising edge of the signal level. For example, if the resolution is 1200 dpi (pixel pitch approximately 21.16 μm) and the moving speed of the surface of the photoconductor 102 is 200 mm / s, the length of one line cycle is approximately 105.8 μs.

[0052] The data signals (DATA1 to DATA20) are output in parallel to the 20 light-emitting chips 400-1 to 400-20. Starting from the rising edge of the line synchronization signal, the first two bits of each data signal are identification information indicating a high level. Valid pixel values ​​follow from the third bit onwards, and by the end of the line cycle of approximately 105.8 us, pixel values ​​corresponding to 2992 (=748 × 4) light-emitting elements 602 are serially transmitted to each light-emitting chip 400.

[0053] 11A is a timing chart when setting data is transmitted from the communication I / F 715 to the light-emitting chips 400-1 to 400-20 (i.e., when setting values ​​are written to the register 1002). From top to bottom in the figure, changes in signal levels along the time axis of a clock signal (CLK), a synchronization signal (SYNC), a data signal on a signal line DATAn, and a data signal on a signal line READn are shown. The data signal on the signal line DATAn is a signal transmitted to the light-emitting chip 400-n, and the data signal on the signal line READn is a signal returned from the light-emitting chip 400-n.

[0054] The frequency of the clock signal (CLK) for transmitting and receiving the setting data may be different from the frequency of the clock signal for transmitting and receiving the image data, and may be, for example, 3 MHz. The communication I / F 715 can generate a clock signal of a desired frequency by frequency-converting the reference clock generated by the clock generation unit 711. The synchronization signal (SYNC) here serves as an enable signal that indicates the period during which communication of the setting data is enabled, and is at a high level during the communication period.

[0055] The data signal (DATAn, n = 1, ..., 20) is transmitted in synchronization with the clock signal, starting from the rising edge of the synchronization signal. The first two bits of each data signal are identification information for identifying the setting data, consisting of a high-level first bit followed by a low-level second bit. The third bit following the identification information is an access control bit, and a low level indicates, for example, writing (W) to the register 1002, i.e., transmitting data from the communication I / F 715 to the light-emitting chip 400. The fourth to seventh bits indicate the address of the register 1002. When the identification information indicates setting data and the access control bit indicates writing (W), the I / F circuit 1001 writes information indicated by the eighth to fifteenth bits of the data signal to a specified address in the register 1002. Naturally, the address and data size are not limited to the example shown.

[0056] FIG. 11B is a timing chart when the communication I / F 715 receives setting data from the light-emitting chips 400-1 to 400-20 (that is, when the setting value is read from the register 1002).

[0057] The frequency of the clock signal (CLK) for transmitting and receiving the setting data may be, for example, 3 MHz, as in the example of Fig. 11A. The synchronization signal (SYNC) also serves as an enable signal indicating the period during which communication of the setting data is enabled, and is at a high level during the communication period.

[0058] The data signals (DATAn, n = 1, ..., 20) are transmitted in synchronization with the clock signal, starting from the rising edge of the synchronization signal. The first two bits of each data signal are identification information for identifying the setting data, consisting of a high-level first bit followed by a low-level second bit. The third bit following the identification information is an access control bit, and a high level indicates, for example, a read (R) from the register 1002, i.e., reception of data from the light-emitting chip 400 by the communication I / F 715. The fourth to seventh bits indicate the address of the register 1002. When the identification information indicates setting data and the access control bit indicates a read (R), the I / F circuit 1001 reads out the information stored at the specified address in the register 1002 and returns it as the eighth to fifteenth bits (D7 to D0) on the signal line READn.

[0059] 12 is a timing chart when invalidation data is transmitted from the communication I / F 715 to the light-emitting chips 400-1 to 400-20. From the top to the bottom, the diagram shows changes in signal levels along the time axis of a clock signal (CLK), a synchronization signal (SYNC), and data signals on signal lines DATA1, DATA2, ..., DATA19, and DATA20.

[0060] The frequency of the clock signal (CLK) may be, for example, 30 MHz. The synchronization signal (SYNC) triggers the transmission of invalidation data by rising to a high level.

[0061] The data signals (DATA1 to DATA20) indicate that invalidation data is being transmitted by setting the first bit of the first two bits of identification information to low level, starting from the rising edge of the synchronization signal. In the example of FIG. 12, the second bit is high level, but the second bit may also be low level. The third and subsequent bits of the data signal may all be low level.

[0062] As can be seen from the above description, the I / F circuit 1001 operates in one of two states: First state: writing setting information received from the communication I / F 715 to the register 1002, or sending setting information read from the register 1002 to the communication I / F 715 Second state: output of image data received from the communication I / F 715 to the light-emitting element array

[0063] In addition, the above-mentioned invalidation data is incorporated to prevent irregular transitions between operating states due to disturbances such as noise or static electricity. That is, the communication I / F 715 transmits the invalidation data to the light-emitting chips 400-1 to 400-20 when switching the operating state of the I / F circuit 1001 between the first state and the second state. Upon receiving the invalidation data, each light-emitting chip 400 transitions to an intermediate state between the first state and the second state, and then transitions to the first state or the second state based on the identification information assigned to the received data. If the I / F circuit 1001 receives image data without receiving the invalidation data while operating in the first state, the I / F circuit 1001 maintains operation in the first state. Furthermore, if the I / F circuit 1001 receives setting data without receiving the invalidation data while operating in the second state, the I / F circuit 1001 also maintains operation in the second state.

[0064] 13 is a state transition diagram showing constraints on transitions of the operating state of the I / F circuit 1001. In addition to the power-off state S0, the I / F circuit 1001 has three operating states: a first state S1, a second state S2, and an intermediate state S3.

[0065] When the power supply voltage VCC is applied, the I / F circuit 1001 transitions from the power-off state S0 to the intermediate state S3. The intermediate state S3 is the state in which invalidation data was received immediately before (or the power was turned on immediately before). When the I / F circuit 1001 receives identification bits "High+Low" indicating setting data in the intermediate state S3, it transitions to the first state (transition T31). When the I / F circuit 1001 receives identification bits "High+High" indicating image data in the intermediate state S3, it transitions to the second state (transition T32). When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalidation data in the intermediate state S3, it maintains the intermediate state (transition T33). Note that "Any" means that either "High" or "Low" is acceptable.

[0066] When the I / F circuit 1001 receives identification bits "High+Low" indicating setting data in the first state S1, it maintains the first state (transition T11). Even if the I / F circuit 1001 receives identification bits "High+High" indicating image data in the first state S1, the I / F circuit 1001 ignores the subsequent data and maintains the first state because transition T12 to the second state is prohibited. When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalid data in the first state S1, it transitions to the intermediate state (transition T13).

[0067] Even if the I / F circuit 1001 receives identification bits "High+Low" indicating setting data in the second state S2, the transition to the first state T21 is prohibited, so the I / F circuit 1001 ignores the subsequent data and maintains the second state. When the I / F circuit 1001 receives identification bits "High+High" indicating image data in the second state S2, it maintains the second state (transition T22). When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalid data in the second state S2, it transitions to the intermediate state (transition T23).

[0068] By thus interposing an intermediate state between the first state and the second state, even if an error in transmitting the identification bit occurs due to an external disturbance, it is possible to avoid a situation in which incorrect data is written to the register 1002 or output to the light-emitting element 602.

[0069] FIG. 14 is a timing chart of data communication in a scenario in which an error in interpretation of identification information occurs during transmission of image data. FIG. 14 illustrates the transmission of image data from the kth line to the k+3th line, which is sent to the light-emitting chip 400-1 via the signal line DATA1, along with a clock signal (CLK) and a line synchronization signal (SYNC). First, the I / F circuit 1001 of the light-emitting chip 400-1 operates in the second state because the identification information of the kth line is “High+High.” The I / F circuit 1001 sequentially receives image data for the 2992 light-emitting elements of the kth line and outputs the data to the data holding unit 1003. Next, the I / F circuit 1001 of the light-emitting chip 400-1 maintains the second state because the identification information of the k+1th line is also “High+High.” The I / F circuit 1001 sequentially receives image data for the k+1th line and outputs the image data to the data holding unit 1003. After that, an error occurs in the second bit of the identification information of the k+2th line, and the identification information is interpreted as “High+Low,” which indicates setting data. However, the I / F circuit 1001 of the light-emitting chip 400-1 has not received the invalidation data and is in the second state, not the intermediate state, so it does not transition to the first state and ignores the bit sequence received following the invalid identification information. As a result, the drive signals based on the image data of the (k+1)th line continue to be supplied to the 2992 light-emitting elements without being updated, and the image of the (k+2)th line becomes the same as the image of the (k+1)th line. Next, because the identification information of the (k+3)th line is "High+High," the I / F circuit 1001 of the light-emitting chip 400-1 maintains the second state, sequentially receives image data of the (k+3)th line, and outputs it to the data holding unit 1003.

[0070] Here, assume that the first bit of the identification information of the (k+2)th line is erroneously interpreted as "Low" (i.e., invalidation data), and the second bit of the identification information of the (k+3)th line is erroneously interpreted as "Low" (i.e., configuration data). In this case, the I / F circuit 1001 transitions to an intermediate state in response to receiving the invalidation data, and then erroneously transitions to the first state for receiving the configuration data. However, the probability that such a transmission error occurs consecutively by chance when two pieces of identification information are received is extremely low. Normally, even if the identification information that should indicate image data is erroneously interpreted as indicating invalidation data, the next identification information again indicates image data, and the I / F circuit 1001 can properly return to the second state.

[0071] <4. Individual setting mode and common setting mode> As described above, the communication I / F 715 can transmit setting information for setting the operation of each of the light-emitting chips 400 to the plurality of slave devices, the light-emitting chips 400. The setting information is written to the register 712 of the image controller 710 by the CPU 701, read by the setting data processing unit 714, and transmitted to the light-emitting chips 400 by the communication I / F 715. Therefore, in order to transmit setting information to each of the 20 light-emitting chips 400-1 to 400-20, the CPU 701 must repeatedly write the setting information to the register 712 via the serial communication line 20 times. However, at least a portion of the setting information is information that should be commonly applied to the plurality of light-emitting chips 400. Therefore, in this embodiment, a mechanism is adopted that can omit redundant writing of such common setting information to the register 712.

[0072] In this embodiment, the communication I / F 715 operates in either a first operation mode or a second operation mode with respect to transmitting setting information to the plurality of light-emitting chips 400. The first operation mode is a mode in which a plurality of pieces of individual setting information read from the first storage area 721 of the register 712 are transmitted to the plurality of light-emitting chips 400, respectively. In the following description, the first operation mode is referred to as the individual setting mode. The second operation mode is a mode in which common setting information read from the first storage area 721 of the register 712 is transmitted to the plurality of light-emitting chips 400. In the following description, the second operation mode is referred to as the common setting mode. The second storage area 722 of the register 712 stores control information indicating whether the communication I / F 715 should operate in the individual setting mode or the common setting mode. When the control information written in the second storage area 722 indicates a first value, the communication I / F 715 operates together with the setting data processing unit 714 in the individual setting mode. Furthermore, when the control information written to the second storage area 722 indicates the second value, the communication I / F 715 operates together with the setting data processing unit 714 in the common setting mode.

[0073] Fig. 15 is a table showing an example of the configuration of register 712 of image controller 710. As described above, register 712 includes first storage area 721 and second storage area 722. In the example of Fig. 15, first storage area 721 is a storage area from addresses '0x00' to '0x28' expressed in hexadecimal. Second storage area 722 is a storage area from addresses '0x29' to '0x31'.

[0074] Addresses '0x00' to '0x13' of the first storage area 721 store individual setting information (s_data_01, s_data_02, ..., s_data_20) to be individually applied to the light-emitting chips 400-1 to 400-20, respectively. Each individual setting information may be, for example, 8 bits. Addresses '0x14' to '0x27' of the first storage area 721 store addresses (s_address_01, s_address_02, ..., s_address_20) of the registers 1002 of the light-emitting chips 400-1 to 400-20 to which the corresponding individual setting information should be written, respectively. Each individual address information may be, for example, 4 bits. Address '0x28' of the first storage area 721 stores common setting information (s_data_common) to be commonly applied to the light-emitting chips 400-1 to 400-20. The common setting information may be at most 8 bits, and in the example of FIG. 15, it is 1 bit.

[0075] Address '0x29' of the second storage area 722 stores a flag (start_write_common) for instructing the communication I / F 715 to perform a write operation in the common setting mode. Address '0x30' of the second storage area 722 stores a flag (start_write_separate) for instructing the communication I / F 715 to perform a write operation in the individual setting mode. Address '0x31' of the second storage area 722 stores a flag (start_read) for instructing the communication I / F 715 to perform a read operation. Each of these three flags may be 1 bit. Note that the configurations of the first storage area 721 and the second storage area 722 are not limited to the above-mentioned examples. For example, two values ​​of a single flag for setting the operation mode may instruct a write operation in the common setting mode or a write operation in the individual setting mode.

[0076] When instructing a write operation in the individual setting mode, the CPU 701 writes a value of '1' to address '0x30' of the second storage area 722. The values ​​of the other two flags may be '0'. When the flag start_write_separate at address '0x30' indicates a value of '1' (first value), the setting data processing unit 714 and the communication I / F 715 start a write operation in the individual setting mode. In the individual setting mode, the setting data processing unit 714 outputs setting data for the light-emitting chip 400-1, which is composed of individual setting information read from address '0x00' and address information read from address '0x14', to the communication I / F 715. The communication I / F 715 assigns access control information to this setting data for the light-emitting chip 400-1 and transmits it to the light-emitting chip 400-1. Furthermore, the setting data processing unit 714 outputs setting data for the light-emitting chip 400-2, which is composed of individual setting information read from address '0x01' and address information read from address '0x15', to the communication I / F 715. The communication I / F 715 assigns access control information to this setting data for the light-emitting chip 400-2 and transmits it to the light-emitting chip 400-1. Transmission of setting data to the other light-emitting chips 400 in the individual setting mode is performed in a similar manner.

[0077] For example, the first address of the register 1002 of each light-emitting chip 400 is an address that stores an individual adjustment value for the light intensity of the light-emitting element array of each light-emitting chip 400. The second address of the register 1002 of each light-emitting chip 400 is an address that stores an individual setting value that indicates whether the power saving mode of each light-emitting chip 400 is on or off, and other setting information. The values ​​of these first addresses or second addresses (or other addresses) are written by the CPU 701 to addresses '0x14' to '0x27' of the first memory area 721 depending on the purpose of setting.

[0078] When instructing a write operation in the common setting mode, the CPU 701 writes a value of '1' to address '0x29' in the second storage area 722. The values ​​of the other two flags may be '0'. When the flag start_write_common at address '0x29' indicates a value of '1' (second value), the setting data processing unit 714 and the communication I / F 715 start a write operation in the common setting mode. In the common setting mode, the communication I / F 715 transmits setting data including common setting information read from address '0x28' to the light-emitting chips 400-1 to 400-20. As an example, the address of the register 1002 to which the common setting information is written in the common setting mode may be the same as the address of the register 1002 to which the individual setting information stored in addresses '0x14' to '0x27' is written. As another example, the first storage area 721 may further store control information (not shown) indicating the address of the register 1002 to which the common setting information is written in the common setting mode.

[0079] In one embodiment, in the common setting mode, the communication I / F 715 overwrites part of the individual setting information read from the first storage area 721 with the common setting information and transmits the common setting information along with the remaining individual setting information to the light-emitting chips 400-1 to 400-20. For example, turning the power-saving mode on or off can be indicated by a single setting bit, which is smaller than the maximum size of 8 bits of setting information that can be transmitted in a single transmission operation. Therefore, by predefining a specific signal position in an 8-bit signal sequence as a bit for setting the power-saving mode, the bit at this signal position can be uniformly interpreted as a bit for setting the power-saving mode regardless of the operating mode. Other signal positions can be used for other setting information. That is, in this embodiment, each of the light-emitting chips 400-1 to 400-20 interprets the setting information received via the corresponding data signal line according to a fixed signal format that is independent of the operating mode of the communication I / F 715. The predefined signal positions of the signal format are shared for transmitting individual setting values ​​in the individual setting mode and common setting values ​​in the common setting mode. With this configuration, there is no need to implement different processing in the light-emitting chip 400 depending on the operating mode of the communication I / F 715, so the configuration of the light-emitting chip 400 can be avoided from becoming complicated, and an increase in the manufacturing cost of the device can be suppressed.

[0080] Fig. 16A is a timing chart of transmission of setting data to the light-emitting chip 400 in the individual setting mode. Fig. 16B is a timing chart of transmission of setting data to the light-emitting chip 400 in the common setting mode. Although these figures only show transmission of setting data to the light-emitting chip 400-1, transmission of setting data to the light-emitting chips 400-2 to 400-20 can be performed in the same way.

[0081] Here, the size of the individual setting information is 8 bits, and the size of the common setting information is 1 bit. Furthermore, in the signal format for transmitting setting data, the fifth signal position D3 of the signal sequence D7-D0 is defined to represent the setting value of the power saving mode.

[0082] As described in relation to FIG. 11A, the frequency of the clock signal (CLK) for transmitting and receiving the setting data may be, for example, 3 MHz. The synchronization signal (SYNC) is at a high level during the communication of the setting data. In both FIGS. 16A and 16B, the first two bits of the data signal (DATA1) are identification information for identifying the setting data, consisting of a high-level first bit and a low-level second bit. The third bit following the identification information is an access control bit, which, for example, indicates a write (W) to the register 1002 when set to a low level. The fourth to seventh bits indicate a bit string s_address_01[3:0] obtained from the first storage area 721 as an address to which the setting information is to be written. Here, X and Y in [X:Y] represent the digit position, and Z[X:Y] represents the third to zeroth digits of the variable Z. The eighth to fifteenth bits indicate the setting information to be written to a specified address in the register 1002 of the light-emitting chip 400-1.

[0083] 16A, the 8th to 15th bits of the setting information D7 to D0 in the individual setting mode indicate the bit string s_data_01[7:0] acquired from the first storage area 721. This is an 8-bit individual setting value for the light-emitting chip 400-1. On the other hand, referring to FIG. 16B, the 8th to 15th bits of the setting information D7 to D0 in the common setting mode indicate the following values: D7~D4=s_data_01[7:4] (7th to 4th digits of individual setting value s_data_01) D3=s_data_common (Common setting value) D2~D0=s_data_01[2:0] (2nd to 0th digits of individual setting value s_data_01) 16A, in the common setting mode, the common setting value is overwritten at the fifth signal position D3 of the setting information. However, regardless of whether the communication I / F 715 is operating in the individual setting mode or the common setting mode, the light-emitting chip 400-1 interprets the received setting information in a certain signal format and sets the operation of the light-emitting chip 400-1.

[0084] When instructing a read operation, the CPU 701 writes a value of '1' to address '0x31' in the second storage area 722. The values ​​of the other two flags may be '0'. When the flag start_read at address '0x31' indicates a value of '1', the setting data processing unit 714 and the communication I / F 715 start the read operation. In the read operation, the setting information read from the specified addresses of the registers 1002 of the light-emitting chips 400-1 to 400-20 is output to the CPU 701 in sequence.

[0085] As an example of the use of the above-described operation mode, the CPU 701 may write individual adjustment values ​​for the light intensity to the register 712 during initial configuration before shipping the product, and set the communication I / F 715 to the individual setting mode. In this case, the communication I / F 715 operating in the individual setting mode transmits the individual adjustment values ​​read from the register 712 to each of the light-emitting chips 400-1 to 400-20. As a result, the photosensitive element 102 is exposed to a uniform amount of light across the plurality of light-emitting chips 400, making it possible to form a high-quality image with no unevenness in the amount of light.

[0086] As another example, before starting execution of a print job, the CPU 701 may write individual setting values ​​for a power-saving mode to the register 712 so as not to apply voltage to light-emitting element arrays that are outside the range of the sheet size being used, and set the communication I / F 715 to the individual setting mode. In this case, the communication I / F 715 operating in the individual setting mode transmits the individual setting values ​​read from the register 712 to each of the light-emitting chips 400-1 to 400-20. As a result, the power-saving modes of some of the light-emitting chips 400 located at the left and right ends in the main scanning direction are enabled, and application of voltage to light-emitting element arrays that are not being used is stopped, thereby reducing power consumption of the exposure head 106.

[0087] As another example, the CPU 701 may write a common setting value to the register 712 to temporarily stop the application of voltage to the light-emitting element array between successive sheets during execution of a print job spanning multiple sheets, and set the communication I / F 715 to the common setting mode. In this case, the communication I / F 715 operating in the common setting mode transmits the common setting value read from the register 712 to each of the light-emitting chips 400-1 to 400-20. As a result, the application of voltage to the light-emitting element arrays of all the light-emitting chips 400 is temporarily stopped, which also reduces the power consumption of the exposure head 106. Furthermore, in this example, the CPU 701 does not need to write redundant setting values ​​to the register 712. This reduces the time required for communication control and improves job execution productivity.

[0088] The signal position at which the common setting value is transmitted in the signal format for transmitting setting data is not limited to that in the above-described embodiment. For example, the communication I / F 715 may transmit the common setting value at a different signal position depending on the write address indicated by the address information in the first storage area 721 of the register 712. Alternatively, the communication I / F 715 may change the signal position at which the common setting value is transmitted based on additional control information (not shown) read from the second storage area 722 of the register 712.

[0089] <5. Processing flow> Fig. 17 is a flowchart showing an example of the flow of chip setting processing that can be performed by the communication system 200 according to the above-described embodiment. The chip setting processing in Fig. 17 can be performed by the communication system 200 at any time when the setting of the light-emitting chip 400 needs to be changed, such as during initial setup before shipping a product, or before, after, or during execution of a print job. At the start of communication processing, default setting information for the light-emitting chips 400-1 to 400-20 is written in the first storage area 721 of the register 712 of the image controller 710. In the following description, processing steps are abbreviated as 'S'.

[0090] First, in S11, the communication process branches depending on whether the common setting mode or the individual setting mode is used to set the light-emitting chips 400-1 to 400-20. If the common setting mode is used, the process proceeds to S12. On the other hand, if the individual setting mode is used, the process proceeds to S14.

[0091] In S12, the CPU 701 writes common setting information to be commonly applied to the light-emitting chips 400-1 to 400-20 to the first storage area 721 of the register 712 via the serial communication line 211. For example, the CPU 701 performs a single write operation to address '0x28' (s_data_common) of the first storage area 721. Next, in S13, the CPU 701 writes control information including a value indicating the common setting mode to the second storage area 722 of the register 712 (for example, start_write_common='1', start_write_separate='0').

[0092] Meanwhile, in S14, the CPU 701 repeatedly writes 20 pieces of individual setting information to be individually applied to the light-emitting chips 400-1 to 400-20 to the first storage area 721 of the register 712 via the serial communication line 211. For example, the CPU 701 repeatedly writes 20 pieces of individual setting information to addresses '0x00' to '0x13' (s_data_01, ..., s_data_20) in the first storage area 721. Note that the CPU 701 also repeatedly writes address information to addresses '0x14' to '0x27' (s_address_01, ..., s_address_20) in the first storage area 721 as necessary. Next, in S15, the CPU 701 writes control information including a value indicating the individual setting mode to the second storage area 722 of the register 712 (for example, start_write_common='0', start_write_separate='1').

[0093] The subsequent steps S16 to S24 are repeated for each of the 20 light-emitting chips 400-1 to 400-20. Hereinafter, the initial value of the variable i is set to 1.

[0094] In S16, the setting data processing unit 714 generates setting data for the i-th light-emitting chip 400-i based on the i-th address information and individual setting information read from the first storage area 721.

[0095] Next, in S17, the setting data processing unit 714 references the control information written in the second storage area 722 and determines whether the operation mode of the communication I / F 715 is the common setting mode or the individual setting mode. If the operation mode of the communication I / F 715 is the common setting mode, in S18 the setting data processing unit 714 overwrites the common setting value read from the first storage area 721 at a predetermined signal position of the setting data generated in S16. On the other hand, if the operation mode of the communication I / F 715 is the individual setting mode, S18 is skipped.

[0096] Next, in S21, the communication I / F 715 transmits the setting data for the i-th light-emitting chip 400-i, which is generated by the setting data processing unit 714, to the light-emitting chip 400-i via the data signal line DATAi. The light-emitting chip 400-i stores the setting information at a specified address in the register 1002, based on the address information of the setting data received from the communication I / F 715.

[0097] Next, in S22, the communication I / F 715 operates in read mode and receives the setting information read from the i-th light-emitting chip 400-i from the same address as the address specified in S21. The communication I / F 715 outputs the received setting information to the CPU 701 via the setting data processing unit 714.

[0098] Next, in S23, the CPU 701 verifies whether the setting information read from the i-th light-emitting chip 400-i in S22 matches the setting information to be written to the light-emitting chip 400-i. If the setting information does not match, it is determined that a write error has occurred, and the process returns to S21, where the setting data is resent to the i-th light-emitting chip 400-i. If the setting information matches, it is determined that the writing was successful, and the process proceeds to S24.

[0099] In S24, the CPU 701 determines whether the variable i has reached 20, which is the number of the light-emitting chips 400. If the variable i has not reached 20, the variable i is incremented in S25, and the above-described steps S16 to S24 are repeated for the next light-emitting chip 400-i. If the variable i has reached 20, the process proceeds to S31.

[0100] In S31, the communication I / F 715 transmits invalidation data to the light emitting chips 400-1 to 400-20, thereby enabling the state transition of the I / F circuits 1001 of the light emitting chips 400-1 to 400-20.

[0101] 18 is a flowchart showing an example of the flow of job control processing that can be performed by communication system 200 according to the above-described embodiment. The job control processing in FIG. 18 is started, for example, in response to acceptance of a print job from a user, and can be performed by CPU 701 and image controller 710 working together.

[0102] First, in S110, prior to execution of a print job, the communication I / F 715 performs the chip setting process described with reference to Fig. 17 under the control of the CPU 701. For example, the communication I / F 715 may operate in the individual setting mode and transmit to the light-emitting chips 400-1 to 400-20 individual adjustment values ​​for individually adjusting the light intensity of the light-emitting element arrays 1005. Additionally or alternatively, the communication I / F 715 may operate in the individual setting mode and transmit to the corresponding light-emitting chips 400 individual setting values ​​for not applying voltage to the light-emitting element arrays 1005 that are outside the range of the sheet size.

[0103] Next, in S111, the communication I / F 715 waits until the sheet is conveyed to a predetermined position. When the timing to start printing (light emission control) arrives, the process proceeds to S113.

[0104] In S113, the communication I / F 715 transmits one line of image data to the light emitting chips 400-1 to 400-20 during the line period indicated by the line synchronization signal. The light emitting element arrays 1005 of the light emitting chips 400-1 to 400-20 are supplied with drive signals based on the image data received from the communication I / F 715. As a result, the light emitted from the light emitting element arrays 1005 exposes the photosensitive member 102, thereby forming one line of a latent image on the surface of the photosensitive member 102.

[0105] The transmission of image data to the light-emitting chips 400-1 to 400-20 in S113 is repeated until it is determined in S115 that the transmission of the final line of input image data has ended. When it is determined that the transmission of the final line of data has ended, the process proceeds to S117. In S117, the communication I / F 715 transmits invalidation data to the light-emitting chips 400-1 to 400-20.

[0106] Subsequent processing branches depending on whether printing of the final page of the print job has finished. If printing of the final page has not finished, processing proceeds to S120. On the other hand, if printing of the final page has finished, processing proceeds to S130.

[0107] S120 represents chip setting processing between successive sheets during execution of a print job spanning multiple sheets. In S120, the communication I / F 715 operates in the common setting mode and transmits, for example, a common setting value (indicating that the power saving mode is on) to the light-emitting chips 400-1 to 400-20 to temporarily stop application of voltage to the light-emitting element array 1005. The application of voltage to the light-emitting element array 1005 can be resumed by transmitting a common setting value indicating that the power saving mode is off to the light-emitting chips 400-1 to 400-20 immediately before the next sheet is transported to the predetermined position.

[0108] S130 represents chip setting processing after the execution of the print job is completed. In S130, the communication I / F 715 operates in the common setting mode and transmits, for example, a common setting value for stopping the application of voltage to the light-emitting element array 1005 to the light-emitting chips 400-1 to 400-20.

[0109] <6. Summary> Various embodiments and examples of the technology according to the present disclosure have been described above using FIGS. 1 to 18. In the above-described embodiments, a communication interface connected to multiple devices reads multiple pieces of individual setting information from a first storage unit and transmits them to the multiple devices when control information written to a second storage unit by a control unit includes a first value indicating an individual setting mode. Furthermore, when control information written to a second storage unit includes a second value indicating a common setting mode, the communication interface reads common setting information from the first storage unit and transmits it to the multiple devices. This configuration enables flexible switching between transmitting individual setting information to multiple devices and transmitting common setting information. In the common setting mode, only one write operation is required for the control unit to write setting values ​​to be transmitted to the multiple devices to the first storage unit. This reduces the communication load for configuring multiple devices, shortens communication time, and improves productivity. In particular, the above-described embodiments are suitable for operation during execution of a print job in an image forming apparatus in which multiple light-emitting chips are involved in exposing a photoconductor.

[0110] Furthermore, in the above-described embodiment, when the communication interface operates in the common setting mode, it can overwrite part of the individual setting information read from the first storage unit with the common setting information and transmit the common setting information together with the remaining part of the individual setting information to multiple devices. Each device only needs to interpret the setting information received via the corresponding signal line in accordance with a fixed signal format, and does not need to switch setting operations depending on the operating mode of the communication interface. This configuration can avoid complicating the configuration of each device and suppress increases in the manufacturing costs of the device.

[0111] In the above-described embodiment, the setting information may include a setting value for determining whether or not to apply a voltage to the drive circuit of the light-emitting element array of the light-emitting chips involved in exposing the photosensitive member. This configuration allows the power-saving mode to be set individually for each light-emitting chip before and after the execution of a print job, or allows the power-saving mode to be quickly turned on / off simultaneously for all light-emitting chips during the execution of a print job. This effectively reduces power consumption in the light-emitting element array.

[0112] Although the present specification has mainly described an example in which the above-described communication system is implemented in an exposure device of an image forming apparatus that forms images using an electrophotographic method, the present invention is not limited to such an example. The above-described communication system may also be applied to image forming apparatuses that form images using other methods, and to devices other than image forming apparatuses.

[0113] Furthermore, although specific numerical values ​​are used in this specification for the purpose of explanation, these specific numerical values ​​are merely examples, and the present invention is not limited to the specific numerical values ​​used in the embodiments. Specifically, the number of light-emitting chips provided on one printed circuit board is not limited to 20 and may be any number equal to or greater than 1. Furthermore, the size of the light-emitting element array of each light-emitting chip 400 is not limited to 4 rows and 748 columns and may be any other size. Furthermore, the circumferential pitch and axial pitch of the light-emitting elements are not limited to approximately 21.16 μm and approximately 5 μm and may be any other value.

[0114] <7. Other embodiments> The above-described embodiment can also be realized in the form of a process in which a program for realizing one or more functions is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., an ASKC) that realizes one or more functions.

[0115] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0116] 1: image forming apparatus, 101a to 101d: image forming unit, 102: photosensitive member, 106: exposure head (exposure device), 200: communication system, 202: printed circuit board (first board), 210: control board (second board), 211: serial communication line, 400-1 to 400-20: light emitting chips (devices), 406: circuit unit, 602: light emitting element, 701: CPU (control unit), 710: image controller, 712: register, 715: communication interface, 721: first storage area (first storage unit), 722: second storage area (second storage unit), 1004: current drive unit (drive circuit), 1005: light emitting element array, DATA1 to DATA20: data signal lines

Claims

1. Multiple devices and a communication interface connected to the plurality of devices via a plurality of signal lines; a first storage unit that stores setting information to be transmitted from the communication interface to the plurality of devices; a second storage unit that stores control information that indicates an operation mode of the communication interface; a control unit that controls an operation of the communication interface by writing the control information to the second storage unit; Equipped with the first storage unit stores a plurality of pieces of individual setting information to be applied individually to the plurality of devices and common setting information to be applied commonly to the plurality of devices; The communication interface includes: When the control information written in the second storage unit includes a first value indicating a first operation mode, reading out the plurality of pieces of individual setting information from the first storage unit and transmitting the read out plurality of pieces of individual setting information to the plurality of devices; When the control information written to the second storage unit includes a second value indicating a second operation mode, reading the common setting information from the first storage unit and transmitting the read common setting information to the plurality of devices. Communication system.

2. 2. The communication system of claim 1, wherein when the control information written to the second memory unit includes the second value, the communication interface overwrites a portion of the individual setting information read from the first memory unit with the common setting information read from the first memory unit, and transmits the common setting information together with the remainder of the individual setting information to the plurality of devices.

3. 3. The communication system according to claim 2, wherein each of the plurality of devices interprets the setting information received via the corresponding signal line in accordance with a fixed signal format independent of the operation mode of the communication interface.

4. The communication system according to claim 3 , wherein the common setting information is transmitted to each of the plurality of devices in a predefined signal position of the fixed signal format.

5. The communication system according to claim 1 , wherein the first storage unit and the second storage unit are different storage areas of the same register.

6. the communication interface is mounted on a first substrate together with the register; the control unit is mounted on a second board different from the first board, and writes information to the register via a serial communication line; The communication system according to claim 5 .

7. An image forming apparatus for forming an image on a sheet, A photoreceptor; an exposure device that exposes the photosensitive member; Equipped with The exposure apparatus includes the communication system according to any one of claims 1 to 6, each of the plurality of devices is a light-emitting chip having an array of light-emitting elements used to expose the photosensitive member; Image forming device.

8. 8. The image forming apparatus according to claim 7, wherein the individual setting information includes an individual setting value for setting whether or not a voltage is applied to a drive circuit of the light emitting element array in each device.

9. the common setting information includes a common setting value for commonly setting whether or not to apply a voltage to a drive circuit of the light-emitting element array in the plurality of devices; when the control information written to the second storage unit includes the second value, the communication interface overwrites the common setting value read from the first storage unit at a signal position for the individual setting value of the individual setting information read from the first storage unit, and transmits the common setting value together with the rest of the individual setting information to the plurality of devices. The image forming apparatus according to claim 8 .

10. the light emitting element array of the plurality of devices is arranged along a main scanning direction parallel to a rotation axis of the photosensitive member, the communication interface operates in the first operation mode during execution of a print job, and transmits to a corresponding device the individual setting value for preventing voltage from being applied to the light-emitting element array that is outside the range of sheet sizes; The image forming apparatus according to claim 8 .

11. the communication interface operates in the second operation mode between successive sheets during execution of a print job spanning multiple sheets, and transmits to the multiple devices a common setting value for temporarily stopping application of voltage to the light-emitting element arrays of the multiple devices; The image forming apparatus according to claim 7 .

12. The image forming apparatus according to claim 7 , wherein the individual setting information includes an individual adjustment value for individually adjusting the light intensity of the light emitting element array in each device.

Images