Power loss protection circuit, data storage module, and server

Abstract

To provide a PLP circuit 200 suitable for a system supplied with a high bus voltage.SOLUTION: A first input terminal in receives, as an input voltage VIN, a voltage generated by an intermediate bus converter 40, which steps down a DC bus voltage VBUS. A second input terminal bus receives the DC bus voltage VBUS. A capacitor connection terminal STR is connected to an external backup capacitor 102. A first switch SW1 is connected between the first input terminal in and an output terminal out. A charging circuit 110 is connected between the second input terminal bus and the capacitor connection terminal STR. An internal converter 120 steps up or down the voltage VSTR at the capacitor connection terminal STR, and stabilizes the output voltage Vout generated at the output terminal out to a target level.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power loss protection circuit. [Background technology]

[0002] A stable supply of power supply voltage is essential for electronic components. A momentary power interruption in the power supply voltage of storage devices such as solid-state drives and hard disks can result in the destruction or loss of stored data. Even after the input voltage is cut off, it is necessary to maintain the power supply voltage for a period of time during which the load performs necessary protection processes such as data evacuation. This function is called power interruption protection, PLP (Power Loss Protection), PLI (Power Loss Imminent), or PFP (Power Failure Protection).

[0003] 1 is a block diagram of a system with a PLP function. The system 2 includes a main power supply 10, a load 20, and a backup circuit 30. The main power supply 10 supplies an AC voltage V AC The bus voltage (input voltage) V is about 12V. BUS Generates the bus voltage V BUS is supplied to the backup circuit 30 and other circuits (not shown).

[0004] The load 20 includes a PMIC (power management circuit) 22 and multiple electronic components 24_1 to 24_n. The PMIC 22 is connected to a 12V power supply voltage V DD The power supply circuit 24 receives the power from the power source 24, boosts or lowers the voltage of the power supply, and supplies the power supply to the electronic components 24_1 to 24_n.

[0005] The backup circuit 30 is provided between the main power supply 10 and the load 20. The backup circuit 30 includes a switch 32, a backup capacitor , and a boost converter .

[0006] The switch 32 is provided on a power line 38 connecting the main power supply 10 to the load 20. The available bus voltage V BUSWhile the bus voltage V BUS is the power supply voltage V DD The boost converter 36 has an input terminal IN connected to a power supply line 38 and an output terminal OUT connected to the backup capacitor 34. The boost converter 36 converts the bus voltage V BUS While the bus voltage V BUS is boosted and the backup capacitor 34 is charged. The capacitance of the backup capacitor 34 is C, and the voltage generated in the backup capacitor 34 is V STR Then, the charge Q and energy E stored in the backup capacitor 34 are expressed by the following equations: Q=C·V STR E is E=C·V STR 2 / 2

[0007] The backup circuit 30 is connected to the bus voltage V BUS When the interruption (loss) of the power supply is detected, the switch 32 is turned off. The boost converter 36 then operates in the reverse direction as a step-down converter with the OUT side as the input and the IN side as the output, and the capacitor voltage V STR , the power supply voltage V DD and supplies it to the load 20.

[0008] In applications such as servers, the bus voltage V BUS There is a trend to change the bus voltage V to a higher voltage (42V to 58V). BUS Increasing this reduces the current required to transmit the same amount of power, and reduces the power consumption in the wiring (cable), which is proportional to the square of the current.

[0009] [overview] The present disclosure has been made in light of this situation, and one exemplary purpose of an embodiment thereof is to provide a power loss protection circuit suitable for a system supplied with a high bus voltage.

[0010] A power loss protection circuit according to one embodiment of the present disclosure includes a first input terminal that receives as an input voltage a voltage generated by an intermediate bus converter that steps down a DC bus voltage; a second input terminal that receives the DC bus voltage or a voltage lower than a DC bus voltage generated based on the DC bus voltage; a capacitor connection terminal to which an external capacitor is to be connected; an output terminal to which a load is to be connected; a first switch connected between the first input terminal and the output terminal; a charging circuit connected between the second input terminal and the capacitor connection terminal; and an internal converter that receives the voltage at the capacitor connection terminal and stabilizes an output voltage generated at the output terminal to a target level.

[0011] Another aspect of the present disclosure is a data storage module detachably attached to a server. The data storage module includes: a first terminal for receiving a first voltage from the server, the first voltage being the output voltage of an intermediate bus converter; a second terminal for receiving a second voltage from the server, the second voltage being the input voltage of the intermediate bus converter or a voltage lower than the input voltage generated based on the input voltage; a power supply circuit; and a power loss protection circuit that receives the first and second voltages and supplies the power supply voltage to the power supply circuit. The power loss protection circuit includes a capacitor, a first switch connected between the first terminal and an input terminal of the power supply circuit, a charging circuit connected between the second terminal and the capacitor, and an internal converter that receives the voltage of the capacitor and supplies an output voltage regulated at a target level to the power supply circuit.

[0012] Another aspect of the present disclosure relates to a server configured to allow the above-described data storage module to be attached and detached. The server includes a third terminal for receiving a voltage generated by an intermediate bus converter that steps down the DC bus voltage, a fourth terminal for receiving the DC bus voltage, a fifth terminal to be connected to the first terminal of the data storage module, a sixth terminal to be connected to the second terminal of the data storage module, a first wire connecting the third terminal and the fifth terminal, and a second wire connecting the fourth terminal and the sixth terminal.

[0013] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of a system with PLP functionality. [Figure 2] FIG. 2 is a circuit diagram of a system including a backup circuit according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram of a backup circuit according to the first embodiment. [Figure 4] FIG. 4 is a time chart illustrating the operation of the backup circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram of a backup circuit according to the second embodiment. [Figure 6] FIG. 6 is a time chart illustrating the operation of the backup circuit of FIG. [Figure 7] FIG. 7 is a circuit diagram of a backup circuit according to the third embodiment. [Figure 8] FIG. 8 is a circuit diagram of a backup circuit according to the fourth embodiment. [Figure 9] FIG. 9 is a circuit diagram of a backup circuit according to a fifth embodiment. [Figure 10] FIG. 10 is a circuit diagram of a backup circuit according to a sixth embodiment. [Figure 11] FIG. 11 is a circuit diagram of a backup circuit according to a seventh embodiment. [Figure 12] FIG. 12 is a circuit diagram of a system including a backup circuit according to an eighth embodiment. [Figure 13] FIG. 13 is a circuit diagram of a system according to a ninth embodiment. [Figure 14]FIG. 14 is a circuit diagram of the computer system.

[0015] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0016] In one embodiment, the power loss protection circuit includes a first input terminal that receives as an input voltage a voltage generated by an intermediate bus converter that steps down a DC bus voltage; a second input terminal that receives the DC bus voltage or a voltage lower than a DC bus voltage generated based on the DC bus voltage; a capacitor connection terminal to which an external capacitor is to be connected; an output terminal to which a load is to be connected; a first switch connected between the first input terminal and the output terminal; a charging circuit connected between the second input terminal and the capacitor connection terminal; and an internal converter that receives the voltage at the capacitor connection terminal and stabilizes the output voltage generated at the output terminal to a target level.

[0017] With this configuration, a DC bus voltage of approximately 40 to 50 V, or a DC voltage derived from it, is supplied to the power loss protection circuit, and this DC bus voltage is used to charge the backup capacitor, eliminating the need for a boost converter as in the past. This reduces losses. Furthermore, while the boost converter's operating mode had to be switched in the past, this configuration eliminates the need for switching because the internal converter only operates in one direction, in buck mode.

[0018] In one embodiment, the voltage on the capacitor may be higher than the input voltage. The internal converter may be a buck converter or a buck-boost converter.

[0019] In one embodiment, the voltage on the capacitor is lower than the input voltage and the internal converter may be a boost converter.

[0020] In one embodiment, the target level of the internal converter is lower than the input voltage, and the internal converter may operate at all times regardless of the presence or absence of an input voltage. This configuration eliminates the need to enable and disable the internal converter depending on the input voltage. Furthermore, while the input voltage is normally supplied, the internal converter is in a light load state and operates in PFM (pulse frequency modulation) mode, so keeping the internal converter enabled at all times only slightly increases switching loss.

[0021] In one embodiment, the internal converter may be enabled when the input voltage is interrupted.

[0022] In one embodiment, the charging circuit includes a second switch, and the on-resistance of the second switch may be higher than the on-resistance of the first switch. Since the charging speed may be slow, an increase in the circuit area can be suppressed by using elements with large on-resistance, i.e., small size.

[0023] In one embodiment, the power loss protection circuit may further include a third switch connected between the output of the internal converter and the output terminal, and a switch control circuit that controls the third switch.

[0024] In one embodiment, the switch control circuit may turn off the third switch when the voltage at the capacitor connection terminal is lower than the output voltage, thereby preventing the backup capacitor from being charged via the internal converter.

[0025] In one embodiment, the switch control circuit may limit the current flowing through the third switch, thereby preventing the backup capacitor from being charged with an excessive current via the internal converter.

[0026] In one embodiment, the switch control circuit may perform soft start control on the third switch.

[0027] In one embodiment, the charging circuit may operate so that the voltage at the capacitor connection terminal does not exceed a predetermined voltage of 35 V or less. This makes it possible to use an element with a 35 V withstand voltage as the backup capacitor, thereby reducing costs.

[0028] In one embodiment, the charging circuit may include a second switch and a control circuit that turns off the second switch when the voltage at the capacitor connection terminal exceeds a predetermined voltage.

[0029] In one embodiment, the charging circuit may include a regulator that stabilizes the voltage at the capacitor connection terminals.

[0030] In one embodiment, the charging circuit may further include a clamp circuit that clamps the voltage at the capacitor connection terminal so that it does not exceed a predetermined voltage.

[0031] According to one embodiment, a data storage module is detachably mounted on a server. The data storage module includes: a first terminal for receiving a first voltage from the server, the first voltage being the output voltage of an intermediate bus converter; a second terminal for receiving a second voltage from the server, the second voltage being the input voltage of the intermediate bus converter or a voltage lower than the input voltage generated based on the input voltage; a power supply circuit; and a power loss protection circuit for receiving the first and second voltages and supplying the power supply voltage to the power supply circuit. The power loss protection circuit includes a capacitor, a first switch connected between the first terminal and an input terminal of the power supply circuit, a charging circuit connected between the second terminal and the capacitor, and an internal converter for receiving the voltage of the capacitor and supplying an output voltage regulated at a target level to the power supply circuit.

[0032] In one embodiment, the voltage on the capacitor may be higher than the input voltage. The internal converter may be a buck converter or a buck-boost converter.

[0033] In one embodiment, the voltage on the capacitor is lower than the input voltage and the internal converter may be a boost converter.

[0034] In one embodiment, the internal converter operates with or without the first voltage, and the target level of the output of the internal converter may be lower than the first voltage.

[0035] In one embodiment, the internal converter may be turned on when the first voltage is interrupted.

[0036] In one embodiment, the charging circuit includes a second switch, and the on-resistance of the second switch may be higher than the on-resistance of the first switch.

[0037] In one embodiment, the data storage module may further include a third switch connected between the output of the internal converter and the input terminal of the power supply circuit, and a switch control unit that controls the third switch.

[0038] In one embodiment, the switch control circuit may turn the third switch off when the voltage of the capacitor is lower than the output voltage.

[0039] In one embodiment, the switch control circuit may control the third switch so that the current flowing through it does not exceed an upper limit current.

[0040] In one embodiment, the switch control circuit may perform soft start control on the third switch.

[0041] In one embodiment, the charging circuit may operate to prevent the voltage on the capacitor from exceeding a predetermined voltage of 35V or less.

[0042] In one embodiment, the charging circuit may include a second switch and a control circuit that turns off the second switch when the voltage of the capacitor exceeds a predetermined voltage.

[0043] In one embodiment, the charging circuit may include a regulator to stabilize the voltage on the capacitor.

[0044] In one embodiment, the charging circuit may further include a clamping circuit that clamps the voltage of the capacitor so that it does not exceed a predetermined voltage.

[0045] In one embodiment, a server is configured to allow the above-described data storage module to be detachably attached. The server includes a third terminal receiving a voltage generated by an intermediate bus converter that steps down the DC bus voltage, a fourth terminal receiving the DC bus voltage, a fifth terminal to be connected to the first terminal of the data storage module, a sixth terminal to be connected to the second terminal of the data storage module, a first wire connecting the third terminal and the fifth terminal, and a second wire connecting the fourth terminal and the sixth terminal.

[0046] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0047] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected, but also a case in which component A and component B are indirectly connected via another component that does not affect the electrical connection or impair function. Also, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which component C is indirectly connected via another component that does not affect the electrical connection or impair function.

[0048] (Embodiment 1) 2 is a circuit diagram of a system 3 including a backup circuit 100 according to an embodiment. The system 3 includes a main power supply 10, an intermediate bus converter 40, a load 20, and the backup circuit 100.

[0049] In the system 2 of FIG. 1, the DC bus voltage V generated by the main power supply 10 BUS In the system 3 of FIG. 2, the bus voltage V generated by the main power supply 10 is 12V. BUS is a voltage higher than 12V, approximately 40 to 50V (specifically, 48V, 52V, 42V, etc., and in this embodiment, 48V).

[0050] This system 3 is provided with an intermediate bus converter 40, which is not present in the system 2 of Fig. 1. The intermediate bus converter 40 converts the 48V bus voltage V BUS is a DC voltage (input voltage) V of about 12 V, which is the standard voltage used in many electronic circuits. IN Convert to.

[0051] The first input terminal IN of the backup circuit 100 is connected to the input voltage V generated by the intermediate bus converter 40. IN The backup circuit 100 is supplied with the bus voltage V BUS The backup circuit 100 further includes a second input terminal BUS to which an input voltage V is supplied. The backup circuit 100 has an output terminal OUT connected to a load 20. The backup circuit 100 is INWhile the input voltage V IN output voltage V OUT The backup circuit 100 supplies the input voltage V IN is normally supplied, the backup capacitor 102 is charged, and the input voltage V IN When the power supply is cut off, the power stored in the backup capacitor 102 is supplied to the load 20.

[0052] The backup circuit 100 includes a first switch SW1, a charging circuit 110, an internal converter 120, a backup capacitor 102, and a controller 130. The main components of the first switch SW1, the charging circuit 110, the internal converter 120, and the controller 130 are integrated into an IC (Integrated Circuit) called a PLP circuit 200.

[0053] The first switch SW1 is connected between the first input terminal in and the output terminal out of the PLP circuit 200. The first switch SW1 is a semiconductor switch (MOS transistor) called an E-Fuse (electronic fuse). The on / off of the first switch SW1 is controlled in response to an enable signal EFUSE_IN.

[0054] An external backup capacitor 102 is connected to the capacitor connection terminal STR.

[0055] The charging circuit 110 is connected between the second input terminal bus and the capacitor connection terminal STR. The charging circuit 110 can be switched between an enabled state and a disabled state in response to an enable signal CHG_EN. In the enabled state, the charging circuit 110 charges the 48V bus voltage V BUS is used to charge the backup capacitor 102.

[0056] The controller 130 receives an input voltage V IN The controller 130 determines whether the input voltage V is normal or cut off, and generates the enable signals EFUSE_EN and CHG_EN. INWhile the input voltage V is normally supplied, the enable signal EFUSE_EN is asserted to turn on the first switch SW1. IN When the power supply is cut off, the enable signal EFUSE_EN is negated so that the first switch SW1 is turned off.

[0057] The controller 130 also controls the input voltage V IN While the input voltage V is normally supplied, the enable signal CHG_EN is asserted so that the charging circuit 110 is in an enabled state. IN When the power supply is cut off, the enable signal CHG_EN is negated so that the charging circuit 110 is disabled.

[0058] The internal converter 120 has an input connected to the capacitor connection terminal STR and an output connected to the output terminal out. The internal converter 120 is an isolated or non-isolated step-down converter, and converts an input voltage V IN When the power supply is cut off, the voltage V of the capacitor connection terminal STR STR (i.e., the voltage of the backup capacitor 102) is stepped down, and a voltage level V higher than the minimum operating voltage of the load 20 is applied to the output terminal out. OUT(REF) The voltage regulated to V OUT That is, the internal converter 120 generates an output voltage V OUT Target level V OUT(REF) Regulate to approach this.

[0059] The above is the basic configuration of the backup circuit 100. In this configuration, the DC bus voltage V BUS is supplied to the backup circuit 100, and this DC bus voltage V BUS The backup capacitor 102 is charged using this current. This eliminates the need for charging using a boost converter as in the past, thereby reducing losses. Furthermore, while in the past it was necessary to configure the boost converter to operate bidirectionally and switch the operating mode, with this configuration the internal converter 120 only needs to operate in one direction in the step-down mode, eliminating the need for switching.

[0060] A more preferable configuration and features of the backup circuit 100 in FIG. 2 will be described.

[0061] Target level V of the internal converter 120 OUT(REF) is the input voltage V IN It is recommended to set the voltage level lower than the V IN When is 12V, V OUT(REF) can be set to about 9 to 11 V (for example, 10 V). IN It may be set to always operate regardless of the presence or absence of

[0062] In this configuration, the input voltage V IN It is not necessary to control the internal converter 120 to be enabled or disabled depending on the input voltage V IN While power is being supplied normally, the internal converter 120 is in a light load state and operates in PFM (pulse frequency modulation) mode, so that keeping the internal converter 120 enabled all the time only slightly increases the switching loss.

[0063] The internal converter 120 may be configured as a step-up / step-down converter. In this case, in a power loss state, the voltage V of the backup capacitor 102 STR is the output voltage V OUT When the voltage V is higher than the target level, the internal converter 120 operates as a buck converter and the voltage V on the backup capacitor 102 STR is the output voltage V OUT When the voltage V falls below the target level, the internal converter 120 operates as a boost converter. STR In this range, power can be continuously supplied to the load 20.

[0064] Next, an example of a specific configuration of the backup circuit 100 will be described.

[0065] Example 1 FIG. 3 is a circuit diagram of a backup circuit 100A according to the first embodiment.

[0066] The first switch SW1 is a semiconductor switch and includes a MOS transistor M11 and a driver DR11. The MOS transistor M11 may be an N-channel or P-channel transistor. In this embodiment, the MOS transistor M11 is integrated into the PLP circuit 200A. The driver DR11 turns on the MOS transistor M11 in response to assertion of an enable signal EFUSE_EN.

[0067] The charging circuit 110 includes a second switch SW2 connected between the second input terminal bus and the capacitor connection terminal STR. Like the first switch SW1, the second switch SW2 is a semiconductor switch and includes a MOS transistor M12 and a driver DR12. The driver DR12 turns on the MOS transistor M12 in response to assertion of the enable signal CHG_EN, thereby enabling the charging circuit 110.

[0068] When the second switch SW2 is turned on, a charging current flows from the second input terminal bus to the capacitor connection terminal STR via the second switch SW2, and the backup capacitor 102 is charged.

[0069] Because a large current flows through the first switch SW1, the on-resistance of the MOS transistor M11 must be small, and therefore the size of the MOS transistor M11 must be large. On the other hand, because it is acceptable for the backup capacitor 102 to be charged slowly, the on-resistance of the MOS transistor M12 of the second switch SW2 can be large, and therefore the size of the MOS transistor M12 can be small. This makes it easy to miniaturize the second switch SW2.

[0070] The internal converter 120A includes a converter controller 122, a high-side transistor (switching transistor) M1 and a low-side transistor (synchronous rectification transistor) M2, which are NMOS transistors, an inductor L1, a capacitor C2, and resistors R1 and R2. The converter controller 122, the high-side transistor M1, and the low-side transistor M2 are integrated into the PLP circuit 200A, and chip components can be used for the inductor L1 and the capacitor C2. The high-side transistor M1 may be a PMOS transistor. The high-side transistor M1 and the low-side transistor M2 may also be configured as discrete components. The converter controller 122 controls the output voltage V generated at the output terminal out. OUT The feedback signal V FB For example, the feedback signal V FB is the output voltage V OUT is a voltage obtained by dividing the voltage by resistors R1 and R2. The resistors R1 and R2 may be integrated into the PLP circuit 200A.

[0071] The converter controller 122 generates a feedback signal V FB is the reference voltage V REF The switching of the high-side transistor M1 and the low-side transistor M2 is controlled so that the output voltage V approaches OUT Target Level V OUT(REF) teeth, V OUT(REF) =V REF ×(R1+R2) / R2 and the input voltage V IN be set lower.

[0072] As mentioned above, the internal converter 120A operates at an input voltage V IN It operates at all times regardless of the presence or absence of input voltage V IN When is supplied, the voltage at the output terminal (out) is V OUT The target level is V OUT(REF)Since the input voltage V is higher than V, the internal converter 120A operates under light load conditions. Under light load conditions, the converter controller 122 turns on the high-side transistor M1 once (or several times) and then operates in PFM mode, suspending switching for a long period of time. IN When the load current to the load 20 is cut off, the load current to the load 20 is supplied via the internal converter 120A, so that the internal converter 120A is in a heavy load state. In a heavy load state, the converter controller 122 controls the feedback signal V FB is the reference voltage V REF The duty cycles of the high-side transistor M1 and the low-side transistor M2 are feedback-controlled so as to approach

[0073] Next, the operation of the backup circuit 100A will be described.

[0074] 4 is a time chart illustrating the operation of the backup circuit 100A of FIG. 3. At time t0, the bus voltage V BUS At time t1, the intermediate bus converter 40 starts up, and the backup circuit 100 receives the 12V input voltage V IN is supplied.

[0075] At time t2, the controller 130 detects the input voltage V IN When the output voltage V OUT The charging circuit 110 starts charging the backup capacitor 102, and the voltage V STR rises towards 48 V. The internal converter 120 operates in PFM mode.

[0076] At time t3, the input voltage V INWhen the controller 130 detects the interruption, the enable signals EFUSE_EN and CHG_EN are negated, the first switch SW1 is turned off, and the charging circuit 110 is disabled. The internal converter 120 enters PWM mode, and the output voltage V OUT is the target level V OUT(REF) After that, the voltage V of the backup capacitor 102 is stabilized to 12V. STR is decreasing.

[0077] The operation of the backup circuit 100 is as described above.

[0078] 4, in the PLP circuit 200A of FIG. 3, the first switch SW1 and the second switch SW2 are turned on at startup (immediately after time t1 in FIG. 4). Since the on-resistance of the first switch SW1 is small, when it is turned on, the output voltage V OUT quickly detects the input voltage V IN Meanwhile, since the on-resistance of the second switch SW2 is high, the backup capacitor 102 is charged slowly.

[0079] Depending on the combination of the on-resistance of the first switch SW1 and the second switch SW2, immediately after the start of the PLP circuit 200A, V STR <V OUT A situation like this may occur. V STR <V OUT As a result, a reverse current flows from the output terminal out to the capacitor connection terminal STR via the inductor L1 and the body diode of the high-side transistor M1. If the impedance of the reverse charging path via the internal converter 120 is low, an inrush current may occur. The configurations described in Examples 2 to 4 can provide a solution to this problem.

[0080] Example 2 FIG. 5 is a circuit diagram of a backup circuit 100B according to a second embodiment. The PLP circuit 200B includes a third switch SW3 and a switch control circuit 140B. The terminal out′ of the PLP circuit 200B is connected to the output node of the internal converter 120B. The third switch SW3 is connected between the terminals out′ and out. The switch control circuit 140B controls the V OUT >V STR When the third switch SW3 is turned off, V OUT <V STR When the third switch SW3 is turned on, a reverse current is prevented from flowing through the internal converter 120B, and no inrush current occurs. Note that although the third switch SW3 is configured as an NMOS transistor here, it may also be configured as a PMOS transistor.

[0081] FIG. 6 is a time chart illustrating the operation of the backup circuit 100B of FIG.

[0082] The basic operation is the same as that of the backup circuit 100A. At time t2, the third switch SW3 is turned off, and no reverse current flows from the output terminal out to the backup capacitor 102. At time t4, the voltage V of the backup capacitor 102 STR is the input voltage V IN When the voltage Vcc exceeds 1 V, the third switch SW3 is turned on.

[0083] Example 3 FIG. 7 is a circuit diagram of a backup circuit 100C according to a third embodiment. Immediately after the start of the backup circuit 100C, during a period in which a reverse current Ir may occur, the switch control circuit 140C limits the reverse current Ir flowing through the third switch SW3 so that it does not exceed an upper limit current Ilim (current limiting function). The third transistor SW3 is a MOS transistor, and the switch control circuit 140C detects the drain current Ir of the MOS transistor and adjusts the gate voltage Vg3 of the MOS transistor so that the detection signal does not exceed a threshold value. The switch control circuit 140C controls the voltage Vg3 of the backup capacitor 102. STR is the input voltage V INWhen the voltage becomes higher and there is no longer any risk of backflow, the MOS transistor is turned on fully.

[0084] According to the third embodiment, by allowing the reverse current Ir, the backup capacitor 102 can be charged via a path separate from the second switch SW2, thereby shortening the charging time. Furthermore, by limiting the amount of the reverse current Ir, it is possible to prevent inrush current.

[0085] Example 4 8 is a circuit diagram of a backup circuit 100D according to Example 4. When the backup circuit 100D is started up, the switch control circuit 140D gradually increases the gate-source voltage of the MOS transistor serving as the third switch SW3 over time, gradually decreasing the on-resistance of the third switch SW3 (soft-start control).

[0086] As a result, during the period in which the reverse current Ir may occur, the on-resistance of the third switch SW3 is high, so that the reverse current Ir can be prevented from increasing, and the inrush current can be suppressed.

[0087] According to the fourth embodiment, by allowing the reverse current Ir, the backup capacitor 102 can be charged via a path separate from the second switch SW2, thereby shortening the charging time. Furthermore, by limiting the amount of the reverse current Ir, it is possible to prevent inrush current.

[0088] Example 5 9 is a circuit diagram of a backup circuit 100E according to a fifth embodiment. The charging circuit 110E charges the voltage V of the backup capacitor 102. STR is the predetermined upper limit voltage V TH It works to prevent it from going any higher.

[0089] The charging circuit 110E includes a MOS transistor M12, a driver DR12, a comparator 112, and a logic gate 114. The comparator 112 detects the voltage V of the backup capacitor 102. STR The upper limit voltage V THThe logic gate 114 performs a logical operation on the enable signal CHG_EN and the output of the comparator 112. The driver DR12 controls the MOS transistor M12 based on the output of the logic gate 114.

[0090] For example, comparator 112 is V STR <V TH High when V STR >V TH The logic gate 114 is an AND gate, and generates a logical product of the output of the comparator 112 and the enable signal CHG_EN. The driver DR12 turns on the MOS transistor M12 when the output of the logic gate 114 is high.

[0091] Upper limit voltage V TH is preferably set to 35 V or lower. This allows a 35 V withstand voltage element to be used as the backup capacitor 102, thereby reducing costs compared to components with a 48 V withstand voltage.

[0092] Example 6 10 is a circuit diagram of a backup circuit 100F according to a sixth embodiment. A charging circuit 110F charges the voltage V of the backup capacitor 102. STR at a predetermined target level V STR(REF) The charging circuit 110F includes a linear regulator that stabilizes the voltage V of the backup capacitor 102. The charging circuit 110F includes a MOS transistor M12 and an error amplifier 116. The error amplifier 116 is turned on when the enable signal CHG_EN is asserted, and STR and target level V STR(REF) The error is amplified to control the gate voltage of the MOS transistor M12. STR(REF) By setting the voltage to 35V or less, a 35V withstand voltage element can be used as the backup capacitor 102, which can reduce costs compared to a 48V withstand voltage part.

[0093] The third switch SW3 described in the second to fourth embodiments may be added to the backup circuits 100E and 100F according to the fifth and sixth embodiments.

[0094] Example 7 11 is a circuit diagram of a backup circuit 100G according to Example 7. The charging circuit 110 may be the one described in Example 5 or Example 6, or may be the one described in Example 1.

[0095] The PLP circuit 200 includes a clamp circuit 150. The clamp circuit 150 clamps the voltage V of the backup capacitor 102. STR , the upper limit voltage V LIM The upper limit voltage V LIM By setting the upper limit voltage V to 35V or less, a 35V withstand voltage element can be used as the backup capacitor 102, which reduces costs compared to a 48V withstand voltage part. LIM is the upper limit voltage V TH It may be equal to or different from.

[0096] The backup circuit 100G according to the seventh embodiment may be added with the third switch SW3 described in the second to fourth embodiments. The backup circuit 100G according to the seventh embodiment may be added with the third switch SW3 described in the second to fourth embodiments.

[0097] Example 8 12 is a circuit diagram of a system 3H including a backup circuit 100H according to an eighth embodiment. In a PLP circuit 200H, a charging circuit 110H charges the backup capacitor 102 with an input voltage V IN This allows a super capacitor with a withstand voltage of about 12 V to be used as the backup capacitor 102.

[0098] The internal converter 120H is a boost converter that converts the input voltage V IN When the power supply is cut off, the voltage V of the capacitor connection terminal STR STR(i.e., the voltage of the backup capacitor 102) is boosted, and a voltage level V higher than the minimum operating voltage of the load 20 is applied to the output terminal out. OUT(REF) The voltage regulated to V OUT In other words, the internal converter 120H generates an output voltage V OUT Target level V OUT(REF) The internal converter 120H may be a step-up / step-down converter.

[0099] The various components described in the first to eighth embodiments can be combined in any manner.

[0100] Example 9 Fig. 13 is a circuit diagram of a system 3I according to Example 9. A backup circuit 100I in Fig. 13 is any one of the backup circuits 100, 100A to 100H described above.

[0101] The system 3I includes a voltage regulation circuit 50. The voltage regulation circuit 50 is provided on a path from the output of the main power supply 10 to the second input terminal bus of the PLP circuit 200. The voltage regulation circuit 50 regulates the bus voltage V BUS DC bus voltage V BUS and supplies it to the second input terminal bus of the PLP circuit 200. The voltage adjustment circuit 50 may be provided outside the backup circuit 100 or inside the backup circuit 100.

[0102] The voltage adjustment circuit 50 can be configured as any one of a step-down converter, a linear regulator (LDO: Low Drop Output), a load switch, and an electronic fuse, or a combination thereof.

[0103] 48V bus voltage V at the second input terminal bus BUSIn a configuration where the voltage supplied to the second input terminal bus is approximately 60V, an absolute maximum rating of approximately 60V must be anticipated. In this case, the IPC-9592 standard requires the pitch between connector terminals to be 0.7mm or more, which would result in a larger connector. However, if the voltage adjustment circuit 50 is used to limit the voltage at the second input terminal bus to 30V or less, the pitch between connector terminals can be made 0.25mm, allowing the connector to be more compact.

[0104] Furthermore, if the voltage adjustment circuit 50 is configured such that the load switch includes an electronic fuse or the like, it is possible to separate the main power supply 10 from the backup circuit 100. This makes it possible to prevent the effects of a failure or abnormality, such as a short circuit, occurring in the backup circuit 100 from reaching the main power supply 10, thereby improving the safety of the system 3.

[0105] The voltage adjustment circuit 50 may be configured by combining a voltage adjustment means such as a step-down converter or a linear regulator with a switch such as a load switch or an electronic fuse.

[0106] Next, a modification of the backup circuit 100 will be described.

[0107] (Variation 1) Input voltage V IN When the input voltage V IN The internal converter 120 may be disabled when the input voltage V IN Simply add a circuit (such as a voltage comparator) to monitor the

[0108] (Variation 2) Regarding the first switch SW1, the second switch SW2, and the third switch SW3, the MOS transistors M11, M12, and M13 may be discrete components. In that case, the MOS transistors M11 to M13 are externally connected to the PLP circuit 200.

[0109] Next, an example of an actual application of System 2 will be described.

[0110] 14 is a circuit diagram of a computer system 300. The computer system 300 includes a main power supply 310, an intermediate bus converter 340, a server (main unit) 400, and a data storage module 500. The computer system 300 is installed in, for example, a data center.

[0111] The main power supply 310 corresponds to the main power supply 10 in FIG. 2 and has a bus voltage V of about 40 to 50 V. BUS Intermediate bus converter 340 corresponds to intermediate bus converter 40 of FIG. 2 and generates a 12V voltage V IN Generate.

[0112] Terminal T3 of server 400 is connected to the input voltage V IN The server 400 includes a controller 410, a CPU 412, a GPU 414, a memory 416, a power supply 420, and other electronic components 422. The controller 410 performs overall control of the entire server 400. The controller 410 also supplies a power supply voltage to the CPU 412 and GPU 414. The power supply 420 supplies a power supply voltage to the electronic components 422. The electronic components 422 may include various controllers, interface circuits, and peripheral circuits.

[0113] The data storage module 500 is detachable from the server 400 and is, for example, a solid state disk (SSD) module. The data storage module 500 may also be a hard disk.

[0114] The data storage module 500 includes the backup circuit 100, a power management circuit (PMIC) 510, and multiple electronic components 520. The multiple electronic components 520 may be, for example, a controller, a NAND flash, a cache memory, an interface, etc. The PMIC 510 supplies power supply voltages of appropriate voltage levels to the multiple electronic components 520 in an appropriate sequence.

[0115] The backup circuit 100 has a 12V input voltage V IN In addition, the 48V bus voltage V BUS The server 400 has a terminal T5 for receiving the bus voltage VBUS. The server 400 also has a terminal T4 to be connected to the terminal IN of the backup circuit 100, and a terminal T6 to be connected to the terminal BUS of the backup circuit 100. The 48V bus voltage V BUS Note that is not used by the server 400 but is instead tapped in to feed the PLP circuit 200.

[0116] The backup circuit 100 is provided with a first wiring 430 and a second wiring 432 to supply voltages of 12V and 48V to the data storage module 500. The first wiring 430 connects between terminals T3 and T5 of the server 400 and supplies the input voltage V IN The second wiring 432 connects the terminals T4 and T6 of the server 400 and supplies the bus voltage V BUS This is the supply route for

[0117] The present invention has been described based on embodiments and using specific terms, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention defined in the claims.

[0118] (Addendum) The present specification discloses the following techniques.

[0119] (Item 1) a first input terminal that receives, as an input voltage, a voltage generated by an intermediate bus converter that steps down the DC bus voltage; a second input terminal for receiving the DC bus voltage or a voltage generated based on the DC bus voltage and lower than the DC bus voltage; a capacitor connection terminal to which an external capacitor is to be connected; an output terminal to be connected to a load; a first switch connected between the first input terminal and the output terminal; a charging circuit connected between the second input terminal and the capacitor connection terminal; an internal converter that receives a voltage at the capacitor connection terminal and stabilizes an output voltage generated at the output terminal at a target level; A power loss protection circuit comprising:

[0120] (Item 2) 2. The power loss protection circuit of item 1, wherein the voltage of the capacitor is higher than the input voltage, and the internal converter is a buck converter or a buck-boost converter.

[0121] (Item 3) 2. The power loss protection circuit of item 1, wherein the voltage of the capacitor is lower than the input voltage and the internal converter is a boost converter.

[0122] (Item 4) 4. The power loss protection circuit of any one of items 1 to 3, wherein the target level of the internal converter is lower than the input voltage, and the internal converter operates regardless of the presence or absence of the input voltage.

[0123] (Item 5) 4. The power loss protection circuit according to any one of items 1 to 3, wherein the internal converter is enabled when the input voltage is interrupted.

[0124] (Item 6) 6. The power loss protection circuit according to any one of items 1 to 5, wherein the charging circuit includes a second switch, and the on-resistance of the second switch is higher than the on-resistance of the first switch.

[0125] (Item 7) a third switch connected between the output of the internal converter and the output terminal; a switch control circuit for controlling the third switch; 6. The power loss protection circuit of any one of items 1 to 5, further comprising:

[0126] (Item 8) 8. The power loss protection circuit according to item 7, wherein the switch control circuit turns off the third switch when the voltage at the capacitor connection terminal is lower than the output voltage.

[0127] (Item 9) 8. The power loss protection circuit according to item 7, wherein the switch control circuit controls the third switch so that the current flowing therethrough does not exceed an upper limit current.

[0128] (Item 10) 8. The power loss protection circuit according to item 7, wherein the switch control circuit performs soft start control on the third switch.

[0129] (Item 11) 6. The power loss protection circuit according to any one of items 1 to 5, wherein the charging circuit operates so that the voltage at the capacitor connection terminal does not exceed a predetermined voltage of 35 V or less.

[0130] (Item 12) The charging circuit A second switch; a control circuit that turns off the second switch when the voltage at the capacitor connection terminal exceeds the predetermined voltage; Item 12. The power loss protection circuit of item 11, comprising:

[0131] (Item 13) Item 12. The power loss protection circuit according to item 11, wherein the charging circuit includes a regulator that stabilizes the voltage of the capacitor connection terminal.

[0132] (Item 14) 6. The power loss protection circuit according to any one of items 1 to 5, wherein the charging circuit further includes a clamp circuit that clamps the voltage at the capacitor connection terminal so that it does not exceed a predetermined voltage.

[0133] (Item 15) A removable SSD (Solid State Disk) module for a server, a first terminal for receiving a first voltage, which is an output voltage of an intermediate bus converter, from the server; a second terminal for receiving a second voltage from the server, the second voltage being an input voltage of the intermediate bus converter or a voltage lower than the input voltage generated based on the input voltage; A power supply circuit; a power loss protection circuit that receives the first voltage and the second voltage and supplies a power supply voltage to the power supply circuit; Equipped with The power loss protection circuit includes: A capacitor; a first switch connected between the first terminal and an input terminal of the power supply circuit; a charging circuit connected between the second terminal and the capacitor; an internal converter that receives the voltage of the capacitor and supplies an output voltage stabilized at a target level to the power supply circuit; A data storage module comprising:

[0134] (Item 16) Item 16. The data storage module of item 15, wherein the voltage of the capacitor is higher than the input voltage, and the internal converter is a buck converter or a buck-boost converter.

[0135] (Item 17) Item 16. The data storage module of item 15, wherein the capacitor voltage is lower than the input voltage and the internal converter is a boost converter.

[0136] (Item 18) 18. The data storage module of any of items 15 to 17, wherein the internal converter is on regardless of the presence or absence of the first voltage, and the target level of the internal converter is lower than the first voltage.

[0137] (Item 19) 18. The data storage module of any one of items 15 to 17, wherein the internal converter is turned on when the first voltage is interrupted.

[0138] (Item 20) 20. The data storage module of any one of items 15 to 19, wherein the charging circuit includes a second switch, and the on-resistance of the second switch is higher than the on-resistance of the first switch.

[0139] (Item 21) a third switch connected between the output of the internal converter and the input terminal of the power supply circuit; a switch control circuit for controlling the third switch; 20. The data storage module of any of items 15 to 19, further comprising:

[0140] (Item 22) 22. The data storage module of claim 21, wherein the switch control circuit turns the third switch off when the voltage of the capacitor is lower than the output voltage.

[0141] (Item 23) 22. The data storage module according to item 21, wherein the switch control circuit controls the third switch so that the current flowing therethrough does not exceed an upper limit current.

[0142] (Item 24) 22. The data storage module of claim 21, wherein the switch control circuit controls the third switch to soft start.

[0143] (Item 25) 25. The data storage module of any one of items 15 to 24, wherein the charging circuit operates to prevent the voltage of the capacitor from exceeding a predetermined voltage of 35V or less.

[0144] (Item 26) The charging circuit A second switch; a control circuit that turns off the second switch when the voltage of the capacitor exceeds the predetermined voltage; 26. The data storage module of item 25, comprising:

[0145] (Item 27) 26. The data storage module of claim 25, wherein the charging circuit includes a regulator that stabilizes the voltage of the capacitor.

[0146] (Item 28) 25. The data storage module of any one of items 15 to 24, wherein the charging circuit further comprises a clamp circuit that clamps the voltage of the capacitor so that it does not exceed a predetermined voltage.

[0147] (Item 29) The data storage module according to any one of items 15 to 28 is configured to be detachable; a third terminal for receiving a voltage generated by an intermediate bus converter that steps down the DC bus voltage; a fourth terminal for receiving the DC bus voltage; a fifth terminal to be connected to the first terminal of the data storage module; a sixth terminal to be connected to the second terminal of the data storage module; a first wiring that connects the third terminal and the fifth terminal; a second wiring that connects the fourth terminal and the sixth terminal; A server comprising: [Explanation of symbols]

[0148] 2,3 System 10 Main power 20 Load 22 PMIC 24 Electronic Components 30 Backup circuit 32 Switch 34 Backup capacitor 36 Boost Converter 40 Intermediate Bus Converter 50 Voltage Regulator Circuit 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G backup circuit 102 Backup capacitor SW1 First switch SW2 Second switch SW3 Third switch 110 Charging circuit 120 Internal Converter 122 Converter Controller 130 Controller 200, 200A, 200B, 200C, 200D, 200E, 200F, 200G PLP circuit 300 Computer Systems 310 Main power supply 340 Intermediate Bus Converter 400 Server 410 Controller 412 CPU 414 GPU 416 memory 420 Power supply 422 Electronic Components 430 1st wiring 423 2nd wiring 500 Data Storage Module 510 PMIC 520 Electronic Components

Claims

1. a first input terminal for receiving, as an input voltage, a voltage generated by an intermediate bus converter that steps down the DC bus voltage; a second input terminal for receiving the DC bus voltage or a voltage generated based on the DC bus voltage and lower than the DC bus voltage; a capacitor connection terminal to which an external capacitor is to be connected; an output terminal to be connected to a load; a first switch connected between the first input terminal and the output terminal; a charging circuit connected between the second input terminal and the capacitor connection terminal; an internal converter that receives a voltage at the capacitor connection terminal and stabilizes an output voltage generated at the output terminal at a target level; A power loss protection circuit comprising:

2. 2. The power loss protection circuit of claim 1, wherein the voltage of the capacitor is higher than the input voltage, and the internal converter is a buck converter or a buck-boost converter.

3. 2. The power loss protection circuit of claim 1, wherein the voltage of the capacitor is lower than the input voltage, and the internal converter is a boost converter.

4. 4. The power loss protection circuit of claim 1, wherein the target level of the internal converter is lower than the input voltage, and the internal converter operates regardless of the presence or absence of the input voltage.

5. 4. The power loss protection circuit according to claim 1, wherein the internal converter is enabled when the input voltage is interrupted.

6. 4. The power loss protection circuit according to claim 1, wherein the charging circuit includes a second switch, and the on-resistance of the second switch is higher than the on-resistance of the first switch.

7. a third switch connected between the output of the internal converter and the output terminal; a switch control circuit for controlling the third switch; 4. The power loss protection circuit of claim 1, further comprising:

8. 8. The power loss protection circuit according to claim 7, wherein the switch control circuit turns off the third switch when the voltage at the capacitor connection terminal is lower than the output voltage.

9. 8. The power loss protection circuit according to claim 7, wherein the switch control circuit controls the third switch so that a current flowing through the third switch does not exceed an upper limit current.

10. 8. The power loss protection circuit according to claim 7, wherein the switch control circuit performs soft start control on the third switch.

11. 4. The power loss protection circuit according to claim 1, wherein the charging circuit operates so that the voltage at the capacitor connection terminal does not exceed a predetermined voltage of 35 V or less.

12. The charging circuit A second switch; a control circuit that turns off the second switch when the voltage at the capacitor connection terminal exceeds the predetermined voltage; 12. The power loss protection circuit of claim 11, comprising:

13. 12. The power loss protection circuit according to claim 11, wherein the charging circuit includes a regulator that stabilizes the voltage at the capacitor connection terminal.

14. 4. The power loss protection circuit according to claim 1, wherein the charging circuit further comprises a clamping circuit that clamps the voltage at the capacitor connection terminal so that it does not exceed a predetermined voltage.

15. A removable SSD (Solid State Disk) module for a server, a first terminal for receiving a first voltage, which is an output voltage of an intermediate bus converter, from the server; a second terminal for receiving a second voltage from the server, the second voltage being an input voltage of the intermediate bus converter or a voltage lower than the input voltage generated based on the input voltage; A power supply circuit; a power loss protection circuit that receives the first voltage and the second voltage and supplies a power supply voltage to the power supply circuit; Equipped with The power loss protection circuit includes: A capacitor; a first switch connected between the first terminal and an input terminal of the power supply circuit; a charging circuit connected between the second terminal and the capacitor; an internal converter that receives the voltage of the capacitor and supplies an output voltage stabilized at a target level to the power supply circuit; A data storage module comprising:

16. 16. The data storage module of claim 15, wherein the voltage of the capacitor is higher than the input voltage, and the internal converter is a buck converter or a buck-boost converter.

17. 16. The data storage module of claim 15, wherein the voltage on the capacitor is lower than the input voltage and the internal converter is a boost converter.

18. 18. The data storage module of claim 15, wherein the internal converter is on regardless of the presence or absence of the first voltage, and the target level of the internal converter is less than the first voltage.

19. 18. The data storage module of claim 15, wherein the internal converter is turned on when the first voltage is interrupted.

20. 18. The data storage module of claim 15, wherein the charging circuit includes a second switch, and the on-resistance of the second switch is higher than the on-resistance of the first switch.

21. a third switch connected between the output of the internal converter and the input terminal of the power supply circuit; a switch control circuit for controlling the third switch; 18. The data storage module of claim 15, further comprising:

22. 22. The data storage module of claim 21, wherein the switch control circuit turns the third switch off when the voltage of the capacitor is lower than the output voltage.

23. 22. The data storage module according to claim 21, wherein the switch control circuit controls the third switch so that a current flowing through the third switch does not exceed an upper limit current.

24. 22. The data storage module of claim 21, wherein the switch control circuit controls the third switch to soft start.

25. 18. The data storage module according to claim 15, wherein the charging circuit operates so as not to cause the voltage of the capacitor to exceed a predetermined voltage of 35V or less.

26. The charging circuit A second switch; a control circuit that turns off the second switch when the voltage of the capacitor exceeds the predetermined voltage; 26. The data storage module of claim 25, comprising:

27. 26. The data storage module of claim 25, wherein the charging circuit includes a regulator that stabilizes the voltage of the capacitor.

28. 18. The data storage module according to claim 15, wherein the charging circuit further comprises a clamping circuit that clamps the voltage of the capacitor so that it does not exceed a predetermined voltage.

29. The data storage module according to any one of claims 15 to 17 is configured to be detachable, a third terminal for receiving a voltage generated by an intermediate bus converter that steps down the DC bus voltage; a fourth terminal for receiving the DC bus voltage; a fifth terminal to be connected to the first terminal of the data storage module; a sixth terminal to be connected to the second terminal of the data storage module; a first wiring connecting the third terminal and the fifth terminal; a second wiring connecting the fourth terminal and the sixth terminal; A server comprising:

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