Source driver and display device
The source driver optimizes power consumption and reduces system costs by integrating a charge share voltage generation circuit to adjust output voltage based on data sequence comparisons, facilitating high-speed display operation.
Patent Information
- Application Number
- JP2024024415
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-21
- Publication Date
- 2025-09-02
AI Technical Summary
Conventional display drivers face challenges in high-speed operation due to increased power consumption and system cost, particularly when sharing voltage from an external power supply, which requires multiple terminals.
A source driver with an integrated charge share voltage generation circuit and switching mechanism that compares data sequences to determine charge sharing and adjusts output voltage accordingly, reducing the need for external terminals and optimizing power consumption.
Enables high-speed operation of display devices while minimizing power consumption and system costs by efficiently sharing charge within the driver.
Smart Images
Figure 2025127625000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a source driver and a display device. [Background technology]
[0002] Active matrix driving is used as a driving method for display devices consisting of display devices such as liquid crystal and organic EL (Electro Luminescence). In active matrix driving display devices, the display panel is composed of a semiconductor substrate on which pixel units and pixel switches are arranged in a matrix. The pixel switches are controlled to turn on and off by a gate signal, and when the pixel switch is turned on, a grayscale voltage signal corresponding to a video data signal is supplied to the pixel units to control the brightness of each pixel unit, thereby producing a display.
[0003] In recent years, display panels for such active matrix display devices have become increasingly high-definition and fast, such as 4K and 8K. Drivers that drive display devices must charge pixel sections by applying grayscale voltage signals via large-capacity data lines. Furthermore, as speeds increase, it becomes necessary to write a target voltage in a short write time. Such high-load, high-speed driving poses the problem of increased driver power consumption. To address this issue, a driver has been proposed that shares voltage (charge share) from an external power supply and shorts the output to a voltage close to the target voltage in order to drive display devices at high speeds (see, for example, Patent Document 1). [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-199203 Summary of the Invention [Problem to be solved by the invention]
[0005] In the above-mentioned conventional technology, the external power supply cannot be adjusted within the driver. Also, if multiple power supplies are to be shorted, multiple terminals are required, which increases the overall cost (system cost) of the display device.
[0006] The present invention has been made in view of the above problems, and has as its object to provide a source driver that is capable of driving a display device at high speed while suppressing the cost and power consumption of the entire device. [Means for solving the problem]
[0007] A source driver according to the present invention is connected to a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of source lines and the plurality of gate lines, and receives a video data signal consisting of a plurality of data strings, generates a plurality of drive voltages based on the video data signal, and applies the drive voltages to each of the plurality of pixel units via each of the plurality of source lines, and includes a charge share voltage generation circuit that generates a plurality of charge share voltages based on a reference voltage, a latch unit that sequentially captures the plurality of data strings for each data string corresponding to each of the plurality of gate lines, and a latch unit that sequentially captures the plurality of data strings for each data string corresponding to each of the plurality of gate lines. The device is characterized by having a charge share calculation circuit that compares a data sequence corresponding to an Nth line (N is an integer greater than or equal to 2) with a data sequence corresponding to an (N-1)th line and performs a determination calculation regarding the charge share of the output voltage for the source output corresponding to the data sequence of the Nth line; and a switching unit that, based on the calculation result of the charge share calculation circuit, selectively switches between outputting one of the plurality of charge share voltages for a predetermined period from the start of the output period during the output period of the source output corresponding to the data sequence of the Nth line, or continuously outputting the drive voltage generated based on the data value of the data sequence of the Nth line from the start of the output period.
[0008] Also, a display device according to the present invention includes a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines; a gate driver that supplies gate signals to the plurality of gate lines; and a source driver that receives a video data signal consisting of a plurality of data strings, generates a plurality of drive voltages based on the video data signal, and applies the drive voltages to each of the plurality of pixel units via each of the plurality of source lines, wherein the source driver includes a charge share voltage generation circuit that generates a plurality of charge share voltages based on a reference voltage, and a wrapper that sequentially takes in the plurality of data strings for each data string corresponding to each of the plurality of gate lines. a charge share calculation circuit that compares a data sequence corresponding to an Nth line (N is an integer equal to or greater than 2) of the plurality of gate lines with a data sequence corresponding to the (N-1)th line and performs a determination calculation regarding the charge share of the output voltage for the source output corresponding to the data sequence of the Nth line; and a switching unit that, based on the calculation result of the charge share calculation circuit, selectively switches between outputting one of the plurality of charge share voltages for a predetermined period from the start of the output period during the output period of the source output corresponding to the data sequence of the Nth line, or continuously outputting the drive voltage generated based on the data value of the data sequence of the Nth line from the start of the output period. [Effects of the Invention]
[0009] The source driver according to the present invention makes it possible to drive a display device at high speed while suppressing the cost and power consumption of the entire device. [Brief explanation of the drawings]
[0010] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a block diagram showing an internal configuration of a source driver according to an embodiment of the present invention. [Figure 3]FIG. 2 is a circuit diagram showing the configuration of a CS voltage generating circuit. [Figure 4] FIG. 1 is a diagram illustrating a CS calculation. [Figure 5] 10A and 10B are diagrams illustrating the pulse width of a clock signal when the CS period is adjusted and when it is not adjusted. [Figure 6] 4A and 4B are diagrams illustrating voltage waveforms of output signals of a source driver in the present embodiment. [Figure 7] 10A and 10B are diagrams illustrating voltage waveforms of output signals when the CS voltage is increased. [Figure 8] 10A and 10B are diagrams illustrating voltage waveforms of output signals when adjusting a CS period. DETAILED DESCRIPTION OF THE INVENTION
[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.
[0012] 1 is a block diagram showing the configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 is an active matrix liquid crystal display device. The display device 100 includes a display panel 11, a display controller 12, a gate driver 13, and a source driver 14.
[0013] The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel units P11 to Pnm and pixel switches M11 to Mnm (n is an integer of 2 or greater, and m is an integer of 2 or greater and a multiple of 3) are arranged in a matrix of n rows and m columns. The display panel 11 has n gate lines GL1 to GLn which are horizontal scanning lines, and m source lines SL1 to SLm which are arranged orthogonally to intersect the gate lines GL1 to GLn. The pixel units P11 to Pnm and pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm, and are arranged in a matrix.
[0014] The pixel switches M11 to Mnm are controlled to be on or off in response to gate signals Vg1 to Vgn supplied from the gate driver 13. The pixel units P11 to Pnm are supplied with pixel drive voltage signals Dv1 to Dvm corresponding to video data from the source driver 14. When the pixel switches M11 to Mnm are each on, the pixel drive voltage signals Dv1 to Dvm are applied to the pixel electrodes of the pixel units P11 to Pnm, charging each pixel electrode. The luminance of the pixel units P11 to Pnm is controlled in response to the pixel drive voltage signals Dv1 to Dvm at the pixel electrodes of the pixel units P11 to Pnm, and display is performed.
[0015] The display controller 12 generates a video data signal VDS including a series of pixel data fragments PD that represent the luminance level of each pixel, for example, in 256 8-bit luminance gradations, based on the video data VD. The video data signal VDS is configured as a video data signal serialized according to the number of transmission paths for each predetermined number of source lines.
[0016] In this embodiment, one frame of video data signal VDS is formed by serially connecting n pixel data fragment groups, each consisting of m pixel data fragments PD. Each of the n pixel data fragment groups is a pixel data fragment group consisting of pixel data fragments corresponding to the gradation voltages to be supplied to pixels on one horizontal scanning line (i.e., each of the gate lines GL1 to GLn). The operation of the source driver 14 generates a video data signal VDS for n×m pixel sections (i.e., pixel section P) based on the m×n pixel data fragments PD. 11 ~P nm ) are generated, and corresponding pixel drive voltage signals Dv1 to Dvm are applied via source lines.
[0017] The display controller 12 also supplies a frame synchronization signal FS, which indicates the timing of each frame of the video data signal VDS, to the source driver 14. Furthermore, the display controller 12 generates a scan timing signal GS, which indicates the timing of applying a horizontal scan pulse to each scan line, based on the video data VD, and supplies this to the gate driver 13.
[0018] The gate driver 13 sequentially applies gate signals Vg1 to Vgn, which include horizontal scanning pulses synchronized with the scanning timing signal GS supplied from the display controller 12, to the gate lines GL1 to GLn of the display panel 11, respectively.
[0019] The source driver 14 receives a frame synchronization signal FS and a video data signal VDS from the display controller 12. The source driver 14 generates multi-level grayscale voltage signals according to the number of grayscale levels indicated by the video data signal VDS, and applies corresponding pixel drive voltage signals Dv1 to Dvm to pixel units P11 to Pnm via source lines SL1 to SLm. The number of source lines SL1 to SLm (i.e., m) corresponds to the number of output channels of the source driver 14.
[0020] 2 is a block diagram showing the internal configuration of the source driver 14. The source driver 14 has an IF / data processing unit 21 and a CS voltage generating circuit 22. The source driver 14 also has output generating blocks 23-1 to 23-m corresponding to output channels 1ch to mch, respectively.
[0021] The IF / data processing unit 21 is an interface circuit unit that receives the video data signal VDS from the display controller 12. The IF / data processing unit 21 supplies a series of pixel data pieces PD (hereinafter also simply referred to as a data string) included in the video data signal VDS to the output generation blocks 23-1 to 23-m for each piece of data corresponding to each output channel.
[0022] Furthermore, the IF / data processing unit 21 generates a CS voltage control signal CVS based on the video data signal VDS and supplies it to a CS voltage generating circuit 22.
[0023] 3 is a circuit diagram showing the configuration of the CS voltage generating circuit 22. The CS voltage generating circuit 22 has input amplifiers 41 and 42, a ladder resistor 43, decoders DCA to DCX, and output amplifiers AP1 to APN.
[0024] The input amplifiers 41 and 42 are supplied with a first reference voltage VGMA_TOP and a second reference voltage VGMA_BOTTOM, respectively. The first reference voltage VGMA_TOP and the second reference voltage VGMA_BOTTOM are reference voltages used to generate grayscale voltages in a grayscale voltage generating circuit (not shown) provided in the source driver 14.
[0025] The input amplifier 41 receives the first reference voltage VGMA_TOP, amplifies it, and supplies it to one end of the ladder resistor 43. The input amplifier 42 receives the second reference voltage VGMA_BOTTOM, amplifies it, and supplies it to the other end of the ladder resistor 43.
[0026] The ladder resistor 43 has voltage output terminals provided at a plurality of different positions, and generates output voltages at a plurality of levels with different voltage values obtained by linearly dividing the voltage between the first reference voltage VGMA_TOP and the second reference voltage VGMA_BOTTOM.
[0027] Based on the CS voltage control signal CVS supplied from the IF / data processing unit 21, the decoders DCA to DCX select multiple output voltages from the multiple levels of output voltages generated by the ladder resistor 43 and supply them to the input terminals of the output amplifiers AP1 to APN.
[0028] The output amplifiers AP1 to APN amplify the output voltages from the decoders DCA to DCX and output them as charge share voltages CSV1 to CSVN.
[0029] 2 again, the output generation block 23-1 includes a first latch 31, a second latch 32, a third latch 33, a DA conversion unit 34, an operational amplifier 35, a CS calculation circuit 36, a CS period adjustment circuit 37, a switching control unit 38, and a switch (SW) 39. The other output generation blocks (i.e., the output generation blocks 23-2 to 23-m) have the same configuration.
[0030] The first latch 31, the second latch 32, and the third latch 33 are latch units that sequentially capture a series of pixel data pieces PD included in the video data signal VDS for each data string corresponding to each of the n gate lines. Each of the first latch 31, the second latch 32, and the third latch 33 constitutes a cascade-connected multi-stage latch that captures a series of pixel data pieces PDn for each line (hereinafter referred to as a line data string LD) and outputs the captured line data string LD to the next stage latch at the timing when the line data string LD of the next line is captured.
[0031] The first latch 31 receives the line data string LD output from the IF / data processing unit 21. The first latch 31 outputs the received line data string LD and supplies it to the second latch 32 and the CS calculation circuit .
[0032] The second latch 32 receives the line data string LD output from the first latch 31. The second latch 32 outputs the received line data string LD and supplies it to the third latch 33 and the CS calculation circuit .
[0033] The third latch 33 captures the line data string LD output from the second latch 32. The third latch 33 outputs the captured line data string LD and supplies it to the DA conversion unit .
[0034] The DA conversion unit 34 generates a gradation voltage Gv by level-shifting each of the pixel data fragments PD included in the line data string LD output from the third latch 33 and performing digital-to-analog conversion on the same. The DA conversion unit 34 performs the digital-to-analog conversion by selecting a gradation voltage Gv corresponding to the luminance level indicated by the plurality of pixel data fragments PD from a plurality of gradation voltages output from a gradation voltage generation circuit (not shown).
[0035] The operational amplifier 35 amplifies the grayscale voltage Gv generated by the DA conversion unit 34 and outputs it as pixel drive voltage signals Dv1 to Dvm.
[0036] The CS calculation circuit 36 receives line data strings LD that differ by one line from the first latch 31 and the second latch 32, compares these data strings, and performs CS (charge share) calculation based on the comparison result, and outputs the calculation result to the switching control unit 38.
[0037] FIG. 4 is a diagram showing a schematic diagram of the CS calculation by the CS calculation circuit 36 of this embodiment, in which an example is shown in which the line data string LD is made up of 8-bit (1 byte) data.
[0038] As described above, the first latch 31 and the second latch 32 take in the line data string LD and output it at the same timing as they take in the line data string LD for the next line. As a result, for example, the first latch 31 outputs the line data string LD for the (N)th line at the same timing as the second latch 32 outputs the line data string LD for the (N-1)th line (N is an integer equal to or greater than 2). Therefore, the CS calculation circuit 36 is supplied with the line data string LD for the (N)th line from the first latch 31 at the same timing as the second latch 32 supplies it with the line data string LD for the (N-1)th line.
[0039] The CS calculation circuit 36 compares the line data sequence LD for the (N-1)th line output from the second latch 32 with the line data sequence LD for the (N)th line output from the first latch 31-1, and performs a determination calculation to determine whether or not to perform output voltage charge sharing during the output period of the source output corresponding to the line data sequence LD for the (N)th line. Specifically, the CS calculation circuit 36 compares the difference between the data value of the line data sequence LD for the (N-1)th line and the data value of the line data sequence LD for the (N)th line with a first threshold value, and determines to perform output voltage charge sharing if the difference is equal to or greater than the first threshold value, and not to perform output voltage charge sharing if the difference is less than the first threshold value. The CS calculation circuit 36 supplies the determination result to the switching control unit 38.
[0040] The source driver 14 of this embodiment performs charge sharing of the output voltage in response to the rising edge of the clock signal CLK1, which indicates the timing of the output period of the source output for each line of the line data column LD. Specifically, since the clock pulse of the clock signal CLK1 is at H level for a predetermined period from the start of the output period of the source output for each line, the source driver 14 performs source output switching control so as to output a charge sharing voltage instead of the pixel drive voltage signal Dv based on the data value of the line data column while the clock pulse is at H level.
[0041] In this embodiment, "the data values of the second most significant bit are different" is set as the first threshold. Therefore, if the data values of the two most significant bits of each line data string LD are different, the CS calculation circuit 36 determines that the difference in data values is equal to or greater than the first threshold, and if the data values of the two most significant bits are the same, the difference in data values is less than the first threshold even if the data values of the third most significant bit and subsequent bits are different. That is, the CS calculation circuit 36 in this embodiment compares the data values of the two most significant bits of the line data string LD of the (N-1)th line and the line data string LD of the (N)th line, and if they are different, determines that the difference in data values is equal to or greater than the first threshold.
[0042] In the example shown in Figure 4, the most significant two bits of the line data string LD for the (N-1)th line are "00", and the most significant two bits of the line data string LD for the (N)th line are "10". Since the data values of the most significant two bits are different, it is determined that the difference in the data values is greater than or equal to the first threshold value.
[0043] Referring again to FIG. 2, the CS period adjustment circuit 37 receives line data strings LD that differ by one line from the first latch 31 and the second latch 32, and by comparing these, determines whether or not to adjust the CS (charge share) period when performing charge sharing.
[0044] The CS period adjustment circuit 37 compares the difference between the data value of the line data string LD for the (N-1)th line and the data value of the line data string LD for the (N)th line with a second threshold, and if the difference is equal to or greater than the second threshold, determines to adjust the CS period. The CS period adjustment circuit 37 adjusts the CS period by changing the pulse width of the clock pulse of the clock signal CLK1 that determines the timing of the source output of the source driver 14 (i.e., the length of the period during which the clock signal CLK1 is at H level).
[0045] The CS period adjustment circuit 37 keeps the pulse width of the clock pulse of the clock signal CLK1 unchanged when the difference in the data values is less than the second threshold, and widens the pulse width of the clock pulse of the clock signal CLK1 when the difference in the data values is equal to or greater than the second threshold.
[0046] In this embodiment, the second threshold value is set to "the data values of the most significant bits being different." Therefore, when the data values of the most significant bits of each line data string LD are different, the CS period adjustment circuit 37 determines that the difference in data values is equal to or greater than the second threshold value, and when the data values of the most significant bits are the same, the difference in data values is less than the second threshold value even if the data values of the second most significant bit and subsequent bits are different.
[0047] As shown in the example of FIG. 4, when the most significant two bits of the line data string LD of the (N-1)th line are “00” and the most significant two bits of the line data string LD of the (N)th line are “10”, the data values of the most significant bits are different, and it is determined that the difference in the data values is greater than or equal to the second threshold value.
[0048] FIG. 5 is a diagram showing a comparison of the pulse width of the clock signal CLK1 when the CS period is adjusted (turned on) and when the CS period is not adjusted (turned off).
[0049] When the CS period adjustment is OFF, the pulse width of the clock pulse of the clock signal CLK1 is the normal pulse width W1. When the CS period adjustment is ON, the pulse width of the clock pulse of the clock signal CLK1 is W2, which is larger than W1.
[0050] 2 again, the switching control unit 38 controls the switching of the switch 39 based on the determination results of the CS calculation circuit 36 and the CS period adjustment circuit 37. Specifically, when the CS calculation circuit 36 determines that the difference in data values between lines is equal to or greater than the first threshold, the switching control unit 38 switches the switch 39 so that it outputs the charge share voltage supplied from the CS voltage generation circuit 22 (i.e., shorts the output to the CS voltage) instead of the normal source output supplied through the DA conversion unit 34 and the operational amplifier 35 while the clock pulse of the clock signal CLK1 is at H level (i.e., for a predetermined period from the start of the output period of the source output). Furthermore, when the clock pulse of the clock signal CLK1 changes to L level, the switching control unit 38 switches the switch 39 so that it outputs the normal source output, i.e., the pixel drive voltage signal D generated based on the data values of the line data string LD.
[0051] 6 is a diagram showing the voltage waveforms of the output signals (pixel drive voltage signals Dv1 to Dvm) of the source driver 14 of this embodiment. The upper part shows the signal waveform of the clock signal CLK1. The lower part shows the output signals of the source driver 14, with the dashed line showing the voltage waveform of the output signal when charge sharing is not performed and the solid line showing the voltage waveform of the output signal when charge sharing of this embodiment is performed. Adjustment of the CS period will be described later; here, we will explain the case where the difference in data value of the line data string LD between lines is equal to or greater than the first threshold value and less than the second threshold value, and the CS period is not adjusted.
[0052] The period from the rising edge of a clock pulse of the clock signal CLK1 to the rising edge of the next clock pulse is the output period of the output signal corresponding to one line of the line data string LD. For example, as shown in Figure 6, if there is a large difference in the data values of the line data string LD between the (N-1)th line and the Nth line, and between the Nth line and the (N+1)th line, the voltage difference of the output signal output from the source driver 14 must also change significantly accordingly. If charge sharing of the output signal is not performed, it will take time for the signal level (voltage value) of the output signal to reach a target value, as shown by the voltage waveform of the dashed line in the figure.
[0053] In contrast, in the source driver 14 of this embodiment, when the difference in data value between lines is large, the source output is switched so that the charge share voltage is output as the output signal for a predetermined period from the start of the output period of the output signal for each line, that is, in this embodiment, for the period during which the clock pulse of the clock signal CLK1 is at H level. This allows the voltage to be changed suddenly at the timing of data switching for each line, as shown by the voltage waveform of the solid line, thereby shortening the time it takes for the output signal to reach the target value.
[0054] Furthermore, the source driver 14 of this embodiment has an internal CS voltage generation circuit 22, and generates the charge share voltage within the source driver 14. This eliminates the need for a dedicated external terminal, unlike when the charge share voltage is supplied from outside the source driver 14, and therefore makes it possible to suppress increases in system costs and power consumption.
[0055] Although Figure 6 shows an example in which there are two charge sharing voltages (CS voltage 1 and CS voltage 2), by increasing the number of charge sharing voltages, it is possible to perform more detailed voltage adjustments and obtain optimal source output.
[0056] 7 shows an example in which the number of charge sharing voltages is four (CS voltage 1>CS voltage 3>CS voltage 4>CS voltage 2). For example, the switching control unit 38 controls the switch 39 to output CS voltage 4 as the charge sharing voltage when the difference in data values is relatively small, and CS voltage 1 when the difference in data values is large. This allows the signal level of the output signal to be changed significantly depending on the difference in data values, thereby enabling the display panel 11 to be driven at high speed more smoothly.
[0057] Furthermore, when the CS period adjustment circuit 37 determines that the difference in data value between lines is equal to or greater than the second threshold, the switching control unit 38 controls the switching of the switch 39 so as to output the CS voltage while adjusting (changing) the CS period.
[0058] FIG. 8 is a diagram showing the voltage waveform of the output signal of the source driver 14 when adjusting the CS period.
[0059] For example, although charge sharing is performed because there is a difference in data value between the (N-1)th line and the Nth line, the difference is relatively small (i.e., equal to or greater than the first threshold and less than the second threshold), so the CS period is not adjusted. In contrast, there is a difference in data value between the Nth line and the (N+1)th line, and this difference is large (i.e., equal to or greater than the second threshold), so the CS period is adjusted. That is, a process is performed to extend the period during which the clock pulse of the clock signal CLK1 is at H level during the output period of the output signal corresponding to the (N+1)th line.
[0060] In this way, by adjusting the CS period according to the difference in data values between lines and lengthening the period during which the charge share voltage is output, the time it takes for the output signal to reach the target value can be shortened, and the source driver 14 can drive the display panel 11 at higher speed.
[0061] It should be noted that the present invention is not limited to the above-described embodiments. For example, in the above-described embodiments, the data values of the most significant two bits of the line data string LD are compared to determine whether the difference in data values is equal to or greater than the first threshold value, but the bit digits to be compared are not limited to this. For example, the data values of the most significant three or four bits may be compared, or the data values of other bit digits may be compared.
[0062] Similarly, in the above embodiment, the adjustment of the CS period was described as an example in which the data value of the most significant bit is determined to be greater than or equal to the second threshold value when it is different, but the bit digits to be compared are not limited to this.
[0063] Furthermore, the adjustment width of the CS period is not limited to that shown in the above embodiment, and may be configured so that the adjustment width can be changed appropriately depending on the difference in data value. [Explanation of symbols]
[0064] 100 display device 11 Display panel 12 Display Controller 13 Gate Driver 14 Source Driver 21 IF / Data processing section 22 CS voltage generation circuit 23-1~23-m Output generation block 31 First latch 32 Second latch 33 Third Latch 34 DA conversion section 35 operational amplifiers 36 CS calculation circuit 37 CS period adjustment circuit 38 Switching control section 39 SW 41,42 Input side amplifier 43 Ladder Resistor
Claims
1. a source driver connected to a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of intersections of the plurality of source lines and the plurality of gate lines, the source driver receiving a video data signal consisting of a plurality of data strings, generating a plurality of drive voltages based on the video data signal, and applying the generated drive voltages to each of the plurality of pixel units via each of the plurality of source lines; a charge share voltage generating circuit that generates a plurality of charge share voltages based on a reference voltage; a latch unit that sequentially captures the plurality of data sequences corresponding to each of the plurality of gate lines; a charge sharing calculation circuit that compares a data sequence corresponding to an N-th line (N is an integer equal to or greater than 2) of the plurality of gate lines with a data sequence corresponding to an (N-1)-th line, and performs a determination calculation regarding charge sharing of an output voltage for a source output corresponding to the data sequence of the N-th line; a switching unit that selectively switches, based on a calculation result of the charge sharing calculation circuit, whether to output one of the plurality of charge sharing voltages for a predetermined period from the start of an output period of a source output corresponding to the data sequence of the Nth line, or to continuously output the drive voltage generated based on the data value of the data sequence of the Nth line from the start of the output period; A source driver comprising:
2. the charge sharing calculation circuit compares a difference between the data values of the data sequence corresponding to the Nth line and the data sequence corresponding to the (N-1)th line with a first threshold; the switching unit outputs the one charge share voltage for a predetermined period from the start of an output period of the source output corresponding to the data sequence of the Nth line when the difference in data values is equal to or greater than the first threshold, and switches the source output so as to continuously output the drive voltage generated based on the data values of the data sequence of the Nth line from the start of the output period when the difference in data values is less than the first threshold.
2. The source driver according to claim 1.
3. the data string is composed of data of a predetermined number of bits, 3. The source driver according to claim 2, wherein the charge sharing calculation circuit compares the data values of a specific bit digit in each of the data string corresponding to the Nth line and the data string corresponding to the (N-1)th line, and if the data values of the specific bit digit are different, determines that the difference in the data values is equal to or greater than the first threshold value.
4. the latch unit is composed of multiple stages of cascade-connected latches, 2. The source driver according to claim 1, wherein the charge sharing operation circuit performs the determination operation based on a comparison result between a data string output from one latch constituting the plurality of stages of latches and a data string output from another latch located in the next stage of the one latch.
5. 3. The source driver according to claim 2, further comprising a charge sharing period adjustment circuit that compares the difference between the data values of the data sequence corresponding to the Nth line and the data sequence corresponding to the (N-1)th line with a second threshold value, and changes the length of the predetermined period during which the charge sharing voltage is output based on the comparison result.
6. the charge share voltage generation circuit includes a resistor ladder circuit, 2. The source driver according to claim 1, wherein the plurality of charge share voltages are generated by dividing the plurality of reference voltages by the resistor ladder circuit.
7. a drive voltage generating unit that generates the drive voltage by selecting a gray scale voltage corresponding to a luminance level indicated by the video data signal from among a plurality of gray scale voltages; 7. The source driver according to claim 6, wherein the charge share voltage generation circuit generates the plurality of charge share voltages by using a gradation reference voltage used by the drive voltage generation unit to generate the plurality of gradation voltages as the reference voltage.
8. a display panel including a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of the intersections of the plurality of source lines and the plurality of gate lines; a gate driver that supplies gate signals to the plurality of gate lines; a source driver that receives a video data signal consisting of a plurality of data strings, generates a plurality of driving voltages based on the video data signal, and applies the driving voltages to each of the plurality of pixel units via each of the plurality of source lines; Including, The source driver a charge share voltage generating circuit that generates a plurality of charge share voltages based on a reference voltage; a latch unit that sequentially captures the plurality of data sequences corresponding to each of the plurality of gate lines; a charge sharing calculation circuit that compares a data sequence corresponding to an N-th line (N is an integer equal to or greater than 2) of the plurality of gate lines with a data sequence corresponding to an (N-1)-th line, and performs a determination calculation regarding charge sharing of an output voltage for a source output corresponding to the data sequence of the N-th line; a switching unit that selectively switches, based on a calculation result of the charge sharing calculation circuit, whether to output one of the plurality of charge sharing voltages for a predetermined period from the start of an output period of a source output corresponding to the data sequence of the Nth line, or to continuously output the drive voltage generated based on the data value of the data sequence of the Nth line from the start of the output period; A display device comprising:
Citation Information
Patent Citations
Driving device and its driving method
JP2007199203A